From 264a3462e0b83b5b0616d52915b58f0d4c8af767 Mon Sep 17 00:00:00 2001 From: GClarkson Date: Sat, 12 Apr 2025 13:30:57 +0100 Subject: [PATCH] Initial commit of firmware --- .gitignore | 88 + CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h | 411 + CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h | 888 + CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h | 1503 + .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1928 ++ CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h | 283 + CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h | 2211 ++ CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h | 1002 + CMSIS_5/CMSIS/Core/Include/cmsis_version.h | 39 + CMSIS_5/CMSIS/Core/Include/core_armv81mml.h | 4228 +++ CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h | 2222 ++ CMSIS_5/CMSIS/Core/Include/core_armv8mml.h | 3209 ++ CMSIS_5/CMSIS/Core/Include/core_cm0.h | 952 + CMSIS_5/CMSIS/Core/Include/core_cm0plus.h | 1087 + CMSIS_5/CMSIS/Core/Include/core_cm1.h | 979 + CMSIS_5/CMSIS/Core/Include/core_cm23.h | 2297 ++ CMSIS_5/CMSIS/Core/Include/core_cm3.h | 1943 ++ CMSIS_5/CMSIS/Core/Include/core_cm33.h | 3277 ++ CMSIS_5/CMSIS/Core/Include/core_cm35p.h | 3277 ++ CMSIS_5/CMSIS/Core/Include/core_cm4.h | 2129 ++ CMSIS_5/CMSIS/Core/Include/core_cm55.h | 4817 +++ CMSIS_5/CMSIS/Core/Include/core_cm7.h | 2366 ++ CMSIS_5/CMSIS/Core/Include/core_cm85.h | 4672 +++ CMSIS_5/CMSIS/Core/Include/core_sc000.h | 1030 + CMSIS_5/CMSIS/Core/Include/core_sc300.h | 1917 + CMSIS_5/CMSIS/Core/Include/core_starmc1.h | 3592 ++ CMSIS_5/CMSIS/Core/Include/mpu_armv7.h | 275 + CMSIS_5/CMSIS/Core/Include/mpu_armv8.h | 352 + CMSIS_5/CMSIS/Core/Include/pac_armv81.h | 206 + CMSIS_5/CMSIS/Core/Include/pmu_armv8.h | 337 + CMSIS_5/CMSIS/Core/Include/tz_context.h | 70 + EFR32MG24/Device/Include/efr32mg24_acmp.h | 654 + EFR32MG24/Device/Include/efr32mg24_aes.h | 453 + EFR32MG24/Device/Include/efr32mg24_agc.h | 2976 ++ EFR32MG24/Device/Include/efr32mg24_amuxcp.h | 261 + EFR32MG24/Device/Include/efr32mg24_bufc.h | 746 + EFR32MG24/Device/Include/efr32mg24_buram.h | 80 + EFR32MG24/Device/Include/efr32mg24_burtc.h | 332 + EFR32MG24/Device/Include/efr32mg24_cmu.h | 1121 + EFR32MG24/Device/Include/efr32mg24_dcdc.h | 455 + EFR32MG24/Device/Include/efr32mg24_devinfo.h | 976 + .../Device/Include/efr32mg24_dma_descriptor.h | 55 + EFR32MG24/Device/Include/efr32mg24_dpll.h | 232 + EFR32MG24/Device/Include/efr32mg24_eca.h | 820 + EFR32MG24/Device/Include/efr32mg24_ecaifadc.h | 134 + EFR32MG24/Device/Include/efr32mg24_emu.h | 803 + EFR32MG24/Device/Include/efr32mg24_eusart.h | 1319 + EFR32MG24/Device/Include/efr32mg24_frc.h | 2608 ++ EFR32MG24/Device/Include/efr32mg24_fsrco.h | 75 + EFR32MG24/Device/Include/efr32mg24_gpcrc.h | 246 + EFR32MG24/Device/Include/efr32mg24_gpio.h | 2632 ++ .../Device/Include/efr32mg24_gpio_port.h | 457 + EFR32MG24/Device/Include/efr32mg24_hfrco.h | 226 + EFR32MG24/Device/Include/efr32mg24_hfxo.h | 801 + EFR32MG24/Device/Include/efr32mg24_i2c.h | 744 + EFR32MG24/Device/Include/efr32mg24_iadc.h | 1072 + EFR32MG24/Device/Include/efr32mg24_icache.h | 248 + EFR32MG24/Device/Include/efr32mg24_keyscan.h | 386 + EFR32MG24/Device/Include/efr32mg24_ldma.h | 685 + EFR32MG24/Device/Include/efr32mg24_ldmaxbar.h | 96 + .../Include/efr32mg24_ldmaxbar_defines.h | 152 + EFR32MG24/Device/Include/efr32mg24_letimer.h | 534 + EFR32MG24/Device/Include/efr32mg24_lfrco.h | 304 + EFR32MG24/Device/Include/efr32mg24_lfxo.h | 281 + EFR32MG24/Device/Include/efr32mg24_mailbox.h | 140 + EFR32MG24/Device/Include/efr32mg24_modem.h | 6657 ++++ EFR32MG24/Device/Include/efr32mg24_mpahbram.h | 443 + EFR32MG24/Device/Include/efr32mg24_msc.h | 546 + EFR32MG24/Device/Include/efr32mg24_mvp.h | 1386 + EFR32MG24/Device/Include/efr32mg24_pcnt.h | 482 + EFR32MG24/Device/Include/efr32mg24_protimer.h | 1838 + EFR32MG24/Device/Include/efr32mg24_prs.h | 1621 + .../Device/Include/efr32mg24_prs_signals.h | 971 + EFR32MG24/Device/Include/efr32mg24_rac.h | 5773 ++++ EFR32MG24/Device/Include/efr32mg24_rfcrc.h | 232 + .../Device/Include/efr32mg24_scratchpad.h | 87 + .../Device/Include/efr32mg24_semailbox.h | 383 + EFR32MG24/Device/Include/efr32mg24_smu.h | 1483 + EFR32MG24/Device/Include/efr32mg24_synth.h | 1124 + EFR32MG24/Device/Include/efr32mg24_syscfg.h | 772 + EFR32MG24/Device/Include/efr32mg24_sysrtc.h | 421 + EFR32MG24/Device/Include/efr32mg24_timer.h | 1020 + EFR32MG24/Device/Include/efr32mg24_ulfrco.h | 147 + EFR32MG24/Device/Include/efr32mg24_usart.h | 1431 + EFR32MG24/Device/Include/efr32mg24_vdac.h | 757 + EFR32MG24/Device/Include/efr32mg24_wdog.h | 375 + .../Device/Include/efr32mg24a010f1024im40.h | 1519 + .../Device/Include/efr32mg24a010f1024im48.h | 1521 + .../Device/Include/efr32mg24a010f1536gm40.h | 1519 + .../Device/Include/efr32mg24a010f1536gm48.h | 1521 + .../Device/Include/efr32mg24a010f1536im40.h | 1519 + .../Device/Include/efr32mg24a010f1536im48.h | 1521 + .../Device/Include/efr32mg24a020f1024im40.h | 1517 + .../Device/Include/efr32mg24a020f1024im48.h | 1519 + .../Device/Include/efr32mg24a020f1536gm40.h | 1517 + .../Device/Include/efr32mg24a020f1536gm48.h | 1519 + .../Device/Include/efr32mg24a020f1536im40.h | 1517 + .../Device/Include/efr32mg24a020f1536im48.h | 1519 + .../Device/Include/efr32mg24a021f1024im40.h | 1514 + .../Device/Include/efr32mg24a110f1024im48.h | 1517 + .../Device/Include/efr32mg24a110f1536gm48.h | 1517 + .../Device/Include/efr32mg24a111f1536gm48.h | 1516 + .../Device/Include/efr32mg24a120f1536gm48.h | 1515 + .../Device/Include/efr32mg24a121f1536gm48.h | 1514 + .../Device/Include/efr32mg24a410f1536im40.h | 1519 + .../Device/Include/efr32mg24a410f1536im48.h | 1521 + .../Device/Include/efr32mg24a420f1536im40.h | 1517 + .../Device/Include/efr32mg24a420f1536im48.h | 1519 + .../Device/Include/efr32mg24a610f1536im40.h | 1519 + .../Device/Include/efr32mg24a620f1536im40.h | 1517 + .../Device/Include/efr32mg24b010f1024im48.h | 1522 + .../Device/Include/efr32mg24b010f1536im40.h | 1520 + .../Device/Include/efr32mg24b010f1536im48.h | 1522 + .../Device/Include/efr32mg24b020f1024im48.h | 1520 + .../Device/Include/efr32mg24b020f1536im40.h | 1518 + .../Device/Include/efr32mg24b020f1536im48.h | 1520 + .../Device/Include/efr32mg24b110f1536gm48.h | 1518 + .../Device/Include/efr32mg24b110f1536im48.h | 1518 + .../Device/Include/efr32mg24b120f1536im48.h | 1516 + .../Device/Include/efr32mg24b210f1536im48.h | 1536 + .../Device/Include/efr32mg24b220f1536im48.h | 1534 + .../Device/Include/efr32mg24b310f1536im48.h | 1533 + .../Device/Include/efr32mg24b610f1536im40.h | 1520 + EFR32MG24/Device/Include/em_device.h | 166 + EFR32MG24/Device/Include/system_efr32mg24.h | 245 + EFR32MG24/Device/Source/system_efr32mg24.c | 656 + EFR32MG24/Scripts/EFR32MG24_Target.js | 44 + EFR32MG24/Source/EFR32MG24_Startup.s | 288 + EFR32MG24/Source/efr32mg24_Vectors.s | 301 + EFR32MG24B310F1536IM48_MemoryMap.xml | 5 + EFR32MG24B310F1536IM48_Registers.xml | 28828 ++++++++++++++++ EFR32MG24_Flash.icf | 138 + Firmware_Debug.jlink | 48 + Libs/CMSIS/Core/Include/cmsis_compiler.h | 283 + Libs/CMSIS/Core/Include/cmsis_gcc.h | 2211 ++ Libs/CMSIS/Core/Include/cmsis_version.h | 39 + Libs/CMSIS/Core/Include/core_cm33.h | 3265 ++ Libs/CMSIS/Core/Include/mpu_armv8.h | 352 + Libs/CMSIS/Core/Include/tz_context.h | 70 + Libs/CMSIS/RTOS2/Include/cmsis_os2.h | 759 + Libs/CMSIS/RTOS2/Include/os_tick.h | 80 + Libs/CMSIS/RTOS2/Source/os_systick.c | 133 + Libs/FreeRTOS/cmsis/Include/freertos_mpool.h | 63 + Libs/FreeRTOS/cmsis/Include/freertos_os2.h | 336 + Libs/FreeRTOS/cmsis/Source/cmsis_os2.c | 2459 ++ Libs/FreeRTOS/kernel/croutine.c | 374 + Libs/FreeRTOS/kernel/event_groups.c | 784 + Libs/FreeRTOS/kernel/include/FreeRTOS.h | 1358 + Libs/FreeRTOS/kernel/include/StackMacros.h | 45 + Libs/FreeRTOS/kernel/include/atomic.h | 432 + Libs/FreeRTOS/kernel/include/croutine.h | 764 + .../kernel/include/deprecated_definitions.h | 292 + Libs/FreeRTOS/kernel/include/event_groups.h | 788 + Libs/FreeRTOS/kernel/include/list.h | 430 + Libs/FreeRTOS/kernel/include/message_buffer.h | 834 + Libs/FreeRTOS/kernel/include/mpu_prototypes.h | 270 + Libs/FreeRTOS/kernel/include/mpu_wrappers.h | 200 + Libs/FreeRTOS/kernel/include/portable.h | 229 + Libs/FreeRTOS/kernel/include/projdefs.h | 133 + Libs/FreeRTOS/kernel/include/queue.h | 1729 + Libs/FreeRTOS/kernel/include/semphr.h | 1186 + Libs/FreeRTOS/kernel/include/stack_macros.h | 140 + Libs/FreeRTOS/kernel/include/stream_buffer.h | 880 + Libs/FreeRTOS/kernel/include/task.h | 3066 ++ Libs/FreeRTOS/kernel/include/timers.h | 1364 + Libs/FreeRTOS/kernel/list.c | 223 + .../GCC/ARM_CM33_NTZ/non_secure/port.c | 1205 + .../GCC/ARM_CM33_NTZ/non_secure/portasm.c | 333 + .../GCC/ARM_CM33_NTZ/non_secure/portasm.h | 126 + .../GCC/ARM_CM33_NTZ/non_secure/portmacro.h | 325 + .../FreeRTOS/kernel/portable/MemMang/heap_3.c | 107 + .../portable/SiliconLabs/tick_power_manager.c | 232 + Libs/FreeRTOS/kernel/queue.c | 3029 ++ Libs/FreeRTOS/kernel/stream_buffer.c | 1327 + Libs/FreeRTOS/kernel/tasks.c | 5408 +++ Libs/FreeRTOS/kernel/timers.c | 1157 + Libs/platform/common/inc/sl_assert.h | 99 + Libs/platform/common/inc/sl_atomic.h | 80 + Libs/platform/common/inc/sl_bit.h | 189 + .../platform/common/inc/sl_cmsis_os2_common.h | 200 + .../common/inc/sl_code_classification.h | 75 + Libs/platform/common/inc/sl_common.h | 420 + Libs/platform/common/inc/sl_compiler.h | 210 + Libs/platform/common/inc/sl_core.h | 499 + Libs/platform/common/inc/sl_enum.h | 66 + Libs/platform/common/inc/sl_slist.h | 173 + Libs/platform/common/inc/sl_status.h | 526 + .../inc/sli_cmsis_os2_ext_task_register.h | 108 + .../common/inc/sli_code_classification.h | 131 + Libs/platform/common/src/sl_assert.c | 76 + .../platform/common/src/sl_cmsis_os2_common.c | 61 + Libs/platform/common/src/sl_core_cortexm.c | 395 + Libs/platform/common/src/sl_slist.c | 190 + Libs/platform/common/src/sl_syscalls.c | 115 + .../src/sli_cmsis_os2_ext_task_register.c | 143 + .../common/toolchain/inc/sl_gcc_preinclude.h | 40 + .../platform/common/toolchain/inc/sl_memory.h | 39 + .../common/toolchain/inc/sl_memory_region.h | 39 + Libs/platform/driver/button/inc/sl_button.h | 191 + .../driver/button/inc/sl_simple_button.h | 225 + Libs/platform/driver/button/src/sl_button.c | 76 + .../driver/button/src/sl_simple_button.c | 205 + Libs/platform/driver/gpio/inc/sl_gpio.h | 521 + Libs/platform/driver/gpio/src/sl_gpio.c | 824 + Libs/platform/driver/leddrv/inc/sl_led.h | 183 + .../driver/leddrv/inc/sl_simple_led.h | 226 + Libs/platform/driver/leddrv/src/sl_led.c | 56 + .../driver/leddrv/src/sl_simple_led.c | 104 + Libs/platform/emlib/inc/em_acmp.h | 1168 + Libs/platform/emlib/inc/em_assert.h | 36 + Libs/platform/emlib/inc/em_burtc.h | 473 + Libs/platform/emlib/inc/em_bus.h | 350 + Libs/platform/emlib/inc/em_chip.h | 483 + Libs/platform/emlib/inc/em_cmu.h | 3655 ++ Libs/platform/emlib/inc/em_cmu_compat.h | 184 + Libs/platform/emlib/inc/em_common.h | 36 + Libs/platform/emlib/inc/em_core.h | 174 + Libs/platform/emlib/inc/em_core_generic.h | 36 + Libs/platform/emlib/inc/em_dbg.h | 130 + Libs/platform/emlib/inc/em_emu.h | 1831 + Libs/platform/emlib/inc/em_eusart.h | 1223 + Libs/platform/emlib/inc/em_eusart_compat.h | 218 + Libs/platform/emlib/inc/em_gpcrc.h | 346 + Libs/platform/emlib/inc/em_gpio.h | 1380 + Libs/platform/emlib/inc/em_i2c.h | 525 + Libs/platform/emlib/inc/em_iadc.h | 1407 + Libs/platform/emlib/inc/em_ldma.h | 2824 ++ Libs/platform/emlib/inc/em_letimer.h | 334 + Libs/platform/emlib/inc/em_msc.h | 889 + Libs/platform/emlib/inc/em_msc_compat.h | 81 + Libs/platform/emlib/inc/em_opamp.h | 1459 + Libs/platform/emlib/inc/em_pcnt.h | 905 + Libs/platform/emlib/inc/em_prs.h | 1170 + Libs/platform/emlib/inc/em_ramfunc.h | 169 + Libs/platform/emlib/inc/em_rmu.h | 178 + Libs/platform/emlib/inc/em_smu.h | 1762 + Libs/platform/emlib/inc/em_syscfg.h | 174 + Libs/platform/emlib/inc/em_system.h | 365 + Libs/platform/emlib/inc/em_system_generic.h | 91 + Libs/platform/emlib/inc/em_timer.h | 1238 + Libs/platform/emlib/inc/em_usart.h | 1093 + Libs/platform/emlib/inc/em_vdac.h | 773 + Libs/platform/emlib/inc/em_version.h | 68 + Libs/platform/emlib/inc/em_wdog.h | 455 + Libs/platform/emlib/inc/sli_em_cmu.h | 1902 + Libs/platform/emlib/src/em_acmp.c | 709 + Libs/platform/emlib/src/em_burtc.c | 433 + Libs/platform/emlib/src/em_cmu.c | 11864 +++++++ Libs/platform/emlib/src/em_core.c | 518 + Libs/platform/emlib/src/em_dbg.c | 132 + Libs/platform/emlib/src/em_emu.c | 4319 +++ Libs/platform/emlib/src/em_eusart.c | 1398 + Libs/platform/emlib/src/em_gpcrc.c | 138 + Libs/platform/emlib/src/em_gpio.c | 452 + Libs/platform/emlib/src/em_i2c.c | 940 + Libs/platform/emlib/src/em_iadc.c | 1178 + Libs/platform/emlib/src/em_ldma.c | 461 + Libs/platform/emlib/src/em_letimer.c | 685 + Libs/platform/emlib/src/em_msc.c | 2081 ++ Libs/platform/emlib/src/em_opamp.c | 700 + Libs/platform/emlib/src/em_pcnt.c | 1067 + Libs/platform/emlib/src/em_prs.c | 661 + Libs/platform/emlib/src/em_rmu.c | 402 + Libs/platform/emlib/src/em_system.c | 433 + Libs/platform/emlib/src/em_timer.c | 520 + Libs/platform/emlib/src/em_usart.c | 1444 + Libs/platform/emlib/src/em_vdac.c | 636 + Libs/platform/emlib/src/em_wdog.c | 355 + .../peripheral/inc/peripheral_sysrtc.h | 32 + .../peripheral/inc/peripheral_sysrtc_compat.h | 33 + Libs/platform/peripheral/inc/sl_hal_bus.h | 274 + Libs/platform/peripheral/inc/sl_hal_gpio.h | 915 + Libs/platform/peripheral/inc/sl_hal_syscfg.h | 89 + Libs/platform/peripheral/inc/sl_hal_sysrtc.h | 445 + .../peripheral/inc/sl_hal_sysrtc_compat.h | 89 + Libs/platform/peripheral/inc/sl_hal_system.h | 146 + .../peripheral/inc/sl_hal_system_generic.h | 344 + Libs/platform/peripheral/src/sl_hal_gpio.c | 432 + Libs/platform/peripheral/src/sl_hal_sysrtc.c | 1012 + Libs/platform/peripheral/src/sl_hal_system.c | 662 + .../clock_manager/inc/sl_clock_manager.h | 661 + .../clock_manager/inc/sl_clock_manager_init.h | 62 + .../clock_manager/inc/sli_clock_manager.h | 64 + .../clock_manager/src/sl_clock_manager.c | 313 + .../src/sl_clock_manager_hal_s2.c | 1040 + .../clock_manager/src/sl_clock_manager_init.c | 40 + .../src/sl_clock_manager_init_hal_s2.c | 886 + .../clock_manager/src/sli_clock_manager_hal.h | 198 + .../src/sli_clock_manager_init_hal.h | 111 + .../device_init/inc/sl_device_init_dcdc.h | 88 + .../device_init/src/sl_device_init_dcdc_s2.c | 60 + .../clocks/sl_device_clock_efr32xg24.c | 339 + .../sl_device_peripheral_hal_efr32xg24.c | 383 + .../device_manager/inc/sl_device_clock.h | 806 + .../device_manager/inc/sl_device_gpio.h | 670 + .../device_manager/inc/sl_device_peripheral.h | 2821 ++ .../inc/sl_device_peripheral_types.h | 65 + .../device_manager/src/sl_device_clock.c | 351 + .../device_manager/src/sl_device_gpio.c | 403 + .../device_manager/src/sl_device_peripheral.c | 769 + .../hfxo_manager/inc/sl_hfxo_manager.h | 144 + .../hfxo_manager/inc/sli_hfxo_manager.h | 102 + .../hfxo_manager/src/sl_hfxo_manager.c | 235 + .../hfxo_manager/src/sl_hfxo_manager_hal_s2.c | 410 + .../src/sli_hfxo_manager_internal.h | 50 + .../inc/arm/cmsis_nvic_virtual.h | 59 + .../inc/sl_interrupt_manager.h | 404 + .../src/sl_interrupt_manager_cortexm.c | 601 + .../src/sli_interrupt_manager.h | 106 + .../service/iostream/inc/sl_iostream.h | 286 + .../service/iostream/inc/sl_iostream_rtt.h | 112 + .../service/iostream/src/sl_iostream.c | 303 + .../service/iostream/src/sl_iostream_rtt.c | 144 + .../memory_manager/inc/sl_memory_manager.h | 971 + .../inc/sl_memory_manager_region.h | 77 + .../profiler/inc/sli_memory_profiler.h | 631 + .../profiler/src/sli_memory_profiler_stubs.c | 126 + .../memory_manager/src/sl_memory_manager.c | 1200 + .../src/sl_memory_manager_cpp.cpp | 212 + .../sl_memory_manager_dynamic_reservation.c | 377 + .../src/sl_memory_manager_pool.c | 242 + .../src/sl_memory_manager_pool_common.c | 112 + .../src/sl_memory_manager_region.c | 144 + .../src/sl_memory_manager_retarget.c | 378 + .../memory_manager/src/sli_memory_manager.h | 340 + .../src/sli_memory_manager_common.c | 712 + Libs/platform/service/mpu/inc/sl_mpu.h | 85 + Libs/platform/service/mpu/src/sl_mpu.c | 493 + .../power_manager/inc/sl_power_manager.h | 591 + .../inc/sl_power_manager_debug.h | 60 + .../power_manager/inc/sli_power_manager.h | 172 + .../src/common/sl_power_manager_common.c | 213 + .../src/common/sl_power_manager_em4.c | 330 + .../src/sleep_loop/sl_power_manager.c | 1097 + .../src/sleep_loop/sl_power_manager_debug.c | 165 + .../src/sleep_loop/sl_power_manager_hal_s2.c | 706 + .../sleep_loop/sli_power_manager_private.h | 164 + .../service/sleeptimer/inc/sl_sleeptimer.h | 1184 + .../service/sleeptimer/inc/sli_sleeptimer.h | 143 + .../service/sleeptimer/src/sl_sleeptimer.c | 1967 ++ .../sleeptimer/src/sl_sleeptimer_hal_burtc.c | 381 + .../sleeptimer/src/sl_sleeptimer_hal_sysrtc.c | 443 + .../sleeptimer/src/sl_sleeptimer_hal_timer.c | 393 + .../sleeptimer/src/sli_sleeptimer_hal.h | 189 + .../service/system/inc/sl_system_init.h | 153 + .../service/system/inc/sl_system_kernel.h | 53 + .../service/system/src/sl_system_init.c | 39 + .../service/system/src/sl_system_kernel.c | 35 + Libs/platform/service/udelay/inc/sl_udelay.h | 78 + Libs/platform/service/udelay/src/sl_udelay.c | 69 + .../service/udelay/src/sl_udelay_armv6m_gcc.S | 60 + Output/Debug/Obj/Firmware/Firmware_files.ind | 103 + .../Debug/Obj/Firmware/em_emu-df97bff7.o.tmp | 0 .../Obj/Firmware/sl_syscalls-637c085d.o.tmp | 0 .../Debug/Obj/Firmware/timers-d0bfcf77.o.tmp | 0 SEGGER_THUMB_Startup.s | 288 + autogen/RTE_Components.h | 34 + autogen/sl_component_catalog.h | 94 + autogen/sl_event_handler.c | 104 + autogen/sl_event_handler.h | 12 + config/FreeRTOSConfig.h | 336 + config/emlib_core_debug_config.h | 45 + config/sl_clock_manager_oscillator_config.h | 376 + config/sl_clock_manager_tree_config.h | 308 + config/sl_core_config.h | 44 + config/sl_device_init_dcdc_config.h | 58 + config/sl_hfxo_manager_config.h | 56 + config/sl_interrupt_manager_s2_config.h | 47 + config/sl_memory_manager_config.h | 49 + config/sl_memory_manager_region_config.h | 49 + config/sl_power_manager_config.h | 78 + config/sl_simple_button_config.h | 72 + config/sl_sleeptimer_config.h | 82 + main.c | 65 + 374 files changed, 332649 insertions(+) create mode 100644 .gitignore create mode 100644 CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h create mode 100644 CMSIS_5/CMSIS/Core/Include/cmsis_version.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_armv81mml.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_armv8mml.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm0.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm0plus.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm1.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm23.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm3.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm33.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm35p.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm4.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm55.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm7.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_cm85.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_sc000.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_sc300.h create mode 100644 CMSIS_5/CMSIS/Core/Include/core_starmc1.h create mode 100644 CMSIS_5/CMSIS/Core/Include/mpu_armv7.h create mode 100644 CMSIS_5/CMSIS/Core/Include/mpu_armv8.h create mode 100644 CMSIS_5/CMSIS/Core/Include/pac_armv81.h create mode 100644 CMSIS_5/CMSIS/Core/Include/pmu_armv8.h create mode 100644 CMSIS_5/CMSIS/Core/Include/tz_context.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_acmp.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_aes.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_agc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_amuxcp.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_bufc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_buram.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_burtc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_cmu.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_dcdc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_devinfo.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_dma_descriptor.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_dpll.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_eca.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_ecaifadc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_emu.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_eusart.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_frc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_fsrco.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_gpcrc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_gpio.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_gpio_port.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_hfrco.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_hfxo.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_i2c.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_iadc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_icache.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_keyscan.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_ldma.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_ldmaxbar.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_ldmaxbar_defines.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_letimer.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_lfrco.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_lfxo.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_mailbox.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_modem.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_mpahbram.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_msc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_mvp.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_pcnt.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_protimer.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_prs.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_prs_signals.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_rac.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_rfcrc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_scratchpad.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_semailbox.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_smu.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_synth.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_syscfg.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_sysrtc.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_timer.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_ulfrco.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_usart.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_vdac.h create mode 100644 EFR32MG24/Device/Include/efr32mg24_wdog.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1024im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1024im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1536gm40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a010f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1024im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1024im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1536gm40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a020f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a021f1024im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a110f1024im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a110f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a111f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a120f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a121f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a410f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a410f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a420f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a420f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a610f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24a620f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b010f1024im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b010f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b010f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b020f1024im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b020f1536im40.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b020f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b110f1536gm48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b110f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b120f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b210f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b220f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b310f1536im48.h create mode 100644 EFR32MG24/Device/Include/efr32mg24b610f1536im40.h create mode 100644 EFR32MG24/Device/Include/em_device.h create mode 100644 EFR32MG24/Device/Include/system_efr32mg24.h create mode 100644 EFR32MG24/Device/Source/system_efr32mg24.c create mode 100644 EFR32MG24/Scripts/EFR32MG24_Target.js create mode 100644 EFR32MG24/Source/EFR32MG24_Startup.s create mode 100644 EFR32MG24/Source/efr32mg24_Vectors.s create mode 100644 EFR32MG24B310F1536IM48_MemoryMap.xml create mode 100644 EFR32MG24B310F1536IM48_Registers.xml create mode 100644 EFR32MG24_Flash.icf create mode 100644 Firmware_Debug.jlink create mode 100644 Libs/CMSIS/Core/Include/cmsis_compiler.h create mode 100644 Libs/CMSIS/Core/Include/cmsis_gcc.h create mode 100644 Libs/CMSIS/Core/Include/cmsis_version.h create mode 100644 Libs/CMSIS/Core/Include/core_cm33.h create mode 100644 Libs/CMSIS/Core/Include/mpu_armv8.h create mode 100644 Libs/CMSIS/Core/Include/tz_context.h create mode 100644 Libs/CMSIS/RTOS2/Include/cmsis_os2.h create mode 100644 Libs/CMSIS/RTOS2/Include/os_tick.h create mode 100644 Libs/CMSIS/RTOS2/Source/os_systick.c create mode 100644 Libs/FreeRTOS/cmsis/Include/freertos_mpool.h create mode 100644 Libs/FreeRTOS/cmsis/Include/freertos_os2.h create mode 100644 Libs/FreeRTOS/cmsis/Source/cmsis_os2.c create mode 100644 Libs/FreeRTOS/kernel/croutine.c create mode 100644 Libs/FreeRTOS/kernel/event_groups.c create mode 100644 Libs/FreeRTOS/kernel/include/FreeRTOS.h create mode 100644 Libs/FreeRTOS/kernel/include/StackMacros.h create mode 100644 Libs/FreeRTOS/kernel/include/atomic.h create mode 100644 Libs/FreeRTOS/kernel/include/croutine.h create mode 100644 Libs/FreeRTOS/kernel/include/deprecated_definitions.h create mode 100644 Libs/FreeRTOS/kernel/include/event_groups.h create mode 100644 Libs/FreeRTOS/kernel/include/list.h create mode 100644 Libs/FreeRTOS/kernel/include/message_buffer.h create mode 100644 Libs/FreeRTOS/kernel/include/mpu_prototypes.h create mode 100644 Libs/FreeRTOS/kernel/include/mpu_wrappers.h create mode 100644 Libs/FreeRTOS/kernel/include/portable.h create mode 100644 Libs/FreeRTOS/kernel/include/projdefs.h create mode 100644 Libs/FreeRTOS/kernel/include/queue.h create mode 100644 Libs/FreeRTOS/kernel/include/semphr.h create mode 100644 Libs/FreeRTOS/kernel/include/stack_macros.h create mode 100644 Libs/FreeRTOS/kernel/include/stream_buffer.h create mode 100644 Libs/FreeRTOS/kernel/include/task.h create mode 100644 Libs/FreeRTOS/kernel/include/timers.h create mode 100644 Libs/FreeRTOS/kernel/list.c create mode 100644 Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c create mode 100644 Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c create mode 100644 Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h create mode 100644 Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h create mode 100644 Libs/FreeRTOS/kernel/portable/MemMang/heap_3.c create mode 100644 Libs/FreeRTOS/kernel/portable/SiliconLabs/tick_power_manager.c create mode 100644 Libs/FreeRTOS/kernel/queue.c create mode 100644 Libs/FreeRTOS/kernel/stream_buffer.c create mode 100644 Libs/FreeRTOS/kernel/tasks.c create mode 100644 Libs/FreeRTOS/kernel/timers.c create mode 100644 Libs/platform/common/inc/sl_assert.h create mode 100644 Libs/platform/common/inc/sl_atomic.h create mode 100644 Libs/platform/common/inc/sl_bit.h create mode 100644 Libs/platform/common/inc/sl_cmsis_os2_common.h create mode 100644 Libs/platform/common/inc/sl_code_classification.h create mode 100644 Libs/platform/common/inc/sl_common.h create mode 100644 Libs/platform/common/inc/sl_compiler.h create mode 100644 Libs/platform/common/inc/sl_core.h create mode 100644 Libs/platform/common/inc/sl_enum.h create mode 100644 Libs/platform/common/inc/sl_slist.h create mode 100644 Libs/platform/common/inc/sl_status.h create mode 100644 Libs/platform/common/inc/sli_cmsis_os2_ext_task_register.h create mode 100644 Libs/platform/common/inc/sli_code_classification.h create mode 100644 Libs/platform/common/src/sl_assert.c create mode 100644 Libs/platform/common/src/sl_cmsis_os2_common.c create mode 100644 Libs/platform/common/src/sl_core_cortexm.c create mode 100644 Libs/platform/common/src/sl_slist.c create mode 100644 Libs/platform/common/src/sl_syscalls.c create mode 100644 Libs/platform/common/src/sli_cmsis_os2_ext_task_register.c create mode 100644 Libs/platform/common/toolchain/inc/sl_gcc_preinclude.h create mode 100644 Libs/platform/common/toolchain/inc/sl_memory.h create mode 100644 Libs/platform/common/toolchain/inc/sl_memory_region.h create mode 100644 Libs/platform/driver/button/inc/sl_button.h create mode 100644 Libs/platform/driver/button/inc/sl_simple_button.h create mode 100644 Libs/platform/driver/button/src/sl_button.c create mode 100644 Libs/platform/driver/button/src/sl_simple_button.c create mode 100644 Libs/platform/driver/gpio/inc/sl_gpio.h create mode 100644 Libs/platform/driver/gpio/src/sl_gpio.c create mode 100644 Libs/platform/driver/leddrv/inc/sl_led.h create mode 100644 Libs/platform/driver/leddrv/inc/sl_simple_led.h create mode 100644 Libs/platform/driver/leddrv/src/sl_led.c create mode 100644 Libs/platform/driver/leddrv/src/sl_simple_led.c create mode 100644 Libs/platform/emlib/inc/em_acmp.h create mode 100644 Libs/platform/emlib/inc/em_assert.h create mode 100644 Libs/platform/emlib/inc/em_burtc.h create mode 100644 Libs/platform/emlib/inc/em_bus.h create mode 100644 Libs/platform/emlib/inc/em_chip.h create mode 100644 Libs/platform/emlib/inc/em_cmu.h create mode 100644 Libs/platform/emlib/inc/em_cmu_compat.h create mode 100644 Libs/platform/emlib/inc/em_common.h create mode 100644 Libs/platform/emlib/inc/em_core.h create mode 100644 Libs/platform/emlib/inc/em_core_generic.h create mode 100644 Libs/platform/emlib/inc/em_dbg.h create mode 100644 Libs/platform/emlib/inc/em_emu.h create mode 100644 Libs/platform/emlib/inc/em_eusart.h create mode 100644 Libs/platform/emlib/inc/em_eusart_compat.h create mode 100644 Libs/platform/emlib/inc/em_gpcrc.h create mode 100644 Libs/platform/emlib/inc/em_gpio.h create mode 100644 Libs/platform/emlib/inc/em_i2c.h create mode 100644 Libs/platform/emlib/inc/em_iadc.h create mode 100644 Libs/platform/emlib/inc/em_ldma.h create mode 100644 Libs/platform/emlib/inc/em_letimer.h create mode 100644 Libs/platform/emlib/inc/em_msc.h create mode 100644 Libs/platform/emlib/inc/em_msc_compat.h create mode 100644 Libs/platform/emlib/inc/em_opamp.h create mode 100644 Libs/platform/emlib/inc/em_pcnt.h create mode 100644 Libs/platform/emlib/inc/em_prs.h create mode 100644 Libs/platform/emlib/inc/em_ramfunc.h create mode 100644 Libs/platform/emlib/inc/em_rmu.h create mode 100644 Libs/platform/emlib/inc/em_smu.h create mode 100644 Libs/platform/emlib/inc/em_syscfg.h create mode 100644 Libs/platform/emlib/inc/em_system.h create mode 100644 Libs/platform/emlib/inc/em_system_generic.h create mode 100644 Libs/platform/emlib/inc/em_timer.h create mode 100644 Libs/platform/emlib/inc/em_usart.h create mode 100644 Libs/platform/emlib/inc/em_vdac.h create mode 100644 Libs/platform/emlib/inc/em_version.h create mode 100644 Libs/platform/emlib/inc/em_wdog.h create mode 100644 Libs/platform/emlib/inc/sli_em_cmu.h create mode 100644 Libs/platform/emlib/src/em_acmp.c create mode 100644 Libs/platform/emlib/src/em_burtc.c create mode 100644 Libs/platform/emlib/src/em_cmu.c create mode 100644 Libs/platform/emlib/src/em_core.c create mode 100644 Libs/platform/emlib/src/em_dbg.c create mode 100644 Libs/platform/emlib/src/em_emu.c create mode 100644 Libs/platform/emlib/src/em_eusart.c create mode 100644 Libs/platform/emlib/src/em_gpcrc.c create mode 100644 Libs/platform/emlib/src/em_gpio.c create mode 100644 Libs/platform/emlib/src/em_i2c.c create mode 100644 Libs/platform/emlib/src/em_iadc.c create mode 100644 Libs/platform/emlib/src/em_ldma.c create mode 100644 Libs/platform/emlib/src/em_letimer.c create mode 100644 Libs/platform/emlib/src/em_msc.c create mode 100644 Libs/platform/emlib/src/em_opamp.c create mode 100644 Libs/platform/emlib/src/em_pcnt.c create mode 100644 Libs/platform/emlib/src/em_prs.c create mode 100644 Libs/platform/emlib/src/em_rmu.c create mode 100644 Libs/platform/emlib/src/em_system.c create mode 100644 Libs/platform/emlib/src/em_timer.c create mode 100644 Libs/platform/emlib/src/em_usart.c create mode 100644 Libs/platform/emlib/src/em_vdac.c create mode 100644 Libs/platform/emlib/src/em_wdog.c create mode 100644 Libs/platform/peripheral/inc/peripheral_sysrtc.h create mode 100644 Libs/platform/peripheral/inc/peripheral_sysrtc_compat.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_bus.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_gpio.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_syscfg.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_sysrtc.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_sysrtc_compat.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_system.h create mode 100644 Libs/platform/peripheral/inc/sl_hal_system_generic.h create mode 100644 Libs/platform/peripheral/src/sl_hal_gpio.c create mode 100644 Libs/platform/peripheral/src/sl_hal_sysrtc.c create mode 100644 Libs/platform/peripheral/src/sl_hal_system.c create mode 100644 Libs/platform/service/clock_manager/inc/sl_clock_manager.h create mode 100644 Libs/platform/service/clock_manager/inc/sl_clock_manager_init.h create mode 100644 Libs/platform/service/clock_manager/inc/sli_clock_manager.h create mode 100644 Libs/platform/service/clock_manager/src/sl_clock_manager.c create mode 100644 Libs/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c create mode 100644 Libs/platform/service/clock_manager/src/sl_clock_manager_init.c create mode 100644 Libs/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c create mode 100644 Libs/platform/service/clock_manager/src/sli_clock_manager_hal.h create mode 100644 Libs/platform/service/clock_manager/src/sli_clock_manager_init_hal.h create mode 100644 Libs/platform/service/device_init/inc/sl_device_init_dcdc.h create mode 100644 Libs/platform/service/device_init/src/sl_device_init_dcdc_s2.c create mode 100644 Libs/platform/service/device_manager/clocks/sl_device_clock_efr32xg24.c create mode 100644 Libs/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c create mode 100644 Libs/platform/service/device_manager/inc/sl_device_clock.h create mode 100644 Libs/platform/service/device_manager/inc/sl_device_gpio.h create mode 100644 Libs/platform/service/device_manager/inc/sl_device_peripheral.h create mode 100644 Libs/platform/service/device_manager/inc/sl_device_peripheral_types.h create mode 100644 Libs/platform/service/device_manager/src/sl_device_clock.c create mode 100644 Libs/platform/service/device_manager/src/sl_device_gpio.c create mode 100644 Libs/platform/service/device_manager/src/sl_device_peripheral.c create mode 100644 Libs/platform/service/hfxo_manager/inc/sl_hfxo_manager.h create mode 100644 Libs/platform/service/hfxo_manager/inc/sli_hfxo_manager.h create mode 100644 Libs/platform/service/hfxo_manager/src/sl_hfxo_manager.c create mode 100644 Libs/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c create mode 100644 Libs/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h create mode 100644 Libs/platform/service/interrupt_manager/inc/arm/cmsis_nvic_virtual.h create mode 100644 Libs/platform/service/interrupt_manager/inc/sl_interrupt_manager.h create mode 100644 Libs/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c create mode 100644 Libs/platform/service/interrupt_manager/src/sli_interrupt_manager.h create mode 100644 Libs/platform/service/iostream/inc/sl_iostream.h create mode 100644 Libs/platform/service/iostream/inc/sl_iostream_rtt.h create mode 100644 Libs/platform/service/iostream/src/sl_iostream.c create mode 100644 Libs/platform/service/iostream/src/sl_iostream_rtt.c create mode 100644 Libs/platform/service/memory_manager/inc/sl_memory_manager.h create mode 100644 Libs/platform/service/memory_manager/inc/sl_memory_manager_region.h create mode 100644 Libs/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h create mode 100644 Libs/platform/service/memory_manager/profiler/src/sli_memory_profiler_stubs.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_cpp.cpp create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_pool.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_pool_common.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_region.c create mode 100644 Libs/platform/service/memory_manager/src/sl_memory_manager_retarget.c create mode 100644 Libs/platform/service/memory_manager/src/sli_memory_manager.h create mode 100644 Libs/platform/service/memory_manager/src/sli_memory_manager_common.c create mode 100644 Libs/platform/service/mpu/inc/sl_mpu.h create mode 100644 Libs/platform/service/mpu/src/sl_mpu.c create mode 100644 Libs/platform/service/power_manager/inc/sl_power_manager.h create mode 100644 Libs/platform/service/power_manager/inc/sl_power_manager_debug.h create mode 100644 Libs/platform/service/power_manager/inc/sli_power_manager.h create mode 100644 Libs/platform/service/power_manager/src/common/sl_power_manager_common.c create mode 100644 Libs/platform/service/power_manager/src/common/sl_power_manager_em4.c create mode 100644 Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager.c create mode 100644 Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c create mode 100644 Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c create mode 100644 Libs/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h create mode 100644 Libs/platform/service/sleeptimer/inc/sl_sleeptimer.h create mode 100644 Libs/platform/service/sleeptimer/inc/sli_sleeptimer.h create mode 100644 Libs/platform/service/sleeptimer/src/sl_sleeptimer.c create mode 100644 Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c create mode 100644 Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c create mode 100644 Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c create mode 100644 Libs/platform/service/sleeptimer/src/sli_sleeptimer_hal.h create mode 100644 Libs/platform/service/system/inc/sl_system_init.h create mode 100644 Libs/platform/service/system/inc/sl_system_kernel.h create mode 100644 Libs/platform/service/system/src/sl_system_init.c create mode 100644 Libs/platform/service/system/src/sl_system_kernel.c create mode 100644 Libs/platform/service/udelay/inc/sl_udelay.h create mode 100644 Libs/platform/service/udelay/src/sl_udelay.c create mode 100644 Libs/platform/service/udelay/src/sl_udelay_armv6m_gcc.S create mode 100644 Output/Debug/Obj/Firmware/Firmware_files.ind create mode 100644 Output/Debug/Obj/Firmware/em_emu-df97bff7.o.tmp create mode 100644 Output/Debug/Obj/Firmware/sl_syscalls-637c085d.o.tmp create mode 100644 Output/Debug/Obj/Firmware/timers-d0bfcf77.o.tmp create mode 100644 SEGGER_THUMB_Startup.s create mode 100644 autogen/RTE_Components.h create mode 100644 autogen/sl_component_catalog.h create mode 100644 autogen/sl_event_handler.c create mode 100644 autogen/sl_event_handler.h create mode 100644 config/FreeRTOSConfig.h create mode 100644 config/emlib_core_debug_config.h create mode 100644 config/sl_clock_manager_oscillator_config.h create mode 100644 config/sl_clock_manager_tree_config.h create mode 100644 config/sl_core_config.h create mode 100644 config/sl_device_init_dcdc_config.h create mode 100644 config/sl_hfxo_manager_config.h create mode 100644 config/sl_interrupt_manager_s2_config.h create mode 100644 config/sl_memory_manager_config.h create mode 100644 config/sl_memory_manager_region_config.h create mode 100644 config/sl_power_manager_config.h create mode 100644 config/sl_simple_button_config.h create mode 100644 config/sl_sleeptimer_config.h create mode 100644 main.c diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..acf5dd9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,88 @@ +# ---> C +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf + +# ---> C++ +# Prerequisites +*.d + +# Compiled Object files +*.slo +*.lo +*.o +*.obj + +# Precompiled Headers +*.gch +*.pch + +# Compiled Dynamic libraries +*.so +*.dylib +*.dll + +# Fortran module files +*.mod +*.smod + +# Compiled Static libraries +*.lai +*.la +*.a +*.lib + +# Executables +*.exe +*.out +*.app + diff --git a/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000..abebc95 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h b/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..a955d47 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h b/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1e255d5 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h b/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h b/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/CMSIS_5/CMSIS/Core/Include/cmsis_version.h b/CMSIS_5/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h b/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000..94128a1 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h b/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..932d3d1 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h b/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..c119fbf --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm0.h b/CMSIS_5/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..6441ff3 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h b/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..4e7179a --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm1.h b/CMSIS_5/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm23.h b/CMSIS_5/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..55fff99 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm3.h b/CMSIS_5/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..74fb87e --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm33.h b/CMSIS_5/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..18a2e6f --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm35p.h b/CMSIS_5/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000..3843d95 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm4.h b/CMSIS_5/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..e21cd14 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm55.h b/CMSIS_5/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 0000000..faa30ce --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm7.h b/CMSIS_5/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..010506e --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_cm85.h b/CMSIS_5/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 0000000..6046311 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_sc000.h b/CMSIS_5/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..dbc755f --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_sc300.h b/CMSIS_5/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..d666210 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/core_starmc1.h b/CMSIS_5/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 0000000..d86c8d3 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h b/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h b/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..3de16ef --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/CMSIS_5/CMSIS/Core/Include/pac_armv81.h b/CMSIS_5/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 0000000..854b60a --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h b/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000..f8f3d89 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/CMSIS_5/CMSIS/Core/Include/tz_context.h b/CMSIS_5/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/CMSIS_5/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/EFR32MG24/Device/Include/efr32mg24_acmp.h b/EFR32MG24/Device/Include/efr32mg24_acmp.h new file mode 100644 index 0000000..6087c46 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_acmp.h @@ -0,0 +1,654 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ACMP_H +#define EFR32MG24_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ACMP ACMP + * @{ + * @brief EFR32MG24 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group EFR32MG24_ACMP */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ACMP + * @{ + * @defgroup EFR32MG24_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 0x00000041UL /**< Mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 0x00000043UL /**< Mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 << 0) /**< Shifted mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 << 0) /**< Shifted mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group EFR32MG24_ACMP_BitFields */ +/** @} End of group EFR32MG24_ACMP */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_ACMP_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_aes.h b/EFR32MG24/Device/Include/efr32mg24_aes.h new file mode 100644 index 0000000..4927b6d --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_aes.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_AES_H +#define EFR32MG24_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_AES AES + * @{ + * @brief EFR32MG24 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32MG24_AES */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_AES + * @{ + * @defgroup EFR32MG24_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32MG24_AES_BitFields */ +/** @} End of group EFR32MG24_AES */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_AES_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_agc.h b/EFR32MG24/Device/Include/efr32mg24_agc.h new file mode 100644 index 0000000..a47d1a1 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_agc.h @@ -0,0 +1,2976 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 AGC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_AGC_H +#define EFR32MG24_AGC_H +#define AGC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_AGC AGC + * @{ + * @brief EFR32MG24 AGC Register Declaration. + *****************************************************************************/ + +/** AGC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS0; /**< Status register 0 */ + __IM uint32_t STATUS1; /**< Status register 1 */ + __IM uint32_t STATUS2; /**< Status register 2 */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t RSSI; /**< Received Signal Strength Indicator */ + __IM uint32_t FRAMERSSI; /**< FRAME RSSI value */ + __IOM uint32_t CTRL0; /**< Control register 0 */ + __IOM uint32_t CTRL1; /**< Control register 1 */ + __IOM uint32_t CTRL2; /**< Control register 2 */ + __IOM uint32_t CTRL3; /**< Control register 3 */ + __IOM uint32_t CTRL4; /**< Control register 4 */ + __IOM uint32_t CTRL5; /**< Control register 5 */ + __IOM uint32_t CTRL6; /**< Control register 6 */ + __IOM uint32_t CTRL7; /**< Control register 1 */ + __IOM uint32_t RSSISTEPTHR; /**< RSSI step threshold */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t GAINRANGE; /**< Range of RX Gain to use in AGC */ + __IOM uint32_t AGCPERIOD0; /**< AGC period */ + __IOM uint32_t AGCPERIOD1; /**< AGC Period */ + __IOM uint32_t HICNTREGION0; /**< Hi-counter region-0 */ + __IOM uint32_t HICNTREGION1; /**< Hi-counter region-1 */ + __IOM uint32_t STEPDWN; /**< Hi-counter region-2 */ + __IOM uint32_t GAINSTEPLIM0; /**< Limits for Gain Steps */ + __IOM uint32_t GAINSTEPLIM1; /**< Limits for Gain Steps */ + __IOM uint32_t PNRFATT0; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFATT1; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFATT2; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFATT3; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT4; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT5; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT6; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT7; /**< PN RF attenuation code group 3 */ + uint32_t RESERVED3[4U]; /**< Reserved for future use */ + __IOM uint32_t PNRFATTALT; /**< PN RF attenuation code group 3 */ + __IOM uint32_t LNAMIXCODE0; /**< LNA/MIX slice code group 0 */ + __IOM uint32_t LNAMIXCODE1; /**< LNA/MIX slice code group 1 */ + __IOM uint32_t PGACODE0; /**< PGA gain code group 0 */ + __IOM uint32_t PGACODE1; /**< PGA gain code group 1 */ + __IOM uint32_t LBT; /**< Configure AGC for (ETSI) LBT */ + __IOM uint32_t MIRRORIF; /**< Mirror Interrupt Flags Register */ + __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags Register */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t RSSIABSTHR; /**< RSSI absolute threshold */ + __IOM uint32_t LNABOOST; /**< LNA boost control register */ + __IOM uint32_t ANTDIV; /**< Antenna diversity AGC setting */ + __IOM uint32_t DUALRFPKDTHD0; /**< Thresholds for dual rfpkd */ + __IOM uint32_t DUALRFPKDTHD1; /**< Thresholds for dual rfpkd */ + __IOM uint32_t SPARE; /**< Spare register for ECO */ + __IOM uint32_t PNRFFILT0; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFFILT1; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFFILT2; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFFILT3; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT4; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT5; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT6; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT7; /**< PN RF attenuation code group 3 */ + __IOM uint32_t FENOTCHATT0; /**< FE Notch attenuation code group 0 */ + __IOM uint32_t FENOTCHATT1; /**< FE Notch attenuation code group 1 */ + __IOM uint32_t FENOTCHATT2; /**< FE Notch attenuation code group 2 */ + __IOM uint32_t FENOTCHATT3; /**< FE Notch attenuation code group 3 */ + __IOM uint32_t FENOTCHATT4; /**< FE Notch attenuation code group 4 */ + __IOM uint32_t FENOTCHATT5; /**< FE Notch attenuation code group 5 */ + __IOM uint32_t FENOTCHATT6; /**< FE Notch attenuation code group 6 */ + __IOM uint32_t FENOTCHATT7; /**< FE Notch attenuation code group 7 */ + __IOM uint32_t FENOTCHATT8; /**< FE Notch attenuation code group 8 */ + __IOM uint32_t FENOTCHATT9; /**< FE Notch attenuation code group 9 */ + __IOM uint32_t FENOTCHATT10; /**< FE Notch attenuation code group 10 */ + __IOM uint32_t FENOTCHATT11; /**< FE Notch attenuation code group 11 */ + __IOM uint32_t FENOTCHFILT0; /**< FE Notch filter code group 0 */ + __IOM uint32_t FENOTCHFILT1; /**< FE Notch filter code group 1 */ + __IOM uint32_t FENOTCHFILT2; /**< FE Notch filter code group 2 */ + __IOM uint32_t FENOTCHFILT3; /**< FE Notch filter code group 3 */ + __IOM uint32_t FENOTCHFILT4; /**< FE Notch filter code group 4 */ + __IOM uint32_t FENOTCHFILT5; /**< FE Notch filter code group 5 */ + __IOM uint32_t FENOTCHFILT6; /**< FE Notch filter code group 6 */ + __IOM uint32_t FENOTCHFILT7; /**< FE Notch filter code group 7 */ + __IOM uint32_t FENOTCHFILT8; /**< FE Notch filter code group 8 */ + __IOM uint32_t FENOTCHFILT9; /**< FE Notch filter code group 9 */ + __IOM uint32_t FENOTCHFILT10; /**< FE Notch filter code group 10 */ + __IOM uint32_t FENOTCHFILT11; /**< FE Notch filter code group 11 */ + __IM uint32_t CCADEBUG; /**< CCA debug register */ + uint32_t RESERVED4[935U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS0_SET; /**< Status register 0 */ + __IM uint32_t STATUS1_SET; /**< Status register 1 */ + __IM uint32_t STATUS2_SET; /**< Status register 2 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t RSSI_SET; /**< Received Signal Strength Indicator */ + __IM uint32_t FRAMERSSI_SET; /**< FRAME RSSI value */ + __IOM uint32_t CTRL0_SET; /**< Control register 0 */ + __IOM uint32_t CTRL1_SET; /**< Control register 1 */ + __IOM uint32_t CTRL2_SET; /**< Control register 2 */ + __IOM uint32_t CTRL3_SET; /**< Control register 3 */ + __IOM uint32_t CTRL4_SET; /**< Control register 4 */ + __IOM uint32_t CTRL5_SET; /**< Control register 5 */ + __IOM uint32_t CTRL6_SET; /**< Control register 6 */ + __IOM uint32_t CTRL7_SET; /**< Control register 1 */ + __IOM uint32_t RSSISTEPTHR_SET; /**< RSSI step threshold */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t GAINRANGE_SET; /**< Range of RX Gain to use in AGC */ + __IOM uint32_t AGCPERIOD0_SET; /**< AGC period */ + __IOM uint32_t AGCPERIOD1_SET; /**< AGC Period */ + __IOM uint32_t HICNTREGION0_SET; /**< Hi-counter region-0 */ + __IOM uint32_t HICNTREGION1_SET; /**< Hi-counter region-1 */ + __IOM uint32_t STEPDWN_SET; /**< Hi-counter region-2 */ + __IOM uint32_t GAINSTEPLIM0_SET; /**< Limits for Gain Steps */ + __IOM uint32_t GAINSTEPLIM1_SET; /**< Limits for Gain Steps */ + __IOM uint32_t PNRFATT0_SET; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFATT1_SET; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFATT2_SET; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFATT3_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT4_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT5_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT6_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT7_SET; /**< PN RF attenuation code group 3 */ + uint32_t RESERVED8[4U]; /**< Reserved for future use */ + __IOM uint32_t PNRFATTALT_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t LNAMIXCODE0_SET; /**< LNA/MIX slice code group 0 */ + __IOM uint32_t LNAMIXCODE1_SET; /**< LNA/MIX slice code group 1 */ + __IOM uint32_t PGACODE0_SET; /**< PGA gain code group 0 */ + __IOM uint32_t PGACODE1_SET; /**< PGA gain code group 1 */ + __IOM uint32_t LBT_SET; /**< Configure AGC for (ETSI) LBT */ + __IOM uint32_t MIRRORIF_SET; /**< Mirror Interrupt Flags Register */ + __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags Register */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t RSSIABSTHR_SET; /**< RSSI absolute threshold */ + __IOM uint32_t LNABOOST_SET; /**< LNA boost control register */ + __IOM uint32_t ANTDIV_SET; /**< Antenna diversity AGC setting */ + __IOM uint32_t DUALRFPKDTHD0_SET; /**< Thresholds for dual rfpkd */ + __IOM uint32_t DUALRFPKDTHD1_SET; /**< Thresholds for dual rfpkd */ + __IOM uint32_t SPARE_SET; /**< Spare register for ECO */ + __IOM uint32_t PNRFFILT0_SET; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFFILT1_SET; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFFILT2_SET; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFFILT3_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT4_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT5_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT6_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT7_SET; /**< PN RF attenuation code group 3 */ + __IOM uint32_t FENOTCHATT0_SET; /**< FE Notch attenuation code group 0 */ + __IOM uint32_t FENOTCHATT1_SET; /**< FE Notch attenuation code group 1 */ + __IOM uint32_t FENOTCHATT2_SET; /**< FE Notch attenuation code group 2 */ + __IOM uint32_t FENOTCHATT3_SET; /**< FE Notch attenuation code group 3 */ + __IOM uint32_t FENOTCHATT4_SET; /**< FE Notch attenuation code group 4 */ + __IOM uint32_t FENOTCHATT5_SET; /**< FE Notch attenuation code group 5 */ + __IOM uint32_t FENOTCHATT6_SET; /**< FE Notch attenuation code group 6 */ + __IOM uint32_t FENOTCHATT7_SET; /**< FE Notch attenuation code group 7 */ + __IOM uint32_t FENOTCHATT8_SET; /**< FE Notch attenuation code group 8 */ + __IOM uint32_t FENOTCHATT9_SET; /**< FE Notch attenuation code group 9 */ + __IOM uint32_t FENOTCHATT10_SET; /**< FE Notch attenuation code group 10 */ + __IOM uint32_t FENOTCHATT11_SET; /**< FE Notch attenuation code group 11 */ + __IOM uint32_t FENOTCHFILT0_SET; /**< FE Notch filter code group 0 */ + __IOM uint32_t FENOTCHFILT1_SET; /**< FE Notch filter code group 1 */ + __IOM uint32_t FENOTCHFILT2_SET; /**< FE Notch filter code group 2 */ + __IOM uint32_t FENOTCHFILT3_SET; /**< FE Notch filter code group 3 */ + __IOM uint32_t FENOTCHFILT4_SET; /**< FE Notch filter code group 4 */ + __IOM uint32_t FENOTCHFILT5_SET; /**< FE Notch filter code group 5 */ + __IOM uint32_t FENOTCHFILT6_SET; /**< FE Notch filter code group 6 */ + __IOM uint32_t FENOTCHFILT7_SET; /**< FE Notch filter code group 7 */ + __IOM uint32_t FENOTCHFILT8_SET; /**< FE Notch filter code group 8 */ + __IOM uint32_t FENOTCHFILT9_SET; /**< FE Notch filter code group 9 */ + __IOM uint32_t FENOTCHFILT10_SET; /**< FE Notch filter code group 10 */ + __IOM uint32_t FENOTCHFILT11_SET; /**< FE Notch filter code group 11 */ + __IM uint32_t CCADEBUG_SET; /**< CCA debug register */ + uint32_t RESERVED9[935U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS0_CLR; /**< Status register 0 */ + __IM uint32_t STATUS1_CLR; /**< Status register 1 */ + __IM uint32_t STATUS2_CLR; /**< Status register 2 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IM uint32_t RSSI_CLR; /**< Received Signal Strength Indicator */ + __IM uint32_t FRAMERSSI_CLR; /**< FRAME RSSI value */ + __IOM uint32_t CTRL0_CLR; /**< Control register 0 */ + __IOM uint32_t CTRL1_CLR; /**< Control register 1 */ + __IOM uint32_t CTRL2_CLR; /**< Control register 2 */ + __IOM uint32_t CTRL3_CLR; /**< Control register 3 */ + __IOM uint32_t CTRL4_CLR; /**< Control register 4 */ + __IOM uint32_t CTRL5_CLR; /**< Control register 5 */ + __IOM uint32_t CTRL6_CLR; /**< Control register 6 */ + __IOM uint32_t CTRL7_CLR; /**< Control register 1 */ + __IOM uint32_t RSSISTEPTHR_CLR; /**< RSSI step threshold */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t GAINRANGE_CLR; /**< Range of RX Gain to use in AGC */ + __IOM uint32_t AGCPERIOD0_CLR; /**< AGC period */ + __IOM uint32_t AGCPERIOD1_CLR; /**< AGC Period */ + __IOM uint32_t HICNTREGION0_CLR; /**< Hi-counter region-0 */ + __IOM uint32_t HICNTREGION1_CLR; /**< Hi-counter region-1 */ + __IOM uint32_t STEPDWN_CLR; /**< Hi-counter region-2 */ + __IOM uint32_t GAINSTEPLIM0_CLR; /**< Limits for Gain Steps */ + __IOM uint32_t GAINSTEPLIM1_CLR; /**< Limits for Gain Steps */ + __IOM uint32_t PNRFATT0_CLR; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFATT1_CLR; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFATT2_CLR; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFATT3_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT4_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT5_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT6_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT7_CLR; /**< PN RF attenuation code group 3 */ + uint32_t RESERVED13[4U]; /**< Reserved for future use */ + __IOM uint32_t PNRFATTALT_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t LNAMIXCODE0_CLR; /**< LNA/MIX slice code group 0 */ + __IOM uint32_t LNAMIXCODE1_CLR; /**< LNA/MIX slice code group 1 */ + __IOM uint32_t PGACODE0_CLR; /**< PGA gain code group 0 */ + __IOM uint32_t PGACODE1_CLR; /**< PGA gain code group 1 */ + __IOM uint32_t LBT_CLR; /**< Configure AGC for (ETSI) LBT */ + __IOM uint32_t MIRRORIF_CLR; /**< Mirror Interrupt Flags Register */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags Register */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t RSSIABSTHR_CLR; /**< RSSI absolute threshold */ + __IOM uint32_t LNABOOST_CLR; /**< LNA boost control register */ + __IOM uint32_t ANTDIV_CLR; /**< Antenna diversity AGC setting */ + __IOM uint32_t DUALRFPKDTHD0_CLR; /**< Thresholds for dual rfpkd */ + __IOM uint32_t DUALRFPKDTHD1_CLR; /**< Thresholds for dual rfpkd */ + __IOM uint32_t SPARE_CLR; /**< Spare register for ECO */ + __IOM uint32_t PNRFFILT0_CLR; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFFILT1_CLR; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFFILT2_CLR; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFFILT3_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT4_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT5_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT6_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT7_CLR; /**< PN RF attenuation code group 3 */ + __IOM uint32_t FENOTCHATT0_CLR; /**< FE Notch attenuation code group 0 */ + __IOM uint32_t FENOTCHATT1_CLR; /**< FE Notch attenuation code group 1 */ + __IOM uint32_t FENOTCHATT2_CLR; /**< FE Notch attenuation code group 2 */ + __IOM uint32_t FENOTCHATT3_CLR; /**< FE Notch attenuation code group 3 */ + __IOM uint32_t FENOTCHATT4_CLR; /**< FE Notch attenuation code group 4 */ + __IOM uint32_t FENOTCHATT5_CLR; /**< FE Notch attenuation code group 5 */ + __IOM uint32_t FENOTCHATT6_CLR; /**< FE Notch attenuation code group 6 */ + __IOM uint32_t FENOTCHATT7_CLR; /**< FE Notch attenuation code group 7 */ + __IOM uint32_t FENOTCHATT8_CLR; /**< FE Notch attenuation code group 8 */ + __IOM uint32_t FENOTCHATT9_CLR; /**< FE Notch attenuation code group 9 */ + __IOM uint32_t FENOTCHATT10_CLR; /**< FE Notch attenuation code group 10 */ + __IOM uint32_t FENOTCHATT11_CLR; /**< FE Notch attenuation code group 11 */ + __IOM uint32_t FENOTCHFILT0_CLR; /**< FE Notch filter code group 0 */ + __IOM uint32_t FENOTCHFILT1_CLR; /**< FE Notch filter code group 1 */ + __IOM uint32_t FENOTCHFILT2_CLR; /**< FE Notch filter code group 2 */ + __IOM uint32_t FENOTCHFILT3_CLR; /**< FE Notch filter code group 3 */ + __IOM uint32_t FENOTCHFILT4_CLR; /**< FE Notch filter code group 4 */ + __IOM uint32_t FENOTCHFILT5_CLR; /**< FE Notch filter code group 5 */ + __IOM uint32_t FENOTCHFILT6_CLR; /**< FE Notch filter code group 6 */ + __IOM uint32_t FENOTCHFILT7_CLR; /**< FE Notch filter code group 7 */ + __IOM uint32_t FENOTCHFILT8_CLR; /**< FE Notch filter code group 8 */ + __IOM uint32_t FENOTCHFILT9_CLR; /**< FE Notch filter code group 9 */ + __IOM uint32_t FENOTCHFILT10_CLR; /**< FE Notch filter code group 10 */ + __IOM uint32_t FENOTCHFILT11_CLR; /**< FE Notch filter code group 11 */ + __IM uint32_t CCADEBUG_CLR; /**< CCA debug register */ + uint32_t RESERVED14[935U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS0_TGL; /**< Status register 0 */ + __IM uint32_t STATUS1_TGL; /**< Status register 1 */ + __IM uint32_t STATUS2_TGL; /**< Status register 2 */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IM uint32_t RSSI_TGL; /**< Received Signal Strength Indicator */ + __IM uint32_t FRAMERSSI_TGL; /**< FRAME RSSI value */ + __IOM uint32_t CTRL0_TGL; /**< Control register 0 */ + __IOM uint32_t CTRL1_TGL; /**< Control register 1 */ + __IOM uint32_t CTRL2_TGL; /**< Control register 2 */ + __IOM uint32_t CTRL3_TGL; /**< Control register 3 */ + __IOM uint32_t CTRL4_TGL; /**< Control register 4 */ + __IOM uint32_t CTRL5_TGL; /**< Control register 5 */ + __IOM uint32_t CTRL6_TGL; /**< Control register 6 */ + __IOM uint32_t CTRL7_TGL; /**< Control register 1 */ + __IOM uint32_t RSSISTEPTHR_TGL; /**< RSSI step threshold */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t GAINRANGE_TGL; /**< Range of RX Gain to use in AGC */ + __IOM uint32_t AGCPERIOD0_TGL; /**< AGC period */ + __IOM uint32_t AGCPERIOD1_TGL; /**< AGC Period */ + __IOM uint32_t HICNTREGION0_TGL; /**< Hi-counter region-0 */ + __IOM uint32_t HICNTREGION1_TGL; /**< Hi-counter region-1 */ + __IOM uint32_t STEPDWN_TGL; /**< Hi-counter region-2 */ + __IOM uint32_t GAINSTEPLIM0_TGL; /**< Limits for Gain Steps */ + __IOM uint32_t GAINSTEPLIM1_TGL; /**< Limits for Gain Steps */ + __IOM uint32_t PNRFATT0_TGL; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFATT1_TGL; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFATT2_TGL; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFATT3_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT4_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT5_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT6_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFATT7_TGL; /**< PN RF attenuation code group 3 */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + __IOM uint32_t PNRFATTALT_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t LNAMIXCODE0_TGL; /**< LNA/MIX slice code group 0 */ + __IOM uint32_t LNAMIXCODE1_TGL; /**< LNA/MIX slice code group 1 */ + __IOM uint32_t PGACODE0_TGL; /**< PGA gain code group 0 */ + __IOM uint32_t PGACODE1_TGL; /**< PGA gain code group 1 */ + __IOM uint32_t LBT_TGL; /**< Configure AGC for (ETSI) LBT */ + __IOM uint32_t MIRRORIF_TGL; /**< Mirror Interrupt Flags Register */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags Register */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t RSSIABSTHR_TGL; /**< RSSI absolute threshold */ + __IOM uint32_t LNABOOST_TGL; /**< LNA boost control register */ + __IOM uint32_t ANTDIV_TGL; /**< Antenna diversity AGC setting */ + __IOM uint32_t DUALRFPKDTHD0_TGL; /**< Thresholds for dual rfpkd */ + __IOM uint32_t DUALRFPKDTHD1_TGL; /**< Thresholds for dual rfpkd */ + __IOM uint32_t SPARE_TGL; /**< Spare register for ECO */ + __IOM uint32_t PNRFFILT0_TGL; /**< PN RF attenuation code group 0 */ + __IOM uint32_t PNRFFILT1_TGL; /**< PN RF attenuation code group 1 */ + __IOM uint32_t PNRFFILT2_TGL; /**< PN RF attenuation code group 2 */ + __IOM uint32_t PNRFFILT3_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT4_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT5_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT6_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t PNRFFILT7_TGL; /**< PN RF attenuation code group 3 */ + __IOM uint32_t FENOTCHATT0_TGL; /**< FE Notch attenuation code group 0 */ + __IOM uint32_t FENOTCHATT1_TGL; /**< FE Notch attenuation code group 1 */ + __IOM uint32_t FENOTCHATT2_TGL; /**< FE Notch attenuation code group 2 */ + __IOM uint32_t FENOTCHATT3_TGL; /**< FE Notch attenuation code group 3 */ + __IOM uint32_t FENOTCHATT4_TGL; /**< FE Notch attenuation code group 4 */ + __IOM uint32_t FENOTCHATT5_TGL; /**< FE Notch attenuation code group 5 */ + __IOM uint32_t FENOTCHATT6_TGL; /**< FE Notch attenuation code group 6 */ + __IOM uint32_t FENOTCHATT7_TGL; /**< FE Notch attenuation code group 7 */ + __IOM uint32_t FENOTCHATT8_TGL; /**< FE Notch attenuation code group 8 */ + __IOM uint32_t FENOTCHATT9_TGL; /**< FE Notch attenuation code group 9 */ + __IOM uint32_t FENOTCHATT10_TGL; /**< FE Notch attenuation code group 10 */ + __IOM uint32_t FENOTCHATT11_TGL; /**< FE Notch attenuation code group 11 */ + __IOM uint32_t FENOTCHFILT0_TGL; /**< FE Notch filter code group 0 */ + __IOM uint32_t FENOTCHFILT1_TGL; /**< FE Notch filter code group 1 */ + __IOM uint32_t FENOTCHFILT2_TGL; /**< FE Notch filter code group 2 */ + __IOM uint32_t FENOTCHFILT3_TGL; /**< FE Notch filter code group 3 */ + __IOM uint32_t FENOTCHFILT4_TGL; /**< FE Notch filter code group 4 */ + __IOM uint32_t FENOTCHFILT5_TGL; /**< FE Notch filter code group 5 */ + __IOM uint32_t FENOTCHFILT6_TGL; /**< FE Notch filter code group 6 */ + __IOM uint32_t FENOTCHFILT7_TGL; /**< FE Notch filter code group 7 */ + __IOM uint32_t FENOTCHFILT8_TGL; /**< FE Notch filter code group 8 */ + __IOM uint32_t FENOTCHFILT9_TGL; /**< FE Notch filter code group 9 */ + __IOM uint32_t FENOTCHFILT10_TGL; /**< FE Notch filter code group 10 */ + __IOM uint32_t FENOTCHFILT11_TGL; /**< FE Notch filter code group 11 */ + __IM uint32_t CCADEBUG_TGL; /**< CCA debug register */ +} AGC_TypeDef; +/** @} End of group EFR32MG24_AGC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_AGC + * @{ + * @defgroup EFR32MG24_AGC_BitFields AGC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AGC IPVERSION */ +#define _AGC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for AGC_IPVERSION */ +#define _AGC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AGC_IPVERSION */ +#define _AGC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AGC_IPVERSION */ +#define _AGC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AGC_IPVERSION */ +#define _AGC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_IPVERSION */ +#define AGC_IPVERSION_IPVERSION_DEFAULT (_AGC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IPVERSION */ + +/* Bit fields for AGC EN */ +#define _AGC_EN_RESETVALUE 0x00000000UL /**< Default value for AGC_EN */ +#define _AGC_EN_MASK 0x00000001UL /**< Mask for AGC_EN */ +#define AGC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _AGC_EN_EN_SHIFT 0 /**< Shift value for AGC_EN */ +#define _AGC_EN_EN_MASK 0x1UL /**< Bit mask for AGC_EN */ +#define _AGC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_EN */ +#define AGC_EN_EN_DEFAULT (_AGC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_EN */ + +/* Bit fields for AGC STATUS0 */ +#define _AGC_STATUS0_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS0 */ +#define _AGC_STATUS0_MASK 0x07FFFFFFUL /**< Mask for AGC_STATUS0 */ +#define _AGC_STATUS0_GAININDEX_SHIFT 0 /**< Shift value for AGC_GAININDEX */ +#define _AGC_STATUS0_GAININDEX_MASK 0x3FUL /**< Bit mask for AGC_GAININDEX */ +#define _AGC_STATUS0_GAININDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_GAININDEX_DEFAULT (_AGC_STATUS0_GAININDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_RFPKDLOWLAT (0x1UL << 6) /**< RFPKD low Latch */ +#define _AGC_STATUS0_RFPKDLOWLAT_SHIFT 6 /**< Shift value for AGC_RFPKDLOWLAT */ +#define _AGC_STATUS0_RFPKDLOWLAT_MASK 0x40UL /**< Bit mask for AGC_RFPKDLOWLAT */ +#define _AGC_STATUS0_RFPKDLOWLAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_RFPKDLOWLAT_DEFAULT (_AGC_STATUS0_RFPKDLOWLAT_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_RFPKDHILAT (0x1UL << 7) /**< RFPKD hi Latch */ +#define _AGC_STATUS0_RFPKDHILAT_SHIFT 7 /**< Shift value for AGC_RFPKDHILAT */ +#define _AGC_STATUS0_RFPKDHILAT_MASK 0x80UL /**< Bit mask for AGC_RFPKDHILAT */ +#define _AGC_STATUS0_RFPKDHILAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_RFPKDHILAT_DEFAULT (_AGC_STATUS0_RFPKDHILAT_DEFAULT << 7) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_IFPKDLOLAT (0x1UL << 8) /**< IFPKD Lo threshold pass Latch */ +#define _AGC_STATUS0_IFPKDLOLAT_SHIFT 8 /**< Shift value for AGC_IFPKDLOLAT */ +#define _AGC_STATUS0_IFPKDLOLAT_MASK 0x100UL /**< Bit mask for AGC_IFPKDLOLAT */ +#define _AGC_STATUS0_IFPKDLOLAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_IFPKDLOLAT_DEFAULT (_AGC_STATUS0_IFPKDLOLAT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_IFPKDHILAT (0x1UL << 9) /**< IFPKD Hi threshold pass Latch */ +#define _AGC_STATUS0_IFPKDHILAT_SHIFT 9 /**< Shift value for AGC_IFPKDHILAT */ +#define _AGC_STATUS0_IFPKDHILAT_MASK 0x200UL /**< Bit mask for AGC_IFPKDHILAT */ +#define _AGC_STATUS0_IFPKDHILAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_IFPKDHILAT_DEFAULT (_AGC_STATUS0_IFPKDHILAT_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_CCA (0x1UL << 10) /**< Clear Channel Assessment */ +#define _AGC_STATUS0_CCA_SHIFT 10 /**< Shift value for AGC_CCA */ +#define _AGC_STATUS0_CCA_MASK 0x400UL /**< Bit mask for AGC_CCA */ +#define _AGC_STATUS0_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_CCA_DEFAULT (_AGC_STATUS0_CCA_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_GAINOK (0x1UL << 11) /**< Gain OK */ +#define _AGC_STATUS0_GAINOK_SHIFT 11 /**< Shift value for AGC_GAINOK */ +#define _AGC_STATUS0_GAINOK_MASK 0x800UL /**< Bit mask for AGC_GAINOK */ +#define _AGC_STATUS0_GAINOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_GAINOK_DEFAULT (_AGC_STATUS0_GAINOK_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define _AGC_STATUS0_PGAINDEX_SHIFT 12 /**< Shift value for AGC_PGAINDEX */ +#define _AGC_STATUS0_PGAINDEX_MASK 0xF000UL /**< Bit mask for AGC_PGAINDEX */ +#define _AGC_STATUS0_PGAINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_PGAINDEX_DEFAULT (_AGC_STATUS0_PGAINDEX_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define _AGC_STATUS0_LNAINDEX_SHIFT 16 /**< Shift value for AGC_LNAINDEX */ +#define _AGC_STATUS0_LNAINDEX_MASK 0xF0000UL /**< Bit mask for AGC_LNAINDEX */ +#define _AGC_STATUS0_LNAINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_LNAINDEX_DEFAULT (_AGC_STATUS0_LNAINDEX_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define _AGC_STATUS0_PNINDEX_SHIFT 20 /**< Shift value for AGC_PNINDEX */ +#define _AGC_STATUS0_PNINDEX_MASK 0x1F00000UL /**< Bit mask for AGC_PNINDEX */ +#define _AGC_STATUS0_PNINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_PNINDEX_DEFAULT (_AGC_STATUS0_PNINDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_STATUS0 */ +#define _AGC_STATUS0_ADCINDEX_SHIFT 25 /**< Shift value for AGC_ADCINDEX */ +#define _AGC_STATUS0_ADCINDEX_MASK 0x6000000UL /**< Bit mask for AGC_ADCINDEX */ +#define _AGC_STATUS0_ADCINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */ +#define AGC_STATUS0_ADCINDEX_DEFAULT (_AGC_STATUS0_ADCINDEX_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_STATUS0 */ + +/* Bit fields for AGC STATUS1 */ +#define _AGC_STATUS1_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS1 */ +#define _AGC_STATUS1_MASK 0x3FFFFEFFUL /**< Mask for AGC_STATUS1 */ +#define _AGC_STATUS1_RFPKDLOWLATCNT_SHIFT 18 /**< Shift value for AGC_RFPKDLOWLATCNT */ +#define _AGC_STATUS1_RFPKDLOWLATCNT_MASK 0x3FFC0000UL /**< Bit mask for AGC_RFPKDLOWLATCNT */ +#define _AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS1 */ +#define AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT (_AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_STATUS1 */ + +/* Bit fields for AGC STATUS2 */ +#define _AGC_STATUS2_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS2 */ +#define _AGC_STATUS2_MASK 0xFFFF4FFFUL /**< Mask for AGC_STATUS2 */ +#define _AGC_STATUS2_RFPKDHILATCNT_SHIFT 0 /**< Shift value for AGC_RFPKDHILATCNT */ +#define _AGC_STATUS2_RFPKDHILATCNT_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDHILATCNT */ +#define _AGC_STATUS2_RFPKDHILATCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */ +#define AGC_STATUS2_RFPKDHILATCNT_DEFAULT (_AGC_STATUS2_RFPKDHILATCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STATUS2 */ +#define AGC_STATUS2_PNDWNUP (0x1UL << 14) /**< Allow PN GAIN UP */ +#define _AGC_STATUS2_PNDWNUP_SHIFT 14 /**< Shift value for AGC_PNDWNUP */ +#define _AGC_STATUS2_PNDWNUP_MASK 0x4000UL /**< Bit mask for AGC_PNDWNUP */ +#define _AGC_STATUS2_PNDWNUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */ +#define AGC_STATUS2_PNDWNUP_DEFAULT (_AGC_STATUS2_PNDWNUP_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_STATUS2 */ +#define _AGC_STATUS2_RFPKDPRDCNT_SHIFT 16 /**< Shift value for AGC_RFPKDPRDCNT */ +#define _AGC_STATUS2_RFPKDPRDCNT_MASK 0xFFFF0000UL /**< Bit mask for AGC_RFPKDPRDCNT */ +#define _AGC_STATUS2_RFPKDPRDCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */ +#define AGC_STATUS2_RFPKDPRDCNT_DEFAULT (_AGC_STATUS2_RFPKDPRDCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_STATUS2 */ + +/* Bit fields for AGC RSSI */ +#define _AGC_RSSI_RESETVALUE 0x00008000UL /**< Default value for AGC_RSSI */ +#define _AGC_RSSI_MASK 0x0000FFC0UL /**< Mask for AGC_RSSI */ +#define _AGC_RSSI_RSSIFRAC_SHIFT 6 /**< Shift value for AGC_RSSIFRAC */ +#define _AGC_RSSI_RSSIFRAC_MASK 0xC0UL /**< Bit mask for AGC_RSSIFRAC */ +#define _AGC_RSSI_RSSIFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSI */ +#define AGC_RSSI_RSSIFRAC_DEFAULT (_AGC_RSSI_RSSIFRAC_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_RSSI */ +#define _AGC_RSSI_RSSIINT_SHIFT 8 /**< Shift value for AGC_RSSIINT */ +#define _AGC_RSSI_RSSIINT_MASK 0xFF00UL /**< Bit mask for AGC_RSSIINT */ +#define _AGC_RSSI_RSSIINT_DEFAULT 0x00000080UL /**< Mode DEFAULT for AGC_RSSI */ +#define AGC_RSSI_RSSIINT_DEFAULT (_AGC_RSSI_RSSIINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSI */ + +/* Bit fields for AGC FRAMERSSI */ +#define _AGC_FRAMERSSI_RESETVALUE 0x00008000UL /**< Default value for AGC_FRAMERSSI */ +#define _AGC_FRAMERSSI_MASK 0x0000FFC0UL /**< Mask for AGC_FRAMERSSI */ +#define _AGC_FRAMERSSI_FRAMERSSIFRAC_SHIFT 6 /**< Shift value for AGC_FRAMERSSIFRAC */ +#define _AGC_FRAMERSSI_FRAMERSSIFRAC_MASK 0xC0UL /**< Bit mask for AGC_FRAMERSSIFRAC */ +#define _AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FRAMERSSI */ +#define AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT (_AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_FRAMERSSI */ +#define _AGC_FRAMERSSI_FRAMERSSIINT_SHIFT 8 /**< Shift value for AGC_FRAMERSSIINT */ +#define _AGC_FRAMERSSI_FRAMERSSIINT_MASK 0xFF00UL /**< Bit mask for AGC_FRAMERSSIINT */ +#define _AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT 0x00000080UL /**< Mode DEFAULT for AGC_FRAMERSSI */ +#define AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT (_AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FRAMERSSI */ + +/* Bit fields for AGC CTRL0 */ +#define _AGC_CTRL0_RESETVALUE 0x2132727FUL /**< Default value for AGC_CTRL0 */ +#define _AGC_CTRL0_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL0 */ +#define _AGC_CTRL0_PWRTARGET_SHIFT 0 /**< Shift value for AGC_PWRTARGET */ +#define _AGC_CTRL0_PWRTARGET_MASK 0xFFUL /**< Bit mask for AGC_PWRTARGET */ +#define _AGC_CTRL0_PWRTARGET_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_PWRTARGET_DEFAULT (_AGC_CTRL0_PWRTARGET_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define _AGC_CTRL0_MODE_SHIFT 8 /**< Shift value for AGC_MODE */ +#define _AGC_CTRL0_MODE_MASK 0x700UL /**< Bit mask for AGC_MODE */ +#define _AGC_CTRL0_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define _AGC_CTRL0_MODE_CONT 0x00000000UL /**< Mode CONT for AGC_CTRL0 */ +#define _AGC_CTRL0_MODE_LOCKPREDET 0x00000001UL /**< Mode LOCKPREDET for AGC_CTRL0 */ +#define _AGC_CTRL0_MODE_LOCKFRAMEDET 0x00000002UL /**< Mode LOCKFRAMEDET for AGC_CTRL0 */ +#define _AGC_CTRL0_MODE_LOCKDSA 0x00000003UL /**< Mode LOCKDSA for AGC_CTRL0 */ +#define AGC_CTRL0_MODE_DEFAULT (_AGC_CTRL0_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_MODE_CONT (_AGC_CTRL0_MODE_CONT << 8) /**< Shifted mode CONT for AGC_CTRL0 */ +#define AGC_CTRL0_MODE_LOCKPREDET (_AGC_CTRL0_MODE_LOCKPREDET << 8) /**< Shifted mode LOCKPREDET for AGC_CTRL0 */ +#define AGC_CTRL0_MODE_LOCKFRAMEDET (_AGC_CTRL0_MODE_LOCKFRAMEDET << 8) /**< Shifted mode LOCKFRAMEDET for AGC_CTRL0 */ +#define AGC_CTRL0_MODE_LOCKDSA (_AGC_CTRL0_MODE_LOCKDSA << 8) /**< Shifted mode LOCKDSA for AGC_CTRL0 */ +#define _AGC_CTRL0_RSSISHIFT_SHIFT 11 /**< Shift value for AGC_RSSISHIFT */ +#define _AGC_CTRL0_RSSISHIFT_MASK 0x7F800UL /**< Bit mask for AGC_RSSISHIFT */ +#define _AGC_CTRL0_RSSISHIFT_DEFAULT 0x0000004EUL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_RSSISHIFT_DEFAULT (_AGC_CTRL0_RSSISHIFT_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISCFLOOPADJ (0x1UL << 19) /**< Disable gain adjustment by CFLOOP */ +#define _AGC_CTRL0_DISCFLOOPADJ_SHIFT 19 /**< Shift value for AGC_DISCFLOOPADJ */ +#define _AGC_CTRL0_DISCFLOOPADJ_MASK 0x80000UL /**< Bit mask for AGC_DISCFLOOPADJ */ +#define _AGC_CTRL0_DISCFLOOPADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISCFLOOPADJ_DEFAULT (_AGC_CTRL0_DISCFLOOPADJ_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_CFLOOPNFADJ (0x1UL << 20) /**< Enable NF correction term in SL */ +#define _AGC_CTRL0_CFLOOPNFADJ_SHIFT 20 /**< Shift value for AGC_CFLOOPNFADJ */ +#define _AGC_CTRL0_CFLOOPNFADJ_MASK 0x100000UL /**< Bit mask for AGC_CFLOOPNFADJ */ +#define _AGC_CTRL0_CFLOOPNFADJ_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_CFLOOPNFADJ_DEFAULT (_AGC_CTRL0_CFLOOPNFADJ_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_CFLOOPNEWCALC (0x1UL << 21) /**< Enable new wanted gain calculation in SL */ +#define _AGC_CTRL0_CFLOOPNEWCALC_SHIFT 21 /**< Shift value for AGC_CFLOOPNEWCALC */ +#define _AGC_CTRL0_CFLOOPNEWCALC_MASK 0x200000UL /**< Bit mask for AGC_CFLOOPNEWCALC */ +#define _AGC_CTRL0_CFLOOPNEWCALC_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_CFLOOPNEWCALC_DEFAULT (_AGC_CTRL0_CFLOOPNEWCALC_DEFAULT << 21) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISRESETCHPWR (0x1UL << 22) /**< Disable Reset of CHPWR */ +#define _AGC_CTRL0_DISRESETCHPWR_SHIFT 22 /**< Shift value for AGC_DISRESETCHPWR */ +#define _AGC_CTRL0_DISRESETCHPWR_MASK 0x400000UL /**< Bit mask for AGC_DISRESETCHPWR */ +#define _AGC_CTRL0_DISRESETCHPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISRESETCHPWR_DEFAULT (_AGC_CTRL0_DISRESETCHPWR_DEFAULT << 22) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_ADCATTENMODE (0x1UL << 23) /**< ADC Attenuator mode */ +#define _AGC_CTRL0_ADCATTENMODE_SHIFT 23 /**< Shift value for AGC_ADCATTENMODE */ +#define _AGC_CTRL0_ADCATTENMODE_MASK 0x800000UL /**< Bit mask for AGC_ADCATTENMODE */ +#define _AGC_CTRL0_ADCATTENMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define _AGC_CTRL0_ADCATTENMODE_DISABLE 0x00000000UL /**< Mode DISABLE for AGC_CTRL0 */ +#define _AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN 0x00000001UL /**< Mode NOTMAXGAIN for AGC_CTRL0 */ +#define AGC_CTRL0_ADCATTENMODE_DEFAULT (_AGC_CTRL0_ADCATTENMODE_DEFAULT << 23) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_ADCATTENMODE_DISABLE (_AGC_CTRL0_ADCATTENMODE_DISABLE << 23) /**< Shifted mode DISABLE for AGC_CTRL0 */ +#define AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN (_AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN << 23) /**< Shifted mode NOTMAXGAIN for AGC_CTRL0 */ +#define AGC_CTRL0_FENOTCHMODESEL (0x1UL << 24) /**< FE notch mode select */ +#define _AGC_CTRL0_FENOTCHMODESEL_SHIFT 24 /**< Shift value for AGC_FENOTCHMODESEL */ +#define _AGC_CTRL0_FENOTCHMODESEL_MASK 0x1000000UL /**< Bit mask for AGC_FENOTCHMODESEL */ +#define _AGC_CTRL0_FENOTCHMODESEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define _AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT 0x00000000UL /**< Mode FENOTCHFILT for AGC_CTRL0 */ +#define _AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN 0x00000001UL /**< Mode FENOTCHATTN for AGC_CTRL0 */ +#define AGC_CTRL0_FENOTCHMODESEL_DEFAULT (_AGC_CTRL0_FENOTCHMODESEL_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT (_AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT << 24) /**< Shifted mode FENOTCHFILT for AGC_CTRL0 */ +#define AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN (_AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN << 24) /**< Shifted mode FENOTCHATTN for AGC_CTRL0 */ +#define _AGC_CTRL0_ADCATTENCODE_SHIFT 25 /**< Shift value for AGC_ADCATTENCODE */ +#define _AGC_CTRL0_ADCATTENCODE_MASK 0x6000000UL /**< Bit mask for AGC_ADCATTENCODE */ +#define _AGC_CTRL0_ADCATTENCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_ADCATTENCODE_DEFAULT (_AGC_CTRL0_ADCATTENCODE_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_ENRSSIRESET (0x1UL << 27) /**< Enables reset of RSSI and CCA */ +#define _AGC_CTRL0_ENRSSIRESET_SHIFT 27 /**< Shift value for AGC_ENRSSIRESET */ +#define _AGC_CTRL0_ENRSSIRESET_MASK 0x8000000UL /**< Bit mask for AGC_ENRSSIRESET */ +#define _AGC_CTRL0_ENRSSIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_ENRSSIRESET_DEFAULT (_AGC_CTRL0_ENRSSIRESET_DEFAULT << 27) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DSADISCFLOOP (0x1UL << 28) /**< Disable channel filter loop */ +#define _AGC_CTRL0_DSADISCFLOOP_SHIFT 28 /**< Shift value for AGC_DSADISCFLOOP */ +#define _AGC_CTRL0_DSADISCFLOOP_MASK 0x10000000UL /**< Bit mask for AGC_DSADISCFLOOP */ +#define _AGC_CTRL0_DSADISCFLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DSADISCFLOOP_DEFAULT (_AGC_CTRL0_DSADISCFLOOP_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISPNGAINUP (0x1UL << 29) /**< Disable PN gain increase */ +#define _AGC_CTRL0_DISPNGAINUP_SHIFT 29 /**< Shift value for AGC_DISPNGAINUP */ +#define _AGC_CTRL0_DISPNGAINUP_MASK 0x20000000UL /**< Bit mask for AGC_DISPNGAINUP */ +#define _AGC_CTRL0_DISPNGAINUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISPNGAINUP_DEFAULT (_AGC_CTRL0_DISPNGAINUP_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISPNDWNCOMP (0x1UL << 30) /**< Disable PN gain decrease compensation */ +#define _AGC_CTRL0_DISPNDWNCOMP_SHIFT 30 /**< Shift value for AGC_DISPNDWNCOMP */ +#define _AGC_CTRL0_DISPNDWNCOMP_MASK 0x40000000UL /**< Bit mask for AGC_DISPNDWNCOMP */ +#define _AGC_CTRL0_DISPNDWNCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_DISPNDWNCOMP_DEFAULT (_AGC_CTRL0_DISPNDWNCOMP_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_AGCRST (0x1UL << 31) /**< AGC reset */ +#define _AGC_CTRL0_AGCRST_SHIFT 31 /**< Shift value for AGC_AGCRST */ +#define _AGC_CTRL0_AGCRST_MASK 0x80000000UL /**< Bit mask for AGC_AGCRST */ +#define _AGC_CTRL0_AGCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */ +#define AGC_CTRL0_AGCRST_DEFAULT (_AGC_CTRL0_AGCRST_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL0 */ + +/* Bit fields for AGC CTRL1 */ +#define _AGC_CTRL1_RESETVALUE 0x00001300UL /**< Default value for AGC_CTRL1 */ +#define _AGC_CTRL1_MASK 0x0007FFFFUL /**< Mask for AGC_CTRL1 */ +#define _AGC_CTRL1_CCATHRSH_SHIFT 0 /**< Shift value for AGC_CCATHRSH */ +#define _AGC_CTRL1_CCATHRSH_MASK 0xFFUL /**< Bit mask for AGC_CCATHRSH */ +#define _AGC_CTRL1_CCATHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_CCATHRSH_DEFAULT (_AGC_CTRL1_CCATHRSH_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL1 */ +#define _AGC_CTRL1_RSSIPERIOD_SHIFT 8 /**< Shift value for AGC_RSSIPERIOD */ +#define _AGC_CTRL1_RSSIPERIOD_MASK 0xF00UL /**< Bit mask for AGC_RSSIPERIOD */ +#define _AGC_CTRL1_RSSIPERIOD_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_RSSIPERIOD_DEFAULT (_AGC_CTRL1_RSSIPERIOD_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL1 */ +#define _AGC_CTRL1_PWRPERIOD_SHIFT 12 /**< Shift value for AGC_PWRPERIOD */ +#define _AGC_CTRL1_PWRPERIOD_MASK 0x7000UL /**< Bit mask for AGC_PWRPERIOD */ +#define _AGC_CTRL1_PWRPERIOD_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_PWRPERIOD_DEFAULT (_AGC_CTRL1_PWRPERIOD_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE_SHIFT 15 /**< Shift value for AGC_CCAMODE */ +#define _AGC_CTRL1_CCAMODE_MASK 0x18000UL /**< Bit mask for AGC_CCAMODE */ +#define _AGC_CTRL1_CCAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE_MODE1 0x00000000UL /**< Mode MODE1 for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE_MODE2 0x00000001UL /**< Mode MODE2 for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE_MODE3 0x00000002UL /**< Mode MODE3 for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE_MODE4 0x00000003UL /**< Mode MODE4 for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE_DEFAULT (_AGC_CTRL1_CCAMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE_MODE1 (_AGC_CTRL1_CCAMODE_MODE1 << 15) /**< Shifted mode MODE1 for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE_MODE2 (_AGC_CTRL1_CCAMODE_MODE2 << 15) /**< Shifted mode MODE2 for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE_MODE3 (_AGC_CTRL1_CCAMODE_MODE3 << 15) /**< Shifted mode MODE3 for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE_MODE4 (_AGC_CTRL1_CCAMODE_MODE4 << 15) /**< Shifted mode MODE4 for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE3LOGIC (0x1UL << 17) /**< Select mode3 logic */ +#define _AGC_CTRL1_CCAMODE3LOGIC_SHIFT 17 /**< Shift value for AGC_CCAMODE3LOGIC */ +#define _AGC_CTRL1_CCAMODE3LOGIC_MASK 0x20000UL /**< Bit mask for AGC_CCAMODE3LOGIC */ +#define _AGC_CTRL1_CCAMODE3LOGIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE3LOGIC_OR 0x00000000UL /**< Mode OR for AGC_CTRL1 */ +#define _AGC_CTRL1_CCAMODE3LOGIC_AND 0x00000001UL /**< Mode AND for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE3LOGIC_DEFAULT (_AGC_CTRL1_CCAMODE3LOGIC_DEFAULT << 17) /**< Shifted mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE3LOGIC_OR (_AGC_CTRL1_CCAMODE3LOGIC_OR << 17) /**< Shifted mode OR for AGC_CTRL1 */ +#define AGC_CTRL1_CCAMODE3LOGIC_AND (_AGC_CTRL1_CCAMODE3LOGIC_AND << 17) /**< Shifted mode AND for AGC_CTRL1 */ +#define AGC_CTRL1_CCASWCTRL (0x1UL << 18) /**< SW control over CCA */ +#define _AGC_CTRL1_CCASWCTRL_SHIFT 18 /**< Shift value for AGC_CCASWCTRL */ +#define _AGC_CTRL1_CCASWCTRL_MASK 0x40000UL /**< Bit mask for AGC_CCASWCTRL */ +#define _AGC_CTRL1_CCASWCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */ +#define AGC_CTRL1_CCASWCTRL_DEFAULT (_AGC_CTRL1_CCASWCTRL_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL1 */ + +/* Bit fields for AGC CTRL2 */ +#define _AGC_CTRL2_RESETVALUE 0x0000610AUL /**< Default value for AGC_CTRL2 */ +#define _AGC_CTRL2_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL2 */ +#define AGC_CTRL2_DMASEL (0x1UL << 0) /**< DMA select */ +#define _AGC_CTRL2_DMASEL_SHIFT 0 /**< Shift value for AGC_DMASEL */ +#define _AGC_CTRL2_DMASEL_MASK 0x1UL /**< Bit mask for AGC_DMASEL */ +#define _AGC_CTRL2_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_DMASEL_RSSI 0x00000000UL /**< Mode RSSI for AGC_CTRL2 */ +#define _AGC_CTRL2_DMASEL_GAIN 0x00000001UL /**< Mode GAIN for AGC_CTRL2 */ +#define AGC_CTRL2_DMASEL_DEFAULT (_AGC_CTRL2_DMASEL_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_DMASEL_RSSI (_AGC_CTRL2_DMASEL_RSSI << 0) /**< Shifted mode RSSI for AGC_CTRL2 */ +#define AGC_CTRL2_DMASEL_GAIN (_AGC_CTRL2_DMASEL_GAIN << 0) /**< Shifted mode GAIN for AGC_CTRL2 */ +#define AGC_CTRL2_SAFEMODE (0x1UL << 1) /**< AGC safe mode */ +#define _AGC_CTRL2_SAFEMODE_SHIFT 1 /**< Shift value for AGC_SAFEMODE */ +#define _AGC_CTRL2_SAFEMODE_MASK 0x2UL /**< Bit mask for AGC_SAFEMODE */ +#define _AGC_CTRL2_SAFEMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_SAFEMODE_DEFAULT (_AGC_CTRL2_SAFEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_SAFEMODETHD_SHIFT 2 /**< Shift value for AGC_SAFEMODETHD */ +#define _AGC_CTRL2_SAFEMODETHD_MASK 0x1CUL /**< Bit mask for AGC_SAFEMODETHD */ +#define _AGC_CTRL2_SAFEMODETHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_SAFEMODETHD_DEFAULT (_AGC_CTRL2_SAFEMODETHD_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_REHICNTTHD_SHIFT 5 /**< Shift value for AGC_REHICNTTHD */ +#define _AGC_CTRL2_REHICNTTHD_MASK 0x1FE0UL /**< Bit mask for AGC_REHICNTTHD */ +#define _AGC_CTRL2_REHICNTTHD_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_REHICNTTHD_DEFAULT (_AGC_CTRL2_REHICNTTHD_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_RELOTHD_SHIFT 13 /**< Shift value for AGC_RELOTHD */ +#define _AGC_CTRL2_RELOTHD_MASK 0xE000UL /**< Bit mask for AGC_RELOTHD */ +#define _AGC_CTRL2_RELOTHD_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_RELOTHD_DEFAULT (_AGC_CTRL2_RELOTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_RELBYCHPWR_SHIFT 16 /**< Shift value for AGC_RELBYCHPWR */ +#define _AGC_CTRL2_RELBYCHPWR_MASK 0x30000UL /**< Bit mask for AGC_RELBYCHPWR */ +#define _AGC_CTRL2_RELBYCHPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_RELBYCHPWR_LO_CNT 0x00000000UL /**< Mode LO_CNT for AGC_CTRL2 */ +#define _AGC_CTRL2_RELBYCHPWR_PWR 0x00000001UL /**< Mode PWR for AGC_CTRL2 */ +#define _AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR 0x00000002UL /**< Mode LO_CNT_PWR for AGC_CTRL2 */ +#define _AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR 0x00000003UL /**< Mode LO_CNT_AND_PWR for AGC_CTRL2 */ +#define AGC_CTRL2_RELBYCHPWR_DEFAULT (_AGC_CTRL2_RELBYCHPWR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_RELBYCHPWR_LO_CNT (_AGC_CTRL2_RELBYCHPWR_LO_CNT << 16) /**< Shifted mode LO_CNT for AGC_CTRL2 */ +#define AGC_CTRL2_RELBYCHPWR_PWR (_AGC_CTRL2_RELBYCHPWR_PWR << 16) /**< Shifted mode PWR for AGC_CTRL2 */ +#define AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR (_AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR << 16) /**< Shifted mode LO_CNT_PWR for AGC_CTRL2 */ +#define AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR (_AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR << 16) /**< Shifted mode LO_CNT_AND_PWR for AGC_CTRL2 */ +#define _AGC_CTRL2_RELTARGETPWR_SHIFT 18 /**< Shift value for AGC_RELTARGETPWR */ +#define _AGC_CTRL2_RELTARGETPWR_MASK 0x3FC0000UL /**< Bit mask for AGC_RELTARGETPWR */ +#define _AGC_CTRL2_RELTARGETPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_RELTARGETPWR_DEFAULT (_AGC_CTRL2_RELTARGETPWR_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define _AGC_CTRL2_RSSICCASUB_SHIFT 26 /**< Shift value for AGC_RSSICCASUB */ +#define _AGC_CTRL2_RSSICCASUB_MASK 0x1C000000UL /**< Bit mask for AGC_RSSICCASUB */ +#define _AGC_CTRL2_RSSICCASUB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_RSSICCASUB_DEFAULT (_AGC_CTRL2_RSSICCASUB_DEFAULT << 26) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_DEBCNTRST (0x1UL << 29) /**< Debonce CNT Reset MODE */ +#define _AGC_CTRL2_DEBCNTRST_SHIFT 29 /**< Shift value for AGC_DEBCNTRST */ +#define _AGC_CTRL2_DEBCNTRST_MASK 0x20000000UL /**< Bit mask for AGC_DEBCNTRST */ +#define _AGC_CTRL2_DEBCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_DEBCNTRST_DEFAULT (_AGC_CTRL2_DEBCNTRST_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_PRSDEBUGEN (0x1UL << 30) /**< PRS Debug Enable */ +#define _AGC_CTRL2_PRSDEBUGEN_SHIFT 30 /**< Shift value for AGC_PRSDEBUGEN */ +#define _AGC_CTRL2_PRSDEBUGEN_MASK 0x40000000UL /**< Bit mask for AGC_PRSDEBUGEN */ +#define _AGC_CTRL2_PRSDEBUGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_PRSDEBUGEN_DEFAULT (_AGC_CTRL2_PRSDEBUGEN_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_DISRFPKD (0x1UL << 31) /**< Disable RF PEAKDET */ +#define _AGC_CTRL2_DISRFPKD_SHIFT 31 /**< Shift value for AGC_DISRFPKD */ +#define _AGC_CTRL2_DISRFPKD_MASK 0x80000000UL /**< Bit mask for AGC_DISRFPKD */ +#define _AGC_CTRL2_DISRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */ +#define AGC_CTRL2_DISRFPKD_DEFAULT (_AGC_CTRL2_DISRFPKD_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL2 */ + +/* Bit fields for AGC CTRL3 */ +#define _AGC_CTRL3_RESETVALUE 0x5140A800UL /**< Default value for AGC_CTRL3 */ +#define _AGC_CTRL3_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL3 */ +#define AGC_CTRL3_IFPKDDEB (0x1UL << 0) /**< IF PEAKDET debounce mode enable */ +#define _AGC_CTRL3_IFPKDDEB_SHIFT 0 /**< Shift value for AGC_IFPKDDEB */ +#define _AGC_CTRL3_IFPKDDEB_MASK 0x1UL /**< Bit mask for AGC_IFPKDDEB */ +#define _AGC_CTRL3_IFPKDDEB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_IFPKDDEB_DEFAULT (_AGC_CTRL3_IFPKDDEB_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_IFPKDDEBTHD_SHIFT 1 /**< Shift value for AGC_IFPKDDEBTHD */ +#define _AGC_CTRL3_IFPKDDEBTHD_MASK 0x6UL /**< Bit mask for AGC_IFPKDDEBTHD */ +#define _AGC_CTRL3_IFPKDDEBTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_IFPKDDEBTHD_DEFAULT (_AGC_CTRL3_IFPKDDEBTHD_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_IFPKDDEBPRD_SHIFT 3 /**< Shift value for AGC_IFPKDDEBPRD */ +#define _AGC_CTRL3_IFPKDDEBPRD_MASK 0x1F8UL /**< Bit mask for AGC_IFPKDDEBPRD */ +#define _AGC_CTRL3_IFPKDDEBPRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_IFPKDDEBPRD_DEFAULT (_AGC_CTRL3_IFPKDDEBPRD_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_IFPKDDEBRST_SHIFT 9 /**< Shift value for AGC_IFPKDDEBRST */ +#define _AGC_CTRL3_IFPKDDEBRST_MASK 0x1E00UL /**< Bit mask for AGC_IFPKDDEBRST */ +#define _AGC_CTRL3_IFPKDDEBRST_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_IFPKDDEBRST_DEFAULT (_AGC_CTRL3_IFPKDDEBRST_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_RFPKDDEB (0x1UL << 13) /**< RF PEAKDET debounce mode enable */ +#define _AGC_CTRL3_RFPKDDEB_SHIFT 13 /**< Shift value for AGC_RFPKDDEB */ +#define _AGC_CTRL3_RFPKDDEB_MASK 0x2000UL /**< Bit mask for AGC_RFPKDDEB */ +#define _AGC_CTRL3_RFPKDDEB_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_RFPKDDEB_DEFAULT (_AGC_CTRL3_RFPKDDEB_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_RFPKDDEBTHD_SHIFT 14 /**< Shift value for AGC_RFPKDDEBTHD */ +#define _AGC_CTRL3_RFPKDDEBTHD_MASK 0x7C000UL /**< Bit mask for AGC_RFPKDDEBTHD */ +#define _AGC_CTRL3_RFPKDDEBTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_RFPKDDEBTHD_DEFAULT (_AGC_CTRL3_RFPKDDEBTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_RFPKDDEBPRD_SHIFT 19 /**< Shift value for AGC_RFPKDDEBPRD */ +#define _AGC_CTRL3_RFPKDDEBPRD_MASK 0x7F80000UL /**< Bit mask for AGC_RFPKDDEBPRD */ +#define _AGC_CTRL3_RFPKDDEBPRD_DEFAULT 0x00000028UL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_RFPKDDEBPRD_DEFAULT (_AGC_CTRL3_RFPKDDEBPRD_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL3 */ +#define _AGC_CTRL3_RFPKDDEBRST_SHIFT 27 /**< Shift value for AGC_RFPKDDEBRST */ +#define _AGC_CTRL3_RFPKDDEBRST_MASK 0xF8000000UL /**< Bit mask for AGC_RFPKDDEBRST */ +#define _AGC_CTRL3_RFPKDDEBRST_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_CTRL3 */ +#define AGC_CTRL3_RFPKDDEBRST_DEFAULT (_AGC_CTRL3_RFPKDDEBRST_DEFAULT << 27) /**< Shifted mode DEFAULT for AGC_CTRL3 */ + +/* Bit fields for AGC CTRL4 */ +#define _AGC_CTRL4_RESETVALUE 0x0000000EUL /**< Default value for AGC_CTRL4 */ +#define _AGC_CTRL4_MASK 0xFF80FFFFUL /**< Mask for AGC_CTRL4 */ +#define _AGC_CTRL4_PERIODRFPKD_SHIFT 0 /**< Shift value for AGC_PERIODRFPKD */ +#define _AGC_CTRL4_PERIODRFPKD_MASK 0xFFFFUL /**< Bit mask for AGC_PERIODRFPKD */ +#define _AGC_CTRL4_PERIODRFPKD_DEFAULT 0x0000000EUL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_PERIODRFPKD_DEFAULT (_AGC_CTRL4_PERIODRFPKD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_DISRFPKDCNTRST (0x1UL << 23) /**< Disable PGOCELOT-5333 fix */ +#define _AGC_CTRL4_DISRFPKDCNTRST_SHIFT 23 /**< Shift value for AGC_DISRFPKDCNTRST */ +#define _AGC_CTRL4_DISRFPKDCNTRST_MASK 0x800000UL /**< Bit mask for AGC_DISRFPKDCNTRST */ +#define _AGC_CTRL4_DISRFPKDCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_DISRFPKDCNTRST_DEFAULT (_AGC_CTRL4_DISRFPKDCNTRST_DEFAULT << 23) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_DISRSTCONDI (0x1UL << 24) /**< Disable PGOCELOT-5333 fix */ +#define _AGC_CTRL4_DISRSTCONDI_SHIFT 24 /**< Shift value for AGC_DISRSTCONDI */ +#define _AGC_CTRL4_DISRSTCONDI_MASK 0x1000000UL /**< Bit mask for AGC_DISRSTCONDI */ +#define _AGC_CTRL4_DISRSTCONDI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_DISRSTCONDI_DEFAULT (_AGC_CTRL4_DISRSTCONDI_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define _AGC_CTRL4_RFPKDPRDGEAR_SHIFT 25 /**< Shift value for AGC_RFPKDPRDGEAR */ +#define _AGC_CTRL4_RFPKDPRDGEAR_MASK 0xE000000UL /**< Bit mask for AGC_RFPKDPRDGEAR */ +#define _AGC_CTRL4_RFPKDPRDGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDPRDGEAR_DEFAULT (_AGC_CTRL4_RFPKDPRDGEAR_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDSYNCSEL (0x1UL << 28) /**< SYNC RF PKD OUTPUT SELECT */ +#define _AGC_CTRL4_RFPKDSYNCSEL_SHIFT 28 /**< Shift value for AGC_RFPKDSYNCSEL */ +#define _AGC_CTRL4_RFPKDSYNCSEL_MASK 0x10000000UL /**< Bit mask for AGC_RFPKDSYNCSEL */ +#define _AGC_CTRL4_RFPKDSYNCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDSYNCSEL_DEFAULT (_AGC_CTRL4_RFPKDSYNCSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDSEL (0x1UL << 29) /**< RF PKD OUTPUT SELECT */ +#define _AGC_CTRL4_RFPKDSEL_SHIFT 29 /**< Shift value for AGC_RFPKDSEL */ +#define _AGC_CTRL4_RFPKDSEL_MASK 0x20000000UL /**< Bit mask for AGC_RFPKDSEL */ +#define _AGC_CTRL4_RFPKDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDSEL_DEFAULT (_AGC_CTRL4_RFPKDSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_FRZPKDEN (0x1UL << 30) /**< PKD Freeze Enable */ +#define _AGC_CTRL4_FRZPKDEN_SHIFT 30 /**< Shift value for AGC_FRZPKDEN */ +#define _AGC_CTRL4_FRZPKDEN_MASK 0x40000000UL /**< Bit mask for AGC_FRZPKDEN */ +#define _AGC_CTRL4_FRZPKDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_FRZPKDEN_DEFAULT (_AGC_CTRL4_FRZPKDEN_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDCNTEN (0x1UL << 31) /**< Counter-based RFPKD Enable */ +#define _AGC_CTRL4_RFPKDCNTEN_SHIFT 31 /**< Shift value for AGC_RFPKDCNTEN */ +#define _AGC_CTRL4_RFPKDCNTEN_MASK 0x80000000UL /**< Bit mask for AGC_RFPKDCNTEN */ +#define _AGC_CTRL4_RFPKDCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */ +#define AGC_CTRL4_RFPKDCNTEN_DEFAULT (_AGC_CTRL4_RFPKDCNTEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL4 */ + +/* Bit fields for AGC CTRL5 */ +#define _AGC_CTRL5_RESETVALUE 0x00000000UL /**< Default value for AGC_CTRL5 */ +#define _AGC_CTRL5_MASK 0xC0FFFFFFUL /**< Mask for AGC_CTRL5 */ +#define _AGC_CTRL5_PNUPDISTHD_SHIFT 0 /**< Shift value for AGC_PNUPDISTHD */ +#define _AGC_CTRL5_PNUPDISTHD_MASK 0xFFFUL /**< Bit mask for AGC_PNUPDISTHD */ +#define _AGC_CTRL5_PNUPDISTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_PNUPDISTHD_DEFAULT (_AGC_CTRL5_PNUPDISTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL5 */ +#define _AGC_CTRL5_PNUPRELTHD_SHIFT 12 /**< Shift value for AGC_PNUPRELTHD */ +#define _AGC_CTRL5_PNUPRELTHD_MASK 0xFFF000UL /**< Bit mask for AGC_PNUPRELTHD */ +#define _AGC_CTRL5_PNUPRELTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_PNUPRELTHD_DEFAULT (_AGC_CTRL5_PNUPRELTHD_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_SEQPNUPALLOW (0x1UL << 30) /**< SEQ Set PN GAIN UP ALLOW */ +#define _AGC_CTRL5_SEQPNUPALLOW_SHIFT 30 /**< Shift value for AGC_SEQPNUPALLOW */ +#define _AGC_CTRL5_SEQPNUPALLOW_MASK 0x40000000UL /**< Bit mask for AGC_SEQPNUPALLOW */ +#define _AGC_CTRL5_SEQPNUPALLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_SEQPNUPALLOW_DEFAULT (_AGC_CTRL5_SEQPNUPALLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_SEQRFPKDEN (0x1UL << 31) /**< SEQ-based RFPKD Enable */ +#define _AGC_CTRL5_SEQRFPKDEN_SHIFT 31 /**< Shift value for AGC_SEQRFPKDEN */ +#define _AGC_CTRL5_SEQRFPKDEN_MASK 0x80000000UL /**< Bit mask for AGC_SEQRFPKDEN */ +#define _AGC_CTRL5_SEQRFPKDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */ +#define AGC_CTRL5_SEQRFPKDEN_DEFAULT (_AGC_CTRL5_SEQRFPKDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL5 */ + +/* Bit fields for AGC CTRL6 */ +#define _AGC_CTRL6_RESETVALUE 0x0003AAA8UL /**< Default value for AGC_CTRL6 */ +#define _AGC_CTRL6_MASK 0x7FFFFFFFUL /**< Mask for AGC_CTRL6 */ +#define _AGC_CTRL6_DUALRFPKDDEC_SHIFT 0 /**< Shift value for AGC_DUALRFPKDDEC */ +#define _AGC_CTRL6_DUALRFPKDDEC_MASK 0x3FFFFUL /**< Bit mask for AGC_DUALRFPKDDEC */ +#define _AGC_CTRL6_DUALRFPKDDEC_DEFAULT 0x0003AAA8UL /**< Mode DEFAULT for AGC_CTRL6 */ +#define AGC_CTRL6_DUALRFPKDDEC_DEFAULT (_AGC_CTRL6_DUALRFPKDDEC_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL6 */ +#define AGC_CTRL6_ENDUALRFPKD (0x1UL << 18) /**< Enable dual RFPKD */ +#define _AGC_CTRL6_ENDUALRFPKD_SHIFT 18 /**< Shift value for AGC_ENDUALRFPKD */ +#define _AGC_CTRL6_ENDUALRFPKD_MASK 0x40000UL /**< Bit mask for AGC_ENDUALRFPKD */ +#define _AGC_CTRL6_ENDUALRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL6 */ +#define AGC_CTRL6_ENDUALRFPKD_DEFAULT (_AGC_CTRL6_ENDUALRFPKD_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL6 */ +#define _AGC_CTRL6_GAINDETTHD_SHIFT 19 /**< Shift value for AGC_GAINDETTHD */ +#define _AGC_CTRL6_GAINDETTHD_MASK 0x7FF80000UL /**< Bit mask for AGC_GAINDETTHD */ +#define _AGC_CTRL6_GAINDETTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL6 */ +#define AGC_CTRL6_GAINDETTHD_DEFAULT (_AGC_CTRL6_GAINDETTHD_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL6 */ + +/* Bit fields for AGC CTRL7 */ +#define _AGC_CTRL7_RESETVALUE 0x00000000UL /**< Default value for AGC_CTRL7 */ +#define _AGC_CTRL7_MASK 0x01FFFFFFUL /**< Mask for AGC_CTRL7 */ +#define _AGC_CTRL7_SUBDEN_SHIFT 0 /**< Shift value for AGC_SUBDEN */ +#define _AGC_CTRL7_SUBDEN_MASK 0xFFUL /**< Bit mask for AGC_SUBDEN */ +#define _AGC_CTRL7_SUBDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */ +#define AGC_CTRL7_SUBDEN_DEFAULT (_AGC_CTRL7_SUBDEN_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL7 */ +#define _AGC_CTRL7_SUBINT_SHIFT 8 /**< Shift value for AGC_SUBINT */ +#define _AGC_CTRL7_SUBINT_MASK 0xFF00UL /**< Bit mask for AGC_SUBINT */ +#define _AGC_CTRL7_SUBINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */ +#define AGC_CTRL7_SUBINT_DEFAULT (_AGC_CTRL7_SUBINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL7 */ +#define _AGC_CTRL7_SUBNUM_SHIFT 16 /**< Shift value for AGC_SUBNUM */ +#define _AGC_CTRL7_SUBNUM_MASK 0xFF0000UL /**< Bit mask for AGC_SUBNUM */ +#define _AGC_CTRL7_SUBNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */ +#define AGC_CTRL7_SUBNUM_DEFAULT (_AGC_CTRL7_SUBNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_CTRL7 */ +#define AGC_CTRL7_SUBPERIOD (0x1UL << 24) /**< Subperiod */ +#define _AGC_CTRL7_SUBPERIOD_SHIFT 24 /**< Shift value for AGC_SUBPERIOD */ +#define _AGC_CTRL7_SUBPERIOD_MASK 0x1000000UL /**< Bit mask for AGC_SUBPERIOD */ +#define _AGC_CTRL7_SUBPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */ +#define AGC_CTRL7_SUBPERIOD_DEFAULT (_AGC_CTRL7_SUBPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL7 */ + +/* Bit fields for AGC RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_RESETVALUE 0x00000000UL /**< Default value for AGC_RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_MASK 0x3FFFFFFFUL /**< Mask for AGC_RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_POSSTEPTHR_SHIFT 0 /**< Shift value for AGC_POSSTEPTHR */ +#define _AGC_RSSISTEPTHR_POSSTEPTHR_MASK 0xFFUL /**< Bit mask for AGC_POSSTEPTHR */ +#define _AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT (_AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_NEGSTEPTHR_SHIFT 8 /**< Shift value for AGC_NEGSTEPTHR */ +#define _AGC_RSSISTEPTHR_NEGSTEPTHR_MASK 0xFF00UL /**< Bit mask for AGC_NEGSTEPTHR */ +#define _AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT (_AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_STEPPER (0x1UL << 16) /**< Step Period */ +#define _AGC_RSSISTEPTHR_STEPPER_SHIFT 16 /**< Shift value for AGC_STEPPER */ +#define _AGC_RSSISTEPTHR_STEPPER_MASK 0x10000UL /**< Bit mask for AGC_STEPPER */ +#define _AGC_RSSISTEPTHR_STEPPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_STEPPER_DEFAULT (_AGC_RSSISTEPTHR_STEPPER_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_SHIFT 17 /**< Shift value for AGC_DEMODRESTARTPER */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_MASK 0x1E0000UL /**< Bit mask for AGC_DEMODRESTARTPER */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT (_AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT << 17) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_SHIFT 21 /**< Shift value for AGC_DEMODRESTARTTHR */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_MASK 0x1FE00000UL /**< Bit mask for AGC_DEMODRESTARTTHR */ +#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT (_AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT << 21) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_RSSIFAST (0x1UL << 29) /**< RSSI fast startup */ +#define _AGC_RSSISTEPTHR_RSSIFAST_SHIFT 29 /**< Shift value for AGC_RSSIFAST */ +#define _AGC_RSSISTEPTHR_RSSIFAST_MASK 0x20000000UL /**< Bit mask for AGC_RSSIFAST */ +#define _AGC_RSSISTEPTHR_RSSIFAST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */ +#define AGC_RSSISTEPTHR_RSSIFAST_DEFAULT (_AGC_RSSISTEPTHR_RSSIFAST_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */ + +/* Bit fields for AGC IF */ +#define _AGC_IF_RESETVALUE 0x00000000UL /**< Default value for AGC_IF */ +#define _AGC_IF_MASK 0x00007F7DUL /**< Mask for AGC_IF */ +#define AGC_IF_RSSIVALID (0x1UL << 0) /**< RSSI Value is Valid */ +#define _AGC_IF_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */ +#define _AGC_IF_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */ +#define _AGC_IF_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSIVALID_DEFAULT (_AGC_IF_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_CCA (0x1UL << 2) /**< Clear Channel Assessment */ +#define _AGC_IF_CCA_SHIFT 2 /**< Shift value for AGC_CCA */ +#define _AGC_IF_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */ +#define _AGC_IF_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_CCA_DEFAULT (_AGC_IF_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSIPOSSTEP (0x1UL << 3) /**< Positive RSSI Step Detected */ +#define _AGC_IF_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */ +#define _AGC_IF_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */ +#define _AGC_IF_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSIPOSSTEP_DEFAULT (_AGC_IF_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSINEGSTEP (0x1UL << 4) /**< Negative RSSI Step Detected */ +#define _AGC_IF_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */ +#define _AGC_IF_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */ +#define _AGC_IF_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSINEGSTEP_DEFAULT (_AGC_IF_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_SHORTRSSIPOSSTEP (0x1UL << 6) /**< Short-term Positive RSSI Step Detected */ +#define _AGC_IF_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_IF_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_IF_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_SHORTRSSIPOSSTEP_DEFAULT (_AGC_IF_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT TOMEOUT */ +#define _AGC_IF_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */ +#define _AGC_IF_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */ +#define _AGC_IF_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RFPKDPRDDONE_DEFAULT (_AGC_IF_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT TOMEOUT */ +#define _AGC_IF_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */ +#define _AGC_IF_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */ +#define _AGC_IF_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RFPKDCNTDONE_DEFAULT (_AGC_IF_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSIHIGH (0x1UL << 10) /**< RSSI high detected */ +#define _AGC_IF_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */ +#define _AGC_IF_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */ +#define _AGC_IF_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSIHIGH_DEFAULT (_AGC_IF_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSILOW (0x1UL << 11) /**< RSSI low detected */ +#define _AGC_IF_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */ +#define _AGC_IF_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */ +#define _AGC_IF_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_RSSILOW_DEFAULT (_AGC_IF_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_CCANODET (0x1UL << 12) /**< CCA Not Detected */ +#define _AGC_IF_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */ +#define _AGC_IF_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */ +#define _AGC_IF_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_CCANODET_DEFAULT (_AGC_IF_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_GAINBELOWGAINTHD (0x1UL << 13) /**< agc gain above threshold int */ +#define _AGC_IF_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */ +#define _AGC_IF_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */ +#define _AGC_IF_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_GAINBELOWGAINTHD_DEFAULT (_AGC_IF_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_IF */ +#define AGC_IF_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int */ +#define _AGC_IF_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */ +#define _AGC_IF_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */ +#define _AGC_IF_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */ +#define AGC_IF_GAINUPDATEFRZ_DEFAULT (_AGC_IF_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_IF */ + +/* Bit fields for AGC IEN */ +#define _AGC_IEN_RESETVALUE 0x00000000UL /**< Default value for AGC_IEN */ +#define _AGC_IEN_MASK 0x00007F7DUL /**< Mask for AGC_IEN */ +#define AGC_IEN_RSSIVALID (0x1UL << 0) /**< RSSIVALID Interrupt Enable */ +#define _AGC_IEN_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */ +#define _AGC_IEN_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */ +#define _AGC_IEN_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSIVALID_DEFAULT (_AGC_IEN_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_CCA (0x1UL << 2) /**< CCA Interrupt Enable */ +#define _AGC_IEN_CCA_SHIFT 2 /**< Shift value for AGC_CCA */ +#define _AGC_IEN_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */ +#define _AGC_IEN_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_CCA_DEFAULT (_AGC_IEN_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSIPOSSTEP (0x1UL << 3) /**< RSSIPOSSTEP Interrupt Enable */ +#define _AGC_IEN_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */ +#define _AGC_IEN_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */ +#define _AGC_IEN_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSIPOSSTEP_DEFAULT (_AGC_IEN_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSINEGSTEP (0x1UL << 4) /**< RSSINEGSTEP Interrupt Enable */ +#define _AGC_IEN_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */ +#define _AGC_IEN_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */ +#define _AGC_IEN_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSINEGSTEP_DEFAULT (_AGC_IEN_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_SHORTRSSIPOSSTEP (0x1UL << 6) /**< SHORTRSSIPOSSTEP Interrupt Enable */ +#define _AGC_IEN_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_IEN_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT (_AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT Interrupt Enable */ +#define _AGC_IEN_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */ +#define _AGC_IEN_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */ +#define _AGC_IEN_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RFPKDPRDDONE_DEFAULT (_AGC_IEN_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT Interrupt Enable */ +#define _AGC_IEN_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */ +#define _AGC_IEN_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */ +#define _AGC_IEN_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RFPKDCNTDONE_DEFAULT (_AGC_IEN_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSIHIGH (0x1UL << 10) /**< RSSIHIGH Interrupt Enable */ +#define _AGC_IEN_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */ +#define _AGC_IEN_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */ +#define _AGC_IEN_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSIHIGH_DEFAULT (_AGC_IEN_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSILOW (0x1UL << 11) /**< RSSILOW Interrupt Enable */ +#define _AGC_IEN_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */ +#define _AGC_IEN_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */ +#define _AGC_IEN_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_RSSILOW_DEFAULT (_AGC_IEN_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_CCANODET (0x1UL << 12) /**< CCANODET Interrupt Enable */ +#define _AGC_IEN_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */ +#define _AGC_IEN_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */ +#define _AGC_IEN_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_CCANODET_DEFAULT (_AGC_IEN_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_GAINBELOWGAINTHD (0x1UL << 13) /**< GAINBELOWGAINTHD Interrupt Enable */ +#define _AGC_IEN_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */ +#define _AGC_IEN_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */ +#define _AGC_IEN_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_GAINBELOWGAINTHD_DEFAULT (_AGC_IEN_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_IEN */ +#define AGC_IEN_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int Enable */ +#define _AGC_IEN_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */ +#define _AGC_IEN_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */ +#define _AGC_IEN_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */ +#define AGC_IEN_GAINUPDATEFRZ_DEFAULT (_AGC_IEN_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_IEN */ + +/* Bit fields for AGC GAINRANGE */ +#define _AGC_GAINRANGE_RESETVALUE 0x00813187UL /**< Default value for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_MASK 0x03FFFFFFUL /**< Mask for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_LNAINDEXBORDER_SHIFT 0 /**< Shift value for AGC_LNAINDEXBORDER */ +#define _AGC_GAINRANGE_LNAINDEXBORDER_MASK 0xFUL /**< Bit mask for AGC_LNAINDEXBORDER */ +#define _AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT (_AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_PGAINDEXBORDER_SHIFT 4 /**< Shift value for AGC_PGAINDEXBORDER */ +#define _AGC_GAINRANGE_PGAINDEXBORDER_MASK 0xF0UL /**< Bit mask for AGC_PGAINDEXBORDER */ +#define _AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT (_AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_GAININCSTEP_SHIFT 8 /**< Shift value for AGC_GAININCSTEP */ +#define _AGC_GAINRANGE_GAININCSTEP_MASK 0xF00UL /**< Bit mask for AGC_GAININCSTEP */ +#define _AGC_GAINRANGE_GAININCSTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_GAININCSTEP_DEFAULT (_AGC_GAINRANGE_GAININCSTEP_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_PNGAINSTEP_SHIFT 12 /**< Shift value for AGC_PNGAINSTEP */ +#define _AGC_GAINRANGE_PNGAINSTEP_MASK 0xF000UL /**< Bit mask for AGC_PNGAINSTEP */ +#define _AGC_GAINRANGE_PNGAINSTEP_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_PNGAINSTEP_DEFAULT (_AGC_GAINRANGE_PNGAINSTEP_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_LATCHEDHISTEP_SHIFT 16 /**< Shift value for AGC_LATCHEDHISTEP */ +#define _AGC_GAINRANGE_LATCHEDHISTEP_MASK 0xF0000UL /**< Bit mask for AGC_LATCHEDHISTEP */ +#define _AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT (_AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ +#define _AGC_GAINRANGE_HIPWRTHD_SHIFT 20 /**< Shift value for AGC_HIPWRTHD */ +#define _AGC_GAINRANGE_HIPWRTHD_MASK 0x3F00000UL /**< Bit mask for AGC_HIPWRTHD */ +#define _AGC_GAINRANGE_HIPWRTHD_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_GAINRANGE */ +#define AGC_GAINRANGE_HIPWRTHD_DEFAULT (_AGC_GAINRANGE_HIPWRTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_GAINRANGE */ + +/* Bit fields for AGC AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_RESETVALUE 0xD607000EUL /**< Default value for AGC_AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_MASK 0xFFFF01FFUL /**< Mask for AGC_AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_PERIODHI_SHIFT 0 /**< Shift value for AGC_PERIODHI */ +#define _AGC_AGCPERIOD0_PERIODHI_MASK 0x1FFUL /**< Bit mask for AGC_PERIODHI */ +#define _AGC_AGCPERIOD0_PERIODHI_DEFAULT 0x0000000EUL /**< Mode DEFAULT for AGC_AGCPERIOD0 */ +#define AGC_AGCPERIOD0_PERIODHI_DEFAULT (_AGC_AGCPERIOD0_PERIODHI_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_MAXHICNTTHD_SHIFT 16 /**< Shift value for AGC_MAXHICNTTHD */ +#define _AGC_AGCPERIOD0_MAXHICNTTHD_MASK 0xFF0000UL /**< Bit mask for AGC_MAXHICNTTHD */ +#define _AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_AGCPERIOD0 */ +#define AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT (_AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_SETTLETIMEIF_SHIFT 24 /**< Shift value for AGC_SETTLETIMEIF */ +#define _AGC_AGCPERIOD0_SETTLETIMEIF_MASK 0xF000000UL /**< Bit mask for AGC_SETTLETIMEIF */ +#define _AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_AGCPERIOD0 */ +#define AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT (_AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */ +#define _AGC_AGCPERIOD0_SETTLETIMERF_SHIFT 28 /**< Shift value for AGC_SETTLETIMERF */ +#define _AGC_AGCPERIOD0_SETTLETIMERF_MASK 0xF0000000UL /**< Bit mask for AGC_SETTLETIMERF */ +#define _AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT 0x0000000DUL /**< Mode DEFAULT for AGC_AGCPERIOD0 */ +#define AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT (_AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */ + +/* Bit fields for AGC AGCPERIOD1 */ +#define _AGC_AGCPERIOD1_RESETVALUE 0x00000037UL /**< Default value for AGC_AGCPERIOD1 */ +#define _AGC_AGCPERIOD1_MASK 0xFFFFFFFFUL /**< Mask for AGC_AGCPERIOD1 */ +#define _AGC_AGCPERIOD1_PERIODLOW_SHIFT 0 /**< Shift value for AGC_PERIODLOW */ +#define _AGC_AGCPERIOD1_PERIODLOW_MASK 0xFFFFFFFFUL /**< Bit mask for AGC_PERIODLOW */ +#define _AGC_AGCPERIOD1_PERIODLOW_DEFAULT 0x00000037UL /**< Mode DEFAULT for AGC_AGCPERIOD1 */ +#define AGC_AGCPERIOD1_PERIODLOW_DEFAULT (_AGC_AGCPERIOD1_PERIODLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_AGCPERIOD1 */ + +/* Bit fields for AGC HICNTREGION0 */ +#define _AGC_HICNTREGION0_RESETVALUE 0x06050403UL /**< Default value for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_MASK 0xFFFFFFFFUL /**< Mask for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION0_SHIFT 0 /**< Shift value for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION0_MASK 0xFFUL /**< Bit mask for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION0_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_HICNTREGION0 */ +#define AGC_HICNTREGION0_HICNTREGION0_DEFAULT (_AGC_HICNTREGION0_HICNTREGION0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION1_SHIFT 8 /**< Shift value for AGC_HICNTREGION1 */ +#define _AGC_HICNTREGION0_HICNTREGION1_MASK 0xFF00UL /**< Bit mask for AGC_HICNTREGION1 */ +#define _AGC_HICNTREGION0_HICNTREGION1_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_HICNTREGION0 */ +#define AGC_HICNTREGION0_HICNTREGION1_DEFAULT (_AGC_HICNTREGION0_HICNTREGION1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION2_SHIFT 16 /**< Shift value for AGC_HICNTREGION2 */ +#define _AGC_HICNTREGION0_HICNTREGION2_MASK 0xFF0000UL /**< Bit mask for AGC_HICNTREGION2 */ +#define _AGC_HICNTREGION0_HICNTREGION2_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_HICNTREGION0 */ +#define AGC_HICNTREGION0_HICNTREGION2_DEFAULT (_AGC_HICNTREGION0_HICNTREGION2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */ +#define _AGC_HICNTREGION0_HICNTREGION3_SHIFT 24 /**< Shift value for AGC_HICNTREGION3 */ +#define _AGC_HICNTREGION0_HICNTREGION3_MASK 0xFF000000UL /**< Bit mask for AGC_HICNTREGION3 */ +#define _AGC_HICNTREGION0_HICNTREGION3_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_HICNTREGION0 */ +#define AGC_HICNTREGION0_HICNTREGION3_DEFAULT (_AGC_HICNTREGION0_HICNTREGION3_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */ + +/* Bit fields for AGC HICNTREGION1 */ +#define _AGC_HICNTREGION1_RESETVALUE 0x00000008UL /**< Default value for AGC_HICNTREGION1 */ +#define _AGC_HICNTREGION1_MASK 0x000000FFUL /**< Mask for AGC_HICNTREGION1 */ +#define _AGC_HICNTREGION1_HICNTREGION4_SHIFT 0 /**< Shift value for AGC_HICNTREGION4 */ +#define _AGC_HICNTREGION1_HICNTREGION4_MASK 0xFFUL /**< Bit mask for AGC_HICNTREGION4 */ +#define _AGC_HICNTREGION1_HICNTREGION4_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_HICNTREGION1 */ +#define AGC_HICNTREGION1_HICNTREGION4_DEFAULT (_AGC_HICNTREGION1_HICNTREGION4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_HICNTREGION1 */ + +/* Bit fields for AGC STEPDWN */ +#define _AGC_STEPDWN_RESETVALUE 0x00036D11UL /**< Default value for AGC_STEPDWN */ +#define _AGC_STEPDWN_MASK 0x0003FFFFUL /**< Mask for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN0_SHIFT 0 /**< Shift value for AGC_STEPDWN0 */ +#define _AGC_STEPDWN_STEPDWN0_MASK 0x7UL /**< Bit mask for AGC_STEPDWN0 */ +#define _AGC_STEPDWN_STEPDWN0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN0_DEFAULT (_AGC_STEPDWN_STEPDWN0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN1_SHIFT 3 /**< Shift value for AGC_STEPDWN1 */ +#define _AGC_STEPDWN_STEPDWN1_MASK 0x38UL /**< Bit mask for AGC_STEPDWN1 */ +#define _AGC_STEPDWN_STEPDWN1_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN1_DEFAULT (_AGC_STEPDWN_STEPDWN1_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN2_SHIFT 6 /**< Shift value for AGC_STEPDWN2 */ +#define _AGC_STEPDWN_STEPDWN2_MASK 0x1C0UL /**< Bit mask for AGC_STEPDWN2 */ +#define _AGC_STEPDWN_STEPDWN2_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN2_DEFAULT (_AGC_STEPDWN_STEPDWN2_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN3_SHIFT 9 /**< Shift value for AGC_STEPDWN3 */ +#define _AGC_STEPDWN_STEPDWN3_MASK 0xE00UL /**< Bit mask for AGC_STEPDWN3 */ +#define _AGC_STEPDWN_STEPDWN3_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN3_DEFAULT (_AGC_STEPDWN_STEPDWN3_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN4_SHIFT 12 /**< Shift value for AGC_STEPDWN4 */ +#define _AGC_STEPDWN_STEPDWN4_MASK 0x7000UL /**< Bit mask for AGC_STEPDWN4 */ +#define _AGC_STEPDWN_STEPDWN4_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN4_DEFAULT (_AGC_STEPDWN_STEPDWN4_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_STEPDWN */ +#define _AGC_STEPDWN_STEPDWN5_SHIFT 15 /**< Shift value for AGC_STEPDWN5 */ +#define _AGC_STEPDWN_STEPDWN5_MASK 0x38000UL /**< Bit mask for AGC_STEPDWN5 */ +#define _AGC_STEPDWN_STEPDWN5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */ +#define AGC_STEPDWN_STEPDWN5_DEFAULT (_AGC_STEPDWN_STEPDWN5_DEFAULT << 15) /**< Shifted mode DEFAULT for AGC_STEPDWN */ + +/* Bit fields for AGC GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_RESETVALUE 0x00003144UL /**< Default value for AGC_GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_MASK 0x01FFFFFFUL /**< Mask for AGC_GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_SHIFT 0 /**< Shift value for AGC_CFLOOPSTEPMAX */ +#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_MASK 0x1FUL /**< Bit mask for AGC_CFLOOPSTEPMAX */ +#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT (_AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_CFLOOPDEL_SHIFT 5 /**< Shift value for AGC_CFLOOPDEL */ +#define _AGC_GAINSTEPLIM0_CFLOOPDEL_MASK 0xFE0UL /**< Bit mask for AGC_CFLOOPDEL */ +#define _AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT (_AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_HYST_SHIFT 12 /**< Shift value for AGC_HYST */ +#define _AGC_GAINSTEPLIM0_HYST_MASK 0xF000UL /**< Bit mask for AGC_HYST */ +#define _AGC_GAINSTEPLIM0_HYST_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_HYST_DEFAULT (_AGC_GAINSTEPLIM0_HYST_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define _AGC_GAINSTEPLIM0_MAXPWRVAR_SHIFT 16 /**< Shift value for AGC_MAXPWRVAR */ +#define _AGC_GAINSTEPLIM0_MAXPWRVAR_MASK 0xFF0000UL /**< Bit mask for AGC_MAXPWRVAR */ +#define _AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT (_AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_TRANRSTAGC (0x1UL << 24) /**< power transient detector Reset AGC */ +#define _AGC_GAINSTEPLIM0_TRANRSTAGC_SHIFT 24 /**< Shift value for AGC_TRANRSTAGC */ +#define _AGC_GAINSTEPLIM0_TRANRSTAGC_MASK 0x1000000UL /**< Bit mask for AGC_TRANRSTAGC */ +#define _AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */ +#define AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT (_AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */ + +/* Bit fields for AGC GAINSTEPLIM1 */ +#define _AGC_GAINSTEPLIM1_RESETVALUE 0x000011BAUL /**< Default value for AGC_GAINSTEPLIM1 */ +#define _AGC_GAINSTEPLIM1_MASK 0x00001FFFUL /**< Mask for AGC_GAINSTEPLIM1 */ +#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_SHIFT 0 /**< Shift value for AGC_LNAINDEXMAX */ +#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_MASK 0xFUL /**< Bit mask for AGC_LNAINDEXMAX */ +#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */ +#define AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */ +#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_SHIFT 4 /**< Shift value for AGC_PGAINDEXMAX */ +#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_MASK 0xF0UL /**< Bit mask for AGC_PGAINDEXMAX */ +#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */ +#define AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */ +#define _AGC_GAINSTEPLIM1_PNINDEXMAX_SHIFT 8 /**< Shift value for AGC_PNINDEXMAX */ +#define _AGC_GAINSTEPLIM1_PNINDEXMAX_MASK 0x1F00UL /**< Bit mask for AGC_PNINDEXMAX */ +#define _AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT 0x00000011UL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */ +#define AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */ + +/* Bit fields for AGC PNRFATT0 */ +#define _AGC_PNRFATT0_RESETVALUE 0x00200400UL /**< Default value for AGC_PNRFATT0 */ +#define _AGC_PNRFATT0_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT0 */ +#define _AGC_PNRFATT0_LNAMIXRFATT1_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT1 */ +#define _AGC_PNRFATT0_LNAMIXRFATT1_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT1 */ +#define _AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PNRFATT0 */ +#define AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */ +#define _AGC_PNRFATT0_LNAMIXRFATT2_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT2 */ +#define _AGC_PNRFATT0_LNAMIXRFATT2_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT2 */ +#define _AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PNRFATT0 */ +#define AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */ +#define _AGC_PNRFATT0_LNAMIXRFATT3_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT3 */ +#define _AGC_PNRFATT0_LNAMIXRFATT3_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT3 */ +#define _AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PNRFATT0 */ +#define AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */ + +/* Bit fields for AGC PNRFATT1 */ +#define _AGC_PNRFATT1_RESETVALUE 0x00801804UL /**< Default value for AGC_PNRFATT1 */ +#define _AGC_PNRFATT1_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT1 */ +#define _AGC_PNRFATT1_LNAMIXRFATT4_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT4 */ +#define _AGC_PNRFATT1_LNAMIXRFATT4_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT4 */ +#define _AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PNRFATT1 */ +#define AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */ +#define _AGC_PNRFATT1_LNAMIXRFATT5_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT5 */ +#define _AGC_PNRFATT1_LNAMIXRFATT5_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT5 */ +#define _AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PNRFATT1 */ +#define AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */ +#define _AGC_PNRFATT1_LNAMIXRFATT6_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT6 */ +#define _AGC_PNRFATT1_LNAMIXRFATT6_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT6 */ +#define _AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PNRFATT1 */ +#define AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */ + +/* Bit fields for AGC PNRFATT2 */ +#define _AGC_PNRFATT2_RESETVALUE 0x01203C0BUL /**< Default value for AGC_PNRFATT2 */ +#define _AGC_PNRFATT2_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT2 */ +#define _AGC_PNRFATT2_LNAMIXRFATT7_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT7 */ +#define _AGC_PNRFATT2_LNAMIXRFATT7_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT7 */ +#define _AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_PNRFATT2 */ +#define AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */ +#define _AGC_PNRFATT2_LNAMIXRFATT8_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT8 */ +#define _AGC_PNRFATT2_LNAMIXRFATT8_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT8 */ +#define _AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFATT2 */ +#define AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */ +#define _AGC_PNRFATT2_LNAMIXRFATT9_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT9 */ +#define _AGC_PNRFATT2_LNAMIXRFATT9_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT9 */ +#define _AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFATT2 */ +#define AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */ + +/* Bit fields for AGC PNRFATT3 */ +#define _AGC_PNRFATT3_RESETVALUE 0x02107C18UL /**< Default value for AGC_PNRFATT3 */ +#define _AGC_PNRFATT3_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT3 */ +#define _AGC_PNRFATT3_LNAMIXRFATT10_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT10 */ +#define _AGC_PNRFATT3_LNAMIXRFATT10_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT10 */ +#define _AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFATT3 */ +#define AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */ +#define _AGC_PNRFATT3_LNAMIXRFATT11_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT11 */ +#define _AGC_PNRFATT3_LNAMIXRFATT11_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT11 */ +#define _AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFATT3 */ +#define AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */ +#define _AGC_PNRFATT3_LNAMIXRFATT12_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT12 */ +#define _AGC_PNRFATT3_LNAMIXRFATT12_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT12 */ +#define _AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFATT3 */ +#define AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */ + +/* Bit fields for AGC PNRFATT4 */ +#define _AGC_PNRFATT4_RESETVALUE 0x06E0FC2FUL /**< Default value for AGC_PNRFATT4 */ +#define _AGC_PNRFATT4_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT4 */ +#define _AGC_PNRFATT4_LNAMIXRFATT13_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT13 */ +#define _AGC_PNRFATT4_LNAMIXRFATT13_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT13 */ +#define _AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFATT4 */ +#define AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */ +#define _AGC_PNRFATT4_LNAMIXRFATT14_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT14 */ +#define _AGC_PNRFATT4_LNAMIXRFATT14_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT14 */ +#define _AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFATT4 */ +#define AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */ +#define _AGC_PNRFATT4_LNAMIXRFATT15_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT15 */ +#define _AGC_PNRFATT4_LNAMIXRFATT15_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT15 */ +#define _AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFATT4 */ +#define AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */ + +/* Bit fields for AGC PNRFATT5 */ +#define _AGC_PNRFATT5_RESETVALUE 0x0180480FUL /**< Default value for AGC_PNRFATT5 */ +#define _AGC_PNRFATT5_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT5 */ +#define _AGC_PNRFATT5_LNAMIXRFATT16_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT16 */ +#define _AGC_PNRFATT5_LNAMIXRFATT16_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT16 */ +#define _AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFATT5 */ +#define AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */ +#define _AGC_PNRFATT5_LNAMIXRFATT17_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT17 */ +#define _AGC_PNRFATT5_LNAMIXRFATT17_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT17 */ +#define _AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFATT5 */ +#define AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */ +#define _AGC_PNRFATT5_LNAMIXRFATT18_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT18 */ +#define _AGC_PNRFATT5_LNAMIXRFATT18_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT18 */ +#define _AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFATT5 */ +#define AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */ + +/* Bit fields for AGC PNRFATT6 */ +#define _AGC_PNRFATT6_RESETVALUE 0x02F0841FUL /**< Default value for AGC_PNRFATT6 */ +#define _AGC_PNRFATT6_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT6 */ +#define _AGC_PNRFATT6_LNAMIXRFATT19_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT19 */ +#define _AGC_PNRFATT6_LNAMIXRFATT19_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT19 */ +#define _AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFATT6 */ +#define AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */ +#define _AGC_PNRFATT6_LNAMIXRFATT20_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT20 */ +#define _AGC_PNRFATT6_LNAMIXRFATT20_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT20 */ +#define _AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFATT6 */ +#define AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */ +#define _AGC_PNRFATT6_LNAMIXRFATT21_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT21 */ +#define _AGC_PNRFATT6_LNAMIXRFATT21_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT21 */ +#define _AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFATT6 */ +#define AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */ + +/* Bit fields for AGC PNRFATT7 */ +#define _AGC_PNRFATT7_RESETVALUE 0x07F1B83FUL /**< Default value for AGC_PNRFATT7 */ +#define _AGC_PNRFATT7_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT7 */ +#define _AGC_PNRFATT7_LNAMIXRFATT22_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT22 */ +#define _AGC_PNRFATT7_LNAMIXRFATT22_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT22 */ +#define _AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFATT7 */ +#define AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */ +#define _AGC_PNRFATT7_LNAMIXRFATT23_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT23 */ +#define _AGC_PNRFATT7_LNAMIXRFATT23_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT23 */ +#define _AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFATT7 */ +#define AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */ +#define _AGC_PNRFATT7_LNAMIXRFATT24_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT24 */ +#define _AGC_PNRFATT7_LNAMIXRFATT24_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT24 */ +#define _AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFATT7 */ +#define AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */ + +/* Bit fields for AGC PNRFATTALT */ +#define _AGC_PNRFATTALT_RESETVALUE 0x0000007FUL /**< Default value for AGC_PNRFATTALT */ +#define _AGC_PNRFATTALT_MASK 0x000003FFUL /**< Mask for AGC_PNRFATTALT */ +#define _AGC_PNRFATTALT_LNAMIXRFATTALT_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATTALT */ +#define _AGC_PNRFATTALT_LNAMIXRFATTALT_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATTALT */ +#define _AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFATTALT */ +#define AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT (_AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATTALT */ + +/* Bit fields for AGC LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_RESETVALUE 0x15724BBDUL /**< Default value for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_MASK 0x3FFFFFFFUL /**< Mask for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_SHIFT 0 /**< Shift value for AGC_LNAMIXSLICE1 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_MASK 0x3FUL /**< Bit mask for AGC_LNAMIXSLICE1 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT 0x0000003DUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */ +#define AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_SHIFT 6 /**< Shift value for AGC_LNAMIXSLICE2 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_MASK 0xFC0UL /**< Bit mask for AGC_LNAMIXSLICE2 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT 0x0000002EUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */ +#define AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_SHIFT 12 /**< Shift value for AGC_LNAMIXSLICE3 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_MASK 0x3F000UL /**< Bit mask for AGC_LNAMIXSLICE3 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT 0x00000024UL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */ +#define AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_SHIFT 18 /**< Shift value for AGC_LNAMIXSLICE4 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_MASK 0xFC0000UL /**< Bit mask for AGC_LNAMIXSLICE4 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT 0x0000001CUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */ +#define AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_SHIFT 24 /**< Shift value for AGC_LNAMIXSLICE5 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_MASK 0x3F000000UL /**< Bit mask for AGC_LNAMIXSLICE5 */ +#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT 0x00000015UL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */ +#define AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */ + +/* Bit fields for AGC LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_RESETVALUE 0x0518A311UL /**< Default value for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_MASK 0x3FFFFFFFUL /**< Mask for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_SHIFT 0 /**< Shift value for AGC_LNAMIXSLICE6 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_MASK 0x3FUL /**< Bit mask for AGC_LNAMIXSLICE6 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT 0x00000011UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */ +#define AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_SHIFT 6 /**< Shift value for AGC_LNAMIXSLICE7 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_MASK 0xFC0UL /**< Bit mask for AGC_LNAMIXSLICE7 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT 0x0000000CUL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */ +#define AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_SHIFT 12 /**< Shift value for AGC_LNAMIXSLICE8 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_MASK 0x3F000UL /**< Bit mask for AGC_LNAMIXSLICE8 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */ +#define AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_SHIFT 18 /**< Shift value for AGC_LNAMIXSLICE9 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_MASK 0xFC0000UL /**< Bit mask for AGC_LNAMIXSLICE9 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */ +#define AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_SHIFT 24 /**< Shift value for AGC_LNAMIXSLICE10 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_MASK 0x3F000000UL /**< Bit mask for AGC_LNAMIXSLICE10 */ +#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */ +#define AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */ + +/* Bit fields for AGC PGACODE0 */ +#define _AGC_PGACODE0_RESETVALUE 0x76543210UL /**< Default value for AGC_PGACODE0 */ +#define _AGC_PGACODE0_MASK 0xFFFFFFFFUL /**< Mask for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN1_SHIFT 0 /**< Shift value for AGC_PGAGAIN1 */ +#define _AGC_PGACODE0_PGAGAIN1_MASK 0xFUL /**< Bit mask for AGC_PGAGAIN1 */ +#define _AGC_PGACODE0_PGAGAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN1_DEFAULT (_AGC_PGACODE0_PGAGAIN1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN2_SHIFT 4 /**< Shift value for AGC_PGAGAIN2 */ +#define _AGC_PGACODE0_PGAGAIN2_MASK 0xF0UL /**< Bit mask for AGC_PGAGAIN2 */ +#define _AGC_PGACODE0_PGAGAIN2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN2_DEFAULT (_AGC_PGACODE0_PGAGAIN2_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN3_SHIFT 8 /**< Shift value for AGC_PGAGAIN3 */ +#define _AGC_PGACODE0_PGAGAIN3_MASK 0xF00UL /**< Bit mask for AGC_PGAGAIN3 */ +#define _AGC_PGACODE0_PGAGAIN3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN3_DEFAULT (_AGC_PGACODE0_PGAGAIN3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN4_SHIFT 12 /**< Shift value for AGC_PGAGAIN4 */ +#define _AGC_PGACODE0_PGAGAIN4_MASK 0xF000UL /**< Bit mask for AGC_PGAGAIN4 */ +#define _AGC_PGACODE0_PGAGAIN4_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN4_DEFAULT (_AGC_PGACODE0_PGAGAIN4_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN5_SHIFT 16 /**< Shift value for AGC_PGAGAIN5 */ +#define _AGC_PGACODE0_PGAGAIN5_MASK 0xF0000UL /**< Bit mask for AGC_PGAGAIN5 */ +#define _AGC_PGACODE0_PGAGAIN5_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN5_DEFAULT (_AGC_PGACODE0_PGAGAIN5_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN6_SHIFT 20 /**< Shift value for AGC_PGAGAIN6 */ +#define _AGC_PGACODE0_PGAGAIN6_MASK 0xF00000UL /**< Bit mask for AGC_PGAGAIN6 */ +#define _AGC_PGACODE0_PGAGAIN6_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN6_DEFAULT (_AGC_PGACODE0_PGAGAIN6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN7_SHIFT 24 /**< Shift value for AGC_PGAGAIN7 */ +#define _AGC_PGACODE0_PGAGAIN7_MASK 0xF000000UL /**< Bit mask for AGC_PGAGAIN7 */ +#define _AGC_PGACODE0_PGAGAIN7_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN7_DEFAULT (_AGC_PGACODE0_PGAGAIN7_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ +#define _AGC_PGACODE0_PGAGAIN8_SHIFT 28 /**< Shift value for AGC_PGAGAIN8 */ +#define _AGC_PGACODE0_PGAGAIN8_MASK 0xF0000000UL /**< Bit mask for AGC_PGAGAIN8 */ +#define _AGC_PGACODE0_PGAGAIN8_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_PGACODE0 */ +#define AGC_PGACODE0_PGAGAIN8_DEFAULT (_AGC_PGACODE0_PGAGAIN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_PGACODE0 */ + +/* Bit fields for AGC PGACODE1 */ +#define _AGC_PGACODE1_RESETVALUE 0x00000A98UL /**< Default value for AGC_PGACODE1 */ +#define _AGC_PGACODE1_MASK 0x00000FFFUL /**< Mask for AGC_PGACODE1 */ +#define _AGC_PGACODE1_PGAGAIN9_SHIFT 0 /**< Shift value for AGC_PGAGAIN9 */ +#define _AGC_PGACODE1_PGAGAIN9_MASK 0xFUL /**< Bit mask for AGC_PGAGAIN9 */ +#define _AGC_PGACODE1_PGAGAIN9_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PGACODE1 */ +#define AGC_PGACODE1_PGAGAIN9_DEFAULT (_AGC_PGACODE1_PGAGAIN9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PGACODE1 */ +#define _AGC_PGACODE1_PGAGAIN10_SHIFT 4 /**< Shift value for AGC_PGAGAIN10 */ +#define _AGC_PGACODE1_PGAGAIN10_MASK 0xF0UL /**< Bit mask for AGC_PGAGAIN10 */ +#define _AGC_PGACODE1_PGAGAIN10_DEFAULT 0x00000009UL /**< Mode DEFAULT for AGC_PGACODE1 */ +#define AGC_PGACODE1_PGAGAIN10_DEFAULT (_AGC_PGACODE1_PGAGAIN10_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_PGACODE1 */ +#define _AGC_PGACODE1_PGAGAIN11_SHIFT 8 /**< Shift value for AGC_PGAGAIN11 */ +#define _AGC_PGACODE1_PGAGAIN11_MASK 0xF00UL /**< Bit mask for AGC_PGAGAIN11 */ +#define _AGC_PGACODE1_PGAGAIN11_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_PGACODE1 */ +#define AGC_PGACODE1_PGAGAIN11_DEFAULT (_AGC_PGACODE1_PGAGAIN11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_PGACODE1 */ + +/* Bit fields for AGC LBT */ +#define _AGC_LBT_RESETVALUE 0x00000000UL /**< Default value for AGC_LBT */ +#define _AGC_LBT_MASK 0x0000007FUL /**< Mask for AGC_LBT */ +#define _AGC_LBT_CCARSSIPERIOD_SHIFT 0 /**< Shift value for AGC_CCARSSIPERIOD */ +#define _AGC_LBT_CCARSSIPERIOD_MASK 0xFUL /**< Bit mask for AGC_CCARSSIPERIOD */ +#define _AGC_LBT_CCARSSIPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */ +#define AGC_LBT_CCARSSIPERIOD_DEFAULT (_AGC_LBT_CCARSSIPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCARSSIPERIOD (0x1UL << 4) /**< RSSI PERIOD during CCA measurements */ +#define _AGC_LBT_ENCCARSSIPERIOD_SHIFT 4 /**< Shift value for AGC_ENCCARSSIPERIOD */ +#define _AGC_LBT_ENCCARSSIPERIOD_MASK 0x10UL /**< Bit mask for AGC_ENCCARSSIPERIOD */ +#define _AGC_LBT_ENCCARSSIPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCARSSIPERIOD_DEFAULT (_AGC_LBT_ENCCARSSIPERIOD_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCAGAINREDUCED (0x1UL << 5) /**< CCA gain reduced */ +#define _AGC_LBT_ENCCAGAINREDUCED_SHIFT 5 /**< Shift value for AGC_ENCCAGAINREDUCED */ +#define _AGC_LBT_ENCCAGAINREDUCED_MASK 0x20UL /**< Bit mask for AGC_ENCCAGAINREDUCED */ +#define _AGC_LBT_ENCCAGAINREDUCED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCAGAINREDUCED_DEFAULT (_AGC_LBT_ENCCAGAINREDUCED_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCARSSIMAX (0x1UL << 6) /**< Use RSSIMAX to indicate CCA */ +#define _AGC_LBT_ENCCARSSIMAX_SHIFT 6 /**< Shift value for AGC_ENCCARSSIMAX */ +#define _AGC_LBT_ENCCARSSIMAX_MASK 0x40UL /**< Bit mask for AGC_ENCCARSSIMAX */ +#define _AGC_LBT_ENCCARSSIMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */ +#define AGC_LBT_ENCCARSSIMAX_DEFAULT (_AGC_LBT_ENCCARSSIMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LBT */ + +/* Bit fields for AGC MIRRORIF */ +#define _AGC_MIRRORIF_RESETVALUE 0x00000000UL /**< Default value for AGC_MIRRORIF */ +#define _AGC_MIRRORIF_MASK 0x0000000FUL /**< Mask for AGC_MIRRORIF */ +#define AGC_MIRRORIF_RSSIPOSSTEPM (0x1UL << 0) /**< Positive RSSI Step Detected */ +#define _AGC_MIRRORIF_RSSIPOSSTEPM_SHIFT 0 /**< Shift value for AGC_RSSIPOSSTEPM */ +#define _AGC_MIRRORIF_RSSIPOSSTEPM_MASK 0x1UL /**< Bit mask for AGC_RSSIPOSSTEPM */ +#define _AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT (_AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_RSSINEGSTEPM (0x1UL << 1) /**< Negative RSSI Step Detected */ +#define _AGC_MIRRORIF_RSSINEGSTEPM_SHIFT 1 /**< Shift value for AGC_RSSINEGSTEPM */ +#define _AGC_MIRRORIF_RSSINEGSTEPM_MASK 0x2UL /**< Bit mask for AGC_RSSINEGSTEPM */ +#define _AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT (_AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_SHORTRSSIPOSSTEPM (0x1UL << 2) /**< Short-term Positive RSSI Step Detected */ +#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_SHIFT 2 /**< Shift value for AGC_SHORTRSSIPOSSTEPM */ +#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_MASK 0x4UL /**< Bit mask for AGC_SHORTRSSIPOSSTEPM */ +#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT (_AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_IFMIRRORCLEAR (0x1UL << 3) /**< Clear bit for the AGC IF MIRROR Register */ +#define _AGC_MIRRORIF_IFMIRRORCLEAR_SHIFT 3 /**< Shift value for AGC_IFMIRRORCLEAR */ +#define _AGC_MIRRORIF_IFMIRRORCLEAR_MASK 0x8UL /**< Bit mask for AGC_IFMIRRORCLEAR */ +#define _AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */ +#define AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT (_AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_MIRRORIF */ + +/* Bit fields for AGC SEQIF */ +#define _AGC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for AGC_SEQIF */ +#define _AGC_SEQIF_MASK 0x00007F7DUL /**< Mask for AGC_SEQIF */ +#define AGC_SEQIF_RSSIVALID (0x1UL << 0) /**< RSSI Value is Valid */ +#define _AGC_SEQIF_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */ +#define _AGC_SEQIF_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */ +#define _AGC_SEQIF_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSIVALID_DEFAULT (_AGC_SEQIF_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_CCA (0x1UL << 2) /**< Clear Channel Assessment */ +#define _AGC_SEQIF_CCA_SHIFT 2 /**< Shift value for AGC_CCA */ +#define _AGC_SEQIF_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */ +#define _AGC_SEQIF_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_CCA_DEFAULT (_AGC_SEQIF_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSIPOSSTEP (0x1UL << 3) /**< Positive RSSI Step Detected */ +#define _AGC_SEQIF_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */ +#define _AGC_SEQIF_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */ +#define _AGC_SEQIF_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSIPOSSTEP_DEFAULT (_AGC_SEQIF_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSINEGSTEP (0x1UL << 4) /**< Negative RSSI Step Detected */ +#define _AGC_SEQIF_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */ +#define _AGC_SEQIF_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */ +#define _AGC_SEQIF_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSINEGSTEP_DEFAULT (_AGC_SEQIF_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_SHORTRSSIPOSSTEP (0x1UL << 6) /**< Short-term Positive RSSI Step Detected */ +#define _AGC_SEQIF_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_SEQIF_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT (_AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT TOMEOUT */ +#define _AGC_SEQIF_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */ +#define _AGC_SEQIF_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */ +#define _AGC_SEQIF_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RFPKDPRDDONE_DEFAULT (_AGC_SEQIF_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT TOMEOUT */ +#define _AGC_SEQIF_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */ +#define _AGC_SEQIF_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */ +#define _AGC_SEQIF_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RFPKDCNTDONE_DEFAULT (_AGC_SEQIF_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSIHIGH (0x1UL << 10) /**< RSSI high detected */ +#define _AGC_SEQIF_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */ +#define _AGC_SEQIF_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */ +#define _AGC_SEQIF_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSIHIGH_DEFAULT (_AGC_SEQIF_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSILOW (0x1UL << 11) /**< RSSI low detected */ +#define _AGC_SEQIF_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */ +#define _AGC_SEQIF_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */ +#define _AGC_SEQIF_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_RSSILOW_DEFAULT (_AGC_SEQIF_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_CCANODET (0x1UL << 12) /**< CCA Not Detected */ +#define _AGC_SEQIF_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */ +#define _AGC_SEQIF_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */ +#define _AGC_SEQIF_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_CCANODET_DEFAULT (_AGC_SEQIF_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_GAINBELOWGAINTHD (0x1UL << 13) /**< agc gain above threshold int */ +#define _AGC_SEQIF_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */ +#define _AGC_SEQIF_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */ +#define _AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT (_AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int */ +#define _AGC_SEQIF_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */ +#define _AGC_SEQIF_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */ +#define _AGC_SEQIF_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */ +#define AGC_SEQIF_GAINUPDATEFRZ_DEFAULT (_AGC_SEQIF_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_SEQIF */ + +/* Bit fields for AGC SEQIEN */ +#define _AGC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for AGC_SEQIEN */ +#define _AGC_SEQIEN_MASK 0x00007F7DUL /**< Mask for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIVALID (0x1UL << 0) /**< RSSIVALID Interrupt Enable */ +#define _AGC_SEQIEN_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */ +#define _AGC_SEQIEN_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */ +#define _AGC_SEQIEN_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIVALID_DEFAULT (_AGC_SEQIEN_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_CCA (0x1UL << 2) /**< CCA Interrupt Enable */ +#define _AGC_SEQIEN_CCA_SHIFT 2 /**< Shift value for AGC_CCA */ +#define _AGC_SEQIEN_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */ +#define _AGC_SEQIEN_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_CCA_DEFAULT (_AGC_SEQIEN_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIPOSSTEP (0x1UL << 3) /**< RSSIPOSSTEP Interrupt Enable */ +#define _AGC_SEQIEN_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */ +#define _AGC_SEQIEN_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */ +#define _AGC_SEQIEN_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIPOSSTEP_DEFAULT (_AGC_SEQIEN_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSINEGSTEP (0x1UL << 4) /**< RSSINEGSTEP Interrupt Enable */ +#define _AGC_SEQIEN_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */ +#define _AGC_SEQIEN_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */ +#define _AGC_SEQIEN_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSINEGSTEP_DEFAULT (_AGC_SEQIEN_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_SHORTRSSIPOSSTEP (0x1UL << 6) /**< SHORTRSSIPOSSTEP Interrupt Enable */ +#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */ +#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT (_AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT Interrupt Enable */ +#define _AGC_SEQIEN_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */ +#define _AGC_SEQIEN_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */ +#define _AGC_SEQIEN_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RFPKDPRDDONE_DEFAULT (_AGC_SEQIEN_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT Interrupt Enable */ +#define _AGC_SEQIEN_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */ +#define _AGC_SEQIEN_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */ +#define _AGC_SEQIEN_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RFPKDCNTDONE_DEFAULT (_AGC_SEQIEN_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIHIGH (0x1UL << 10) /**< RSSIHIGH Interrupt Enable */ +#define _AGC_SEQIEN_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */ +#define _AGC_SEQIEN_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */ +#define _AGC_SEQIEN_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSIHIGH_DEFAULT (_AGC_SEQIEN_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSILOW (0x1UL << 11) /**< RSSILOW Interrupt Enable */ +#define _AGC_SEQIEN_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */ +#define _AGC_SEQIEN_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */ +#define _AGC_SEQIEN_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_RSSILOW_DEFAULT (_AGC_SEQIEN_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_CCANODET (0x1UL << 12) /**< CCANODET Interrupt Enable */ +#define _AGC_SEQIEN_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */ +#define _AGC_SEQIEN_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */ +#define _AGC_SEQIEN_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_CCANODET_DEFAULT (_AGC_SEQIEN_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_GAINBELOWGAINTHD (0x1UL << 13) /**< GAINBELOWGAINTHD Interrupt Enable */ +#define _AGC_SEQIEN_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */ +#define _AGC_SEQIEN_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */ +#define _AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT (_AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int Enable */ +#define _AGC_SEQIEN_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */ +#define _AGC_SEQIEN_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */ +#define _AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */ +#define AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT (_AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_SEQIEN */ + +/* Bit fields for AGC RSSIABSTHR */ +#define _AGC_RSSIABSTHR_RESETVALUE 0x00000000UL /**< Default value for AGC_RSSIABSTHR */ +#define _AGC_RSSIABSTHR_MASK 0xFFFFFFFFUL /**< Mask for AGC_RSSIABSTHR */ +#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_SHIFT 0 /**< Shift value for AGC_RSSIHIGHTHRSH */ +#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_MASK 0xFFUL /**< Bit mask for AGC_RSSIHIGHTHRSH */ +#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */ +#define AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT (_AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */ +#define _AGC_RSSIABSTHR_RSSILOWTHRSH_SHIFT 8 /**< Shift value for AGC_RSSILOWTHRSH */ +#define _AGC_RSSIABSTHR_RSSILOWTHRSH_MASK 0xFF00UL /**< Bit mask for AGC_RSSILOWTHRSH */ +#define _AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */ +#define AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT (_AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */ +#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_SHIFT 16 /**< Shift value for AGC_SIRSSIHIGHTHR */ +#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_MASK 0xFF0000UL /**< Bit mask for AGC_SIRSSIHIGHTHR */ +#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */ +#define AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT (_AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */ +#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_SHIFT 24 /**< Shift value for AGC_SIRSSINEGSTEPTHR */ +#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_MASK 0xFF000000UL /**< Bit mask for AGC_SIRSSINEGSTEPTHR */ +#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */ +#define AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT (_AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */ + +/* Bit fields for AGC LNABOOST */ +#define _AGC_LNABOOST_RESETVALUE 0x000001FEUL /**< Default value for AGC_LNABOOST */ +#define _AGC_LNABOOST_MASK 0x000001FFUL /**< Mask for AGC_LNABOOST */ +#define AGC_LNABOOST_BOOSTLNA (0x1UL << 0) /**< LNA GAIN BOOST mode */ +#define _AGC_LNABOOST_BOOSTLNA_SHIFT 0 /**< Shift value for AGC_BOOSTLNA */ +#define _AGC_LNABOOST_BOOSTLNA_MASK 0x1UL /**< Bit mask for AGC_BOOSTLNA */ +#define _AGC_LNABOOST_BOOSTLNA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LNABOOST */ +#define AGC_LNABOOST_BOOSTLNA_DEFAULT (_AGC_LNABOOST_BOOSTLNA_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNABOOST */ +#define _AGC_LNABOOST_LNABWADJ_SHIFT 1 /**< Shift value for AGC_LNABWADJ */ +#define _AGC_LNABOOST_LNABWADJ_MASK 0x1EUL /**< Bit mask for AGC_LNABWADJ */ +#define _AGC_LNABOOST_LNABWADJ_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_LNABOOST */ +#define AGC_LNABOOST_LNABWADJ_DEFAULT (_AGC_LNABOOST_LNABWADJ_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_LNABOOST */ +#define _AGC_LNABOOST_LNABWADJBOOST_SHIFT 5 /**< Shift value for AGC_LNABWADJBOOST */ +#define _AGC_LNABOOST_LNABWADJBOOST_MASK 0x1E0UL /**< Bit mask for AGC_LNABWADJBOOST */ +#define _AGC_LNABOOST_LNABWADJBOOST_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_LNABOOST */ +#define AGC_LNABOOST_LNABWADJBOOST_DEFAULT (_AGC_LNABOOST_LNABWADJBOOST_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_LNABOOST */ + +/* Bit fields for AGC ANTDIV */ +#define _AGC_ANTDIV_RESETVALUE 0x00000000UL /**< Default value for AGC_ANTDIV */ +#define _AGC_ANTDIV_MASK 0x000007FFUL /**< Mask for AGC_ANTDIV */ +#define _AGC_ANTDIV_GAINMODE_SHIFT 0 /**< Shift value for AGC_GAINMODE */ +#define _AGC_ANTDIV_GAINMODE_MASK 0x3UL /**< Bit mask for AGC_GAINMODE */ +#define _AGC_ANTDIV_GAINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */ +#define _AGC_ANTDIV_GAINMODE_DISABLE 0x00000000UL /**< Mode DISABLE for AGC_ANTDIV */ +#define _AGC_ANTDIV_GAINMODE_SINGLE_PACKET 0x00000001UL /**< Mode SINGLE_PACKET for AGC_ANTDIV */ +#define _AGC_ANTDIV_GAINMODE_ALWAYS 0x00000002UL /**< Mode ALWAYS for AGC_ANTDIV */ +#define AGC_ANTDIV_GAINMODE_DEFAULT (_AGC_ANTDIV_GAINMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_ANTDIV */ +#define AGC_ANTDIV_GAINMODE_DISABLE (_AGC_ANTDIV_GAINMODE_DISABLE << 0) /**< Shifted mode DISABLE for AGC_ANTDIV */ +#define AGC_ANTDIV_GAINMODE_SINGLE_PACKET (_AGC_ANTDIV_GAINMODE_SINGLE_PACKET << 0) /**< Shifted mode SINGLE_PACKET for AGC_ANTDIV */ +#define AGC_ANTDIV_GAINMODE_ALWAYS (_AGC_ANTDIV_GAINMODE_ALWAYS << 0) /**< Shifted mode ALWAYS for AGC_ANTDIV */ +#define _AGC_ANTDIV_DEBOUNCECNTTHD_SHIFT 2 /**< Shift value for AGC_DEBOUNCECNTTHD */ +#define _AGC_ANTDIV_DEBOUNCECNTTHD_MASK 0x1FCUL /**< Bit mask for AGC_DEBOUNCECNTTHD */ +#define _AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */ +#define AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT (_AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_ANTDIV */ +#define _AGC_ANTDIV_DISRSSIANTDIVFIX_SHIFT 9 /**< Shift value for AGC_DISRSSIANTDIVFIX */ +#define _AGC_ANTDIV_DISRSSIANTDIVFIX_MASK 0x600UL /**< Bit mask for AGC_DISRSSIANTDIVFIX */ +#define _AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */ +#define AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT (_AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_ANTDIV */ + +/* Bit fields for AGC DUALRFPKDTHD0 */ +#define _AGC_DUALRFPKDTHD0_RESETVALUE 0x000A0001UL /**< Default value for AGC_DUALRFPKDTHD0 */ +#define _AGC_DUALRFPKDTHD0_MASK 0x0FFF0FFFUL /**< Mask for AGC_DUALRFPKDTHD0 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_SHIFT 0 /**< Shift value for AGC_RFPKDLOWTHD0 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDLOWTHD0 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD0 */ +#define AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT (_AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD0 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_SHIFT 16 /**< Shift value for AGC_RFPKDLOWTHD1 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_MASK 0xFFF0000UL /**< Bit mask for AGC_RFPKDLOWTHD1 */ +#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_DUALRFPKDTHD0 */ +#define AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT (_AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD0 */ + +/* Bit fields for AGC DUALRFPKDTHD1 */ +#define _AGC_DUALRFPKDTHD1_RESETVALUE 0x00280001UL /**< Default value for AGC_DUALRFPKDTHD1 */ +#define _AGC_DUALRFPKDTHD1_MASK 0x0FFF0FFFUL /**< Mask for AGC_DUALRFPKDTHD1 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_SHIFT 0 /**< Shift value for AGC_RFPKDHITHD0 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDHITHD0 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD1 */ +#define AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT (_AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD1 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_SHIFT 16 /**< Shift value for AGC_RFPKDHITHD1 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_MASK 0xFFF0000UL /**< Bit mask for AGC_RFPKDHITHD1 */ +#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT 0x00000028UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD1 */ +#define AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT (_AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD1 */ + +/* Bit fields for AGC SPARE */ +#define _AGC_SPARE_RESETVALUE 0x00000000UL /**< Default value for AGC_SPARE */ +#define _AGC_SPARE_MASK 0x000000FFUL /**< Mask for AGC_SPARE */ +#define _AGC_SPARE_SPAREREG_SHIFT 0 /**< Shift value for AGC_SPAREREG */ +#define _AGC_SPARE_SPAREREG_MASK 0xFFUL /**< Bit mask for AGC_SPAREREG */ +#define _AGC_SPARE_SPAREREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SPARE */ +#define AGC_SPARE_SPAREREG_DEFAULT (_AGC_SPARE_SPAREREG_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SPARE */ + +/* Bit fields for AGC PNRFFILT0 */ +#define _AGC_PNRFFILT0_RESETVALUE 0x00200400UL /**< Default value for AGC_PNRFFILT0 */ +#define _AGC_PNRFFILT0_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT0 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT1_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT1 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT1_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT1 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PNRFFILT0 */ +#define AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT2_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT2 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT2_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT2 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PNRFFILT0 */ +#define AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT3_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT3 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT3_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT3 */ +#define _AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PNRFFILT0 */ +#define AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */ + +/* Bit fields for AGC PNRFFILT1 */ +#define _AGC_PNRFFILT1_RESETVALUE 0x00801804UL /**< Default value for AGC_PNRFFILT1 */ +#define _AGC_PNRFFILT1_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT1 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT4_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT4 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT4_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT4 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PNRFFILT1 */ +#define AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT5_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT5 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT5_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT5 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PNRFFILT1 */ +#define AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT6_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT6 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT6_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT6 */ +#define _AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PNRFFILT1 */ +#define AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */ + +/* Bit fields for AGC PNRFFILT2 */ +#define _AGC_PNRFFILT2_RESETVALUE 0x01203C0BUL /**< Default value for AGC_PNRFFILT2 */ +#define _AGC_PNRFFILT2_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT2 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT7_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT7 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT7_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT7 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_PNRFFILT2 */ +#define AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT8_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT8 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT8_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT8 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFFILT2 */ +#define AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT9_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT9 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT9_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT9 */ +#define _AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFFILT2 */ +#define AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */ + +/* Bit fields for AGC PNRFFILT3 */ +#define _AGC_PNRFFILT3_RESETVALUE 0x02107C18UL /**< Default value for AGC_PNRFFILT3 */ +#define _AGC_PNRFFILT3_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT3 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT10_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT10 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT10_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT10 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFFILT3 */ +#define AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT11_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT11 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT11_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT11 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFFILT3 */ +#define AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT12_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT12 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT12_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT12 */ +#define _AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFFILT3 */ +#define AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */ + +/* Bit fields for AGC PNRFFILT4 */ +#define _AGC_PNRFFILT4_RESETVALUE 0x06E0FC2FUL /**< Default value for AGC_PNRFFILT4 */ +#define _AGC_PNRFFILT4_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT4 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT13_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT13 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT13_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT13 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFFILT4 */ +#define AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT14_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT14 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT14_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT14 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFFILT4 */ +#define AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT15_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT15 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT15_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT15 */ +#define _AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFFILT4 */ +#define AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */ + +/* Bit fields for AGC PNRFFILT5 */ +#define _AGC_PNRFFILT5_RESETVALUE 0x0180480FUL /**< Default value for AGC_PNRFFILT5 */ +#define _AGC_PNRFFILT5_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT5 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT16_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT16 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT16_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT16 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFFILT5 */ +#define AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT17_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT17 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT17_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT17 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFFILT5 */ +#define AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT18_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT18 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT18_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT18 */ +#define _AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFFILT5 */ +#define AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */ + +/* Bit fields for AGC PNRFFILT6 */ +#define _AGC_PNRFFILT6_RESETVALUE 0x02F0841FUL /**< Default value for AGC_PNRFFILT6 */ +#define _AGC_PNRFFILT6_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT6 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT19_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT19 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT19_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT19 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFFILT6 */ +#define AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT20_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT20 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT20_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT20 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFFILT6 */ +#define AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT21_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT21 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT21_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT21 */ +#define _AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFFILT6 */ +#define AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */ + +/* Bit fields for AGC PNRFFILT7 */ +#define _AGC_PNRFFILT7_RESETVALUE 0x07F1B83FUL /**< Default value for AGC_PNRFFILT7 */ +#define _AGC_PNRFFILT7_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT7 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT22_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT22 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT22_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT22 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFFILT7 */ +#define AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT23_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT23 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT23_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT23 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFFILT7 */ +#define AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT24_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT24 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT24_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT24 */ +#define _AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFFILT7 */ +#define AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */ + +/* Bit fields for AGC FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL1 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL1 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE1 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE1 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE1 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE1 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHRATTNEN1 (0x1UL << 12) /**< FE notch rattn enable for index 1 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN1 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN1 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHEN1 (0x1UL << 13) /**< FE notch enable for index 1 */ +#define _AGC_FENOTCHATT0_FENOTCHEN1_SHIFT 13 /**< Shift value for AGC_FENOTCHEN1 */ +#define _AGC_FENOTCHATT0_FENOTCHEN1_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN1 */ +#define _AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL2 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL2 */ +#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE2 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE2 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE2 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE2 */ +#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHRATTNEN2 (0x1UL << 28) /**< FE notch rattn enable for index 2 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN2 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN2 */ +#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHEN2 (0x1UL << 29) /**< FE notch enable for index 2 */ +#define _AGC_FENOTCHATT0_FENOTCHEN2_SHIFT 29 /**< Shift value for AGC_FENOTCHEN2 */ +#define _AGC_FENOTCHATT0_FENOTCHEN2_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN2 */ +#define _AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */ +#define AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */ + +/* Bit fields for AGC FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL3 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL3 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE3 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE3 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE3 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE3 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHRATTNEN3 (0x1UL << 12) /**< FE notch rattn enable for index 3 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN3 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN3 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHEN3 (0x1UL << 13) /**< FE notch enable for index 3 */ +#define _AGC_FENOTCHATT1_FENOTCHEN3_SHIFT 13 /**< Shift value for AGC_FENOTCHEN3 */ +#define _AGC_FENOTCHATT1_FENOTCHEN3_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN3 */ +#define _AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL4 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL4 */ +#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE4 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE4 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE4 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE4 */ +#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHRATTNEN4 (0x1UL << 28) /**< FE notch rattn enable for index 4 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN4 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN4 */ +#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHEN4 (0x1UL << 29) /**< FE notch enable for index 4 */ +#define _AGC_FENOTCHATT1_FENOTCHEN4_SHIFT 29 /**< Shift value for AGC_FENOTCHEN4 */ +#define _AGC_FENOTCHATT1_FENOTCHEN4_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN4 */ +#define _AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */ +#define AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */ + +/* Bit fields for AGC FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL5 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL5 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE5 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE5 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE5 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE5 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHRATTNEN5 (0x1UL << 12) /**< FE notch rattn enable for index 5 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN5 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN5 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHEN5 (0x1UL << 13) /**< FE notch enable for index 5 */ +#define _AGC_FENOTCHATT2_FENOTCHEN5_SHIFT 13 /**< Shift value for AGC_FENOTCHEN5 */ +#define _AGC_FENOTCHATT2_FENOTCHEN5_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN5 */ +#define _AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL6 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL6 */ +#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE6 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE6 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE6 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE6 */ +#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHRATTNEN6 (0x1UL << 28) /**< FE notch rattn enable for index 6 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN6 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN6 */ +#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHEN6 (0x1UL << 29) /**< FE notch enable for index 6 */ +#define _AGC_FENOTCHATT2_FENOTCHEN6_SHIFT 29 /**< Shift value for AGC_FENOTCHEN6 */ +#define _AGC_FENOTCHATT2_FENOTCHEN6_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN6 */ +#define _AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */ +#define AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */ + +/* Bit fields for AGC FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL7 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL7 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE7 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE7 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE7 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE7 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHRATTNEN7 (0x1UL << 12) /**< FE notch rattn enable for index 7 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN7 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN7 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHEN7 (0x1UL << 13) /**< FE notch enable for index 7 */ +#define _AGC_FENOTCHATT3_FENOTCHEN7_SHIFT 13 /**< Shift value for AGC_FENOTCHEN7 */ +#define _AGC_FENOTCHATT3_FENOTCHEN7_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN7 */ +#define _AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL8 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL8 */ +#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE8 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE8 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE8 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE8 */ +#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHRATTNEN8 (0x1UL << 28) /**< FE notch rattn enable for index 8 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN8 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN8 */ +#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHEN8 (0x1UL << 29) /**< FE notch enable for index 8 */ +#define _AGC_FENOTCHATT3_FENOTCHEN8_SHIFT 29 /**< Shift value for AGC_FENOTCHEN8 */ +#define _AGC_FENOTCHATT3_FENOTCHEN8_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN8 */ +#define _AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */ +#define AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */ + +/* Bit fields for AGC FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL9 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL9 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE9 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE9 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE9 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE9 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHRATTNEN9 (0x1UL << 12) /**< FE notch rattn enable for index 9 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN9 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN9 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHEN9 (0x1UL << 13) /**< FE notch enable for index 9 */ +#define _AGC_FENOTCHATT4_FENOTCHEN9_SHIFT 13 /**< Shift value for AGC_FENOTCHEN9 */ +#define _AGC_FENOTCHATT4_FENOTCHEN9_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN9 */ +#define _AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL10 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL10 */ +#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE10 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE10 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE10 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE10 */ +#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHRATTNEN10 (0x1UL << 28) /**< FE notch rattn enable for index 10 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN10 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN10 */ +#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHEN10 (0x1UL << 29) /**< FE notch enable for index 10 */ +#define _AGC_FENOTCHATT4_FENOTCHEN10_SHIFT 29 /**< Shift value for AGC_FENOTCHEN10 */ +#define _AGC_FENOTCHATT4_FENOTCHEN10_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN10 */ +#define _AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */ +#define AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */ + +/* Bit fields for AGC FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL11 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL11 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE11 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE11 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE11 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE11 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHRATTNEN11 (0x1UL << 12) /**< FE notch rattn enable for index 11 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN11 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN11 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHEN11 (0x1UL << 13) /**< FE notch enable for index 11 */ +#define _AGC_FENOTCHATT5_FENOTCHEN11_SHIFT 13 /**< Shift value for AGC_FENOTCHEN11 */ +#define _AGC_FENOTCHATT5_FENOTCHEN11_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN11 */ +#define _AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL12 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL12 */ +#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE12 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE12 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE12 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE12 */ +#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHRATTNEN12 (0x1UL << 28) /**< FE notch rattn enable for index 12 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN12 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN12 */ +#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHEN12 (0x1UL << 29) /**< FE notch enable for index 12 */ +#define _AGC_FENOTCHATT5_FENOTCHEN12_SHIFT 29 /**< Shift value for AGC_FENOTCHEN12 */ +#define _AGC_FENOTCHATT5_FENOTCHEN12_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN12 */ +#define _AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */ +#define AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */ + +/* Bit fields for AGC FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL13 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL13 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE13 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE13 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE13 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE13 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHRATTNEN13 (0x1UL << 12) /**< FE notch rattn enable for index 13 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN13 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN13 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHEN13 (0x1UL << 13) /**< FE notch enable for index 13 */ +#define _AGC_FENOTCHATT6_FENOTCHEN13_SHIFT 13 /**< Shift value for AGC_FENOTCHEN13 */ +#define _AGC_FENOTCHATT6_FENOTCHEN13_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN13 */ +#define _AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL14 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL14 */ +#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE14 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE14 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE14 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE14 */ +#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHRATTNEN14 (0x1UL << 28) /**< FE notch rattn enable for index 14 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN14 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN14 */ +#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHEN14 (0x1UL << 29) /**< FE notch enable for index 14 */ +#define _AGC_FENOTCHATT6_FENOTCHEN14_SHIFT 29 /**< Shift value for AGC_FENOTCHEN14 */ +#define _AGC_FENOTCHATT6_FENOTCHEN14_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN14 */ +#define _AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */ +#define AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */ + +/* Bit fields for AGC FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_RESETVALUE 0x20080000UL /**< Default value for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL15 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL15 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE15 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE15 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE15 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE15 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHRATTNEN15 (0x1UL << 12) /**< FE notch rattn enable for index 15 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN15 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN15 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHEN15 (0x1UL << 13) /**< FE notch enable for index 15 */ +#define _AGC_FENOTCHATT7_FENOTCHEN15_SHIFT 13 /**< Shift value for AGC_FENOTCHEN15 */ +#define _AGC_FENOTCHATT7_FENOTCHEN15_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN15 */ +#define _AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL16 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL16 */ +#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE16 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE16 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE16 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE16 */ +#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHRATTNEN16 (0x1UL << 28) /**< FE notch rattn enable for index 16 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN16 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN16 */ +#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHEN16 (0x1UL << 29) /**< FE notch enable for index 16 */ +#define _AGC_FENOTCHATT7_FENOTCHEN16_SHIFT 29 /**< Shift value for AGC_FENOTCHEN16 */ +#define _AGC_FENOTCHATT7_FENOTCHEN16_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN16 */ +#define _AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */ +#define AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */ + +/* Bit fields for AGC FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_RESETVALUE 0x200B200AUL /**< Default value for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL17 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL17 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE17 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE17 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE17 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE17 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHRATTNEN17 (0x1UL << 12) /**< FE notch rattn enable for index 17 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN17 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN17 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHEN17 (0x1UL << 13) /**< FE notch enable for index 17 */ +#define _AGC_FENOTCHATT8_FENOTCHEN17_SHIFT 13 /**< Shift value for AGC_FENOTCHEN17 */ +#define _AGC_FENOTCHATT8_FENOTCHEN17_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN17 */ +#define _AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL18 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL18 */ +#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE18 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE18 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE18 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE18 */ +#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHRATTNEN18 (0x1UL << 28) /**< FE notch rattn enable for index 18 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN18 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN18 */ +#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHEN18 (0x1UL << 29) /**< FE notch enable for index 18 */ +#define _AGC_FENOTCHATT8_FENOTCHEN18_SHIFT 29 /**< Shift value for AGC_FENOTCHEN18 */ +#define _AGC_FENOTCHATT8_FENOTCHEN18_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN18 */ +#define _AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */ +#define AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */ + +/* Bit fields for AGC FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL19 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL19 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE19 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE19 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE19 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE19 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHRATTNEN19 (0x1UL << 12) /**< FE notch rattn enable for index 19 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN19 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN19 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHEN19 (0x1UL << 13) /**< FE notch enable for index 19 */ +#define _AGC_FENOTCHATT9_FENOTCHEN19_SHIFT 13 /**< Shift value for AGC_FENOTCHEN19 */ +#define _AGC_FENOTCHATT9_FENOTCHEN19_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN19 */ +#define _AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL20 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL20 */ +#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE20 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE20 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE20 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE20 */ +#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHRATTNEN20 (0x1UL << 28) /**< FE notch rattn enable for index 20 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN20 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN20 */ +#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHEN20 (0x1UL << 29) /**< FE notch enable for index 20 */ +#define _AGC_FENOTCHATT9_FENOTCHEN20_SHIFT 29 /**< Shift value for AGC_FENOTCHEN20 */ +#define _AGC_FENOTCHATT9_FENOTCHEN20_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN20 */ +#define _AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */ +#define AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */ + +/* Bit fields for AGC FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL21 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL21 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE21 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE21 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE21 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE21 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHRATTNEN21 (0x1UL << 12) /**< FE notch rattn enable for index 21 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN21 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN21 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHEN21 (0x1UL << 13) /**< FE notch enable for index 21 */ +#define _AGC_FENOTCHATT10_FENOTCHEN21_SHIFT 13 /**< Shift value for AGC_FENOTCHEN21 */ +#define _AGC_FENOTCHATT10_FENOTCHEN21_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN21 */ +#define _AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL22 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL22 */ +#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE22 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE22 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE22 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE22 */ +#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHRATTNEN22 (0x1UL << 28) /**< FE notch rattn enable for index 22 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN22 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN22 */ +#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHEN22 (0x1UL << 29) /**< FE notch enable for index 22 */ +#define _AGC_FENOTCHATT10_FENOTCHEN22_SHIFT 29 /**< Shift value for AGC_FENOTCHEN22 */ +#define _AGC_FENOTCHATT10_FENOTCHEN22_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN22 */ +#define _AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */ +#define AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */ + +/* Bit fields for AGC FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL23 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL23 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE23 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE23 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE23 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE23 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHRATTNEN23 (0x1UL << 12) /**< FE notch rattn enable for index 23 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN23 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN23 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHEN23 (0x1UL << 13) /**< FE notch enable for index 23 */ +#define _AGC_FENOTCHATT11_FENOTCHEN23_SHIFT 13 /**< Shift value for AGC_FENOTCHEN23 */ +#define _AGC_FENOTCHATT11_FENOTCHEN23_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN23 */ +#define _AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL24 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL24 */ +#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE24 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE24 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE24 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE24 */ +#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHRATTNEN24 (0x1UL << 28) /**< FE notch rattn enable for index 24 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN24 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN24 */ +#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHEN24 (0x1UL << 29) /**< FE notch enable for index 24 */ +#define _AGC_FENOTCHATT11_FENOTCHEN24_SHIFT 29 /**< Shift value for AGC_FENOTCHEN24 */ +#define _AGC_FENOTCHATT11_FENOTCHEN24_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN24 */ +#define _AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */ +#define AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */ + +/* Bit fields for AGC FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL1 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL1 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE1 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE1 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE1 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE1 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHRATTNEN1 (0x1UL << 12) /**< FE notch rattn enable for index 1 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN1 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN1 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHEN1 (0x1UL << 13) /**< FE notch enable for index 1 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN1_SHIFT 13 /**< Shift value for AGC_FENOTCHEN1 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN1_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN1 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL2 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL2 */ +#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE2 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE2 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE2 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE2 */ +#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHRATTNEN2 (0x1UL << 28) /**< FE notch rattn enable for index 2 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN2 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN2 */ +#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHEN2 (0x1UL << 29) /**< FE notch enable for index 2 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN2_SHIFT 29 /**< Shift value for AGC_FENOTCHEN2 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN2_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN2 */ +#define _AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */ +#define AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */ + +/* Bit fields for AGC FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL3 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL3 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE3 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE3 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE3 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE3 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHRATTNEN3 (0x1UL << 12) /**< FE notch rattn enable for index 3 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN3 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN3 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHEN3 (0x1UL << 13) /**< FE notch enable for index 3 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN3_SHIFT 13 /**< Shift value for AGC_FENOTCHEN3 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN3_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN3 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL4 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL4 */ +#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE4 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE4 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE4 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE4 */ +#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHRATTNEN4 (0x1UL << 28) /**< FE notch rattn enable for index 4 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN4 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN4 */ +#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHEN4 (0x1UL << 29) /**< FE notch enable for index 4 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN4_SHIFT 29 /**< Shift value for AGC_FENOTCHEN4 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN4_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN4 */ +#define _AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */ +#define AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */ + +/* Bit fields for AGC FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL5 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL5 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE5 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE5 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE5 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE5 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHRATTNEN5 (0x1UL << 12) /**< FE notch rattn enable for index 5 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN5 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN5 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHEN5 (0x1UL << 13) /**< FE notch enable for index 5 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN5_SHIFT 13 /**< Shift value for AGC_FENOTCHEN5 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN5_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN5 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL6 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL6 */ +#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE6 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE6 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE6 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE6 */ +#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHRATTNEN6 (0x1UL << 28) /**< FE notch rattn enable for index 6 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN6 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN6 */ +#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHEN6 (0x1UL << 29) /**< FE notch enable for index 6 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN6_SHIFT 29 /**< Shift value for AGC_FENOTCHEN6 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN6_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN6 */ +#define _AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */ +#define AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */ + +/* Bit fields for AGC FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL7 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL7 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE7 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE7 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE7 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE7 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHRATTNEN7 (0x1UL << 12) /**< FE notch rattn enable for index 7 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN7 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN7 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHEN7 (0x1UL << 13) /**< FE notch enable for index 7 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN7_SHIFT 13 /**< Shift value for AGC_FENOTCHEN7 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN7_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN7 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL8 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL8 */ +#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE8 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE8 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE8 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE8 */ +#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHRATTNEN8 (0x1UL << 28) /**< FE notch rattn enable for index 8 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN8 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN8 */ +#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHEN8 (0x1UL << 29) /**< FE notch enable for index 8 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN8_SHIFT 29 /**< Shift value for AGC_FENOTCHEN8 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN8_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN8 */ +#define _AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */ +#define AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */ + +/* Bit fields for AGC FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL9 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL9 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE9 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE9 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE9 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE9 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHRATTNEN9 (0x1UL << 12) /**< FE notch rattn enable for index 9 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN9 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN9 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHEN9 (0x1UL << 13) /**< FE notch enable for index 9 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN9_SHIFT 13 /**< Shift value for AGC_FENOTCHEN9 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN9_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN9 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL10 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL10 */ +#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE10 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE10 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE10 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE10 */ +#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHRATTNEN10 (0x1UL << 28) /**< FE notch rattn enable for index 10 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN10 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN10 */ +#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHEN10 (0x1UL << 29) /**< FE notch enable for index 10 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN10_SHIFT 29 /**< Shift value for AGC_FENOTCHEN10 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN10_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN10 */ +#define _AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */ +#define AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */ + +/* Bit fields for AGC FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL11 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL11 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE11 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE11 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE11 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE11 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHRATTNEN11 (0x1UL << 12) /**< FE notch rattn enable for index 11 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN11 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN11 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHEN11 (0x1UL << 13) /**< FE notch enable for index 11 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN11_SHIFT 13 /**< Shift value for AGC_FENOTCHEN11 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN11_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN11 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL12 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL12 */ +#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE12 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE12 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE12 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE12 */ +#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHRATTNEN12 (0x1UL << 28) /**< FE notch rattn enable for index 12 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN12 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN12 */ +#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHEN12 (0x1UL << 29) /**< FE notch enable for index 12 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN12_SHIFT 29 /**< Shift value for AGC_FENOTCHEN12 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN12_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN12 */ +#define _AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */ +#define AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */ + +/* Bit fields for AGC FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL13 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL13 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE13 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE13 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE13 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE13 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHRATTNEN13 (0x1UL << 12) /**< FE notch rattn enable for index 13 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN13 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN13 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHEN13 (0x1UL << 13) /**< FE notch enable for index 13 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN13_SHIFT 13 /**< Shift value for AGC_FENOTCHEN13 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN13_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN13 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL14 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL14 */ +#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE14 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE14 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE14 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE14 */ +#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHRATTNEN14 (0x1UL << 28) /**< FE notch rattn enable for index 14 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN14 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN14 */ +#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHEN14 (0x1UL << 29) /**< FE notch enable for index 14 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN14_SHIFT 29 /**< Shift value for AGC_FENOTCHEN14 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN14_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN14 */ +#define _AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */ +#define AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */ + +/* Bit fields for AGC FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_RESETVALUE 0x20080000UL /**< Default value for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL15 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL15 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE15 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE15 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE15 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE15 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHRATTNEN15 (0x1UL << 12) /**< FE notch rattn enable for index 15 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN15 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN15 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHEN15 (0x1UL << 13) /**< FE notch enable for index 15 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN15_SHIFT 13 /**< Shift value for AGC_FENOTCHEN15 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN15_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN15 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL16 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL16 */ +#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE16 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE16 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE16 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE16 */ +#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHRATTNEN16 (0x1UL << 28) /**< FE notch rattn enable for index 16 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN16 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN16 */ +#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHEN16 (0x1UL << 29) /**< FE notch enable for index 16 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN16_SHIFT 29 /**< Shift value for AGC_FENOTCHEN16 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN16_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN16 */ +#define _AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */ +#define AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */ + +/* Bit fields for AGC FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_RESETVALUE 0x200B200AUL /**< Default value for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL17 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL17 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE17 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE17 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE17 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE17 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHRATTNEN17 (0x1UL << 12) /**< FE notch rattn enable for index 17 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN17 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN17 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHEN17 (0x1UL << 13) /**< FE notch enable for index 17 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN17_SHIFT 13 /**< Shift value for AGC_FENOTCHEN17 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN17_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN17 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL18 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL18 */ +#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE18 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE18 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE18 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE18 */ +#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHRATTNEN18 (0x1UL << 28) /**< FE notch rattn enable for index 18 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN18 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN18 */ +#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHEN18 (0x1UL << 29) /**< FE notch enable for index 18 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN18_SHIFT 29 /**< Shift value for AGC_FENOTCHEN18 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN18_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN18 */ +#define _AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */ +#define AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */ + +/* Bit fields for AGC FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL19 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL19 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE19 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE19 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE19 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE19 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHRATTNEN19 (0x1UL << 12) /**< FE notch rattn enable for index 19 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN19 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN19 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHEN19 (0x1UL << 13) /**< FE notch enable for index 19 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN19_SHIFT 13 /**< Shift value for AGC_FENOTCHEN19 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN19_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN19 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL20 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL20 */ +#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE20 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE20 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE20 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE20 */ +#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHRATTNEN20 (0x1UL << 28) /**< FE notch rattn enable for index 20 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN20 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN20 */ +#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHEN20 (0x1UL << 29) /**< FE notch enable for index 20 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN20_SHIFT 29 /**< Shift value for AGC_FENOTCHEN20 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN20_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN20 */ +#define _AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */ +#define AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */ + +/* Bit fields for AGC FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL21 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL21 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE21 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE21 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE21 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE21 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHRATTNEN21 (0x1UL << 12) /**< FE notch rattn enable for index 21 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN21 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN21 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHEN21 (0x1UL << 13) /**< FE notch enable for index 21 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN21_SHIFT 13 /**< Shift value for AGC_FENOTCHEN21 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN21_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN21 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL22 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL22 */ +#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE22 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE22 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE22 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE22 */ +#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHRATTNEN22 (0x1UL << 28) /**< FE notch rattn enable for index 22 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN22 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN22 */ +#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHEN22 (0x1UL << 29) /**< FE notch enable for index 22 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN22_SHIFT 29 /**< Shift value for AGC_FENOTCHEN22 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN22_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN22 */ +#define _AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */ +#define AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */ + +/* Bit fields for AGC FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL23 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL23 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE23 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE23 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE23 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE23 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHRATTNEN23 (0x1UL << 12) /**< FE notch rattn enable for index 23 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN23 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN23 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHEN23 (0x1UL << 13) /**< FE notch enable for index 23 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN23_SHIFT 13 /**< Shift value for AGC_FENOTCHEN23 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN23_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN23 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL24 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL24 */ +#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE24 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE24 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE24 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE24 */ +#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHRATTNEN24 (0x1UL << 28) /**< FE notch rattn enable for index 24 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN24 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN24 */ +#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHEN24 (0x1UL << 29) /**< FE notch enable for index 24 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN24_SHIFT 29 /**< Shift value for AGC_FENOTCHEN24 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN24_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN24 */ +#define _AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */ +#define AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */ + +/* Bit fields for AGC CCADEBUG */ +#define _AGC_CCADEBUG_RESETVALUE 0x00000000UL /**< Default value for AGC_CCADEBUG */ +#define _AGC_CCADEBUG_MASK 0x000003FFUL /**< Mask for AGC_CCADEBUG */ +#define _AGC_CCADEBUG_DEBUGCCARSSI_SHIFT 0 /**< Shift value for AGC_DEBUGCCARSSI */ +#define _AGC_CCADEBUG_DEBUGCCARSSI_MASK 0xFFUL /**< Bit mask for AGC_DEBUGCCARSSI */ +#define _AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */ +#define AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT (_AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CCADEBUG */ +#define AGC_CCADEBUG_DEBUGCCAM1 (0x1UL << 8) /**< Mode 1 Clear Channel Assessment */ +#define _AGC_CCADEBUG_DEBUGCCAM1_SHIFT 8 /**< Shift value for AGC_DEBUGCCAM1 */ +#define _AGC_CCADEBUG_DEBUGCCAM1_MASK 0x100UL /**< Bit mask for AGC_DEBUGCCAM1 */ +#define _AGC_CCADEBUG_DEBUGCCAM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */ +#define AGC_CCADEBUG_DEBUGCCAM1_DEFAULT (_AGC_CCADEBUG_DEBUGCCAM1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CCADEBUG */ +#define AGC_CCADEBUG_DEBUGCCASIGDET (0x1UL << 9) /**< Signal detector Clear Channel Assessment */ +#define _AGC_CCADEBUG_DEBUGCCASIGDET_SHIFT 9 /**< Shift value for AGC_DEBUGCCASIGDET */ +#define _AGC_CCADEBUG_DEBUGCCASIGDET_MASK 0x200UL /**< Bit mask for AGC_DEBUGCCASIGDET */ +#define _AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */ +#define AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT (_AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_CCADEBUG */ + +/** @} End of group EFR32MG24_AGC_BitFields */ +/** @} End of group EFR32MG24_AGC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_AGC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_amuxcp.h b/EFR32MG24/Device/Include/efr32mg24_amuxcp.h new file mode 100644 index 0000000..83709fe --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_amuxcp.h @@ -0,0 +1,261 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 AMUXCP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_AMUXCP_H +#define EFR32MG24_AMUXCP_H +#define AMUXCP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_AMUXCP AMUXCP + * @{ + * @brief EFR32MG24 AMUXCP Register Declaration. + *****************************************************************************/ + +/** AMUXCP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t TEST; /**< Test */ + __IOM uint32_t TRIM; /**< Trim */ + uint32_t RESERVED1[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t TEST_SET; /**< Test */ + __IOM uint32_t TRIM_SET; /**< Trim */ + uint32_t RESERVED3[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t TEST_CLR; /**< Test */ + __IOM uint32_t TRIM_CLR; /**< Trim */ + uint32_t RESERVED5[1018U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t TEST_TGL; /**< Test */ + __IOM uint32_t TRIM_TGL; /**< Trim */ +} AMUXCP_TypeDef; +/** @} End of group EFR32MG24_AMUXCP */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_AMUXCP + * @{ + * @defgroup EFR32MG24_AMUXCP_BitFields AMUXCP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AMUXCP IPVERSION */ +#define _AMUXCP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AMUXCP_IPVERSION */ +#define _AMUXCP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_IPVERSION */ +#define AMUXCP_IPVERSION_IPVERSION_DEFAULT (_AMUXCP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_IPVERSION */ + +/* Bit fields for AMUXCP CTRL */ +#define _AMUXCP_CTRL_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_CTRL */ +#define _AMUXCP_CTRL_MASK 0x00000033UL /**< Mask for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCEHP (0x1UL << 0) /**< Force High Power */ +#define _AMUXCP_CTRL_FORCEHP_SHIFT 0 /**< Shift value for AMUXCP_FORCEHP */ +#define _AMUXCP_CTRL_FORCEHP_MASK 0x1UL /**< Bit mask for AMUXCP_FORCEHP */ +#define _AMUXCP_CTRL_FORCEHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCEHP_DEFAULT (_AMUXCP_CTRL_FORCEHP_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCELP (0x1UL << 1) /**< Force Low Power */ +#define _AMUXCP_CTRL_FORCELP_SHIFT 1 /**< Shift value for AMUXCP_FORCELP */ +#define _AMUXCP_CTRL_FORCELP_MASK 0x2UL /**< Bit mask for AMUXCP_FORCELP */ +#define _AMUXCP_CTRL_FORCELP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCELP_DEFAULT (_AMUXCP_CTRL_FORCELP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCERUN (0x1UL << 4) /**< Force run */ +#define _AMUXCP_CTRL_FORCERUN_SHIFT 4 /**< Shift value for AMUXCP_FORCERUN */ +#define _AMUXCP_CTRL_FORCERUN_MASK 0x10UL /**< Bit mask for AMUXCP_FORCERUN */ +#define _AMUXCP_CTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCERUN_DEFAULT (_AMUXCP_CTRL_FORCERUN_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCESTOP (0x1UL << 5) /**< Force stop */ +#define _AMUXCP_CTRL_FORCESTOP_SHIFT 5 /**< Shift value for AMUXCP_FORCESTOP */ +#define _AMUXCP_CTRL_FORCESTOP_MASK 0x20UL /**< Bit mask for AMUXCP_FORCESTOP */ +#define _AMUXCP_CTRL_FORCESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */ +#define AMUXCP_CTRL_FORCESTOP_DEFAULT (_AMUXCP_CTRL_FORCESTOP_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_CTRL */ + +/* Bit fields for AMUXCP STATUS */ +#define _AMUXCP_STATUS_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_STATUS */ +#define _AMUXCP_STATUS_MASK 0x00000003UL /**< Mask for AMUXCP_STATUS */ +#define AMUXCP_STATUS_RUN (0x1UL << 0) /**< running */ +#define _AMUXCP_STATUS_RUN_SHIFT 0 /**< Shift value for AMUXCP_RUN */ +#define _AMUXCP_STATUS_RUN_MASK 0x1UL /**< Bit mask for AMUXCP_RUN */ +#define _AMUXCP_STATUS_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_RUN_DEFAULT (_AMUXCP_STATUS_RUN_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_HICAP (0x1UL << 1) /**< high cap */ +#define _AMUXCP_STATUS_HICAP_SHIFT 1 /**< Shift value for AMUXCP_HICAP */ +#define _AMUXCP_STATUS_HICAP_MASK 0x2UL /**< Bit mask for AMUXCP_HICAP */ +#define _AMUXCP_STATUS_HICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */ +#define AMUXCP_STATUS_HICAP_DEFAULT (_AMUXCP_STATUS_HICAP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_STATUS */ + +/* Bit fields for AMUXCP TEST */ +#define _AMUXCP_TEST_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_TEST */ +#define _AMUXCP_TEST_MASK 0x80003313UL /**< Mask for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCCLK (0x1UL << 0) /**< Sync Clock */ +#define _AMUXCP_TEST_SYNCCLK_SHIFT 0 /**< Shift value for AMUXCP_SYNCCLK */ +#define _AMUXCP_TEST_SYNCCLK_MASK 0x1UL /**< Bit mask for AMUXCP_SYNCCLK */ +#define _AMUXCP_TEST_SYNCCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCCLK_DEFAULT (_AMUXCP_TEST_SYNCCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCMODE (0x1UL << 1) /**< Sync Mode */ +#define _AMUXCP_TEST_SYNCMODE_SHIFT 1 /**< Shift value for AMUXCP_SYNCMODE */ +#define _AMUXCP_TEST_SYNCMODE_MASK 0x2UL /**< Bit mask for AMUXCP_SYNCMODE */ +#define _AMUXCP_TEST_SYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_SYNCMODE_DEFAULT (_AMUXCP_TEST_SYNCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEREQUEST (0x1UL << 4) /**< Force Request */ +#define _AMUXCP_TEST_FORCEREQUEST_SHIFT 4 /**< Shift value for AMUXCP_FORCEREQUEST */ +#define _AMUXCP_TEST_FORCEREQUEST_MASK 0x10UL /**< Bit mask for AMUXCP_FORCEREQUEST */ +#define _AMUXCP_TEST_FORCEREQUEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEREQUEST_DEFAULT (_AMUXCP_TEST_FORCEREQUEST_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEHICAP (0x1UL << 8) /**< Force high capacitance driver */ +#define _AMUXCP_TEST_FORCEHICAP_SHIFT 8 /**< Shift value for AMUXCP_FORCEHICAP */ +#define _AMUXCP_TEST_FORCEHICAP_MASK 0x100UL /**< Bit mask for AMUXCP_FORCEHICAP */ +#define _AMUXCP_TEST_FORCEHICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEHICAP_DEFAULT (_AMUXCP_TEST_FORCEHICAP_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCELOCAP (0x1UL << 9) /**< Force low capacitance driver */ +#define _AMUXCP_TEST_FORCELOCAP_SHIFT 9 /**< Shift value for AMUXCP_FORCELOCAP */ +#define _AMUXCP_TEST_FORCELOCAP_MASK 0x200UL /**< Bit mask for AMUXCP_FORCELOCAP */ +#define _AMUXCP_TEST_FORCELOCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCELOCAP_DEFAULT (_AMUXCP_TEST_FORCELOCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTON (0x1UL << 12) /**< Force Boost On */ +#define _AMUXCP_TEST_FORCEBOOSTON_SHIFT 12 /**< Shift value for AMUXCP_FORCEBOOSTON */ +#define _AMUXCP_TEST_FORCEBOOSTON_MASK 0x1000UL /**< Bit mask for AMUXCP_FORCEBOOSTON */ +#define _AMUXCP_TEST_FORCEBOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTON_DEFAULT (_AMUXCP_TEST_FORCEBOOSTON_DEFAULT << 12) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTOFF (0x1UL << 13) /**< Force Boost Off */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_SHIFT 13 /**< Shift value for AMUXCP_FORCEBOOSTOFF */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_MASK 0x2000UL /**< Bit mask for AMUXCP_FORCEBOOSTOFF */ +#define _AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT (_AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_STATUSEN (0x1UL << 31) /**< Enable write to status bits */ +#define _AMUXCP_TEST_STATUSEN_SHIFT 31 /**< Shift value for AMUXCP_STATUSEN */ +#define _AMUXCP_TEST_STATUSEN_MASK 0x80000000UL /**< Bit mask for AMUXCP_STATUSEN */ +#define _AMUXCP_TEST_STATUSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */ +#define AMUXCP_TEST_STATUSEN_DEFAULT (_AMUXCP_TEST_STATUSEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AMUXCP_TEST */ + +/* Bit fields for AMUXCP TRIM */ +#define _AMUXCP_TRIM_RESETVALUE 0x77E44AB1UL /**< Default value for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_MASK 0x77FFEFFFUL /**< Mask for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_SHIFT 0 /**< Shift value for AMUXCP_WARMUPTIME */ +#define _AMUXCP_TRIM_WARMUPTIME_MASK 0x3UL /**< Bit mask for AMUXCP_WARMUPTIME */ +#define _AMUXCP_TRIM_WARMUPTIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 0x00000000UL /**< Mode WUCYCLES72 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 0x00000001UL /**< Mode WUCYCLES96 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 0x00000002UL /**< Mode WUCYCLES128 for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 0x00000003UL /**< Mode WUCYCLES160 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_DEFAULT (_AMUXCP_TRIM_WARMUPTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 << 0) /**< Shifted mode WUCYCLES72 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 << 0) /**< Shifted mode WUCYCLES96 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 << 0) /**< Shifted mode WUCYCLES128 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 << 0) /**< Shifted mode WUCYCLES160 for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPLO (0x1UL << 2) /**< Float VDDCP Low Power */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_SHIFT 2 /**< Shift value for AMUXCP_FLOATVDDCPLO */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_MASK 0x4UL /**< Bit mask for AMUXCP_FLOATVDDCPLO */ +#define _AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT << 2) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPHI (0x1UL << 3) /**< Float VDDCP High Power */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_SHIFT 3 /**< Shift value for AMUXCP_FLOATVDDCPHI */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_MASK 0x8UL /**< Bit mask for AMUXCP_FLOATVDDCPHI */ +#define _AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT << 3) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2LO (0x1UL << 4) /**< Bypass Div2 Low Power */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_SHIFT 4 /**< Shift value for AMUXCP_BYPASSDIV2LO */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_MASK 0x10UL /**< Bit mask for AMUXCP_BYPASSDIV2LO */ +#define _AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2HI (0x1UL << 5) /**< Bypass Div2 High Power */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_SHIFT 5 /**< Shift value for AMUXCP_BYPASSDIV2HI */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_MASK 0x20UL /**< Bit mask for AMUXCP_BYPASSDIV2HI */ +#define _AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XLO (0x1UL << 6) /**< Bump 0.5X Low Power */ +#define _AMUXCP_TRIM_BUMP0P5XLO_SHIFT 6 /**< Shift value for AMUXCP_BUMP0P5XLO */ +#define _AMUXCP_TRIM_BUMP0P5XLO_MASK 0x40UL /**< Bit mask for AMUXCP_BUMP0P5XLO */ +#define _AMUXCP_TRIM_BUMP0P5XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XLO_DEFAULT (_AMUXCP_TRIM_BUMP0P5XLO_DEFAULT << 6) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XHI (0x1UL << 7) /**< Bump 0.5X High Power */ +#define _AMUXCP_TRIM_BUMP0P5XHI_SHIFT 7 /**< Shift value for AMUXCP_BUMP0P5XHI */ +#define _AMUXCP_TRIM_BUMP0P5XHI_MASK 0x80UL /**< Bit mask for AMUXCP_BUMP0P5XHI */ +#define _AMUXCP_TRIM_BUMP0P5XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BUMP0P5XHI_DEFAULT (_AMUXCP_TRIM_BUMP0P5XHI_DEFAULT << 7) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XLO (0x1UL << 8) /**< Bias 2x Low Power */ +#define _AMUXCP_TRIM_BIAS2XLO_SHIFT 8 /**< Shift value for AMUXCP_BIAS2XLO */ +#define _AMUXCP_TRIM_BIAS2XLO_MASK 0x100UL /**< Bit mask for AMUXCP_BIAS2XLO */ +#define _AMUXCP_TRIM_BIAS2XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XLO_DEFAULT (_AMUXCP_TRIM_BIAS2XLO_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XHI (0x1UL << 9) /**< Bias 2x High Power */ +#define _AMUXCP_TRIM_BIAS2XHI_SHIFT 9 /**< Shift value for AMUXCP_BIAS2XHI */ +#define _AMUXCP_TRIM_BIAS2XHI_MASK 0x200UL /**< Bit mask for AMUXCP_BIAS2XHI */ +#define _AMUXCP_TRIM_BIAS2XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIAS2XHI_DEFAULT (_AMUXCP_TRIM_BIAS2XHI_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_SHIFT 10 /**< Shift value for AMUXCP_VOLTAGECTRLLO */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_MASK 0xC00UL /**< Bit mask for AMUXCP_VOLTAGECTRLLO */ +#define _AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT << 10) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_SHIFT 13 /**< Shift value for AMUXCP_VOLTAGECTRLHI */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_MASK 0x6000UL /**< Bit mask for AMUXCP_VOLTAGECTRLHI */ +#define _AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLLO_SHIFT 15 /**< Shift value for AMUXCP_BIASCTRLLO */ +#define _AMUXCP_TRIM_BIASCTRLLO_MASK 0x38000UL /**< Bit mask for AMUXCP_BIASCTRLLO */ +#define _AMUXCP_TRIM_BIASCTRLLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLLO_DEFAULT (_AMUXCP_TRIM_BIASCTRLLO_DEFAULT << 15) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_SHIFT 18 /**< Shift value for AMUXCP_BIASCTRLLOCONT */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_MASK 0x1C0000UL /**< Bit mask for AMUXCP_BIASCTRLLOCONT */ +#define _AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT (_AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT << 18) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_BIASCTRLHI_SHIFT 21 /**< Shift value for AMUXCP_BIASCTRLHI */ +#define _AMUXCP_TRIM_BIASCTRLHI_MASK 0xE00000UL /**< Bit mask for AMUXCP_BIASCTRLHI */ +#define _AMUXCP_TRIM_BIASCTRLHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_BIASCTRLHI_DEFAULT (_AMUXCP_TRIM_BIASCTRLHI_DEFAULT << 21) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_PUMPCAPLO_SHIFT 24 /**< Shift value for AMUXCP_PUMPCAPLO */ +#define _AMUXCP_TRIM_PUMPCAPLO_MASK 0x7000000UL /**< Bit mask for AMUXCP_PUMPCAPLO */ +#define _AMUXCP_TRIM_PUMPCAPLO_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_PUMPCAPLO_DEFAULT (_AMUXCP_TRIM_PUMPCAPLO_DEFAULT << 24) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ +#define _AMUXCP_TRIM_PUMPCAPHI_SHIFT 28 /**< Shift value for AMUXCP_PUMPCAPHI */ +#define _AMUXCP_TRIM_PUMPCAPHI_MASK 0x70000000UL /**< Bit mask for AMUXCP_PUMPCAPHI */ +#define _AMUXCP_TRIM_PUMPCAPHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */ +#define AMUXCP_TRIM_PUMPCAPHI_DEFAULT (_AMUXCP_TRIM_PUMPCAPHI_DEFAULT << 28) /**< Shifted mode DEFAULT for AMUXCP_TRIM */ + +/** @} End of group EFR32MG24_AMUXCP_BitFields */ +/** @} End of group EFR32MG24_AMUXCP */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_AMUXCP_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_bufc.h b/EFR32MG24/Device/Include/efr32mg24_bufc.h new file mode 100644 index 0000000..062b34f --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_bufc.h @@ -0,0 +1,746 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 BUFC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_BUFC_H +#define EFR32MG24_BUFC_H +#define BUFC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_BUFC BUFC + * @{ + * @brief EFR32MG24 BUFC Register Declaration. + *****************************************************************************/ + +/** BUFC BUF Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Buffer Control */ + __IOM uint32_t ADDR; /**< Buffer Address */ + __IOM uint32_t WRITEOFFSET; /**< Write Offset */ + __IOM uint32_t READOFFSET; /**< Read Offset */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t READDATA; /**< Buffer Read Data */ + __IOM uint32_t WRITEDATA; /**< Buffer Write Data */ + __IOM uint32_t XWRITE; /**< Buffer XOR Write */ + __IM uint32_t STATUS; /**< Buffer Status Register */ + __IOM uint32_t THRESHOLDCTRL; /**< Threshold Control */ + __IOM uint32_t CMD; /**< Buffer Command */ + __IOM uint32_t FIFOASYNC; /**< New Register */ + __IM uint32_t READDATA32; /**< Buffer Read Data */ + __IOM uint32_t WRITEDATA32; /**< Buffer Write Data */ + __IOM uint32_t XWRITE32; /**< Buffer XOR Write */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} BUFC_BUF_TypeDef; + +/** BUFC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IOM uint32_t LPMODE; /**< Low power mode control */ + BUFC_BUF_TypeDef BUF[4U]; /**< Data Buffer */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< BUFC Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQIF; /**< SEQ BUFC Interrupt Flags */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t AHBCONFIG; /**< AHB Configuration */ + uint32_t RESERVED1[950U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IOM uint32_t LPMODE_SET; /**< Low power mode control */ + BUFC_BUF_TypeDef BUF_SET[4U]; /**< Data Buffer */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< BUFC Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t SEQIF_SET; /**< SEQ BUFC Interrupt Flags */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t AHBCONFIG_SET; /**< AHB Configuration */ + uint32_t RESERVED3[950U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IOM uint32_t LPMODE_CLR; /**< Low power mode control */ + BUFC_BUF_TypeDef BUF_CLR[4U]; /**< Data Buffer */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< BUFC Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t SEQIF_CLR; /**< SEQ BUFC Interrupt Flags */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t AHBCONFIG_CLR; /**< AHB Configuration */ + uint32_t RESERVED5[950U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IOM uint32_t LPMODE_TGL; /**< Low power mode control */ + BUFC_BUF_TypeDef BUF_TGL[4U]; /**< Data Buffer */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< BUFC Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t SEQIF_TGL; /**< SEQ BUFC Interrupt Flags */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t AHBCONFIG_TGL; /**< AHB Configuration */ +} BUFC_TypeDef; +/** @} End of group EFR32MG24_BUFC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_BUFC + * @{ + * @defgroup EFR32MG24_BUFC_BitFields BUFC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BUFC IPVERSION */ +#define _BUFC_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for BUFC_IPVERSION */ +#define _BUFC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BUFC_IPVERSION */ +#define _BUFC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BUFC_IPVERSION */ +#define _BUFC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_IPVERSION */ +#define _BUFC_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for BUFC_IPVERSION */ +#define BUFC_IPVERSION_IPVERSION_DEFAULT (_BUFC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IPVERSION */ + +/* Bit fields for BUFC EN */ +#define _BUFC_EN_RESETVALUE 0x00000000UL /**< Default value for BUFC_EN */ +#define _BUFC_EN_MASK 0x00000001UL /**< Mask for BUFC_EN */ +#define BUFC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _BUFC_EN_EN_SHIFT 0 /**< Shift value for BUFC_EN */ +#define _BUFC_EN_EN_MASK 0x1UL /**< Bit mask for BUFC_EN */ +#define _BUFC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_EN */ +#define BUFC_EN_EN_DEFAULT (_BUFC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_EN */ + +/* Bit fields for BUFC LPMODE */ +#define _BUFC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BUFC_LPMODE */ +#define _BUFC_LPMODE_MASK 0x00000003UL /**< Mask for BUFC_LPMODE */ +#define BUFC_LPMODE_LPENBYSEQ (0x1UL << 0) /**< Low power mode enable from sequencer */ +#define _BUFC_LPMODE_LPENBYSEQ_SHIFT 0 /**< Shift value for BUFC_LPENBYSEQ */ +#define _BUFC_LPMODE_LPENBYSEQ_MASK 0x1UL /**< Bit mask for BUFC_LPENBYSEQ */ +#define _BUFC_LPMODE_LPENBYSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */ +#define BUFC_LPMODE_LPENBYSEQ_DEFAULT (_BUFC_LPMODE_LPENBYSEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_LPMODE */ +#define BUFC_LPMODE_LPENBYM33 (0x1UL << 1) /**< Low power mode enable from M33 */ +#define _BUFC_LPMODE_LPENBYM33_SHIFT 1 /**< Shift value for BUFC_LPENBYM33 */ +#define _BUFC_LPMODE_LPENBYM33_MASK 0x2UL /**< Bit mask for BUFC_LPENBYM33 */ +#define _BUFC_LPMODE_LPENBYM33_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */ +#define BUFC_LPMODE_LPENBYM33_DEFAULT (_BUFC_LPMODE_LPENBYM33_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_LPMODE */ + +/* Bit fields for BUFC BUF_CTRL */ +#define _BUFC_BUF_CTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_MASK 0x00000007UL /**< Mask for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SHIFT 0 /**< Shift value for BUFC_SIZE */ +#define _BUFC_BUF_CTRL_SIZE_MASK 0x7UL /**< Bit mask for BUFC_SIZE */ +#define _BUFC_BUF_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE64 0x00000000UL /**< Mode SIZE64 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE128 0x00000001UL /**< Mode SIZE128 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE256 0x00000002UL /**< Mode SIZE256 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE512 0x00000003UL /**< Mode SIZE512 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE1024 0x00000004UL /**< Mode SIZE1024 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE2048 0x00000005UL /**< Mode SIZE2048 for BUFC_BUF_CTRL */ +#define _BUFC_BUF_CTRL_SIZE_SIZE4096 0x00000006UL /**< Mode SIZE4096 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_DEFAULT (_BUFC_BUF_CTRL_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE64 (_BUFC_BUF_CTRL_SIZE_SIZE64 << 0) /**< Shifted mode SIZE64 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE128 (_BUFC_BUF_CTRL_SIZE_SIZE128 << 0) /**< Shifted mode SIZE128 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE256 (_BUFC_BUF_CTRL_SIZE_SIZE256 << 0) /**< Shifted mode SIZE256 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE512 (_BUFC_BUF_CTRL_SIZE_SIZE512 << 0) /**< Shifted mode SIZE512 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE1024 (_BUFC_BUF_CTRL_SIZE_SIZE1024 << 0) /**< Shifted mode SIZE1024 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE2048 (_BUFC_BUF_CTRL_SIZE_SIZE2048 << 0) /**< Shifted mode SIZE2048 for BUFC_BUF_CTRL */ +#define BUFC_BUF_CTRL_SIZE_SIZE4096 (_BUFC_BUF_CTRL_SIZE_SIZE4096 << 0) /**< Shifted mode SIZE4096 for BUFC_BUF_CTRL */ + +/* Bit fields for BUFC BUF_ADDR */ +#define _BUFC_BUF_ADDR_RESETVALUE 0x20000000UL /**< Default value for BUFC_BUF_ADDR */ +#define _BUFC_BUF_ADDR_MASK 0xFFFFFFFCUL /**< Mask for BUFC_BUF_ADDR */ +#define _BUFC_BUF_ADDR_ADDR_SHIFT 2 /**< Shift value for BUFC_ADDR */ +#define _BUFC_BUF_ADDR_ADDR_MASK 0xFFFFFFFCUL /**< Bit mask for BUFC_ADDR */ +#define _BUFC_BUF_ADDR_ADDR_DEFAULT 0x08000000UL /**< Mode DEFAULT for BUFC_BUF_ADDR */ +#define BUFC_BUF_ADDR_ADDR_DEFAULT (_BUFC_BUF_ADDR_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_BUF_ADDR */ + +/* Bit fields for BUFC BUF_WRITEOFFSET */ +#define _BUFC_BUF_WRITEOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEOFFSET */ +#define _BUFC_BUF_WRITEOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_WRITEOFFSET */ +#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_SHIFT 0 /**< Shift value for BUFC_WRITEOFFSET */ +#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_WRITEOFFSET */ +#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEOFFSET */ +#define BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT (_BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEOFFSET*/ + +/* Bit fields for BUFC BUF_READOFFSET */ +#define _BUFC_BUF_READOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READOFFSET */ +#define _BUFC_BUF_READOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_READOFFSET */ +#define _BUFC_BUF_READOFFSET_READOFFSET_SHIFT 0 /**< Shift value for BUFC_READOFFSET */ +#define _BUFC_BUF_READOFFSET_READOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_READOFFSET */ +#define _BUFC_BUF_READOFFSET_READOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READOFFSET */ +#define BUFC_BUF_READOFFSET_READOFFSET_DEFAULT (_BUFC_BUF_READOFFSET_READOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READOFFSET*/ + +/* Bit fields for BUFC BUF_READDATA */ +#define _BUFC_BUF_READDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA */ +#define _BUFC_BUF_READDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_READDATA */ +#define _BUFC_BUF_READDATA_READDATA_SHIFT 0 /**< Shift value for BUFC_READDATA */ +#define _BUFC_BUF_READDATA_READDATA_MASK 0xFFUL /**< Bit mask for BUFC_READDATA */ +#define _BUFC_BUF_READDATA_READDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA */ +#define BUFC_BUF_READDATA_READDATA_DEFAULT (_BUFC_BUF_READDATA_READDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA */ + +/* Bit fields for BUFC BUF_WRITEDATA */ +#define _BUFC_BUF_WRITEDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA */ +#define _BUFC_BUF_WRITEDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_WRITEDATA */ +#define _BUFC_BUF_WRITEDATA_WRITEDATA_SHIFT 0 /**< Shift value for BUFC_WRITEDATA */ +#define _BUFC_BUF_WRITEDATA_WRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_WRITEDATA */ +#define _BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA */ +#define BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT (_BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA */ + +/* Bit fields for BUFC BUF_XWRITE */ +#define _BUFC_BUF_XWRITE_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE */ +#define _BUFC_BUF_XWRITE_MASK 0x000000FFUL /**< Mask for BUFC_BUF_XWRITE */ +#define _BUFC_BUF_XWRITE_XORWRITEDATA_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA */ +#define _BUFC_BUF_XWRITE_XORWRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_XORWRITEDATA */ +#define _BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE */ +#define BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT (_BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE */ + +/* Bit fields for BUFC BUF_STATUS */ +#define _BUFC_BUF_STATUS_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_STATUS */ +#define _BUFC_BUF_STATUS_MASK 0x01111FFFUL /**< Mask for BUFC_BUF_STATUS */ +#define _BUFC_BUF_STATUS_BYTES_SHIFT 0 /**< Shift value for BUFC_BYTES */ +#define _BUFC_BUF_STATUS_BYTES_MASK 0x1FFFUL /**< Bit mask for BUFC_BYTES */ +#define _BUFC_BUF_STATUS_BYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */ +#define BUFC_BUF_STATUS_BYTES_DEFAULT (_BUFC_BUF_STATUS_BYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */ +#define BUFC_BUF_STATUS_THRESHOLDFLAG (0x1UL << 20) /**< Buffer Threshold Flag */ +#define _BUFC_BUF_STATUS_THRESHOLDFLAG_SHIFT 20 /**< Shift value for BUFC_THRESHOLDFLAG */ +#define _BUFC_BUF_STATUS_THRESHOLDFLAG_MASK 0x100000UL /**< Bit mask for BUFC_THRESHOLDFLAG */ +#define _BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */ +#define BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT (_BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */ + +/* Bit fields for BUFC BUF_THRESHOLDCTRL */ +#define _BUFC_BUF_THRESHOLDCTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_THRESHOLDCTRL */ +#define _BUFC_BUF_THRESHOLDCTRL_MASK 0x00003FFFUL /**< Mask for BUFC_BUF_THRESHOLDCTRL */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_SHIFT 0 /**< Shift value for BUFC_THRESHOLD */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_MASK 0x1FFFUL /**< Bit mask for BUFC_THRESHOLD */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */ +#define BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/ +#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE (0x1UL << 13) /**< Buffer Threshold Mode */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_SHIFT 13 /**< Shift value for BUFC_THRESHOLDMODE */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_MASK 0x2000UL /**< Bit mask for BUFC_THRESHOLDMODE */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER 0x00000000UL /**< Mode LARGER for BUFC_BUF_THRESHOLDCTRL */ +#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL 0x00000001UL /**< Mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL */ +#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/ +#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER << 13) /**< Shifted mode LARGER for BUFC_BUF_THRESHOLDCTRL*/ +#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL << 13) /**< Shifted mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL*/ + +/* Bit fields for BUFC BUF_CMD */ +#define _BUFC_BUF_CMD_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CMD */ +#define _BUFC_BUF_CMD_MASK 0x0000000FUL /**< Mask for BUFC_BUF_CMD */ +#define BUFC_BUF_CMD_CLEAR (0x1UL << 0) /**< Buffer Clear */ +#define _BUFC_BUF_CMD_CLEAR_SHIFT 0 /**< Shift value for BUFC_CLEAR */ +#define _BUFC_BUF_CMD_CLEAR_MASK 0x1UL /**< Bit mask for BUFC_CLEAR */ +#define _BUFC_BUF_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */ +#define BUFC_BUF_CMD_CLEAR_DEFAULT (_BUFC_BUF_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */ +#define BUFC_BUF_CMD_PREFETCH (0x1UL << 1) /**< Prefetch */ +#define _BUFC_BUF_CMD_PREFETCH_SHIFT 1 /**< Shift value for BUFC_PREFETCH */ +#define _BUFC_BUF_CMD_PREFETCH_MASK 0x2UL /**< Bit mask for BUFC_PREFETCH */ +#define _BUFC_BUF_CMD_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */ +#define BUFC_BUF_CMD_PREFETCH_DEFAULT (_BUFC_BUF_CMD_PREFETCH_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */ + +/* Bit fields for BUFC BUF_FIFOASYNC */ +#define _BUFC_BUF_FIFOASYNC_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_FIFOASYNC */ +#define _BUFC_BUF_FIFOASYNC_MASK 0x00000001UL /**< Mask for BUFC_BUF_FIFOASYNC */ +#define BUFC_BUF_FIFOASYNC_RST (0x1UL << 0) /**< Reset ASYNC */ +#define _BUFC_BUF_FIFOASYNC_RST_SHIFT 0 /**< Shift value for BUFC_RST */ +#define _BUFC_BUF_FIFOASYNC_RST_MASK 0x1UL /**< Bit mask for BUFC_RST */ +#define _BUFC_BUF_FIFOASYNC_RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_FIFOASYNC */ +#define BUFC_BUF_FIFOASYNC_RST_DEFAULT (_BUFC_BUF_FIFOASYNC_RST_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_FIFOASYNC */ + +/* Bit fields for BUFC BUF_READDATA32 */ +#define _BUFC_BUF_READDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA32 */ +#define _BUFC_BUF_READDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_READDATA32 */ +#define _BUFC_BUF_READDATA32_READDATA32_SHIFT 0 /**< Shift value for BUFC_READDATA32 */ +#define _BUFC_BUF_READDATA32_READDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_READDATA32 */ +#define _BUFC_BUF_READDATA32_READDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA32 */ +#define BUFC_BUF_READDATA32_READDATA32_DEFAULT (_BUFC_BUF_READDATA32_READDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA32*/ + +/* Bit fields for BUFC BUF_WRITEDATA32 */ +#define _BUFC_BUF_WRITEDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA32 */ +#define _BUFC_BUF_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_WRITEDATA32 */ +#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_SHIFT 0 /**< Shift value for BUFC_WRITEDATA32 */ +#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_WRITEDATA32 */ +#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA32 */ +#define BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT (_BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA32*/ + +/* Bit fields for BUFC BUF_XWRITE32 */ +#define _BUFC_BUF_XWRITE32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE32 */ +#define _BUFC_BUF_XWRITE32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_XWRITE32 */ +#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA32 */ +#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_XORWRITEDATA32 */ +#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE32 */ +#define BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT (_BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE32 */ + +/* Bit fields for BUFC IF */ +#define _BUFC_IF_RESETVALUE 0x00000000UL /**< Default value for BUFC_IF */ +#define _BUFC_IF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IF */ +#define BUFC_IF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */ +#define _BUFC_IF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ +#define _BUFC_IF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ +#define _BUFC_IF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0OF_DEFAULT (_BUFC_IF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */ +#define _BUFC_IF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ +#define _BUFC_IF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ +#define _BUFC_IF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0UF_DEFAULT (_BUFC_IF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */ +#define _BUFC_IF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ +#define _BUFC_IF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ +#define _BUFC_IF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0THR_DEFAULT (_BUFC_IF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */ +#define _BUFC_IF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ +#define _BUFC_IF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ +#define _BUFC_IF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0CORR_DEFAULT (_BUFC_IF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */ +#define _BUFC_IF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */ +#define _BUFC_IF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */ +#define _BUFC_IF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF0NWA_DEFAULT (_BUFC_IF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */ +#define _BUFC_IF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ +#define _BUFC_IF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ +#define _BUFC_IF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1OF_DEFAULT (_BUFC_IF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */ +#define _BUFC_IF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ +#define _BUFC_IF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ +#define _BUFC_IF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1UF_DEFAULT (_BUFC_IF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */ +#define _BUFC_IF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ +#define _BUFC_IF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ +#define _BUFC_IF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1THR_DEFAULT (_BUFC_IF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */ +#define _BUFC_IF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ +#define _BUFC_IF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ +#define _BUFC_IF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1CORR_DEFAULT (_BUFC_IF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */ +#define _BUFC_IF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */ +#define _BUFC_IF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */ +#define _BUFC_IF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF1NWA_DEFAULT (_BUFC_IF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */ +#define _BUFC_IF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ +#define _BUFC_IF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ +#define _BUFC_IF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2OF_DEFAULT (_BUFC_IF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */ +#define _BUFC_IF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ +#define _BUFC_IF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ +#define _BUFC_IF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2UF_DEFAULT (_BUFC_IF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */ +#define _BUFC_IF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ +#define _BUFC_IF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ +#define _BUFC_IF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2THR_DEFAULT (_BUFC_IF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */ +#define _BUFC_IF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ +#define _BUFC_IF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ +#define _BUFC_IF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2CORR_DEFAULT (_BUFC_IF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */ +#define _BUFC_IF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */ +#define _BUFC_IF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */ +#define _BUFC_IF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF2NWA_DEFAULT (_BUFC_IF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */ +#define _BUFC_IF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ +#define _BUFC_IF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ +#define _BUFC_IF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3OF_DEFAULT (_BUFC_IF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */ +#define _BUFC_IF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ +#define _BUFC_IF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ +#define _BUFC_IF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3UF_DEFAULT (_BUFC_IF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */ +#define _BUFC_IF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ +#define _BUFC_IF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ +#define _BUFC_IF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3THR_DEFAULT (_BUFC_IF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */ +#define _BUFC_IF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ +#define _BUFC_IF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ +#define _BUFC_IF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3CORR_DEFAULT (_BUFC_IF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */ +#define _BUFC_IF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */ +#define _BUFC_IF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */ +#define _BUFC_IF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUF3NWA_DEFAULT (_BUFC_IF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUSERROR (0x1UL << 31) /**< Bus Error */ +#define _BUFC_IF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ +#define _BUFC_IF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ +#define _BUFC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ +#define BUFC_IF_BUSERROR_DEFAULT (_BUFC_IF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IF */ + +/* Bit fields for BUFC IEN */ +#define _BUFC_IEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_IEN */ +#define _BUFC_IEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IEN */ +#define BUFC_IEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */ +#define _BUFC_IEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ +#define _BUFC_IEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ +#define _BUFC_IEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0OF_DEFAULT (_BUFC_IEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */ +#define _BUFC_IEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ +#define _BUFC_IEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ +#define _BUFC_IEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0UF_DEFAULT (_BUFC_IEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */ +#define _BUFC_IEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ +#define _BUFC_IEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ +#define _BUFC_IEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0THR_DEFAULT (_BUFC_IEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */ +#define _BUFC_IEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ +#define _BUFC_IEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ +#define _BUFC_IEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0CORR_DEFAULT (_BUFC_IEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */ +#define _BUFC_IEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */ +#define _BUFC_IEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */ +#define _BUFC_IEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF0NWA_DEFAULT (_BUFC_IEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */ +#define _BUFC_IEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ +#define _BUFC_IEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ +#define _BUFC_IEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1OF_DEFAULT (_BUFC_IEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */ +#define _BUFC_IEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ +#define _BUFC_IEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ +#define _BUFC_IEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1UF_DEFAULT (_BUFC_IEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */ +#define _BUFC_IEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ +#define _BUFC_IEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ +#define _BUFC_IEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1THR_DEFAULT (_BUFC_IEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */ +#define _BUFC_IEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ +#define _BUFC_IEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ +#define _BUFC_IEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1CORR_DEFAULT (_BUFC_IEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */ +#define _BUFC_IEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */ +#define _BUFC_IEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */ +#define _BUFC_IEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF1NWA_DEFAULT (_BUFC_IEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */ +#define _BUFC_IEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ +#define _BUFC_IEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ +#define _BUFC_IEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2OF_DEFAULT (_BUFC_IEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */ +#define _BUFC_IEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ +#define _BUFC_IEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ +#define _BUFC_IEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2UF_DEFAULT (_BUFC_IEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */ +#define _BUFC_IEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ +#define _BUFC_IEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ +#define _BUFC_IEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2THR_DEFAULT (_BUFC_IEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */ +#define _BUFC_IEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ +#define _BUFC_IEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ +#define _BUFC_IEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2CORR_DEFAULT (_BUFC_IEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */ +#define _BUFC_IEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */ +#define _BUFC_IEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */ +#define _BUFC_IEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF2NWA_DEFAULT (_BUFC_IEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */ +#define _BUFC_IEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ +#define _BUFC_IEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ +#define _BUFC_IEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3OF_DEFAULT (_BUFC_IEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */ +#define _BUFC_IEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ +#define _BUFC_IEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ +#define _BUFC_IEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3UF_DEFAULT (_BUFC_IEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */ +#define _BUFC_IEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ +#define _BUFC_IEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ +#define _BUFC_IEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3THR_DEFAULT (_BUFC_IEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */ +#define _BUFC_IEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ +#define _BUFC_IEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ +#define _BUFC_IEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3CORR_DEFAULT (_BUFC_IEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */ +#define _BUFC_IEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */ +#define _BUFC_IEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */ +#define _BUFC_IEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUF3NWA_DEFAULT (_BUFC_IEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */ +#define _BUFC_IEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ +#define _BUFC_IEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ +#define _BUFC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ +#define BUFC_IEN_BUSERROR_DEFAULT (_BUFC_IEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IEN */ + +/* Bit fields for BUFC SEQIF */ +#define _BUFC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIF */ +#define _BUFC_SEQIF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */ +#define _BUFC_SEQIF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ +#define _BUFC_SEQIF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ +#define _BUFC_SEQIF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0OF_DEFAULT (_BUFC_SEQIF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */ +#define _BUFC_SEQIF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ +#define _BUFC_SEQIF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ +#define _BUFC_SEQIF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0UF_DEFAULT (_BUFC_SEQIF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */ +#define _BUFC_SEQIF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ +#define _BUFC_SEQIF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ +#define _BUFC_SEQIF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0THR_DEFAULT (_BUFC_SEQIF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */ +#define _BUFC_SEQIF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ +#define _BUFC_SEQIF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ +#define _BUFC_SEQIF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0CORR_DEFAULT (_BUFC_SEQIF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */ +#define _BUFC_SEQIF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */ +#define _BUFC_SEQIF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */ +#define _BUFC_SEQIF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF0NWA_DEFAULT (_BUFC_SEQIF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */ +#define _BUFC_SEQIF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ +#define _BUFC_SEQIF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ +#define _BUFC_SEQIF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1OF_DEFAULT (_BUFC_SEQIF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */ +#define _BUFC_SEQIF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ +#define _BUFC_SEQIF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ +#define _BUFC_SEQIF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1UF_DEFAULT (_BUFC_SEQIF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */ +#define _BUFC_SEQIF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ +#define _BUFC_SEQIF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ +#define _BUFC_SEQIF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1THR_DEFAULT (_BUFC_SEQIF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */ +#define _BUFC_SEQIF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ +#define _BUFC_SEQIF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ +#define _BUFC_SEQIF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1CORR_DEFAULT (_BUFC_SEQIF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */ +#define _BUFC_SEQIF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */ +#define _BUFC_SEQIF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */ +#define _BUFC_SEQIF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF1NWA_DEFAULT (_BUFC_SEQIF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */ +#define _BUFC_SEQIF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ +#define _BUFC_SEQIF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ +#define _BUFC_SEQIF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2OF_DEFAULT (_BUFC_SEQIF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */ +#define _BUFC_SEQIF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ +#define _BUFC_SEQIF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ +#define _BUFC_SEQIF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2UF_DEFAULT (_BUFC_SEQIF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */ +#define _BUFC_SEQIF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ +#define _BUFC_SEQIF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ +#define _BUFC_SEQIF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2THR_DEFAULT (_BUFC_SEQIF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */ +#define _BUFC_SEQIF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ +#define _BUFC_SEQIF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ +#define _BUFC_SEQIF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2CORR_DEFAULT (_BUFC_SEQIF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */ +#define _BUFC_SEQIF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */ +#define _BUFC_SEQIF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */ +#define _BUFC_SEQIF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF2NWA_DEFAULT (_BUFC_SEQIF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */ +#define _BUFC_SEQIF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ +#define _BUFC_SEQIF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ +#define _BUFC_SEQIF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3OF_DEFAULT (_BUFC_SEQIF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */ +#define _BUFC_SEQIF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ +#define _BUFC_SEQIF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ +#define _BUFC_SEQIF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3UF_DEFAULT (_BUFC_SEQIF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */ +#define _BUFC_SEQIF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ +#define _BUFC_SEQIF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ +#define _BUFC_SEQIF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3THR_DEFAULT (_BUFC_SEQIF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */ +#define _BUFC_SEQIF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ +#define _BUFC_SEQIF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ +#define _BUFC_SEQIF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3CORR_DEFAULT (_BUFC_SEQIF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */ +#define _BUFC_SEQIF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */ +#define _BUFC_SEQIF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */ +#define _BUFC_SEQIF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUF3NWA_DEFAULT (_BUFC_SEQIF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUSERROR (0x1UL << 31) /**< Bus Error */ +#define _BUFC_SEQIF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ +#define _BUFC_SEQIF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ +#define _BUFC_SEQIF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */ +#define BUFC_SEQIF_BUSERROR_DEFAULT (_BUFC_SEQIF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIF */ + +/* Bit fields for BUFC SEQIEN */ +#define _BUFC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIEN */ +#define _BUFC_SEQIEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ +#define _BUFC_SEQIEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ +#define _BUFC_SEQIEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0OF_DEFAULT (_BUFC_SEQIEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ +#define _BUFC_SEQIEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ +#define _BUFC_SEQIEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0UF_DEFAULT (_BUFC_SEQIEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ +#define _BUFC_SEQIEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ +#define _BUFC_SEQIEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0THR_DEFAULT (_BUFC_SEQIEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ +#define _BUFC_SEQIEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ +#define _BUFC_SEQIEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0CORR_DEFAULT (_BUFC_SEQIEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */ +#define _BUFC_SEQIEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */ +#define _BUFC_SEQIEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */ +#define _BUFC_SEQIEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF0NWA_DEFAULT (_BUFC_SEQIEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ +#define _BUFC_SEQIEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ +#define _BUFC_SEQIEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1OF_DEFAULT (_BUFC_SEQIEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ +#define _BUFC_SEQIEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ +#define _BUFC_SEQIEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1UF_DEFAULT (_BUFC_SEQIEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ +#define _BUFC_SEQIEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ +#define _BUFC_SEQIEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1THR_DEFAULT (_BUFC_SEQIEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ +#define _BUFC_SEQIEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ +#define _BUFC_SEQIEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1CORR_DEFAULT (_BUFC_SEQIEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */ +#define _BUFC_SEQIEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */ +#define _BUFC_SEQIEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */ +#define _BUFC_SEQIEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF1NWA_DEFAULT (_BUFC_SEQIEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ +#define _BUFC_SEQIEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ +#define _BUFC_SEQIEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2OF_DEFAULT (_BUFC_SEQIEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ +#define _BUFC_SEQIEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ +#define _BUFC_SEQIEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2UF_DEFAULT (_BUFC_SEQIEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ +#define _BUFC_SEQIEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ +#define _BUFC_SEQIEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2THR_DEFAULT (_BUFC_SEQIEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ +#define _BUFC_SEQIEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ +#define _BUFC_SEQIEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2CORR_DEFAULT (_BUFC_SEQIEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */ +#define _BUFC_SEQIEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */ +#define _BUFC_SEQIEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */ +#define _BUFC_SEQIEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF2NWA_DEFAULT (_BUFC_SEQIEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ +#define _BUFC_SEQIEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ +#define _BUFC_SEQIEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3OF_DEFAULT (_BUFC_SEQIEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */ +#define _BUFC_SEQIEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ +#define _BUFC_SEQIEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ +#define _BUFC_SEQIEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3UF_DEFAULT (_BUFC_SEQIEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ +#define _BUFC_SEQIEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ +#define _BUFC_SEQIEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3THR_DEFAULT (_BUFC_SEQIEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */ +#define _BUFC_SEQIEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ +#define _BUFC_SEQIEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ +#define _BUFC_SEQIEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3CORR_DEFAULT (_BUFC_SEQIEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */ +#define _BUFC_SEQIEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */ +#define _BUFC_SEQIEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */ +#define _BUFC_SEQIEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUF3NWA_DEFAULT (_BUFC_SEQIEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */ +#define _BUFC_SEQIEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ +#define _BUFC_SEQIEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ +#define _BUFC_SEQIEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */ +#define BUFC_SEQIEN_BUSERROR_DEFAULT (_BUFC_SEQIEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIEN */ + +/* Bit fields for BUFC AHBCONFIG */ +#define _BUFC_AHBCONFIG_RESETVALUE 0x00000001UL /**< Default value for BUFC_AHBCONFIG */ +#define _BUFC_AHBCONFIG_MASK 0x00000001UL /**< Mask for BUFC_AHBCONFIG */ +#define BUFC_AHBCONFIG_AHBHPROTBUFFERABLE (0x1UL << 0) /**< Bufferable privileged AHB */ +#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_SHIFT 0 /**< Shift value for BUFC_AHBHPROTBUFFERABLE */ +#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_MASK 0x1UL /**< Bit mask for BUFC_AHBHPROTBUFFERABLE */ +#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for BUFC_AHBCONFIG */ +#define BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT (_BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_AHBCONFIG */ + +/** @} End of group EFR32MG24_BUFC_BitFields */ +/** @} End of group EFR32MG24_BUFC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_BUFC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_buram.h b/EFR32MG24/Device/Include/efr32mg24_buram.h new file mode 100644 index 0000000..e6d6d8b --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_buram.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_BURAM_H +#define EFR32MG24_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_BURAM BURAM + * @{ + * @brief EFR32MG24 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct { + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32MG24_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_BURAM + * @{ + * @defgroup EFR32MG24_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32MG24_BURAM_BitFields */ +/** @} End of group EFR32MG24_BURAM */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_BURAM_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_burtc.h b/EFR32MG24/Device/Include/efr32mg24_burtc.h new file mode 100644 index 0000000..bb3029e --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_burtc.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_BURTC_H +#define EFR32MG24_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_BURTC BURTC + * @{ + * @brief EFR32MG24 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32MG24_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_BURTC + * @{ + * @defgroup EFR32MG24_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32MG24_BURTC_BitFields */ +/** @} End of group EFR32MG24_BURTC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_BURTC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_cmu.h b/EFR32MG24/Device/Include/efr32mg24_cmu.h new file mode 100644 index 0000000..b5995d4 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_cmu.h @@ -0,0 +1,1121 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_CMU_H +#define EFR32MG24_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_CMU CMU + * @{ + * @brief EFR32MG24 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED11[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED14[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED16[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED18[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL; /**< VDAC1 Clock Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED27[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED28[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED30[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED32[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED33[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED35[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED37[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED38[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED40[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED42[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_SET; /**< VDAC1 Clock Control */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED49[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED51[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED54[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED56[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED57[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED59[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED60[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED61[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED62[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED63[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED64[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED65[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED66[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED68[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED69[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_CLR; /**< VDAC1 Clock Control */ + uint32_t RESERVED70[1U]; /**< Reserved for future use */ + uint32_t RESERVED71[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED72[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED73[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED74[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED75[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED76[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED77[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED78[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED79[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED80[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED81[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED82[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED83[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED84[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED85[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED86[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED87[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED88[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED89[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED90[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED91[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED92[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED93[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_TGL; /**< VDAC1 Clock Control */ + uint32_t RESERVED94[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group EFR32MG24_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_CMU + * @{ + * @defgroup EFR32MG24_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFDFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x7EFFEFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1 (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC1_SHIFT 29 /**< Shift value for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_MASK 0x20000000UL /**< Bit mask for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1_DEFAULT (_CMU_CLKEN1_VDAC1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MVP_SHIFT 30 /**< Shift value for CMU_MVP */ +#define _CMU_CLKEN1_MVP_MASK 0x40000000UL /**< Bit mask for CMU_MVP */ +#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ + +/* Bit fields for CMU SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ + +/* Bit fields for CMU VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ + +/* Bit fields for CMU PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC1CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ + +/** @} End of group EFR32MG24_CMU_BitFields */ +/** @} End of group EFR32MG24_CMU */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_CMU_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_dcdc.h b/EFR32MG24/Device/Include/efr32mg24_dcdc.h new file mode 100644 index 0000000..3946313 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_dcdc.h @@ -0,0 +1,455 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2025 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DCDC_H +#define EFR32MG24_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DCDC DCDC + * @{ + * @brief EFR32MG24 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct dcdc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[7U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED23[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[7U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + uint32_t RESERVED32[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED34[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[7U]; /**< Reserved for future use */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32MG24_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DCDC + * @{ + * @defgroup EFR32MG24_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ (0x1UL << 31) /**< PFMX Enable */ +#define _DCDC_CTRL_PFMXEXTREQ_SHIFT 31 /**< Shift value for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_MASK 0x80000000UL /**< Bit mask for DCDC_PFMXEXTREQ */ +#define _DCDC_CTRL_PFMXEXTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD 0x00000000UL /**< Mode EXTLOWLOAD for DCDC_CTRL */ +#define _DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD 0x00000001UL /**< Mode EXTHIGHLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_DEFAULT (_DCDC_CTRL_PFMXEXTREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTLOWLOAD << 31) /**< Shifted mode EXTLOWLOAD for DCDC_CTRL */ +#define DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD (_DCDC_CTRL_PFMXEXTREQ_EXTHIGHLOAD << 31) /**< Shifted mode EXTHIGHLOAD for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC PFMXCTRL */ +#define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ +#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ +#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ +#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ +#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32MG24_DCDC_BitFields */ +/** @} End of group EFR32MG24_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_DCDC_H diff --git a/EFR32MG24/Device/Include/efr32mg24_devinfo.h b/EFR32MG24/Device/Include/efr32mg24_devinfo.h new file mode 100644 index 0000000..aec0de8 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_devinfo.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DEVINFO_H +#define EFR32MG24_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DEVINFO DEVINFO + * @{ + * @brief EFR32MG24 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct { + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct { + __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct { + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature */ + __IM uint32_t EMUTEMP; /**< EMU Temp */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t FENOTCHCAL; /**< FENOTCH Calibration */ + uint32_t RESERVED7[78U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32MG24_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DEVINFO + * @{ + * @defgroup EFR32MG24_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x0B000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH (0x1UL << 4) /**< FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_SHIFT 4 /**< Shift value for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_MASK 0x10UL /**< Bit mask for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH_DEFAULT (_DEVINFO_SWCAPA1_FENOTCH_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/* Bit fields for DEVINFO FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_RESETVALUE 0x000000FFUL /**< Default value for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_SHIFT 0 /**< Shift value for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_MASK 0xFUL /**< Bit mask for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_SHIFT 4 /**< Shift value for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_MASK 0xF0UL /**< Bit mask for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ + +/** @} End of group EFR32MG24_DEVINFO_BitFields */ +/** @} End of group EFR32MG24_DEVINFO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_DEVINFO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_dma_descriptor.h b/EFR32MG24/Device/Include/efr32mg24_dma_descriptor.h new file mode 100644 index 0000000..d5aeb7a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_dma_descriptor.h @@ -0,0 +1,55 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ diff --git a/EFR32MG24/Device/Include/efr32mg24_dpll.h b/EFR32MG24/Device/Include/efr32mg24_dpll.h new file mode 100644 index 0000000..18cf038 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_dpll.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DPLL_H +#define EFR32MG24_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DPLL DPLL + * @{ + * @brief EFR32MG24 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32MG24_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DPLL + * @{ + * @defgroup EFR32MG24_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32MG24_DPLL_BitFields */ +/** @} End of group EFR32MG24_DPLL */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_DPLL_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_eca.h b/EFR32MG24/Device/Include/efr32mg24_eca.h new file mode 100644 index 0000000..e4b284a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_eca.h @@ -0,0 +1,820 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 ECA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ECA_H +#define EFR32MG24_ECA_H +#define ECA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ECA ECA + * @{ + * @brief EFR32MG24 ECA Register Declaration. + *****************************************************************************/ + +/** ECA BUF Register Group Declaration. */ +typedef struct { + __IOM uint32_t BASE; /**< BUFFER BASE ADDRESS */ + __IOM uint32_t LIMITOFFSET; /**< Limit Offset */ + __IOM uint32_t WMOFFSET; /**< Watermark Offset */ +} ECA_BUF_TypeDef; + +/** ECA Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t CONTROL; /**< Control */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt EN */ + __IM uint32_t DMABUSERRORSTATUS; /**< DMA Bus Error Status */ + ECA_BUF_TypeDef BUF[2U]; /**< */ + __IM uint32_t BUFPTRSTATUS; /**< Buffer Pointer Status */ + __IOM uint32_t STARTTRIGCTRL; /**< Start Trigger Control */ + __IOM uint32_t STOPTRIGCTRL; /**< Stop Trigger Control */ + __IOM uint32_t STARTTRIGENMASK; /**< Start Trigger Enable Mask */ + __IOM uint32_t STARTTRIGREDMASK; /**< Start Trigger Rising Edge Mask */ + __IOM uint32_t STARTTRIGFEDMASK; /**< Start Trigger Falling Edge Mask */ + __IOM uint32_t STARTTRIGLVL0MASK; /**< Start Trigger Level 0 Mask */ + __IOM uint32_t STARTTRIGLVL1MASK; /**< Start Trigger Level 1 Mask */ + __IOM uint32_t STOPTRIGENMASK; /**< Stop Trigger Enable Mask */ + __IOM uint32_t STOPTRIGREDMASK; /**< Stop Trigger Rising Edge Mask */ + __IOM uint32_t STOPTRIGFEDMASK; /**< Stop Trigger Falling Edge Mask */ + __IOM uint32_t STOPTRIGLVL0MASK; /**< Stop Trigger Level 0 Mask */ + __IOM uint32_t STOPTRIGLVL1MASK; /**< Stop Trigger Level 1 Mask */ + __IOM uint32_t CAPTURECTRL; /**< Capture Control */ + __IOM uint32_t CAPTURESTARTDELAY; /**< Capture Start Delay */ + __IOM uint32_t CAPTURESTOPDELAY; /**< Capture Stop Delay */ + __IOM uint32_t CAPTURERATECTRL; /**< Capture Rate Control */ + __IOM uint32_t PLAYBACKCTRL; /**< Playback Control */ + __IOM uint32_t PLAYBACKRATECTRL; /**< Playback Rate Control */ + __IOM uint32_t EVENTCNTRCTRL; /**< Event Counter Control */ + __IOM uint32_t EVENTCNTRCOMPARE; /**< Event Counter Compare */ + __IM uint32_t EVENTCNTRSTATUS; /**< Event Counter Status */ + uint32_t RESERVED0[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t CONTROL_SET; /**< Control */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt EN */ + __IM uint32_t DMABUSERRORSTATUS_SET; /**< DMA Bus Error Status */ + ECA_BUF_TypeDef BUF_SET[2U]; /**< */ + __IM uint32_t BUFPTRSTATUS_SET; /**< Buffer Pointer Status */ + __IOM uint32_t STARTTRIGCTRL_SET; /**< Start Trigger Control */ + __IOM uint32_t STOPTRIGCTRL_SET; /**< Stop Trigger Control */ + __IOM uint32_t STARTTRIGENMASK_SET; /**< Start Trigger Enable Mask */ + __IOM uint32_t STARTTRIGREDMASK_SET; /**< Start Trigger Rising Edge Mask */ + __IOM uint32_t STARTTRIGFEDMASK_SET; /**< Start Trigger Falling Edge Mask */ + __IOM uint32_t STARTTRIGLVL0MASK_SET; /**< Start Trigger Level 0 Mask */ + __IOM uint32_t STARTTRIGLVL1MASK_SET; /**< Start Trigger Level 1 Mask */ + __IOM uint32_t STOPTRIGENMASK_SET; /**< Stop Trigger Enable Mask */ + __IOM uint32_t STOPTRIGREDMASK_SET; /**< Stop Trigger Rising Edge Mask */ + __IOM uint32_t STOPTRIGFEDMASK_SET; /**< Stop Trigger Falling Edge Mask */ + __IOM uint32_t STOPTRIGLVL0MASK_SET; /**< Stop Trigger Level 0 Mask */ + __IOM uint32_t STOPTRIGLVL1MASK_SET; /**< Stop Trigger Level 1 Mask */ + __IOM uint32_t CAPTURECTRL_SET; /**< Capture Control */ + __IOM uint32_t CAPTURESTARTDELAY_SET; /**< Capture Start Delay */ + __IOM uint32_t CAPTURESTOPDELAY_SET; /**< Capture Stop Delay */ + __IOM uint32_t CAPTURERATECTRL_SET; /**< Capture Rate Control */ + __IOM uint32_t PLAYBACKCTRL_SET; /**< Playback Control */ + __IOM uint32_t PLAYBACKRATECTRL_SET; /**< Playback Rate Control */ + __IOM uint32_t EVENTCNTRCTRL_SET; /**< Event Counter Control */ + __IOM uint32_t EVENTCNTRCOMPARE_SET; /**< Event Counter Compare */ + __IM uint32_t EVENTCNTRSTATUS_SET; /**< Event Counter Status */ + uint32_t RESERVED1[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t CONTROL_CLR; /**< Control */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt EN */ + __IM uint32_t DMABUSERRORSTATUS_CLR; /**< DMA Bus Error Status */ + ECA_BUF_TypeDef BUF_CLR[2U]; /**< */ + __IM uint32_t BUFPTRSTATUS_CLR; /**< Buffer Pointer Status */ + __IOM uint32_t STARTTRIGCTRL_CLR; /**< Start Trigger Control */ + __IOM uint32_t STOPTRIGCTRL_CLR; /**< Stop Trigger Control */ + __IOM uint32_t STARTTRIGENMASK_CLR; /**< Start Trigger Enable Mask */ + __IOM uint32_t STARTTRIGREDMASK_CLR; /**< Start Trigger Rising Edge Mask */ + __IOM uint32_t STARTTRIGFEDMASK_CLR; /**< Start Trigger Falling Edge Mask */ + __IOM uint32_t STARTTRIGLVL0MASK_CLR; /**< Start Trigger Level 0 Mask */ + __IOM uint32_t STARTTRIGLVL1MASK_CLR; /**< Start Trigger Level 1 Mask */ + __IOM uint32_t STOPTRIGENMASK_CLR; /**< Stop Trigger Enable Mask */ + __IOM uint32_t STOPTRIGREDMASK_CLR; /**< Stop Trigger Rising Edge Mask */ + __IOM uint32_t STOPTRIGFEDMASK_CLR; /**< Stop Trigger Falling Edge Mask */ + __IOM uint32_t STOPTRIGLVL0MASK_CLR; /**< Stop Trigger Level 0 Mask */ + __IOM uint32_t STOPTRIGLVL1MASK_CLR; /**< Stop Trigger Level 1 Mask */ + __IOM uint32_t CAPTURECTRL_CLR; /**< Capture Control */ + __IOM uint32_t CAPTURESTARTDELAY_CLR; /**< Capture Start Delay */ + __IOM uint32_t CAPTURESTOPDELAY_CLR; /**< Capture Stop Delay */ + __IOM uint32_t CAPTURERATECTRL_CLR; /**< Capture Rate Control */ + __IOM uint32_t PLAYBACKCTRL_CLR; /**< Playback Control */ + __IOM uint32_t PLAYBACKRATECTRL_CLR; /**< Playback Rate Control */ + __IOM uint32_t EVENTCNTRCTRL_CLR; /**< Event Counter Control */ + __IOM uint32_t EVENTCNTRCOMPARE_CLR; /**< Event Counter Compare */ + __IM uint32_t EVENTCNTRSTATUS_CLR; /**< Event Counter Status */ + uint32_t RESERVED2[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t CONTROL_TGL; /**< Control */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt EN */ + __IM uint32_t DMABUSERRORSTATUS_TGL; /**< DMA Bus Error Status */ + ECA_BUF_TypeDef BUF_TGL[2U]; /**< */ + __IM uint32_t BUFPTRSTATUS_TGL; /**< Buffer Pointer Status */ + __IOM uint32_t STARTTRIGCTRL_TGL; /**< Start Trigger Control */ + __IOM uint32_t STOPTRIGCTRL_TGL; /**< Stop Trigger Control */ + __IOM uint32_t STARTTRIGENMASK_TGL; /**< Start Trigger Enable Mask */ + __IOM uint32_t STARTTRIGREDMASK_TGL; /**< Start Trigger Rising Edge Mask */ + __IOM uint32_t STARTTRIGFEDMASK_TGL; /**< Start Trigger Falling Edge Mask */ + __IOM uint32_t STARTTRIGLVL0MASK_TGL; /**< Start Trigger Level 0 Mask */ + __IOM uint32_t STARTTRIGLVL1MASK_TGL; /**< Start Trigger Level 1 Mask */ + __IOM uint32_t STOPTRIGENMASK_TGL; /**< Stop Trigger Enable Mask */ + __IOM uint32_t STOPTRIGREDMASK_TGL; /**< Stop Trigger Rising Edge Mask */ + __IOM uint32_t STOPTRIGFEDMASK_TGL; /**< Stop Trigger Falling Edge Mask */ + __IOM uint32_t STOPTRIGLVL0MASK_TGL; /**< Stop Trigger Level 0 Mask */ + __IOM uint32_t STOPTRIGLVL1MASK_TGL; /**< Stop Trigger Level 1 Mask */ + __IOM uint32_t CAPTURECTRL_TGL; /**< Capture Control */ + __IOM uint32_t CAPTURESTARTDELAY_TGL; /**< Capture Start Delay */ + __IOM uint32_t CAPTURESTOPDELAY_TGL; /**< Capture Stop Delay */ + __IOM uint32_t CAPTURERATECTRL_TGL; /**< Capture Rate Control */ + __IOM uint32_t PLAYBACKCTRL_TGL; /**< Playback Control */ + __IOM uint32_t PLAYBACKRATECTRL_TGL; /**< Playback Rate Control */ + __IOM uint32_t EVENTCNTRCTRL_TGL; /**< Event Counter Control */ + __IOM uint32_t EVENTCNTRCOMPARE_TGL; /**< Event Counter Compare */ + __IM uint32_t EVENTCNTRSTATUS_TGL; /**< Event Counter Status */ +} ECA_TypeDef; +/** @} End of group EFR32MG24_ECA */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ECA + * @{ + * @defgroup EFR32MG24_ECA_BitFields ECA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ECA IPVERSION */ +#define _ECA_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ECA_IPVERSION */ +#define _ECA_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ECA_IPVERSION */ +#define _ECA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ECA_IPVERSION */ +#define _ECA_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_IPVERSION */ +#define _ECA_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECA_IPVERSION */ +#define ECA_IPVERSION_IPVERSION_DEFAULT (_ECA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IPVERSION */ + +/* Bit fields for ECA EN */ +#define _ECA_EN_RESETVALUE 0x00000000UL /**< Default value for ECA_EN */ +#define _ECA_EN_MASK 0x00000003UL /**< Mask for ECA_EN */ +#define ECA_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _ECA_EN_EN_SHIFT 0 /**< Shift value for ECA_EN */ +#define _ECA_EN_EN_MASK 0x1UL /**< Bit mask for ECA_EN */ +#define _ECA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EN */ +#define ECA_EN_EN_DEFAULT (_ECA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EN */ +#define ECA_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _ECA_EN_DISABLING_SHIFT 1 /**< Shift value for ECA_DISABLING */ +#define _ECA_EN_DISABLING_MASK 0x2UL /**< Bit mask for ECA_DISABLING */ +#define _ECA_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EN */ +#define ECA_EN_DISABLING_DEFAULT (_ECA_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_EN */ + +/* Bit fields for ECA SWRST */ +#define _ECA_SWRST_RESETVALUE 0x00000000UL /**< Default value for ECA_SWRST */ +#define _ECA_SWRST_MASK 0x00000003UL /**< Mask for ECA_SWRST */ +#define ECA_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _ECA_SWRST_SWRST_SHIFT 0 /**< Shift value for ECA_SWRST */ +#define _ECA_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ECA_SWRST */ +#define _ECA_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_SWRST */ +#define ECA_SWRST_SWRST_DEFAULT (_ECA_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_SWRST */ +#define ECA_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _ECA_SWRST_RESETTING_SHIFT 1 /**< Shift value for ECA_RESETTING */ +#define _ECA_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ECA_RESETTING */ +#define _ECA_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_SWRST */ +#define ECA_SWRST_RESETTING_DEFAULT (_ECA_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_SWRST */ + +/* Bit fields for ECA CMD */ +#define _ECA_CMD_RESETVALUE 0x00000000UL /**< Default value for ECA_CMD */ +#define _ECA_CMD_MASK 0x0000001FUL /**< Mask for ECA_CMD */ +#define _ECA_CMD_MODE_SHIFT 0 /**< Shift value for ECA_MODE */ +#define _ECA_CMD_MODE_MASK 0x3UL /**< Bit mask for ECA_MODE */ +#define _ECA_CMD_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */ +#define _ECA_CMD_MODE_DISABLED 0x00000001UL /**< Mode DISABLED for ECA_CMD */ +#define _ECA_CMD_MODE_CAPTURE 0x00000002UL /**< Mode CAPTURE for ECA_CMD */ +#define _ECA_CMD_MODE_PLAYBACK 0x00000003UL /**< Mode PLAYBACK for ECA_CMD */ +#define ECA_CMD_MODE_DEFAULT (_ECA_CMD_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CMD */ +#define ECA_CMD_MODE_DISABLED (_ECA_CMD_MODE_DISABLED << 0) /**< Shifted mode DISABLED for ECA_CMD */ +#define ECA_CMD_MODE_CAPTURE (_ECA_CMD_MODE_CAPTURE << 0) /**< Shifted mode CAPTURE for ECA_CMD */ +#define ECA_CMD_MODE_PLAYBACK (_ECA_CMD_MODE_PLAYBACK << 0) /**< Shifted mode PLAYBACK for ECA_CMD */ +#define ECA_CMD_STARTEVENTCNTR (0x1UL << 2) /**< Start Event Counter */ +#define _ECA_CMD_STARTEVENTCNTR_SHIFT 2 /**< Shift value for ECA_STARTEVENTCNTR */ +#define _ECA_CMD_STARTEVENTCNTR_MASK 0x4UL /**< Bit mask for ECA_STARTEVENTCNTR */ +#define _ECA_CMD_STARTEVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */ +#define ECA_CMD_STARTEVENTCNTR_DEFAULT (_ECA_CMD_STARTEVENTCNTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_CMD */ +#define ECA_CMD_STOPEVENTCNTR (0x1UL << 3) /**< Stop Event Counter */ +#define _ECA_CMD_STOPEVENTCNTR_SHIFT 3 /**< Shift value for ECA_STOPEVENTCNTR */ +#define _ECA_CMD_STOPEVENTCNTR_MASK 0x8UL /**< Bit mask for ECA_STOPEVENTCNTR */ +#define _ECA_CMD_STOPEVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */ +#define ECA_CMD_STOPEVENTCNTR_DEFAULT (_ECA_CMD_STOPEVENTCNTR_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_CMD */ +#define ECA_CMD_CLEAREVENTCNTR (0x1UL << 4) /**< Clear Event Counter */ +#define _ECA_CMD_CLEAREVENTCNTR_SHIFT 4 /**< Shift value for ECA_CLEAREVENTCNTR */ +#define _ECA_CMD_CLEAREVENTCNTR_MASK 0x10UL /**< Bit mask for ECA_CLEAREVENTCNTR */ +#define _ECA_CMD_CLEAREVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */ +#define ECA_CMD_CLEAREVENTCNTR_DEFAULT (_ECA_CMD_CLEAREVENTCNTR_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_CMD */ + +/* Bit fields for ECA CONTROL */ +#define _ECA_CONTROL_RESETVALUE 0x00000000UL /**< Default value for ECA_CONTROL */ +#define _ECA_CONTROL_MASK 0x00000003UL /**< Mask for ECA_CONTROL */ +#define ECA_CONTROL_BUFMODE (0x1UL << 0) /**< Buffer Mode */ +#define _ECA_CONTROL_BUFMODE_SHIFT 0 /**< Shift value for ECA_BUFMODE */ +#define _ECA_CONTROL_BUFMODE_MASK 0x1UL /**< Bit mask for ECA_BUFMODE */ +#define _ECA_CONTROL_BUFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CONTROL */ +#define _ECA_CONTROL_BUFMODE_SINGLE 0x00000000UL /**< Mode SINGLE for ECA_CONTROL */ +#define _ECA_CONTROL_BUFMODE_DUAL 0x00000001UL /**< Mode DUAL for ECA_CONTROL */ +#define ECA_CONTROL_BUFMODE_DEFAULT (_ECA_CONTROL_BUFMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CONTROL */ +#define ECA_CONTROL_BUFMODE_SINGLE (_ECA_CONTROL_BUFMODE_SINGLE << 0) /**< Shifted mode SINGLE for ECA_CONTROL */ +#define ECA_CONTROL_BUFMODE_DUAL (_ECA_CONTROL_BUFMODE_DUAL << 0) /**< Shifted mode DUAL for ECA_CONTROL */ +#define ECA_CONTROL_QCHANNELMODE (0x1UL << 1) /**< Q-Channel Mode */ +#define _ECA_CONTROL_QCHANNELMODE_SHIFT 1 /**< Shift value for ECA_QCHANNELMODE */ +#define _ECA_CONTROL_QCHANNELMODE_MASK 0x2UL /**< Bit mask for ECA_QCHANNELMODE */ +#define _ECA_CONTROL_QCHANNELMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CONTROL */ +#define _ECA_CONTROL_QCHANNELMODE_ACCEPT 0x00000000UL /**< Mode ACCEPT for ECA_CONTROL */ +#define _ECA_CONTROL_QCHANNELMODE_DENY 0x00000001UL /**< Mode DENY for ECA_CONTROL */ +#define ECA_CONTROL_QCHANNELMODE_DEFAULT (_ECA_CONTROL_QCHANNELMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_CONTROL */ +#define ECA_CONTROL_QCHANNELMODE_ACCEPT (_ECA_CONTROL_QCHANNELMODE_ACCEPT << 1) /**< Shifted mode ACCEPT for ECA_CONTROL */ +#define ECA_CONTROL_QCHANNELMODE_DENY (_ECA_CONTROL_QCHANNELMODE_DENY << 1) /**< Shifted mode DENY for ECA_CONTROL */ + +/* Bit fields for ECA STATUS */ +#define _ECA_STATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_STATUS */ +#define _ECA_STATUS_MASK 0x0000000FUL /**< Mask for ECA_STATUS */ +#define _ECA_STATUS_RUNMODE_SHIFT 0 /**< Shift value for ECA_RUNMODE */ +#define _ECA_STATUS_RUNMODE_MASK 0x3UL /**< Bit mask for ECA_RUNMODE */ +#define _ECA_STATUS_RUNMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */ +#define _ECA_STATUS_RUNMODE_DISABLED 0x00000000UL /**< Mode DISABLED for ECA_STATUS */ +#define _ECA_STATUS_RUNMODE_CAPTURE 0x00000001UL /**< Mode CAPTURE for ECA_STATUS */ +#define _ECA_STATUS_RUNMODE_PLAYBACK 0x00000002UL /**< Mode PLAYBACK for ECA_STATUS */ +#define ECA_STATUS_RUNMODE_DEFAULT (_ECA_STATUS_RUNMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STATUS */ +#define ECA_STATUS_RUNMODE_DISABLED (_ECA_STATUS_RUNMODE_DISABLED << 0) /**< Shifted mode DISABLED for ECA_STATUS */ +#define ECA_STATUS_RUNMODE_CAPTURE (_ECA_STATUS_RUNMODE_CAPTURE << 0) /**< Shifted mode CAPTURE for ECA_STATUS */ +#define ECA_STATUS_RUNMODE_PLAYBACK (_ECA_STATUS_RUNMODE_PLAYBACK << 0) /**< Shifted mode PLAYBACK for ECA_STATUS */ +#define ECA_STATUS_SYNCBUSY (0x1UL << 2) /**< Sync Busy */ +#define _ECA_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for ECA_SYNCBUSY */ +#define _ECA_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for ECA_SYNCBUSY */ +#define _ECA_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */ +#define ECA_STATUS_SYNCBUSY_DEFAULT (_ECA_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_STATUS */ +#define ECA_STATUS_EVENTCNTRSTARTED (0x1UL << 3) /**< Event Counter Started */ +#define _ECA_STATUS_EVENTCNTRSTARTED_SHIFT 3 /**< Shift value for ECA_EVENTCNTRSTARTED */ +#define _ECA_STATUS_EVENTCNTRSTARTED_MASK 0x8UL /**< Bit mask for ECA_EVENTCNTRSTARTED */ +#define _ECA_STATUS_EVENTCNTRSTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */ +#define ECA_STATUS_EVENTCNTRSTARTED_DEFAULT (_ECA_STATUS_EVENTCNTRSTARTED_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STATUS */ + +/* Bit fields for ECA IF */ +#define _ECA_IF_RESETVALUE 0x00000000UL /**< Default value for ECA_IF */ +#define _ECA_IF_MASK 0x00003FFFUL /**< Mask for ECA_IF */ +#define ECA_IF_BUF0WMIND (0x1UL << 0) /**< BUF0 Watermark Indication */ +#define _ECA_IF_BUF0WMIND_SHIFT 0 /**< Shift value for ECA_BUF0WMIND */ +#define _ECA_IF_BUF0WMIND_MASK 0x1UL /**< Bit mask for ECA_BUF0WMIND */ +#define _ECA_IF_BUF0WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF0WMIND_DEFAULT (_ECA_IF_BUF0WMIND_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF1WMIND (0x1UL << 1) /**< BUF1 Watermark Indication */ +#define _ECA_IF_BUF1WMIND_SHIFT 1 /**< Shift value for ECA_BUF1WMIND */ +#define _ECA_IF_BUF1WMIND_MASK 0x2UL /**< Bit mask for ECA_BUF1WMIND */ +#define _ECA_IF_BUF1WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF1WMIND_DEFAULT (_ECA_IF_BUF1WMIND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF0FULLIND (0x1UL << 2) /**< BUF0 Full Indication */ +#define _ECA_IF_BUF0FULLIND_SHIFT 2 /**< Shift value for ECA_BUF0FULLIND */ +#define _ECA_IF_BUF0FULLIND_MASK 0x4UL /**< Bit mask for ECA_BUF0FULLIND */ +#define _ECA_IF_BUF0FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF0FULLIND_DEFAULT (_ECA_IF_BUF0FULLIND_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF1FULLIND (0x1UL << 3) /**< BUF1 Full Indication */ +#define _ECA_IF_BUF1FULLIND_SHIFT 3 /**< Shift value for ECA_BUF1FULLIND */ +#define _ECA_IF_BUF1FULLIND_MASK 0x8UL /**< Bit mask for ECA_BUF1FULLIND */ +#define _ECA_IF_BUF1FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_BUF1FULLIND_DEFAULT (_ECA_IF_BUF1FULLIND_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_STARTTRIG (0x1UL << 4) /**< Start Trigger */ +#define _ECA_IF_STARTTRIG_SHIFT 4 /**< Shift value for ECA_STARTTRIG */ +#define _ECA_IF_STARTTRIG_MASK 0x10UL /**< Bit mask for ECA_STARTTRIG */ +#define _ECA_IF_STARTTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_STARTTRIG_DEFAULT (_ECA_IF_STARTTRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_STOPTRIG (0x1UL << 5) /**< Stop Trigger */ +#define _ECA_IF_STOPTRIG_SHIFT 5 /**< Shift value for ECA_STOPTRIG */ +#define _ECA_IF_STOPTRIG_MASK 0x20UL /**< Bit mask for ECA_STOPTRIG */ +#define _ECA_IF_STOPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_STOPTRIG_DEFAULT (_ECA_IF_STOPTRIG_DEFAULT << 5) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_CAPTURESTART (0x1UL << 6) /**< Capture Start */ +#define _ECA_IF_CAPTURESTART_SHIFT 6 /**< Shift value for ECA_CAPTURESTART */ +#define _ECA_IF_CAPTURESTART_MASK 0x40UL /**< Bit mask for ECA_CAPTURESTART */ +#define _ECA_IF_CAPTURESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_CAPTURESTART_DEFAULT (_ECA_IF_CAPTURESTART_DEFAULT << 6) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_CAPTUREEND (0x1UL << 7) /**< Capture End */ +#define _ECA_IF_CAPTUREEND_SHIFT 7 /**< Shift value for ECA_CAPTUREEND */ +#define _ECA_IF_CAPTUREEND_MASK 0x80UL /**< Bit mask for ECA_CAPTUREEND */ +#define _ECA_IF_CAPTUREEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_CAPTUREEND_DEFAULT (_ECA_IF_CAPTUREEND_DEFAULT << 7) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_PLAYBACKSTART (0x1UL << 8) /**< Playback Start */ +#define _ECA_IF_PLAYBACKSTART_SHIFT 8 /**< Shift value for ECA_PLAYBACKSTART */ +#define _ECA_IF_PLAYBACKSTART_MASK 0x100UL /**< Bit mask for ECA_PLAYBACKSTART */ +#define _ECA_IF_PLAYBACKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_PLAYBACKSTART_DEFAULT (_ECA_IF_PLAYBACKSTART_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_PLAYBACKEND (0x1UL << 9) /**< Playback End */ +#define _ECA_IF_PLAYBACKEND_SHIFT 9 /**< Shift value for ECA_PLAYBACKEND */ +#define _ECA_IF_PLAYBACKEND_MASK 0x200UL /**< Bit mask for ECA_PLAYBACKEND */ +#define _ECA_IF_PLAYBACKEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_PLAYBACKEND_DEFAULT (_ECA_IF_PLAYBACKEND_DEFAULT << 9) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_EVENTCNTRCOMP (0x1UL << 10) /**< Event Counter Compare */ +#define _ECA_IF_EVENTCNTRCOMP_SHIFT 10 /**< Shift value for ECA_EVENTCNTRCOMP */ +#define _ECA_IF_EVENTCNTRCOMP_MASK 0x400UL /**< Bit mask for ECA_EVENTCNTRCOMP */ +#define _ECA_IF_EVENTCNTRCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_EVENTCNTRCOMP_DEFAULT (_ECA_IF_EVENTCNTRCOMP_DEFAULT << 10) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_FIFOORERROR (0x1UL << 11) /**< FIFO Overrun Error */ +#define _ECA_IF_FIFOORERROR_SHIFT 11 /**< Shift value for ECA_FIFOORERROR */ +#define _ECA_IF_FIFOORERROR_MASK 0x800UL /**< Bit mask for ECA_FIFOORERROR */ +#define _ECA_IF_FIFOORERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_FIFOORERROR_DEFAULT (_ECA_IF_FIFOORERROR_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_FIFOURERROR (0x1UL << 12) /**< FIFO Underrun Error */ +#define _ECA_IF_FIFOURERROR_SHIFT 12 /**< Shift value for ECA_FIFOURERROR */ +#define _ECA_IF_FIFOURERROR_MASK 0x1000UL /**< Bit mask for ECA_FIFOURERROR */ +#define _ECA_IF_FIFOURERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_FIFOURERROR_DEFAULT (_ECA_IF_FIFOURERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for ECA_IF */ +#define ECA_IF_DMABUSERROR (0x1UL << 13) /**< DMA Bus Error */ +#define _ECA_IF_DMABUSERROR_SHIFT 13 /**< Shift value for ECA_DMABUSERROR */ +#define _ECA_IF_DMABUSERROR_MASK 0x2000UL /**< Bit mask for ECA_DMABUSERROR */ +#define _ECA_IF_DMABUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */ +#define ECA_IF_DMABUSERROR_DEFAULT (_ECA_IF_DMABUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for ECA_IF */ + +/* Bit fields for ECA IEN */ +#define _ECA_IEN_RESETVALUE 0x00000000UL /**< Default value for ECA_IEN */ +#define _ECA_IEN_MASK 0x00003FFFUL /**< Mask for ECA_IEN */ +#define ECA_IEN_BUF0WMIND (0x1UL << 0) /**< New BitField */ +#define _ECA_IEN_BUF0WMIND_SHIFT 0 /**< Shift value for ECA_BUF0WMIND */ +#define _ECA_IEN_BUF0WMIND_MASK 0x1UL /**< Bit mask for ECA_BUF0WMIND */ +#define _ECA_IEN_BUF0WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF0WMIND_DEFAULT (_ECA_IEN_BUF0WMIND_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF1WMIND (0x1UL << 1) /**< New BitField */ +#define _ECA_IEN_BUF1WMIND_SHIFT 1 /**< Shift value for ECA_BUF1WMIND */ +#define _ECA_IEN_BUF1WMIND_MASK 0x2UL /**< Bit mask for ECA_BUF1WMIND */ +#define _ECA_IEN_BUF1WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF1WMIND_DEFAULT (_ECA_IEN_BUF1WMIND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF0FULLIND (0x1UL << 2) /**< New BitField */ +#define _ECA_IEN_BUF0FULLIND_SHIFT 2 /**< Shift value for ECA_BUF0FULLIND */ +#define _ECA_IEN_BUF0FULLIND_MASK 0x4UL /**< Bit mask for ECA_BUF0FULLIND */ +#define _ECA_IEN_BUF0FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF0FULLIND_DEFAULT (_ECA_IEN_BUF0FULLIND_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF1FULLIND (0x1UL << 3) /**< New BitField */ +#define _ECA_IEN_BUF1FULLIND_SHIFT 3 /**< Shift value for ECA_BUF1FULLIND */ +#define _ECA_IEN_BUF1FULLIND_MASK 0x8UL /**< Bit mask for ECA_BUF1FULLIND */ +#define _ECA_IEN_BUF1FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_BUF1FULLIND_DEFAULT (_ECA_IEN_BUF1FULLIND_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_STARTTRIG (0x1UL << 4) /**< New BitField */ +#define _ECA_IEN_STARTTRIG_SHIFT 4 /**< Shift value for ECA_STARTTRIG */ +#define _ECA_IEN_STARTTRIG_MASK 0x10UL /**< Bit mask for ECA_STARTTRIG */ +#define _ECA_IEN_STARTTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_STARTTRIG_DEFAULT (_ECA_IEN_STARTTRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_STOPTRIG (0x1UL << 5) /**< New BitField */ +#define _ECA_IEN_STOPTRIG_SHIFT 5 /**< Shift value for ECA_STOPTRIG */ +#define _ECA_IEN_STOPTRIG_MASK 0x20UL /**< Bit mask for ECA_STOPTRIG */ +#define _ECA_IEN_STOPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_STOPTRIG_DEFAULT (_ECA_IEN_STOPTRIG_DEFAULT << 5) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_CAPTURESTART (0x1UL << 6) /**< New BitField */ +#define _ECA_IEN_CAPTURESTART_SHIFT 6 /**< Shift value for ECA_CAPTURESTART */ +#define _ECA_IEN_CAPTURESTART_MASK 0x40UL /**< Bit mask for ECA_CAPTURESTART */ +#define _ECA_IEN_CAPTURESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_CAPTURESTART_DEFAULT (_ECA_IEN_CAPTURESTART_DEFAULT << 6) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_CAPTUREEND (0x1UL << 7) /**< New BitField */ +#define _ECA_IEN_CAPTUREEND_SHIFT 7 /**< Shift value for ECA_CAPTUREEND */ +#define _ECA_IEN_CAPTUREEND_MASK 0x80UL /**< Bit mask for ECA_CAPTUREEND */ +#define _ECA_IEN_CAPTUREEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_CAPTUREEND_DEFAULT (_ECA_IEN_CAPTUREEND_DEFAULT << 7) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_PLAYBACKSTART (0x1UL << 8) /**< New BitField */ +#define _ECA_IEN_PLAYBACKSTART_SHIFT 8 /**< Shift value for ECA_PLAYBACKSTART */ +#define _ECA_IEN_PLAYBACKSTART_MASK 0x100UL /**< Bit mask for ECA_PLAYBACKSTART */ +#define _ECA_IEN_PLAYBACKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_PLAYBACKSTART_DEFAULT (_ECA_IEN_PLAYBACKSTART_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_PLAYBACKEND (0x1UL << 9) /**< New BitField */ +#define _ECA_IEN_PLAYBACKEND_SHIFT 9 /**< Shift value for ECA_PLAYBACKEND */ +#define _ECA_IEN_PLAYBACKEND_MASK 0x200UL /**< Bit mask for ECA_PLAYBACKEND */ +#define _ECA_IEN_PLAYBACKEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_PLAYBACKEND_DEFAULT (_ECA_IEN_PLAYBACKEND_DEFAULT << 9) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_EVENTCNTRCOMP (0x1UL << 10) /**< New BitField */ +#define _ECA_IEN_EVENTCNTRCOMP_SHIFT 10 /**< Shift value for ECA_EVENTCNTRCOMP */ +#define _ECA_IEN_EVENTCNTRCOMP_MASK 0x400UL /**< Bit mask for ECA_EVENTCNTRCOMP */ +#define _ECA_IEN_EVENTCNTRCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_EVENTCNTRCOMP_DEFAULT (_ECA_IEN_EVENTCNTRCOMP_DEFAULT << 10) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_FIFOORERROR (0x1UL << 11) /**< New BitField */ +#define _ECA_IEN_FIFOORERROR_SHIFT 11 /**< Shift value for ECA_FIFOORERROR */ +#define _ECA_IEN_FIFOORERROR_MASK 0x800UL /**< Bit mask for ECA_FIFOORERROR */ +#define _ECA_IEN_FIFOORERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_FIFOORERROR_DEFAULT (_ECA_IEN_FIFOORERROR_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_FIFOURERROR (0x1UL << 12) /**< New BitField */ +#define _ECA_IEN_FIFOURERROR_SHIFT 12 /**< Shift value for ECA_FIFOURERROR */ +#define _ECA_IEN_FIFOURERROR_MASK 0x1000UL /**< Bit mask for ECA_FIFOURERROR */ +#define _ECA_IEN_FIFOURERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_FIFOURERROR_DEFAULT (_ECA_IEN_FIFOURERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for ECA_IEN */ +#define ECA_IEN_DMABUSERROR (0x1UL << 13) /**< New BitField */ +#define _ECA_IEN_DMABUSERROR_SHIFT 13 /**< Shift value for ECA_DMABUSERROR */ +#define _ECA_IEN_DMABUSERROR_MASK 0x2000UL /**< Bit mask for ECA_DMABUSERROR */ +#define _ECA_IEN_DMABUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */ +#define ECA_IEN_DMABUSERROR_DEFAULT (_ECA_IEN_DMABUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for ECA_IEN */ + +/* Bit fields for ECA DMABUSERRORSTATUS */ +#define _ECA_DMABUSERRORSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_DMABUSERRORSTATUS */ +#define _ECA_DMABUSERRORSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_DMABUSERRORSTATUS */ +#define _ECA_DMABUSERRORSTATUS_ADDR_SHIFT 0 /**< Shift value for ECA_ADDR */ +#define _ECA_DMABUSERRORSTATUS_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ADDR */ +#define _ECA_DMABUSERRORSTATUS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_DMABUSERRORSTATUS */ +#define ECA_DMABUSERRORSTATUS_ADDR_DEFAULT (_ECA_DMABUSERRORSTATUS_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_DMABUSERRORSTATUS*/ + +/* Bit fields for ECA BUF_BASE */ +#define _ECA_BUF_BASE_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_BASE */ +#define _ECA_BUF_BASE_MASK 0xFFFFFFFFUL /**< Mask for ECA_BUF_BASE */ +#define _ECA_BUF_BASE_BASE_SHIFT 0 /**< Shift value for ECA_BASE */ +#define _ECA_BUF_BASE_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_BASE */ +#define _ECA_BUF_BASE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_BASE */ +#define ECA_BUF_BASE_BASE_DEFAULT (_ECA_BUF_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_BUF_BASE */ + +/* Bit fields for ECA BUF_LIMITOFFSET */ +#define _ECA_BUF_LIMITOFFSET_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_LIMITOFFSET */ +#define _ECA_BUF_LIMITOFFSET_MASK 0x0007FFFCUL /**< Mask for ECA_BUF_LIMITOFFSET */ +#define _ECA_BUF_LIMITOFFSET_OFFSET_SHIFT 2 /**< Shift value for ECA_OFFSET */ +#define _ECA_BUF_LIMITOFFSET_OFFSET_MASK 0x7FFFCUL /**< Bit mask for ECA_OFFSET */ +#define _ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_LIMITOFFSET */ +#define ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT (_ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_BUF_LIMITOFFSET*/ + +/* Bit fields for ECA BUF_WMOFFSET */ +#define _ECA_BUF_WMOFFSET_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_WMOFFSET */ +#define _ECA_BUF_WMOFFSET_MASK 0x0007FFFCUL /**< Mask for ECA_BUF_WMOFFSET */ +#define _ECA_BUF_WMOFFSET_OFFSET_SHIFT 2 /**< Shift value for ECA_OFFSET */ +#define _ECA_BUF_WMOFFSET_OFFSET_MASK 0x7FFFCUL /**< Bit mask for ECA_OFFSET */ +#define _ECA_BUF_WMOFFSET_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_WMOFFSET */ +#define ECA_BUF_WMOFFSET_OFFSET_DEFAULT (_ECA_BUF_WMOFFSET_OFFSET_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_BUF_WMOFFSET */ + +/* Bit fields for ECA BUFPTRSTATUS */ +#define _ECA_BUFPTRSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_BUFPTRSTATUS */ +#define _ECA_BUFPTRSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_BUFPTRSTATUS */ +#define _ECA_BUFPTRSTATUS_STATUS_SHIFT 0 /**< Shift value for ECA_STATUS */ +#define _ECA_BUFPTRSTATUS_STATUS_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_STATUS */ +#define _ECA_BUFPTRSTATUS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUFPTRSTATUS */ +#define ECA_BUFPTRSTATUS_STATUS_DEFAULT (_ECA_BUFPTRSTATUS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_BUFPTRSTATUS */ + +/* Bit fields for ECA STARTTRIGCTRL */ +#define _ECA_STARTTRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGCTRL */ +#define _ECA_STARTTRIGCTRL_MASK 0x0000001FUL /**< Mask for ECA_STARTTRIGCTRL */ +#define _ECA_STARTTRIGCTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */ +#define _ECA_STARTTRIGCTRL_TRACESEL_MASK 0x7UL /**< Bit mask for ECA_TRACESEL */ +#define _ECA_STARTTRIGCTRL_TRACESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_TRACESEL_DEFAULT (_ECA_STARTTRIGCTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_ENABLE (0x1UL << 3) /**< Enable */ +#define _ECA_STARTTRIGCTRL_ENABLE_SHIFT 3 /**< Shift value for ECA_ENABLE */ +#define _ECA_STARTTRIGCTRL_ENABLE_MASK 0x8UL /**< Bit mask for ECA_ENABLE */ +#define _ECA_STARTTRIGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_ENABLE_DEFAULT (_ECA_STARTTRIGCTRL_ENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_COMBMODE (0x1UL << 4) /**< Combination Mode */ +#define _ECA_STARTTRIGCTRL_COMBMODE_SHIFT 4 /**< Shift value for ECA_COMBMODE */ +#define _ECA_STARTTRIGCTRL_COMBMODE_MASK 0x10UL /**< Bit mask for ECA_COMBMODE */ +#define _ECA_STARTTRIGCTRL_COMBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */ +#define _ECA_STARTTRIGCTRL_COMBMODE_AND 0x00000000UL /**< Mode AND for ECA_STARTTRIGCTRL */ +#define _ECA_STARTTRIGCTRL_COMBMODE_OR 0x00000001UL /**< Mode OR for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_COMBMODE_DEFAULT (_ECA_STARTTRIGCTRL_COMBMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_COMBMODE_AND (_ECA_STARTTRIGCTRL_COMBMODE_AND << 4) /**< Shifted mode AND for ECA_STARTTRIGCTRL */ +#define ECA_STARTTRIGCTRL_COMBMODE_OR (_ECA_STARTTRIGCTRL_COMBMODE_OR << 4) /**< Shifted mode OR for ECA_STARTTRIGCTRL */ + +/* Bit fields for ECA STOPTRIGCTRL */ +#define _ECA_STOPTRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGCTRL */ +#define _ECA_STOPTRIGCTRL_MASK 0x0000001FUL /**< Mask for ECA_STOPTRIGCTRL */ +#define _ECA_STOPTRIGCTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */ +#define _ECA_STOPTRIGCTRL_TRACESEL_MASK 0x7UL /**< Bit mask for ECA_TRACESEL */ +#define _ECA_STOPTRIGCTRL_TRACESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_TRACESEL_DEFAULT (_ECA_STOPTRIGCTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_ENABLE (0x1UL << 3) /**< Enable */ +#define _ECA_STOPTRIGCTRL_ENABLE_SHIFT 3 /**< Shift value for ECA_ENABLE */ +#define _ECA_STOPTRIGCTRL_ENABLE_MASK 0x8UL /**< Bit mask for ECA_ENABLE */ +#define _ECA_STOPTRIGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_ENABLE_DEFAULT (_ECA_STOPTRIGCTRL_ENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_COMBMODE (0x1UL << 4) /**< Combination Mode */ +#define _ECA_STOPTRIGCTRL_COMBMODE_SHIFT 4 /**< Shift value for ECA_COMBMODE */ +#define _ECA_STOPTRIGCTRL_COMBMODE_MASK 0x10UL /**< Bit mask for ECA_COMBMODE */ +#define _ECA_STOPTRIGCTRL_COMBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */ +#define _ECA_STOPTRIGCTRL_COMBMODE_AND 0x00000000UL /**< Mode AND for ECA_STOPTRIGCTRL */ +#define _ECA_STOPTRIGCTRL_COMBMODE_OR 0x00000001UL /**< Mode OR for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_COMBMODE_DEFAULT (_ECA_STOPTRIGCTRL_COMBMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_COMBMODE_AND (_ECA_STOPTRIGCTRL_COMBMODE_AND << 4) /**< Shifted mode AND for ECA_STOPTRIGCTRL */ +#define ECA_STOPTRIGCTRL_COMBMODE_OR (_ECA_STOPTRIGCTRL_COMBMODE_OR << 4) /**< Shifted mode OR for ECA_STOPTRIGCTRL */ + +/* Bit fields for ECA STARTTRIGENMASK */ +#define _ECA_STARTTRIGENMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGENMASK */ +#define _ECA_STARTTRIGENMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGENMASK */ +#define _ECA_STARTTRIGENMASK_ENMASK_SHIFT 0 /**< Shift value for ECA_ENMASK */ +#define _ECA_STARTTRIGENMASK_ENMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ENMASK */ +#define _ECA_STARTTRIGENMASK_ENMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGENMASK */ +#define ECA_STARTTRIGENMASK_ENMASK_DEFAULT (_ECA_STARTTRIGENMASK_ENMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGENMASK*/ + +/* Bit fields for ECA STARTTRIGREDMASK */ +#define _ECA_STARTTRIGREDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGREDMASK */ +#define _ECA_STARTTRIGREDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGREDMASK */ +#define _ECA_STARTTRIGREDMASK_REDMASK_SHIFT 0 /**< Shift value for ECA_REDMASK */ +#define _ECA_STARTTRIGREDMASK_REDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_REDMASK */ +#define _ECA_STARTTRIGREDMASK_REDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGREDMASK */ +#define ECA_STARTTRIGREDMASK_REDMASK_DEFAULT (_ECA_STARTTRIGREDMASK_REDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGREDMASK*/ + +/* Bit fields for ECA STARTTRIGFEDMASK */ +#define _ECA_STARTTRIGFEDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGFEDMASK */ +#define _ECA_STARTTRIGFEDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGFEDMASK */ +#define _ECA_STARTTRIGFEDMASK_FEDMASK_SHIFT 0 /**< Shift value for ECA_FEDMASK */ +#define _ECA_STARTTRIGFEDMASK_FEDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_FEDMASK */ +#define _ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGFEDMASK */ +#define ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT (_ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGFEDMASK*/ + +/* Bit fields for ECA STARTTRIGLVL0MASK */ +#define _ECA_STARTTRIGLVL0MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGLVL0MASK */ +#define _ECA_STARTTRIGLVL0MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGLVL0MASK */ +#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_SHIFT 0 /**< Shift value for ECA_LVL0MASK */ +#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL0MASK */ +#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGLVL0MASK */ +#define ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT (_ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGLVL0MASK*/ + +/* Bit fields for ECA STARTTRIGLVL1MASK */ +#define _ECA_STARTTRIGLVL1MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGLVL1MASK */ +#define _ECA_STARTTRIGLVL1MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGLVL1MASK */ +#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_SHIFT 0 /**< Shift value for ECA_LVL1MASK */ +#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL1MASK */ +#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGLVL1MASK */ +#define ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT (_ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGLVL1MASK*/ + +/* Bit fields for ECA STOPTRIGENMASK */ +#define _ECA_STOPTRIGENMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGENMASK */ +#define _ECA_STOPTRIGENMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGENMASK */ +#define _ECA_STOPTRIGENMASK_ENMASK_SHIFT 0 /**< Shift value for ECA_ENMASK */ +#define _ECA_STOPTRIGENMASK_ENMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ENMASK */ +#define _ECA_STOPTRIGENMASK_ENMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGENMASK */ +#define ECA_STOPTRIGENMASK_ENMASK_DEFAULT (_ECA_STOPTRIGENMASK_ENMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGENMASK */ + +/* Bit fields for ECA STOPTRIGREDMASK */ +#define _ECA_STOPTRIGREDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGREDMASK */ +#define _ECA_STOPTRIGREDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGREDMASK */ +#define _ECA_STOPTRIGREDMASK_REDMASK_SHIFT 0 /**< Shift value for ECA_REDMASK */ +#define _ECA_STOPTRIGREDMASK_REDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_REDMASK */ +#define _ECA_STOPTRIGREDMASK_REDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGREDMASK */ +#define ECA_STOPTRIGREDMASK_REDMASK_DEFAULT (_ECA_STOPTRIGREDMASK_REDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGREDMASK*/ + +/* Bit fields for ECA STOPTRIGFEDMASK */ +#define _ECA_STOPTRIGFEDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGFEDMASK */ +#define _ECA_STOPTRIGFEDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGFEDMASK */ +#define _ECA_STOPTRIGFEDMASK_FEDMASK_SHIFT 0 /**< Shift value for ECA_FEDMASK */ +#define _ECA_STOPTRIGFEDMASK_FEDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_FEDMASK */ +#define _ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGFEDMASK */ +#define ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT (_ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGFEDMASK*/ + +/* Bit fields for ECA STOPTRIGLVL0MASK */ +#define _ECA_STOPTRIGLVL0MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGLVL0MASK */ +#define _ECA_STOPTRIGLVL0MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGLVL0MASK */ +#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_SHIFT 0 /**< Shift value for ECA_LVL0MASK */ +#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL0MASK */ +#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGLVL0MASK */ +#define ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT (_ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGLVL0MASK*/ + +/* Bit fields for ECA STOPTRIGLVL1MASK */ +#define _ECA_STOPTRIGLVL1MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGLVL1MASK */ +#define _ECA_STOPTRIGLVL1MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGLVL1MASK */ +#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_SHIFT 0 /**< Shift value for ECA_LVL1MASK */ +#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL1MASK */ +#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGLVL1MASK */ +#define ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT (_ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGLVL1MASK*/ + +/* Bit fields for ECA CAPTURECTRL */ +#define _ECA_CAPTURECTRL_RESETVALUE 0x00000501UL /**< Default value for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_MASK 0x7FF7FFFFUL /**< Mask for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */ +#define _ECA_CAPTURECTRL_TRACESEL_MASK 0xFFUL /**< Bit mask for ECA_TRACESEL */ +#define _ECA_CAPTURECTRL_TRACESEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_TRACESEL_DEFAULT (_ECA_CAPTURECTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_SHIFT 8 /**< Shift value for ECA_DATAWIDTH */ +#define _ECA_CAPTURECTRL_DATAWIDTH_MASK 0x700UL /**< Bit mask for ECA_DATAWIDTH */ +#define _ECA_CAPTURECTRL_DATAWIDTH_DEFAULT 0x00000005UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT1 0x00000000UL /**< Mode BIT1 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT2 0x00000001UL /**< Mode BIT2 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT4 0x00000002UL /**< Mode BIT4 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT8 0x00000003UL /**< Mode BIT8 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT16 0x00000004UL /**< Mode BIT16 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAWIDTH_BIT32 0x00000005UL /**< Mode BIT32 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_DEFAULT (_ECA_CAPTURECTRL_DATAWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT1 (_ECA_CAPTURECTRL_DATAWIDTH_BIT1 << 8) /**< Shifted mode BIT1 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT2 (_ECA_CAPTURECTRL_DATAWIDTH_BIT2 << 8) /**< Shifted mode BIT2 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT4 (_ECA_CAPTURECTRL_DATAWIDTH_BIT4 << 8) /**< Shifted mode BIT4 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT8 (_ECA_CAPTURECTRL_DATAWIDTH_BIT8 << 8) /**< Shifted mode BIT8 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT16 (_ECA_CAPTURECTRL_DATAWIDTH_BIT16 << 8) /**< Shifted mode BIT16 for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAWIDTH_BIT32 (_ECA_CAPTURECTRL_DATAWIDTH_BIT32 << 8) /**< Shifted mode BIT32 for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAROTATESIZE_SHIFT 11 /**< Shift value for ECA_DATAROTATESIZE */ +#define _ECA_CAPTURECTRL_DATAROTATESIZE_MASK 0xF800UL /**< Bit mask for ECA_DATAROTATESIZE */ +#define _ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT (_ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STARTMODE (0x1UL << 16) /**< Start Mode */ +#define _ECA_CAPTURECTRL_STARTMODE_SHIFT 16 /**< Shift value for ECA_STARTMODE */ +#define _ECA_CAPTURECTRL_STARTMODE_MASK 0x10000UL /**< Bit mask for ECA_STARTMODE */ +#define _ECA_CAPTURECTRL_STARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STARTMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STARTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STARTMODE_DEFAULT (_ECA_CAPTURECTRL_STARTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STARTMODE_MANUAL (_ECA_CAPTURECTRL_STARTMODE_MANUAL << 16) /**< Shifted mode MANUAL for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STARTMODE_START_TRIGGER (_ECA_CAPTURECTRL_STARTMODE_START_TRIGGER << 16) /**< Shifted mode START_TRIGGER for ECA_CAPTURECTRL*/ +#define _ECA_CAPTURECTRL_STOPMODE_SHIFT 17 /**< Shift value for ECA_STOPMODE */ +#define _ECA_CAPTURECTRL_STOPMODE_MASK 0x60000UL /**< Bit mask for ECA_STOPMODE */ +#define _ECA_CAPTURECTRL_STOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STOPMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STOPMODE_BUF_FULL 0x00000001UL /**< Mode BUF_FULL for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER 0x00000002UL /**< Mode STOP_TRIGGER for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL 0x00000003UL /**< Mode STOP_TRIGGER_FULL for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPMODE_DEFAULT (_ECA_CAPTURECTRL_STOPMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPMODE_CONTINUOUS (_ECA_CAPTURECTRL_STOPMODE_CONTINUOUS << 17) /**< Shifted mode CONTINUOUS for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPMODE_BUF_FULL (_ECA_CAPTURECTRL_STOPMODE_BUF_FULL << 17) /**< Shifted mode BUF_FULL for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER (_ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER << 17) /**< Shifted mode STOP_TRIGGER for ECA_CAPTURECTRL*/ +#define ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL (_ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL << 17) /**< Shifted mode STOP_TRIGGER_FULL for ECA_CAPTURECTRL*/ +#define _ECA_CAPTURECTRL_COND_SHIFT 20 /**< Shift value for ECA_COND */ +#define _ECA_CAPTURECTRL_COND_MASK 0x300000UL /**< Bit mask for ECA_COND */ +#define _ECA_CAPTURECTRL_COND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_COND_TIMED 0x00000000UL /**< Mode TIMED for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_COND_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_COND_SLAVE 0x00000002UL /**< Mode SLAVE for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_COND_DEFAULT (_ECA_CAPTURECTRL_COND_DEFAULT << 20) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_COND_TIMED (_ECA_CAPTURECTRL_COND_TIMED << 20) /**< Shifted mode TIMED for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_COND_START_TRIGGER (_ECA_CAPTURECTRL_COND_START_TRIGGER << 20) /**< Shifted mode START_TRIGGER for ECA_CAPTURECTRL*/ +#define ECA_CAPTURECTRL_COND_SLAVE (_ECA_CAPTURECTRL_COND_SLAVE << 20) /**< Shifted mode SLAVE for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPCONDPRI (0x1UL << 22) /**< Stop Condition Priority */ +#define _ECA_CAPTURECTRL_STOPCONDPRI_SHIFT 22 /**< Shift value for ECA_STOPCONDPRI */ +#define _ECA_CAPTURECTRL_STOPCONDPRI_MASK 0x400000UL /**< Bit mask for ECA_STOPCONDPRI */ +#define _ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT (_ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT << 22) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_WRITEDIS (0x1UL << 23) /**< Write Memory Disable */ +#define _ECA_CAPTURECTRL_WRITEDIS_SHIFT 23 /**< Shift value for ECA_WRITEDIS */ +#define _ECA_CAPTURECTRL_WRITEDIS_MASK 0x800000UL /**< Bit mask for ECA_WRITEDIS */ +#define _ECA_CAPTURECTRL_WRITEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_WRITEDIS_DEFAULT (_ECA_CAPTURECTRL_WRITEDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAOUTEN (0x1UL << 24) /**< Port Interface Enable */ +#define _ECA_CAPTURECTRL_DATAOUTEN_SHIFT 24 /**< Shift value for ECA_DATAOUTEN */ +#define _ECA_CAPTURECTRL_DATAOUTEN_MASK 0x1000000UL /**< Bit mask for ECA_DATAOUTEN */ +#define _ECA_CAPTURECTRL_DATAOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAOUTEN_DEFAULT (_ECA_CAPTURECTRL_DATAOUTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ +#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_SHIFT 25 /**< Shift value for ECA_DATAOUTDSHIFT */ +#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_MASK 0x7E000000UL /**< Bit mask for ECA_DATAOUTDSHIFT */ +#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */ +#define ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT (_ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT << 25) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */ + +/* Bit fields for ECA CAPTURESTARTDELAY */ +#define _ECA_CAPTURESTARTDELAY_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURESTARTDELAY */ +#define _ECA_CAPTURESTARTDELAY_MASK 0xFFFFFFFFUL /**< Mask for ECA_CAPTURESTARTDELAY */ +#define _ECA_CAPTURESTARTDELAY_DELAY_SHIFT 0 /**< Shift value for ECA_DELAY */ +#define _ECA_CAPTURESTARTDELAY_DELAY_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_DELAY */ +#define _ECA_CAPTURESTARTDELAY_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURESTARTDELAY */ +#define ECA_CAPTURESTARTDELAY_DELAY_DEFAULT (_ECA_CAPTURESTARTDELAY_DELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURESTARTDELAY*/ + +/* Bit fields for ECA CAPTURESTOPDELAY */ +#define _ECA_CAPTURESTOPDELAY_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURESTOPDELAY */ +#define _ECA_CAPTURESTOPDELAY_MASK 0xFFFFFFFFUL /**< Mask for ECA_CAPTURESTOPDELAY */ +#define _ECA_CAPTURESTOPDELAY_DELAY_SHIFT 0 /**< Shift value for ECA_DELAY */ +#define _ECA_CAPTURESTOPDELAY_DELAY_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_DELAY */ +#define _ECA_CAPTURESTOPDELAY_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURESTOPDELAY */ +#define ECA_CAPTURESTOPDELAY_DELAY_DEFAULT (_ECA_CAPTURESTOPDELAY_DELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURESTOPDELAY*/ + +/* Bit fields for ECA CAPTURERATECTRL */ +#define _ECA_CAPTURERATECTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURERATECTRL */ +#define _ECA_CAPTURERATECTRL_MASK 0x0000FFFFUL /**< Mask for ECA_CAPTURERATECTRL */ +#define _ECA_CAPTURERATECTRL_RATE_SHIFT 0 /**< Shift value for ECA_RATE */ +#define _ECA_CAPTURERATECTRL_RATE_MASK 0xFFFFUL /**< Bit mask for ECA_RATE */ +#define _ECA_CAPTURERATECTRL_RATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURERATECTRL */ +#define ECA_CAPTURERATECTRL_RATE_DEFAULT (_ECA_CAPTURERATECTRL_RATE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURERATECTRL*/ + +/* Bit fields for ECA PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_RESETVALUE 0x00000014UL /**< Default value for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_MASK 0x0000001FUL /**< Mask for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_MODE (0x1UL << 0) /**< Playback Mode */ +#define _ECA_PLAYBACKCTRL_MODE_SHIFT 0 /**< Shift value for ECA_MODE */ +#define _ECA_PLAYBACKCTRL_MODE_MASK 0x1UL /**< Bit mask for ECA_MODE */ +#define _ECA_PLAYBACKCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_MODE_SINGLE 0x00000000UL /**< Mode SINGLE for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_MODE_LOOP 0x00000001UL /**< Mode LOOP for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_MODE_DEFAULT (_ECA_PLAYBACKCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_MODE_SINGLE (_ECA_PLAYBACKCTRL_MODE_SINGLE << 0) /**< Shifted mode SINGLE for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_MODE_LOOP (_ECA_PLAYBACKCTRL_MODE_LOOP << 0) /**< Shifted mode LOOP for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_COND (0x1UL << 1) /**< Playback Condition */ +#define _ECA_PLAYBACKCTRL_COND_SHIFT 1 /**< Shift value for ECA_COND */ +#define _ECA_PLAYBACKCTRL_COND_MASK 0x2UL /**< Bit mask for ECA_COND */ +#define _ECA_PLAYBACKCTRL_COND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_COND_START_TRIGGER 0x00000000UL /**< Mode START_TRIGGER for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_COND_TIMED 0x00000001UL /**< Mode TIMED for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_COND_DEFAULT (_ECA_PLAYBACKCTRL_COND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_COND_START_TRIGGER (_ECA_PLAYBACKCTRL_COND_START_TRIGGER << 1) /**< Shifted mode START_TRIGGER for ECA_PLAYBACKCTRL*/ +#define ECA_PLAYBACKCTRL_COND_TIMED (_ECA_PLAYBACKCTRL_COND_TIMED << 1) /**< Shifted mode TIMED for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_SHIFT 2 /**< Shift value for ECA_DATAWIDTH */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_MASK 0x1CUL /**< Bit mask for ECA_DATAWIDTH */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT 0x00000005UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 0x00000000UL /**< Mode BIT1 for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 0x00000001UL /**< Mode BIT2 for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 0x00000002UL /**< Mode BIT4 for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 0x00000003UL /**< Mode BIT8 for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 0x00000004UL /**< Mode BIT16 for ECA_PLAYBACKCTRL */ +#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 0x00000005UL /**< Mode BIT32 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT (_ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 << 2) /**< Shifted mode BIT1 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 << 2) /**< Shifted mode BIT2 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 << 2) /**< Shifted mode BIT4 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 << 2) /**< Shifted mode BIT8 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 << 2) /**< Shifted mode BIT16 for ECA_PLAYBACKCTRL */ +#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 << 2) /**< Shifted mode BIT32 for ECA_PLAYBACKCTRL */ + +/* Bit fields for ECA PLAYBACKRATECTRL */ +#define _ECA_PLAYBACKRATECTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_PLAYBACKRATECTRL */ +#define _ECA_PLAYBACKRATECTRL_MASK 0x0000FFFFUL /**< Mask for ECA_PLAYBACKRATECTRL */ +#define _ECA_PLAYBACKRATECTRL_RATE_SHIFT 0 /**< Shift value for ECA_RATE */ +#define _ECA_PLAYBACKRATECTRL_RATE_MASK 0xFFFFUL /**< Bit mask for ECA_RATE */ +#define _ECA_PLAYBACKRATECTRL_RATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKRATECTRL */ +#define ECA_PLAYBACKRATECTRL_RATE_DEFAULT (_ECA_PLAYBACKRATECTRL_RATE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_PLAYBACKRATECTRL*/ + +/* Bit fields for ECA EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_MASK 0x0000001FUL /**< Mask for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STARTMODE (0x1UL << 0) /**< Start Mode */ +#define _ECA_EVENTCNTRCTRL_STARTMODE_SHIFT 0 /**< Shift value for ECA_STARTMODE */ +#define _ECA_EVENTCNTRCTRL_STARTMODE_MASK 0x1UL /**< Bit mask for ECA_STARTMODE */ +#define _ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_STARTMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT (_ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STARTMODE_MANUAL (_ECA_EVENTCNTRCTRL_STARTMODE_MANUAL << 0) /**< Shifted mode MANUAL for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER (_ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER << 0) /**< Shifted mode START_TRIGGER for ECA_EVENTCNTRCTRL*/ +#define _ECA_EVENTCNTRCTRL_STOPMODE_SHIFT 1 /**< Shift value for ECA_STOPMODE */ +#define _ECA_EVENTCNTRCTRL_STOPMODE_MASK 0x6UL /**< Bit mask for ECA_STOPMODE */ +#define _ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_STOPMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER 0x00000001UL /**< Mode STOP_TRIGGER for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_STOPMODE_COMPARE 0x00000002UL /**< Mode COMPARE for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT (_ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STOPMODE_MANUAL (_ECA_EVENTCNTRCTRL_STOPMODE_MANUAL << 1) /**< Shifted mode MANUAL for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER (_ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER << 1) /**< Shifted mode STOP_TRIGGER for ECA_EVENTCNTRCTRL*/ +#define ECA_EVENTCNTRCTRL_STOPMODE_COMPARE (_ECA_EVENTCNTRCTRL_STOPMODE_COMPARE << 1) /**< Shifted mode COMPARE for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_SHIFT 3 /**< Shift value for ECA_COUNTMODE */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_MASK 0x18UL /**< Bit mask for ECA_COUNTMODE */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS 0x00000000UL /**< Mode ALWAYS for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER 0x00000002UL /**< Mode STOP_TRIGGER for ECA_EVENTCNTRCTRL */ +#define _ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER 0x00000003UL /**< Mode ALL_TRIGGER for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT (_ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS (_ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS << 3) /**< Shifted mode ALWAYS for ECA_EVENTCNTRCTRL */ +#define ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER << 3) /**< Shifted mode START_TRIGGER for ECA_EVENTCNTRCTRL*/ +#define ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER << 3) /**< Shifted mode STOP_TRIGGER for ECA_EVENTCNTRCTRL*/ +#define ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER << 3) /**< Shifted mode ALL_TRIGGER for ECA_EVENTCNTRCTRL*/ + +/* Bit fields for ECA EVENTCNTRCOMPARE */ +#define _ECA_EVENTCNTRCOMPARE_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRCOMPARE */ +#define _ECA_EVENTCNTRCOMPARE_MASK 0xFFFFFFFFUL /**< Mask for ECA_EVENTCNTRCOMPARE */ +#define _ECA_EVENTCNTRCOMPARE_COMPARE_SHIFT 0 /**< Shift value for ECA_COMPARE */ +#define _ECA_EVENTCNTRCOMPARE_COMPARE_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_COMPARE */ +#define _ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCOMPARE */ +#define ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT (_ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCOMPARE*/ + +/* Bit fields for ECA EVENTCNTRSTATUS */ +#define _ECA_EVENTCNTRSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRSTATUS */ +#define _ECA_EVENTCNTRSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_EVENTCNTRSTATUS */ +#define _ECA_EVENTCNTRSTATUS_STATUS_SHIFT 0 /**< Shift value for ECA_STATUS */ +#define _ECA_EVENTCNTRSTATUS_STATUS_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_STATUS */ +#define _ECA_EVENTCNTRSTATUS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRSTATUS */ +#define ECA_EVENTCNTRSTATUS_STATUS_DEFAULT (_ECA_EVENTCNTRSTATUS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRSTATUS*/ + +/** @} End of group EFR32MG24_ECA_BitFields */ +/** @} End of group EFR32MG24_ECA */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_ECA_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_ecaifadc.h b/EFR32MG24/Device/Include/efr32mg24_ecaifadc.h new file mode 100644 index 0000000..5605416 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_ecaifadc.h @@ -0,0 +1,134 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 ECAIFADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ECAIFADC_H +#define EFR32MG24_ECAIFADC_H +#define ECAIFADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ECAIFADC ECAIFADC + * @{ + * @brief EFR32MG24 ECAIFADC Register Declaration. + *****************************************************************************/ + +/** ECAIFADC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< New Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1019U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< New Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED3[1019U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< New Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED5[1019U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< New Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ +} ECAIFADC_TypeDef; +/** @} End of group EFR32MG24_ECAIFADC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ECAIFADC + * @{ + * @defgroup EFR32MG24_ECAIFADC_BitFields ECAIFADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ECAIFADC IPVERSION */ +#define _ECAIFADC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ECAIFADC_IPVERSION */ +#define _ECAIFADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ECAIFADC_IPVERSION */ +#define _ECAIFADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ECAIFADC_IPVERSION */ +#define _ECAIFADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ECAIFADC_IPVERSION */ +#define _ECAIFADC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECAIFADC_IPVERSION */ +#define ECAIFADC_IPVERSION_IPVERSION_DEFAULT (_ECAIFADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_IPVERSION */ + +/* Bit fields for ECAIFADC EN */ +#define _ECAIFADC_EN_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_EN */ +#define _ECAIFADC_EN_MASK 0x00000001UL /**< Mask for ECAIFADC_EN */ +#define ECAIFADC_EN_EN (0x1UL << 0) /**< IFADC Debug Enable */ +#define _ECAIFADC_EN_EN_SHIFT 0 /**< Shift value for ECAIFADC_EN */ +#define _ECAIFADC_EN_EN_MASK 0x1UL /**< Bit mask for ECAIFADC_EN */ +#define _ECAIFADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_EN */ +#define ECAIFADC_EN_EN_DEFAULT (_ECAIFADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_EN */ + +/* Bit fields for ECAIFADC CTRL */ +#define _ECAIFADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_MASK 0x00000007UL /**< Mask for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_MODE (0x1UL << 0) /**< Mode */ +#define _ECAIFADC_CTRL_MODE_SHIFT 0 /**< Shift value for ECAIFADC_MODE */ +#define _ECAIFADC_CTRL_MODE_MASK 0x1UL /**< Bit mask for ECAIFADC_MODE */ +#define _ECAIFADC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_MODE_MP 0x00000000UL /**< Mode MP for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_MODE_IQ 0x00000001UL /**< Mode IQ for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_MODE_DEFAULT (_ECAIFADC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_MODE_MP (_ECAIFADC_CTRL_MODE_MP << 0) /**< Shifted mode MP for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_MODE_IQ (_ECAIFADC_CTRL_MODE_IQ << 0) /**< Shifted mode IQ for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_IQSEL_SHIFT 1 /**< Shift value for ECAIFADC_IQSEL */ +#define _ECAIFADC_CTRL_IQSEL_MASK 0x6UL /**< Bit mask for ECAIFADC_IQSEL */ +#define _ECAIFADC_CTRL_IQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_IQSEL_NA 0x00000000UL /**< Mode NA for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_IQSEL_IONLY 0x00000001UL /**< Mode IONLY for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_IQSEL_QONLY 0x00000002UL /**< Mode QONLY for ECAIFADC_CTRL */ +#define _ECAIFADC_CTRL_IQSEL_IANDQ 0x00000003UL /**< Mode IANDQ for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_IQSEL_DEFAULT (_ECAIFADC_CTRL_IQSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_IQSEL_NA (_ECAIFADC_CTRL_IQSEL_NA << 1) /**< Shifted mode NA for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_IQSEL_IONLY (_ECAIFADC_CTRL_IQSEL_IONLY << 1) /**< Shifted mode IONLY for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_IQSEL_QONLY (_ECAIFADC_CTRL_IQSEL_QONLY << 1) /**< Shifted mode QONLY for ECAIFADC_CTRL */ +#define ECAIFADC_CTRL_IQSEL_IANDQ (_ECAIFADC_CTRL_IQSEL_IANDQ << 1) /**< Shifted mode IANDQ for ECAIFADC_CTRL */ + +/* Bit fields for ECAIFADC STATUS */ +#define _ECAIFADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_STATUS */ +#define _ECAIFADC_STATUS_MASK 0x00000001UL /**< Mask for ECAIFADC_STATUS */ +#define ECAIFADC_STATUS_OVERFLOW (0x1UL << 0) /**< Capture Overflow */ +#define _ECAIFADC_STATUS_OVERFLOW_SHIFT 0 /**< Shift value for ECAIFADC_OVERFLOW */ +#define _ECAIFADC_STATUS_OVERFLOW_MASK 0x1UL /**< Bit mask for ECAIFADC_OVERFLOW */ +#define _ECAIFADC_STATUS_OVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_STATUS */ +#define ECAIFADC_STATUS_OVERFLOW_DEFAULT (_ECAIFADC_STATUS_OVERFLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_STATUS */ + +/** @} End of group EFR32MG24_ECAIFADC_BitFields */ +/** @} End of group EFR32MG24_ECAIFADC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_ECAIFADC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_emu.h b/EFR32MG24/Device/Include/efr32mg24_emu.h new file mode 100644 index 0000000..90a1693 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_emu.h @@ -0,0 +1,803 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_EMU_H +#define EFR32MG24_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_EMU EMU + * @{ + * @brief EFR32MG24 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct { + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + __IOM uint32_t SEQIF; /**< Interrupt Flags Sequencer */ + __IOM uint32_t SEQIEN; /**< Interrupt Enables Sequencer */ + uint32_t RESERVED7[4U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + uint32_t RESERVED21[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + __IOM uint32_t SEQIF_SET; /**< Interrupt Flags Sequencer */ + __IOM uint32_t SEQIEN_SET; /**< Interrupt Enables Sequencer */ + uint32_t RESERVED22[4U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + __IOM uint32_t SEQIF_CLR; /**< Interrupt Flags Sequencer */ + __IOM uint32_t SEQIEN_CLR; /**< Interrupt Enables Sequencer */ + uint32_t RESERVED37[4U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + uint32_t RESERVED51[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + __IOM uint32_t SEQIF_TGL; /**< Interrupt Flags Sequencer */ + __IOM uint32_t SEQIEN_TGL; /**< Interrupt Enables Sequencer */ + uint32_t RESERVED52[4U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group EFR32MG24_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_EMU + * @{ + * @defgroup EFR32MG24_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFEFFFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 8) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 8 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x100UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 9) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 9 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x200UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 10) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 10 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x400UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU SEQIF */ +#define _EMU_SEQIF_RESETVALUE 0x00000000UL /**< Default value for EMU_SEQIF */ +#define _EMU_SEQIF_MASK 0xE0000000UL /**< Mask for EMU_SEQIF */ +#define EMU_SEQIF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_SEQIF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_SEQIF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_SEQIF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */ +#define EMU_SEQIF_TEMP_DEFAULT (_EMU_SEQIF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEQIF */ +#define EMU_SEQIF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_SEQIF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_SEQIF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_SEQIF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */ +#define EMU_SEQIF_TEMPLOW_DEFAULT (_EMU_SEQIF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEQIF */ +#define EMU_SEQIF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_SEQIF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_SEQIF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_SEQIF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */ +#define EMU_SEQIF_TEMPHIGH_DEFAULT (_EMU_SEQIF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEQIF */ + +/* Bit fields for EMU SEQIEN */ +#define _EMU_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_SEQIEN */ +#define _EMU_SEQIEN_MASK 0xE0000000UL /**< Mask for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_SEQIEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_SEQIEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_SEQIEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMP_DEFAULT (_EMU_SEQIEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_SEQIEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_SEQIEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_SEQIEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMPLOW_DEFAULT (_EMU_SEQIEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_SEQIEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_SEQIEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_SEQIEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */ +#define EMU_SEQIEN_TEMPHIGH_DEFAULT (_EMU_SEQIEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEQIEN */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32MG24_EMU_BitFields */ +/** @} End of group EFR32MG24_EMU */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_EMU_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_eusart.h b/EFR32MG24/Device/Include/efr32mg24_eusart.h new file mode 100644 index 0000000..320131b --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_eusart.h @@ -0,0 +1,1319 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_EUSART_H +#define EFR32MG24_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_EUSART EUSART + * @{ + * @brief EFR32MG24 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG; /**< DALI Config Register */ + uint32_t RESERVED0[41U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_SET; /**< DALI Config Register */ + uint32_t RESERVED3[41U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_CLR; /**< DALI Config Register */ + uint32_t RESERVED6[41U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_TGL; /**< DALI Config Register */ + uint32_t RESERVED9[41U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group EFR32MG24_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_EUSART + * @{ + * @defgroup EFR32MG24_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/* Bit fields for EUSART DALICFG */ +#define _EUSART_DALICFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DALICFG */ +#define _EUSART_DALICFG_MASK 0x00009F3FUL /**< Mask for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN (0x1UL << 0) /**< DALI Enable Bit */ +#define _EUSART_DALICFG_DALIEN_SHIFT 0 /**< Shift value for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_MASK 0x1UL /**< Bit mask for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN_DEFAULT (_EUSART_DALICFG_DALIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SHIFT 1 /**< Shift value for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_MASK 0x3EUL /**< Bit mask for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_DEFAULT (_EUSART_DALICFG_DALITXDATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHT (_EUSART_DALICFG_DALITXDATABITS_EIGHT << 1) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINE (_EUSART_DALICFG_DALITXDATABITS_NINE << 1) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TEN (_EUSART_DALICFG_DALITXDATABITS_TEN << 1) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_ELEVEN (_EUSART_DALICFG_DALITXDATABITS_ELEVEN << 1) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWELVE (_EUSART_DALICFG_DALITXDATABITS_TWELVE << 1) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTEEN (_EUSART_DALICFG_DALITXDATABITS_THIRTEEN << 1) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FOURTEEN (_EUSART_DALICFG_DALITXDATABITS_FOURTEEN << 1) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FIFTEEN (_EUSART_DALICFG_DALITXDATABITS_FIFTEEN << 1) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SIXTEEN (_EUSART_DALICFG_DALITXDATABITS_SIXTEEN << 1) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALITXDATABITS_SEVENTEEN << 1) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALITXDATABITS_EIGHTEEN << 1) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINETEEN (_EUSART_DALICFG_DALITXDATABITS_NINETEEN << 1) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTY (_EUSART_DALICFG_DALITXDATABITS_TWENTY << 1) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYONE (_EUSART_DALICFG_DALITXDATABITS_TWENTYONE << 1) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALITXDATABITS_TWENTYTWO << 1) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE << 1) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR << 1) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE << 1) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALITXDATABITS_TWENTYSIX << 1) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN << 1) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT << 1) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALITXDATABITS_TWENTYNINE << 1) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTY (_EUSART_DALICFG_DALITXDATABITS_THIRTY << 1) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYONE (_EUSART_DALICFG_DALITXDATABITS_THIRTYONE << 1) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALITXDATABITS_THIRTYTWO << 1) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SHIFT 8 /**< Shift value for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_MASK 0x1F00UL /**< Bit mask for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_DEFAULT (_EUSART_DALICFG_DALIRXDATABITS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHT (_EUSART_DALICFG_DALIRXDATABITS_EIGHT << 8) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINE (_EUSART_DALICFG_DALIRXDATABITS_NINE << 8) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TEN (_EUSART_DALICFG_DALIRXDATABITS_TEN << 8) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_ELEVEN (_EUSART_DALICFG_DALIRXDATABITS_ELEVEN << 8) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWELVE (_EUSART_DALICFG_DALIRXDATABITS_TWELVE << 8) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTEEN (_EUSART_DALICFG_DALIRXDATABITS_THIRTEEN << 8) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FOURTEEN (_EUSART_DALICFG_DALIRXDATABITS_FOURTEEN << 8) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FIFTEEN (_EUSART_DALICFG_DALIRXDATABITS_FIFTEEN << 8) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SIXTEEN (_EUSART_DALICFG_DALIRXDATABITS_SIXTEEN << 8) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN << 8) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN << 8) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINETEEN (_EUSART_DALICFG_DALIRXDATABITS_NINETEEN << 8) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTY (_EUSART_DALICFG_DALIRXDATABITS_TWENTY << 8) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYONE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYONE << 8) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO << 8) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE << 8) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR << 8) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE << 8) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX << 8) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN << 8) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT << 8) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE << 8) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTY (_EUSART_DALICFG_DALIRXDATABITS_THIRTY << 8) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYONE (_EUSART_DALICFG_DALIRXDATABITS_THIRTYONE << 8) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO << 8) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT (0x1UL << 15) /**< DALI RX Enabled During Transmission */ +#define _EUSART_DALICFG_DALIRXENDT_SHIFT 15 /**< Shift value for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_MASK 0x8000UL /**< Bit mask for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT_DEFAULT (_EUSART_DALICFG_DALIRXENDT_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_DALICFG */ + +/** @} End of group EFR32MG24_EUSART_BitFields */ +/** @} End of group EFR32MG24_EUSART */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_EUSART_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_frc.h b/EFR32MG24/Device/Include/efr32mg24_frc.h new file mode 100644 index 0000000..8685419 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_frc.h @@ -0,0 +1,2608 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 FRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_FRC_H +#define EFR32MG24_FRC_H +#define FRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_FRC FRC + * @{ + * @brief EFR32MG24 FRC Register Declaration. + *****************************************************************************/ + +/** FRC FCD Register Group Declaration. */ +typedef struct { + __IOM uint32_t FCD; /**< Frame Control Descriptor */ +} FRC_FCD_TypeDef; + +/** FRC INTELEMENT Register Group Declaration. */ +typedef struct { + __IM uint32_t INTELEMENT; /**< Interleaver element value */ +} FRC_INTELEMENT_TypeDef; + +/** FRC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS; /**< FRC Status */ + __IOM uint32_t DFLCTRL; /**< Dynamic Frame Length Control */ + __IOM uint32_t MAXLENGTH; /**< Maximum Frame Length Register */ + __IOM uint32_t ADDRFILTCTRL; /**< Address Filter Control */ + __IOM uint32_t DATABUFFER; /**< Frame controller data buffer */ + __IM uint32_t WCNT; /**< Word Counter Value Register */ + __IOM uint32_t WCNTCMP0; /**< Word Counter Compare 0 */ + __IOM uint32_t WCNTCMP1; /**< Word Counter Compare 1 */ + __IOM uint32_t WCNTCMP2; /**< Word Counter Compare 2 */ + __IOM uint32_t CMD; /**< FRC Commands */ + __IOM uint32_t WHITECTRL; /**< Whitener Control */ + __IOM uint32_t WHITEPOLY; /**< Whitener Polynomial */ + __IOM uint32_t WHITEINIT; /**< Whitener Initial Value */ + __IOM uint32_t FECCTRL; /**< Forward Error Correction Control */ + __IOM uint32_t BLOCKRAMADDR; /**< Block decoding RAM address register */ + __IOM uint32_t CONVRAMADDR; /**< Convolutional decoding RAM address */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t RXCTRL; /**< RX Control Register */ + __IOM uint32_t TRAILTXDATACTRL; /**< Trailing TX Data Control */ + __IOM uint32_t TRAILRXDATA; /**< Trailing RX Data */ + __IM uint32_t SCNT; /**< Sub-Frame Counter Value Register */ + __IOM uint32_t CONVGENERATOR; /**< Convolutional Coder Polynomials */ + __IOM uint32_t PUNCTCTRL; /**< Puncturing Control */ + __IOM uint32_t PAUSECTRL; /**< Pause Control */ + __IOM uint32_t IF; /**< Frame Controller Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t OTACNT; /**< Over the air number of bits counter */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFFERMODE; /**< FRC Buffer Control */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t SNIFFCTRL; /**< FRC Sniffer Control Register */ + __IOM uint32_t AUXDATA; /**< Auxiliary sniffer data output register */ + __IOM uint32_t RAWCTRL; /**< Raw data control */ + __IM uint32_t RXRAWDATA; /**< Receiver RAW data */ + __IM uint32_t PAUSEDATA; /**< Receiver pause data */ + __IM uint32_t LIKELYCONVSTATE; /**< Most likely convolutional decoder state */ + __IM uint32_t INTELEMENTNEXT; /**< Interleaver element value */ + __IOM uint32_t INTWRITEPOINT; /**< Interleaver write pointer */ + __IOM uint32_t INTREADPOINT; /**< Interleaver read pointer */ + __IOM uint32_t AUTOCG; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP; /**< Automatic clock gating */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t SEQIF; /**< SEQ Frame Controller Interrupt Flags */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t WCNTCMP3; /**< Word Counter Compare 3 */ + __IOM uint32_t BOICTRL; /**< Bit of Interest Control */ + __IOM uint32_t DSLCTRL; /**< Dynamic Supp Length Control */ + __IOM uint32_t WCNTCMP4; /**< Word Counter Compare 4 */ + __IOM uint32_t WCNTCMP5; /**< Word Counter Compare 5 */ + __IOM uint32_t PKTBUFCTRL; /**< Packet Capture Buffer Ctrl */ + __IM uint32_t PKTBUFSTATUS; /**< Packet Capture Buffer Status */ + __IM uint32_t PKTBUF0; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF1; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF2; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF3; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF4; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF5; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF6; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF7; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF8; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF9; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF10; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF11; /**< Packet Capture Data Buffer */ + FRC_FCD_TypeDef FCD[4U]; /**< Frame Descriptors */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + FRC_INTELEMENT_TypeDef INTELEMENT[16U]; /**< Interleaver element */ + __IOM uint32_t AHBCONFIG; /**< AHB Configuration */ + uint32_t RESERVED4[927U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_SET; /**< FRC Status */ + __IOM uint32_t DFLCTRL_SET; /**< Dynamic Frame Length Control */ + __IOM uint32_t MAXLENGTH_SET; /**< Maximum Frame Length Register */ + __IOM uint32_t ADDRFILTCTRL_SET; /**< Address Filter Control */ + __IOM uint32_t DATABUFFER_SET; /**< Frame controller data buffer */ + __IM uint32_t WCNT_SET; /**< Word Counter Value Register */ + __IOM uint32_t WCNTCMP0_SET; /**< Word Counter Compare 0 */ + __IOM uint32_t WCNTCMP1_SET; /**< Word Counter Compare 1 */ + __IOM uint32_t WCNTCMP2_SET; /**< Word Counter Compare 2 */ + __IOM uint32_t CMD_SET; /**< FRC Commands */ + __IOM uint32_t WHITECTRL_SET; /**< Whitener Control */ + __IOM uint32_t WHITEPOLY_SET; /**< Whitener Polynomial */ + __IOM uint32_t WHITEINIT_SET; /**< Whitener Initial Value */ + __IOM uint32_t FECCTRL_SET; /**< Forward Error Correction Control */ + __IOM uint32_t BLOCKRAMADDR_SET; /**< Block decoding RAM address register */ + __IOM uint32_t CONVRAMADDR_SET; /**< Convolutional decoding RAM address */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t RXCTRL_SET; /**< RX Control Register */ + __IOM uint32_t TRAILTXDATACTRL_SET; /**< Trailing TX Data Control */ + __IOM uint32_t TRAILRXDATA_SET; /**< Trailing RX Data */ + __IM uint32_t SCNT_SET; /**< Sub-Frame Counter Value Register */ + __IOM uint32_t CONVGENERATOR_SET; /**< Convolutional Coder Polynomials */ + __IOM uint32_t PUNCTCTRL_SET; /**< Puncturing Control */ + __IOM uint32_t PAUSECTRL_SET; /**< Pause Control */ + __IOM uint32_t IF_SET; /**< Frame Controller Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t OTACNT_SET; /**< Over the air number of bits counter */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFFERMODE_SET; /**< FRC Buffer Control */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t SNIFFCTRL_SET; /**< FRC Sniffer Control Register */ + __IOM uint32_t AUXDATA_SET; /**< Auxiliary sniffer data output register */ + __IOM uint32_t RAWCTRL_SET; /**< Raw data control */ + __IM uint32_t RXRAWDATA_SET; /**< Receiver RAW data */ + __IM uint32_t PAUSEDATA_SET; /**< Receiver pause data */ + __IM uint32_t LIKELYCONVSTATE_SET; /**< Most likely convolutional decoder state */ + __IM uint32_t INTELEMENTNEXT_SET; /**< Interleaver element value */ + __IOM uint32_t INTWRITEPOINT_SET; /**< Interleaver write pointer */ + __IOM uint32_t INTREADPOINT_SET; /**< Interleaver read pointer */ + __IOM uint32_t AUTOCG_SET; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_SET; /**< Automatic clock gating */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t SEQIF_SET; /**< SEQ Frame Controller Interrupt Flags */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t WCNTCMP3_SET; /**< Word Counter Compare 3 */ + __IOM uint32_t BOICTRL_SET; /**< Bit of Interest Control */ + __IOM uint32_t DSLCTRL_SET; /**< Dynamic Supp Length Control */ + __IOM uint32_t WCNTCMP4_SET; /**< Word Counter Compare 4 */ + __IOM uint32_t WCNTCMP5_SET; /**< Word Counter Compare 5 */ + __IOM uint32_t PKTBUFCTRL_SET; /**< Packet Capture Buffer Ctrl */ + __IM uint32_t PKTBUFSTATUS_SET; /**< Packet Capture Buffer Status */ + __IM uint32_t PKTBUF0_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF1_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF2_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF3_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF4_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF5_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF6_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF7_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF8_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF9_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF10_SET; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF11_SET; /**< Packet Capture Data Buffer */ + FRC_FCD_TypeDef FCD_SET[4U]; /**< Frame Descriptors */ + uint32_t RESERVED8[10U]; /**< Reserved for future use */ + FRC_INTELEMENT_TypeDef INTELEMENT_SET[16U]; /**< Interleaver element */ + __IOM uint32_t AHBCONFIG_SET; /**< AHB Configuration */ + uint32_t RESERVED9[927U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_CLR; /**< FRC Status */ + __IOM uint32_t DFLCTRL_CLR; /**< Dynamic Frame Length Control */ + __IOM uint32_t MAXLENGTH_CLR; /**< Maximum Frame Length Register */ + __IOM uint32_t ADDRFILTCTRL_CLR; /**< Address Filter Control */ + __IOM uint32_t DATABUFFER_CLR; /**< Frame controller data buffer */ + __IM uint32_t WCNT_CLR; /**< Word Counter Value Register */ + __IOM uint32_t WCNTCMP0_CLR; /**< Word Counter Compare 0 */ + __IOM uint32_t WCNTCMP1_CLR; /**< Word Counter Compare 1 */ + __IOM uint32_t WCNTCMP2_CLR; /**< Word Counter Compare 2 */ + __IOM uint32_t CMD_CLR; /**< FRC Commands */ + __IOM uint32_t WHITECTRL_CLR; /**< Whitener Control */ + __IOM uint32_t WHITEPOLY_CLR; /**< Whitener Polynomial */ + __IOM uint32_t WHITEINIT_CLR; /**< Whitener Initial Value */ + __IOM uint32_t FECCTRL_CLR; /**< Forward Error Correction Control */ + __IOM uint32_t BLOCKRAMADDR_CLR; /**< Block decoding RAM address register */ + __IOM uint32_t CONVRAMADDR_CLR; /**< Convolutional decoding RAM address */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t RXCTRL_CLR; /**< RX Control Register */ + __IOM uint32_t TRAILTXDATACTRL_CLR; /**< Trailing TX Data Control */ + __IOM uint32_t TRAILRXDATA_CLR; /**< Trailing RX Data */ + __IM uint32_t SCNT_CLR; /**< Sub-Frame Counter Value Register */ + __IOM uint32_t CONVGENERATOR_CLR; /**< Convolutional Coder Polynomials */ + __IOM uint32_t PUNCTCTRL_CLR; /**< Puncturing Control */ + __IOM uint32_t PAUSECTRL_CLR; /**< Pause Control */ + __IOM uint32_t IF_CLR; /**< Frame Controller Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t OTACNT_CLR; /**< Over the air number of bits counter */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFFERMODE_CLR; /**< FRC Buffer Control */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SNIFFCTRL_CLR; /**< FRC Sniffer Control Register */ + __IOM uint32_t AUXDATA_CLR; /**< Auxiliary sniffer data output register */ + __IOM uint32_t RAWCTRL_CLR; /**< Raw data control */ + __IM uint32_t RXRAWDATA_CLR; /**< Receiver RAW data */ + __IM uint32_t PAUSEDATA_CLR; /**< Receiver pause data */ + __IM uint32_t LIKELYCONVSTATE_CLR; /**< Most likely convolutional decoder state */ + __IM uint32_t INTELEMENTNEXT_CLR; /**< Interleaver element value */ + __IOM uint32_t INTWRITEPOINT_CLR; /**< Interleaver write pointer */ + __IOM uint32_t INTREADPOINT_CLR; /**< Interleaver read pointer */ + __IOM uint32_t AUTOCG_CLR; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_CLR; /**< Automatic clock gating */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Frame Controller Interrupt Flags */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t WCNTCMP3_CLR; /**< Word Counter Compare 3 */ + __IOM uint32_t BOICTRL_CLR; /**< Bit of Interest Control */ + __IOM uint32_t DSLCTRL_CLR; /**< Dynamic Supp Length Control */ + __IOM uint32_t WCNTCMP4_CLR; /**< Word Counter Compare 4 */ + __IOM uint32_t WCNTCMP5_CLR; /**< Word Counter Compare 5 */ + __IOM uint32_t PKTBUFCTRL_CLR; /**< Packet Capture Buffer Ctrl */ + __IM uint32_t PKTBUFSTATUS_CLR; /**< Packet Capture Buffer Status */ + __IM uint32_t PKTBUF0_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF1_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF2_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF3_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF4_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF5_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF6_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF7_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF8_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF9_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF10_CLR; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF11_CLR; /**< Packet Capture Data Buffer */ + FRC_FCD_TypeDef FCD_CLR[4U]; /**< Frame Descriptors */ + uint32_t RESERVED13[10U]; /**< Reserved for future use */ + FRC_INTELEMENT_TypeDef INTELEMENT_CLR[16U]; /**< Interleaver element */ + __IOM uint32_t AHBCONFIG_CLR; /**< AHB Configuration */ + uint32_t RESERVED14[927U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_TGL; /**< FRC Status */ + __IOM uint32_t DFLCTRL_TGL; /**< Dynamic Frame Length Control */ + __IOM uint32_t MAXLENGTH_TGL; /**< Maximum Frame Length Register */ + __IOM uint32_t ADDRFILTCTRL_TGL; /**< Address Filter Control */ + __IOM uint32_t DATABUFFER_TGL; /**< Frame controller data buffer */ + __IM uint32_t WCNT_TGL; /**< Word Counter Value Register */ + __IOM uint32_t WCNTCMP0_TGL; /**< Word Counter Compare 0 */ + __IOM uint32_t WCNTCMP1_TGL; /**< Word Counter Compare 1 */ + __IOM uint32_t WCNTCMP2_TGL; /**< Word Counter Compare 2 */ + __IOM uint32_t CMD_TGL; /**< FRC Commands */ + __IOM uint32_t WHITECTRL_TGL; /**< Whitener Control */ + __IOM uint32_t WHITEPOLY_TGL; /**< Whitener Polynomial */ + __IOM uint32_t WHITEINIT_TGL; /**< Whitener Initial Value */ + __IOM uint32_t FECCTRL_TGL; /**< Forward Error Correction Control */ + __IOM uint32_t BLOCKRAMADDR_TGL; /**< Block decoding RAM address register */ + __IOM uint32_t CONVRAMADDR_TGL; /**< Convolutional decoding RAM address */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t RXCTRL_TGL; /**< RX Control Register */ + __IOM uint32_t TRAILTXDATACTRL_TGL; /**< Trailing TX Data Control */ + __IOM uint32_t TRAILRXDATA_TGL; /**< Trailing RX Data */ + __IM uint32_t SCNT_TGL; /**< Sub-Frame Counter Value Register */ + __IOM uint32_t CONVGENERATOR_TGL; /**< Convolutional Coder Polynomials */ + __IOM uint32_t PUNCTCTRL_TGL; /**< Puncturing Control */ + __IOM uint32_t PAUSECTRL_TGL; /**< Pause Control */ + __IOM uint32_t IF_TGL; /**< Frame Controller Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t OTACNT_TGL; /**< Over the air number of bits counter */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFFERMODE_TGL; /**< FRC Buffer Control */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t SNIFFCTRL_TGL; /**< FRC Sniffer Control Register */ + __IOM uint32_t AUXDATA_TGL; /**< Auxiliary sniffer data output register */ + __IOM uint32_t RAWCTRL_TGL; /**< Raw data control */ + __IM uint32_t RXRAWDATA_TGL; /**< Receiver RAW data */ + __IM uint32_t PAUSEDATA_TGL; /**< Receiver pause data */ + __IM uint32_t LIKELYCONVSTATE_TGL; /**< Most likely convolutional decoder state */ + __IM uint32_t INTELEMENTNEXT_TGL; /**< Interleaver element value */ + __IOM uint32_t INTWRITEPOINT_TGL; /**< Interleaver write pointer */ + __IOM uint32_t INTREADPOINT_TGL; /**< Interleaver read pointer */ + __IOM uint32_t AUTOCG_TGL; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_TGL; /**< Automatic clock gating */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Frame Controller Interrupt Flags */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ + __IOM uint32_t WCNTCMP3_TGL; /**< Word Counter Compare 3 */ + __IOM uint32_t BOICTRL_TGL; /**< Bit of Interest Control */ + __IOM uint32_t DSLCTRL_TGL; /**< Dynamic Supp Length Control */ + __IOM uint32_t WCNTCMP4_TGL; /**< Word Counter Compare 4 */ + __IOM uint32_t WCNTCMP5_TGL; /**< Word Counter Compare 5 */ + __IOM uint32_t PKTBUFCTRL_TGL; /**< Packet Capture Buffer Ctrl */ + __IM uint32_t PKTBUFSTATUS_TGL; /**< Packet Capture Buffer Status */ + __IM uint32_t PKTBUF0_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF1_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF2_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF3_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF4_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF5_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF6_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF7_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF8_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF9_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF10_TGL; /**< Packet Capture Data Buffer */ + __IM uint32_t PKTBUF11_TGL; /**< Packet Capture Data Buffer */ + FRC_FCD_TypeDef FCD_TGL[4U]; /**< Frame Descriptors */ + uint32_t RESERVED18[10U]; /**< Reserved for future use */ + FRC_INTELEMENT_TypeDef INTELEMENT_TGL[16U]; /**< Interleaver element */ + __IOM uint32_t AHBCONFIG_TGL; /**< AHB Configuration */ +} FRC_TypeDef; +/** @} End of group EFR32MG24_FRC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_FRC + * @{ + * @defgroup EFR32MG24_FRC_BitFields FRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FRC IPVERSION */ +#define _FRC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for FRC_IPVERSION */ +#define _FRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FRC_IPVERSION */ +#define _FRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FRC_IPVERSION */ +#define _FRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_IPVERSION */ +#define _FRC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for FRC_IPVERSION */ +#define FRC_IPVERSION_IPVERSION_DEFAULT (_FRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IPVERSION */ + +/* Bit fields for FRC EN */ +#define _FRC_EN_RESETVALUE 0x00000000UL /**< Default value for FRC_EN */ +#define _FRC_EN_MASK 0x00000001UL /**< Mask for FRC_EN */ +#define FRC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _FRC_EN_EN_SHIFT 0 /**< Shift value for FRC_EN */ +#define _FRC_EN_EN_MASK 0x1UL /**< Bit mask for FRC_EN */ +#define _FRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_EN */ +#define FRC_EN_EN_DEFAULT (_FRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_EN */ + +/* Bit fields for FRC STATUS */ +#define _FRC_STATUS_RESETVALUE 0x00000000UL /**< Default value for FRC_STATUS */ +#define _FRC_STATUS_MASK 0x07FFFFFFUL /**< Mask for FRC_STATUS */ +#define _FRC_STATUS_SNIFFDCOUNT_SHIFT 0 /**< Shift value for FRC_SNIFFDCOUNT */ +#define _FRC_STATUS_SNIFFDCOUNT_MASK 0x1FUL /**< Bit mask for FRC_SNIFFDCOUNT */ +#define _FRC_STATUS_SNIFFDCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_SNIFFDCOUNT_DEFAULT (_FRC_STATUS_SNIFFDCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_ACTIVETXFCD (0x1UL << 5) /**< Active Transmit Frame Descriptor */ +#define _FRC_STATUS_ACTIVETXFCD_SHIFT 5 /**< Shift value for FRC_ACTIVETXFCD */ +#define _FRC_STATUS_ACTIVETXFCD_MASK 0x20UL /**< Bit mask for FRC_ACTIVETXFCD */ +#define _FRC_STATUS_ACTIVETXFCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define _FRC_STATUS_ACTIVETXFCD_FCD0 0x00000000UL /**< Mode FCD0 for FRC_STATUS */ +#define _FRC_STATUS_ACTIVETXFCD_FCD1 0x00000001UL /**< Mode FCD1 for FRC_STATUS */ +#define FRC_STATUS_ACTIVETXFCD_DEFAULT (_FRC_STATUS_ACTIVETXFCD_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_ACTIVETXFCD_FCD0 (_FRC_STATUS_ACTIVETXFCD_FCD0 << 5) /**< Shifted mode FCD0 for FRC_STATUS */ +#define FRC_STATUS_ACTIVETXFCD_FCD1 (_FRC_STATUS_ACTIVETXFCD_FCD1 << 5) /**< Shifted mode FCD1 for FRC_STATUS */ +#define FRC_STATUS_ACTIVERXFCD (0x1UL << 6) /**< Active Receive Frame Descriptor */ +#define _FRC_STATUS_ACTIVERXFCD_SHIFT 6 /**< Shift value for FRC_ACTIVERXFCD */ +#define _FRC_STATUS_ACTIVERXFCD_MASK 0x40UL /**< Bit mask for FRC_ACTIVERXFCD */ +#define _FRC_STATUS_ACTIVERXFCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define _FRC_STATUS_ACTIVERXFCD_FCD2 0x00000000UL /**< Mode FCD2 for FRC_STATUS */ +#define _FRC_STATUS_ACTIVERXFCD_FCD3 0x00000001UL /**< Mode FCD3 for FRC_STATUS */ +#define FRC_STATUS_ACTIVERXFCD_DEFAULT (_FRC_STATUS_ACTIVERXFCD_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_ACTIVERXFCD_FCD2 (_FRC_STATUS_ACTIVERXFCD_FCD2 << 6) /**< Shifted mode FCD2 for FRC_STATUS */ +#define FRC_STATUS_ACTIVERXFCD_FCD3 (_FRC_STATUS_ACTIVERXFCD_FCD3 << 6) /**< Shifted mode FCD3 for FRC_STATUS */ +#define FRC_STATUS_SNIFFDFRAME (0x1UL << 7) /**< Sniffer data frame active status */ +#define _FRC_STATUS_SNIFFDFRAME_SHIFT 7 /**< Shift value for FRC_SNIFFDFRAME */ +#define _FRC_STATUS_SNIFFDFRAME_MASK 0x80UL /**< Bit mask for FRC_SNIFFDFRAME */ +#define _FRC_STATUS_SNIFFDFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_SNIFFDFRAME_DEFAULT (_FRC_STATUS_SNIFFDFRAME_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXRAWBLOCKED (0x1UL << 8) /**< Receiver raw trigger block is active */ +#define _FRC_STATUS_RXRAWBLOCKED_SHIFT 8 /**< Shift value for FRC_RXRAWBLOCKED */ +#define _FRC_STATUS_RXRAWBLOCKED_MASK 0x100UL /**< Bit mask for FRC_RXRAWBLOCKED */ +#define _FRC_STATUS_RXRAWBLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXRAWBLOCKED_DEFAULT (_FRC_STATUS_RXRAWBLOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMEOK (0x1UL << 9) /**< Frame valid */ +#define _FRC_STATUS_FRAMEOK_SHIFT 9 /**< Shift value for FRC_FRAMEOK */ +#define _FRC_STATUS_FRAMEOK_MASK 0x200UL /**< Bit mask for FRC_FRAMEOK */ +#define _FRC_STATUS_FRAMEOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMEOK_DEFAULT (_FRC_STATUS_FRAMEOK_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXABORTINPROGRESS (0x1UL << 10) /**< Receive aborted in progress status flag */ +#define _FRC_STATUS_RXABORTINPROGRESS_SHIFT 10 /**< Shift value for FRC_RXABORTINPROGRESS */ +#define _FRC_STATUS_RXABORTINPROGRESS_MASK 0x400UL /**< Bit mask for FRC_RXABORTINPROGRESS */ +#define _FRC_STATUS_RXABORTINPROGRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXABORTINPROGRESS_DEFAULT (_FRC_STATUS_RXABORTINPROGRESS_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_TXWORD (0x1UL << 11) /**< Transmit Word Flag */ +#define _FRC_STATUS_TXWORD_SHIFT 11 /**< Shift value for FRC_TXWORD */ +#define _FRC_STATUS_TXWORD_MASK 0x800UL /**< Bit mask for FRC_TXWORD */ +#define _FRC_STATUS_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_TXWORD_DEFAULT (_FRC_STATUS_TXWORD_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXWORD (0x1UL << 12) /**< Receive Word Flag */ +#define _FRC_STATUS_RXWORD_SHIFT 12 /**< Shift value for FRC_RXWORD */ +#define _FRC_STATUS_RXWORD_MASK 0x1000UL /**< Bit mask for FRC_RXWORD */ +#define _FRC_STATUS_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXWORD_DEFAULT (_FRC_STATUS_RXWORD_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_CONVPAUSED (0x1UL << 13) /**< Convolutional coder pause event active */ +#define _FRC_STATUS_CONVPAUSED_SHIFT 13 /**< Shift value for FRC_CONVPAUSED */ +#define _FRC_STATUS_CONVPAUSED_MASK 0x2000UL /**< Bit mask for FRC_CONVPAUSED */ +#define _FRC_STATUS_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_CONVPAUSED_DEFAULT (_FRC_STATUS_CONVPAUSED_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_TXSUBFRAMEPAUSED (0x1UL << 14) /**< Transmit subframe pause event active */ +#define _FRC_STATUS_TXSUBFRAMEPAUSED_SHIFT 14 /**< Shift value for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_STATUS_TXSUBFRAMEPAUSED_MASK 0x4000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT (_FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_INTERLEAVEREADPAUSED (0x1UL << 15) /**< Interleaver read pause event active */ +#define _FRC_STATUS_INTERLEAVEREADPAUSED_SHIFT 15 /**< Shift value for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_STATUS_INTERLEAVEREADPAUSED_MASK 0x8000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT (_FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_INTERLEAVEWRITEPAUSED (0x1UL << 16) /**< Interleaver write pause event active */ +#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_SHIFT 16 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_MASK 0x10000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMEDETPAUSED (0x1UL << 17) /**< Frame detected pause event active */ +#define _FRC_STATUS_FRAMEDETPAUSED_SHIFT 17 /**< Shift value for FRC_FRAMEDETPAUSED */ +#define _FRC_STATUS_FRAMEDETPAUSED_MASK 0x20000UL /**< Bit mask for FRC_FRAMEDETPAUSED */ +#define _FRC_STATUS_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMEDETPAUSED_DEFAULT (_FRC_STATUS_FRAMEDETPAUSED_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMELENGTHERROR (0x1UL << 18) /**< Frame Length Error for RX and TX */ +#define _FRC_STATUS_FRAMELENGTHERROR_SHIFT 18 /**< Shift value for FRC_FRAMELENGTHERROR */ +#define _FRC_STATUS_FRAMELENGTHERROR_MASK 0x40000UL /**< Bit mask for FRC_FRAMELENGTHERROR */ +#define _FRC_STATUS_FRAMELENGTHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FRAMELENGTHERROR_DEFAULT (_FRC_STATUS_FRAMELENGTHERROR_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_DEMODERROR (0x1UL << 19) /**< Demod Error in RX */ +#define _FRC_STATUS_DEMODERROR_SHIFT 19 /**< Shift value for FRC_DEMODERROR */ +#define _FRC_STATUS_DEMODERROR_MASK 0x80000UL /**< Bit mask for FRC_DEMODERROR */ +#define _FRC_STATUS_DEMODERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_DEMODERROR_DEFAULT (_FRC_STATUS_DEMODERROR_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_SHIFT 20 /**< Shift value for FRC_FSMSTATE */ +#define _FRC_STATUS_FSMSTATE_MASK 0x1F00000UL /**< Bit mask for FRC_FSMSTATE */ +#define _FRC_STATUS_FSMSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_IDLE 0x00000000UL /**< Mode IDLE for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_INIT 0x00000001UL /**< Mode RX_INIT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_DATA 0x00000002UL /**< Mode RX_DATA for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_CRC 0x00000003UL /**< Mode RX_CRC for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_FCD_UPDATE 0x00000004UL /**< Mode RX_FCD_UPDATE for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_DISCARD 0x00000005UL /**< Mode RX_DISCARD for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_TRAIL 0x00000006UL /**< Mode RX_TRAIL for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_DONE 0x00000007UL /**< Mode RX_DONE for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_PAUSE_INIT 0x00000008UL /**< Mode RX_PAUSE_INIT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_PAUSED 0x00000009UL /**< Mode RX_PAUSED for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_UNDEFINED1 0x0000000AUL /**< Mode UNDEFINED1 for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_UNDEFINED2 0x0000000BUL /**< Mode UNDEFINED2 for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK 0x0000000CUL /**< Mode RX_CRC_ZEROCHECK for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_SUP 0x0000000DUL /**< Mode RX_SUP for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_RX_WAITEOF 0x0000000EUL /**< Mode RX_WAITEOF for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_UNDEFINED3 0x0000000FUL /**< Mode UNDEFINED3 for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_INIT 0x00000010UL /**< Mode TX_INIT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_DATA 0x00000011UL /**< Mode TX_DATA for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_CRC 0x00000012UL /**< Mode TX_CRC for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_FCD_UPDATE 0x00000013UL /**< Mode TX_FCD_UPDATE for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_TRAIL 0x00000014UL /**< Mode TX_TRAIL for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_FLUSH 0x00000015UL /**< Mode TX_FLUSH for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_DONE 0x00000016UL /**< Mode TX_DONE for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_DONE_WAIT 0x00000017UL /**< Mode TX_DONE_WAIT for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_RAW 0x00000018UL /**< Mode TX_RAW for FRC_STATUS */ +#define _FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH 0x00000019UL /**< Mode TX_PAUSEFLUSH for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_DEFAULT (_FRC_STATUS_FSMSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_IDLE (_FRC_STATUS_FSMSTATE_IDLE << 20) /**< Shifted mode IDLE for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_INIT (_FRC_STATUS_FSMSTATE_RX_INIT << 20) /**< Shifted mode RX_INIT for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_DATA (_FRC_STATUS_FSMSTATE_RX_DATA << 20) /**< Shifted mode RX_DATA for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_CRC (_FRC_STATUS_FSMSTATE_RX_CRC << 20) /**< Shifted mode RX_CRC for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_FCD_UPDATE (_FRC_STATUS_FSMSTATE_RX_FCD_UPDATE << 20) /**< Shifted mode RX_FCD_UPDATE for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_DISCARD (_FRC_STATUS_FSMSTATE_RX_DISCARD << 20) /**< Shifted mode RX_DISCARD for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_TRAIL (_FRC_STATUS_FSMSTATE_RX_TRAIL << 20) /**< Shifted mode RX_TRAIL for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_DONE (_FRC_STATUS_FSMSTATE_RX_DONE << 20) /**< Shifted mode RX_DONE for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_PAUSE_INIT (_FRC_STATUS_FSMSTATE_RX_PAUSE_INIT << 20) /**< Shifted mode RX_PAUSE_INIT for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_PAUSED (_FRC_STATUS_FSMSTATE_RX_PAUSED << 20) /**< Shifted mode RX_PAUSED for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_UNDEFINED1 (_FRC_STATUS_FSMSTATE_UNDEFINED1 << 20) /**< Shifted mode UNDEFINED1 for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_UNDEFINED2 (_FRC_STATUS_FSMSTATE_UNDEFINED2 << 20) /**< Shifted mode UNDEFINED2 for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK (_FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK << 20) /**< Shifted mode RX_CRC_ZEROCHECK for FRC_STATUS*/ +#define FRC_STATUS_FSMSTATE_RX_SUP (_FRC_STATUS_FSMSTATE_RX_SUP << 20) /**< Shifted mode RX_SUP for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_RX_WAITEOF (_FRC_STATUS_FSMSTATE_RX_WAITEOF << 20) /**< Shifted mode RX_WAITEOF for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_UNDEFINED3 (_FRC_STATUS_FSMSTATE_UNDEFINED3 << 20) /**< Shifted mode UNDEFINED3 for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_INIT (_FRC_STATUS_FSMSTATE_TX_INIT << 20) /**< Shifted mode TX_INIT for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_DATA (_FRC_STATUS_FSMSTATE_TX_DATA << 20) /**< Shifted mode TX_DATA for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_CRC (_FRC_STATUS_FSMSTATE_TX_CRC << 20) /**< Shifted mode TX_CRC for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_FCD_UPDATE (_FRC_STATUS_FSMSTATE_TX_FCD_UPDATE << 20) /**< Shifted mode TX_FCD_UPDATE for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_TRAIL (_FRC_STATUS_FSMSTATE_TX_TRAIL << 20) /**< Shifted mode TX_TRAIL for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_FLUSH (_FRC_STATUS_FSMSTATE_TX_FLUSH << 20) /**< Shifted mode TX_FLUSH for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_DONE (_FRC_STATUS_FSMSTATE_TX_DONE << 20) /**< Shifted mode TX_DONE for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_DONE_WAIT (_FRC_STATUS_FSMSTATE_TX_DONE_WAIT << 20) /**< Shifted mode TX_DONE_WAIT for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_RAW (_FRC_STATUS_FSMSTATE_TX_RAW << 20) /**< Shifted mode TX_RAW for FRC_STATUS */ +#define FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH (_FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH << 20) /**< Shifted mode TX_PAUSEFLUSH for FRC_STATUS */ +#define FRC_STATUS_RXWCNTMATCHPAUSED (0x1UL << 25) /**< Nth byte received pause event active */ +#define _FRC_STATUS_RXWCNTMATCHPAUSED_SHIFT 25 /**< Shift value for FRC_RXWCNTMATCHPAUSED */ +#define _FRC_STATUS_RXWCNTMATCHPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_RXWCNTMATCHPAUSED */ +#define _FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT (_FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_CRCERRORTOLERATED (0x1UL << 26) /**< CRC error tolerated */ +#define _FRC_STATUS_CRCERRORTOLERATED_SHIFT 26 /**< Shift value for FRC_CRCERRORTOLERATED */ +#define _FRC_STATUS_CRCERRORTOLERATED_MASK 0x4000000UL /**< Bit mask for FRC_CRCERRORTOLERATED */ +#define _FRC_STATUS_CRCERRORTOLERATED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */ +#define FRC_STATUS_CRCERRORTOLERATED_DEFAULT (_FRC_STATUS_CRCERRORTOLERATED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_STATUS */ + +/* Bit fields for FRC DFLCTRL */ +#define _FRC_DFLCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_MASK 0x01FFFF7FUL /**< Mask for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_SHIFT 0 /**< Shift value for FRC_DFLMODE */ +#define _FRC_DFLCTRL_DFLMODE_MASK 0x7UL /**< Bit mask for FRC_DFLMODE */ +#define _FRC_DFLCTRL_DFLMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_SINGLEBYTE 0x00000001UL /**< Mode SINGLEBYTE for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB 0x00000002UL /**< Mode SINGLEBYTEMSB for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST 0x00000003UL /**< Mode DUALBYTELSBFIRST for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST 0x00000004UL /**< Mode DUALBYTEMSBFIRST for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_INFINITE 0x00000005UL /**< Mode INFINITE for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLMODE_BLOCKERROR 0x00000006UL /**< Mode BLOCKERROR for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_DEFAULT (_FRC_DFLCTRL_DFLMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_DISABLE (_FRC_DFLCTRL_DFLMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_SINGLEBYTE (_FRC_DFLCTRL_DFLMODE_SINGLEBYTE << 0) /**< Shifted mode SINGLEBYTE for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB (_FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB << 0) /**< Shifted mode SINGLEBYTEMSB for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST (_FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST << 0) /**< Shifted mode DUALBYTELSBFIRST for FRC_DFLCTRL*/ +#define FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST (_FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST << 0) /**< Shifted mode DUALBYTEMSBFIRST for FRC_DFLCTRL*/ +#define FRC_DFLCTRL_DFLMODE_INFINITE (_FRC_DFLCTRL_DFLMODE_INFINITE << 0) /**< Shifted mode INFINITE for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLMODE_BLOCKERROR (_FRC_DFLCTRL_DFLMODE_BLOCKERROR << 0) /**< Shifted mode BLOCKERROR for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBITORDER (0x1UL << 3) /**< Dynamic Frame Length Bit order */ +#define _FRC_DFLCTRL_DFLBITORDER_SHIFT 3 /**< Shift value for FRC_DFLBITORDER */ +#define _FRC_DFLCTRL_DFLBITORDER_MASK 0x8UL /**< Bit mask for FRC_DFLBITORDER */ +#define _FRC_DFLCTRL_DFLBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLBITORDER_NORMAL 0x00000000UL /**< Mode NORMAL for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLBITORDER_REVERSE 0x00000001UL /**< Mode REVERSE for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBITORDER_DEFAULT (_FRC_DFLCTRL_DFLBITORDER_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBITORDER_NORMAL (_FRC_DFLCTRL_DFLBITORDER_NORMAL << 3) /**< Shifted mode NORMAL for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBITORDER_REVERSE (_FRC_DFLCTRL_DFLBITORDER_REVERSE << 3) /**< Shifted mode REVERSE for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLSHIFT_SHIFT 4 /**< Shift value for FRC_DFLSHIFT */ +#define _FRC_DFLCTRL_DFLSHIFT_MASK 0x70UL /**< Bit mask for FRC_DFLSHIFT */ +#define _FRC_DFLCTRL_DFLSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLSHIFT_DEFAULT (_FRC_DFLCTRL_DFLSHIFT_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLOFFSET_SHIFT 8 /**< Shift value for FRC_DFLOFFSET */ +#define _FRC_DFLCTRL_DFLOFFSET_MASK 0xF00UL /**< Bit mask for FRC_DFLOFFSET */ +#define _FRC_DFLCTRL_DFLOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLOFFSET_DEFAULT (_FRC_DFLCTRL_DFLOFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLBITS_SHIFT 12 /**< Shift value for FRC_DFLBITS */ +#define _FRC_DFLCTRL_DFLBITS_MASK 0xF000UL /**< Bit mask for FRC_DFLBITS */ +#define _FRC_DFLCTRL_DFLBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBITS_DEFAULT (_FRC_DFLCTRL_DFLBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_MINLENGTH_SHIFT 16 /**< Shift value for FRC_MINLENGTH */ +#define _FRC_DFLCTRL_MINLENGTH_MASK 0xF0000UL /**< Bit mask for FRC_MINLENGTH */ +#define _FRC_DFLCTRL_MINLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_MINLENGTH_DEFAULT (_FRC_DFLCTRL_MINLENGTH_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLINCLUDECRC (0x1UL << 20) /**< Length field includes CRC values or not */ +#define _FRC_DFLCTRL_DFLINCLUDECRC_SHIFT 20 /**< Shift value for FRC_DFLINCLUDECRC */ +#define _FRC_DFLCTRL_DFLINCLUDECRC_MASK 0x100000UL /**< Bit mask for FRC_DFLINCLUDECRC */ +#define _FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLINCLUDECRC_X0 0x00000000UL /**< Mode X0 for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLINCLUDECRC_X1 0x00000001UL /**< Mode X1 for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT (_FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLINCLUDECRC_X0 (_FRC_DFLCTRL_DFLINCLUDECRC_X0 << 20) /**< Shifted mode X0 for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLINCLUDECRC_X1 (_FRC_DFLCTRL_DFLINCLUDECRC_X1 << 20) /**< Shifted mode X1 for FRC_DFLCTRL */ +#define _FRC_DFLCTRL_DFLBOIOFFSET_SHIFT 21 /**< Shift value for FRC_DFLBOIOFFSET */ +#define _FRC_DFLCTRL_DFLBOIOFFSET_MASK 0x1E00000UL /**< Bit mask for FRC_DFLBOIOFFSET */ +#define _FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */ +#define FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT (_FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_DFLCTRL */ + +/* Bit fields for FRC MAXLENGTH */ +#define _FRC_MAXLENGTH_RESETVALUE 0x00004FFFUL /**< Default value for FRC_MAXLENGTH */ +#define _FRC_MAXLENGTH_MASK 0x0000FFFFUL /**< Mask for FRC_MAXLENGTH */ +#define _FRC_MAXLENGTH_MAXLENGTH_SHIFT 0 /**< Shift value for FRC_MAXLENGTH */ +#define _FRC_MAXLENGTH_MAXLENGTH_MASK 0xFFFUL /**< Bit mask for FRC_MAXLENGTH */ +#define _FRC_MAXLENGTH_MAXLENGTH_DEFAULT 0x00000FFFUL /**< Mode DEFAULT for FRC_MAXLENGTH */ +#define FRC_MAXLENGTH_MAXLENGTH_DEFAULT (_FRC_MAXLENGTH_MAXLENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_MAXLENGTH */ +#define _FRC_MAXLENGTH_INILENGTH_SHIFT 12 /**< Shift value for FRC_INILENGTH */ +#define _FRC_MAXLENGTH_INILENGTH_MASK 0xF000UL /**< Bit mask for FRC_INILENGTH */ +#define _FRC_MAXLENGTH_INILENGTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for FRC_MAXLENGTH */ +#define FRC_MAXLENGTH_INILENGTH_DEFAULT (_FRC_MAXLENGTH_INILENGTH_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_MAXLENGTH */ + +/* Bit fields for FRC ADDRFILTCTRL */ +#define _FRC_ADDRFILTCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_ADDRFILTCTRL */ +#define _FRC_ADDRFILTCTRL_MASK 0x0000FF07UL /**< Mask for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_EN (0x1UL << 0) /**< Address Filter Enable */ +#define _FRC_ADDRFILTCTRL_EN_SHIFT 0 /**< Shift value for FRC_EN */ +#define _FRC_ADDRFILTCTRL_EN_MASK 0x1UL /**< Bit mask for FRC_EN */ +#define _FRC_ADDRFILTCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_EN_DEFAULT (_FRC_ADDRFILTCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_BRDCST00EN (0x1UL << 1) /**< Broadcast Address 0x00 Enable */ +#define _FRC_ADDRFILTCTRL_BRDCST00EN_SHIFT 1 /**< Shift value for FRC_BRDCST00EN */ +#define _FRC_ADDRFILTCTRL_BRDCST00EN_MASK 0x2UL /**< Bit mask for FRC_BRDCST00EN */ +#define _FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT (_FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_BRDCSTFFEN (0x1UL << 2) /**< Broadcast Address 0xFF Enable */ +#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_SHIFT 2 /**< Shift value for FRC_BRDCSTFFEN */ +#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_MASK 0x4UL /**< Bit mask for FRC_BRDCSTFFEN */ +#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT (_FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */ +#define _FRC_ADDRFILTCTRL_ADDRESS_SHIFT 8 /**< Shift value for FRC_ADDRESS */ +#define _FRC_ADDRFILTCTRL_ADDRESS_MASK 0xFF00UL /**< Bit mask for FRC_ADDRESS */ +#define _FRC_ADDRFILTCTRL_ADDRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */ +#define FRC_ADDRFILTCTRL_ADDRESS_DEFAULT (_FRC_ADDRFILTCTRL_ADDRESS_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */ + +/* Bit fields for FRC DATABUFFER */ +#define _FRC_DATABUFFER_RESETVALUE 0x00000000UL /**< Default value for FRC_DATABUFFER */ +#define _FRC_DATABUFFER_MASK 0x000000FFUL /**< Mask for FRC_DATABUFFER */ +#define _FRC_DATABUFFER_DATABUFFER_SHIFT 0 /**< Shift value for FRC_DATABUFFER */ +#define _FRC_DATABUFFER_DATABUFFER_MASK 0xFFUL /**< Bit mask for FRC_DATABUFFER */ +#define _FRC_DATABUFFER_DATABUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DATABUFFER */ +#define FRC_DATABUFFER_DATABUFFER_DEFAULT (_FRC_DATABUFFER_DATABUFFER_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DATABUFFER */ + +/* Bit fields for FRC WCNT */ +#define _FRC_WCNT_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNT */ +#define _FRC_WCNT_MASK 0x00000FFFUL /**< Mask for FRC_WCNT */ +#define _FRC_WCNT_WCNT_SHIFT 0 /**< Shift value for FRC_WCNT */ +#define _FRC_WCNT_WCNT_MASK 0xFFFUL /**< Bit mask for FRC_WCNT */ +#define _FRC_WCNT_WCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNT */ +#define FRC_WCNT_WCNT_DEFAULT (_FRC_WCNT_WCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNT */ + +/* Bit fields for FRC WCNTCMP0 */ +#define _FRC_WCNTCMP0_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP0 */ +#define _FRC_WCNTCMP0_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP0 */ +#define _FRC_WCNTCMP0_FRAMELENGTH_SHIFT 0 /**< Shift value for FRC_FRAMELENGTH */ +#define _FRC_WCNTCMP0_FRAMELENGTH_MASK 0xFFFUL /**< Bit mask for FRC_FRAMELENGTH */ +#define _FRC_WCNTCMP0_FRAMELENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP0 */ +#define FRC_WCNTCMP0_FRAMELENGTH_DEFAULT (_FRC_WCNTCMP0_FRAMELENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP0 */ + +/* Bit fields for FRC WCNTCMP1 */ +#define _FRC_WCNTCMP1_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP1 */ +#define _FRC_WCNTCMP1_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP1 */ +#define _FRC_WCNTCMP1_LENGTHFIELDLOC_SHIFT 0 /**< Shift value for FRC_LENGTHFIELDLOC */ +#define _FRC_WCNTCMP1_LENGTHFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_LENGTHFIELDLOC */ +#define _FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP1 */ +#define FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT (_FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP1 */ + +/* Bit fields for FRC WCNTCMP2 */ +#define _FRC_WCNTCMP2_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP2 */ +#define _FRC_WCNTCMP2_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP2 */ +#define _FRC_WCNTCMP2_ADDRFIELDLOC_SHIFT 0 /**< Shift value for FRC_ADDRFIELDLOC */ +#define _FRC_WCNTCMP2_ADDRFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_ADDRFIELDLOC */ +#define _FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP2 */ +#define FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT (_FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP2 */ + +/* Bit fields for FRC CMD */ +#define _FRC_CMD_RESETVALUE 0x00000000UL /**< Default value for FRC_CMD */ +#define _FRC_CMD_MASK 0x00003FFFUL /**< Mask for FRC_CMD */ +#define FRC_CMD_RXABORT (0x1UL << 0) /**< RX Abort */ +#define _FRC_CMD_RXABORT_SHIFT 0 /**< Shift value for FRC_RXABORT */ +#define _FRC_CMD_RXABORT_MASK 0x1UL /**< Bit mask for FRC_RXABORT */ +#define _FRC_CMD_RXABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_RXABORT_DEFAULT (_FRC_CMD_RXABORT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_FRAMEDETRESUME (0x1UL << 1) /**< FRAMEDET resume */ +#define _FRC_CMD_FRAMEDETRESUME_SHIFT 1 /**< Shift value for FRC_FRAMEDETRESUME */ +#define _FRC_CMD_FRAMEDETRESUME_MASK 0x2UL /**< Bit mask for FRC_FRAMEDETRESUME */ +#define _FRC_CMD_FRAMEDETRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_FRAMEDETRESUME_DEFAULT (_FRC_CMD_FRAMEDETRESUME_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEWRITERESUME (0x1UL << 2) /**< Interleaver write resume */ +#define _FRC_CMD_INTERLEAVEWRITERESUME_SHIFT 2 /**< Shift value for FRC_INTERLEAVEWRITERESUME */ +#define _FRC_CMD_INTERLEAVEWRITERESUME_MASK 0x4UL /**< Bit mask for FRC_INTERLEAVEWRITERESUME */ +#define _FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT (_FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEREADRESUME (0x1UL << 3) /**< Interleaver read resume */ +#define _FRC_CMD_INTERLEAVEREADRESUME_SHIFT 3 /**< Shift value for FRC_INTERLEAVEREADRESUME */ +#define _FRC_CMD_INTERLEAVEREADRESUME_MASK 0x8UL /**< Bit mask for FRC_INTERLEAVEREADRESUME */ +#define _FRC_CMD_INTERLEAVEREADRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEREADRESUME_DEFAULT (_FRC_CMD_INTERLEAVEREADRESUME_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVRESUME (0x1UL << 4) /**< Convolutional coder resume */ +#define _FRC_CMD_CONVRESUME_SHIFT 4 /**< Shift value for FRC_CONVRESUME */ +#define _FRC_CMD_CONVRESUME_MASK 0x10UL /**< Bit mask for FRC_CONVRESUME */ +#define _FRC_CMD_CONVRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVRESUME_DEFAULT (_FRC_CMD_CONVRESUME_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVTERMINATE (0x1UL << 5) /**< Convolutional coder termination */ +#define _FRC_CMD_CONVTERMINATE_SHIFT 5 /**< Shift value for FRC_CONVTERMINATE */ +#define _FRC_CMD_CONVTERMINATE_MASK 0x20UL /**< Bit mask for FRC_CONVTERMINATE */ +#define _FRC_CMD_CONVTERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVTERMINATE_DEFAULT (_FRC_CMD_CONVTERMINATE_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_TXSUBFRAMERESUME (0x1UL << 6) /**< TX subframe resume */ +#define _FRC_CMD_TXSUBFRAMERESUME_SHIFT 6 /**< Shift value for FRC_TXSUBFRAMERESUME */ +#define _FRC_CMD_TXSUBFRAMERESUME_MASK 0x40UL /**< Bit mask for FRC_TXSUBFRAMERESUME */ +#define _FRC_CMD_TXSUBFRAMERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_TXSUBFRAMERESUME_DEFAULT (_FRC_CMD_TXSUBFRAMERESUME_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEINIT (0x1UL << 7) /**< Interleaver initialization */ +#define _FRC_CMD_INTERLEAVEINIT_SHIFT 7 /**< Shift value for FRC_INTERLEAVEINIT */ +#define _FRC_CMD_INTERLEAVEINIT_MASK 0x80UL /**< Bit mask for FRC_INTERLEAVEINIT */ +#define _FRC_CMD_INTERLEAVEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVEINIT_DEFAULT (_FRC_CMD_INTERLEAVEINIT_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVECNTCLEAR (0x1UL << 8) /**< Interleaver counter clear */ +#define _FRC_CMD_INTERLEAVECNTCLEAR_SHIFT 8 /**< Shift value for FRC_INTERLEAVECNTCLEAR */ +#define _FRC_CMD_INTERLEAVECNTCLEAR_MASK 0x100UL /**< Bit mask for FRC_INTERLEAVECNTCLEAR */ +#define _FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT (_FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVINIT (0x1UL << 9) /**< Convolutional coder initialize */ +#define _FRC_CMD_CONVINIT_SHIFT 9 /**< Shift value for FRC_CONVINIT */ +#define _FRC_CMD_CONVINIT_MASK 0x200UL /**< Bit mask for FRC_CONVINIT */ +#define _FRC_CMD_CONVINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_CONVINIT_DEFAULT (_FRC_CMD_CONVINIT_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_BLOCKINIT (0x1UL << 10) /**< Block coder initialize */ +#define _FRC_CMD_BLOCKINIT_SHIFT 10 /**< Shift value for FRC_BLOCKINIT */ +#define _FRC_CMD_BLOCKINIT_MASK 0x400UL /**< Bit mask for FRC_BLOCKINIT */ +#define _FRC_CMD_BLOCKINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_BLOCKINIT_DEFAULT (_FRC_CMD_BLOCKINIT_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_STATEINIT (0x1UL << 11) /**< FRC State initialize */ +#define _FRC_CMD_STATEINIT_SHIFT 11 /**< Shift value for FRC_STATEINIT */ +#define _FRC_CMD_STATEINIT_MASK 0x800UL /**< Bit mask for FRC_STATEINIT */ +#define _FRC_CMD_STATEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_STATEINIT_DEFAULT (_FRC_CMD_STATEINIT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_RXRAWUNBLOCK (0x1UL << 12) /**< Clear RXRAWBLOCKED status flag */ +#define _FRC_CMD_RXRAWUNBLOCK_SHIFT 12 /**< Shift value for FRC_RXRAWUNBLOCK */ +#define _FRC_CMD_RXRAWUNBLOCK_MASK 0x1000UL /**< Bit mask for FRC_RXRAWUNBLOCK */ +#define _FRC_CMD_RXRAWUNBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_RXRAWUNBLOCK_DEFAULT (_FRC_CMD_RXRAWUNBLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_CMD */ +#define FRC_CMD_RXPAUSERESUME (0x1UL << 13) /**< RX pause on nth byte resume */ +#define _FRC_CMD_RXPAUSERESUME_SHIFT 13 /**< Shift value for FRC_RXPAUSERESUME */ +#define _FRC_CMD_RXPAUSERESUME_MASK 0x2000UL /**< Bit mask for FRC_RXPAUSERESUME */ +#define _FRC_CMD_RXPAUSERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */ +#define FRC_CMD_RXPAUSERESUME_DEFAULT (_FRC_CMD_RXPAUSERESUME_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_CMD */ + +/* Bit fields for FRC WHITECTRL */ +#define _FRC_WHITECTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_MASK 0x00001F7FUL /**< Mask for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_SHIFT 0 /**< Shift value for FRC_FEEDBACKSEL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_MASK 0x1FUL /**< Bit mask for FRC_FEEDBACKSEL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT0 0x00000000UL /**< Mode BIT0 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT1 0x00000001UL /**< Mode BIT1 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT2 0x00000002UL /**< Mode BIT2 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT3 0x00000003UL /**< Mode BIT3 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT4 0x00000004UL /**< Mode BIT4 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT5 0x00000005UL /**< Mode BIT5 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT6 0x00000006UL /**< Mode BIT6 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT7 0x00000007UL /**< Mode BIT7 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT8 0x00000008UL /**< Mode BIT8 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT9 0x00000009UL /**< Mode BIT9 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT10 0x0000000AUL /**< Mode BIT10 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT11 0x0000000BUL /**< Mode BIT11 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT12 0x0000000CUL /**< Mode BIT12 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT13 0x0000000DUL /**< Mode BIT13 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT14 0x0000000EUL /**< Mode BIT14 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_BIT15 0x0000000FUL /**< Mode BIT15 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_INPUT 0x00000010UL /**< Mode INPUT for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_ZERO 0x00000011UL /**< Mode ZERO for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_ONE 0x00000012UL /**< Mode ONE for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD 0x00000013UL /**< Mode TXLASTWORD for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_DEFAULT (_FRC_WHITECTRL_FEEDBACKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT0 (_FRC_WHITECTRL_FEEDBACKSEL_BIT0 << 0) /**< Shifted mode BIT0 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT1 (_FRC_WHITECTRL_FEEDBACKSEL_BIT1 << 0) /**< Shifted mode BIT1 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT2 (_FRC_WHITECTRL_FEEDBACKSEL_BIT2 << 0) /**< Shifted mode BIT2 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT3 (_FRC_WHITECTRL_FEEDBACKSEL_BIT3 << 0) /**< Shifted mode BIT3 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT4 (_FRC_WHITECTRL_FEEDBACKSEL_BIT4 << 0) /**< Shifted mode BIT4 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT5 (_FRC_WHITECTRL_FEEDBACKSEL_BIT5 << 0) /**< Shifted mode BIT5 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT6 (_FRC_WHITECTRL_FEEDBACKSEL_BIT6 << 0) /**< Shifted mode BIT6 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT7 (_FRC_WHITECTRL_FEEDBACKSEL_BIT7 << 0) /**< Shifted mode BIT7 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT8 (_FRC_WHITECTRL_FEEDBACKSEL_BIT8 << 0) /**< Shifted mode BIT8 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT9 (_FRC_WHITECTRL_FEEDBACKSEL_BIT9 << 0) /**< Shifted mode BIT9 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT10 (_FRC_WHITECTRL_FEEDBACKSEL_BIT10 << 0) /**< Shifted mode BIT10 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT11 (_FRC_WHITECTRL_FEEDBACKSEL_BIT11 << 0) /**< Shifted mode BIT11 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT12 (_FRC_WHITECTRL_FEEDBACKSEL_BIT12 << 0) /**< Shifted mode BIT12 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT13 (_FRC_WHITECTRL_FEEDBACKSEL_BIT13 << 0) /**< Shifted mode BIT13 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT14 (_FRC_WHITECTRL_FEEDBACKSEL_BIT14 << 0) /**< Shifted mode BIT14 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_BIT15 (_FRC_WHITECTRL_FEEDBACKSEL_BIT15 << 0) /**< Shifted mode BIT15 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_INPUT (_FRC_WHITECTRL_FEEDBACKSEL_INPUT << 0) /**< Shifted mode INPUT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_ZERO (_FRC_WHITECTRL_FEEDBACKSEL_ZERO << 0) /**< Shifted mode ZERO for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_ONE (_FRC_WHITECTRL_FEEDBACKSEL_ONE << 0) /**< Shifted mode ONE for FRC_WHITECTRL */ +#define FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD (_FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD << 0) /**< Shifted mode TXLASTWORD for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_XORFEEDBACK_SHIFT 5 /**< Shift value for FRC_XORFEEDBACK */ +#define _FRC_WHITECTRL_XORFEEDBACK_MASK 0x60UL /**< Bit mask for FRC_XORFEEDBACK */ +#define _FRC_WHITECTRL_XORFEEDBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_XORFEEDBACK_DIRECT 0x00000000UL /**< Mode DIRECT for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_XORFEEDBACK_XOR 0x00000001UL /**< Mode XOR for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_XORFEEDBACK_ZERO 0x00000002UL /**< Mode ZERO for FRC_WHITECTRL */ +#define FRC_WHITECTRL_XORFEEDBACK_DEFAULT (_FRC_WHITECTRL_XORFEEDBACK_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_XORFEEDBACK_DIRECT (_FRC_WHITECTRL_XORFEEDBACK_DIRECT << 5) /**< Shifted mode DIRECT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_XORFEEDBACK_XOR (_FRC_WHITECTRL_XORFEEDBACK_XOR << 5) /**< Shifted mode XOR for FRC_WHITECTRL */ +#define FRC_WHITECTRL_XORFEEDBACK_ZERO (_FRC_WHITECTRL_XORFEEDBACK_ZERO << 5) /**< Shifted mode ZERO for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_SHROUTPUTSEL_SHIFT 8 /**< Shift value for FRC_SHROUTPUTSEL */ +#define _FRC_WHITECTRL_SHROUTPUTSEL_MASK 0xF00UL /**< Bit mask for FRC_SHROUTPUTSEL */ +#define _FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT (_FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_BLOCKERRORCORRECT (0x1UL << 12) /**< Block Errors Correction enable */ +#define _FRC_WHITECTRL_BLOCKERRORCORRECT_SHIFT 12 /**< Shift value for FRC_BLOCKERRORCORRECT */ +#define _FRC_WHITECTRL_BLOCKERRORCORRECT_MASK 0x1000UL /**< Bit mask for FRC_BLOCKERRORCORRECT */ +#define _FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_BLOCKERRORCORRECT_X0 0x00000000UL /**< Mode X0 for FRC_WHITECTRL */ +#define _FRC_WHITECTRL_BLOCKERRORCORRECT_X1 0x00000001UL /**< Mode X1 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT (_FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_WHITECTRL */ +#define FRC_WHITECTRL_BLOCKERRORCORRECT_X0 (_FRC_WHITECTRL_BLOCKERRORCORRECT_X0 << 12) /**< Shifted mode X0 for FRC_WHITECTRL */ +#define FRC_WHITECTRL_BLOCKERRORCORRECT_X1 (_FRC_WHITECTRL_BLOCKERRORCORRECT_X1 << 12) /**< Shifted mode X1 for FRC_WHITECTRL */ + +/* Bit fields for FRC WHITEPOLY */ +#define _FRC_WHITEPOLY_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITEPOLY */ +#define _FRC_WHITEPOLY_MASK 0x0000FFFFUL /**< Mask for FRC_WHITEPOLY */ +#define _FRC_WHITEPOLY_POLY_SHIFT 0 /**< Shift value for FRC_POLY */ +#define _FRC_WHITEPOLY_POLY_MASK 0xFFFFUL /**< Bit mask for FRC_POLY */ +#define _FRC_WHITEPOLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITEPOLY */ +#define FRC_WHITEPOLY_POLY_DEFAULT (_FRC_WHITEPOLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITEPOLY */ + +/* Bit fields for FRC WHITEINIT */ +#define _FRC_WHITEINIT_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITEINIT */ +#define _FRC_WHITEINIT_MASK 0x0000FFFFUL /**< Mask for FRC_WHITEINIT */ +#define _FRC_WHITEINIT_WHITEINIT_SHIFT 0 /**< Shift value for FRC_WHITEINIT */ +#define _FRC_WHITEINIT_WHITEINIT_MASK 0xFFFFUL /**< Bit mask for FRC_WHITEINIT */ +#define _FRC_WHITEINIT_WHITEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITEINIT */ +#define FRC_WHITEINIT_WHITEINIT_DEFAULT (_FRC_WHITEINIT_WHITEINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITEINIT */ + +/* Bit fields for FRC FECCTRL */ +#define _FRC_FECCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_FECCTRL */ +#define _FRC_FECCTRL_MASK 0x003FFFF7UL /**< Mask for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_SHIFT 0 /**< Shift value for FRC_BLOCKWHITEMODE */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_MASK 0x7UL /**< Bit mask for FRC_BLOCKWHITEMODE */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_DIRECT 0x00000000UL /**< Mode DIRECT for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_WHITE 0x00000001UL /**< Mode WHITE for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE 0x00000002UL /**< Mode BYTEWHITE for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 0x00000003UL /**< Mode INTERLEAVEDWHITE0 for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 0x00000004UL /**< Mode INTERLEAVEDWHITE1 for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT 0x00000005UL /**< Mode BLOCKCODEINSERT for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE 0x00000006UL /**< Mode BLOCKCODEREPLACE for FRC_FECCTRL */ +#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP 0x00000007UL /**< Mode BLOCKLOOKUP for FRC_FECCTRL */ +#define FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT (_FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_BLOCKWHITEMODE_DIRECT (_FRC_FECCTRL_BLOCKWHITEMODE_DIRECT << 0) /**< Shifted mode DIRECT for FRC_FECCTRL */ +#define FRC_FECCTRL_BLOCKWHITEMODE_WHITE (_FRC_FECCTRL_BLOCKWHITEMODE_WHITE << 0) /**< Shifted mode WHITE for FRC_FECCTRL */ +#define FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE (_FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE << 0) /**< Shifted mode BYTEWHITE for FRC_FECCTRL */ +#define FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 (_FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 << 0) /**< Shifted mode INTERLEAVEDWHITE0 for FRC_FECCTRL*/ +#define FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 (_FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 << 0) /**< Shifted mode INTERLEAVEDWHITE1 for FRC_FECCTRL*/ +#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT << 0) /**< Shifted mode BLOCKCODEINSERT for FRC_FECCTRL*/ +#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE << 0) /**< Shifted mode BLOCKCODEREPLACE for FRC_FECCTRL*/ +#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP << 0) /**< Shifted mode BLOCKLOOKUP for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVMODE_SHIFT 4 /**< Shift value for FRC_CONVMODE */ +#define _FRC_FECCTRL_CONVMODE_MASK 0x30UL /**< Bit mask for FRC_CONVMODE */ +#define _FRC_FECCTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVMODE_CONVOLUTIONAL 0x00000001UL /**< Mode CONVOLUTIONAL for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVMODE_REPEAT 0x00000002UL /**< Mode REPEAT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVMODE_DEFAULT (_FRC_FECCTRL_CONVMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVMODE_DISABLE (_FRC_FECCTRL_CONVMODE_DISABLE << 4) /**< Shifted mode DISABLE for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVMODE_CONVOLUTIONAL (_FRC_FECCTRL_CONVMODE_CONVOLUTIONAL << 4) /**< Shifted mode CONVOLUTIONAL for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVMODE_REPEAT (_FRC_FECCTRL_CONVMODE_REPEAT << 4) /**< Shifted mode REPEAT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVDECODEMODE (0x1UL << 6) /**< Convolutional decoding mode setting. */ +#define _FRC_FECCTRL_CONVDECODEMODE_SHIFT 6 /**< Shift value for FRC_CONVDECODEMODE */ +#define _FRC_FECCTRL_CONVDECODEMODE_MASK 0x40UL /**< Bit mask for FRC_CONVDECODEMODE */ +#define _FRC_FECCTRL_CONVDECODEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVDECODEMODE_SOFT 0x00000000UL /**< Mode SOFT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVDECODEMODE_HARD 0x00000001UL /**< Mode HARD for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVDECODEMODE_DEFAULT (_FRC_FECCTRL_CONVDECODEMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVDECODEMODE_SOFT (_FRC_FECCTRL_CONVDECODEMODE_SOFT << 6) /**< Shifted mode SOFT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVDECODEMODE_HARD (_FRC_FECCTRL_CONVDECODEMODE_HARD << 6) /**< Shifted mode HARD for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVTRACEBACKDISABLE (0x1UL << 7) /**< Convolutional traceback disabling */ +#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_SHIFT 7 /**< Shift value for FRC_CONVTRACEBACKDISABLE */ +#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_MASK 0x80UL /**< Bit mask for FRC_CONVTRACEBACKDISABLE */ +#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT (_FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 (_FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 << 7) /**< Shifted mode X0 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 (_FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 << 7) /**< Shifted mode X1 for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVINV_SHIFT 8 /**< Shift value for FRC_CONVINV */ +#define _FRC_FECCTRL_CONVINV_MASK 0x300UL /**< Bit mask for FRC_CONVINV */ +#define _FRC_FECCTRL_CONVINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVINV_DEFAULT (_FRC_FECCTRL_CONVINV_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEMODE_SHIFT 10 /**< Shift value for FRC_INTERLEAVEMODE */ +#define _FRC_FECCTRL_INTERLEAVEMODE_MASK 0xC00UL /**< Bit mask for FRC_INTERLEAVEMODE */ +#define _FRC_FECCTRL_INTERLEAVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEMODE_ENABLE 0x00000001UL /**< Mode ENABLE for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER 0x00000002UL /**< Mode RXBUFFER for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER 0x00000003UL /**< Mode RXTXBUFFER for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEMODE_DEFAULT (_FRC_FECCTRL_INTERLEAVEMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEMODE_DISABLE (_FRC_FECCTRL_INTERLEAVEMODE_DISABLE << 10) /**< Shifted mode DISABLE for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEMODE_ENABLE (_FRC_FECCTRL_INTERLEAVEMODE_ENABLE << 10) /**< Shifted mode ENABLE for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER (_FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER << 10) /**< Shifted mode RXBUFFER for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER (_FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER << 10) /**< Shifted mode RXTXBUFFER for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_SHIFT 12 /**< Shift value for FRC_INTERLEAVEFIRSTINDEX */ +#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_MASK 0xF000UL /**< Bit mask for FRC_INTERLEAVEFIRSTINDEX */ +#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT (_FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEWIDTH (0x1UL << 16) /**< Interleave symbol width. */ +#define _FRC_FECCTRL_INTERLEAVEWIDTH_SHIFT 16 /**< Shift value for FRC_INTERLEAVEWIDTH */ +#define _FRC_FECCTRL_INTERLEAVEWIDTH_MASK 0x10000UL /**< Bit mask for FRC_INTERLEAVEWIDTH */ +#define _FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEWIDTH_ONE 0x00000000UL /**< Mode ONE for FRC_FECCTRL */ +#define _FRC_FECCTRL_INTERLEAVEWIDTH_TWO 0x00000001UL /**< Mode TWO for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT (_FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEWIDTH_ONE (_FRC_FECCTRL_INTERLEAVEWIDTH_ONE << 16) /**< Shifted mode ONE for FRC_FECCTRL */ +#define FRC_FECCTRL_INTERLEAVEWIDTH_TWO (_FRC_FECCTRL_INTERLEAVEWIDTH_TWO << 16) /**< Shifted mode TWO for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVBUSLOCK (0x1UL << 17) /**< Convolutional decoding bus lock */ +#define _FRC_FECCTRL_CONVBUSLOCK_SHIFT 17 /**< Shift value for FRC_CONVBUSLOCK */ +#define _FRC_FECCTRL_CONVBUSLOCK_MASK 0x20000UL /**< Bit mask for FRC_CONVBUSLOCK */ +#define _FRC_FECCTRL_CONVBUSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVBUSLOCK_DEFAULT (_FRC_FECCTRL_CONVBUSLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVSUBFRAMETERMINATE (0x1UL << 18) /**< Enable trellis termination for subframes */ +#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_SHIFT 18 /**< Shift value for FRC_CONVSUBFRAMETERMINATE */ +#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_MASK 0x40000UL /**< Bit mask for FRC_CONVSUBFRAMETERMINATE */ +#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 << 18) /**< Shifted mode X0 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 << 18) /**< Shifted mode X1 for FRC_FECCTRL */ +#define FRC_FECCTRL_SINGLEBLOCK (0x1UL << 19) /**< Single block code per frame */ +#define _FRC_FECCTRL_SINGLEBLOCK_SHIFT 19 /**< Shift value for FRC_SINGLEBLOCK */ +#define _FRC_FECCTRL_SINGLEBLOCK_MASK 0x80000UL /**< Bit mask for FRC_SINGLEBLOCK */ +#define _FRC_FECCTRL_SINGLEBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_SINGLEBLOCK_DEFAULT (_FRC_FECCTRL_SINGLEBLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_FORCE2FSK (0x1UL << 20) /**< Force use of 2-FSK */ +#define _FRC_FECCTRL_FORCE2FSK_SHIFT 20 /**< Shift value for FRC_FORCE2FSK */ +#define _FRC_FECCTRL_FORCE2FSK_MASK 0x100000UL /**< Bit mask for FRC_FORCE2FSK */ +#define _FRC_FECCTRL_FORCE2FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_FORCE2FSK_DEFAULT (_FRC_FECCTRL_FORCE2FSK_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVHARDERROR (0x1UL << 21) /**< Enable convolutional decoding hard error */ +#define _FRC_FECCTRL_CONVHARDERROR_SHIFT 21 /**< Shift value for FRC_CONVHARDERROR */ +#define _FRC_FECCTRL_CONVHARDERROR_MASK 0x200000UL /**< Bit mask for FRC_CONVHARDERROR */ +#define _FRC_FECCTRL_CONVHARDERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVHARDERROR_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */ +#define _FRC_FECCTRL_CONVHARDERROR_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVHARDERROR_DEFAULT (_FRC_FECCTRL_CONVHARDERROR_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVHARDERROR_X0 (_FRC_FECCTRL_CONVHARDERROR_X0 << 21) /**< Shifted mode X0 for FRC_FECCTRL */ +#define FRC_FECCTRL_CONVHARDERROR_X1 (_FRC_FECCTRL_CONVHARDERROR_X1 << 21) /**< Shifted mode X1 for FRC_FECCTRL */ + +/* Bit fields for FRC BLOCKRAMADDR */ +#define _FRC_BLOCKRAMADDR_RESETVALUE 0x00004000UL /**< Default value for FRC_BLOCKRAMADDR */ +#define _FRC_BLOCKRAMADDR_MASK 0xFFFFFFFCUL /**< Mask for FRC_BLOCKRAMADDR */ +#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_SHIFT 2 /**< Shift value for FRC_BLOCKRAMADDR */ +#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_MASK 0xFFFFFFFCUL /**< Bit mask for FRC_BLOCKRAMADDR */ +#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT 0x00001000UL /**< Mode DEFAULT for FRC_BLOCKRAMADDR */ +#define FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT (_FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_BLOCKRAMADDR */ + +/* Bit fields for FRC CONVRAMADDR */ +#define _FRC_CONVRAMADDR_RESETVALUE 0x00004000UL /**< Default value for FRC_CONVRAMADDR */ +#define _FRC_CONVRAMADDR_MASK 0xFFFFFFFCUL /**< Mask for FRC_CONVRAMADDR */ +#define _FRC_CONVRAMADDR_CONVRAMADDR_SHIFT 2 /**< Shift value for FRC_CONVRAMADDR */ +#define _FRC_CONVRAMADDR_CONVRAMADDR_MASK 0xFFFFFFFCUL /**< Bit mask for FRC_CONVRAMADDR */ +#define _FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT 0x00001000UL /**< Mode DEFAULT for FRC_CONVRAMADDR */ +#define FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT (_FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CONVRAMADDR */ + +/* Bit fields for FRC CTRL */ +#define _FRC_CTRL_RESETVALUE 0x03000700UL /**< Default value for FRC_CTRL */ +#define _FRC_CTRL_MASK 0x071F7FF7UL /**< Mask for FRC_CTRL */ +#define FRC_CTRL_RANDOMTX (0x1UL << 0) /**< Random TX Mode */ +#define _FRC_CTRL_RANDOMTX_SHIFT 0 /**< Shift value for FRC_RANDOMTX */ +#define _FRC_CTRL_RANDOMTX_MASK 0x1UL /**< Bit mask for FRC_RANDOMTX */ +#define _FRC_CTRL_RANDOMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_RANDOMTX_DEFAULT (_FRC_CTRL_RANDOMTX_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_UARTMODE (0x1UL << 1) /**< Data Uart Mode */ +#define _FRC_CTRL_UARTMODE_SHIFT 1 /**< Shift value for FRC_UARTMODE */ +#define _FRC_CTRL_UARTMODE_MASK 0x2UL /**< Bit mask for FRC_UARTMODE */ +#define _FRC_CTRL_UARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_UARTMODE_DEFAULT (_FRC_CTRL_UARTMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_BITORDER (0x1UL << 2) /**< Data Bit Order. */ +#define _FRC_CTRL_BITORDER_SHIFT 2 /**< Shift value for FRC_BITORDER */ +#define _FRC_CTRL_BITORDER_MASK 0x4UL /**< Bit mask for FRC_BITORDER */ +#define _FRC_CTRL_BITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_BITORDER_LSBFIRST 0x00000000UL /**< Mode LSBFIRST for FRC_CTRL */ +#define _FRC_CTRL_BITORDER_MSBFIRST 0x00000001UL /**< Mode MSBFIRST for FRC_CTRL */ +#define FRC_CTRL_BITORDER_DEFAULT (_FRC_CTRL_BITORDER_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_BITORDER_LSBFIRST (_FRC_CTRL_BITORDER_LSBFIRST << 2) /**< Shifted mode LSBFIRST for FRC_CTRL */ +#define FRC_CTRL_BITORDER_MSBFIRST (_FRC_CTRL_BITORDER_MSBFIRST << 2) /**< Shifted mode MSBFIRST for FRC_CTRL */ +#define _FRC_CTRL_TXFCDMODE_SHIFT 4 /**< Shift value for FRC_TXFCDMODE */ +#define _FRC_CTRL_TXFCDMODE_MASK 0x30UL /**< Bit mask for FRC_TXFCDMODE */ +#define _FRC_CTRL_TXFCDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_TXFCDMODE_FCDMODE0 0x00000000UL /**< Mode FCDMODE0 for FRC_CTRL */ +#define _FRC_CTRL_TXFCDMODE_FCDMODE1 0x00000001UL /**< Mode FCDMODE1 for FRC_CTRL */ +#define _FRC_CTRL_TXFCDMODE_FCDMODE2 0x00000002UL /**< Mode FCDMODE2 for FRC_CTRL */ +#define _FRC_CTRL_TXFCDMODE_FCDMODE3 0x00000003UL /**< Mode FCDMODE3 for FRC_CTRL */ +#define FRC_CTRL_TXFCDMODE_DEFAULT (_FRC_CTRL_TXFCDMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_TXFCDMODE_FCDMODE0 (_FRC_CTRL_TXFCDMODE_FCDMODE0 << 4) /**< Shifted mode FCDMODE0 for FRC_CTRL */ +#define FRC_CTRL_TXFCDMODE_FCDMODE1 (_FRC_CTRL_TXFCDMODE_FCDMODE1 << 4) /**< Shifted mode FCDMODE1 for FRC_CTRL */ +#define FRC_CTRL_TXFCDMODE_FCDMODE2 (_FRC_CTRL_TXFCDMODE_FCDMODE2 << 4) /**< Shifted mode FCDMODE2 for FRC_CTRL */ +#define FRC_CTRL_TXFCDMODE_FCDMODE3 (_FRC_CTRL_TXFCDMODE_FCDMODE3 << 4) /**< Shifted mode FCDMODE3 for FRC_CTRL */ +#define _FRC_CTRL_RXFCDMODE_SHIFT 6 /**< Shift value for FRC_RXFCDMODE */ +#define _FRC_CTRL_RXFCDMODE_MASK 0xC0UL /**< Bit mask for FRC_RXFCDMODE */ +#define _FRC_CTRL_RXFCDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_RXFCDMODE_FCDMODE0 0x00000000UL /**< Mode FCDMODE0 for FRC_CTRL */ +#define _FRC_CTRL_RXFCDMODE_FCDMODE1 0x00000001UL /**< Mode FCDMODE1 for FRC_CTRL */ +#define _FRC_CTRL_RXFCDMODE_FCDMODE2 0x00000002UL /**< Mode FCDMODE2 for FRC_CTRL */ +#define _FRC_CTRL_RXFCDMODE_FCDMODE3 0x00000003UL /**< Mode FCDMODE3 for FRC_CTRL */ +#define FRC_CTRL_RXFCDMODE_DEFAULT (_FRC_CTRL_RXFCDMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_RXFCDMODE_FCDMODE0 (_FRC_CTRL_RXFCDMODE_FCDMODE0 << 6) /**< Shifted mode FCDMODE0 for FRC_CTRL */ +#define FRC_CTRL_RXFCDMODE_FCDMODE1 (_FRC_CTRL_RXFCDMODE_FCDMODE1 << 6) /**< Shifted mode FCDMODE1 for FRC_CTRL */ +#define FRC_CTRL_RXFCDMODE_FCDMODE2 (_FRC_CTRL_RXFCDMODE_FCDMODE2 << 6) /**< Shifted mode FCDMODE2 for FRC_CTRL */ +#define FRC_CTRL_RXFCDMODE_FCDMODE3 (_FRC_CTRL_RXFCDMODE_FCDMODE3 << 6) /**< Shifted mode FCDMODE3 for FRC_CTRL */ +#define _FRC_CTRL_BITSPERWORD_SHIFT 8 /**< Shift value for FRC_BITSPERWORD */ +#define _FRC_CTRL_BITSPERWORD_MASK 0x700UL /**< Bit mask for FRC_BITSPERWORD */ +#define _FRC_CTRL_BITSPERWORD_DEFAULT 0x00000007UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_BITSPERWORD_DEFAULT (_FRC_CTRL_BITSPERWORD_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_RATESELECT_SHIFT 11 /**< Shift value for FRC_RATESELECT */ +#define _FRC_CTRL_RATESELECT_MASK 0x1800UL /**< Bit mask for FRC_RATESELECT */ +#define _FRC_CTRL_RATESELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_RATESELECT_DEFAULT (_FRC_CTRL_RATESELECT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_TXPREFETCH (0x1UL << 13) /**< Transmit prefetch data */ +#define _FRC_CTRL_TXPREFETCH_SHIFT 13 /**< Shift value for FRC_TXPREFETCH */ +#define _FRC_CTRL_TXPREFETCH_MASK 0x2000UL /**< Bit mask for FRC_TXPREFETCH */ +#define _FRC_CTRL_TXPREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_TXPREFETCH_X0 0x00000000UL /**< Mode X0 for FRC_CTRL */ +#define _FRC_CTRL_TXPREFETCH_X1 0x00000001UL /**< Mode X1 for FRC_CTRL */ +#define FRC_CTRL_TXPREFETCH_DEFAULT (_FRC_CTRL_TXPREFETCH_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_TXPREFETCH_X0 (_FRC_CTRL_TXPREFETCH_X0 << 13) /**< Shifted mode X0 for FRC_CTRL */ +#define FRC_CTRL_TXPREFETCH_X1 (_FRC_CTRL_TXPREFETCH_X1 << 13) /**< Shifted mode X1 for FRC_CTRL */ +#define FRC_CTRL_TXFETCHBLOCKING (0x1UL << 14) /**< Transmit fetch data blocking */ +#define _FRC_CTRL_TXFETCHBLOCKING_SHIFT 14 /**< Shift value for FRC_TXFETCHBLOCKING */ +#define _FRC_CTRL_TXFETCHBLOCKING_MASK 0x4000UL /**< Bit mask for FRC_TXFETCHBLOCKING */ +#define _FRC_CTRL_TXFETCHBLOCKING_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_TXFETCHBLOCKING_DEFAULT (_FRC_CTRL_TXFETCHBLOCKING_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SEQHANDSHAKE (0x1UL << 16) /**< Sequencer data handshake */ +#define _FRC_CTRL_SEQHANDSHAKE_SHIFT 16 /**< Shift value for FRC_SEQHANDSHAKE */ +#define _FRC_CTRL_SEQHANDSHAKE_MASK 0x10000UL /**< Bit mask for FRC_SEQHANDSHAKE */ +#define _FRC_CTRL_SEQHANDSHAKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define _FRC_CTRL_SEQHANDSHAKE_X0 0x00000000UL /**< Mode X0 for FRC_CTRL */ +#define _FRC_CTRL_SEQHANDSHAKE_X1 0x00000001UL /**< Mode X1 for FRC_CTRL */ +#define FRC_CTRL_SEQHANDSHAKE_DEFAULT (_FRC_CTRL_SEQHANDSHAKE_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SEQHANDSHAKE_X0 (_FRC_CTRL_SEQHANDSHAKE_X0 << 16) /**< Shifted mode X0 for FRC_CTRL */ +#define FRC_CTRL_SEQHANDSHAKE_X1 (_FRC_CTRL_SEQHANDSHAKE_X1 << 16) /**< Shifted mode X1 for FRC_CTRL */ +#define FRC_CTRL_PRBSTEST (0x1UL << 17) /**< Pseudo-Random Bit Sequence Testmode */ +#define _FRC_CTRL_PRBSTEST_SHIFT 17 /**< Shift value for FRC_PRBSTEST */ +#define _FRC_CTRL_PRBSTEST_MASK 0x20000UL /**< Bit mask for FRC_PRBSTEST */ +#define _FRC_CTRL_PRBSTEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_PRBSTEST_DEFAULT (_FRC_CTRL_PRBSTEST_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_LPMODEDIS (0x1UL << 18) /**< Disable FRC low power */ +#define _FRC_CTRL_LPMODEDIS_SHIFT 18 /**< Shift value for FRC_LPMODEDIS */ +#define _FRC_CTRL_LPMODEDIS_MASK 0x40000UL /**< Bit mask for FRC_LPMODEDIS */ +#define _FRC_CTRL_LPMODEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_LPMODEDIS_DEFAULT (_FRC_CTRL_LPMODEDIS_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_WAITEOFEN (0x1UL << 19) /**< Enable STATE_TX_WAITEOF */ +#define _FRC_CTRL_WAITEOFEN_SHIFT 19 /**< Shift value for FRC_WAITEOFEN */ +#define _FRC_CTRL_WAITEOFEN_MASK 0x80000UL /**< Bit mask for FRC_WAITEOFEN */ +#define _FRC_CTRL_WAITEOFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_WAITEOFEN_DEFAULT (_FRC_CTRL_WAITEOFEN_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_RXABORTIGNOREDIS (0x1UL << 20) /**< Disable ignoring CMD_RXABORT */ +#define _FRC_CTRL_RXABORTIGNOREDIS_SHIFT 20 /**< Shift value for FRC_RXABORTIGNOREDIS */ +#define _FRC_CTRL_RXABORTIGNOREDIS_MASK 0x100000UL /**< Bit mask for FRC_RXABORTIGNOREDIS */ +#define _FRC_CTRL_RXABORTIGNOREDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_RXABORTIGNOREDIS_DEFAULT (_FRC_CTRL_RXABORTIGNOREDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SKIPTXTRAILDATAWHITEN (0x1UL << 24) /**< TX Trail Data Skip Whitening */ +#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_SHIFT 24 /**< Shift value for FRC_SKIPTXTRAILDATAWHITEN */ +#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_MASK 0x1000000UL /**< Bit mask for FRC_SKIPTXTRAILDATAWHITEN */ +#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT (_FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SKIPRXSUPSTATEWHITEN (0x1UL << 25) /**< RX Supplemental Data Skip Whitening */ +#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_SHIFT 25 /**< Shift value for FRC_SKIPRXSUPSTATEWHITEN */ +#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_MASK 0x2000000UL /**< Bit mask for FRC_SKIPRXSUPSTATEWHITEN */ +#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT (_FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_HOLDTXTRAILDATAACTIVE (0x1UL << 26) /**< Defeat bit to hold txtraildata active */ +#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_SHIFT 26 /**< Shift value for FRC_HOLDTXTRAILDATAACTIVE */ +#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_MASK 0x4000000UL /**< Bit mask for FRC_HOLDTXTRAILDATAACTIVE */ +#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */ +#define FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT (_FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_CTRL */ + +/* Bit fields for FRC RXCTRL */ +#define _FRC_RXCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_RXCTRL */ +#define _FRC_RXCTRL_MASK 0x00000FFFUL /**< Mask for FRC_RXCTRL */ +#define FRC_RXCTRL_STORECRC (0x1UL << 0) /**< Store CRC value. */ +#define _FRC_RXCTRL_STORECRC_SHIFT 0 /**< Shift value for FRC_STORECRC */ +#define _FRC_RXCTRL_STORECRC_MASK 0x1UL /**< Bit mask for FRC_STORECRC */ +#define _FRC_RXCTRL_STORECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_STORECRC_DEFAULT (_FRC_RXCTRL_STORECRC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTCRCERRORS (0x1UL << 1) /**< Accept CRC Errors. */ +#define _FRC_RXCTRL_ACCEPTCRCERRORS_SHIFT 1 /**< Shift value for FRC_ACCEPTCRCERRORS */ +#define _FRC_RXCTRL_ACCEPTCRCERRORS_MASK 0x2UL /**< Bit mask for FRC_ACCEPTCRCERRORS */ +#define _FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define _FRC_RXCTRL_ACCEPTCRCERRORS_REJECT 0x00000000UL /**< Mode REJECT for FRC_RXCTRL */ +#define _FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT 0x00000001UL /**< Mode ACCEPT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTCRCERRORS_REJECT (_FRC_RXCTRL_ACCEPTCRCERRORS_REJECT << 1) /**< Shifted mode REJECT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT (_FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT << 1) /**< Shifted mode ACCEPT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTBLOCKERRORS (0x1UL << 2) /**< Accept Block Decoding Errors. */ +#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_SHIFT 2 /**< Shift value for FRC_ACCEPTBLOCKERRORS */ +#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_MASK 0x4UL /**< Bit mask for FRC_ACCEPTBLOCKERRORS */ +#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT 0x00000000UL /**< Mode REJECT for FRC_RXCTRL */ +#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT 0x00000001UL /**< Mode ACCEPT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT << 2) /**< Shifted mode REJECT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT << 2) /**< Shifted mode ACCEPT for FRC_RXCTRL */ +#define FRC_RXCTRL_TRACKABFRAME (0x1UL << 3) /**< Track Aborted RX Frame */ +#define _FRC_RXCTRL_TRACKABFRAME_SHIFT 3 /**< Shift value for FRC_TRACKABFRAME */ +#define _FRC_RXCTRL_TRACKABFRAME_MASK 0x8UL /**< Bit mask for FRC_TRACKABFRAME */ +#define _FRC_RXCTRL_TRACKABFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define _FRC_RXCTRL_TRACKABFRAME_X0 0x00000000UL /**< Mode X0 for FRC_RXCTRL */ +#define _FRC_RXCTRL_TRACKABFRAME_X1 0x00000001UL /**< Mode X1 for FRC_RXCTRL */ +#define FRC_RXCTRL_TRACKABFRAME_DEFAULT (_FRC_RXCTRL_TRACKABFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_TRACKABFRAME_X0 (_FRC_RXCTRL_TRACKABFRAME_X0 << 3) /**< Shifted mode X0 for FRC_RXCTRL */ +#define FRC_RXCTRL_TRACKABFRAME_X1 (_FRC_RXCTRL_TRACKABFRAME_X1 << 3) /**< Shifted mode X1 for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFCLEAR (0x1UL << 4) /**< Buffer Clear */ +#define _FRC_RXCTRL_BUFCLEAR_SHIFT 4 /**< Shift value for FRC_BUFCLEAR */ +#define _FRC_RXCTRL_BUFCLEAR_MASK 0x10UL /**< Bit mask for FRC_BUFCLEAR */ +#define _FRC_RXCTRL_BUFCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFCLEAR_DEFAULT (_FRC_RXCTRL_BUFCLEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFRESTOREFRAMEERROR (0x1UL << 5) /**< Buffer restore on frame error */ +#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_SHIFT 5 /**< Shift value for FRC_BUFRESTOREFRAMEERROR */ +#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_MASK 0x20UL /**< Bit mask for FRC_BUFRESTOREFRAMEERROR */ +#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT (_FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFRESTORERXABORTED (0x1UL << 6) /**< Buffer restore on RXABORTED */ +#define _FRC_RXCTRL_BUFRESTORERXABORTED_SHIFT 6 /**< Shift value for FRC_BUFRESTORERXABORTED */ +#define _FRC_RXCTRL_BUFRESTORERXABORTED_MASK 0x40UL /**< Bit mask for FRC_BUFRESTORERXABORTED */ +#define _FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT (_FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_SHIFT 7 /**< Shift value for FRC_RXFRAMEENDAHEADBYTES */ +#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_MASK 0x780UL /**< Bit mask for FRC_RXFRAMEENDAHEADBYTES */ +#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT (_FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTUARTERRORS (0x1UL << 11) /**< Accept UART Start/Stop bit Errors. */ +#define _FRC_RXCTRL_ACCEPTUARTERRORS_SHIFT 11 /**< Shift value for FRC_ACCEPTUARTERRORS */ +#define _FRC_RXCTRL_ACCEPTUARTERRORS_MASK 0x800UL /**< Bit mask for FRC_ACCEPTUARTERRORS */ +#define _FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */ +#define FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_RXCTRL */ + +/* Bit fields for FRC TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_MASK 0x00FFFFFFUL /**< Mask for FRC_TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_SHIFT 0 /**< Shift value for FRC_TRAILTXDATA */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_MASK 0xFFUL /**< Bit mask for FRC_TRAILTXDATA */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_SHIFT 8 /**< Shift value for FRC_TRAILTXDATACNT */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_MASK 0x700UL /**< Bit mask for FRC_TRAILTXDATACNT */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ +#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE (0x1UL << 11) /**< Force trailing TX data insertion */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_SHIFT 11 /**< Shift value for FRC_TRAILTXDATAFORCE */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_MASK 0x800UL /**< Bit mask for FRC_TRAILTXDATAFORCE */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 0x00000000UL /**< Mode X0 for FRC_TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 0x00000001UL /**< Mode X1 for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ +#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 << 11) /**< Shifted mode X0 for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 << 11) /**< Shifted mode X1 for FRC_TRAILTXDATACTRL */ +#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_SHIFT 12 /**< Shift value for FRC_TRAILTXREPLEN */ +#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_MASK 0x3FF000UL /**< Bit mask for FRC_TRAILTXREPLEN */ +#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ +#define FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE (0x1UL << 22) /**< TX Sup Len Override */ +#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_SHIFT 22 /**< Shift value for FRC_TXSUPPLENOVERIDE */ +#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_MASK 0x400000UL /**< Bit mask for FRC_TXSUPPLENOVERIDE */ +#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT (_FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ +#define FRC_TRAILTXDATACTRL_POSTAMBLEEN (0x1UL << 23) /**< WMBUS T mode postamble enable */ +#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_SHIFT 23 /**< Shift value for FRC_POSTAMBLEEN */ +#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_MASK 0x800000UL /**< Bit mask for FRC_POSTAMBLEEN */ +#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */ +#define FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT (_FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/ + +/* Bit fields for FRC TRAILRXDATA */ +#define _FRC_TRAILRXDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_TRAILRXDATA */ +#define _FRC_TRAILRXDATA_MASK 0x0000003FUL /**< Mask for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_RSSI (0x1UL << 0) /**< Append RSSI */ +#define _FRC_TRAILRXDATA_RSSI_SHIFT 0 /**< Shift value for FRC_RSSI */ +#define _FRC_TRAILRXDATA_RSSI_MASK 0x1UL /**< Bit mask for FRC_RSSI */ +#define _FRC_TRAILRXDATA_RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_RSSI_DEFAULT (_FRC_TRAILRXDATA_RSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_CRCOK (0x1UL << 1) /**< Append CRC OK Indicator */ +#define _FRC_TRAILRXDATA_CRCOK_SHIFT 1 /**< Shift value for FRC_CRCOK */ +#define _FRC_TRAILRXDATA_CRCOK_MASK 0x2UL /**< Bit mask for FRC_CRCOK */ +#define _FRC_TRAILRXDATA_CRCOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_CRCOK_DEFAULT (_FRC_TRAILRXDATA_CRCOK_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0BASE (0x1UL << 2) /**< PROTIMER Capture Compare channel 0 Base */ +#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_SHIFT 2 /**< Shift value for FRC_PROTIMERCC0BASE */ +#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_MASK 0x4UL /**< Bit mask for FRC_PROTIMERCC0BASE */ +#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0WRAPL (0x1UL << 3) /**< PROTIMER Capture Compare channel 0 WrapL */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_SHIFT 3 /**< Shift value for FRC_PROTIMERCC0WRAPL */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_MASK 0x8UL /**< Bit mask for FRC_PROTIMERCC0WRAPL */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0WRAPH (0x1UL << 4) /**< PROTIMER Capture Compare channel 0 WrapH */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_SHIFT 4 /**< Shift value for FRC_PROTIMERCC0WRAPH */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_MASK 0x10UL /**< Bit mask for FRC_PROTIMERCC0WRAPH */ +#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_RTCSTAMP (0x1UL << 5) /**< RTCC Time Stamp */ +#define _FRC_TRAILRXDATA_RTCSTAMP_SHIFT 5 /**< Shift value for FRC_RTCSTAMP */ +#define _FRC_TRAILRXDATA_RTCSTAMP_MASK 0x20UL /**< Bit mask for FRC_RTCSTAMP */ +#define _FRC_TRAILRXDATA_RTCSTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */ +#define FRC_TRAILRXDATA_RTCSTAMP_DEFAULT (_FRC_TRAILRXDATA_RTCSTAMP_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */ + +/* Bit fields for FRC SCNT */ +#define _FRC_SCNT_RESETVALUE 0x00000000UL /**< Default value for FRC_SCNT */ +#define _FRC_SCNT_MASK 0x000000FFUL /**< Mask for FRC_SCNT */ +#define _FRC_SCNT_SCNT_SHIFT 0 /**< Shift value for FRC_SCNT */ +#define _FRC_SCNT_SCNT_MASK 0xFFUL /**< Bit mask for FRC_SCNT */ +#define _FRC_SCNT_SCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SCNT */ +#define FRC_SCNT_SCNT_DEFAULT (_FRC_SCNT_SCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SCNT */ + +/* Bit fields for FRC CONVGENERATOR */ +#define _FRC_CONVGENERATOR_RESETVALUE 0x00000000UL /**< Default value for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_MASK 0x00037F7FUL /**< Mask for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_GENERATOR0_SHIFT 0 /**< Shift value for FRC_GENERATOR0 */ +#define _FRC_CONVGENERATOR_GENERATOR0_MASK 0x7FUL /**< Bit mask for FRC_GENERATOR0 */ +#define _FRC_CONVGENERATOR_GENERATOR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_GENERATOR0_DEFAULT (_FRC_CONVGENERATOR_GENERATOR0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_GENERATOR1_SHIFT 8 /**< Shift value for FRC_GENERATOR1 */ +#define _FRC_CONVGENERATOR_GENERATOR1_MASK 0x7F00UL /**< Bit mask for FRC_GENERATOR1 */ +#define _FRC_CONVGENERATOR_GENERATOR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_GENERATOR1_DEFAULT (_FRC_CONVGENERATOR_GENERATOR1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_RECURSIVE (0x1UL << 16) /**< Convolutional encoding */ +#define _FRC_CONVGENERATOR_RECURSIVE_SHIFT 16 /**< Shift value for FRC_RECURSIVE */ +#define _FRC_CONVGENERATOR_RECURSIVE_MASK 0x10000UL /**< Bit mask for FRC_RECURSIVE */ +#define _FRC_CONVGENERATOR_RECURSIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_RECURSIVE_X0 0x00000000UL /**< Mode X0 for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_RECURSIVE_X1 0x00000001UL /**< Mode X1 for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_RECURSIVE_DEFAULT (_FRC_CONVGENERATOR_RECURSIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_RECURSIVE_X0 (_FRC_CONVGENERATOR_RECURSIVE_X0 << 16) /**< Shifted mode X0 for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_RECURSIVE_X1 (_FRC_CONVGENERATOR_RECURSIVE_X1 << 16) /**< Shifted mode X1 for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_NONSYSTEMATIC (0x1UL << 17) /**< Non systematic recursive code */ +#define _FRC_CONVGENERATOR_NONSYSTEMATIC_SHIFT 17 /**< Shift value for FRC_NONSYSTEMATIC */ +#define _FRC_CONVGENERATOR_NONSYSTEMATIC_MASK 0x20000UL /**< Bit mask for FRC_NONSYSTEMATIC */ +#define _FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_NONSYSTEMATIC_X0 0x00000000UL /**< Mode X0 for FRC_CONVGENERATOR */ +#define _FRC_CONVGENERATOR_NONSYSTEMATIC_X1 0x00000001UL /**< Mode X1 for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT (_FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_NONSYSTEMATIC_X0 (_FRC_CONVGENERATOR_NONSYSTEMATIC_X0 << 17) /**< Shifted mode X0 for FRC_CONVGENERATOR */ +#define FRC_CONVGENERATOR_NONSYSTEMATIC_X1 (_FRC_CONVGENERATOR_NONSYSTEMATIC_X1 << 17) /**< Shifted mode X1 for FRC_CONVGENERATOR */ + +/* Bit fields for FRC PUNCTCTRL */ +#define _FRC_PUNCTCTRL_RESETVALUE 0x00000101UL /**< Default value for FRC_PUNCTCTRL */ +#define _FRC_PUNCTCTRL_MASK 0x00007F7FUL /**< Mask for FRC_PUNCTCTRL */ +#define _FRC_PUNCTCTRL_PUNCT0_SHIFT 0 /**< Shift value for FRC_PUNCT0 */ +#define _FRC_PUNCTCTRL_PUNCT0_MASK 0x7FUL /**< Bit mask for FRC_PUNCT0 */ +#define _FRC_PUNCTCTRL_PUNCT0_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_PUNCTCTRL */ +#define FRC_PUNCTCTRL_PUNCT0_DEFAULT (_FRC_PUNCTCTRL_PUNCT0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PUNCTCTRL */ +#define _FRC_PUNCTCTRL_PUNCT1_SHIFT 8 /**< Shift value for FRC_PUNCT1 */ +#define _FRC_PUNCTCTRL_PUNCT1_MASK 0x7F00UL /**< Bit mask for FRC_PUNCT1 */ +#define _FRC_PUNCTCTRL_PUNCT1_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_PUNCTCTRL */ +#define FRC_PUNCTCTRL_PUNCT1_DEFAULT (_FRC_PUNCTCTRL_PUNCT1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PUNCTCTRL */ + +/* Bit fields for FRC PAUSECTRL */ +#define _FRC_PAUSECTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_PAUSECTRL */ +#define _FRC_PAUSECTRL_MASK 0x07FFF83FUL /**< Mask for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_FRAMEDETPAUSEEN (0x1UL << 0) /**< Frame detect pause enable */ +#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_SHIFT 0 /**< Shift value for FRC_FRAMEDETPAUSEEN */ +#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_MASK 0x1UL /**< Bit mask for FRC_FRAMEDETPAUSEEN */ +#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT (_FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN (0x1UL << 1) /**< Transmit interleaver write pause enable */ +#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_SHIFT 1 /**< Shift value for FRC_TXINTERLEAVEWRITEPAUSEEN*/ +#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_MASK 0x2UL /**< Bit mask for FRC_TXINTERLEAVEWRITEPAUSEEN */ +#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN (0x1UL << 2) /**< Receive interleaver write pause enable */ +#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_SHIFT 2 /**< Shift value for FRC_RXINTERLEAVEWRITEPAUSEEN*/ +#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_MASK 0x4UL /**< Bit mask for FRC_RXINTERLEAVEWRITEPAUSEEN */ +#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN (0x1UL << 3) /**< Interleaver read pause enable */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_SHIFT 3 /**< Shift value for FRC_INTERLEAVEREADPAUSEEN */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_MASK 0x8UL /**< Bit mask for FRC_INTERLEAVEREADPAUSEEN */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN (0x1UL << 4) /**< Transmit subframe pause enable */ +#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_SHIFT 4 /**< Shift value for FRC_TXSUBFRAMEPAUSEEN */ +#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_MASK 0x10UL /**< Bit mask for FRC_TXSUBFRAMEPAUSEEN */ +#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN (0x1UL << 5) /**< Receive wcnt match pause enable */ +#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_SHIFT 5 /**< Shift value for FRC_RXWCNTMATCHPAUSEEN */ +#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_MASK 0x20UL /**< Bit mask for FRC_RXWCNTMATCHPAUSEEN */ +#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT (_FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define _FRC_PAUSECTRL_CONVPAUSECNT_SHIFT 11 /**< Shift value for FRC_CONVPAUSECNT */ +#define _FRC_PAUSECTRL_CONVPAUSECNT_MASK 0x1F800UL /**< Bit mask for FRC_CONVPAUSECNT */ +#define _FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT (_FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_SHIFT 17 /**< Shift value for FRC_INTERLEAVEWRITEPAUSECNT */ +#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_MASK 0x3E0000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSECNT */ +#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_SHIFT 22 /**< Shift value for FRC_INTERLEAVEREADPAUSECNT */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_MASK 0x7C00000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSECNT */ +#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */ +#define FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */ + +/* Bit fields for FRC IF */ +#define _FRC_IF_RESETVALUE 0x00000000UL /**< Default value for FRC_IF */ +#define _FRC_IF_MASK 0xFFFFFFFFUL /**< Mask for FRC_IF */ +#define FRC_IF_TXDONE (0x1UL << 0) /**< TX Done Interrupt Flag */ +#define _FRC_IF_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */ +#define _FRC_IF_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */ +#define _FRC_IF_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXDONE_DEFAULT (_FRC_IF_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Flag */ +#define _FRC_IF_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */ +#define _FRC_IF_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */ +#define _FRC_IF_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXAFTERFRAMEDONE_DEFAULT (_FRC_IF_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Flag */ +#define _FRC_IF_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */ +#define _FRC_IF_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */ +#define _FRC_IF_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXABORTED_DEFAULT (_FRC_IF_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Flag */ +#define _FRC_IF_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */ +#define _FRC_IF_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */ +#define _FRC_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXUF_DEFAULT (_FRC_IF_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXDONE (0x1UL << 4) /**< RX Done Interrupt Flag */ +#define _FRC_IF_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */ +#define _FRC_IF_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */ +#define _FRC_IF_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXDONE_DEFAULT (_FRC_IF_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Flag */ +#define _FRC_IF_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */ +#define _FRC_IF_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */ +#define _FRC_IF_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXABORTED_DEFAULT (_FRC_IF_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Flag */ +#define _FRC_IF_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */ +#define _FRC_IF_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */ +#define _FRC_IF_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_FRAMEERROR_DEFAULT (_FRC_IF_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Flag */ +#define _FRC_IF_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */ +#define _FRC_IF_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */ +#define _FRC_IF_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_BLOCKERROR_DEFAULT (_FRC_IF_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Flag */ +#define _FRC_IF_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */ +#define _FRC_IF_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */ +#define _FRC_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXOF_DEFAULT (_FRC_IF_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Event */ +#define _FRC_IF_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */ +#define _FRC_IF_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */ +#define _FRC_IF_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP0_DEFAULT (_FRC_IF_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Event */ +#define _FRC_IF_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */ +#define _FRC_IF_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */ +#define _FRC_IF_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP1_DEFAULT (_FRC_IF_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Event */ +#define _FRC_IF_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */ +#define _FRC_IF_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */ +#define _FRC_IF_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP2_DEFAULT (_FRC_IF_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_ADDRERROR (0x1UL << 12) /**< Receive address error event */ +#define _FRC_IF_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */ +#define _FRC_IF_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */ +#define _FRC_IF_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_ADDRERROR_DEFAULT (_FRC_IF_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_BUSERROR (0x1UL << 13) /**< A bus error event occurred */ +#define _FRC_IF_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */ +#define _FRC_IF_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */ +#define _FRC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_BUSERROR_DEFAULT (_FRC_IF_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data event */ +#define _FRC_IF_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */ +#define _FRC_IF_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */ +#define _FRC_IF_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXRAWEVENT_DEFAULT (_FRC_IF_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data event */ +#define _FRC_IF_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */ +#define _FRC_IF_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */ +#define _FRC_IF_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXRAWEVENT_DEFAULT (_FRC_IF_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow */ +#define _FRC_IF_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */ +#define _FRC_IF_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */ +#define _FRC_IF_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_SNIFFOF_DEFAULT (_FRC_IF_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Event */ +#define _FRC_IF_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */ +#define _FRC_IF_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */ +#define _FRC_IF_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP3_DEFAULT (_FRC_IF_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Event */ +#define _FRC_IF_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */ +#define _FRC_IF_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */ +#define _FRC_IF_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP4_DEFAULT (_FRC_IF_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_BOISET (0x1UL << 19) /**< BOI SET */ +#define _FRC_IF_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */ +#define _FRC_IF_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */ +#define _FRC_IF_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_BOISET_DEFAULT (_FRC_IF_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_PKTBUFSTART (0x1UL << 20) /**< Packet Buffer Start */ +#define _FRC_IF_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */ +#define _FRC_IF_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */ +#define _FRC_IF_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_PKTBUFSTART_DEFAULT (_FRC_IF_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_PKTBUFTHRESHOLD (0x1UL << 21) /**< Packet Buffer Threshold */ +#define _FRC_IF_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */ +#define _FRC_IF_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */ +#define _FRC_IF_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_PKTBUFTHRESHOLD_DEFAULT (_FRC_IF_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXRAWOF (0x1UL << 22) /**< RX raw FIFO overflow */ +#define _FRC_IF_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */ +#define _FRC_IF_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */ +#define _FRC_IF_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXRAWOF_DEFAULT (_FRC_IF_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Event */ +#define _FRC_IF_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */ +#define _FRC_IF_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */ +#define _FRC_IF_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_WCNTCMP5_DEFAULT (_FRC_IF_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event active */ +#define _FRC_IF_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */ +#define _FRC_IF_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */ +#define _FRC_IF_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_FRAMEDETPAUSED_DEFAULT (_FRC_IF_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event active */ +#define _FRC_IF_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_IF_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event active */ +#define _FRC_IF_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_IF_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_IF_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_INTERLEAVEREADPAUSED_DEFAULT (_FRC_IF_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event active */ +#define _FRC_IF_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_IF_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_IF_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXSUBFRAMEPAUSED_DEFAULT (_FRC_IF_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event active */ +#define _FRC_IF_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */ +#define _FRC_IF_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */ +#define _FRC_IF_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_CONVPAUSED_DEFAULT (_FRC_IF_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Flag */ +#define _FRC_IF_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */ +#define _FRC_IF_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */ +#define _FRC_IF_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_RXWORD_DEFAULT (_FRC_IF_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Flag */ +#define _FRC_IF_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */ +#define _FRC_IF_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */ +#define _FRC_IF_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_TXWORD_DEFAULT (_FRC_IF_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_IF */ +#define FRC_IF_UARTERROR (0x1UL << 31) /**< Uart Error Interrupt Flag */ +#define _FRC_IF_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */ +#define _FRC_IF_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */ +#define _FRC_IF_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */ +#define FRC_IF_UARTERROR_DEFAULT (_FRC_IF_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_IF */ + +/* Bit fields for FRC IEN */ +#define _FRC_IEN_RESETVALUE 0x00000000UL /**< Default value for FRC_IEN */ +#define _FRC_IEN_MASK 0xFFFFFFFFUL /**< Mask for FRC_IEN */ +#define FRC_IEN_TXDONE (0x1UL << 0) /**< TX Done Interrupt Enable */ +#define _FRC_IEN_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */ +#define _FRC_IEN_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */ +#define _FRC_IEN_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXDONE_DEFAULT (_FRC_IEN_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Enable */ +#define _FRC_IEN_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */ +#define _FRC_IEN_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */ +#define _FRC_IEN_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXAFTERFRAMEDONE_DEFAULT (_FRC_IEN_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Enable */ +#define _FRC_IEN_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */ +#define _FRC_IEN_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */ +#define _FRC_IEN_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXABORTED_DEFAULT (_FRC_IEN_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Enable */ +#define _FRC_IEN_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */ +#define _FRC_IEN_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */ +#define _FRC_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXUF_DEFAULT (_FRC_IEN_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXDONE (0x1UL << 4) /**< RX Done Interrupt Enable */ +#define _FRC_IEN_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */ +#define _FRC_IEN_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */ +#define _FRC_IEN_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXDONE_DEFAULT (_FRC_IEN_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Enable */ +#define _FRC_IEN_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */ +#define _FRC_IEN_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */ +#define _FRC_IEN_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXABORTED_DEFAULT (_FRC_IEN_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Enable */ +#define _FRC_IEN_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */ +#define _FRC_IEN_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */ +#define _FRC_IEN_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_FRAMEERROR_DEFAULT (_FRC_IEN_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Enable */ +#define _FRC_IEN_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */ +#define _FRC_IEN_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */ +#define _FRC_IEN_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BLOCKERROR_DEFAULT (_FRC_IEN_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Enable */ +#define _FRC_IEN_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */ +#define _FRC_IEN_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */ +#define _FRC_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXOF_DEFAULT (_FRC_IEN_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Enable */ +#define _FRC_IEN_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */ +#define _FRC_IEN_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */ +#define _FRC_IEN_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP0_DEFAULT (_FRC_IEN_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Enable */ +#define _FRC_IEN_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */ +#define _FRC_IEN_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */ +#define _FRC_IEN_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP1_DEFAULT (_FRC_IEN_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Enable */ +#define _FRC_IEN_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */ +#define _FRC_IEN_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */ +#define _FRC_IEN_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP2_DEFAULT (_FRC_IEN_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_ADDRERROR (0x1UL << 12) /**< Receive address error enable */ +#define _FRC_IEN_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */ +#define _FRC_IEN_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */ +#define _FRC_IEN_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_ADDRERROR_DEFAULT (_FRC_IEN_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BUSERROR (0x1UL << 13) /**< Bus error enable */ +#define _FRC_IEN_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */ +#define _FRC_IEN_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */ +#define _FRC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BUSERROR_DEFAULT (_FRC_IEN_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data enable */ +#define _FRC_IEN_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */ +#define _FRC_IEN_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */ +#define _FRC_IEN_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXRAWEVENT_DEFAULT (_FRC_IEN_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data enable */ +#define _FRC_IEN_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */ +#define _FRC_IEN_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */ +#define _FRC_IEN_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXRAWEVENT_DEFAULT (_FRC_IEN_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow enable */ +#define _FRC_IEN_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */ +#define _FRC_IEN_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */ +#define _FRC_IEN_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_SNIFFOF_DEFAULT (_FRC_IEN_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Enable */ +#define _FRC_IEN_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */ +#define _FRC_IEN_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */ +#define _FRC_IEN_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP3_DEFAULT (_FRC_IEN_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Enable */ +#define _FRC_IEN_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */ +#define _FRC_IEN_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */ +#define _FRC_IEN_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP4_DEFAULT (_FRC_IEN_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BOISET (0x1UL << 19) /**< BOISET */ +#define _FRC_IEN_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */ +#define _FRC_IEN_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */ +#define _FRC_IEN_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_BOISET_DEFAULT (_FRC_IEN_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_PKTBUFSTART (0x1UL << 20) /**< PKTBUFSTART Enable */ +#define _FRC_IEN_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */ +#define _FRC_IEN_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */ +#define _FRC_IEN_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_PKTBUFSTART_DEFAULT (_FRC_IEN_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_PKTBUFTHRESHOLD (0x1UL << 21) /**< PKTBUFTHRESHOLD Enable */ +#define _FRC_IEN_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */ +#define _FRC_IEN_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */ +#define _FRC_IEN_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_PKTBUFTHRESHOLD_DEFAULT (_FRC_IEN_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXRAWOF (0x1UL << 22) /**< RXRAWOF Enable */ +#define _FRC_IEN_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */ +#define _FRC_IEN_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */ +#define _FRC_IEN_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXRAWOF_DEFAULT (_FRC_IEN_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Enable */ +#define _FRC_IEN_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */ +#define _FRC_IEN_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */ +#define _FRC_IEN_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_WCNTCMP5_DEFAULT (_FRC_IEN_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event enable */ +#define _FRC_IEN_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */ +#define _FRC_IEN_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */ +#define _FRC_IEN_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_FRAMEDETPAUSED_DEFAULT (_FRC_IEN_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event enable */ +#define _FRC_IEN_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_IEN_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event enable */ +#define _FRC_IEN_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_IEN_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT (_FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event enable */ +#define _FRC_IEN_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_IEN_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT (_FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event enable */ +#define _FRC_IEN_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */ +#define _FRC_IEN_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */ +#define _FRC_IEN_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_CONVPAUSED_DEFAULT (_FRC_IEN_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Enable */ +#define _FRC_IEN_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */ +#define _FRC_IEN_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */ +#define _FRC_IEN_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_RXWORD_DEFAULT (_FRC_IEN_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Enable */ +#define _FRC_IEN_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */ +#define _FRC_IEN_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */ +#define _FRC_IEN_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_TXWORD_DEFAULT (_FRC_IEN_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_IEN */ +#define FRC_IEN_UARTERROR (0x1UL << 31) /**< UART Error Interrupt Enable */ +#define _FRC_IEN_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */ +#define _FRC_IEN_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */ +#define _FRC_IEN_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */ +#define FRC_IEN_UARTERROR_DEFAULT (_FRC_IEN_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_IEN */ + +/* Bit fields for FRC OTACNT */ +#define _FRC_OTACNT_RESETVALUE 0x00000000UL /**< Default value for FRC_OTACNT */ +#define _FRC_OTACNT_MASK 0xFFFFFFFFUL /**< Mask for FRC_OTACNT */ +#define _FRC_OTACNT_OTARXCNT_SHIFT 0 /**< Shift value for FRC_OTARXCNT */ +#define _FRC_OTACNT_OTARXCNT_MASK 0xFFFFUL /**< Bit mask for FRC_OTARXCNT */ +#define _FRC_OTACNT_OTARXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_OTACNT */ +#define FRC_OTACNT_OTARXCNT_DEFAULT (_FRC_OTACNT_OTARXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_OTACNT */ +#define _FRC_OTACNT_OTATXCNT_SHIFT 16 /**< Shift value for FRC_OTATXCNT */ +#define _FRC_OTACNT_OTATXCNT_MASK 0xFFFF0000UL /**< Bit mask for FRC_OTATXCNT */ +#define _FRC_OTACNT_OTATXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_OTACNT */ +#define FRC_OTACNT_OTATXCNT_DEFAULT (_FRC_OTACNT_OTATXCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_OTACNT */ + +/* Bit fields for FRC BUFFERMODE */ +#define _FRC_BUFFERMODE_RESETVALUE 0x00000000UL /**< Default value for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_MASK 0x0000000FUL /**< Mask for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_TXBUFFERMODE (0x1UL << 0) /**< Transmit Buffer Mode */ +#define _FRC_BUFFERMODE_TXBUFFERMODE_SHIFT 0 /**< Shift value for FRC_TXBUFFERMODE */ +#define _FRC_BUFFERMODE_TXBUFFERMODE_MASK 0x1UL /**< Bit mask for FRC_TXBUFFERMODE */ +#define _FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_TXBUFFERMODE_BUFC 0x00000000UL /**< Mode BUFC for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_TXBUFFERMODE_REGISTER 0x00000001UL /**< Mode REGISTER for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT (_FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_TXBUFFERMODE_BUFC (_FRC_BUFFERMODE_TXBUFFERMODE_BUFC << 0) /**< Shifted mode BUFC for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_TXBUFFERMODE_REGISTER (_FRC_BUFFERMODE_TXBUFFERMODE_REGISTER << 0) /**< Shifted mode REGISTER for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_SHIFT 1 /**< Shift value for FRC_RXBUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_MASK 0x6UL /**< Bit mask for FRC_RXBUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_BUFC 0x00000000UL /**< Mode BUFC for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_REGISTER 0x00000001UL /**< Mode REGISTER for FRC_BUFFERMODE */ +#define _FRC_BUFFERMODE_RXBUFFERMODE_DISABLE 0x00000002UL /**< Mode DISABLE for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT (_FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXBUFFERMODE_BUFC (_FRC_BUFFERMODE_RXBUFFERMODE_BUFC << 1) /**< Shifted mode BUFC for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXBUFFERMODE_REGISTER (_FRC_BUFFERMODE_RXBUFFERMODE_REGISTER << 1) /**< Shifted mode REGISTER for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXBUFFERMODE_DISABLE (_FRC_BUFFERMODE_RXBUFFERMODE_DISABLE << 1) /**< Shifted mode DISABLE for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXFRCBUFMUX (0x1UL << 3) /**< RX FRC Buffer Mux */ +#define _FRC_BUFFERMODE_RXFRCBUFMUX_SHIFT 3 /**< Shift value for FRC_RXFRCBUFMUX */ +#define _FRC_BUFFERMODE_RXFRCBUFMUX_MASK 0x8UL /**< Bit mask for FRC_RXFRCBUFMUX */ +#define _FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */ +#define FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT (_FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */ + +/* Bit fields for FRC SNIFFCTRL */ +#define _FRC_SNIFFCTRL_RESETVALUE 0x000007FCUL /**< Default value for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_MASK 0x0003FFFFUL /**< Mask for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFMODE_SHIFT 0 /**< Shift value for FRC_SNIFFMODE */ +#define _FRC_SNIFFCTRL_SNIFFMODE_MASK 0x3UL /**< Bit mask for FRC_SNIFFMODE */ +#define _FRC_SNIFFCTRL_SNIFFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFMODE_OFF 0x00000000UL /**< Mode OFF for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFMODE_UART 0x00000001UL /**< Mode UART for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFMODE_SPI 0x00000002UL /**< Mode SPI for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFMODE_DEFAULT (_FRC_SNIFFCTRL_SNIFFMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFMODE_OFF (_FRC_SNIFFCTRL_SNIFFMODE_OFF << 0) /**< Shifted mode OFF for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFMODE_UART (_FRC_SNIFFCTRL_SNIFFMODE_UART << 0) /**< Shifted mode UART for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFMODE_SPI (_FRC_SNIFFCTRL_SNIFFMODE_SPI << 0) /**< Shifted mode SPI for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFBITS (0x1UL << 2) /**< Data sniff data bits */ +#define _FRC_SNIFFCTRL_SNIFFBITS_SHIFT 2 /**< Shift value for FRC_SNIFFBITS */ +#define _FRC_SNIFFCTRL_SNIFFBITS_MASK 0x4UL /**< Bit mask for FRC_SNIFFBITS */ +#define _FRC_SNIFFCTRL_SNIFFBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFBITS_EIGHT 0x00000000UL /**< Mode EIGHT for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFBITS_NINE 0x00000001UL /**< Mode NINE for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFBITS_DEFAULT (_FRC_SNIFFCTRL_SNIFFBITS_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFBITS_EIGHT (_FRC_SNIFFCTRL_SNIFFBITS_EIGHT << 2) /**< Shifted mode EIGHT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFBITS_NINE (_FRC_SNIFFCTRL_SNIFFBITS_NINE << 2) /**< Shifted mode NINE for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFRXDATA (0x1UL << 3) /**< Enable sniffing of received data. */ +#define _FRC_SNIFFCTRL_SNIFFRXDATA_SHIFT 3 /**< Shift value for FRC_SNIFFRXDATA */ +#define _FRC_SNIFFCTRL_SNIFFRXDATA_MASK 0x8UL /**< Bit mask for FRC_SNIFFRXDATA */ +#define _FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFTXDATA (0x1UL << 4) /**< Enable sniffing of transmitted data. */ +#define _FRC_SNIFFCTRL_SNIFFTXDATA_SHIFT 4 /**< Shift value for FRC_SNIFFTXDATA */ +#define _FRC_SNIFFCTRL_SNIFFTXDATA_MASK 0x10UL /**< Bit mask for FRC_SNIFFTXDATA */ +#define _FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFRSSI (0x1UL << 5) /**< Enable sniffing of RSSI */ +#define _FRC_SNIFFCTRL_SNIFFRSSI_SHIFT 5 /**< Shift value for FRC_SNIFFRSSI */ +#define _FRC_SNIFFCTRL_SNIFFRSSI_MASK 0x20UL /**< Bit mask for FRC_SNIFFRSSI */ +#define _FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT (_FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFSTATE (0x1UL << 6) /**< Enable sniffing of state information */ +#define _FRC_SNIFFCTRL_SNIFFSTATE_SHIFT 6 /**< Shift value for FRC_SNIFFSTATE */ +#define _FRC_SNIFFCTRL_SNIFFSTATE_MASK 0x40UL /**< Bit mask for FRC_SNIFFSTATE */ +#define _FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT (_FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFAUXDATA (0x1UL << 7) /**< Enable sniffing of auxiliary data */ +#define _FRC_SNIFFCTRL_SNIFFAUXDATA_SHIFT 7 /**< Shift value for FRC_SNIFFAUXDATA */ +#define _FRC_SNIFFCTRL_SNIFFAUXDATA_MASK 0x80UL /**< Bit mask for FRC_SNIFFAUXDATA */ +#define _FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define _FRC_SNIFFCTRL_SNIFFBR_SHIFT 8 /**< Shift value for FRC_SNIFFBR */ +#define _FRC_SNIFFCTRL_SNIFFBR_MASK 0xFF00UL /**< Bit mask for FRC_SNIFFBR */ +#define _FRC_SNIFFCTRL_SNIFFBR_DEFAULT 0x00000007UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFBR_DEFAULT (_FRC_SNIFFCTRL_SNIFFBR_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFSYNCWORD (0x1UL << 17) /**< Sniffer baudrate setting */ +#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_SHIFT 17 /**< Shift value for FRC_SNIFFSYNCWORD */ +#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_MASK 0x20000UL /**< Bit mask for FRC_SNIFFSYNCWORD */ +#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SNIFFCTRL */ +#define FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT (_FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */ + +/* Bit fields for FRC AUXDATA */ +#define _FRC_AUXDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_AUXDATA */ +#define _FRC_AUXDATA_MASK 0x000001FFUL /**< Mask for FRC_AUXDATA */ +#define _FRC_AUXDATA_AUXDATA_SHIFT 0 /**< Shift value for FRC_AUXDATA */ +#define _FRC_AUXDATA_AUXDATA_MASK 0x1FFUL /**< Bit mask for FRC_AUXDATA */ +#define _FRC_AUXDATA_AUXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_AUXDATA */ +#define FRC_AUXDATA_AUXDATA_DEFAULT (_FRC_AUXDATA_AUXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AUXDATA */ + +/* Bit fields for FRC RAWCTRL */ +#define _FRC_RAWCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_MASK 0x000021BFUL /**< Mask for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_TXRAWMODE_SHIFT 0 /**< Shift value for FRC_TXRAWMODE */ +#define _FRC_RAWCTRL_TXRAWMODE_MASK 0x3UL /**< Bit mask for FRC_TXRAWMODE */ +#define _FRC_RAWCTRL_TXRAWMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_TXRAWMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER 0x00000001UL /**< Mode SINGLEBUFFER for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER 0x00000002UL /**< Mode REPEATBUFFER for FRC_RAWCTRL */ +#define FRC_RAWCTRL_TXRAWMODE_DEFAULT (_FRC_RAWCTRL_TXRAWMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RAWCTRL */ +#define FRC_RAWCTRL_TXRAWMODE_DISABLE (_FRC_RAWCTRL_TXRAWMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_RAWCTRL */ +#define FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER (_FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER << 0) /**< Shifted mode SINGLEBUFFER for FRC_RAWCTRL */ +#define FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER (_FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER << 0) /**< Shifted mode REPEATBUFFER for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_SHIFT 2 /**< Shift value for FRC_RXRAWMODE */ +#define _FRC_RAWCTRL_RXRAWMODE_MASK 0x1CUL /**< Bit mask for FRC_RXRAWMODE */ +#define _FRC_RAWCTRL_RXRAWMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_SINGLEITEM 0x00000001UL /**< Mode SINGLEITEM for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER 0x00000002UL /**< Mode SINGLEBUFFER for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME 0x00000003UL /**< Mode SINGLEBUFFERFRAME for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER 0x00000004UL /**< Mode REPEATBUFFER for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWMODE_DEFAULT (_FRC_RAWCTRL_RXRAWMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWMODE_DISABLE (_FRC_RAWCTRL_RXRAWMODE_DISABLE << 2) /**< Shifted mode DISABLE for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWMODE_SINGLEITEM (_FRC_RAWCTRL_RXRAWMODE_SINGLEITEM << 2) /**< Shifted mode SINGLEITEM for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER (_FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER << 2) /**< Shifted mode SINGLEBUFFER for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME (_FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME << 2) /**< Shifted mode SINGLEBUFFERFRAME for FRC_RAWCTRL*/ +#define FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER (_FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER << 2) /**< Shifted mode REPEATBUFFER for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWRANDOM (0x1UL << 5) /**< Receive raw data random number generator */ +#define _FRC_RAWCTRL_RXRAWRANDOM_SHIFT 5 /**< Shift value for FRC_RXRAWRANDOM */ +#define _FRC_RAWCTRL_RXRAWRANDOM_MASK 0x20UL /**< Bit mask for FRC_RXRAWRANDOM */ +#define _FRC_RAWCTRL_RXRAWRANDOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWRANDOM_DEFAULT (_FRC_RAWCTRL_RXRAWRANDOM_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_SHIFT 7 /**< Shift value for FRC_RXRAWTRIGGER */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_MASK 0x180UL /**< Bit mask for FRC_RXRAWTRIGGER */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_PRS 0x00000001UL /**< Mode PRS for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG 0x00000002UL /**< Mode INTERNALSIG for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT (_FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE (_FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE << 7) /**< Shifted mode IMMEDIATE for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWTRIGGER_PRS (_FRC_RAWCTRL_RXRAWTRIGGER_PRS << 7) /**< Shifted mode PRS for FRC_RAWCTRL */ +#define FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG (_FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG << 7) /**< Shifted mode INTERNALSIG for FRC_RAWCTRL */ +#define FRC_RAWCTRL_DEMODRAWDATAMUX (0x1UL << 13) /**< Raw data mux control */ +#define _FRC_RAWCTRL_DEMODRAWDATAMUX_SHIFT 13 /**< Shift value for FRC_DEMODRAWDATAMUX */ +#define _FRC_RAWCTRL_DEMODRAWDATAMUX_MASK 0x2000UL /**< Bit mask for FRC_DEMODRAWDATAMUX */ +#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL 0x00000000UL /**< Mode DEMODRAWDATASEL for FRC_RAWCTRL */ +#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 0x00000001UL /**< Mode DEMODRAWDATASEL2 for FRC_RAWCTRL */ +#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_RAWCTRL */ +#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL << 13) /**< Shifted mode DEMODRAWDATASEL for FRC_RAWCTRL*/ +#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 << 13) /**< Shifted mode DEMODRAWDATASEL2 for FRC_RAWCTRL*/ + +/* Bit fields for FRC RXRAWDATA */ +#define _FRC_RXRAWDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_RXRAWDATA */ +#define _FRC_RXRAWDATA_MASK 0xFFFFFFFFUL /**< Mask for FRC_RXRAWDATA */ +#define _FRC_RXRAWDATA_RXRAWDATA_SHIFT 0 /**< Shift value for FRC_RXRAWDATA */ +#define _FRC_RXRAWDATA_RXRAWDATA_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_RXRAWDATA */ +#define _FRC_RXRAWDATA_RXRAWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXRAWDATA */ +#define FRC_RXRAWDATA_RXRAWDATA_DEFAULT (_FRC_RXRAWDATA_RXRAWDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RXRAWDATA */ + +/* Bit fields for FRC PAUSEDATA */ +#define _FRC_PAUSEDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_PAUSEDATA */ +#define _FRC_PAUSEDATA_MASK 0xFFFFFFFFUL /**< Mask for FRC_PAUSEDATA */ +#define _FRC_PAUSEDATA_PAUSEDATA_SHIFT 0 /**< Shift value for FRC_PAUSEDATA */ +#define _FRC_PAUSEDATA_PAUSEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_PAUSEDATA */ +#define _FRC_PAUSEDATA_PAUSEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSEDATA */ +#define FRC_PAUSEDATA_PAUSEDATA_DEFAULT (_FRC_PAUSEDATA_PAUSEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PAUSEDATA */ + +/* Bit fields for FRC LIKELYCONVSTATE */ +#define _FRC_LIKELYCONVSTATE_RESETVALUE 0x00000000UL /**< Default value for FRC_LIKELYCONVSTATE */ +#define _FRC_LIKELYCONVSTATE_MASK 0x0000003FUL /**< Mask for FRC_LIKELYCONVSTATE */ +#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_SHIFT 0 /**< Shift value for FRC_LIKELYCONVSTATE */ +#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_MASK 0x3FUL /**< Bit mask for FRC_LIKELYCONVSTATE */ +#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_LIKELYCONVSTATE */ +#define FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT (_FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_LIKELYCONVSTATE*/ + +/* Bit fields for FRC INTELEMENTNEXT */ +#define _FRC_INTELEMENTNEXT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTELEMENTNEXT */ +#define _FRC_INTELEMENTNEXT_MASK 0x000000FFUL /**< Mask for FRC_INTELEMENTNEXT */ +#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_SHIFT 0 /**< Shift value for FRC_INTELEMENTNEXT */ +#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_MASK 0xFFUL /**< Bit mask for FRC_INTELEMENTNEXT */ +#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTELEMENTNEXT */ +#define FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT (_FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTELEMENTNEXT */ + +/* Bit fields for FRC INTWRITEPOINT */ +#define _FRC_INTWRITEPOINT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTWRITEPOINT */ +#define _FRC_INTWRITEPOINT_MASK 0x0000001FUL /**< Mask for FRC_INTWRITEPOINT */ +#define _FRC_INTWRITEPOINT_INTWRITEPOINT_SHIFT 0 /**< Shift value for FRC_INTWRITEPOINT */ +#define _FRC_INTWRITEPOINT_INTWRITEPOINT_MASK 0x1FUL /**< Bit mask for FRC_INTWRITEPOINT */ +#define _FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTWRITEPOINT */ +#define FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT (_FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTWRITEPOINT */ + +/* Bit fields for FRC INTREADPOINT */ +#define _FRC_INTREADPOINT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTREADPOINT */ +#define _FRC_INTREADPOINT_MASK 0x0000001FUL /**< Mask for FRC_INTREADPOINT */ +#define _FRC_INTREADPOINT_INTREADPOINT_SHIFT 0 /**< Shift value for FRC_INTREADPOINT */ +#define _FRC_INTREADPOINT_INTREADPOINT_MASK 0x1FUL /**< Bit mask for FRC_INTREADPOINT */ +#define _FRC_INTREADPOINT_INTREADPOINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTREADPOINT */ +#define FRC_INTREADPOINT_INTREADPOINT_DEFAULT (_FRC_INTREADPOINT_INTREADPOINT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTREADPOINT */ + +/* Bit fields for FRC AUTOCG */ +#define _FRC_AUTOCG_RESETVALUE 0x00000000UL /**< Default value for FRC_AUTOCG */ +#define _FRC_AUTOCG_MASK 0x0000FFFFUL /**< Mask for FRC_AUTOCG */ +#define _FRC_AUTOCG_AUTOCGEN_SHIFT 0 /**< Shift value for FRC_AUTOCGEN */ +#define _FRC_AUTOCG_AUTOCGEN_MASK 0xFFFFUL /**< Bit mask for FRC_AUTOCGEN */ +#define _FRC_AUTOCG_AUTOCGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_AUTOCG */ +#define FRC_AUTOCG_AUTOCGEN_DEFAULT (_FRC_AUTOCG_AUTOCGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AUTOCG */ + +/* Bit fields for FRC CGCLKSTOP */ +#define _FRC_CGCLKSTOP_RESETVALUE 0x00000000UL /**< Default value for FRC_CGCLKSTOP */ +#define _FRC_CGCLKSTOP_MASK 0x0000FFFFUL /**< Mask for FRC_CGCLKSTOP */ +#define _FRC_CGCLKSTOP_FORCEOFF_SHIFT 0 /**< Shift value for FRC_FORCEOFF */ +#define _FRC_CGCLKSTOP_FORCEOFF_MASK 0xFFFFUL /**< Bit mask for FRC_FORCEOFF */ +#define _FRC_CGCLKSTOP_FORCEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CGCLKSTOP */ +#define FRC_CGCLKSTOP_FORCEOFF_DEFAULT (_FRC_CGCLKSTOP_FORCEOFF_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CGCLKSTOP */ + +/* Bit fields for FRC SEQIF */ +#define _FRC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for FRC_SEQIF */ +#define _FRC_SEQIF_MASK 0xFFFFFFFFUL /**< Mask for FRC_SEQIF */ +#define FRC_SEQIF_TXDONE (0x1UL << 0) /**< TX Done Interrupt Flag */ +#define _FRC_SEQIF_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */ +#define _FRC_SEQIF_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */ +#define _FRC_SEQIF_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXDONE_DEFAULT (_FRC_SEQIF_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Flag */ +#define _FRC_SEQIF_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */ +#define _FRC_SEQIF_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */ +#define _FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT (_FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Flag */ +#define _FRC_SEQIF_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */ +#define _FRC_SEQIF_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */ +#define _FRC_SEQIF_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXABORTED_DEFAULT (_FRC_SEQIF_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Flag */ +#define _FRC_SEQIF_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */ +#define _FRC_SEQIF_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */ +#define _FRC_SEQIF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXUF_DEFAULT (_FRC_SEQIF_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXDONE (0x1UL << 4) /**< RX Done Interrupt Flag */ +#define _FRC_SEQIF_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */ +#define _FRC_SEQIF_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */ +#define _FRC_SEQIF_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXDONE_DEFAULT (_FRC_SEQIF_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Flag */ +#define _FRC_SEQIF_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */ +#define _FRC_SEQIF_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */ +#define _FRC_SEQIF_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXABORTED_DEFAULT (_FRC_SEQIF_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Flag */ +#define _FRC_SEQIF_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */ +#define _FRC_SEQIF_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */ +#define _FRC_SEQIF_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_FRAMEERROR_DEFAULT (_FRC_SEQIF_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Flag */ +#define _FRC_SEQIF_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */ +#define _FRC_SEQIF_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */ +#define _FRC_SEQIF_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BLOCKERROR_DEFAULT (_FRC_SEQIF_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Flag */ +#define _FRC_SEQIF_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */ +#define _FRC_SEQIF_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */ +#define _FRC_SEQIF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXOF_DEFAULT (_FRC_SEQIF_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Event */ +#define _FRC_SEQIF_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */ +#define _FRC_SEQIF_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */ +#define _FRC_SEQIF_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP0_DEFAULT (_FRC_SEQIF_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Event */ +#define _FRC_SEQIF_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */ +#define _FRC_SEQIF_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */ +#define _FRC_SEQIF_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP1_DEFAULT (_FRC_SEQIF_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Event */ +#define _FRC_SEQIF_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */ +#define _FRC_SEQIF_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */ +#define _FRC_SEQIF_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP2_DEFAULT (_FRC_SEQIF_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_ADDRERROR (0x1UL << 12) /**< Receive address error event */ +#define _FRC_SEQIF_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */ +#define _FRC_SEQIF_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */ +#define _FRC_SEQIF_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_ADDRERROR_DEFAULT (_FRC_SEQIF_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BUSERROR (0x1UL << 13) /**< A bus error event occurred */ +#define _FRC_SEQIF_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */ +#define _FRC_SEQIF_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */ +#define _FRC_SEQIF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BUSERROR_DEFAULT (_FRC_SEQIF_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data event */ +#define _FRC_SEQIF_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */ +#define _FRC_SEQIF_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */ +#define _FRC_SEQIF_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXRAWEVENT_DEFAULT (_FRC_SEQIF_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data event */ +#define _FRC_SEQIF_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */ +#define _FRC_SEQIF_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */ +#define _FRC_SEQIF_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXRAWEVENT_DEFAULT (_FRC_SEQIF_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow */ +#define _FRC_SEQIF_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */ +#define _FRC_SEQIF_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */ +#define _FRC_SEQIF_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_SNIFFOF_DEFAULT (_FRC_SEQIF_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Event */ +#define _FRC_SEQIF_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */ +#define _FRC_SEQIF_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */ +#define _FRC_SEQIF_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP3_DEFAULT (_FRC_SEQIF_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Event */ +#define _FRC_SEQIF_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */ +#define _FRC_SEQIF_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */ +#define _FRC_SEQIF_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP4_DEFAULT (_FRC_SEQIF_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BOISET (0x1UL << 19) /**< BOISET Event */ +#define _FRC_SEQIF_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */ +#define _FRC_SEQIF_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */ +#define _FRC_SEQIF_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_BOISET_DEFAULT (_FRC_SEQIF_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_PKTBUFSTART (0x1UL << 20) /**< Packet Buffer Start */ +#define _FRC_SEQIF_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */ +#define _FRC_SEQIF_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */ +#define _FRC_SEQIF_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_PKTBUFSTART_DEFAULT (_FRC_SEQIF_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_PKTBUFTHRESHOLD (0x1UL << 21) /**< Packet Buffer Threshold */ +#define _FRC_SEQIF_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */ +#define _FRC_SEQIF_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */ +#define _FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT (_FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXRAWOF (0x1UL << 22) /**< RX raw FIFO overflow */ +#define _FRC_SEQIF_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */ +#define _FRC_SEQIF_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */ +#define _FRC_SEQIF_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXRAWOF_DEFAULT (_FRC_SEQIF_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Event */ +#define _FRC_SEQIF_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */ +#define _FRC_SEQIF_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */ +#define _FRC_SEQIF_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_WCNTCMP5_DEFAULT (_FRC_SEQIF_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event active */ +#define _FRC_SEQIF_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */ +#define _FRC_SEQIF_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */ +#define _FRC_SEQIF_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_FRAMEDETPAUSED_DEFAULT (_FRC_SEQIF_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event active */ +#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event active */ +#define _FRC_SEQIF_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_SEQIF_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT (_FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event active */ +#define _FRC_SEQIF_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_SEQIF_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT (_FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event active */ +#define _FRC_SEQIF_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */ +#define _FRC_SEQIF_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */ +#define _FRC_SEQIF_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_CONVPAUSED_DEFAULT (_FRC_SEQIF_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Flag */ +#define _FRC_SEQIF_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */ +#define _FRC_SEQIF_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */ +#define _FRC_SEQIF_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_RXWORD_DEFAULT (_FRC_SEQIF_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Flag */ +#define _FRC_SEQIF_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */ +#define _FRC_SEQIF_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */ +#define _FRC_SEQIF_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_TXWORD_DEFAULT (_FRC_SEQIF_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_UARTERROR (0x1UL << 31) /**< Uart Error Interrupt Flag */ +#define _FRC_SEQIF_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */ +#define _FRC_SEQIF_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */ +#define _FRC_SEQIF_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */ +#define FRC_SEQIF_UARTERROR_DEFAULT (_FRC_SEQIF_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_SEQIF */ + +/* Bit fields for FRC SEQIEN */ +#define _FRC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for FRC_SEQIEN */ +#define _FRC_SEQIEN_MASK 0xFFFFFFFFUL /**< Mask for FRC_SEQIEN */ +#define FRC_SEQIEN_TXDONE (0x1UL << 0) /**< TX Done Interrupt Enable */ +#define _FRC_SEQIEN_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */ +#define _FRC_SEQIEN_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */ +#define _FRC_SEQIEN_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXDONE_DEFAULT (_FRC_SEQIEN_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Enable */ +#define _FRC_SEQIEN_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */ +#define _FRC_SEQIEN_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */ +#define _FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT (_FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Enable */ +#define _FRC_SEQIEN_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */ +#define _FRC_SEQIEN_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */ +#define _FRC_SEQIEN_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXABORTED_DEFAULT (_FRC_SEQIEN_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Enable */ +#define _FRC_SEQIEN_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */ +#define _FRC_SEQIEN_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */ +#define _FRC_SEQIEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXUF_DEFAULT (_FRC_SEQIEN_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXDONE (0x1UL << 4) /**< RX Done Interrupt Enable */ +#define _FRC_SEQIEN_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */ +#define _FRC_SEQIEN_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */ +#define _FRC_SEQIEN_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXDONE_DEFAULT (_FRC_SEQIEN_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Enable */ +#define _FRC_SEQIEN_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */ +#define _FRC_SEQIEN_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */ +#define _FRC_SEQIEN_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXABORTED_DEFAULT (_FRC_SEQIEN_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Enable */ +#define _FRC_SEQIEN_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */ +#define _FRC_SEQIEN_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */ +#define _FRC_SEQIEN_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_FRAMEERROR_DEFAULT (_FRC_SEQIEN_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Enable */ +#define _FRC_SEQIEN_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */ +#define _FRC_SEQIEN_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */ +#define _FRC_SEQIEN_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BLOCKERROR_DEFAULT (_FRC_SEQIEN_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Enable */ +#define _FRC_SEQIEN_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */ +#define _FRC_SEQIEN_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */ +#define _FRC_SEQIEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXOF_DEFAULT (_FRC_SEQIEN_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Enable */ +#define _FRC_SEQIEN_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */ +#define _FRC_SEQIEN_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */ +#define _FRC_SEQIEN_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP0_DEFAULT (_FRC_SEQIEN_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Enable */ +#define _FRC_SEQIEN_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */ +#define _FRC_SEQIEN_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */ +#define _FRC_SEQIEN_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP1_DEFAULT (_FRC_SEQIEN_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Enable */ +#define _FRC_SEQIEN_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */ +#define _FRC_SEQIEN_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */ +#define _FRC_SEQIEN_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP2_DEFAULT (_FRC_SEQIEN_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_ADDRERROR (0x1UL << 12) /**< Receive address error enable */ +#define _FRC_SEQIEN_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */ +#define _FRC_SEQIEN_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */ +#define _FRC_SEQIEN_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_ADDRERROR_DEFAULT (_FRC_SEQIEN_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BUSERROR (0x1UL << 13) /**< Bus error enable */ +#define _FRC_SEQIEN_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */ +#define _FRC_SEQIEN_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */ +#define _FRC_SEQIEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BUSERROR_DEFAULT (_FRC_SEQIEN_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data enable */ +#define _FRC_SEQIEN_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */ +#define _FRC_SEQIEN_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */ +#define _FRC_SEQIEN_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXRAWEVENT_DEFAULT (_FRC_SEQIEN_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data enable */ +#define _FRC_SEQIEN_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */ +#define _FRC_SEQIEN_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */ +#define _FRC_SEQIEN_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXRAWEVENT_DEFAULT (_FRC_SEQIEN_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow enable */ +#define _FRC_SEQIEN_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */ +#define _FRC_SEQIEN_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */ +#define _FRC_SEQIEN_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_SNIFFOF_DEFAULT (_FRC_SEQIEN_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Enable */ +#define _FRC_SEQIEN_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */ +#define _FRC_SEQIEN_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */ +#define _FRC_SEQIEN_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP3_DEFAULT (_FRC_SEQIEN_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Enable */ +#define _FRC_SEQIEN_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */ +#define _FRC_SEQIEN_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */ +#define _FRC_SEQIEN_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP4_DEFAULT (_FRC_SEQIEN_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BOISET (0x1UL << 19) /**< Word Counter Compare 2 Enable */ +#define _FRC_SEQIEN_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */ +#define _FRC_SEQIEN_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */ +#define _FRC_SEQIEN_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_BOISET_DEFAULT (_FRC_SEQIEN_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_PKTBUFSTART (0x1UL << 20) /**< PKTBUFSTART Enable */ +#define _FRC_SEQIEN_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */ +#define _FRC_SEQIEN_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */ +#define _FRC_SEQIEN_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_PKTBUFSTART_DEFAULT (_FRC_SEQIEN_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_PKTBUFTHRESHOLD (0x1UL << 21) /**< PKTBUFTHRESHOLD Enable */ +#define _FRC_SEQIEN_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */ +#define _FRC_SEQIEN_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */ +#define _FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT (_FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXRAWOF (0x1UL << 22) /**< RXRAWOF Enable */ +#define _FRC_SEQIEN_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */ +#define _FRC_SEQIEN_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */ +#define _FRC_SEQIEN_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXRAWOF_DEFAULT (_FRC_SEQIEN_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Enable */ +#define _FRC_SEQIEN_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */ +#define _FRC_SEQIEN_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */ +#define _FRC_SEQIEN_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_WCNTCMP5_DEFAULT (_FRC_SEQIEN_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event enable */ +#define _FRC_SEQIEN_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */ +#define _FRC_SEQIEN_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */ +#define _FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT (_FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event enable */ +#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */ +#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event enable */ +#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */ +#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT (_FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event enable */ +#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */ +#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT (_FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event enable */ +#define _FRC_SEQIEN_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */ +#define _FRC_SEQIEN_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */ +#define _FRC_SEQIEN_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_CONVPAUSED_DEFAULT (_FRC_SEQIEN_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Enable */ +#define _FRC_SEQIEN_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */ +#define _FRC_SEQIEN_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */ +#define _FRC_SEQIEN_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_RXWORD_DEFAULT (_FRC_SEQIEN_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Enable */ +#define _FRC_SEQIEN_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */ +#define _FRC_SEQIEN_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */ +#define _FRC_SEQIEN_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_TXWORD_DEFAULT (_FRC_SEQIEN_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_UARTERROR (0x1UL << 31) /**< UART Error Interrupt Enable */ +#define _FRC_SEQIEN_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */ +#define _FRC_SEQIEN_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */ +#define _FRC_SEQIEN_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */ +#define FRC_SEQIEN_UARTERROR_DEFAULT (_FRC_SEQIEN_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_SEQIEN */ + +/* Bit fields for FRC WCNTCMP3 */ +#define _FRC_WCNTCMP3_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP3 */ +#define _FRC_WCNTCMP3_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP3 */ +#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_SHIFT 0 /**< Shift value for FRC_SUPPLENFIELDLOC */ +#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_SUPPLENFIELDLOC */ +#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP3 */ +#define FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT (_FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP3 */ + +/* Bit fields for FRC BOICTRL */ +#define _FRC_BOICTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_BOICTRL */ +#define _FRC_BOICTRL_MASK 0x0001FFFFUL /**< Mask for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIEN (0x1UL << 0) /**< BOI EN */ +#define _FRC_BOICTRL_BOIEN_SHIFT 0 /**< Shift value for FRC_BOIEN */ +#define _FRC_BOICTRL_BOIEN_MASK 0x1UL /**< Bit mask for FRC_BOIEN */ +#define _FRC_BOICTRL_BOIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIEN_DEFAULT (_FRC_BOICTRL_BOIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_BOICTRL */ +#define _FRC_BOICTRL_BOIFIELDLOC_SHIFT 1 /**< Shift value for FRC_BOIFIELDLOC */ +#define _FRC_BOICTRL_BOIFIELDLOC_MASK 0x1FFEUL /**< Bit mask for FRC_BOIFIELDLOC */ +#define _FRC_BOICTRL_BOIFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIFIELDLOC_DEFAULT (_FRC_BOICTRL_BOIFIELDLOC_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_BOICTRL */ +#define _FRC_BOICTRL_BOIBITPOS_SHIFT 13 /**< Shift value for FRC_BOIBITPOS */ +#define _FRC_BOICTRL_BOIBITPOS_MASK 0xE000UL /**< Bit mask for FRC_BOIBITPOS */ +#define _FRC_BOICTRL_BOIBITPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIBITPOS_DEFAULT (_FRC_BOICTRL_BOIBITPOS_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIMATCHVAL (0x1UL << 16) /**< BOI match value */ +#define _FRC_BOICTRL_BOIMATCHVAL_SHIFT 16 /**< Shift value for FRC_BOIMATCHVAL */ +#define _FRC_BOICTRL_BOIMATCHVAL_MASK 0x10000UL /**< Bit mask for FRC_BOIMATCHVAL */ +#define _FRC_BOICTRL_BOIMATCHVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */ +#define FRC_BOICTRL_BOIMATCHVAL_DEFAULT (_FRC_BOICTRL_BOIMATCHVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_BOICTRL */ + +/* Bit fields for FRC DSLCTRL */ +#define _FRC_DSLCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_MASK 0x7FFFFF7FUL /**< Mask for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_SHIFT 0 /**< Shift value for FRC_DSLMODE */ +#define _FRC_DSLCTRL_DSLMODE_MASK 0x7UL /**< Bit mask for FRC_DSLMODE */ +#define _FRC_DSLCTRL_DSLMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_SINGLEBYTE 0x00000001UL /**< Mode SINGLEBYTE for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB 0x00000002UL /**< Mode SINGLEBYTEMSB for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST 0x00000003UL /**< Mode DUALBYTELSBFIRST for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST 0x00000004UL /**< Mode DUALBYTEMSBFIRST for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_INFINITE 0x00000005UL /**< Mode INFINITE for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMODE_BLOCKERROR 0x00000006UL /**< Mode BLOCKERROR for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_DEFAULT (_FRC_DSLCTRL_DSLMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_DISABLE (_FRC_DSLCTRL_DSLMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_SINGLEBYTE (_FRC_DSLCTRL_DSLMODE_SINGLEBYTE << 0) /**< Shifted mode SINGLEBYTE for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB (_FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB << 0) /**< Shifted mode SINGLEBYTEMSB for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST (_FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST << 0) /**< Shifted mode DUALBYTELSBFIRST for FRC_DSLCTRL*/ +#define FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST (_FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST << 0) /**< Shifted mode DUALBYTEMSBFIRST for FRC_DSLCTRL*/ +#define FRC_DSLCTRL_DSLMODE_INFINITE (_FRC_DSLCTRL_DSLMODE_INFINITE << 0) /**< Shifted mode INFINITE for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMODE_BLOCKERROR (_FRC_DSLCTRL_DSLMODE_BLOCKERROR << 0) /**< Shifted mode BLOCKERROR for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLBITORDER (0x1UL << 3) /**< Dynamic Frame Length Bit order */ +#define _FRC_DSLCTRL_DSLBITORDER_SHIFT 3 /**< Shift value for FRC_DSLBITORDER */ +#define _FRC_DSLCTRL_DSLBITORDER_MASK 0x8UL /**< Bit mask for FRC_DSLBITORDER */ +#define _FRC_DSLCTRL_DSLBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLBITORDER_NORMAL 0x00000000UL /**< Mode NORMAL for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLBITORDER_REVERSE 0x00000001UL /**< Mode REVERSE for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLBITORDER_DEFAULT (_FRC_DSLCTRL_DSLBITORDER_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLBITORDER_NORMAL (_FRC_DSLCTRL_DSLBITORDER_NORMAL << 3) /**< Shifted mode NORMAL for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLBITORDER_REVERSE (_FRC_DSLCTRL_DSLBITORDER_REVERSE << 3) /**< Shifted mode REVERSE for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLSHIFT_SHIFT 4 /**< Shift value for FRC_DSLSHIFT */ +#define _FRC_DSLCTRL_DSLSHIFT_MASK 0x70UL /**< Bit mask for FRC_DSLSHIFT */ +#define _FRC_DSLCTRL_DSLSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLSHIFT_DEFAULT (_FRC_DSLCTRL_DSLSHIFT_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLOFFSET_SHIFT 8 /**< Shift value for FRC_DSLOFFSET */ +#define _FRC_DSLCTRL_DSLOFFSET_MASK 0xFF00UL /**< Bit mask for FRC_DSLOFFSET */ +#define _FRC_DSLCTRL_DSLOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLOFFSET_DEFAULT (_FRC_DSLCTRL_DSLOFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLBITS_SHIFT 16 /**< Shift value for FRC_DSLBITS */ +#define _FRC_DSLCTRL_DSLBITS_MASK 0xF0000UL /**< Bit mask for FRC_DSLBITS */ +#define _FRC_DSLCTRL_DSLBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLBITS_DEFAULT (_FRC_DSLCTRL_DSLBITS_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_DSLMINLENGTH_SHIFT 20 /**< Shift value for FRC_DSLMINLENGTH */ +#define _FRC_DSLCTRL_DSLMINLENGTH_MASK 0xF00000UL /**< Bit mask for FRC_DSLMINLENGTH */ +#define _FRC_DSLCTRL_DSLMINLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_DSLMINLENGTH_DEFAULT (_FRC_DSLCTRL_DSLMINLENGTH_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_SHIFT 24 /**< Shift value for FRC_RXSUPRECEPMODE */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_MASK 0x7000000UL /**< Bit mask for FRC_RXSUPRECEPMODE */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP 0x00000000UL /**< Mode NOSUP for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED 0x00000001UL /**< Mode BOIDSLBASED for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED 0x00000002UL /**< Mode BOIFIXEDSLBASED for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED 0x00000003UL /**< Mode DSLBASED for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED 0x00000004UL /**< Mode FIXEDSLBASED for FRC_DSLCTRL */ +#define FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT (_FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP (_FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP << 24) /**< Shifted mode NOSUP for FRC_DSLCTRL */ +#define FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED << 24) /**< Shifted mode BOIDSLBASED for FRC_DSLCTRL */ +#define FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED << 24) /**< Shifted mode BOIFIXEDSLBASED for FRC_DSLCTRL*/ +#define FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED << 24) /**< Shifted mode DSLBASED for FRC_DSLCTRL */ +#define FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED << 24) /**< Shifted mode FIXEDSLBASED for FRC_DSLCTRL */ +#define FRC_DSLCTRL_STORESUP (0x1UL << 27) /**< Store SUPP in BUFC */ +#define _FRC_DSLCTRL_STORESUP_SHIFT 27 /**< Shift value for FRC_STORESUP */ +#define _FRC_DSLCTRL_STORESUP_MASK 0x8000000UL /**< Bit mask for FRC_STORESUP */ +#define _FRC_DSLCTRL_STORESUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_STORESUP_DEFAULT (_FRC_DSLCTRL_STORESUP_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ +#define _FRC_DSLCTRL_SUPSHFFACTOR_SHIFT 28 /**< Shift value for FRC_SUPSHFFACTOR */ +#define _FRC_DSLCTRL_SUPSHFFACTOR_MASK 0x70000000UL /**< Bit mask for FRC_SUPSHFFACTOR */ +#define _FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */ +#define FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT (_FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_DSLCTRL */ + +/* Bit fields for FRC WCNTCMP4 */ +#define _FRC_WCNTCMP4_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP4 */ +#define _FRC_WCNTCMP4_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP4 */ +#define _FRC_WCNTCMP4_SUPPLENGTH_SHIFT 0 /**< Shift value for FRC_SUPPLENGTH */ +#define _FRC_WCNTCMP4_SUPPLENGTH_MASK 0xFFFUL /**< Bit mask for FRC_SUPPLENGTH */ +#define _FRC_WCNTCMP4_SUPPLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP4 */ +#define FRC_WCNTCMP4_SUPPLENGTH_DEFAULT (_FRC_WCNTCMP4_SUPPLENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP4 */ + +/* Bit fields for FRC WCNTCMP5 */ +#define _FRC_WCNTCMP5_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP5 */ +#define _FRC_WCNTCMP5_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP5 */ +#define _FRC_WCNTCMP5_RXPAUSELOC_SHIFT 0 /**< Shift value for FRC_RXPAUSELOC */ +#define _FRC_WCNTCMP5_RXPAUSELOC_MASK 0xFFFUL /**< Bit mask for FRC_RXPAUSELOC */ +#define _FRC_WCNTCMP5_RXPAUSELOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP5 */ +#define FRC_WCNTCMP5_RXPAUSELOC_DEFAULT (_FRC_WCNTCMP5_RXPAUSELOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP5 */ + +/* Bit fields for FRC PKTBUFCTRL */ +#define _FRC_PKTBUFCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUFCTRL */ +#define _FRC_PKTBUFCTRL_MASK 0x0303FFFFUL /**< Mask for FRC_PKTBUFCTRL */ +#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_SHIFT 0 /**< Shift value for FRC_PKTBUFSTARTLOC */ +#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_MASK 0xFFFUL /**< Bit mask for FRC_PKTBUFSTARTLOC */ +#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_SHIFT 12 /**< Shift value for FRC_PKTBUFTHRESHOLD */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_MASK 0x3F000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN (0x1UL << 24) /**< Packet Buffer Threshold Enable */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_SHIFT 24 /**< Shift value for FRC_PKTBUFTHRESHOLDEN */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_MASK 0x1000000UL /**< Bit mask for FRC_PKTBUFTHRESHOLDEN */ +#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFSTOP (0x1UL << 25) /**< Packet Buffer stop receiving command */ +#define _FRC_PKTBUFCTRL_PKTBUFSTOP_SHIFT 25 /**< Shift value for FRC_PKTBUFSTOP */ +#define _FRC_PKTBUFCTRL_PKTBUFSTOP_MASK 0x2000000UL /**< Bit mask for FRC_PKTBUFSTOP */ +#define _FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */ +#define FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */ + +/* Bit fields for FRC PKTBUFSTATUS */ +#define _FRC_PKTBUFSTATUS_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUFSTATUS */ +#define _FRC_PKTBUFSTATUS_MASK 0x0000003FUL /**< Mask for FRC_PKTBUFSTATUS */ +#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_SHIFT 0 /**< Shift value for FRC_PKTBUFCOUNT */ +#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_MASK 0x3FUL /**< Bit mask for FRC_PKTBUFCOUNT */ +#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFSTATUS */ +#define FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT (_FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUFSTATUS */ + +/* Bit fields for FRC PKTBUF0 */ +#define _FRC_PKTBUF0_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF0_SHIFT 0 /**< Shift value for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF0_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */ +#define FRC_PKTBUF0_PKTBUF0_DEFAULT (_FRC_PKTBUF0_PKTBUF0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF1_SHIFT 8 /**< Shift value for FRC_PKTBUF1 */ +#define _FRC_PKTBUF0_PKTBUF1_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF1 */ +#define _FRC_PKTBUF0_PKTBUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */ +#define FRC_PKTBUF0_PKTBUF1_DEFAULT (_FRC_PKTBUF0_PKTBUF1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF2_SHIFT 16 /**< Shift value for FRC_PKTBUF2 */ +#define _FRC_PKTBUF0_PKTBUF2_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF2 */ +#define _FRC_PKTBUF0_PKTBUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */ +#define FRC_PKTBUF0_PKTBUF2_DEFAULT (_FRC_PKTBUF0_PKTBUF2_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */ +#define _FRC_PKTBUF0_PKTBUF3_SHIFT 24 /**< Shift value for FRC_PKTBUF3 */ +#define _FRC_PKTBUF0_PKTBUF3_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF3 */ +#define _FRC_PKTBUF0_PKTBUF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */ +#define FRC_PKTBUF0_PKTBUF3_DEFAULT (_FRC_PKTBUF0_PKTBUF3_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */ + +/* Bit fields for FRC PKTBUF1 */ +#define _FRC_PKTBUF1_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF1 */ +#define _FRC_PKTBUF1_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF1 */ +#define _FRC_PKTBUF1_PKTBUF4_SHIFT 0 /**< Shift value for FRC_PKTBUF4 */ +#define _FRC_PKTBUF1_PKTBUF4_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF4 */ +#define _FRC_PKTBUF1_PKTBUF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */ +#define FRC_PKTBUF1_PKTBUF4_DEFAULT (_FRC_PKTBUF1_PKTBUF4_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */ +#define _FRC_PKTBUF1_PKTBUF5_SHIFT 8 /**< Shift value for FRC_PKTBUF5 */ +#define _FRC_PKTBUF1_PKTBUF5_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF5 */ +#define _FRC_PKTBUF1_PKTBUF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */ +#define FRC_PKTBUF1_PKTBUF5_DEFAULT (_FRC_PKTBUF1_PKTBUF5_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */ +#define _FRC_PKTBUF1_PKTBUF6_SHIFT 16 /**< Shift value for FRC_PKTBUF6 */ +#define _FRC_PKTBUF1_PKTBUF6_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF6 */ +#define _FRC_PKTBUF1_PKTBUF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */ +#define FRC_PKTBUF1_PKTBUF6_DEFAULT (_FRC_PKTBUF1_PKTBUF6_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */ +#define _FRC_PKTBUF1_PKTBUF7_SHIFT 24 /**< Shift value for FRC_PKTBUF7 */ +#define _FRC_PKTBUF1_PKTBUF7_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF7 */ +#define _FRC_PKTBUF1_PKTBUF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */ +#define FRC_PKTBUF1_PKTBUF7_DEFAULT (_FRC_PKTBUF1_PKTBUF7_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */ + +/* Bit fields for FRC PKTBUF2 */ +#define _FRC_PKTBUF2_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF2 */ +#define _FRC_PKTBUF2_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF2 */ +#define _FRC_PKTBUF2_PKTBUF8_SHIFT 0 /**< Shift value for FRC_PKTBUF8 */ +#define _FRC_PKTBUF2_PKTBUF8_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF8 */ +#define _FRC_PKTBUF2_PKTBUF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */ +#define FRC_PKTBUF2_PKTBUF8_DEFAULT (_FRC_PKTBUF2_PKTBUF8_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */ +#define _FRC_PKTBUF2_PKTBUF9_SHIFT 8 /**< Shift value for FRC_PKTBUF9 */ +#define _FRC_PKTBUF2_PKTBUF9_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF9 */ +#define _FRC_PKTBUF2_PKTBUF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */ +#define FRC_PKTBUF2_PKTBUF9_DEFAULT (_FRC_PKTBUF2_PKTBUF9_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */ +#define _FRC_PKTBUF2_PKTBUF10_SHIFT 16 /**< Shift value for FRC_PKTBUF10 */ +#define _FRC_PKTBUF2_PKTBUF10_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF10 */ +#define _FRC_PKTBUF2_PKTBUF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */ +#define FRC_PKTBUF2_PKTBUF10_DEFAULT (_FRC_PKTBUF2_PKTBUF10_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */ +#define _FRC_PKTBUF2_PKTBUF11_SHIFT 24 /**< Shift value for FRC_PKTBUF11 */ +#define _FRC_PKTBUF2_PKTBUF11_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF11 */ +#define _FRC_PKTBUF2_PKTBUF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */ +#define FRC_PKTBUF2_PKTBUF11_DEFAULT (_FRC_PKTBUF2_PKTBUF11_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */ + +/* Bit fields for FRC PKTBUF3 */ +#define _FRC_PKTBUF3_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF3 */ +#define _FRC_PKTBUF3_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF3 */ +#define _FRC_PKTBUF3_PKTBUF12_SHIFT 0 /**< Shift value for FRC_PKTBUF12 */ +#define _FRC_PKTBUF3_PKTBUF12_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF12 */ +#define _FRC_PKTBUF3_PKTBUF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */ +#define FRC_PKTBUF3_PKTBUF12_DEFAULT (_FRC_PKTBUF3_PKTBUF12_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */ +#define _FRC_PKTBUF3_PKTBUF13_SHIFT 8 /**< Shift value for FRC_PKTBUF13 */ +#define _FRC_PKTBUF3_PKTBUF13_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF13 */ +#define _FRC_PKTBUF3_PKTBUF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */ +#define FRC_PKTBUF3_PKTBUF13_DEFAULT (_FRC_PKTBUF3_PKTBUF13_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */ +#define _FRC_PKTBUF3_PKTBUF14_SHIFT 16 /**< Shift value for FRC_PKTBUF14 */ +#define _FRC_PKTBUF3_PKTBUF14_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF14 */ +#define _FRC_PKTBUF3_PKTBUF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */ +#define FRC_PKTBUF3_PKTBUF14_DEFAULT (_FRC_PKTBUF3_PKTBUF14_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */ +#define _FRC_PKTBUF3_PKTBUF15_SHIFT 24 /**< Shift value for FRC_PKTBUF15 */ +#define _FRC_PKTBUF3_PKTBUF15_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF15 */ +#define _FRC_PKTBUF3_PKTBUF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */ +#define FRC_PKTBUF3_PKTBUF15_DEFAULT (_FRC_PKTBUF3_PKTBUF15_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */ + +/* Bit fields for FRC PKTBUF4 */ +#define _FRC_PKTBUF4_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF4 */ +#define _FRC_PKTBUF4_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF4 */ +#define _FRC_PKTBUF4_PKTBUF16_SHIFT 0 /**< Shift value for FRC_PKTBUF16 */ +#define _FRC_PKTBUF4_PKTBUF16_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF16 */ +#define _FRC_PKTBUF4_PKTBUF16_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */ +#define FRC_PKTBUF4_PKTBUF16_DEFAULT (_FRC_PKTBUF4_PKTBUF16_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */ +#define _FRC_PKTBUF4_PKTBUF17_SHIFT 8 /**< Shift value for FRC_PKTBUF17 */ +#define _FRC_PKTBUF4_PKTBUF17_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF17 */ +#define _FRC_PKTBUF4_PKTBUF17_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */ +#define FRC_PKTBUF4_PKTBUF17_DEFAULT (_FRC_PKTBUF4_PKTBUF17_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */ +#define _FRC_PKTBUF4_PKTBUF18_SHIFT 16 /**< Shift value for FRC_PKTBUF18 */ +#define _FRC_PKTBUF4_PKTBUF18_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF18 */ +#define _FRC_PKTBUF4_PKTBUF18_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */ +#define FRC_PKTBUF4_PKTBUF18_DEFAULT (_FRC_PKTBUF4_PKTBUF18_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */ +#define _FRC_PKTBUF4_PKTBUF19_SHIFT 24 /**< Shift value for FRC_PKTBUF19 */ +#define _FRC_PKTBUF4_PKTBUF19_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF19 */ +#define _FRC_PKTBUF4_PKTBUF19_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */ +#define FRC_PKTBUF4_PKTBUF19_DEFAULT (_FRC_PKTBUF4_PKTBUF19_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */ + +/* Bit fields for FRC PKTBUF5 */ +#define _FRC_PKTBUF5_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF5 */ +#define _FRC_PKTBUF5_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF5 */ +#define _FRC_PKTBUF5_PKTBUF20_SHIFT 0 /**< Shift value for FRC_PKTBUF20 */ +#define _FRC_PKTBUF5_PKTBUF20_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF20 */ +#define _FRC_PKTBUF5_PKTBUF20_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */ +#define FRC_PKTBUF5_PKTBUF20_DEFAULT (_FRC_PKTBUF5_PKTBUF20_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */ +#define _FRC_PKTBUF5_PKTBUF21_SHIFT 8 /**< Shift value for FRC_PKTBUF21 */ +#define _FRC_PKTBUF5_PKTBUF21_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF21 */ +#define _FRC_PKTBUF5_PKTBUF21_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */ +#define FRC_PKTBUF5_PKTBUF21_DEFAULT (_FRC_PKTBUF5_PKTBUF21_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */ +#define _FRC_PKTBUF5_PKTBUF22_SHIFT 16 /**< Shift value for FRC_PKTBUF22 */ +#define _FRC_PKTBUF5_PKTBUF22_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF22 */ +#define _FRC_PKTBUF5_PKTBUF22_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */ +#define FRC_PKTBUF5_PKTBUF22_DEFAULT (_FRC_PKTBUF5_PKTBUF22_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */ +#define _FRC_PKTBUF5_PKTBUF23_SHIFT 24 /**< Shift value for FRC_PKTBUF23 */ +#define _FRC_PKTBUF5_PKTBUF23_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF23 */ +#define _FRC_PKTBUF5_PKTBUF23_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */ +#define FRC_PKTBUF5_PKTBUF23_DEFAULT (_FRC_PKTBUF5_PKTBUF23_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */ + +/* Bit fields for FRC PKTBUF6 */ +#define _FRC_PKTBUF6_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF6 */ +#define _FRC_PKTBUF6_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF6 */ +#define _FRC_PKTBUF6_PKTBUF24_SHIFT 0 /**< Shift value for FRC_PKTBUF24 */ +#define _FRC_PKTBUF6_PKTBUF24_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF24 */ +#define _FRC_PKTBUF6_PKTBUF24_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */ +#define FRC_PKTBUF6_PKTBUF24_DEFAULT (_FRC_PKTBUF6_PKTBUF24_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */ +#define _FRC_PKTBUF6_PKTBUF25_SHIFT 8 /**< Shift value for FRC_PKTBUF25 */ +#define _FRC_PKTBUF6_PKTBUF25_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF25 */ +#define _FRC_PKTBUF6_PKTBUF25_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */ +#define FRC_PKTBUF6_PKTBUF25_DEFAULT (_FRC_PKTBUF6_PKTBUF25_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */ +#define _FRC_PKTBUF6_PKTBUF26_SHIFT 16 /**< Shift value for FRC_PKTBUF26 */ +#define _FRC_PKTBUF6_PKTBUF26_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF26 */ +#define _FRC_PKTBUF6_PKTBUF26_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */ +#define FRC_PKTBUF6_PKTBUF26_DEFAULT (_FRC_PKTBUF6_PKTBUF26_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */ +#define _FRC_PKTBUF6_PKTBUF27_SHIFT 24 /**< Shift value for FRC_PKTBUF27 */ +#define _FRC_PKTBUF6_PKTBUF27_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF27 */ +#define _FRC_PKTBUF6_PKTBUF27_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */ +#define FRC_PKTBUF6_PKTBUF27_DEFAULT (_FRC_PKTBUF6_PKTBUF27_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */ + +/* Bit fields for FRC PKTBUF7 */ +#define _FRC_PKTBUF7_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF7 */ +#define _FRC_PKTBUF7_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF7 */ +#define _FRC_PKTBUF7_PKTBUF28_SHIFT 0 /**< Shift value for FRC_PKTBUF28 */ +#define _FRC_PKTBUF7_PKTBUF28_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF28 */ +#define _FRC_PKTBUF7_PKTBUF28_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */ +#define FRC_PKTBUF7_PKTBUF28_DEFAULT (_FRC_PKTBUF7_PKTBUF28_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */ +#define _FRC_PKTBUF7_PKTBUF29_SHIFT 8 /**< Shift value for FRC_PKTBUF29 */ +#define _FRC_PKTBUF7_PKTBUF29_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF29 */ +#define _FRC_PKTBUF7_PKTBUF29_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */ +#define FRC_PKTBUF7_PKTBUF29_DEFAULT (_FRC_PKTBUF7_PKTBUF29_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */ +#define _FRC_PKTBUF7_PKTBUF30_SHIFT 16 /**< Shift value for FRC_PKTBUF30 */ +#define _FRC_PKTBUF7_PKTBUF30_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF30 */ +#define _FRC_PKTBUF7_PKTBUF30_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */ +#define FRC_PKTBUF7_PKTBUF30_DEFAULT (_FRC_PKTBUF7_PKTBUF30_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */ +#define _FRC_PKTBUF7_PKTBUF31_SHIFT 24 /**< Shift value for FRC_PKTBUF31 */ +#define _FRC_PKTBUF7_PKTBUF31_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF31 */ +#define _FRC_PKTBUF7_PKTBUF31_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */ +#define FRC_PKTBUF7_PKTBUF31_DEFAULT (_FRC_PKTBUF7_PKTBUF31_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */ + +/* Bit fields for FRC PKTBUF8 */ +#define _FRC_PKTBUF8_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF8 */ +#define _FRC_PKTBUF8_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF8 */ +#define _FRC_PKTBUF8_PKTBUF32_SHIFT 0 /**< Shift value for FRC_PKTBUF32 */ +#define _FRC_PKTBUF8_PKTBUF32_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF32 */ +#define _FRC_PKTBUF8_PKTBUF32_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */ +#define FRC_PKTBUF8_PKTBUF32_DEFAULT (_FRC_PKTBUF8_PKTBUF32_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */ +#define _FRC_PKTBUF8_PKTBUF33_SHIFT 8 /**< Shift value for FRC_PKTBUF33 */ +#define _FRC_PKTBUF8_PKTBUF33_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF33 */ +#define _FRC_PKTBUF8_PKTBUF33_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */ +#define FRC_PKTBUF8_PKTBUF33_DEFAULT (_FRC_PKTBUF8_PKTBUF33_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */ +#define _FRC_PKTBUF8_PKTBUF34_SHIFT 16 /**< Shift value for FRC_PKTBUF34 */ +#define _FRC_PKTBUF8_PKTBUF34_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF34 */ +#define _FRC_PKTBUF8_PKTBUF34_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */ +#define FRC_PKTBUF8_PKTBUF34_DEFAULT (_FRC_PKTBUF8_PKTBUF34_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */ +#define _FRC_PKTBUF8_PKTBUF35_SHIFT 24 /**< Shift value for FRC_PKTBUF35 */ +#define _FRC_PKTBUF8_PKTBUF35_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF35 */ +#define _FRC_PKTBUF8_PKTBUF35_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */ +#define FRC_PKTBUF8_PKTBUF35_DEFAULT (_FRC_PKTBUF8_PKTBUF35_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */ + +/* Bit fields for FRC PKTBUF9 */ +#define _FRC_PKTBUF9_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF9 */ +#define _FRC_PKTBUF9_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF9 */ +#define _FRC_PKTBUF9_PKTBUF36_SHIFT 0 /**< Shift value for FRC_PKTBUF36 */ +#define _FRC_PKTBUF9_PKTBUF36_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF36 */ +#define _FRC_PKTBUF9_PKTBUF36_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */ +#define FRC_PKTBUF9_PKTBUF36_DEFAULT (_FRC_PKTBUF9_PKTBUF36_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */ +#define _FRC_PKTBUF9_PKTBUF37_SHIFT 8 /**< Shift value for FRC_PKTBUF37 */ +#define _FRC_PKTBUF9_PKTBUF37_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF37 */ +#define _FRC_PKTBUF9_PKTBUF37_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */ +#define FRC_PKTBUF9_PKTBUF37_DEFAULT (_FRC_PKTBUF9_PKTBUF37_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */ +#define _FRC_PKTBUF9_PKTBUF38_SHIFT 16 /**< Shift value for FRC_PKTBUF38 */ +#define _FRC_PKTBUF9_PKTBUF38_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF38 */ +#define _FRC_PKTBUF9_PKTBUF38_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */ +#define FRC_PKTBUF9_PKTBUF38_DEFAULT (_FRC_PKTBUF9_PKTBUF38_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */ +#define _FRC_PKTBUF9_PKTBUF39_SHIFT 24 /**< Shift value for FRC_PKTBUF39 */ +#define _FRC_PKTBUF9_PKTBUF39_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF39 */ +#define _FRC_PKTBUF9_PKTBUF39_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */ +#define FRC_PKTBUF9_PKTBUF39_DEFAULT (_FRC_PKTBUF9_PKTBUF39_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */ + +/* Bit fields for FRC PKTBUF10 */ +#define _FRC_PKTBUF10_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF10 */ +#define _FRC_PKTBUF10_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF10 */ +#define _FRC_PKTBUF10_PKTBUF40_SHIFT 0 /**< Shift value for FRC_PKTBUF40 */ +#define _FRC_PKTBUF10_PKTBUF40_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF40 */ +#define _FRC_PKTBUF10_PKTBUF40_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */ +#define FRC_PKTBUF10_PKTBUF40_DEFAULT (_FRC_PKTBUF10_PKTBUF40_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */ +#define _FRC_PKTBUF10_PKTBUF41_SHIFT 8 /**< Shift value for FRC_PKTBUF41 */ +#define _FRC_PKTBUF10_PKTBUF41_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF41 */ +#define _FRC_PKTBUF10_PKTBUF41_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */ +#define FRC_PKTBUF10_PKTBUF41_DEFAULT (_FRC_PKTBUF10_PKTBUF41_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */ +#define _FRC_PKTBUF10_PKTBUF42_SHIFT 16 /**< Shift value for FRC_PKTBUF42 */ +#define _FRC_PKTBUF10_PKTBUF42_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF42 */ +#define _FRC_PKTBUF10_PKTBUF42_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */ +#define FRC_PKTBUF10_PKTBUF42_DEFAULT (_FRC_PKTBUF10_PKTBUF42_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */ +#define _FRC_PKTBUF10_PKTBUF43_SHIFT 24 /**< Shift value for FRC_PKTBUF43 */ +#define _FRC_PKTBUF10_PKTBUF43_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF43 */ +#define _FRC_PKTBUF10_PKTBUF43_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */ +#define FRC_PKTBUF10_PKTBUF43_DEFAULT (_FRC_PKTBUF10_PKTBUF43_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */ + +/* Bit fields for FRC PKTBUF11 */ +#define _FRC_PKTBUF11_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF11 */ +#define _FRC_PKTBUF11_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF11 */ +#define _FRC_PKTBUF11_PKTBUF44_SHIFT 0 /**< Shift value for FRC_PKTBUF44 */ +#define _FRC_PKTBUF11_PKTBUF44_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF44 */ +#define _FRC_PKTBUF11_PKTBUF44_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */ +#define FRC_PKTBUF11_PKTBUF44_DEFAULT (_FRC_PKTBUF11_PKTBUF44_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */ +#define _FRC_PKTBUF11_PKTBUF45_SHIFT 8 /**< Shift value for FRC_PKTBUF45 */ +#define _FRC_PKTBUF11_PKTBUF45_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF45 */ +#define _FRC_PKTBUF11_PKTBUF45_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */ +#define FRC_PKTBUF11_PKTBUF45_DEFAULT (_FRC_PKTBUF11_PKTBUF45_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */ +#define _FRC_PKTBUF11_PKTBUF46_SHIFT 16 /**< Shift value for FRC_PKTBUF46 */ +#define _FRC_PKTBUF11_PKTBUF46_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF46 */ +#define _FRC_PKTBUF11_PKTBUF46_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */ +#define FRC_PKTBUF11_PKTBUF46_DEFAULT (_FRC_PKTBUF11_PKTBUF46_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */ +#define _FRC_PKTBUF11_PKTBUF47_SHIFT 24 /**< Shift value for FRC_PKTBUF47 */ +#define _FRC_PKTBUF11_PKTBUF47_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF47 */ +#define _FRC_PKTBUF11_PKTBUF47_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */ +#define FRC_PKTBUF11_PKTBUF47_DEFAULT (_FRC_PKTBUF11_PKTBUF47_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */ + +/* Bit fields for FRC FCD */ +#define _FRC_FCD_RESETVALUE 0x000000FFUL /**< Default value for FRC_FCD */ +#define _FRC_FCD_MASK 0x0001FFFFUL /**< Mask for FRC_FCD */ +#define _FRC_FCD_WORDS_SHIFT 0 /**< Shift value for FRC_WORDS */ +#define _FRC_FCD_WORDS_MASK 0xFFUL /**< Bit mask for FRC_WORDS */ +#define _FRC_FCD_WORDS_DEFAULT 0x000000FFUL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_WORDS_DEFAULT (_FRC_FCD_WORDS_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_FCD */ +#define _FRC_FCD_BUFFER_SHIFT 8 /**< Shift value for FRC_BUFFER */ +#define _FRC_FCD_BUFFER_MASK 0x300UL /**< Bit mask for FRC_BUFFER */ +#define _FRC_FCD_BUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_BUFFER_DEFAULT (_FRC_FCD_BUFFER_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_FCD */ +#define FRC_FCD_INCLUDECRC (0x1UL << 10) /**< Include CRC */ +#define _FRC_FCD_INCLUDECRC_SHIFT 10 /**< Shift value for FRC_INCLUDECRC */ +#define _FRC_FCD_INCLUDECRC_MASK 0x400UL /**< Bit mask for FRC_INCLUDECRC */ +#define _FRC_FCD_INCLUDECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_INCLUDECRC_DEFAULT (_FRC_FCD_INCLUDECRC_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_FCD */ +#define FRC_FCD_CALCCRC (0x1UL << 11) /**< Calculate CRC */ +#define _FRC_FCD_CALCCRC_SHIFT 11 /**< Shift value for FRC_CALCCRC */ +#define _FRC_FCD_CALCCRC_MASK 0x800UL /**< Bit mask for FRC_CALCCRC */ +#define _FRC_FCD_CALCCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_CALCCRC_DEFAULT (_FRC_FCD_CALCCRC_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_FCD */ +#define _FRC_FCD_SKIPCRC_SHIFT 12 /**< Shift value for FRC_SKIPCRC */ +#define _FRC_FCD_SKIPCRC_MASK 0x3000UL /**< Bit mask for FRC_SKIPCRC */ +#define _FRC_FCD_SKIPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_SKIPCRC_DEFAULT (_FRC_FCD_SKIPCRC_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_FCD */ +#define FRC_FCD_SKIPWHITE (0x1UL << 14) /**< Skip data whitening in this subframe */ +#define _FRC_FCD_SKIPWHITE_SHIFT 14 /**< Shift value for FRC_SKIPWHITE */ +#define _FRC_FCD_SKIPWHITE_MASK 0x4000UL /**< Bit mask for FRC_SKIPWHITE */ +#define _FRC_FCD_SKIPWHITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_SKIPWHITE_DEFAULT (_FRC_FCD_SKIPWHITE_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_FCD */ +#define FRC_FCD_ADDTRAILTXDATA (0x1UL << 15) /**< Add trailing TX data in this subframe */ +#define _FRC_FCD_ADDTRAILTXDATA_SHIFT 15 /**< Shift value for FRC_ADDTRAILTXDATA */ +#define _FRC_FCD_ADDTRAILTXDATA_MASK 0x8000UL /**< Bit mask for FRC_ADDTRAILTXDATA */ +#define _FRC_FCD_ADDTRAILTXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_ADDTRAILTXDATA_DEFAULT (_FRC_FCD_ADDTRAILTXDATA_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_FCD */ +#define FRC_FCD_EXCLUDESUBFRAMEWCNT (0x1UL << 16) /**< Exclude subframe from WCNT */ +#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_SHIFT 16 /**< Shift value for FRC_EXCLUDESUBFRAMEWCNT */ +#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_MASK 0x10000UL /**< Bit mask for FRC_EXCLUDESUBFRAMEWCNT */ +#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */ +#define FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT (_FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_FCD */ + +/* Bit fields for FRC INTELEMENT */ +#define _FRC_INTELEMENT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTELEMENT */ +#define _FRC_INTELEMENT_MASK 0x000000FFUL /**< Mask for FRC_INTELEMENT */ +#define _FRC_INTELEMENT_INTELEMENT_SHIFT 0 /**< Shift value for FRC_INTELEMENT */ +#define _FRC_INTELEMENT_INTELEMENT_MASK 0xFFUL /**< Bit mask for FRC_INTELEMENT */ +#define _FRC_INTELEMENT_INTELEMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTELEMENT */ +#define FRC_INTELEMENT_INTELEMENT_DEFAULT (_FRC_INTELEMENT_INTELEMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTELEMENT */ + +/* Bit fields for FRC AHBCONFIG */ +#define _FRC_AHBCONFIG_RESETVALUE 0x00000001UL /**< Default value for FRC_AHBCONFIG */ +#define _FRC_AHBCONFIG_MASK 0x00000001UL /**< Mask for FRC_AHBCONFIG */ +#define FRC_AHBCONFIG_AHBHPROTBUFFERABLE (0x1UL << 0) /**< Bufferable Privileged data for AHB */ +#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_SHIFT 0 /**< Shift value for FRC_AHBHPROTBUFFERABLE */ +#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_MASK 0x1UL /**< Bit mask for FRC_AHBHPROTBUFFERABLE */ +#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_AHBCONFIG */ +#define FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT (_FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AHBCONFIG */ + +/** @} End of group EFR32MG24_FRC_BitFields */ +/** @} End of group EFR32MG24_FRC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_FRC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_fsrco.h b/EFR32MG24/Device/Include/efr32mg24_fsrco.h new file mode 100644 index 0000000..a12fda1 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_fsrco.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_FSRCO_H +#define EFR32MG24_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_FSRCO FSRCO + * @{ + * @brief EFR32MG24 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32MG24_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_FSRCO + * @{ + * @defgroup EFR32MG24_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32MG24_FSRCO_BitFields */ +/** @} End of group EFR32MG24_FSRCO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_FSRCO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_gpcrc.h b/EFR32MG24/Device/Include/efr32mg24_gpcrc.h new file mode 100644 index 0000000..0768909 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_gpcrc.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_GPCRC_H +#define EFR32MG24_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_GPCRC GPCRC + * @{ + * @brief EFR32MG24 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32MG24_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_GPCRC + * @{ + * @defgroup EFR32MG24_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32MG24_GPCRC_BitFields */ +/** @} End of group EFR32MG24_GPCRC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_GPCRC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_gpio.h b/EFR32MG24/Device/Include/efr32mg24_gpio.h new file mode 100644 index 0000000..3ffb7d5 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_gpio.h @@ -0,0 +1,2632 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_GPIO_H +#define EFR32MG24_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32mg24_gpio_port.h" + +typedef struct { + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_KEYSCANROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_PCNTROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t ASYNCH12ROUTE; /**< ASYNCH12 port/pin select */ + __IOM uint32_t ASYNCH13ROUTE; /**< ASYNCH13 port/pin select */ + __IOM uint32_t ASYNCH14ROUTE; /**< ASYNCH14 port/pin select */ + __IOM uint32_t ASYNCH15ROUTE; /**< ASYNCH15 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< RAC pin enable */ + __IOM uint32_t LNAENROUTE; /**< LNAEN port/pin select */ + __IOM uint32_t PAENROUTE; /**< PAEN port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_RACROUTE_TypeDef; + +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_SYXOROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct { + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE; /**< rac DBUS config registers */ + uint32_t RESERVED10[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED11[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED12[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED13[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED16[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED17[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_SET; /**< rac DBUS config registers */ + uint32_t RESERVED22[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED23[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED24[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED25[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED28[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_CLR; /**< rac DBUS config registers */ + uint32_t RESERVED34[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED35[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED36[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED37[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED38[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED39[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED40[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_TGL; /**< rac DBUS config registers */ + uint32_t RESERVED46[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC1CH0 (_GPIO_ABUSALLOC_AODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC1CH1 (_GPIO_ABUSALLOC_AODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC1CH0 (_GPIO_BBUSALLOC_BODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC1CH1 (_GPIO_BBUSALLOC_BODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_KEYSCAN ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PCNT S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ + +/* Bit fields for GPIO_PCNT S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x000FFFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN (0x1UL << 12) /**< ASYNCH12 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_SHIFT 12 /**< Shift value for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_MASK 0x1000UL /**< Bit mask for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN (0x1UL << 13) /**< ASYNCH13 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_SHIFT 13 /**< Shift value for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_MASK 0x2000UL /**< Bit mask for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN (0x1UL << 14) /**< ASYNCH14 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_SHIFT 14 /**< Shift value for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_MASK 0x4000UL /**< Bit mask for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN (0x1UL << 15) /**< ASYNCH15 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_SHIFT 15 /**< Shift value for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_MASK 0x8000UL /**< Bit mask for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 16) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 16 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x10000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 17) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 17 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x20000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 18) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 18 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x40000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 19) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 19 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x80000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_RAC ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN (0x1UL << 0) /**< LNAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_SHIFT 0 /**< Shift value for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_MASK 0x1UL /**< Bit mask for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN (0x1UL << 1) /**< PAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_SHIFT 1 /**< Shift value for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_MASK 0x2UL /**< Bit mask for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ + +/* Bit fields for GPIO_RAC LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PORT_DEFAULT (_GPIO_RAC_LNAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ +#define _GPIO_RAC_LNAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PIN_DEFAULT (_GPIO_RAC_LNAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ + +/* Bit fields for GPIO_RAC PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PORT_DEFAULT (_GPIO_RAC_PAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PIN_DEFAULT (_GPIO_RAC_PAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ + +/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_GPIO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_gpio_port.h b/EFR32MG24/Device/Include/efr32mg24_gpio_port.h new file mode 100644 index 0000000..898d4a1 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_gpio_port.h @@ -0,0 +1,457 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32MG24 GPIO PORT + *****************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x000000FFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000003FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x3FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000003FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x3FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif /* GPIO_PORT_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_hfrco.h b/EFR32MG24/Device/Include/efr32mg24_hfrco.h new file mode 100644 index 0000000..3d6633c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_hfrco.h @@ -0,0 +1,226 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_HFRCO_H +#define EFR32MG24_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_HFRCO HFRCO + * @{ + * @brief EFR32MG24 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32MG24_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_HFRCO + * @{ + * @defgroup EFR32MG24_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32MG24_HFRCO_BitFields */ +/** @} End of group EFR32MG24_HFRCO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_HFRCO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_hfxo.h b/EFR32MG24/Device/Include/efr32mg24_hfxo.h new file mode 100644 index 0000000..7be0282 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_hfxo.h @@ -0,0 +1,801 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_HFXO_H +#define EFR32MG24_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_HFXO HFXO + * @{ + * @brief EFR32MG24 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32MG24_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_HFXO + * @{ + * @defgroup EFR32MG24_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ + +/* Bit fields for HFXO BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ + +/* Bit fields for HFXO BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32MG24_HFXO_BitFields */ +/** @} End of group EFR32MG24_HFXO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_HFXO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_i2c.h b/EFR32MG24/Device/Include/efr32mg24_i2c.h new file mode 100644 index 0000000..2ee8509 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_i2c.h @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_I2C_H +#define EFR32MG24_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_I2C I2C + * @{ + * @brief EFR32MG24 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32MG24_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_I2C + * @{ + * @defgroup EFR32MG24_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32MG24_I2C_BitFields */ +/** @} End of group EFR32MG24_I2C */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_I2C_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_iadc.h b/EFR32MG24/Device/Include/efr32mg24_iadc.h new file mode 100644 index 0000000..2a3c00b --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_iadc.h @@ -0,0 +1,1072 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_IADC_H +#define EFR32MG24_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_IADC IADC + * @{ + * @brief EFR32MG24 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct { + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32MG24_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_IADC + * @{ + * @defgroup EFR32MG24_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define _IADC_CFG_ADCMODE_HIGHSPEED 0x00000001UL /**< Mode HIGHSPEED for IADC_CFG */ +#define _IADC_CFG_ADCMODE_HIGHACCURACY 0x00000002UL /**< Mode HIGHACCURACY for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_HIGHSPEED (_IADC_CFG_ADCMODE_HIGHSPEED << 0) /**< Shifted mode HIGHSPEED for IADC_CFG */ +#define IADC_CFG_ADCMODE_HIGHACCURACY (_IADC_CFG_ADCMODE_HIGHACCURACY << 0) /**< Shifted mode HIGHACCURACY for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_OSRHA_SHIFT 5 /**< Shift value for IADC_OSRHA */ +#define _IADC_CFG_OSRHA_MASK 0xE0UL /**< Bit mask for IADC_OSRHA */ +#define _IADC_CFG_OSRHA_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC16 0x00000000UL /**< Mode HIACC16 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC32 0x00000001UL /**< Mode HIACC32 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC64 0x00000002UL /**< Mode HIACC64 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC92 0x00000003UL /**< Mode HIACC92 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC128 0x00000004UL /**< Mode HIACC128 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC256 0x00000005UL /**< Mode HIACC256 for IADC_CFG */ +#define IADC_CFG_OSRHA_DEFAULT (_IADC_CFG_OSRHA_DEFAULT << 5) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC16 (_IADC_CFG_OSRHA_HIACC16 << 5) /**< Shifted mode HIACC16 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC32 (_IADC_CFG_OSRHA_HIACC32 << 5) /**< Shifted mode HIACC32 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC64 (_IADC_CFG_OSRHA_HIACC64 << 5) /**< Shifted mode HIACC64 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC92 (_IADC_CFG_OSRHA_HIACC92 << 5) /**< Shifted mode HIACC92 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC128 (_IADC_CFG_OSRHA_HIACC128 << 5) /**< Shifted mode HIACC128 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC256 (_IADC_CFG_OSRHA_HIACC256 << 5) /**< Shifted mode HIACC256 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF2P5 0x00000002UL /**< Mode VREF2P5 for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF2P5 (_IADC_CFG_REFSEL_VREF2P5 << 16) /**< Shifted mode VREF2P5 for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32MG24_IADC_BitFields */ +/** @} End of group EFR32MG24_IADC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_IADC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_icache.h b/EFR32MG24/Device/Include/efr32mg24_icache.h new file mode 100644 index 0000000..31902b7 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_icache.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ICACHE_H +#define EFR32MG24_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ICACHE ICACHE + * @{ + * @brief EFR32MG24 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32MG24_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ICACHE + * @{ + * @defgroup EFR32MG24_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32MG24_ICACHE_BitFields */ +/** @} End of group EFR32MG24_ICACHE */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_ICACHE_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_keyscan.h b/EFR32MG24/Device/Include/efr32mg24_keyscan.h new file mode 100644 index 0000000..31f4f58 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_keyscan.h @@ -0,0 +1,386 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 KEYSCAN register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_KEYSCAN_H +#define EFR32MG24_KEYSCAN_H +#define KEYSCAN_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_KEYSCAN KEYSCAN + * @{ + * @brief EFR32MG24 KEYSCAN Register Declaration. + *****************************************************************************/ + +/** KEYSCAN Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +} KEYSCAN_TypeDef; +/** @} End of group EFR32MG24_KEYSCAN */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_KEYSCAN + * @{ + * @defgroup EFR32MG24_KEYSCAN_BitFields KEYSCAN Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for KEYSCAN IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ + +/* Bit fields for KEYSCAN EN */ +#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */ +#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */ +#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */ +#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */ + +/* Bit fields for KEYSCAN SWRST */ +#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ + +/* Bit fields for KEYSCAN CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ + +/* Bit fields for KEYSCAN CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ + +/* Bit fields for KEYSCAN DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ + +/* Bit fields for KEYSCAN STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ + +/* Bit fields for KEYSCAN IF */ +#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */ +#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */ +#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */ +#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */ +#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */ + +/* Bit fields for KEYSCAN IEN */ +#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */ +#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */ +#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */ +#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */ +#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ + +/** @} End of group EFR32MG24_KEYSCAN_BitFields */ +/** @} End of group EFR32MG24_KEYSCAN */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_KEYSCAN_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_ldma.h b/EFR32MG24/Device/Include/efr32mg24_ldma.h new file mode 100644 index 0000000..0266244 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_ldma.h @@ -0,0 +1,685 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LDMA_H +#define EFR32MG24_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LDMA LDMA + * @{ + * @brief EFR32MG24 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32MG24_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LDMA + * @{ + * @defgroup EFR32MG24_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x1F100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32MG24_LDMA_BitFields */ +/** @} End of group EFR32MG24_LDMA */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_LDMA_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_ldmaxbar.h b/EFR32MG24/Device/Include/efr32mg24_ldmaxbar.h new file mode 100644 index 0000000..9597832 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_ldmaxbar.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LDMAXBAR_H +#define EFR32MG24_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32MG24 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32MG24_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LDMAXBAR + * @{ + * @defgroup EFR32MG24_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32MG24_LDMAXBAR_BitFields */ +/** @} End of group EFR32MG24_LDMAXBAR */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_LDMAXBAR_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_ldmaxbar_defines.h b/EFR32MG24/Device/Include/efr32mg24_ldmaxbar_defines.h new file mode 100644 index 0000000..ac0960e --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_ldmaxbar_defines.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +/* Module source selection indices */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x0000000fUL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000010UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x00000011UL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 0x00000012UL /**< Mode VDAC1 for LDMAXBAR_CH_REQSEL */ + +/* Shifted source selection indices */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 << 16) /**< Shifted Mode VDAC1 for LDMAXBAR_CH_REQSEL */ + +/* Module signal selection indices */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ 0x00000000UL /** Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ 0x00000001UL /** Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +/* Shifted Module signal selection indices */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ diff --git a/EFR32MG24/Device/Include/efr32mg24_letimer.h b/EFR32MG24/Device/Include/efr32mg24_letimer.h new file mode 100644 index 0000000..7439682 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_letimer.h @@ -0,0 +1,534 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LETIMER_H +#define EFR32MG24_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LETIMER LETIMER + * @{ + * @brief EFR32MG24 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32MG24_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LETIMER + * @{ + * @defgroup EFR32MG24_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32MG24_LETIMER_BitFields */ +/** @} End of group EFR32MG24_LETIMER */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_LETIMER_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_lfrco.h b/EFR32MG24/Device/Include/efr32mg24_lfrco.h new file mode 100644 index 0000000..a8c058e --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_lfrco.h @@ -0,0 +1,304 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LFRCO_H +#define EFR32MG24_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LFRCO LFRCO + * @{ + * @brief EFR32MG24 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32MG24_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LFRCO + * @{ + * @defgroup EFR32MG24_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group EFR32MG24_LFRCO_BitFields */ +/** @} End of group EFR32MG24_LFRCO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_LFRCO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_lfxo.h b/EFR32MG24/Device/Include/efr32mg24_lfxo.h new file mode 100644 index 0000000..cda75b1 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_lfxo.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LFXO_H +#define EFR32MG24_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LFXO LFXO + * @{ + * @brief EFR32MG24 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32MG24_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LFXO + * @{ + * @defgroup EFR32MG24_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32MG24_LFXO_BitFields */ +/** @} End of group EFR32MG24_LFXO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_LFXO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_mailbox.h b/EFR32MG24/Device/Include/efr32mg24_mailbox.h new file mode 100644 index 0000000..0ff92ea --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_mailbox.h @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 MAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MAILBOX_H +#define EFR32MG24_MAILBOX_H +#define MAILBOX_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MAILBOX MAILBOX + * @{ + * @brief EFR32MG24 MAILBOX Register Declaration. + *****************************************************************************/ + +/** MAILBOX MSGPTRS Register Group Declaration. */ +typedef struct { + __IOM uint32_t MSGPTR; /**< Message Pointer */ +} MAILBOX_MSGPTRS_TypeDef; + +/** MAILBOX Register Declaration. */ +typedef struct { + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +} MAILBOX_TypeDef; +/** @} End of group EFR32MG24_MAILBOX */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MAILBOX + * @{ + * @defgroup EFR32MG24_MAILBOX_BitFields MAILBOX Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MAILBOX MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ + +/* Bit fields for MAILBOX IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ + +/* Bit fields for MAILBOX IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ + +/** @} End of group EFR32MG24_MAILBOX_BitFields */ +/** @} End of group EFR32MG24_MAILBOX */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_MAILBOX_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_modem.h b/EFR32MG24/Device/Include/efr32mg24_modem.h new file mode 100644 index 0000000..5992721 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_modem.h @@ -0,0 +1,6657 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 MODEM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MODEM_H +#define EFR32MG24_MODEM_H +#define MODEM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MODEM MODEM + * @{ + * @brief EFR32MG24 MODEM Register Declaration. + *****************************************************************************/ + +/** MODEM IRCALCOEFWR Register Group Declaration. */ +typedef struct { + __IOM uint32_t IRCALCOEFWR; /**< IRCAL COEF WR per antenna */ +} MODEM_IRCALCOEFWR_TypeDef; + +/** MODEM Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t STATUS2; /**< Status Register 2 */ + __IM uint32_t STATUS3; /**< Status Register 3 */ + __IM uint32_t STATUS4; /**< ANT DIV RSSI Status */ + __IM uint32_t STATUS5; /**< Collision restart status */ + __IM uint32_t STATUS6; /**< ANT DIV Correlation Status */ + __IM uint32_t STATUS7; /**< PHASE Demod Status */ + __IM uint32_t TIMDETSTATUS; /**< Timing Detection Status Register */ + __IM uint32_t FSMSTATUS; /**< Demod FSM Status Register */ + __IM uint32_t FREQOFFEST; /**< Frequency Offset Estimate */ + __IOM uint32_t AFCADJRX; /**< AFC Adjustment RX */ + __IOM uint32_t AFCADJTX; /**< AFC Adjustment TX */ + __IOM uint32_t MIXCTRL; /**< Analog mixer control */ + __IOM uint32_t CTRL0; /**< Control Register 0 */ + __IOM uint32_t CTRL1; /**< Control Register 1 */ + __IOM uint32_t CTRL2; /**< Control Register 2 */ + __IOM uint32_t CTRL3; /**< Control Register 3 */ + __IOM uint32_t CTRL4; /**< Control Register 4 */ + __IOM uint32_t CTRL5; /**< Control Register 5 */ + __IOM uint32_t CTRL6; /**< Control Register 6 */ + __IOM uint32_t TXBR; /**< Transmit baudrate */ + __IOM uint32_t RXBR; /**< Receive Baudrate */ + __IOM uint32_t CF; /**< Channel Filter */ + __IOM uint32_t PRE; /**< Preamble Register */ + __IOM uint32_t SYNC0; /**< Sync word 0 */ + __IOM uint32_t SYNC1; /**< Sync word 1 */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t DSSS0; /**< DSSS symbol 0 Register */ + __IOM uint32_t MODINDEX; /**< Modulation Index */ + __IOM uint32_t AFC; /**< Automatic Frequency Control */ + __IOM uint32_t AFCADJLIM; /**< AFC Adjustment Limit */ + __IOM uint32_t SHAPING0; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING1; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING2; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING3; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING4; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING5; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING6; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING7; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING8; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING9; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING10; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING11; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING12; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING13; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING14; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING15; /**< Shaping Coefficients */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t RAMPCTRL; /**< Ramping Register */ + __IOM uint32_t RAMPLEV; /**< Ramping Register */ + __IOM uint32_t ANARAMPCTRL; /**< Analog Ramping Control */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + __IOM uint32_t DCCOMP; /**< DC Offset Compensation Filter Settings */ + __IOM uint32_t DCCOMPFILTINIT; /**< DC Offset compensation Filter */ + __IM uint32_t DCESTI; /**< DC Offset Estimated value */ + __IOM uint32_t SRCCHF; /**< SRC ratio values and channel filter */ + __IOM uint32_t INTAFC; /**< Internal AFC */ + __IOM uint32_t DSATHD0; /**< DSA detector threshold-0 */ + __IOM uint32_t DSATHD1; /**< DSA detector threshold-1 */ + __IOM uint32_t DSATHD2; /**< DSA detector threshold-2 */ + __IOM uint32_t DSATHD3; /**< DSA detector threshold 3 */ + __IOM uint32_t DSATHD4; /**< DSA detector threshold 4 */ + __IOM uint32_t DSACTRL; /**< DSA mode */ + __IOM uint32_t DIGMIXCTRL; /**< Digital mixer control register */ + __IOM uint32_t VITERBIDEMOD; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG0; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG1; /**< Viterbi demodulator */ + __IOM uint32_t VTTRACK; /**< Viterbi demodulator tracking loop */ + __IOM uint32_t VTBLETIMING; /**< Viterbi BLE timing stamp control */ + __IM uint32_t BREST; /**< Baudrate Estimate */ + __IOM uint32_t AUTOCG; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP; /**< Automatic clock gating */ + __IM uint32_t POE; /**< Phase Offset Estimate */ + __IOM uint32_t DIRECTMODE; /**< Direct Mode Control */ + __IOM uint32_t LONGRANGE; /**< BLE Long Range */ + __IOM uint32_t LONGRANGE1; /**< BLE Long Range Set1 */ + __IOM uint32_t LONGRANGE2; /**< BLE Long Range Set2 */ + __IOM uint32_t LONGRANGE3; /**< BLE Long Range Set3 */ + __IOM uint32_t LONGRANGE4; /**< BLE Long Range Set4 */ + __IOM uint32_t LONGRANGE5; /**< BLE Long Range Set5 */ + __IOM uint32_t LONGRANGE6; /**< BLE Long Range Set6 */ + __IOM uint32_t LRFRC; /**< BLE Long Range FRC interface */ + __IOM uint32_t COH0; /**< Coherent demodulator control signals */ + __IOM uint32_t COH1; /**< Coherent demodulator control signals */ + __IOM uint32_t COH2; /**< Coherent demodulator control signals */ + __IOM uint32_t COH3; /**< Coherent demodulator control signals */ + __IOM uint32_t CMD; /**< Command register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SYNCPROPERTIES; /**< Sync word properties */ + __IOM uint32_t DIGIGAINCTRL; /**< Digital Gain Control */ + __IOM uint32_t PRSCTRL; /**< Mux control for PRS outputs */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t REALTIMCFE; /**< Real time Cost Function Engine CTRL */ + __IOM uint32_t ETSCTRL; /**< Early Time Stamp Control */ + __IOM uint32_t ETSTIM; /**< Early Time Stamp Timing */ + __IOM uint32_t ANTSWCTRL; /**< Antenna Switch Control */ + __IOM uint32_t ANTSWCTRL1; /**< Antenna Switch Control 1 */ + __IOM uint32_t ANTSWSTART; /**< Antenna Switch Start */ + __IOM uint32_t ANTSWEND; /**< Antenna Switch End */ + __IOM uint32_t TRECPMPATT; /**< TRECS Preamble pattern */ + __IOM uint32_t TRECPMDET; /**< TRECS preamble Detection CTRL */ + __IOM uint32_t TRECSCFG; /**< TRECS configuration */ + __IOM uint32_t CFGANTPATT; /**< Configure Antenna Pattern */ + __IOM uint32_t COCURRMODE; /**< CONCURRENT MODE */ + __IOM uint32_t CHFCOE00; /**< CHF COE. Set0 group0 */ + __IOM uint32_t CHFCOE01; /**< CHF COE. Set0 group1 */ + __IOM uint32_t CHFCOE02; /**< CHF COE. Set0 group2 */ + __IOM uint32_t CHFCOE03; /**< CHF COE. Set0 group3 */ + __IOM uint32_t CHFCOE04; /**< CHF COE. Set0 group4 */ + __IOM uint32_t CHFCOE05; /**< CHF COE. Set0 group5 */ + __IOM uint32_t CHFCOE06; /**< CHF COE. Set0 group6 */ + __IOM uint32_t CHFCOE10; /**< CHF COE. Set1 group0 */ + __IOM uint32_t CHFCOE11; /**< CHF COE. Set1 group1 */ + __IOM uint32_t CHFCOE12; /**< CHF COE. Set1 group2 */ + __IOM uint32_t CHFCOE13; /**< CHF COE. Set1 group3 */ + __IOM uint32_t CHFCOE14; /**< CHF COE. Set1 group4 */ + __IOM uint32_t CHFCOE15; /**< CHF COE. Set1 group5 */ + __IOM uint32_t CHFCOE16; /**< CHF COE. Set1 group6 */ + __IOM uint32_t CHFCTRL; /**< CHF control */ + __IOM uint32_t CHFLATENCYCTRL; /**< CHF Latency Control */ + __IOM uint32_t FRMSCHTIME; /**< FRAM SCH TIME-OUT length */ + __IOM uint32_t PREFILTCOEFF; /**< Preamble Filter Coefficients */ + __IOM uint32_t RXRESTART; /**< Collision restart control */ + __IOM uint32_t SQ; /**< Preamble Sense Mode */ + __IOM uint32_t SQEXT; /**< Preamble Sense Mode EXT */ + __IOM uint32_t SQI; /**< Signal quality indicator */ + __IOM uint32_t ANTDIVCTRL; /**< Antenna Diversity Mode Control Register */ + __IOM uint32_t ANTDIVFW; /**< PHASE DEMOD FW mode */ + __IOM uint32_t PHDMODANTDIV; /**< PHASE DEMOD ANTENNA DIVSERSITY */ + __IOM uint32_t PHANTDECSION; /**< PHASE DEMOD ANT-DIV Decision */ + __IOM uint32_t PHDMODCTRL; /**< PHASE DEMOD CTRL */ + __IOM uint32_t SICTRL0; /**< Signal Identifier CTRL0 */ + __IOM uint32_t SICTRL1; /**< Signal Identifier CTRL1 */ + __IM uint32_t SISTATUS; /**< Signal Identifier Status */ + __IOM uint32_t CFGANTPATTEXT; /**< Configure Antenna Pattern */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SICTRL2; /**< Signal Identifier CTRL2 */ + __IOM uint32_t CHFSWCTRL; /**< Channel Filter Switch Time */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t IRCAL; /**< IRCAL control signals */ + __IM uint32_t IRCALCOEF; /**< IRCAL COEF values */ + MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR[2U]; /**< IRCAL COEFS WR per antenna */ + __IOM uint32_t ADCTRL1; /**< ADCTRL1 */ + __IOM uint32_t ADCTRL2; /**< ADCTRL2 */ + __IM uint32_t ADQUAL0; /**< ADQUAL0 */ + __IM uint32_t ADQUAL1; /**< ADQUAL1 */ + __IM uint32_t ADQUAL2; /**< ADQUAL2 */ + __IM uint32_t ADQUAL3; /**< ADQUAL3 */ + __IOM uint32_t ADQUAL4; /**< ADQUAL4 */ + __IOM uint32_t ADQUAL5; /**< ADQUAL5 */ + __IOM uint32_t ADQUAL6; /**< ADQUAL6 */ + __IOM uint32_t ADQUAL7; /**< ADQUAL7 */ + __IOM uint32_t ADQUAL8; /**< ADQUAL8 */ + __IM uint32_t ADQUAL9; /**< ADQUAL9 */ + __IM uint32_t ADQUAL10; /**< ADQUAL10 */ + __IOM uint32_t ADFSM0; /**< ADFSM0 */ + __IOM uint32_t ADFSM1; /**< ADFSM1 */ + __IOM uint32_t ADFSM2; /**< ADFSM2 */ + __IOM uint32_t ADFSM3; /**< ADFSM3 */ + __IOM uint32_t ADFSM4; /**< ADFSM4 */ + __IOM uint32_t ADFSM5; /**< ADFSM5 */ + __IOM uint32_t ADFSM6; /**< ADFSM6 */ + __IOM uint32_t ADFSM7; /**< ADFSM7 */ + __IOM uint32_t ADFSM8; /**< ADFSM8 */ + __IOM uint32_t ADFSM9; /**< ADFSM9 */ + __IOM uint32_t ADFSM10; /**< ADFSM10 */ + __IOM uint32_t ADFSM11; /**< ADFSM11 */ + __IOM uint32_t ADFSM12; /**< ADFSM12 */ + __IOM uint32_t ADFSM13; /**< ADFSM13 */ + __IOM uint32_t ADFSM14; /**< ADFSM14 */ + __IOM uint32_t ADFSM15; /**< ADFSM15 */ + __IOM uint32_t ADFSM16; /**< ADFSM16 */ + __IOM uint32_t ADFSM17; /**< ADFSM17 */ + __IOM uint32_t ADFSM18; /**< ADFSM18 */ + __IOM uint32_t ADFSM19; /**< ADFSM19 */ + __IOM uint32_t ADFSM20; /**< ADFSM20 */ + __IOM uint32_t ADFSM21; /**< ADFSM21 */ + __IM uint32_t ADFSM22; /**< ADFSM22 */ + __IOM uint32_t ADFSM23; /**< ADFSM23 */ + __IOM uint32_t ADFSM24; /**< ADFSM24 */ + __IOM uint32_t ADFSM25; /**< ADFSM25 */ + __IOM uint32_t ADFSM26; /**< ADFSM26 */ + __IOM uint32_t ADFSM27; /**< ADFSM27 */ + __IOM uint32_t ADFSM28; /**< ADFSM28 */ + __IOM uint32_t ADFSM29; /**< ADFSM29 */ + __IOM uint32_t ADFSM30; /**< ADFSM30 */ + __IOM uint32_t ADPC1; /**< ADPC1 */ + __IOM uint32_t ADPC2; /**< ADPC2 */ + __IOM uint32_t ADPC3; /**< ADPC3 */ + __IOM uint32_t ADPC4; /**< ADPC4 */ + __IOM uint32_t ADPC5; /**< ADPC5 */ + __IOM uint32_t ADPC6; /**< ADPC6 */ + __IOM uint32_t ADPC7; /**< ADPC7 */ + __IOM uint32_t ADPC8; /**< ADPC8 */ + __IOM uint32_t ADPC9; /**< ADPC9 */ + __IOM uint32_t ADPC10; /**< ADPC10 */ + uint32_t RESERVED6[6U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[15U]; /**< Reserved for future use */ + __IOM uint32_t HADMCTRL0; /**< HADM Control */ + __IOM uint32_t HADMCTRL1; /**< HADM Control 1 */ + __IM uint32_t HADMSTATUS0; /**< HADM Status */ + __IM uint32_t HADMSTATUS1; /**< HADM Status 1 */ + __IM uint32_t HADMSTATUS2; /**< HADM Status 2 */ + __IM uint32_t HADMSTATUS3; /**< HADM Status 3 */ + __IM uint32_t HADMSTATUS4; /**< HADM Status 4 */ + __IM uint32_t HADMSTATUS5; /**< HADM Status 5 */ + __IM uint32_t HADMSTATUS6; /**< HADM Status 6 */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t SRC2NCOCTRL; /**< SRC2 NCO CTRL */ + uint32_t RESERVED10[7U]; /**< Reserved for future use */ + __IOM uint32_t SPARE; /**< Spare register */ + uint32_t RESERVED11[767U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t STATUS2_SET; /**< Status Register 2 */ + __IM uint32_t STATUS3_SET; /**< Status Register 3 */ + __IM uint32_t STATUS4_SET; /**< ANT DIV RSSI Status */ + __IM uint32_t STATUS5_SET; /**< Collision restart status */ + __IM uint32_t STATUS6_SET; /**< ANT DIV Correlation Status */ + __IM uint32_t STATUS7_SET; /**< PHASE Demod Status */ + __IM uint32_t TIMDETSTATUS_SET; /**< Timing Detection Status Register */ + __IM uint32_t FSMSTATUS_SET; /**< Demod FSM Status Register */ + __IM uint32_t FREQOFFEST_SET; /**< Frequency Offset Estimate */ + __IOM uint32_t AFCADJRX_SET; /**< AFC Adjustment RX */ + __IOM uint32_t AFCADJTX_SET; /**< AFC Adjustment TX */ + __IOM uint32_t MIXCTRL_SET; /**< Analog mixer control */ + __IOM uint32_t CTRL0_SET; /**< Control Register 0 */ + __IOM uint32_t CTRL1_SET; /**< Control Register 1 */ + __IOM uint32_t CTRL2_SET; /**< Control Register 2 */ + __IOM uint32_t CTRL3_SET; /**< Control Register 3 */ + __IOM uint32_t CTRL4_SET; /**< Control Register 4 */ + __IOM uint32_t CTRL5_SET; /**< Control Register 5 */ + __IOM uint32_t CTRL6_SET; /**< Control Register 6 */ + __IOM uint32_t TXBR_SET; /**< Transmit baudrate */ + __IOM uint32_t RXBR_SET; /**< Receive Baudrate */ + __IOM uint32_t CF_SET; /**< Channel Filter */ + __IOM uint32_t PRE_SET; /**< Preamble Register */ + __IOM uint32_t SYNC0_SET; /**< Sync word 0 */ + __IOM uint32_t SYNC1_SET; /**< Sync word 1 */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t DSSS0_SET; /**< DSSS symbol 0 Register */ + __IOM uint32_t MODINDEX_SET; /**< Modulation Index */ + __IOM uint32_t AFC_SET; /**< Automatic Frequency Control */ + __IOM uint32_t AFCADJLIM_SET; /**< AFC Adjustment Limit */ + __IOM uint32_t SHAPING0_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING1_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING2_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING3_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING4_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING5_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING6_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING7_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING8_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING9_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING10_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING11_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING12_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING13_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING14_SET; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING15_SET; /**< Shaping Coefficients */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t RAMPCTRL_SET; /**< Ramping Register */ + __IOM uint32_t RAMPLEV_SET; /**< Ramping Register */ + __IOM uint32_t ANARAMPCTRL_SET; /**< Analog Ramping Control */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + __IOM uint32_t DCCOMP_SET; /**< DC Offset Compensation Filter Settings */ + __IOM uint32_t DCCOMPFILTINIT_SET; /**< DC Offset compensation Filter */ + __IM uint32_t DCESTI_SET; /**< DC Offset Estimated value */ + __IOM uint32_t SRCCHF_SET; /**< SRC ratio values and channel filter */ + __IOM uint32_t INTAFC_SET; /**< Internal AFC */ + __IOM uint32_t DSATHD0_SET; /**< DSA detector threshold-0 */ + __IOM uint32_t DSATHD1_SET; /**< DSA detector threshold-1 */ + __IOM uint32_t DSATHD2_SET; /**< DSA detector threshold-2 */ + __IOM uint32_t DSATHD3_SET; /**< DSA detector threshold 3 */ + __IOM uint32_t DSATHD4_SET; /**< DSA detector threshold 4 */ + __IOM uint32_t DSACTRL_SET; /**< DSA mode */ + __IOM uint32_t DIGMIXCTRL_SET; /**< Digital mixer control register */ + __IOM uint32_t VITERBIDEMOD_SET; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG0_SET; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG1_SET; /**< Viterbi demodulator */ + __IOM uint32_t VTTRACK_SET; /**< Viterbi demodulator tracking loop */ + __IOM uint32_t VTBLETIMING_SET; /**< Viterbi BLE timing stamp control */ + __IM uint32_t BREST_SET; /**< Baudrate Estimate */ + __IOM uint32_t AUTOCG_SET; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_SET; /**< Automatic clock gating */ + __IM uint32_t POE_SET; /**< Phase Offset Estimate */ + __IOM uint32_t DIRECTMODE_SET; /**< Direct Mode Control */ + __IOM uint32_t LONGRANGE_SET; /**< BLE Long Range */ + __IOM uint32_t LONGRANGE1_SET; /**< BLE Long Range Set1 */ + __IOM uint32_t LONGRANGE2_SET; /**< BLE Long Range Set2 */ + __IOM uint32_t LONGRANGE3_SET; /**< BLE Long Range Set3 */ + __IOM uint32_t LONGRANGE4_SET; /**< BLE Long Range Set4 */ + __IOM uint32_t LONGRANGE5_SET; /**< BLE Long Range Set5 */ + __IOM uint32_t LONGRANGE6_SET; /**< BLE Long Range Set6 */ + __IOM uint32_t LRFRC_SET; /**< BLE Long Range FRC interface */ + __IOM uint32_t COH0_SET; /**< Coherent demodulator control signals */ + __IOM uint32_t COH1_SET; /**< Coherent demodulator control signals */ + __IOM uint32_t COH2_SET; /**< Coherent demodulator control signals */ + __IOM uint32_t COH3_SET; /**< Coherent demodulator control signals */ + __IOM uint32_t CMD_SET; /**< Command register */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t SYNCPROPERTIES_SET; /**< Sync word properties */ + __IOM uint32_t DIGIGAINCTRL_SET; /**< Digital Gain Control */ + __IOM uint32_t PRSCTRL_SET; /**< Mux control for PRS outputs */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t REALTIMCFE_SET; /**< Real time Cost Function Engine CTRL */ + __IOM uint32_t ETSCTRL_SET; /**< Early Time Stamp Control */ + __IOM uint32_t ETSTIM_SET; /**< Early Time Stamp Timing */ + __IOM uint32_t ANTSWCTRL_SET; /**< Antenna Switch Control */ + __IOM uint32_t ANTSWCTRL1_SET; /**< Antenna Switch Control 1 */ + __IOM uint32_t ANTSWSTART_SET; /**< Antenna Switch Start */ + __IOM uint32_t ANTSWEND_SET; /**< Antenna Switch End */ + __IOM uint32_t TRECPMPATT_SET; /**< TRECS Preamble pattern */ + __IOM uint32_t TRECPMDET_SET; /**< TRECS preamble Detection CTRL */ + __IOM uint32_t TRECSCFG_SET; /**< TRECS configuration */ + __IOM uint32_t CFGANTPATT_SET; /**< Configure Antenna Pattern */ + __IOM uint32_t COCURRMODE_SET; /**< CONCURRENT MODE */ + __IOM uint32_t CHFCOE00_SET; /**< CHF COE. Set0 group0 */ + __IOM uint32_t CHFCOE01_SET; /**< CHF COE. Set0 group1 */ + __IOM uint32_t CHFCOE02_SET; /**< CHF COE. Set0 group2 */ + __IOM uint32_t CHFCOE03_SET; /**< CHF COE. Set0 group3 */ + __IOM uint32_t CHFCOE04_SET; /**< CHF COE. Set0 group4 */ + __IOM uint32_t CHFCOE05_SET; /**< CHF COE. Set0 group5 */ + __IOM uint32_t CHFCOE06_SET; /**< CHF COE. Set0 group6 */ + __IOM uint32_t CHFCOE10_SET; /**< CHF COE. Set1 group0 */ + __IOM uint32_t CHFCOE11_SET; /**< CHF COE. Set1 group1 */ + __IOM uint32_t CHFCOE12_SET; /**< CHF COE. Set1 group2 */ + __IOM uint32_t CHFCOE13_SET; /**< CHF COE. Set1 group3 */ + __IOM uint32_t CHFCOE14_SET; /**< CHF COE. Set1 group4 */ + __IOM uint32_t CHFCOE15_SET; /**< CHF COE. Set1 group5 */ + __IOM uint32_t CHFCOE16_SET; /**< CHF COE. Set1 group6 */ + __IOM uint32_t CHFCTRL_SET; /**< CHF control */ + __IOM uint32_t CHFLATENCYCTRL_SET; /**< CHF Latency Control */ + __IOM uint32_t FRMSCHTIME_SET; /**< FRAM SCH TIME-OUT length */ + __IOM uint32_t PREFILTCOEFF_SET; /**< Preamble Filter Coefficients */ + __IOM uint32_t RXRESTART_SET; /**< Collision restart control */ + __IOM uint32_t SQ_SET; /**< Preamble Sense Mode */ + __IOM uint32_t SQEXT_SET; /**< Preamble Sense Mode EXT */ + __IOM uint32_t SQI_SET; /**< Signal quality indicator */ + __IOM uint32_t ANTDIVCTRL_SET; /**< Antenna Diversity Mode Control Register */ + __IOM uint32_t ANTDIVFW_SET; /**< PHASE DEMOD FW mode */ + __IOM uint32_t PHDMODANTDIV_SET; /**< PHASE DEMOD ANTENNA DIVSERSITY */ + __IOM uint32_t PHANTDECSION_SET; /**< PHASE DEMOD ANT-DIV Decision */ + __IOM uint32_t PHDMODCTRL_SET; /**< PHASE DEMOD CTRL */ + __IOM uint32_t SICTRL0_SET; /**< Signal Identifier CTRL0 */ + __IOM uint32_t SICTRL1_SET; /**< Signal Identifier CTRL1 */ + __IM uint32_t SISTATUS_SET; /**< Signal Identifier Status */ + __IOM uint32_t CFGANTPATTEXT_SET; /**< Configure Antenna Pattern */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t SICTRL2_SET; /**< Signal Identifier CTRL2 */ + __IOM uint32_t CHFSWCTRL_SET; /**< Channel Filter Switch Time */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t IRCAL_SET; /**< IRCAL control signals */ + __IM uint32_t IRCALCOEF_SET; /**< IRCAL COEF values */ + MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_SET[2U]; /**< IRCAL COEFS WR per antenna */ + __IOM uint32_t ADCTRL1_SET; /**< ADCTRL1 */ + __IOM uint32_t ADCTRL2_SET; /**< ADCTRL2 */ + __IM uint32_t ADQUAL0_SET; /**< ADQUAL0 */ + __IM uint32_t ADQUAL1_SET; /**< ADQUAL1 */ + __IM uint32_t ADQUAL2_SET; /**< ADQUAL2 */ + __IM uint32_t ADQUAL3_SET; /**< ADQUAL3 */ + __IOM uint32_t ADQUAL4_SET; /**< ADQUAL4 */ + __IOM uint32_t ADQUAL5_SET; /**< ADQUAL5 */ + __IOM uint32_t ADQUAL6_SET; /**< ADQUAL6 */ + __IOM uint32_t ADQUAL7_SET; /**< ADQUAL7 */ + __IOM uint32_t ADQUAL8_SET; /**< ADQUAL8 */ + __IM uint32_t ADQUAL9_SET; /**< ADQUAL9 */ + __IM uint32_t ADQUAL10_SET; /**< ADQUAL10 */ + __IOM uint32_t ADFSM0_SET; /**< ADFSM0 */ + __IOM uint32_t ADFSM1_SET; /**< ADFSM1 */ + __IOM uint32_t ADFSM2_SET; /**< ADFSM2 */ + __IOM uint32_t ADFSM3_SET; /**< ADFSM3 */ + __IOM uint32_t ADFSM4_SET; /**< ADFSM4 */ + __IOM uint32_t ADFSM5_SET; /**< ADFSM5 */ + __IOM uint32_t ADFSM6_SET; /**< ADFSM6 */ + __IOM uint32_t ADFSM7_SET; /**< ADFSM7 */ + __IOM uint32_t ADFSM8_SET; /**< ADFSM8 */ + __IOM uint32_t ADFSM9_SET; /**< ADFSM9 */ + __IOM uint32_t ADFSM10_SET; /**< ADFSM10 */ + __IOM uint32_t ADFSM11_SET; /**< ADFSM11 */ + __IOM uint32_t ADFSM12_SET; /**< ADFSM12 */ + __IOM uint32_t ADFSM13_SET; /**< ADFSM13 */ + __IOM uint32_t ADFSM14_SET; /**< ADFSM14 */ + __IOM uint32_t ADFSM15_SET; /**< ADFSM15 */ + __IOM uint32_t ADFSM16_SET; /**< ADFSM16 */ + __IOM uint32_t ADFSM17_SET; /**< ADFSM17 */ + __IOM uint32_t ADFSM18_SET; /**< ADFSM18 */ + __IOM uint32_t ADFSM19_SET; /**< ADFSM19 */ + __IOM uint32_t ADFSM20_SET; /**< ADFSM20 */ + __IOM uint32_t ADFSM21_SET; /**< ADFSM21 */ + __IM uint32_t ADFSM22_SET; /**< ADFSM22 */ + __IOM uint32_t ADFSM23_SET; /**< ADFSM23 */ + __IOM uint32_t ADFSM24_SET; /**< ADFSM24 */ + __IOM uint32_t ADFSM25_SET; /**< ADFSM25 */ + __IOM uint32_t ADFSM26_SET; /**< ADFSM26 */ + __IOM uint32_t ADFSM27_SET; /**< ADFSM27 */ + __IOM uint32_t ADFSM28_SET; /**< ADFSM28 */ + __IOM uint32_t ADFSM29_SET; /**< ADFSM29 */ + __IOM uint32_t ADFSM30_SET; /**< ADFSM30 */ + __IOM uint32_t ADPC1_SET; /**< ADPC1 */ + __IOM uint32_t ADPC2_SET; /**< ADPC2 */ + __IOM uint32_t ADPC3_SET; /**< ADPC3 */ + __IOM uint32_t ADPC4_SET; /**< ADPC4 */ + __IOM uint32_t ADPC5_SET; /**< ADPC5 */ + __IOM uint32_t ADPC6_SET; /**< ADPC6 */ + __IOM uint32_t ADPC7_SET; /**< ADPC7 */ + __IOM uint32_t ADPC8_SET; /**< ADPC8 */ + __IOM uint32_t ADPC9_SET; /**< ADPC9 */ + __IOM uint32_t ADPC10_SET; /**< ADPC10 */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[15U]; /**< Reserved for future use */ + __IOM uint32_t HADMCTRL0_SET; /**< HADM Control */ + __IOM uint32_t HADMCTRL1_SET; /**< HADM Control 1 */ + __IM uint32_t HADMSTATUS0_SET; /**< HADM Status */ + __IM uint32_t HADMSTATUS1_SET; /**< HADM Status 1 */ + __IM uint32_t HADMSTATUS2_SET; /**< HADM Status 2 */ + __IM uint32_t HADMSTATUS3_SET; /**< HADM Status 3 */ + __IM uint32_t HADMSTATUS4_SET; /**< HADM Status 4 */ + __IM uint32_t HADMSTATUS5_SET; /**< HADM Status 5 */ + __IM uint32_t HADMSTATUS6_SET; /**< HADM Status 6 */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t SRC2NCOCTRL_SET; /**< SRC2 NCO CTRL */ + uint32_t RESERVED22[7U]; /**< Reserved for future use */ + __IOM uint32_t SPARE_SET; /**< Spare register */ + uint32_t RESERVED23[767U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t STATUS2_CLR; /**< Status Register 2 */ + __IM uint32_t STATUS3_CLR; /**< Status Register 3 */ + __IM uint32_t STATUS4_CLR; /**< ANT DIV RSSI Status */ + __IM uint32_t STATUS5_CLR; /**< Collision restart status */ + __IM uint32_t STATUS6_CLR; /**< ANT DIV Correlation Status */ + __IM uint32_t STATUS7_CLR; /**< PHASE Demod Status */ + __IM uint32_t TIMDETSTATUS_CLR; /**< Timing Detection Status Register */ + __IM uint32_t FSMSTATUS_CLR; /**< Demod FSM Status Register */ + __IM uint32_t FREQOFFEST_CLR; /**< Frequency Offset Estimate */ + __IOM uint32_t AFCADJRX_CLR; /**< AFC Adjustment RX */ + __IOM uint32_t AFCADJTX_CLR; /**< AFC Adjustment TX */ + __IOM uint32_t MIXCTRL_CLR; /**< Analog mixer control */ + __IOM uint32_t CTRL0_CLR; /**< Control Register 0 */ + __IOM uint32_t CTRL1_CLR; /**< Control Register 1 */ + __IOM uint32_t CTRL2_CLR; /**< Control Register 2 */ + __IOM uint32_t CTRL3_CLR; /**< Control Register 3 */ + __IOM uint32_t CTRL4_CLR; /**< Control Register 4 */ + __IOM uint32_t CTRL5_CLR; /**< Control Register 5 */ + __IOM uint32_t CTRL6_CLR; /**< Control Register 6 */ + __IOM uint32_t TXBR_CLR; /**< Transmit baudrate */ + __IOM uint32_t RXBR_CLR; /**< Receive Baudrate */ + __IOM uint32_t CF_CLR; /**< Channel Filter */ + __IOM uint32_t PRE_CLR; /**< Preamble Register */ + __IOM uint32_t SYNC0_CLR; /**< Sync word 0 */ + __IOM uint32_t SYNC1_CLR; /**< Sync word 1 */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t DSSS0_CLR; /**< DSSS symbol 0 Register */ + __IOM uint32_t MODINDEX_CLR; /**< Modulation Index */ + __IOM uint32_t AFC_CLR; /**< Automatic Frequency Control */ + __IOM uint32_t AFCADJLIM_CLR; /**< AFC Adjustment Limit */ + __IOM uint32_t SHAPING0_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING1_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING2_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING3_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING4_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING5_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING6_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING7_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING8_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING9_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING10_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING11_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING12_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING13_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING14_CLR; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING15_CLR; /**< Shaping Coefficients */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t RAMPCTRL_CLR; /**< Ramping Register */ + __IOM uint32_t RAMPLEV_CLR; /**< Ramping Register */ + __IOM uint32_t ANARAMPCTRL_CLR; /**< Analog Ramping Control */ + uint32_t RESERVED25[11U]; /**< Reserved for future use */ + __IOM uint32_t DCCOMP_CLR; /**< DC Offset Compensation Filter Settings */ + __IOM uint32_t DCCOMPFILTINIT_CLR; /**< DC Offset compensation Filter */ + __IM uint32_t DCESTI_CLR; /**< DC Offset Estimated value */ + __IOM uint32_t SRCCHF_CLR; /**< SRC ratio values and channel filter */ + __IOM uint32_t INTAFC_CLR; /**< Internal AFC */ + __IOM uint32_t DSATHD0_CLR; /**< DSA detector threshold-0 */ + __IOM uint32_t DSATHD1_CLR; /**< DSA detector threshold-1 */ + __IOM uint32_t DSATHD2_CLR; /**< DSA detector threshold-2 */ + __IOM uint32_t DSATHD3_CLR; /**< DSA detector threshold 3 */ + __IOM uint32_t DSATHD4_CLR; /**< DSA detector threshold 4 */ + __IOM uint32_t DSACTRL_CLR; /**< DSA mode */ + __IOM uint32_t DIGMIXCTRL_CLR; /**< Digital mixer control register */ + __IOM uint32_t VITERBIDEMOD_CLR; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG0_CLR; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG1_CLR; /**< Viterbi demodulator */ + __IOM uint32_t VTTRACK_CLR; /**< Viterbi demodulator tracking loop */ + __IOM uint32_t VTBLETIMING_CLR; /**< Viterbi BLE timing stamp control */ + __IM uint32_t BREST_CLR; /**< Baudrate Estimate */ + __IOM uint32_t AUTOCG_CLR; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_CLR; /**< Automatic clock gating */ + __IM uint32_t POE_CLR; /**< Phase Offset Estimate */ + __IOM uint32_t DIRECTMODE_CLR; /**< Direct Mode Control */ + __IOM uint32_t LONGRANGE_CLR; /**< BLE Long Range */ + __IOM uint32_t LONGRANGE1_CLR; /**< BLE Long Range Set1 */ + __IOM uint32_t LONGRANGE2_CLR; /**< BLE Long Range Set2 */ + __IOM uint32_t LONGRANGE3_CLR; /**< BLE Long Range Set3 */ + __IOM uint32_t LONGRANGE4_CLR; /**< BLE Long Range Set4 */ + __IOM uint32_t LONGRANGE5_CLR; /**< BLE Long Range Set5 */ + __IOM uint32_t LONGRANGE6_CLR; /**< BLE Long Range Set6 */ + __IOM uint32_t LRFRC_CLR; /**< BLE Long Range FRC interface */ + __IOM uint32_t COH0_CLR; /**< Coherent demodulator control signals */ + __IOM uint32_t COH1_CLR; /**< Coherent demodulator control signals */ + __IOM uint32_t COH2_CLR; /**< Coherent demodulator control signals */ + __IOM uint32_t COH3_CLR; /**< Coherent demodulator control signals */ + __IOM uint32_t CMD_CLR; /**< Command register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + __IOM uint32_t SYNCPROPERTIES_CLR; /**< Sync word properties */ + __IOM uint32_t DIGIGAINCTRL_CLR; /**< Digital Gain Control */ + __IOM uint32_t PRSCTRL_CLR; /**< Mux control for PRS outputs */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t REALTIMCFE_CLR; /**< Real time Cost Function Engine CTRL */ + __IOM uint32_t ETSCTRL_CLR; /**< Early Time Stamp Control */ + __IOM uint32_t ETSTIM_CLR; /**< Early Time Stamp Timing */ + __IOM uint32_t ANTSWCTRL_CLR; /**< Antenna Switch Control */ + __IOM uint32_t ANTSWCTRL1_CLR; /**< Antenna Switch Control 1 */ + __IOM uint32_t ANTSWSTART_CLR; /**< Antenna Switch Start */ + __IOM uint32_t ANTSWEND_CLR; /**< Antenna Switch End */ + __IOM uint32_t TRECPMPATT_CLR; /**< TRECS Preamble pattern */ + __IOM uint32_t TRECPMDET_CLR; /**< TRECS preamble Detection CTRL */ + __IOM uint32_t TRECSCFG_CLR; /**< TRECS configuration */ + __IOM uint32_t CFGANTPATT_CLR; /**< Configure Antenna Pattern */ + __IOM uint32_t COCURRMODE_CLR; /**< CONCURRENT MODE */ + __IOM uint32_t CHFCOE00_CLR; /**< CHF COE. Set0 group0 */ + __IOM uint32_t CHFCOE01_CLR; /**< CHF COE. Set0 group1 */ + __IOM uint32_t CHFCOE02_CLR; /**< CHF COE. Set0 group2 */ + __IOM uint32_t CHFCOE03_CLR; /**< CHF COE. Set0 group3 */ + __IOM uint32_t CHFCOE04_CLR; /**< CHF COE. Set0 group4 */ + __IOM uint32_t CHFCOE05_CLR; /**< CHF COE. Set0 group5 */ + __IOM uint32_t CHFCOE06_CLR; /**< CHF COE. Set0 group6 */ + __IOM uint32_t CHFCOE10_CLR; /**< CHF COE. Set1 group0 */ + __IOM uint32_t CHFCOE11_CLR; /**< CHF COE. Set1 group1 */ + __IOM uint32_t CHFCOE12_CLR; /**< CHF COE. Set1 group2 */ + __IOM uint32_t CHFCOE13_CLR; /**< CHF COE. Set1 group3 */ + __IOM uint32_t CHFCOE14_CLR; /**< CHF COE. Set1 group4 */ + __IOM uint32_t CHFCOE15_CLR; /**< CHF COE. Set1 group5 */ + __IOM uint32_t CHFCOE16_CLR; /**< CHF COE. Set1 group6 */ + __IOM uint32_t CHFCTRL_CLR; /**< CHF control */ + __IOM uint32_t CHFLATENCYCTRL_CLR; /**< CHF Latency Control */ + __IOM uint32_t FRMSCHTIME_CLR; /**< FRAM SCH TIME-OUT length */ + __IOM uint32_t PREFILTCOEFF_CLR; /**< Preamble Filter Coefficients */ + __IOM uint32_t RXRESTART_CLR; /**< Collision restart control */ + __IOM uint32_t SQ_CLR; /**< Preamble Sense Mode */ + __IOM uint32_t SQEXT_CLR; /**< Preamble Sense Mode EXT */ + __IOM uint32_t SQI_CLR; /**< Signal quality indicator */ + __IOM uint32_t ANTDIVCTRL_CLR; /**< Antenna Diversity Mode Control Register */ + __IOM uint32_t ANTDIVFW_CLR; /**< PHASE DEMOD FW mode */ + __IOM uint32_t PHDMODANTDIV_CLR; /**< PHASE DEMOD ANTENNA DIVSERSITY */ + __IOM uint32_t PHANTDECSION_CLR; /**< PHASE DEMOD ANT-DIV Decision */ + __IOM uint32_t PHDMODCTRL_CLR; /**< PHASE DEMOD CTRL */ + __IOM uint32_t SICTRL0_CLR; /**< Signal Identifier CTRL0 */ + __IOM uint32_t SICTRL1_CLR; /**< Signal Identifier CTRL1 */ + __IM uint32_t SISTATUS_CLR; /**< Signal Identifier Status */ + __IOM uint32_t CFGANTPATTEXT_CLR; /**< Configure Antenna Pattern */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t SICTRL2_CLR; /**< Signal Identifier CTRL2 */ + __IOM uint32_t CHFSWCTRL_CLR; /**< Channel Filter Switch Time */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t IRCAL_CLR; /**< IRCAL control signals */ + __IM uint32_t IRCALCOEF_CLR; /**< IRCAL COEF values */ + MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_CLR[2U]; /**< IRCAL COEFS WR per antenna */ + __IOM uint32_t ADCTRL1_CLR; /**< ADCTRL1 */ + __IOM uint32_t ADCTRL2_CLR; /**< ADCTRL2 */ + __IM uint32_t ADQUAL0_CLR; /**< ADQUAL0 */ + __IM uint32_t ADQUAL1_CLR; /**< ADQUAL1 */ + __IM uint32_t ADQUAL2_CLR; /**< ADQUAL2 */ + __IM uint32_t ADQUAL3_CLR; /**< ADQUAL3 */ + __IOM uint32_t ADQUAL4_CLR; /**< ADQUAL4 */ + __IOM uint32_t ADQUAL5_CLR; /**< ADQUAL5 */ + __IOM uint32_t ADQUAL6_CLR; /**< ADQUAL6 */ + __IOM uint32_t ADQUAL7_CLR; /**< ADQUAL7 */ + __IOM uint32_t ADQUAL8_CLR; /**< ADQUAL8 */ + __IM uint32_t ADQUAL9_CLR; /**< ADQUAL9 */ + __IM uint32_t ADQUAL10_CLR; /**< ADQUAL10 */ + __IOM uint32_t ADFSM0_CLR; /**< ADFSM0 */ + __IOM uint32_t ADFSM1_CLR; /**< ADFSM1 */ + __IOM uint32_t ADFSM2_CLR; /**< ADFSM2 */ + __IOM uint32_t ADFSM3_CLR; /**< ADFSM3 */ + __IOM uint32_t ADFSM4_CLR; /**< ADFSM4 */ + __IOM uint32_t ADFSM5_CLR; /**< ADFSM5 */ + __IOM uint32_t ADFSM6_CLR; /**< ADFSM6 */ + __IOM uint32_t ADFSM7_CLR; /**< ADFSM7 */ + __IOM uint32_t ADFSM8_CLR; /**< ADFSM8 */ + __IOM uint32_t ADFSM9_CLR; /**< ADFSM9 */ + __IOM uint32_t ADFSM10_CLR; /**< ADFSM10 */ + __IOM uint32_t ADFSM11_CLR; /**< ADFSM11 */ + __IOM uint32_t ADFSM12_CLR; /**< ADFSM12 */ + __IOM uint32_t ADFSM13_CLR; /**< ADFSM13 */ + __IOM uint32_t ADFSM14_CLR; /**< ADFSM14 */ + __IOM uint32_t ADFSM15_CLR; /**< ADFSM15 */ + __IOM uint32_t ADFSM16_CLR; /**< ADFSM16 */ + __IOM uint32_t ADFSM17_CLR; /**< ADFSM17 */ + __IOM uint32_t ADFSM18_CLR; /**< ADFSM18 */ + __IOM uint32_t ADFSM19_CLR; /**< ADFSM19 */ + __IOM uint32_t ADFSM20_CLR; /**< ADFSM20 */ + __IOM uint32_t ADFSM21_CLR; /**< ADFSM21 */ + __IM uint32_t ADFSM22_CLR; /**< ADFSM22 */ + __IOM uint32_t ADFSM23_CLR; /**< ADFSM23 */ + __IOM uint32_t ADFSM24_CLR; /**< ADFSM24 */ + __IOM uint32_t ADFSM25_CLR; /**< ADFSM25 */ + __IOM uint32_t ADFSM26_CLR; /**< ADFSM26 */ + __IOM uint32_t ADFSM27_CLR; /**< ADFSM27 */ + __IOM uint32_t ADFSM28_CLR; /**< ADFSM28 */ + __IOM uint32_t ADFSM29_CLR; /**< ADFSM29 */ + __IOM uint32_t ADFSM30_CLR; /**< ADFSM30 */ + __IOM uint32_t ADPC1_CLR; /**< ADPC1 */ + __IOM uint32_t ADPC2_CLR; /**< ADPC2 */ + __IOM uint32_t ADPC3_CLR; /**< ADPC3 */ + __IOM uint32_t ADPC4_CLR; /**< ADPC4 */ + __IOM uint32_t ADPC5_CLR; /**< ADPC5 */ + __IOM uint32_t ADPC6_CLR; /**< ADPC6 */ + __IOM uint32_t ADPC7_CLR; /**< ADPC7 */ + __IOM uint32_t ADPC8_CLR; /**< ADPC8 */ + __IOM uint32_t ADPC9_CLR; /**< ADPC9 */ + __IOM uint32_t ADPC10_CLR; /**< ADPC10 */ + uint32_t RESERVED30[6U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + uint32_t RESERVED32[15U]; /**< Reserved for future use */ + __IOM uint32_t HADMCTRL0_CLR; /**< HADM Control */ + __IOM uint32_t HADMCTRL1_CLR; /**< HADM Control 1 */ + __IM uint32_t HADMSTATUS0_CLR; /**< HADM Status */ + __IM uint32_t HADMSTATUS1_CLR; /**< HADM Status 1 */ + __IM uint32_t HADMSTATUS2_CLR; /**< HADM Status 2 */ + __IM uint32_t HADMSTATUS3_CLR; /**< HADM Status 3 */ + __IM uint32_t HADMSTATUS4_CLR; /**< HADM Status 4 */ + __IM uint32_t HADMSTATUS5_CLR; /**< HADM Status 5 */ + __IM uint32_t HADMSTATUS6_CLR; /**< HADM Status 6 */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t SRC2NCOCTRL_CLR; /**< SRC2 NCO CTRL */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t SPARE_CLR; /**< Spare register */ + uint32_t RESERVED35[767U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t STATUS2_TGL; /**< Status Register 2 */ + __IM uint32_t STATUS3_TGL; /**< Status Register 3 */ + __IM uint32_t STATUS4_TGL; /**< ANT DIV RSSI Status */ + __IM uint32_t STATUS5_TGL; /**< Collision restart status */ + __IM uint32_t STATUS6_TGL; /**< ANT DIV Correlation Status */ + __IM uint32_t STATUS7_TGL; /**< PHASE Demod Status */ + __IM uint32_t TIMDETSTATUS_TGL; /**< Timing Detection Status Register */ + __IM uint32_t FSMSTATUS_TGL; /**< Demod FSM Status Register */ + __IM uint32_t FREQOFFEST_TGL; /**< Frequency Offset Estimate */ + __IOM uint32_t AFCADJRX_TGL; /**< AFC Adjustment RX */ + __IOM uint32_t AFCADJTX_TGL; /**< AFC Adjustment TX */ + __IOM uint32_t MIXCTRL_TGL; /**< Analog mixer control */ + __IOM uint32_t CTRL0_TGL; /**< Control Register 0 */ + __IOM uint32_t CTRL1_TGL; /**< Control Register 1 */ + __IOM uint32_t CTRL2_TGL; /**< Control Register 2 */ + __IOM uint32_t CTRL3_TGL; /**< Control Register 3 */ + __IOM uint32_t CTRL4_TGL; /**< Control Register 4 */ + __IOM uint32_t CTRL5_TGL; /**< Control Register 5 */ + __IOM uint32_t CTRL6_TGL; /**< Control Register 6 */ + __IOM uint32_t TXBR_TGL; /**< Transmit baudrate */ + __IOM uint32_t RXBR_TGL; /**< Receive Baudrate */ + __IOM uint32_t CF_TGL; /**< Channel Filter */ + __IOM uint32_t PRE_TGL; /**< Preamble Register */ + __IOM uint32_t SYNC0_TGL; /**< Sync word 0 */ + __IOM uint32_t SYNC1_TGL; /**< Sync word 1 */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t DSSS0_TGL; /**< DSSS symbol 0 Register */ + __IOM uint32_t MODINDEX_TGL; /**< Modulation Index */ + __IOM uint32_t AFC_TGL; /**< Automatic Frequency Control */ + __IOM uint32_t AFCADJLIM_TGL; /**< AFC Adjustment Limit */ + __IOM uint32_t SHAPING0_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING1_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING2_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING3_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING4_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING5_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING6_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING7_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING8_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING9_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING10_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING11_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING12_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING13_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING14_TGL; /**< Shaping Coefficients */ + __IOM uint32_t SHAPING15_TGL; /**< Shaping Coefficients */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t RAMPCTRL_TGL; /**< Ramping Register */ + __IOM uint32_t RAMPLEV_TGL; /**< Ramping Register */ + __IOM uint32_t ANARAMPCTRL_TGL; /**< Analog Ramping Control */ + uint32_t RESERVED37[11U]; /**< Reserved for future use */ + __IOM uint32_t DCCOMP_TGL; /**< DC Offset Compensation Filter Settings */ + __IOM uint32_t DCCOMPFILTINIT_TGL; /**< DC Offset compensation Filter */ + __IM uint32_t DCESTI_TGL; /**< DC Offset Estimated value */ + __IOM uint32_t SRCCHF_TGL; /**< SRC ratio values and channel filter */ + __IOM uint32_t INTAFC_TGL; /**< Internal AFC */ + __IOM uint32_t DSATHD0_TGL; /**< DSA detector threshold-0 */ + __IOM uint32_t DSATHD1_TGL; /**< DSA detector threshold-1 */ + __IOM uint32_t DSATHD2_TGL; /**< DSA detector threshold-2 */ + __IOM uint32_t DSATHD3_TGL; /**< DSA detector threshold 3 */ + __IOM uint32_t DSATHD4_TGL; /**< DSA detector threshold 4 */ + __IOM uint32_t DSACTRL_TGL; /**< DSA mode */ + __IOM uint32_t DIGMIXCTRL_TGL; /**< Digital mixer control register */ + __IOM uint32_t VITERBIDEMOD_TGL; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG0_TGL; /**< Viterbi demodulator */ + __IOM uint32_t VTCORRCFG1_TGL; /**< Viterbi demodulator */ + __IOM uint32_t VTTRACK_TGL; /**< Viterbi demodulator tracking loop */ + __IOM uint32_t VTBLETIMING_TGL; /**< Viterbi BLE timing stamp control */ + __IM uint32_t BREST_TGL; /**< Baudrate Estimate */ + __IOM uint32_t AUTOCG_TGL; /**< Automatic clock gating */ + __IOM uint32_t CGCLKSTOP_TGL; /**< Automatic clock gating */ + __IM uint32_t POE_TGL; /**< Phase Offset Estimate */ + __IOM uint32_t DIRECTMODE_TGL; /**< Direct Mode Control */ + __IOM uint32_t LONGRANGE_TGL; /**< BLE Long Range */ + __IOM uint32_t LONGRANGE1_TGL; /**< BLE Long Range Set1 */ + __IOM uint32_t LONGRANGE2_TGL; /**< BLE Long Range Set2 */ + __IOM uint32_t LONGRANGE3_TGL; /**< BLE Long Range Set3 */ + __IOM uint32_t LONGRANGE4_TGL; /**< BLE Long Range Set4 */ + __IOM uint32_t LONGRANGE5_TGL; /**< BLE Long Range Set5 */ + __IOM uint32_t LONGRANGE6_TGL; /**< BLE Long Range Set6 */ + __IOM uint32_t LRFRC_TGL; /**< BLE Long Range FRC interface */ + __IOM uint32_t COH0_TGL; /**< Coherent demodulator control signals */ + __IOM uint32_t COH1_TGL; /**< Coherent demodulator control signals */ + __IOM uint32_t COH2_TGL; /**< Coherent demodulator control signals */ + __IOM uint32_t COH3_TGL; /**< Coherent demodulator control signals */ + __IOM uint32_t CMD_TGL; /**< Command register */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + __IOM uint32_t SYNCPROPERTIES_TGL; /**< Sync word properties */ + __IOM uint32_t DIGIGAINCTRL_TGL; /**< Digital Gain Control */ + __IOM uint32_t PRSCTRL_TGL; /**< Mux control for PRS outputs */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t REALTIMCFE_TGL; /**< Real time Cost Function Engine CTRL */ + __IOM uint32_t ETSCTRL_TGL; /**< Early Time Stamp Control */ + __IOM uint32_t ETSTIM_TGL; /**< Early Time Stamp Timing */ + __IOM uint32_t ANTSWCTRL_TGL; /**< Antenna Switch Control */ + __IOM uint32_t ANTSWCTRL1_TGL; /**< Antenna Switch Control 1 */ + __IOM uint32_t ANTSWSTART_TGL; /**< Antenna Switch Start */ + __IOM uint32_t ANTSWEND_TGL; /**< Antenna Switch End */ + __IOM uint32_t TRECPMPATT_TGL; /**< TRECS Preamble pattern */ + __IOM uint32_t TRECPMDET_TGL; /**< TRECS preamble Detection CTRL */ + __IOM uint32_t TRECSCFG_TGL; /**< TRECS configuration */ + __IOM uint32_t CFGANTPATT_TGL; /**< Configure Antenna Pattern */ + __IOM uint32_t COCURRMODE_TGL; /**< CONCURRENT MODE */ + __IOM uint32_t CHFCOE00_TGL; /**< CHF COE. Set0 group0 */ + __IOM uint32_t CHFCOE01_TGL; /**< CHF COE. Set0 group1 */ + __IOM uint32_t CHFCOE02_TGL; /**< CHF COE. Set0 group2 */ + __IOM uint32_t CHFCOE03_TGL; /**< CHF COE. Set0 group3 */ + __IOM uint32_t CHFCOE04_TGL; /**< CHF COE. Set0 group4 */ + __IOM uint32_t CHFCOE05_TGL; /**< CHF COE. Set0 group5 */ + __IOM uint32_t CHFCOE06_TGL; /**< CHF COE. Set0 group6 */ + __IOM uint32_t CHFCOE10_TGL; /**< CHF COE. Set1 group0 */ + __IOM uint32_t CHFCOE11_TGL; /**< CHF COE. Set1 group1 */ + __IOM uint32_t CHFCOE12_TGL; /**< CHF COE. Set1 group2 */ + __IOM uint32_t CHFCOE13_TGL; /**< CHF COE. Set1 group3 */ + __IOM uint32_t CHFCOE14_TGL; /**< CHF COE. Set1 group4 */ + __IOM uint32_t CHFCOE15_TGL; /**< CHF COE. Set1 group5 */ + __IOM uint32_t CHFCOE16_TGL; /**< CHF COE. Set1 group6 */ + __IOM uint32_t CHFCTRL_TGL; /**< CHF control */ + __IOM uint32_t CHFLATENCYCTRL_TGL; /**< CHF Latency Control */ + __IOM uint32_t FRMSCHTIME_TGL; /**< FRAM SCH TIME-OUT length */ + __IOM uint32_t PREFILTCOEFF_TGL; /**< Preamble Filter Coefficients */ + __IOM uint32_t RXRESTART_TGL; /**< Collision restart control */ + __IOM uint32_t SQ_TGL; /**< Preamble Sense Mode */ + __IOM uint32_t SQEXT_TGL; /**< Preamble Sense Mode EXT */ + __IOM uint32_t SQI_TGL; /**< Signal quality indicator */ + __IOM uint32_t ANTDIVCTRL_TGL; /**< Antenna Diversity Mode Control Register */ + __IOM uint32_t ANTDIVFW_TGL; /**< PHASE DEMOD FW mode */ + __IOM uint32_t PHDMODANTDIV_TGL; /**< PHASE DEMOD ANTENNA DIVSERSITY */ + __IOM uint32_t PHANTDECSION_TGL; /**< PHASE DEMOD ANT-DIV Decision */ + __IOM uint32_t PHDMODCTRL_TGL; /**< PHASE DEMOD CTRL */ + __IOM uint32_t SICTRL0_TGL; /**< Signal Identifier CTRL0 */ + __IOM uint32_t SICTRL1_TGL; /**< Signal Identifier CTRL1 */ + __IM uint32_t SISTATUS_TGL; /**< Signal Identifier Status */ + __IOM uint32_t CFGANTPATTEXT_TGL; /**< Configure Antenna Pattern */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IOM uint32_t SICTRL2_TGL; /**< Signal Identifier CTRL2 */ + __IOM uint32_t CHFSWCTRL_TGL; /**< Channel Filter Switch Time */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t IRCAL_TGL; /**< IRCAL control signals */ + __IM uint32_t IRCALCOEF_TGL; /**< IRCAL COEF values */ + MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_TGL[2U]; /**< IRCAL COEFS WR per antenna */ + __IOM uint32_t ADCTRL1_TGL; /**< ADCTRL1 */ + __IOM uint32_t ADCTRL2_TGL; /**< ADCTRL2 */ + __IM uint32_t ADQUAL0_TGL; /**< ADQUAL0 */ + __IM uint32_t ADQUAL1_TGL; /**< ADQUAL1 */ + __IM uint32_t ADQUAL2_TGL; /**< ADQUAL2 */ + __IM uint32_t ADQUAL3_TGL; /**< ADQUAL3 */ + __IOM uint32_t ADQUAL4_TGL; /**< ADQUAL4 */ + __IOM uint32_t ADQUAL5_TGL; /**< ADQUAL5 */ + __IOM uint32_t ADQUAL6_TGL; /**< ADQUAL6 */ + __IOM uint32_t ADQUAL7_TGL; /**< ADQUAL7 */ + __IOM uint32_t ADQUAL8_TGL; /**< ADQUAL8 */ + __IM uint32_t ADQUAL9_TGL; /**< ADQUAL9 */ + __IM uint32_t ADQUAL10_TGL; /**< ADQUAL10 */ + __IOM uint32_t ADFSM0_TGL; /**< ADFSM0 */ + __IOM uint32_t ADFSM1_TGL; /**< ADFSM1 */ + __IOM uint32_t ADFSM2_TGL; /**< ADFSM2 */ + __IOM uint32_t ADFSM3_TGL; /**< ADFSM3 */ + __IOM uint32_t ADFSM4_TGL; /**< ADFSM4 */ + __IOM uint32_t ADFSM5_TGL; /**< ADFSM5 */ + __IOM uint32_t ADFSM6_TGL; /**< ADFSM6 */ + __IOM uint32_t ADFSM7_TGL; /**< ADFSM7 */ + __IOM uint32_t ADFSM8_TGL; /**< ADFSM8 */ + __IOM uint32_t ADFSM9_TGL; /**< ADFSM9 */ + __IOM uint32_t ADFSM10_TGL; /**< ADFSM10 */ + __IOM uint32_t ADFSM11_TGL; /**< ADFSM11 */ + __IOM uint32_t ADFSM12_TGL; /**< ADFSM12 */ + __IOM uint32_t ADFSM13_TGL; /**< ADFSM13 */ + __IOM uint32_t ADFSM14_TGL; /**< ADFSM14 */ + __IOM uint32_t ADFSM15_TGL; /**< ADFSM15 */ + __IOM uint32_t ADFSM16_TGL; /**< ADFSM16 */ + __IOM uint32_t ADFSM17_TGL; /**< ADFSM17 */ + __IOM uint32_t ADFSM18_TGL; /**< ADFSM18 */ + __IOM uint32_t ADFSM19_TGL; /**< ADFSM19 */ + __IOM uint32_t ADFSM20_TGL; /**< ADFSM20 */ + __IOM uint32_t ADFSM21_TGL; /**< ADFSM21 */ + __IM uint32_t ADFSM22_TGL; /**< ADFSM22 */ + __IOM uint32_t ADFSM23_TGL; /**< ADFSM23 */ + __IOM uint32_t ADFSM24_TGL; /**< ADFSM24 */ + __IOM uint32_t ADFSM25_TGL; /**< ADFSM25 */ + __IOM uint32_t ADFSM26_TGL; /**< ADFSM26 */ + __IOM uint32_t ADFSM27_TGL; /**< ADFSM27 */ + __IOM uint32_t ADFSM28_TGL; /**< ADFSM28 */ + __IOM uint32_t ADFSM29_TGL; /**< ADFSM29 */ + __IOM uint32_t ADFSM30_TGL; /**< ADFSM30 */ + __IOM uint32_t ADPC1_TGL; /**< ADPC1 */ + __IOM uint32_t ADPC2_TGL; /**< ADPC2 */ + __IOM uint32_t ADPC3_TGL; /**< ADPC3 */ + __IOM uint32_t ADPC4_TGL; /**< ADPC4 */ + __IOM uint32_t ADPC5_TGL; /**< ADPC5 */ + __IOM uint32_t ADPC6_TGL; /**< ADPC6 */ + __IOM uint32_t ADPC7_TGL; /**< ADPC7 */ + __IOM uint32_t ADPC8_TGL; /**< ADPC8 */ + __IOM uint32_t ADPC9_TGL; /**< ADPC9 */ + __IOM uint32_t ADPC10_TGL; /**< ADPC10 */ + uint32_t RESERVED42[6U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[15U]; /**< Reserved for future use */ + __IOM uint32_t HADMCTRL0_TGL; /**< HADM Control */ + __IOM uint32_t HADMCTRL1_TGL; /**< HADM Control 1 */ + __IM uint32_t HADMSTATUS0_TGL; /**< HADM Status */ + __IM uint32_t HADMSTATUS1_TGL; /**< HADM Status 1 */ + __IM uint32_t HADMSTATUS2_TGL; /**< HADM Status 2 */ + __IM uint32_t HADMSTATUS3_TGL; /**< HADM Status 3 */ + __IM uint32_t HADMSTATUS4_TGL; /**< HADM Status 4 */ + __IM uint32_t HADMSTATUS5_TGL; /**< HADM Status 5 */ + __IM uint32_t HADMSTATUS6_TGL; /**< HADM Status 6 */ + uint32_t RESERVED45[3U]; /**< Reserved for future use */ + __IOM uint32_t SRC2NCOCTRL_TGL; /**< SRC2 NCO CTRL */ + uint32_t RESERVED46[7U]; /**< Reserved for future use */ + __IOM uint32_t SPARE_TGL; /**< Spare register */ +} MODEM_TypeDef; +/** @} End of group EFR32MG24_MODEM */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MODEM + * @{ + * @defgroup EFR32MG24_MODEM_BitFields MODEM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MODEM IPVERSION */ +#define _MODEM_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MODEM_IPVERSION */ +#define _MODEM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MODEM_IPVERSION */ +#define _MODEM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MODEM_IPVERSION */ +#define _MODEM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_IPVERSION */ +#define _MODEM_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_IPVERSION */ +#define MODEM_IPVERSION_IPVERSION_DEFAULT (_MODEM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IPVERSION */ + +/* Bit fields for MODEM EN */ +#define _MODEM_EN_RESETVALUE 0x00000000UL /**< Default value for MODEM_EN */ +#define _MODEM_EN_MASK 0x00000001UL /**< Mask for MODEM_EN */ +#define MODEM_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _MODEM_EN_EN_SHIFT 0 /**< Shift value for MODEM_EN */ +#define _MODEM_EN_EN_MASK 0x1UL /**< Bit mask for MODEM_EN */ +#define _MODEM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_EN */ +#define MODEM_EN_EN_DEFAULT (_MODEM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_EN */ + +/* Bit fields for MODEM IF */ +#define _MODEM_IF_RESETVALUE 0x00000000UL /**< Default value for MODEM_IF */ +#define _MODEM_IF_MASK 0x3FFFFFFFUL /**< Mask for MODEM_IF */ +#define MODEM_IF_TXFRAMESENT (0x1UL << 0) /**< Frame sent */ +#define _MODEM_IF_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */ +#define _MODEM_IF_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */ +#define _MODEM_IF_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXFRAMESENT_DEFAULT (_MODEM_IF_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */ +#define _MODEM_IF_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */ +#define _MODEM_IF_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */ +#define _MODEM_IF_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXSYNCSENT_DEFAULT (_MODEM_IF_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXPRESENT (0x1UL << 2) /**< Preamble sent */ +#define _MODEM_IF_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */ +#define _MODEM_IF_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */ +#define _MODEM_IF_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXPRESENT_DEFAULT (_MODEM_IF_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */ +#define _MODEM_IF_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */ +#define _MODEM_IF_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */ +#define _MODEM_IF_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_TXRAMPDONE_DEFAULT (_MODEM_IF_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */ +#define _MODEM_IF_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */ +#define _MODEM_IF_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */ +#define _MODEM_IF_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_LDTNOARR_DEFAULT (_MODEM_IF_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */ +#define _MODEM_IF_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */ +#define _MODEM_IF_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */ +#define _MODEM_IF_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHDSADET_DEFAULT (_MODEM_IF_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */ +#define _MODEM_IF_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */ +#define _MODEM_IF_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */ +#define _MODEM_IF_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHYUNCODEDET_DEFAULT (_MODEM_IF_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */ +#define _MODEM_IF_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */ +#define _MODEM_IF_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */ +#define _MODEM_IF_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_PHYCODEDET_DEFAULT (_MODEM_IF_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMDET (0x1UL << 8) /**< Timing detected */ +#define _MODEM_IF_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */ +#define _MODEM_IF_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */ +#define _MODEM_IF_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMDET_DEFAULT (_MODEM_IF_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXPREDET (0x1UL << 9) /**< Preamble detected */ +#define _MODEM_IF_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */ +#define _MODEM_IF_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */ +#define _MODEM_IF_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXPREDET_DEFAULT (_MODEM_IF_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */ +#define _MODEM_IF_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */ +#define _MODEM_IF_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */ +#define _MODEM_IF_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDET0_DEFAULT (_MODEM_IF_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */ +#define _MODEM_IF_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */ +#define _MODEM_IF_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */ +#define _MODEM_IF_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDET1_DEFAULT (_MODEM_IF_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMLOST (0x1UL << 12) /**< Timing lost */ +#define _MODEM_IF_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */ +#define _MODEM_IF_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */ +#define _MODEM_IF_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMLOST_DEFAULT (_MODEM_IF_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXPRELOST (0x1UL << 13) /**< Preamble lost */ +#define _MODEM_IF_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */ +#define _MODEM_IF_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */ +#define _MODEM_IF_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXPRELOST_DEFAULT (_MODEM_IF_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */ +#define _MODEM_IF_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */ +#define _MODEM_IF_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */ +#define _MODEM_IF_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXFRAMEDETOF_DEFAULT (_MODEM_IF_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMNF (0x1UL << 15) /**< Timing not found */ +#define _MODEM_IF_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */ +#define _MODEM_IF_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */ +#define _MODEM_IF_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXTIMNF_DEFAULT (_MODEM_IF_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */ +#define _MODEM_IF_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */ +#define _MODEM_IF_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */ +#define _MODEM_IF_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_FRCTIMOUT_DEFAULT (_MODEM_IF_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_ETS (0x1UL << 17) /**< Early Time Stamp detect */ +#define _MODEM_IF_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */ +#define _MODEM_IF_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */ +#define _MODEM_IF_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_ETS_DEFAULT (_MODEM_IF_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_CFGANTPATTRD (0x1UL << 18) /**< cfg */ +#define _MODEM_IF_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */ +#define _MODEM_IF_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */ +#define _MODEM_IF_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_CFGANTPATTRD_DEFAULT (_MODEM_IF_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */ +#define _MODEM_IF_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_IF_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */ +#define _MODEM_IF_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_IF_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQDET (0x1UL << 21) /**< SQ Detect */ +#define _MODEM_IF_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */ +#define _MODEM_IF_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */ +#define _MODEM_IF_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQDET_DEFAULT (_MODEM_IF_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQNOTDET (0x1UL << 22) /**< SQ Not Detect */ +#define _MODEM_IF_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */ +#define _MODEM_IF_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */ +#define _MODEM_IF_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQNOTDET_DEFAULT (_MODEM_IF_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */ +#define _MODEM_IF_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */ +#define _MODEM_IF_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */ +#define _MODEM_IF_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_ANTDIVRDY_DEFAULT (_MODEM_IF_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */ +#define _MODEM_IF_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */ +#define _MODEM_IF_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */ +#define _MODEM_IF_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SOFTRESETDONE_DEFAULT (_MODEM_IF_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQPRENOTDET (0x1UL << 25) /**< SQ Not Detect */ +#define _MODEM_IF_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */ +#define _MODEM_IF_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */ +#define _MODEM_IF_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQPRENOTDET_DEFAULT (_MODEM_IF_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not Detect */ +#define _MODEM_IF_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */ +#define _MODEM_IF_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */ +#define _MODEM_IF_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQFRAMENOTDET_DEFAULT (_MODEM_IF_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ AFC out of band */ +#define _MODEM_IF_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_IF_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_IF_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SQAFCOUTOFBAND_DEFAULT (_MODEM_IF_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SIDET (0x1UL << 28) /**< Signal identified */ +#define _MODEM_IF_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */ +#define _MODEM_IF_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */ +#define _MODEM_IF_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SIDET_DEFAULT (_MODEM_IF_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SIRESET (0x1UL << 29) /**< Signal identifier reset */ +#define _MODEM_IF_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */ +#define _MODEM_IF_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */ +#define _MODEM_IF_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */ +#define MODEM_IF_SIRESET_DEFAULT (_MODEM_IF_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_IF */ + +/* Bit fields for MODEM IEN */ +#define _MODEM_IEN_RESETVALUE 0x00000000UL /**< Default value for MODEM_IEN */ +#define _MODEM_IEN_MASK 0x3FFFFFFFUL /**< Mask for MODEM_IEN */ +#define MODEM_IEN_TXFRAMESENT (0x1UL << 0) /**< Frame sent */ +#define _MODEM_IEN_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */ +#define _MODEM_IEN_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */ +#define _MODEM_IEN_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXFRAMESENT_DEFAULT (_MODEM_IEN_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */ +#define _MODEM_IEN_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */ +#define _MODEM_IEN_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */ +#define _MODEM_IEN_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXSYNCSENT_DEFAULT (_MODEM_IEN_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXPRESENT (0x1UL << 2) /**< Preamble sent */ +#define _MODEM_IEN_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */ +#define _MODEM_IEN_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */ +#define _MODEM_IEN_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXPRESENT_DEFAULT (_MODEM_IEN_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */ +#define _MODEM_IEN_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */ +#define _MODEM_IEN_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */ +#define _MODEM_IEN_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_TXRAMPDONE_DEFAULT (_MODEM_IEN_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */ +#define _MODEM_IEN_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */ +#define _MODEM_IEN_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */ +#define _MODEM_IEN_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_LDTNOARR_DEFAULT (_MODEM_IEN_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */ +#define _MODEM_IEN_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */ +#define _MODEM_IEN_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */ +#define _MODEM_IEN_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHDSADET_DEFAULT (_MODEM_IEN_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */ +#define _MODEM_IEN_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */ +#define _MODEM_IEN_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */ +#define _MODEM_IEN_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHYUNCODEDET_DEFAULT (_MODEM_IEN_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */ +#define _MODEM_IEN_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */ +#define _MODEM_IEN_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */ +#define _MODEM_IEN_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_PHYCODEDET_DEFAULT (_MODEM_IEN_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMDET (0x1UL << 8) /**< Timing detected */ +#define _MODEM_IEN_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */ +#define _MODEM_IEN_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */ +#define _MODEM_IEN_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMDET_DEFAULT (_MODEM_IEN_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXPREDET (0x1UL << 9) /**< Preamble detected */ +#define _MODEM_IEN_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */ +#define _MODEM_IEN_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */ +#define _MODEM_IEN_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXPREDET_DEFAULT (_MODEM_IEN_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */ +#define _MODEM_IEN_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */ +#define _MODEM_IEN_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */ +#define _MODEM_IEN_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDET0_DEFAULT (_MODEM_IEN_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */ +#define _MODEM_IEN_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */ +#define _MODEM_IEN_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */ +#define _MODEM_IEN_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDET1_DEFAULT (_MODEM_IEN_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMLOST (0x1UL << 12) /**< Timing lost */ +#define _MODEM_IEN_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */ +#define _MODEM_IEN_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */ +#define _MODEM_IEN_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMLOST_DEFAULT (_MODEM_IEN_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXPRELOST (0x1UL << 13) /**< Preamble lost */ +#define _MODEM_IEN_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */ +#define _MODEM_IEN_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */ +#define _MODEM_IEN_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXPRELOST_DEFAULT (_MODEM_IEN_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */ +#define _MODEM_IEN_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */ +#define _MODEM_IEN_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */ +#define _MODEM_IEN_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXFRAMEDETOF_DEFAULT (_MODEM_IEN_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMNF (0x1UL << 15) /**< Timing not found */ +#define _MODEM_IEN_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */ +#define _MODEM_IEN_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */ +#define _MODEM_IEN_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXTIMNF_DEFAULT (_MODEM_IEN_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */ +#define _MODEM_IEN_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */ +#define _MODEM_IEN_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */ +#define _MODEM_IEN_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_FRCTIMOUT_DEFAULT (_MODEM_IEN_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_ETS (0x1UL << 17) /**< Early Time Stamp detect */ +#define _MODEM_IEN_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */ +#define _MODEM_IEN_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */ +#define _MODEM_IEN_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_ETS_DEFAULT (_MODEM_IEN_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */ +#define _MODEM_IEN_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */ +#define _MODEM_IEN_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */ +#define _MODEM_IEN_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_CFGANTPATTRD_DEFAULT (_MODEM_IEN_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */ +#define _MODEM_IEN_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_IEN_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */ +#define _MODEM_IEN_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_IEN_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQDET (0x1UL << 21) /**< SQ Detected */ +#define _MODEM_IEN_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */ +#define _MODEM_IEN_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */ +#define _MODEM_IEN_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQDET_DEFAULT (_MODEM_IEN_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQNOTDET (0x1UL << 22) /**< SQ Not Detected */ +#define _MODEM_IEN_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */ +#define _MODEM_IEN_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */ +#define _MODEM_IEN_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQNOTDET_DEFAULT (_MODEM_IEN_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */ +#define _MODEM_IEN_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */ +#define _MODEM_IEN_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */ +#define _MODEM_IEN_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_ANTDIVRDY_DEFAULT (_MODEM_IEN_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */ +#define _MODEM_IEN_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */ +#define _MODEM_IEN_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */ +#define _MODEM_IEN_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SOFTRESETDONE_DEFAULT (_MODEM_IEN_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQPRENOTDET (0x1UL << 25) /**< SQ Not Detected */ +#define _MODEM_IEN_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */ +#define _MODEM_IEN_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */ +#define _MODEM_IEN_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQPRENOTDET_DEFAULT (_MODEM_IEN_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not Detected */ +#define _MODEM_IEN_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */ +#define _MODEM_IEN_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */ +#define _MODEM_IEN_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQFRAMENOTDET_DEFAULT (_MODEM_IEN_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */ +#define _MODEM_IEN_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_IEN_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_IEN_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SQAFCOUTOFBAND_DEFAULT (_MODEM_IEN_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SIDET (0x1UL << 28) /**< Signal Identified */ +#define _MODEM_IEN_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */ +#define _MODEM_IEN_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */ +#define _MODEM_IEN_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SIDET_DEFAULT (_MODEM_IEN_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SIRESET (0x1UL << 29) /**< Signal identifier reset */ +#define _MODEM_IEN_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */ +#define _MODEM_IEN_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */ +#define _MODEM_IEN_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */ +#define MODEM_IEN_SIRESET_DEFAULT (_MODEM_IEN_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_IEN */ + +/* Bit fields for MODEM SEQIF */ +#define _MODEM_SEQIF_RESETVALUE 0x00000000UL /**< Default value for MODEM_SEQIF */ +#define _MODEM_SEQIF_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SEQIF */ +#define MODEM_SEQIF_TXFRAMESENT (0x1UL << 0) /**< Frame sent */ +#define _MODEM_SEQIF_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */ +#define _MODEM_SEQIF_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */ +#define _MODEM_SEQIF_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXFRAMESENT_DEFAULT (_MODEM_SEQIF_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */ +#define _MODEM_SEQIF_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */ +#define _MODEM_SEQIF_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */ +#define _MODEM_SEQIF_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXSYNCSENT_DEFAULT (_MODEM_SEQIF_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXPRESENT (0x1UL << 2) /**< Preamble sent */ +#define _MODEM_SEQIF_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */ +#define _MODEM_SEQIF_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */ +#define _MODEM_SEQIF_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXPRESENT_DEFAULT (_MODEM_SEQIF_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */ +#define _MODEM_SEQIF_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */ +#define _MODEM_SEQIF_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */ +#define _MODEM_SEQIF_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_TXRAMPDONE_DEFAULT (_MODEM_SEQIF_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */ +#define _MODEM_SEQIF_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */ +#define _MODEM_SEQIF_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */ +#define _MODEM_SEQIF_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_LDTNOARR_DEFAULT (_MODEM_SEQIF_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */ +#define _MODEM_SEQIF_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */ +#define _MODEM_SEQIF_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */ +#define _MODEM_SEQIF_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHDSADET_DEFAULT (_MODEM_SEQIF_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */ +#define _MODEM_SEQIF_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */ +#define _MODEM_SEQIF_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */ +#define _MODEM_SEQIF_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHYUNCODEDET_DEFAULT (_MODEM_SEQIF_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */ +#define _MODEM_SEQIF_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */ +#define _MODEM_SEQIF_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */ +#define _MODEM_SEQIF_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_PHYCODEDET_DEFAULT (_MODEM_SEQIF_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMDET (0x1UL << 8) /**< Timing detected */ +#define _MODEM_SEQIF_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */ +#define _MODEM_SEQIF_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */ +#define _MODEM_SEQIF_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMDET_DEFAULT (_MODEM_SEQIF_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXPREDET (0x1UL << 9) /**< Preamble detected */ +#define _MODEM_SEQIF_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */ +#define _MODEM_SEQIF_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */ +#define _MODEM_SEQIF_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXPREDET_DEFAULT (_MODEM_SEQIF_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */ +#define _MODEM_SEQIF_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */ +#define _MODEM_SEQIF_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */ +#define _MODEM_SEQIF_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDET0_DEFAULT (_MODEM_SEQIF_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */ +#define _MODEM_SEQIF_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */ +#define _MODEM_SEQIF_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */ +#define _MODEM_SEQIF_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDET1_DEFAULT (_MODEM_SEQIF_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMLOST (0x1UL << 12) /**< Timing lost */ +#define _MODEM_SEQIF_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */ +#define _MODEM_SEQIF_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */ +#define _MODEM_SEQIF_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMLOST_DEFAULT (_MODEM_SEQIF_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXPRELOST (0x1UL << 13) /**< Preamble lost */ +#define _MODEM_SEQIF_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */ +#define _MODEM_SEQIF_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */ +#define _MODEM_SEQIF_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXPRELOST_DEFAULT (_MODEM_SEQIF_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */ +#define _MODEM_SEQIF_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */ +#define _MODEM_SEQIF_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */ +#define _MODEM_SEQIF_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXFRAMEDETOF_DEFAULT (_MODEM_SEQIF_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMNF (0x1UL << 15) /**< Timing not found */ +#define _MODEM_SEQIF_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */ +#define _MODEM_SEQIF_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */ +#define _MODEM_SEQIF_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXTIMNF_DEFAULT (_MODEM_SEQIF_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */ +#define _MODEM_SEQIF_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */ +#define _MODEM_SEQIF_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */ +#define _MODEM_SEQIF_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_FRCTIMOUT_DEFAULT (_MODEM_SEQIF_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_ETS (0x1UL << 17) /**< Early timestamp */ +#define _MODEM_SEQIF_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */ +#define _MODEM_SEQIF_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */ +#define _MODEM_SEQIF_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_ETS_DEFAULT (_MODEM_SEQIF_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */ +#define _MODEM_SEQIF_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */ +#define _MODEM_SEQIF_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */ +#define _MODEM_SEQIF_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_CFGANTPATTRD_DEFAULT (_MODEM_SEQIF_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */ +#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */ +#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQDET (0x1UL << 21) /**< SQ Detected */ +#define _MODEM_SEQIF_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */ +#define _MODEM_SEQIF_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */ +#define _MODEM_SEQIF_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQDET_DEFAULT (_MODEM_SEQIF_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQNOTDET (0x1UL << 22) /**< SQ NOT Detected */ +#define _MODEM_SEQIF_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */ +#define _MODEM_SEQIF_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */ +#define _MODEM_SEQIF_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQNOTDET_DEFAULT (_MODEM_SEQIF_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */ +#define _MODEM_SEQIF_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */ +#define _MODEM_SEQIF_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */ +#define _MODEM_SEQIF_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_ANTDIVRDY_DEFAULT (_MODEM_SEQIF_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */ +#define _MODEM_SEQIF_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */ +#define _MODEM_SEQIF_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */ +#define _MODEM_SEQIF_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SOFTRESETDONE_DEFAULT (_MODEM_SEQIF_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQPRENOTDET (0x1UL << 25) /**< SQ NOT Detected */ +#define _MODEM_SEQIF_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */ +#define _MODEM_SEQIF_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */ +#define _MODEM_SEQIF_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQPRENOTDET_DEFAULT (_MODEM_SEQIF_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQFRAMENOTDET (0x1UL << 26) /**< SQ NOT Detected */ +#define _MODEM_SEQIF_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */ +#define _MODEM_SEQIF_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */ +#define _MODEM_SEQIF_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQFRAMENOTDET_DEFAULT (_MODEM_SEQIF_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */ +#define _MODEM_SEQIF_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_SEQIF_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT (_MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SIDET (0x1UL << 28) /**< Signal identified */ +#define _MODEM_SEQIF_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */ +#define _MODEM_SEQIF_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */ +#define _MODEM_SEQIF_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SIDET_DEFAULT (_MODEM_SEQIF_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SIRESET (0x1UL << 29) /**< Signal identifier reset */ +#define _MODEM_SEQIF_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */ +#define _MODEM_SEQIF_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */ +#define _MODEM_SEQIF_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */ +#define MODEM_SEQIF_SIRESET_DEFAULT (_MODEM_SEQIF_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SEQIF */ + +/* Bit fields for MODEM SEQIEN */ +#define _MODEM_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for MODEM_SEQIEN */ +#define _MODEM_SEQIEN_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXFRAMESENT (0x1UL << 0) /**< Frame sent */ +#define _MODEM_SEQIEN_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */ +#define _MODEM_SEQIEN_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */ +#define _MODEM_SEQIEN_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXFRAMESENT_DEFAULT (_MODEM_SEQIEN_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */ +#define _MODEM_SEQIEN_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */ +#define _MODEM_SEQIEN_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */ +#define _MODEM_SEQIEN_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXSYNCSENT_DEFAULT (_MODEM_SEQIEN_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXPRESENT (0x1UL << 2) /**< Preamble sent */ +#define _MODEM_SEQIEN_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */ +#define _MODEM_SEQIEN_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */ +#define _MODEM_SEQIEN_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXPRESENT_DEFAULT (_MODEM_SEQIEN_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */ +#define _MODEM_SEQIEN_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */ +#define _MODEM_SEQIEN_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */ +#define _MODEM_SEQIEN_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_TXRAMPDONE_DEFAULT (_MODEM_SEQIEN_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */ +#define _MODEM_SEQIEN_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */ +#define _MODEM_SEQIEN_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */ +#define _MODEM_SEQIEN_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_LDTNOARR_DEFAULT (_MODEM_SEQIEN_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */ +#define _MODEM_SEQIEN_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */ +#define _MODEM_SEQIEN_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */ +#define _MODEM_SEQIEN_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHDSADET_DEFAULT (_MODEM_SEQIEN_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */ +#define _MODEM_SEQIEN_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */ +#define _MODEM_SEQIEN_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */ +#define _MODEM_SEQIEN_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHYUNCODEDET_DEFAULT (_MODEM_SEQIEN_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */ +#define _MODEM_SEQIEN_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */ +#define _MODEM_SEQIEN_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */ +#define _MODEM_SEQIEN_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_PHYCODEDET_DEFAULT (_MODEM_SEQIEN_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMDET (0x1UL << 8) /**< Timing detected */ +#define _MODEM_SEQIEN_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */ +#define _MODEM_SEQIEN_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */ +#define _MODEM_SEQIEN_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMDET_DEFAULT (_MODEM_SEQIEN_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXPREDET (0x1UL << 9) /**< Preamble detected */ +#define _MODEM_SEQIEN_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */ +#define _MODEM_SEQIEN_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */ +#define _MODEM_SEQIEN_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXPREDET_DEFAULT (_MODEM_SEQIEN_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */ +#define _MODEM_SEQIEN_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */ +#define _MODEM_SEQIEN_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */ +#define _MODEM_SEQIEN_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDET0_DEFAULT (_MODEM_SEQIEN_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */ +#define _MODEM_SEQIEN_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */ +#define _MODEM_SEQIEN_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */ +#define _MODEM_SEQIEN_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDET1_DEFAULT (_MODEM_SEQIEN_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMLOST (0x1UL << 12) /**< Timing lost */ +#define _MODEM_SEQIEN_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */ +#define _MODEM_SEQIEN_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */ +#define _MODEM_SEQIEN_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMLOST_DEFAULT (_MODEM_SEQIEN_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXPRELOST (0x1UL << 13) /**< Preamble lost */ +#define _MODEM_SEQIEN_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */ +#define _MODEM_SEQIEN_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */ +#define _MODEM_SEQIEN_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXPRELOST_DEFAULT (_MODEM_SEQIEN_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */ +#define _MODEM_SEQIEN_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */ +#define _MODEM_SEQIEN_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */ +#define _MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT (_MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMNF (0x1UL << 15) /**< Timing not found */ +#define _MODEM_SEQIEN_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */ +#define _MODEM_SEQIEN_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */ +#define _MODEM_SEQIEN_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXTIMNF_DEFAULT (_MODEM_SEQIEN_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */ +#define _MODEM_SEQIEN_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */ +#define _MODEM_SEQIEN_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */ +#define _MODEM_SEQIEN_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_FRCTIMOUT_DEFAULT (_MODEM_SEQIEN_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_ETS (0x1UL << 17) /**< Early time stamp */ +#define _MODEM_SEQIEN_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */ +#define _MODEM_SEQIEN_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */ +#define _MODEM_SEQIEN_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_ETS_DEFAULT (_MODEM_SEQIEN_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */ +#define _MODEM_SEQIEN_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */ +#define _MODEM_SEQIEN_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */ +#define _MODEM_SEQIEN_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_CFGANTPATTRD_DEFAULT (_MODEM_SEQIEN_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */ +#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQDET (0x1UL << 21) /**< SQ DET */ +#define _MODEM_SEQIEN_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */ +#define _MODEM_SEQIEN_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */ +#define _MODEM_SEQIEN_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQDET_DEFAULT (_MODEM_SEQIEN_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQNOTDET (0x1UL << 22) /**< SQ Not DET */ +#define _MODEM_SEQIEN_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */ +#define _MODEM_SEQIEN_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */ +#define _MODEM_SEQIEN_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQNOTDET_DEFAULT (_MODEM_SEQIEN_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */ +#define _MODEM_SEQIEN_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */ +#define _MODEM_SEQIEN_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */ +#define _MODEM_SEQIEN_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_ANTDIVRDY_DEFAULT (_MODEM_SEQIEN_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */ +#define _MODEM_SEQIEN_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */ +#define _MODEM_SEQIEN_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */ +#define _MODEM_SEQIEN_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SOFTRESETDONE_DEFAULT (_MODEM_SEQIEN_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQPRENOTDET (0x1UL << 25) /**< SQ Not DET */ +#define _MODEM_SEQIEN_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */ +#define _MODEM_SEQIEN_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */ +#define _MODEM_SEQIEN_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQPRENOTDET_DEFAULT (_MODEM_SEQIEN_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not DET */ +#define _MODEM_SEQIEN_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */ +#define _MODEM_SEQIEN_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */ +#define _MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT (_MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */ +#define _MODEM_SEQIEN_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_SEQIEN_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */ +#define _MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT (_MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SIDET (0x1UL << 28) /**< Signal Identified */ +#define _MODEM_SEQIEN_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */ +#define _MODEM_SEQIEN_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */ +#define _MODEM_SEQIEN_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SIDET_DEFAULT (_MODEM_SEQIEN_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SIRESET (0x1UL << 29) /**< Signal identifier reset */ +#define _MODEM_SEQIEN_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */ +#define _MODEM_SEQIEN_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */ +#define _MODEM_SEQIEN_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */ +#define MODEM_SEQIEN_SIRESET_DEFAULT (_MODEM_SEQIEN_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SEQIEN */ + +/* Bit fields for MODEM STATUS */ +#define _MODEM_STATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS */ +#define _MODEM_STATUS_MASK 0xFFFFFFFFUL /**< Mask for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_SHIFT 0 /**< Shift value for MODEM_DEMODSTATE */ +#define _MODEM_STATUS_DEMODSTATE_MASK 0x7UL /**< Bit mask for MODEM_DEMODSTATE */ +#define _MODEM_STATUS_DEMODSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_OFF 0x00000000UL /**< Mode OFF for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_TIMINGSEARCH 0x00000001UL /**< Mode TIMINGSEARCH for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_PRESEARCH 0x00000002UL /**< Mode PRESEARCH for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_FRAMESEARCH 0x00000003UL /**< Mode FRAMESEARCH for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_RXFRAME 0x00000004UL /**< Mode RXFRAME for MODEM_STATUS */ +#define _MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 0x00000005UL /**< Mode FRAMEDETMODE0 for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_DEFAULT (_MODEM_STATUS_DEMODSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_OFF (_MODEM_STATUS_DEMODSTATE_OFF << 0) /**< Shifted mode OFF for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_TIMINGSEARCH (_MODEM_STATUS_DEMODSTATE_TIMINGSEARCH << 0) /**< Shifted mode TIMINGSEARCH for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_PRESEARCH (_MODEM_STATUS_DEMODSTATE_PRESEARCH << 0) /**< Shifted mode PRESEARCH for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_FRAMESEARCH (_MODEM_STATUS_DEMODSTATE_FRAMESEARCH << 0) /**< Shifted mode FRAMESEARCH for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_RXFRAME (_MODEM_STATUS_DEMODSTATE_RXFRAME << 0) /**< Shifted mode RXFRAME for MODEM_STATUS */ +#define MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 (_MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 << 0) /**< Shifted mode FRAMEDETMODE0 for MODEM_STATUS */ +#define MODEM_STATUS_BCRCFEDSADET (0x1UL << 3) /**< BCR CFE DSA DETECTION */ +#define _MODEM_STATUS_BCRCFEDSADET_SHIFT 3 /**< Shift value for MODEM_BCRCFEDSADET */ +#define _MODEM_STATUS_BCRCFEDSADET_MASK 0x8UL /**< Bit mask for MODEM_BCRCFEDSADET */ +#define _MODEM_STATUS_BCRCFEDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_BCRCFEDSADET_DEFAULT (_MODEM_STATUS_BCRCFEDSADET_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_FRAMEDETID (0x1UL << 4) /**< Frame Detected ID */ +#define _MODEM_STATUS_FRAMEDETID_SHIFT 4 /**< Shift value for MODEM_FRAMEDETID */ +#define _MODEM_STATUS_FRAMEDETID_MASK 0x10UL /**< Bit mask for MODEM_FRAMEDETID */ +#define _MODEM_STATUS_FRAMEDETID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_FRAMEDETID_FRAMEDET0 0x00000000UL /**< Mode FRAMEDET0 for MODEM_STATUS */ +#define _MODEM_STATUS_FRAMEDETID_FRAMEDET1 0x00000001UL /**< Mode FRAMEDET1 for MODEM_STATUS */ +#define MODEM_STATUS_FRAMEDETID_DEFAULT (_MODEM_STATUS_FRAMEDETID_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_FRAMEDETID_FRAMEDET0 (_MODEM_STATUS_FRAMEDETID_FRAMEDET0 << 4) /**< Shifted mode FRAMEDET0 for MODEM_STATUS */ +#define MODEM_STATUS_FRAMEDETID_FRAMEDET1 (_MODEM_STATUS_FRAMEDETID_FRAMEDET1 << 4) /**< Shifted mode FRAMEDET1 for MODEM_STATUS */ +#define MODEM_STATUS_ANTSEL (0x1UL << 5) /**< Selected Antenna */ +#define _MODEM_STATUS_ANTSEL_SHIFT 5 /**< Shift value for MODEM_ANTSEL */ +#define _MODEM_STATUS_ANTSEL_MASK 0x20UL /**< Bit mask for MODEM_ANTSEL */ +#define _MODEM_STATUS_ANTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_ANTSEL_ANTENNA0 0x00000000UL /**< Mode ANTENNA0 for MODEM_STATUS */ +#define _MODEM_STATUS_ANTSEL_ANTENNA1 0x00000001UL /**< Mode ANTENNA1 for MODEM_STATUS */ +#define MODEM_STATUS_ANTSEL_DEFAULT (_MODEM_STATUS_ANTSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_ANTSEL_ANTENNA0 (_MODEM_STATUS_ANTSEL_ANTENNA0 << 5) /**< Shifted mode ANTENNA0 for MODEM_STATUS */ +#define MODEM_STATUS_ANTSEL_ANTENNA1 (_MODEM_STATUS_ANTSEL_ANTENNA1 << 5) /**< Shifted mode ANTENNA1 for MODEM_STATUS */ +#define MODEM_STATUS_TIMSEQINV (0x1UL << 6) /**< Timing Sequence Inverted */ +#define _MODEM_STATUS_TIMSEQINV_SHIFT 6 /**< Shift value for MODEM_TIMSEQINV */ +#define _MODEM_STATUS_TIMSEQINV_MASK 0x40UL /**< Bit mask for MODEM_TIMSEQINV */ +#define _MODEM_STATUS_TIMSEQINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_TIMSEQINV_DEFAULT (_MODEM_STATUS_TIMSEQINV_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_TIMLOSTCAUSE (0x1UL << 7) /**< Timing Lost Cause */ +#define _MODEM_STATUS_TIMLOSTCAUSE_SHIFT 7 /**< Shift value for MODEM_TIMLOSTCAUSE */ +#define _MODEM_STATUS_TIMLOSTCAUSE_MASK 0x80UL /**< Bit mask for MODEM_TIMLOSTCAUSE */ +#define _MODEM_STATUS_TIMLOSTCAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_TIMLOSTCAUSE_LOWCORR 0x00000000UL /**< Mode LOWCORR for MODEM_STATUS */ +#define _MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT 0x00000001UL /**< Mode TIMEOUT for MODEM_STATUS */ +#define MODEM_STATUS_TIMLOSTCAUSE_DEFAULT (_MODEM_STATUS_TIMLOSTCAUSE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_TIMLOSTCAUSE_LOWCORR (_MODEM_STATUS_TIMLOSTCAUSE_LOWCORR << 7) /**< Shifted mode LOWCORR for MODEM_STATUS */ +#define MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT (_MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT << 7) /**< Shifted mode TIMEOUT for MODEM_STATUS */ +#define MODEM_STATUS_DSADETECTED (0x1UL << 8) /**< PHASE-DSA detected */ +#define _MODEM_STATUS_DSADETECTED_SHIFT 8 /**< Shift value for MODEM_DSADETECTED */ +#define _MODEM_STATUS_DSADETECTED_MASK 0x100UL /**< Bit mask for MODEM_DSADETECTED */ +#define _MODEM_STATUS_DSADETECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_DSADETECTED_DEFAULT (_MODEM_STATUS_DSADETECTED_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_DSAFREQESTDONE (0x1UL << 9) /**< DSA frequency estimation complete */ +#define _MODEM_STATUS_DSAFREQESTDONE_SHIFT 9 /**< Shift value for MODEM_DSAFREQESTDONE */ +#define _MODEM_STATUS_DSAFREQESTDONE_MASK 0x200UL /**< Bit mask for MODEM_DSAFREQESTDONE */ +#define _MODEM_STATUS_DSAFREQESTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_DSAFREQESTDONE_DEFAULT (_MODEM_STATUS_DSAFREQESTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_VITERBIDEMODTIMDET (0x1UL << 10) /**< Viterbi Demod timing detected */ +#define _MODEM_STATUS_VITERBIDEMODTIMDET_SHIFT 10 /**< Shift value for MODEM_VITERBIDEMODTIMDET */ +#define _MODEM_STATUS_VITERBIDEMODTIMDET_MASK 0x400UL /**< Bit mask for MODEM_VITERBIDEMODTIMDET */ +#define _MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT (_MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_VITERBIDEMODFRAMEDET (0x1UL << 11) /**< Viterbi Demod frame detected */ +#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_SHIFT 11 /**< Shift value for MODEM_VITERBIDEMODFRAMEDET */ +#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_MASK 0x800UL /**< Bit mask for MODEM_VITERBIDEMODFRAMEDET */ +#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT (_MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_STAMPSTATE_SHIFT 12 /**< Shift value for MODEM_STAMPSTATE */ +#define _MODEM_STATUS_STAMPSTATE_MASK 0x7000UL /**< Bit mask for MODEM_STAMPSTATE */ +#define _MODEM_STATUS_STAMPSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_STAMPSTATE_DEFAULT (_MODEM_STATUS_STAMPSTATE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_TRECSDSAADET (0x1UL << 15) /**< TRECS DSA DETECTION */ +#define _MODEM_STATUS_TRECSDSAADET_SHIFT 15 /**< Shift value for MODEM_TRECSDSAADET */ +#define _MODEM_STATUS_TRECSDSAADET_MASK 0x8000UL /**< Bit mask for MODEM_TRECSDSAADET */ +#define _MODEM_STATUS_TRECSDSAADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_TRECSDSAADET_DEFAULT (_MODEM_STATUS_TRECSDSAADET_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_CORR_SHIFT 16 /**< Shift value for MODEM_CORR */ +#define _MODEM_STATUS_CORR_MASK 0xFF0000UL /**< Bit mask for MODEM_CORR */ +#define _MODEM_STATUS_CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_CORR_DEFAULT (_MODEM_STATUS_CORR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_STATUS */ +#define _MODEM_STATUS_WEAKSYMBOLS_SHIFT 24 /**< Shift value for MODEM_WEAKSYMBOLS */ +#define _MODEM_STATUS_WEAKSYMBOLS_MASK 0xFF000000UL /**< Bit mask for MODEM_WEAKSYMBOLS */ +#define _MODEM_STATUS_WEAKSYMBOLS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */ +#define MODEM_STATUS_WEAKSYMBOLS_DEFAULT (_MODEM_STATUS_WEAKSYMBOLS_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_STATUS */ + +/* Bit fields for MODEM STATUS2 */ +#define _MODEM_STATUS2_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS2 */ +#define _MODEM_STATUS2_MASK 0xFFFCFFFFUL /**< Mask for MODEM_STATUS2 */ +#define _MODEM_STATUS2_CHPWRACCUMUX_SHIFT 0 /**< Shift value for MODEM_CHPWRACCUMUX */ +#define _MODEM_STATUS2_CHPWRACCUMUX_MASK 0xFFUL /**< Bit mask for MODEM_CHPWRACCUMUX */ +#define _MODEM_STATUS2_CHPWRACCUMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_CHPWRACCUMUX_DEFAULT (_MODEM_STATUS2_CHPWRACCUMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ +#define _MODEM_STATUS2_BBSSMUX_SHIFT 8 /**< Shift value for MODEM_BBSSMUX */ +#define _MODEM_STATUS2_BBSSMUX_MASK 0xF00UL /**< Bit mask for MODEM_BBSSMUX */ +#define _MODEM_STATUS2_BBSSMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_BBSSMUX_DEFAULT (_MODEM_STATUS2_BBSSMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ +#define _MODEM_STATUS2_LRBLECI_SHIFT 12 /**< Shift value for MODEM_LRBLECI */ +#define _MODEM_STATUS2_LRBLECI_MASK 0x3000UL /**< Bit mask for MODEM_LRBLECI */ +#define _MODEM_STATUS2_LRBLECI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define _MODEM_STATUS2_LRBLECI_LR125k 0x00000000UL /**< Mode LR125k for MODEM_STATUS2 */ +#define _MODEM_STATUS2_LRBLECI_LR500k 0x00000001UL /**< Mode LR500k for MODEM_STATUS2 */ +#define MODEM_STATUS2_LRBLECI_DEFAULT (_MODEM_STATUS2_LRBLECI_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_LRBLECI_LR125k (_MODEM_STATUS2_LRBLECI_LR125k << 12) /**< Shifted mode LR125k for MODEM_STATUS2 */ +#define MODEM_STATUS2_LRBLECI_LR500k (_MODEM_STATUS2_LRBLECI_LR500k << 12) /**< Shifted mode LR500k for MODEM_STATUS2 */ +#define MODEM_STATUS2_UNCODEDPHY (0x1UL << 14) /**< UNCODED PHY DET */ +#define _MODEM_STATUS2_UNCODEDPHY_SHIFT 14 /**< Shift value for MODEM_UNCODEDPHY */ +#define _MODEM_STATUS2_UNCODEDPHY_MASK 0x4000UL /**< Bit mask for MODEM_UNCODEDPHY */ +#define _MODEM_STATUS2_UNCODEDPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_UNCODEDPHY_DEFAULT (_MODEM_STATUS2_UNCODEDPHY_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_CODEDPHY (0x1UL << 15) /**< CODED PHY DET */ +#define _MODEM_STATUS2_CODEDPHY_SHIFT 15 /**< Shift value for MODEM_CODEDPHY */ +#define _MODEM_STATUS2_CODEDPHY_MASK 0x8000UL /**< Bit mask for MODEM_CODEDPHY */ +#define _MODEM_STATUS2_CODEDPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_CODEDPHY_DEFAULT (_MODEM_STATUS2_CODEDPHY_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ +#define _MODEM_STATUS2_RTCOST_SHIFT 18 /**< Shift value for MODEM_RTCOST */ +#define _MODEM_STATUS2_RTCOST_MASK 0xFFFC0000UL /**< Bit mask for MODEM_RTCOST */ +#define _MODEM_STATUS2_RTCOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */ +#define MODEM_STATUS2_RTCOST_DEFAULT (_MODEM_STATUS2_RTCOST_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_STATUS2 */ + +/* Bit fields for MODEM STATUS3 */ +#define _MODEM_STATUS3_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS3 */ +#define _MODEM_STATUS3_MASK 0x0FFFFFFFUL /**< Mask for MODEM_STATUS3 */ +#define _MODEM_STATUS3_BBPFOUTABS1_SHIFT 0 /**< Shift value for MODEM_BBPFOUTABS1 */ +#define _MODEM_STATUS3_BBPFOUTABS1_MASK 0x7FFUL /**< Bit mask for MODEM_BBPFOUTABS1 */ +#define _MODEM_STATUS3_BBPFOUTABS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_BBPFOUTABS1_DEFAULT (_MODEM_STATUS3_BBPFOUTABS1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define _MODEM_STATUS3_BBPFOUTABS_SHIFT 11 /**< Shift value for MODEM_BBPFOUTABS */ +#define _MODEM_STATUS3_BBPFOUTABS_MASK 0x3FF800UL /**< Bit mask for MODEM_BBPFOUTABS */ +#define _MODEM_STATUS3_BBPFOUTABS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_BBPFOUTABS_DEFAULT (_MODEM_STATUS3_BBPFOUTABS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_LRDSALIVE (0x1UL << 22) /**< BLRDSA Prefilter above LRSPIKETHD */ +#define _MODEM_STATUS3_LRDSALIVE_SHIFT 22 /**< Shift value for MODEM_LRDSALIVE */ +#define _MODEM_STATUS3_LRDSALIVE_MASK 0x400000UL /**< Bit mask for MODEM_LRDSALIVE */ +#define _MODEM_STATUS3_LRDSALIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_LRDSALIVE_DEFAULT (_MODEM_STATUS3_LRDSALIVE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_COHDSALIVE (0x1UL << 23) /**< COHDSA Prefilter above CDTH */ +#define _MODEM_STATUS3_COHDSALIVE_SHIFT 23 /**< Shift value for MODEM_COHDSALIVE */ +#define _MODEM_STATUS3_COHDSALIVE_MASK 0x800000UL /**< Bit mask for MODEM_COHDSALIVE */ +#define _MODEM_STATUS3_COHDSALIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_COHDSALIVE_DEFAULT (_MODEM_STATUS3_COHDSALIVE_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_LRDSADET (0x1UL << 24) /**< DSA prefilter above LRSPIKETHD */ +#define _MODEM_STATUS3_LRDSADET_SHIFT 24 /**< Shift value for MODEM_LRDSADET */ +#define _MODEM_STATUS3_LRDSADET_MASK 0x1000000UL /**< Bit mask for MODEM_LRDSADET */ +#define _MODEM_STATUS3_LRDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_LRDSADET_DEFAULT (_MODEM_STATUS3_LRDSADET_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_COHDSADET (0x1UL << 25) /**< DSA prefilter above CDTH */ +#define _MODEM_STATUS3_COHDSADET_SHIFT 25 /**< Shift value for MODEM_COHDSADET */ +#define _MODEM_STATUS3_COHDSADET_MASK 0x2000000UL /**< Bit mask for MODEM_COHDSADET */ +#define _MODEM_STATUS3_COHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_COHDSADET_DEFAULT (_MODEM_STATUS3_COHDSADET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_SYNCSECPEAKABTH (0x1UL << 26) /**< SYNC second peak above threshold */ +#define _MODEM_STATUS3_SYNCSECPEAKABTH_SHIFT 26 /**< Shift value for MODEM_SYNCSECPEAKABTH */ +#define _MODEM_STATUS3_SYNCSECPEAKABTH_MASK 0x4000000UL /**< Bit mask for MODEM_SYNCSECPEAKABTH */ +#define _MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT (_MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_SOFTRSTDONE (0x1UL << 27) /**< Soft reset done */ +#define _MODEM_STATUS3_SOFTRSTDONE_SHIFT 27 /**< Shift value for MODEM_SOFTRSTDONE */ +#define _MODEM_STATUS3_SOFTRSTDONE_MASK 0x8000000UL /**< Bit mask for MODEM_SOFTRSTDONE */ +#define _MODEM_STATUS3_SOFTRSTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */ +#define MODEM_STATUS3_SOFTRSTDONE_DEFAULT (_MODEM_STATUS3_SOFTRSTDONE_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_STATUS3 */ + +/* Bit fields for MODEM STATUS4 */ +#define _MODEM_STATUS4_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS4 */ +#define _MODEM_STATUS4_MASK 0x01FF01FFUL /**< Mask for MODEM_STATUS4 */ +#define _MODEM_STATUS4_ANT0RSSI_SHIFT 0 /**< Shift value for MODEM_ANT0RSSI */ +#define _MODEM_STATUS4_ANT0RSSI_MASK 0x1FFUL /**< Bit mask for MODEM_ANT0RSSI */ +#define _MODEM_STATUS4_ANT0RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS4 */ +#define MODEM_STATUS4_ANT0RSSI_DEFAULT (_MODEM_STATUS4_ANT0RSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS4 */ +#define _MODEM_STATUS4_ANT1RSSI_SHIFT 16 /**< Shift value for MODEM_ANT1RSSI */ +#define _MODEM_STATUS4_ANT1RSSI_MASK 0x1FF0000UL /**< Bit mask for MODEM_ANT1RSSI */ +#define _MODEM_STATUS4_ANT1RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS4 */ +#define MODEM_STATUS4_ANT1RSSI_DEFAULT (_MODEM_STATUS4_ANT1RSSI_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_STATUS4 */ + +/* Bit fields for MODEM STATUS5 */ +#define _MODEM_STATUS5_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS5 */ +#define _MODEM_STATUS5_MASK 0x000001FFUL /**< Mask for MODEM_STATUS5 */ +#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_SHIFT 0 /**< Shift value for MODEM_RXRESTARTMAFLTDOUT */ +#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_MASK 0x1FFUL /**< Bit mask for MODEM_RXRESTARTMAFLTDOUT */ +#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS5 */ +#define MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT (_MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS5 */ + +/* Bit fields for MODEM STATUS6 */ +#define _MODEM_STATUS6_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS6 */ +#define _MODEM_STATUS6_MASK 0xC00FFFFFUL /**< Mask for MODEM_STATUS6 */ +#define _MODEM_STATUS6_ANT0CORR_SHIFT 0 /**< Shift value for MODEM_ANT0CORR */ +#define _MODEM_STATUS6_ANT0CORR_MASK 0x3FFUL /**< Bit mask for MODEM_ANT0CORR */ +#define _MODEM_STATUS6_ANT0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT0CORR_DEFAULT (_MODEM_STATUS6_ANT0CORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS6 */ +#define _MODEM_STATUS6_ANT1CORR_SHIFT 10 /**< Shift value for MODEM_ANT1CORR */ +#define _MODEM_STATUS6_ANT1CORR_MASK 0xFFC00UL /**< Bit mask for MODEM_ANT1CORR */ +#define _MODEM_STATUS6_ANT1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT1CORR_DEFAULT (_MODEM_STATUS6_ANT1CORR_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT0OUT (0x1UL << 30) /**< ANT0 OUTPUT */ +#define _MODEM_STATUS6_ANT0OUT_SHIFT 30 /**< Shift value for MODEM_ANT0OUT */ +#define _MODEM_STATUS6_ANT0OUT_MASK 0x40000000UL /**< Bit mask for MODEM_ANT0OUT */ +#define _MODEM_STATUS6_ANT0OUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT0OUT_DEFAULT (_MODEM_STATUS6_ANT0OUT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT1OUT (0x1UL << 31) /**< ANT1 OUTPUT */ +#define _MODEM_STATUS6_ANT1OUT_SHIFT 31 /**< Shift value for MODEM_ANT1OUT */ +#define _MODEM_STATUS6_ANT1OUT_MASK 0x80000000UL /**< Bit mask for MODEM_ANT1OUT */ +#define _MODEM_STATUS6_ANT1OUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */ +#define MODEM_STATUS6_ANT1OUT_DEFAULT (_MODEM_STATUS6_ANT1OUT_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_STATUS6 */ + +/* Bit fields for MODEM STATUS7 */ +#define _MODEM_STATUS7_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS7 */ +#define _MODEM_STATUS7_MASK 0xBFFFFFFFUL /**< Mask for MODEM_STATUS7 */ +#define _MODEM_STATUS7_FDEVEST_SHIFT 0 /**< Shift value for MODEM_FDEVEST */ +#define _MODEM_STATUS7_FDEVEST_MASK 0x3FUL /**< Bit mask for MODEM_FDEVEST */ +#define _MODEM_STATUS7_FDEVEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_FDEVEST_DEFAULT (_MODEM_STATUS7_FDEVEST_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS7 */ +#define _MODEM_STATUS7_DEMODSOFT_SHIFT 6 /**< Shift value for MODEM_DEMODSOFT */ +#define _MODEM_STATUS7_DEMODSOFT_MASK 0x7FFC0UL /**< Bit mask for MODEM_DEMODSOFT */ +#define _MODEM_STATUS7_DEMODSOFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_DEMODSOFT_DEFAULT (_MODEM_STATUS7_DEMODSOFT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_STATUS7 */ +#define _MODEM_STATUS7_CFEPHDIFF_SHIFT 19 /**< Shift value for MODEM_CFEPHDIFF */ +#define _MODEM_STATUS7_CFEPHDIFF_MASK 0x1FF80000UL /**< Bit mask for MODEM_CFEPHDIFF */ +#define _MODEM_STATUS7_CFEPHDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_CFEPHDIFF_DEFAULT (_MODEM_STATUS7_CFEPHDIFF_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_MINCOSTPASS (0x1UL << 29) /**< Min.COST Threshold Pass */ +#define _MODEM_STATUS7_MINCOSTPASS_SHIFT 29 /**< Shift value for MODEM_MINCOSTPASS */ +#define _MODEM_STATUS7_MINCOSTPASS_MASK 0x20000000UL /**< Bit mask for MODEM_MINCOSTPASS */ +#define _MODEM_STATUS7_MINCOSTPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_MINCOSTPASS_DEFAULT (_MODEM_STATUS7_MINCOSTPASS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_CFEDSADET (0x1UL << 31) /**< CFE-based DSA Detection */ +#define _MODEM_STATUS7_CFEDSADET_SHIFT 31 /**< Shift value for MODEM_CFEDSADET */ +#define _MODEM_STATUS7_CFEDSADET_MASK 0x80000000UL /**< Bit mask for MODEM_CFEDSADET */ +#define _MODEM_STATUS7_CFEDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */ +#define MODEM_STATUS7_CFEDSADET_DEFAULT (_MODEM_STATUS7_CFEDSADET_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_STATUS7 */ + +/* Bit fields for MODEM TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_MASK 0x1F0FFFFFUL /**< Mask for MODEM_TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_TIMDETCORR_SHIFT 0 /**< Shift value for MODEM_TIMDETCORR */ +#define _MODEM_TIMDETSTATUS_TIMDETCORR_MASK 0xFFUL /**< Bit mask for MODEM_TIMDETCORR */ +#define _MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_SHIFT 8 /**< Shift value for MODEM_TIMDETFREQOFFEST */ +#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_MASK 0xFF00UL /**< Bit mask for MODEM_TIMDETFREQOFFEST */ +#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_SHIFT 16 /**< Shift value for MODEM_TIMDETPREERRORS */ +#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_MASK 0xF0000UL /**< Bit mask for MODEM_TIMDETPREERRORS */ +#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETPASS (0x1UL << 24) /**< Timing detection pass */ +#define _MODEM_TIMDETSTATUS_TIMDETPASS_SHIFT 24 /**< Shift value for MODEM_TIMDETPASS */ +#define _MODEM_TIMDETSTATUS_TIMDETPASS_MASK 0x1000000UL /**< Bit mask for MODEM_TIMDETPASS */ +#define _MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */ +#define _MODEM_TIMDETSTATUS_TIMDETINDEX_SHIFT 25 /**< Shift value for MODEM_TIMDETINDEX */ +#define _MODEM_TIMDETSTATUS_TIMDETINDEX_MASK 0x1E000000UL /**< Bit mask for MODEM_TIMDETINDEX */ +#define _MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */ +#define MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */ + +/* Bit fields for MODEM FSMSTATUS */ +#define _MODEM_FSMSTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_MASK 0x00FFFFFFUL /**< Mask for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_SHIFT 0 /**< Shift value for MODEM_DETSTATE */ +#define _MODEM_FSMSTATUS_DETSTATE_MASK 0x7FUL /**< Bit mask for MODEM_DETSTATE */ +#define _MODEM_FSMSTATUS_DETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_OFF 0x00000000UL /**< Mode OFF for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH 0x0000000AUL /**< Mode TIMINGSEARCH for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_PRESEARCH 0x00000014UL /**< Mode PRESEARCH for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH 0x0000001EUL /**< Mode FRAMESEARCH for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_RXFRAME 0x00000028UL /**< Mode RXFRAME for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 0x00000032UL /**< Mode FRAMEDETMODE0 for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DETSTATE_DEFAULT (_MODEM_FSMSTATUS_DETSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DETSTATE_OFF (_MODEM_FSMSTATUS_DETSTATE_OFF << 0) /**< Shifted mode OFF for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH (_MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH << 0) /**< Shifted mode TIMINGSEARCH for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_DETSTATE_PRESEARCH (_MODEM_FSMSTATUS_DETSTATE_PRESEARCH << 0) /**< Shifted mode PRESEARCH for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH (_MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH << 0) /**< Shifted mode FRAMESEARCH for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_DETSTATE_RXFRAME (_MODEM_FSMSTATUS_DETSTATE_RXFRAME << 0) /**< Shifted mode RXFRAME for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 (_MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 << 0) /**< Shifted mode FRAMEDETMODE0 for MODEM_FSMSTATUS*/ +#define _MODEM_FSMSTATUS_DSASTATE_SHIFT 7 /**< Shift value for MODEM_DSASTATE */ +#define _MODEM_FSMSTATUS_DSASTATE_MASK 0x380UL /**< Bit mask for MODEM_DSASTATE */ +#define _MODEM_FSMSTATUS_DSASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK 0x00000001UL /**< Mode ARRIVALCHK for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_STATUSCHK 0x00000002UL /**< Mode STATUSCHK for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_SAMPPW 0x00000003UL /**< Mode SAMPPW for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_WAITPWRUP 0x00000004UL /**< Mode WAITPWRUP for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_WAITDSALO 0x00000005UL /**< Mode WAITDSALO for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_WAITABORT 0x00000006UL /**< Mode WAITABORT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_DSASTATE_STOP 0x00000007UL /**< Mode STOP for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_DEFAULT (_MODEM_FSMSTATUS_DSASTATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_IDLE (_MODEM_FSMSTATUS_DSASTATE_IDLE << 7) /**< Shifted mode IDLE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK (_MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK << 7) /**< Shifted mode ARRIVALCHK for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_STATUSCHK (_MODEM_FSMSTATUS_DSASTATE_STATUSCHK << 7) /**< Shifted mode STATUSCHK for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_SAMPPW (_MODEM_FSMSTATUS_DSASTATE_SAMPPW << 7) /**< Shifted mode SAMPPW for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_WAITPWRUP (_MODEM_FSMSTATUS_DSASTATE_WAITPWRUP << 7) /**< Shifted mode WAITPWRUP for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_WAITDSALO (_MODEM_FSMSTATUS_DSASTATE_WAITDSALO << 7) /**< Shifted mode WAITDSALO for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_WAITABORT (_MODEM_FSMSTATUS_DSASTATE_WAITABORT << 7) /**< Shifted mode WAITABORT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_DSASTATE_STOP (_MODEM_FSMSTATUS_DSASTATE_STOP << 7) /**< Shifted mode STOP for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_SHIFT 10 /**< Shift value for MODEM_LRBLESTATE */ +#define _MODEM_FSMSTATUS_LRBLESTATE_MASK 0x7C00UL /**< Bit mask for MODEM_LRBLESTATE */ +#define _MODEM_FSMSTATUS_LRBLESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_CLEANUP 0x00000001UL /**< Mode CLEANUP for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_CORRCOE 0x00000002UL /**< Mode CORRCOE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA 0x00000003UL /**< Mode WAITLRDSA for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_MAXCORR 0x00000004UL /**< Mode MAXCORR for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_WAITRDY 0x00000005UL /**< Mode WAITRDY for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA 0x00000006UL /**< Mode FEC1DATA for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK 0x00000007UL /**< Mode FEC1ACK for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_PAUSE 0x00000008UL /**< Mode PAUSE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA 0x00000009UL /**< Mode FEC2DATA for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK 0x0000000AUL /**< Mode FEC2ACK for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR 0x0000000BUL /**< Mode TRACKCUR for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR 0x0000000CUL /**< Mode TRACKEAR for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT 0x0000000DUL /**< Mode TRACKLAT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE 0x0000000EUL /**< Mode TRACKDONE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_TDECISION 0x0000000FUL /**< Mode TDECISION for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_LRBLESTATE_STOP 0x00000010UL /**< Mode STOP for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_DEFAULT (_MODEM_FSMSTATUS_LRBLESTATE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_IDLE (_MODEM_FSMSTATUS_LRBLESTATE_IDLE << 10) /**< Shifted mode IDLE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_CLEANUP (_MODEM_FSMSTATUS_LRBLESTATE_CLEANUP << 10) /**< Shifted mode CLEANUP for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_CORRCOE (_MODEM_FSMSTATUS_LRBLESTATE_CORRCOE << 10) /**< Shifted mode CORRCOE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA (_MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA << 10) /**< Shifted mode WAITLRDSA for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_MAXCORR (_MODEM_FSMSTATUS_LRBLESTATE_MAXCORR << 10) /**< Shifted mode MAXCORR for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_WAITRDY (_MODEM_FSMSTATUS_LRBLESTATE_WAITRDY << 10) /**< Shifted mode WAITRDY for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA (_MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA << 10) /**< Shifted mode FEC1DATA for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK (_MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK << 10) /**< Shifted mode FEC1ACK for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_PAUSE (_MODEM_FSMSTATUS_LRBLESTATE_PAUSE << 10) /**< Shifted mode PAUSE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA (_MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA << 10) /**< Shifted mode FEC2DATA for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK (_MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK << 10) /**< Shifted mode FEC2ACK for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR (_MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR << 10) /**< Shifted mode TRACKCUR for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR (_MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR << 10) /**< Shifted mode TRACKEAR for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT (_MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT << 10) /**< Shifted mode TRACKLAT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE (_MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE << 10) /**< Shifted mode TRACKDONE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_TDECISION (_MODEM_FSMSTATUS_LRBLESTATE_TDECISION << 10) /**< Shifted mode TDECISION for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_LRBLESTATE_STOP (_MODEM_FSMSTATUS_LRBLESTATE_STOP << 10) /**< Shifted mode STOP for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_SHIFT 15 /**< Shift value for MODEM_NBBLESTATE */ +#define _MODEM_FSMSTATUS_NBBLESTATE_MASK 0xF8000UL /**< Bit mask for MODEM_NBBLESTATE */ +#define _MODEM_FSMSTATUS_NBBLESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_VTINITI 0x00000001UL /**< Mode VTINITI for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT 0x00000002UL /**< Mode ADDRNXT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_INICOST 0x00000003UL /**< Mode INICOST for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_CALCCOST 0x00000004UL /**< Mode CALCCOST for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_INITALACQU 0x00000005UL /**< Mode INITALACQU for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC 0x00000006UL /**< Mode INITALCOSTCALC for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC 0x00000007UL /**< Mode MINCOSTCALC for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_FREQACQU 0x00000008UL /**< Mode FREQACQU for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE 0x00000009UL /**< Mode FREQACQUDONE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY 0x0000000AUL /**< Mode TIMINGACQUEARLY for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR 0x0000000BUL /**< Mode TIMINGACQUCURR for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE 0x0000000CUL /**< Mode TIMINGACQULATE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE 0x0000000DUL /**< Mode TIMINGACQUDONE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 0x0000000EUL /**< Mode VIRTBIINIT0 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 0x0000000FUL /**< Mode VIRTBIINIT1 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC 0x00000010UL /**< Mode VIRTBIRXSYNC for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD 0x00000011UL /**< Mode VIRTBIRXPAYLOAD for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC 0x00000012UL /**< Mode HARDRXSYNC for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD 0x00000013UL /**< Mode HARDXPAYLOAD for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ 0x00000014UL /**< Mode TRACKFREQ for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY 0x00000015UL /**< Mode TRACKTIMEARLY for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR 0x00000016UL /**< Mode TRACKTIMCURR for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE 0x00000017UL /**< Mode TRACKTIMLATE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE 0x00000018UL /**< Mode TRACKDONE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION 0x00000019UL /**< Mode TRACKDECISION for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_STOP 0x0000001AUL /**< Mode STOP for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_WAITACK 0x0000001BUL /**< Mode WAITACK for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_NBBLESTATE_DEBUG 0x0000001CUL /**< Mode DEBUG for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_DEFAULT (_MODEM_FSMSTATUS_NBBLESTATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_IDLE (_MODEM_FSMSTATUS_NBBLESTATE_IDLE << 15) /**< Shifted mode IDLE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_VTINITI (_MODEM_FSMSTATUS_NBBLESTATE_VTINITI << 15) /**< Shifted mode VTINITI for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT (_MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT << 15) /**< Shifted mode ADDRNXT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_INICOST (_MODEM_FSMSTATUS_NBBLESTATE_INICOST << 15) /**< Shifted mode INICOST for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_CALCCOST (_MODEM_FSMSTATUS_NBBLESTATE_CALCCOST << 15) /**< Shifted mode CALCCOST for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_INITALACQU (_MODEM_FSMSTATUS_NBBLESTATE_INITALACQU << 15) /**< Shifted mode INITALACQU for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC (_MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC << 15) /**< Shifted mode INITALCOSTCALC for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC (_MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC << 15) /**< Shifted mode MINCOSTCALC for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_FREQACQU (_MODEM_FSMSTATUS_NBBLESTATE_FREQACQU << 15) /**< Shifted mode FREQACQU for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE (_MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE << 15) /**< Shifted mode FREQACQUDONE for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY << 15) /**< Shifted mode TIMINGACQUEARLY for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR << 15) /**< Shifted mode TIMINGACQUCURR for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE << 15) /**< Shifted mode TIMINGACQULATE for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE << 15) /**< Shifted mode TIMINGACQUDONE for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 << 15) /**< Shifted mode VIRTBIINIT0 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 << 15) /**< Shifted mode VIRTBIINIT1 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC << 15) /**< Shifted mode VIRTBIRXSYNC for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD << 15) /**< Shifted mode VIRTBIRXPAYLOAD for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC (_MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC << 15) /**< Shifted mode HARDRXSYNC for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD (_MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD << 15) /**< Shifted mode HARDXPAYLOAD for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ (_MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ << 15) /**< Shifted mode TRACKFREQ for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY << 15) /**< Shifted mode TRACKTIMEARLY for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR << 15) /**< Shifted mode TRACKTIMCURR for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE << 15) /**< Shifted mode TRACKTIMLATE for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE (_MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE << 15) /**< Shifted mode TRACKDONE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION (_MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION << 15) /**< Shifted mode TRACKDECISION for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_NBBLESTATE_STOP (_MODEM_FSMSTATUS_NBBLESTATE_STOP << 15) /**< Shifted mode STOP for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_WAITACK (_MODEM_FSMSTATUS_NBBLESTATE_WAITACK << 15) /**< Shifted mode WAITACK for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_NBBLESTATE_DEBUG (_MODEM_FSMSTATUS_NBBLESTATE_DEBUG << 15) /**< Shifted mode DEBUG for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_SHIFT 20 /**< Shift value for MODEM_ANTDIVSTATE */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_MASK 0xF00000UL /**< Bit mask for MODEM_ANTDIVSTATE */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 0x00000001UL /**< Mode FIRST_ANT0 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 0x00000002UL /**< Mode FIRST_ANT1 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 0x00000003UL /**< Mode TIMSEARCH_ANT0 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 0x00000004UL /**< Mode TIMSEARCH_ANT1 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 0x00000005UL /**< Mode TIMDET_ANT0 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 0x00000006UL /**< Mode TIMDET_ANT1 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE 0x00000007UL /**< Mode EVALUATE for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED 0x00000008UL /**< Mode TIMSEARCH_SELECTED for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED 0x00000009UL /**< Mode TIMDET_SELECTED for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 0x0000000AUL /**< Mode REPEAT_ANT0 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 0x0000000BUL /**< Mode REPEAT_ANT1 for MODEM_FSMSTATUS */ +#define _MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL 0x0000000FUL /**< Mode MANUAL for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT (_MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_IDLE (_MODEM_FSMSTATUS_ANTDIVSTATE_IDLE << 20) /**< Shifted mode IDLE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 << 20) /**< Shifted mode FIRST_ANT0 for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 << 20) /**< Shifted mode FIRST_ANT1 for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 << 20) /**< Shifted mode TIMSEARCH_ANT0 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 << 20) /**< Shifted mode TIMSEARCH_ANT1 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 << 20) /**< Shifted mode TIMDET_ANT0 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 << 20) /**< Shifted mode TIMDET_ANT1 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE (_MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE << 20) /**< Shifted mode EVALUATE for MODEM_FSMSTATUS */ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED << 20) /**< Shifted mode TIMSEARCH_SELECTED for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED << 20) /**< Shifted mode TIMDET_SELECTED for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 << 20) /**< Shifted mode REPEAT_ANT0 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 << 20) /**< Shifted mode REPEAT_ANT1 for MODEM_FSMSTATUS*/ +#define MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL (_MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL << 20) /**< Shifted mode MANUAL for MODEM_FSMSTATUS */ + +/* Bit fields for MODEM FREQOFFEST */ +#define _MODEM_FREQOFFEST_RESETVALUE 0x00000000UL /**< Default value for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_MASK 0xFFFFFFFFUL /**< Mask for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_FREQOFFEST_SHIFT 0 /**< Shift value for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_FREQOFFEST_MASK 0x1FFFUL /**< Bit mask for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_FREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */ +#define MODEM_FREQOFFEST_FREQOFFEST_DEFAULT (_MODEM_FREQOFFEST_FREQOFFEST_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_CORRVAL_SHIFT 13 /**< Shift value for MODEM_CORRVAL */ +#define _MODEM_FREQOFFEST_CORRVAL_MASK 0xFFE000UL /**< Bit mask for MODEM_CORRVAL */ +#define _MODEM_FREQOFFEST_CORRVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */ +#define MODEM_FREQOFFEST_CORRVAL_DEFAULT (_MODEM_FREQOFFEST_CORRVAL_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */ +#define _MODEM_FREQOFFEST_SOFTVAL_SHIFT 24 /**< Shift value for MODEM_SOFTVAL */ +#define _MODEM_FREQOFFEST_SOFTVAL_MASK 0xFF000000UL /**< Bit mask for MODEM_SOFTVAL */ +#define _MODEM_FREQOFFEST_SOFTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */ +#define MODEM_FREQOFFEST_SOFTVAL_DEFAULT (_MODEM_FREQOFFEST_SOFTVAL_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */ + +/* Bit fields for MODEM AFCADJRX */ +#define _MODEM_AFCADJRX_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_MASK 0xF1F7FFFFUL /**< Mask for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_AFCADJRX_SHIFT 0 /**< Shift value for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_AFCADJRX_MASK 0x7FFFFUL /**< Bit mask for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_AFCADJRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */ +#define MODEM_AFCADJRX_AFCADJRX_DEFAULT (_MODEM_AFCADJRX_AFCADJRX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_AFCSCALEM_SHIFT 20 /**< Shift value for MODEM_AFCSCALEM */ +#define _MODEM_AFCADJRX_AFCSCALEM_MASK 0x1F00000UL /**< Bit mask for MODEM_AFCSCALEM */ +#define _MODEM_AFCADJRX_AFCSCALEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */ +#define MODEM_AFCADJRX_AFCSCALEM_DEFAULT (_MODEM_AFCADJRX_AFCSCALEM_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */ +#define _MODEM_AFCADJRX_AFCSCALEE_SHIFT 28 /**< Shift value for MODEM_AFCSCALEE */ +#define _MODEM_AFCADJRX_AFCSCALEE_MASK 0xF0000000UL /**< Bit mask for MODEM_AFCSCALEE */ +#define _MODEM_AFCADJRX_AFCSCALEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */ +#define MODEM_AFCADJRX_AFCSCALEE_DEFAULT (_MODEM_AFCADJRX_AFCSCALEE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */ + +/* Bit fields for MODEM AFCADJTX */ +#define _MODEM_AFCADJTX_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_MASK 0xF1F7FFFFUL /**< Mask for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_AFCADJTX_SHIFT 0 /**< Shift value for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_AFCADJTX_MASK 0x7FFFFUL /**< Bit mask for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_AFCADJTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */ +#define MODEM_AFCADJTX_AFCADJTX_DEFAULT (_MODEM_AFCADJTX_AFCADJTX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_AFCSCALEM_SHIFT 20 /**< Shift value for MODEM_AFCSCALEM */ +#define _MODEM_AFCADJTX_AFCSCALEM_MASK 0x1F00000UL /**< Bit mask for MODEM_AFCSCALEM */ +#define _MODEM_AFCADJTX_AFCSCALEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */ +#define MODEM_AFCADJTX_AFCSCALEM_DEFAULT (_MODEM_AFCADJTX_AFCSCALEM_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */ +#define _MODEM_AFCADJTX_AFCSCALEE_SHIFT 28 /**< Shift value for MODEM_AFCSCALEE */ +#define _MODEM_AFCADJTX_AFCSCALEE_MASK 0xF0000000UL /**< Bit mask for MODEM_AFCSCALEE */ +#define _MODEM_AFCADJTX_AFCSCALEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */ +#define MODEM_AFCADJTX_AFCSCALEE_DEFAULT (_MODEM_AFCADJTX_AFCSCALEE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */ + +/* Bit fields for MODEM MIXCTRL */ +#define _MODEM_MIXCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_MIXCTRL */ +#define _MODEM_MIXCTRL_MASK 0x00000010UL /**< Mask for MODEM_MIXCTRL */ +#define MODEM_MIXCTRL_DIGIQSWAPEN (0x1UL << 4) /**< Digital I/Q swap enable */ +#define _MODEM_MIXCTRL_DIGIQSWAPEN_SHIFT 4 /**< Shift value for MODEM_DIGIQSWAPEN */ +#define _MODEM_MIXCTRL_DIGIQSWAPEN_MASK 0x10UL /**< Bit mask for MODEM_DIGIQSWAPEN */ +#define _MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MIXCTRL */ +#define MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT (_MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_MIXCTRL */ + +/* Bit fields for MODEM CTRL0 */ +#define _MODEM_CTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL0 */ +#define MODEM_CTRL0_FDM0DIFFDIS (0x1UL << 0) /**< Frame Detection Mode 0 disable */ +#define _MODEM_CTRL0_FDM0DIFFDIS_SHIFT 0 /**< Shift value for MODEM_FDM0DIFFDIS */ +#define _MODEM_CTRL0_FDM0DIFFDIS_MASK 0x1UL /**< Bit mask for MODEM_FDM0DIFFDIS */ +#define _MODEM_CTRL0_FDM0DIFFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_FDM0DIFFDIS_DEFAULT (_MODEM_CTRL0_FDM0DIFFDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_SHIFT 1 /**< Shift value for MODEM_MAPFSK */ +#define _MODEM_CTRL0_MAPFSK_MASK 0xEUL /**< Bit mask for MODEM_MAPFSK */ +#define _MODEM_CTRL0_MAPFSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP0 0x00000000UL /**< Mode MAP0 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP1 0x00000001UL /**< Mode MAP1 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP2 0x00000002UL /**< Mode MAP2 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP3 0x00000003UL /**< Mode MAP3 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP4 0x00000004UL /**< Mode MAP4 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP5 0x00000005UL /**< Mode MAP5 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP6 0x00000006UL /**< Mode MAP6 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MAPFSK_MAP7 0x00000007UL /**< Mode MAP7 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_DEFAULT (_MODEM_CTRL0_MAPFSK_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP0 (_MODEM_CTRL0_MAPFSK_MAP0 << 1) /**< Shifted mode MAP0 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP1 (_MODEM_CTRL0_MAPFSK_MAP1 << 1) /**< Shifted mode MAP1 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP2 (_MODEM_CTRL0_MAPFSK_MAP2 << 1) /**< Shifted mode MAP2 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP3 (_MODEM_CTRL0_MAPFSK_MAP3 << 1) /**< Shifted mode MAP3 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP4 (_MODEM_CTRL0_MAPFSK_MAP4 << 1) /**< Shifted mode MAP4 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP5 (_MODEM_CTRL0_MAPFSK_MAP5 << 1) /**< Shifted mode MAP5 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP6 (_MODEM_CTRL0_MAPFSK_MAP6 << 1) /**< Shifted mode MAP6 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MAPFSK_MAP7 (_MODEM_CTRL0_MAPFSK_MAP7 << 1) /**< Shifted mode MAP7 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_CODING_SHIFT 4 /**< Shift value for MODEM_CODING */ +#define _MODEM_CTRL0_CODING_MASK 0x30UL /**< Bit mask for MODEM_CODING */ +#define _MODEM_CTRL0_CODING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_CODING_NRZ 0x00000000UL /**< Mode NRZ for MODEM_CTRL0 */ +#define _MODEM_CTRL0_CODING_MANCHESTER 0x00000001UL /**< Mode MANCHESTER for MODEM_CTRL0 */ +#define _MODEM_CTRL0_CODING_DSSS 0x00000002UL /**< Mode DSSS for MODEM_CTRL0 */ +#define _MODEM_CTRL0_CODING_LINECODE 0x00000003UL /**< Mode LINECODE for MODEM_CTRL0 */ +#define MODEM_CTRL0_CODING_DEFAULT (_MODEM_CTRL0_CODING_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_CODING_NRZ (_MODEM_CTRL0_CODING_NRZ << 4) /**< Shifted mode NRZ for MODEM_CTRL0 */ +#define MODEM_CTRL0_CODING_MANCHESTER (_MODEM_CTRL0_CODING_MANCHESTER << 4) /**< Shifted mode MANCHESTER for MODEM_CTRL0 */ +#define MODEM_CTRL0_CODING_DSSS (_MODEM_CTRL0_CODING_DSSS << 4) /**< Shifted mode DSSS for MODEM_CTRL0 */ +#define MODEM_CTRL0_CODING_LINECODE (_MODEM_CTRL0_CODING_LINECODE << 4) /**< Shifted mode LINECODE for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_SHIFT 6 /**< Shift value for MODEM_MODFORMAT */ +#define _MODEM_CTRL0_MODFORMAT_MASK 0x1C0UL /**< Bit mask for MODEM_MODFORMAT */ +#define _MODEM_CTRL0_MODFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_FSK2 0x00000000UL /**< Mode FSK2 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_FSK4 0x00000001UL /**< Mode FSK4 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_BPSK 0x00000002UL /**< Mode BPSK for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_DBPSK 0x00000003UL /**< Mode DBPSK for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_OQPSK 0x00000004UL /**< Mode OQPSK for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_MSK 0x00000005UL /**< Mode MSK for MODEM_CTRL0 */ +#define _MODEM_CTRL0_MODFORMAT_OOKASK 0x00000006UL /**< Mode OOKASK for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_DEFAULT (_MODEM_CTRL0_MODFORMAT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_FSK2 (_MODEM_CTRL0_MODFORMAT_FSK2 << 6) /**< Shifted mode FSK2 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_FSK4 (_MODEM_CTRL0_MODFORMAT_FSK4 << 6) /**< Shifted mode FSK4 for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_BPSK (_MODEM_CTRL0_MODFORMAT_BPSK << 6) /**< Shifted mode BPSK for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_DBPSK (_MODEM_CTRL0_MODFORMAT_DBPSK << 6) /**< Shifted mode DBPSK for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_OQPSK (_MODEM_CTRL0_MODFORMAT_OQPSK << 6) /**< Shifted mode OQPSK for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_MSK (_MODEM_CTRL0_MODFORMAT_MSK << 6) /**< Shifted mode MSK for MODEM_CTRL0 */ +#define MODEM_CTRL0_MODFORMAT_OOKASK (_MODEM_CTRL0_MODFORMAT_OOKASK << 6) /**< Shifted mode OOKASK for MODEM_CTRL0 */ +#define MODEM_CTRL0_DUALCORROPTDIS (0x1UL << 9) /**< Dual Correlation Optimization Disable */ +#define _MODEM_CTRL0_DUALCORROPTDIS_SHIFT 9 /**< Shift value for MODEM_DUALCORROPTDIS */ +#define _MODEM_CTRL0_DUALCORROPTDIS_MASK 0x200UL /**< Bit mask for MODEM_DUALCORROPTDIS */ +#define _MODEM_CTRL0_DUALCORROPTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DUALCORROPTDIS_DEFAULT (_MODEM_CTRL0_DUALCORROPTDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_OOKASYNCPIN (0x1UL << 10) /**< OOK asynchronous pin mode */ +#define _MODEM_CTRL0_OOKASYNCPIN_SHIFT 10 /**< Shift value for MODEM_OOKASYNCPIN */ +#define _MODEM_CTRL0_OOKASYNCPIN_MASK 0x400UL /**< Bit mask for MODEM_OOKASYNCPIN */ +#define _MODEM_CTRL0_OOKASYNCPIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_OOKASYNCPIN_DEFAULT (_MODEM_CTRL0_OOKASYNCPIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSLEN_SHIFT 11 /**< Shift value for MODEM_DSSSLEN */ +#define _MODEM_CTRL0_DSSSLEN_MASK 0xF800UL /**< Bit mask for MODEM_DSSSLEN */ +#define _MODEM_CTRL0_DSSSLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSLEN_DEFAULT (_MODEM_CTRL0_DSSSLEN_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT 16 /**< Shift value for MODEM_DSSSSHIFTS */ +#define _MODEM_CTRL0_DSSSSHIFTS_MASK 0x70000UL /**< Bit mask for MODEM_DSSSSHIFTS */ +#define _MODEM_CTRL0_DSSSSHIFTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT1 0x00000001UL /**< Mode SHIFT1 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT2 0x00000002UL /**< Mode SHIFT2 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT4 0x00000003UL /**< Mode SHIFT4 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT8 0x00000004UL /**< Mode SHIFT8 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT16 0x00000005UL /**< Mode SHIFT16 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_DEFAULT (_MODEM_CTRL0_DSSSSHIFTS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_NOSHIFT (_MODEM_CTRL0_DSSSSHIFTS_NOSHIFT << 16) /**< Shifted mode NOSHIFT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_SHIFT1 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT1 << 16) /**< Shifted mode SHIFT1 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_SHIFT2 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT2 << 16) /**< Shifted mode SHIFT2 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_SHIFT4 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT4 << 16) /**< Shifted mode SHIFT4 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_SHIFT8 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT8 << 16) /**< Shifted mode SHIFT8 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSSHIFTS_SHIFT16 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT16 << 16) /**< Shifted mode SHIFT16 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSDOUBLE_SHIFT 19 /**< Shift value for MODEM_DSSSDOUBLE */ +#define _MODEM_CTRL0_DSSSDOUBLE_MASK 0x180000UL /**< Bit mask for MODEM_DSSSDOUBLE */ +#define _MODEM_CTRL0_DSSSDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSDOUBLE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSDOUBLE_INV 0x00000001UL /**< Mode INV for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DSSSDOUBLE_CONJ 0x00000002UL /**< Mode CONJ for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSDOUBLE_DEFAULT (_MODEM_CTRL0_DSSSDOUBLE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSDOUBLE_DIS (_MODEM_CTRL0_DSSSDOUBLE_DIS << 19) /**< Shifted mode DIS for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSDOUBLE_INV (_MODEM_CTRL0_DSSSDOUBLE_INV << 19) /**< Shifted mode INV for MODEM_CTRL0 */ +#define MODEM_CTRL0_DSSSDOUBLE_CONJ (_MODEM_CTRL0_DSSSDOUBLE_CONJ << 19) /**< Shifted mode CONJ for MODEM_CTRL0 */ +#define MODEM_CTRL0_DETDIS (0x1UL << 21) /**< Detection disable */ +#define _MODEM_CTRL0_DETDIS_SHIFT 21 /**< Shift value for MODEM_DETDIS */ +#define _MODEM_CTRL0_DETDIS_MASK 0x200000UL /**< Bit mask for MODEM_DETDIS */ +#define _MODEM_CTRL0_DETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DETDIS_DEFAULT (_MODEM_CTRL0_DETDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_SHIFT 22 /**< Shift value for MODEM_DIFFENCMODE */ +#define _MODEM_CTRL0_DIFFENCMODE_MASK 0x1C00000UL /**< Bit mask for MODEM_DIFFENCMODE */ +#define _MODEM_CTRL0_DIFFENCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_RR0 0x00000001UL /**< Mode RR0 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_RE0 0x00000002UL /**< Mode RE0 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_RR1 0x00000003UL /**< Mode RR1 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DIFFENCMODE_RE1 0x00000004UL /**< Mode RE1 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_DEFAULT (_MODEM_CTRL0_DIFFENCMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_DIS (_MODEM_CTRL0_DIFFENCMODE_DIS << 22) /**< Shifted mode DIS for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_RR0 (_MODEM_CTRL0_DIFFENCMODE_RR0 << 22) /**< Shifted mode RR0 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_RE0 (_MODEM_CTRL0_DIFFENCMODE_RE0 << 22) /**< Shifted mode RE0 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_RR1 (_MODEM_CTRL0_DIFFENCMODE_RR1 << 22) /**< Shifted mode RR1 for MODEM_CTRL0 */ +#define MODEM_CTRL0_DIFFENCMODE_RE1 (_MODEM_CTRL0_DIFFENCMODE_RE1 << 22) /**< Shifted mode RE1 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_SHAPING_SHIFT 25 /**< Shift value for MODEM_SHAPING */ +#define _MODEM_CTRL0_SHAPING_MASK 0x6000000UL /**< Bit mask for MODEM_SHAPING */ +#define _MODEM_CTRL0_SHAPING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_SHAPING_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL0 */ +#define _MODEM_CTRL0_SHAPING_ODDLENGTH 0x00000001UL /**< Mode ODDLENGTH for MODEM_CTRL0 */ +#define _MODEM_CTRL0_SHAPING_EVENLENGTH 0x00000002UL /**< Mode EVENLENGTH for MODEM_CTRL0 */ +#define _MODEM_CTRL0_SHAPING_ASYMMETRIC 0x00000003UL /**< Mode ASYMMETRIC for MODEM_CTRL0 */ +#define MODEM_CTRL0_SHAPING_DEFAULT (_MODEM_CTRL0_SHAPING_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_SHAPING_DISABLED (_MODEM_CTRL0_SHAPING_DISABLED << 25) /**< Shifted mode DISABLED for MODEM_CTRL0 */ +#define MODEM_CTRL0_SHAPING_ODDLENGTH (_MODEM_CTRL0_SHAPING_ODDLENGTH << 25) /**< Shifted mode ODDLENGTH for MODEM_CTRL0 */ +#define MODEM_CTRL0_SHAPING_EVENLENGTH (_MODEM_CTRL0_SHAPING_EVENLENGTH << 25) /**< Shifted mode EVENLENGTH for MODEM_CTRL0 */ +#define MODEM_CTRL0_SHAPING_ASYMMETRIC (_MODEM_CTRL0_SHAPING_ASYMMETRIC << 25) /**< Shifted mode ASYMMETRIC for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_SHIFT 27 /**< Shift value for MODEM_DEMODRAWDATASEL */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_MASK 0x38000000UL /**< Bit mask for MODEM_DEMODRAWDATASEL */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY 0x00000001UL /**< Mode ENTROPY for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_ADC 0x00000002UL /**< Mode ADC for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB 0x00000003UL /**< Mode FILTLSB for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB 0x00000004UL /**< Mode FILTMSB for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL 0x00000005UL /**< Mode FILTFULL for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_FREQ 0x00000006UL /**< Mode FREQ for MODEM_CTRL0 */ +#define _MODEM_CTRL0_DEMODRAWDATASEL_DEMOD 0x00000007UL /**< Mode DEMOD for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT (_MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_DIS (_MODEM_CTRL0_DEMODRAWDATASEL_DIS << 27) /**< Shifted mode DIS for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY (_MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY << 27) /**< Shifted mode ENTROPY for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_ADC (_MODEM_CTRL0_DEMODRAWDATASEL_ADC << 27) /**< Shifted mode ADC for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB (_MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB << 27) /**< Shifted mode FILTLSB for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB (_MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB << 27) /**< Shifted mode FILTMSB for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL (_MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL << 27) /**< Shifted mode FILTFULL for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_FREQ (_MODEM_CTRL0_DEMODRAWDATASEL_FREQ << 27) /**< Shifted mode FREQ for MODEM_CTRL0 */ +#define MODEM_CTRL0_DEMODRAWDATASEL_DEMOD (_MODEM_CTRL0_DEMODRAWDATASEL_DEMOD << 27) /**< Shifted mode DEMOD for MODEM_CTRL0 */ +#define _MODEM_CTRL0_FRAMEDETDEL_SHIFT 30 /**< Shift value for MODEM_FRAMEDETDEL */ +#define _MODEM_CTRL0_FRAMEDETDEL_MASK 0xC0000000UL /**< Bit mask for MODEM_FRAMEDETDEL */ +#define _MODEM_CTRL0_FRAMEDETDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */ +#define _MODEM_CTRL0_FRAMEDETDEL_DEL0 0x00000000UL /**< Mode DEL0 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_FRAMEDETDEL_DEL8 0x00000001UL /**< Mode DEL8 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_FRAMEDETDEL_DEL16 0x00000002UL /**< Mode DEL16 for MODEM_CTRL0 */ +#define _MODEM_CTRL0_FRAMEDETDEL_DEL32 0x00000003UL /**< Mode DEL32 for MODEM_CTRL0 */ +#define MODEM_CTRL0_FRAMEDETDEL_DEFAULT (_MODEM_CTRL0_FRAMEDETDEL_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL0 */ +#define MODEM_CTRL0_FRAMEDETDEL_DEL0 (_MODEM_CTRL0_FRAMEDETDEL_DEL0 << 30) /**< Shifted mode DEL0 for MODEM_CTRL0 */ +#define MODEM_CTRL0_FRAMEDETDEL_DEL8 (_MODEM_CTRL0_FRAMEDETDEL_DEL8 << 30) /**< Shifted mode DEL8 for MODEM_CTRL0 */ +#define MODEM_CTRL0_FRAMEDETDEL_DEL16 (_MODEM_CTRL0_FRAMEDETDEL_DEL16 << 30) /**< Shifted mode DEL16 for MODEM_CTRL0 */ +#define MODEM_CTRL0_FRAMEDETDEL_DEL32 (_MODEM_CTRL0_FRAMEDETDEL_DEL32 << 30) /**< Shifted mode DEL32 for MODEM_CTRL0 */ + +/* Bit fields for MODEM CTRL1 */ +#define _MODEM_CTRL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL1 */ +#define _MODEM_CTRL1_MASK 0xFFFFDFFFUL /**< Mask for MODEM_CTRL1 */ +#define _MODEM_CTRL1_SYNCBITS_SHIFT 0 /**< Shift value for MODEM_SYNCBITS */ +#define _MODEM_CTRL1_SYNCBITS_MASK 0x1FUL /**< Bit mask for MODEM_SYNCBITS */ +#define _MODEM_CTRL1_SYNCBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCBITS_DEFAULT (_MODEM_CTRL1_SYNCBITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_SYNCERRORS_SHIFT 5 /**< Shift value for MODEM_SYNCERRORS */ +#define _MODEM_CTRL1_SYNCERRORS_MASK 0x1E0UL /**< Bit mask for MODEM_SYNCERRORS */ +#define _MODEM_CTRL1_SYNCERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCERRORS_DEFAULT (_MODEM_CTRL1_SYNCERRORS_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_DUALSYNC (0x1UL << 9) /**< Dual sync words. */ +#define _MODEM_CTRL1_DUALSYNC_SHIFT 9 /**< Shift value for MODEM_DUALSYNC */ +#define _MODEM_CTRL1_DUALSYNC_MASK 0x200UL /**< Bit mask for MODEM_DUALSYNC */ +#define _MODEM_CTRL1_DUALSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_DUALSYNC_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL1 */ +#define _MODEM_CTRL1_DUALSYNC_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_DUALSYNC_DEFAULT (_MODEM_CTRL1_DUALSYNC_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_DUALSYNC_DISABLED (_MODEM_CTRL1_DUALSYNC_DISABLED << 9) /**< Shifted mode DISABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_DUALSYNC_ENABLED (_MODEM_CTRL1_DUALSYNC_ENABLED << 9) /**< Shifted mode ENABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_TXSYNC (0x1UL << 10) /**< Transmit sync word. */ +#define _MODEM_CTRL1_TXSYNC_SHIFT 10 /**< Shift value for MODEM_TXSYNC */ +#define _MODEM_CTRL1_TXSYNC_MASK 0x400UL /**< Bit mask for MODEM_TXSYNC */ +#define _MODEM_CTRL1_TXSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_TXSYNC_SYNC0 0x00000000UL /**< Mode SYNC0 for MODEM_CTRL1 */ +#define _MODEM_CTRL1_TXSYNC_SYNC1 0x00000001UL /**< Mode SYNC1 for MODEM_CTRL1 */ +#define MODEM_CTRL1_TXSYNC_DEFAULT (_MODEM_CTRL1_TXSYNC_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_TXSYNC_SYNC0 (_MODEM_CTRL1_TXSYNC_SYNC0 << 10) /**< Shifted mode SYNC0 for MODEM_CTRL1 */ +#define MODEM_CTRL1_TXSYNC_SYNC1 (_MODEM_CTRL1_TXSYNC_SYNC1 << 10) /**< Shifted mode SYNC1 for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCDATA (0x1UL << 11) /**< Sync data. */ +#define _MODEM_CTRL1_SYNCDATA_SHIFT 11 /**< Shift value for MODEM_SYNCDATA */ +#define _MODEM_CTRL1_SYNCDATA_MASK 0x800UL /**< Bit mask for MODEM_SYNCDATA */ +#define _MODEM_CTRL1_SYNCDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_SYNCDATA_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL1 */ +#define _MODEM_CTRL1_SYNCDATA_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCDATA_DEFAULT (_MODEM_CTRL1_SYNCDATA_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCDATA_DISABLED (_MODEM_CTRL1_SYNCDATA_DISABLED << 11) /**< Shifted mode DISABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNCDATA_ENABLED (_MODEM_CTRL1_SYNCDATA_ENABLED << 11) /**< Shifted mode ENABLED for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNC1INV (0x1UL << 12) /**< SYNC1 invert. */ +#define _MODEM_CTRL1_SYNC1INV_SHIFT 12 /**< Shift value for MODEM_SYNC1INV */ +#define _MODEM_CTRL1_SYNC1INV_MASK 0x1000UL /**< Bit mask for MODEM_SYNC1INV */ +#define _MODEM_CTRL1_SYNC1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_SYNC1INV_DEFAULT (_MODEM_CTRL1_SYNC1INV_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_COMPMODE_SHIFT 14 /**< Shift value for MODEM_COMPMODE */ +#define _MODEM_CTRL1_COMPMODE_MASK 0xC000UL /**< Bit mask for MODEM_COMPMODE */ +#define _MODEM_CTRL1_COMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_COMPMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL1 */ +#define _MODEM_CTRL1_COMPMODE_PRELOCK 0x00000001UL /**< Mode PRELOCK for MODEM_CTRL1 */ +#define _MODEM_CTRL1_COMPMODE_FRAMELOCK 0x00000002UL /**< Mode FRAMELOCK for MODEM_CTRL1 */ +#define _MODEM_CTRL1_COMPMODE_NOLOCK 0x00000003UL /**< Mode NOLOCK for MODEM_CTRL1 */ +#define MODEM_CTRL1_COMPMODE_DEFAULT (_MODEM_CTRL1_COMPMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_COMPMODE_DIS (_MODEM_CTRL1_COMPMODE_DIS << 14) /**< Shifted mode DIS for MODEM_CTRL1 */ +#define MODEM_CTRL1_COMPMODE_PRELOCK (_MODEM_CTRL1_COMPMODE_PRELOCK << 14) /**< Shifted mode PRELOCK for MODEM_CTRL1 */ +#define MODEM_CTRL1_COMPMODE_FRAMELOCK (_MODEM_CTRL1_COMPMODE_FRAMELOCK << 14) /**< Shifted mode FRAMELOCK for MODEM_CTRL1 */ +#define MODEM_CTRL1_COMPMODE_NOLOCK (_MODEM_CTRL1_COMPMODE_NOLOCK << 14) /**< Shifted mode NOLOCK for MODEM_CTRL1 */ +#define _MODEM_CTRL1_RESYNCPER_SHIFT 16 /**< Shift value for MODEM_RESYNCPER */ +#define _MODEM_CTRL1_RESYNCPER_MASK 0xF0000UL /**< Bit mask for MODEM_RESYNCPER */ +#define _MODEM_CTRL1_RESYNCPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_RESYNCPER_DEFAULT (_MODEM_CTRL1_RESYNCPER_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_PHASEDEMOD_SHIFT 20 /**< Shift value for MODEM_PHASEDEMOD */ +#define _MODEM_CTRL1_PHASEDEMOD_MASK 0x300000UL /**< Bit mask for MODEM_PHASEDEMOD */ +#define _MODEM_CTRL1_PHASEDEMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_PHASEDEMOD_BDD 0x00000000UL /**< Mode BDD for MODEM_CTRL1 */ +#define _MODEM_CTRL1_PHASEDEMOD_MBDD 0x00000001UL /**< Mode MBDD for MODEM_CTRL1 */ +#define _MODEM_CTRL1_PHASEDEMOD_COH 0x00000002UL /**< Mode COH for MODEM_CTRL1 */ +#define MODEM_CTRL1_PHASEDEMOD_DEFAULT (_MODEM_CTRL1_PHASEDEMOD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_PHASEDEMOD_BDD (_MODEM_CTRL1_PHASEDEMOD_BDD << 20) /**< Shifted mode BDD for MODEM_CTRL1 */ +#define MODEM_CTRL1_PHASEDEMOD_MBDD (_MODEM_CTRL1_PHASEDEMOD_MBDD << 20) /**< Shifted mode MBDD for MODEM_CTRL1 */ +#define MODEM_CTRL1_PHASEDEMOD_COH (_MODEM_CTRL1_PHASEDEMOD_COH << 20) /**< Shifted mode COH for MODEM_CTRL1 */ +#define _MODEM_CTRL1_FREQOFFESTPER_SHIFT 22 /**< Shift value for MODEM_FREQOFFESTPER */ +#define _MODEM_CTRL1_FREQOFFESTPER_MASK 0x1C00000UL /**< Bit mask for MODEM_FREQOFFESTPER */ +#define _MODEM_CTRL1_FREQOFFESTPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_FREQOFFESTPER_DEFAULT (_MODEM_CTRL1_FREQOFFESTPER_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ +#define _MODEM_CTRL1_FREQOFFESTLIM_SHIFT 25 /**< Shift value for MODEM_FREQOFFESTLIM */ +#define _MODEM_CTRL1_FREQOFFESTLIM_MASK 0xFE000000UL /**< Bit mask for MODEM_FREQOFFESTLIM */ +#define _MODEM_CTRL1_FREQOFFESTLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */ +#define MODEM_CTRL1_FREQOFFESTLIM_DEFAULT (_MODEM_CTRL1_FREQOFFESTLIM_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL1 */ + +/* Bit fields for MODEM CTRL2 */ +#define _MODEM_CTRL2_RESETVALUE 0x00001000UL /**< Default value for MODEM_CTRL2 */ +#define _MODEM_CTRL2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL2 */ +#define _MODEM_CTRL2_SQITHRESH_SHIFT 0 /**< Shift value for MODEM_SQITHRESH */ +#define _MODEM_CTRL2_SQITHRESH_MASK 0xFFUL /**< Bit mask for MODEM_SQITHRESH */ +#define _MODEM_CTRL2_SQITHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_SQITHRESH_DEFAULT (_MODEM_CTRL2_SQITHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXFRCDIS (0x1UL << 8) /**< Receive FRC disable */ +#define _MODEM_CTRL2_RXFRCDIS_SHIFT 8 /**< Shift value for MODEM_RXFRCDIS */ +#define _MODEM_CTRL2_RXFRCDIS_MASK 0x100UL /**< Bit mask for MODEM_RXFRCDIS */ +#define _MODEM_CTRL2_RXFRCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXFRCDIS_DEFAULT (_MODEM_CTRL2_RXFRCDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXPINMODE (0x1UL << 9) /**< Receive pin mode */ +#define _MODEM_CTRL2_RXPINMODE_SHIFT 9 /**< Shift value for MODEM_RXPINMODE */ +#define _MODEM_CTRL2_RXPINMODE_MASK 0x200UL /**< Bit mask for MODEM_RXPINMODE */ +#define _MODEM_CTRL2_RXPINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RXPINMODE_SYNCHRONOUS 0x00000000UL /**< Mode SYNCHRONOUS for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS 0x00000001UL /**< Mode ASYNCHRONOUS for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXPINMODE_DEFAULT (_MODEM_CTRL2_RXPINMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXPINMODE_SYNCHRONOUS (_MODEM_CTRL2_RXPINMODE_SYNCHRONOUS << 9) /**< Shifted mode SYNCHRONOUS for MODEM_CTRL2 */ +#define MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS (_MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS << 9) /**< Shifted mode ASYNCHRONOUS for MODEM_CTRL2 */ +#define _MODEM_CTRL2_TXPINMODE_SHIFT 10 /**< Shift value for MODEM_TXPINMODE */ +#define _MODEM_CTRL2_TXPINMODE_MASK 0xC00UL /**< Bit mask for MODEM_TXPINMODE */ +#define _MODEM_CTRL2_TXPINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_TXPINMODE_OFF 0x00000000UL /**< Mode OFF for MODEM_CTRL2 */ +#define _MODEM_CTRL2_TXPINMODE_MFM 0x00000001UL /**< Mode MFM for MODEM_CTRL2 */ +#define _MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS 0x00000002UL /**< Mode ASYNCHRONOUS for MODEM_CTRL2 */ +#define _MODEM_CTRL2_TXPINMODE_SYNCHRONOUS 0x00000003UL /**< Mode SYNCHRONOUS for MODEM_CTRL2 */ +#define MODEM_CTRL2_TXPINMODE_DEFAULT (_MODEM_CTRL2_TXPINMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_TXPINMODE_OFF (_MODEM_CTRL2_TXPINMODE_OFF << 10) /**< Shifted mode OFF for MODEM_CTRL2 */ +#define MODEM_CTRL2_TXPINMODE_MFM (_MODEM_CTRL2_TXPINMODE_MFM << 10) /**< Shifted mode MFM for MODEM_CTRL2 */ +#define MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS (_MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS << 10) /**< Shifted mode ASYNCHRONOUS for MODEM_CTRL2 */ +#define MODEM_CTRL2_TXPINMODE_SYNCHRONOUS (_MODEM_CTRL2_TXPINMODE_SYNCHRONOUS << 10) /**< Shifted mode SYNCHRONOUS for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_SHIFT 12 /**< Shift value for MODEM_DATAFILTER */ +#define _MODEM_CTRL2_DATAFILTER_MASK 0x7000UL /**< Bit mask for MODEM_DATAFILTER */ +#define _MODEM_CTRL2_DATAFILTER_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_SHORT 0x00000001UL /**< Mode SHORT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_MEDIUM 0x00000002UL /**< Mode MEDIUM for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_LONG 0x00000003UL /**< Mode LONG for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_LEN6 0x00000004UL /**< Mode LEN6 for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_LEN7 0x00000005UL /**< Mode LEN7 for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_LEN8 0x00000006UL /**< Mode LEN8 for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DATAFILTER_LEN9 0x00000007UL /**< Mode LEN9 for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_DEFAULT (_MODEM_CTRL2_DATAFILTER_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_DISABLED (_MODEM_CTRL2_DATAFILTER_DISABLED << 12) /**< Shifted mode DISABLED for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_SHORT (_MODEM_CTRL2_DATAFILTER_SHORT << 12) /**< Shifted mode SHORT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_MEDIUM (_MODEM_CTRL2_DATAFILTER_MEDIUM << 12) /**< Shifted mode MEDIUM for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_LONG (_MODEM_CTRL2_DATAFILTER_LONG << 12) /**< Shifted mode LONG for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_LEN6 (_MODEM_CTRL2_DATAFILTER_LEN6 << 12) /**< Shifted mode LEN6 for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_LEN7 (_MODEM_CTRL2_DATAFILTER_LEN7 << 12) /**< Shifted mode LEN7 for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_LEN8 (_MODEM_CTRL2_DATAFILTER_LEN8 << 12) /**< Shifted mode LEN8 for MODEM_CTRL2 */ +#define MODEM_CTRL2_DATAFILTER_LEN9 (_MODEM_CTRL2_DATAFILTER_LEN9 << 12) /**< Shifted mode LEN9 for MODEM_CTRL2 */ +#define _MODEM_CTRL2_BRDIVA_SHIFT 15 /**< Shift value for MODEM_BRDIVA */ +#define _MODEM_CTRL2_BRDIVA_MASK 0x78000UL /**< Bit mask for MODEM_BRDIVA */ +#define _MODEM_CTRL2_BRDIVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_BRDIVA_DEFAULT (_MODEM_CTRL2_BRDIVA_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_BRDIVB_SHIFT 19 /**< Shift value for MODEM_BRDIVB */ +#define _MODEM_CTRL2_BRDIVB_MASK 0x780000UL /**< Bit mask for MODEM_BRDIVB */ +#define _MODEM_CTRL2_BRDIVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_BRDIVB_DEFAULT (_MODEM_CTRL2_BRDIVB_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DEVMULA_SHIFT 23 /**< Shift value for MODEM_DEVMULA */ +#define _MODEM_CTRL2_DEVMULA_MASK 0x1800000UL /**< Bit mask for MODEM_DEVMULA */ +#define _MODEM_CTRL2_DEVMULA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DEVMULA_DEFAULT (_MODEM_CTRL2_DEVMULA_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DEVMULB_SHIFT 25 /**< Shift value for MODEM_DEVMULB */ +#define _MODEM_CTRL2_DEVMULB_MASK 0x6000000UL /**< Bit mask for MODEM_DEVMULB */ +#define _MODEM_CTRL2_DEVMULB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DEVMULB_DEFAULT (_MODEM_CTRL2_DEVMULB_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RATESELMODE_SHIFT 27 /**< Shift value for MODEM_RATESELMODE */ +#define _MODEM_CTRL2_RATESELMODE_MASK 0x18000000UL /**< Bit mask for MODEM_RATESELMODE */ +#define _MODEM_CTRL2_RATESELMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RATESELMODE_NOCHANGE 0x00000000UL /**< Mode NOCHANGE for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RATESELMODE_PAYLOAD 0x00000001UL /**< Mode PAYLOAD for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RATESELMODE_FRC 0x00000002UL /**< Mode FRC for MODEM_CTRL2 */ +#define _MODEM_CTRL2_RATESELMODE_SYNC 0x00000003UL /**< Mode SYNC for MODEM_CTRL2 */ +#define MODEM_CTRL2_RATESELMODE_DEFAULT (_MODEM_CTRL2_RATESELMODE_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_RATESELMODE_NOCHANGE (_MODEM_CTRL2_RATESELMODE_NOCHANGE << 27) /**< Shifted mode NOCHANGE for MODEM_CTRL2 */ +#define MODEM_CTRL2_RATESELMODE_PAYLOAD (_MODEM_CTRL2_RATESELMODE_PAYLOAD << 27) /**< Shifted mode PAYLOAD for MODEM_CTRL2 */ +#define MODEM_CTRL2_RATESELMODE_FRC (_MODEM_CTRL2_RATESELMODE_FRC << 27) /**< Shifted mode FRC for MODEM_CTRL2 */ +#define MODEM_CTRL2_RATESELMODE_SYNC (_MODEM_CTRL2_RATESELMODE_SYNC << 27) /**< Shifted mode SYNC for MODEM_CTRL2 */ +#define MODEM_CTRL2_DEVWEIGHTDIS (0x1UL << 29) /**< Deviation weighting disable. */ +#define _MODEM_CTRL2_DEVWEIGHTDIS_SHIFT 29 /**< Shift value for MODEM_DEVWEIGHTDIS */ +#define _MODEM_CTRL2_DEVWEIGHTDIS_MASK 0x20000000UL /**< Bit mask for MODEM_DEVWEIGHTDIS */ +#define _MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT (_MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DMASEL_SHIFT 30 /**< Shift value for MODEM_DMASEL */ +#define _MODEM_CTRL2_DMASEL_MASK 0xC0000000UL /**< Bit mask for MODEM_DMASEL */ +#define _MODEM_CTRL2_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DMASEL_SOFT 0x00000000UL /**< Mode SOFT for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DMASEL_CORR 0x00000001UL /**< Mode CORR for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DMASEL_FREQOFFEST 0x00000002UL /**< Mode FREQOFFEST for MODEM_CTRL2 */ +#define _MODEM_CTRL2_DMASEL_POE 0x00000003UL /**< Mode POE for MODEM_CTRL2 */ +#define MODEM_CTRL2_DMASEL_DEFAULT (_MODEM_CTRL2_DMASEL_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DMASEL_SOFT (_MODEM_CTRL2_DMASEL_SOFT << 30) /**< Shifted mode SOFT for MODEM_CTRL2 */ +#define MODEM_CTRL2_DMASEL_CORR (_MODEM_CTRL2_DMASEL_CORR << 30) /**< Shifted mode CORR for MODEM_CTRL2 */ +#define MODEM_CTRL2_DMASEL_FREQOFFEST (_MODEM_CTRL2_DMASEL_FREQOFFEST << 30) /**< Shifted mode FREQOFFEST for MODEM_CTRL2 */ +#define MODEM_CTRL2_DMASEL_POE (_MODEM_CTRL2_DMASEL_POE << 30) /**< Shifted mode POE for MODEM_CTRL2 */ + +/* Bit fields for MODEM CTRL3 */ +#define _MODEM_CTRL3_RESETVALUE 0x00008000UL /**< Default value for MODEM_CTRL3 */ +#define _MODEM_CTRL3_MASK 0xFFFFFF8FUL /**< Mask for MODEM_CTRL3 */ +#define MODEM_CTRL3_PRSDINEN (0x1UL << 0) /**< DIN PRS enable */ +#define _MODEM_CTRL3_PRSDINEN_SHIFT 0 /**< Shift value for MODEM_PRSDINEN */ +#define _MODEM_CTRL3_PRSDINEN_MASK 0x1UL /**< Bit mask for MODEM_PRSDINEN */ +#define _MODEM_CTRL3_PRSDINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_PRSDINEN_DEFAULT (_MODEM_CTRL3_PRSDINEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TIMINGBASESGAIN_SHIFT 1 /**< Shift value for MODEM_TIMINGBASESGAIN */ +#define _MODEM_CTRL3_TIMINGBASESGAIN_MASK 0x6UL /**< Bit mask for MODEM_TIMINGBASESGAIN */ +#define _MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT (_MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_DEVMULBCW (0x1UL << 3) /**< Deviatiion Factor B CW Mode */ +#define _MODEM_CTRL3_DEVMULBCW_SHIFT 3 /**< Shift value for MODEM_DEVMULBCW */ +#define _MODEM_CTRL3_DEVMULBCW_MASK 0x8UL /**< Bit mask for MODEM_DEVMULBCW */ +#define _MODEM_CTRL3_DEVMULBCW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_DEVMULBCW_DEFAULT (_MODEM_CTRL3_DEVMULBCW_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_SHIFT 8 /**< Shift value for MODEM_ANTDIVMODE */ +#define _MODEM_CTRL3_ANTDIVMODE_MASK 0x700UL /**< Bit mask for MODEM_ANTDIVMODE */ +#define _MODEM_CTRL3_ANTDIVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_ANTENNA0 0x00000000UL /**< Mode ANTENNA0 for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_ANTENNA1 0x00000001UL /**< Mode ANTENNA1 for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST 0x00000002UL /**< Mode ANTSELFIRST for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_ANTSELCORR 0x00000003UL /**< Mode ANTSELCORR for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI 0x00000004UL /**< Mode ANTSELRSSI for MODEM_CTRL3 */ +#define _MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV 0x00000005UL /**< Mode PHDEMODANTDIV for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_DEFAULT (_MODEM_CTRL3_ANTDIVMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_ANTENNA0 (_MODEM_CTRL3_ANTDIVMODE_ANTENNA0 << 8) /**< Shifted mode ANTENNA0 for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_ANTENNA1 (_MODEM_CTRL3_ANTDIVMODE_ANTENNA1 << 8) /**< Shifted mode ANTENNA1 for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST (_MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST << 8) /**< Shifted mode ANTSELFIRST for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_ANTSELCORR (_MODEM_CTRL3_ANTDIVMODE_ANTSELCORR << 8) /**< Shifted mode ANTSELCORR for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI (_MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI << 8) /**< Shifted mode ANTSELRSSI for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV (_MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV << 8) /**< Shifted mode PHDEMODANTDIV for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVREPEATDIS (0x1UL << 11) /**< Antenna diversity repeat disable */ +#define _MODEM_CTRL3_ANTDIVREPEATDIS_SHIFT 11 /**< Shift value for MODEM_ANTDIVREPEATDIS */ +#define _MODEM_CTRL3_ANTDIVREPEATDIS_MASK 0x800UL /**< Bit mask for MODEM_ANTDIVREPEATDIS */ +#define _MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT (_MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPMODE_SHIFT 12 /**< Shift value for MODEM_TSAMPMODE */ +#define _MODEM_CTRL3_TSAMPMODE_MASK 0x3000UL /**< Bit mask for MODEM_TSAMPMODE */ +#define _MODEM_CTRL3_TSAMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPMODE_OFF 0x00000000UL /**< Mode OFF for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPMODE_ON 0x00000001UL /**< Mode ON for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPMODE_DIFF 0x00000002UL /**< Mode DIFF for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPMODE_DEFAULT (_MODEM_CTRL3_TSAMPMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPMODE_OFF (_MODEM_CTRL3_TSAMPMODE_OFF << 12) /**< Shifted mode OFF for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPMODE_ON (_MODEM_CTRL3_TSAMPMODE_ON << 12) /**< Shifted mode ON for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPMODE_DIFF (_MODEM_CTRL3_TSAMPMODE_DIFF << 12) /**< Shifted mode DIFF for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPDEL_SHIFT 14 /**< Shift value for MODEM_TSAMPDEL */ +#define _MODEM_CTRL3_TSAMPDEL_MASK 0xC000UL /**< Bit mask for MODEM_TSAMPDEL */ +#define _MODEM_CTRL3_TSAMPDEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPDEL_DEFAULT (_MODEM_CTRL3_TSAMPDEL_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ +#define _MODEM_CTRL3_TSAMPLIM_SHIFT 16 /**< Shift value for MODEM_TSAMPLIM */ +#define _MODEM_CTRL3_TSAMPLIM_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TSAMPLIM */ +#define _MODEM_CTRL3_TSAMPLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */ +#define MODEM_CTRL3_TSAMPLIM_DEFAULT (_MODEM_CTRL3_TSAMPLIM_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL3 */ + +/* Bit fields for MODEM CTRL4 */ +#define _MODEM_CTRL4_RESETVALUE 0x03000000UL /**< Default value for MODEM_CTRL4 */ +#define _MODEM_CTRL4_MASK 0xBFFFFFFFUL /**< Mask for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ISICOMP_SHIFT 0 /**< Shift value for MODEM_ISICOMP */ +#define _MODEM_CTRL4_ISICOMP_MASK 0xFUL /**< Bit mask for MODEM_ISICOMP */ +#define _MODEM_CTRL4_ISICOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_ISICOMP_DEFAULT (_MODEM_CTRL4_ISICOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_DEVOFFCOMP (0x1UL << 4) /**< Deviation offset compensation */ +#define _MODEM_CTRL4_DEVOFFCOMP_SHIFT 4 /**< Shift value for MODEM_DEVOFFCOMP */ +#define _MODEM_CTRL4_DEVOFFCOMP_MASK 0x10UL /**< Bit mask for MODEM_DEVOFFCOMP */ +#define _MODEM_CTRL4_DEVOFFCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_DEVOFFCOMP_DEFAULT (_MODEM_CTRL4_DEVOFFCOMP_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_PREDISTGAIN_SHIFT 5 /**< Shift value for MODEM_PREDISTGAIN */ +#define _MODEM_CTRL4_PREDISTGAIN_MASK 0x3E0UL /**< Bit mask for MODEM_PREDISTGAIN */ +#define _MODEM_CTRL4_PREDISTGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTGAIN_DEFAULT (_MODEM_CTRL4_PREDISTGAIN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_PREDISTDEB_SHIFT 10 /**< Shift value for MODEM_PREDISTDEB */ +#define _MODEM_CTRL4_PREDISTDEB_MASK 0x1C00UL /**< Bit mask for MODEM_PREDISTDEB */ +#define _MODEM_CTRL4_PREDISTDEB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTDEB_DEFAULT (_MODEM_CTRL4_PREDISTDEB_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTAVG (0x1UL << 13) /**< Predistortion Average */ +#define _MODEM_CTRL4_PREDISTAVG_SHIFT 13 /**< Shift value for MODEM_PREDISTAVG */ +#define _MODEM_CTRL4_PREDISTAVG_MASK 0x2000UL /**< Bit mask for MODEM_PREDISTAVG */ +#define _MODEM_CTRL4_PREDISTAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_PREDISTAVG_AVG8 0x00000000UL /**< Mode AVG8 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_PREDISTAVG_AVG16 0x00000001UL /**< Mode AVG16 for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTAVG_DEFAULT (_MODEM_CTRL4_PREDISTAVG_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTAVG_AVG8 (_MODEM_CTRL4_PREDISTAVG_AVG8 << 13) /**< Shifted mode AVG8 for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTAVG_AVG16 (_MODEM_CTRL4_PREDISTAVG_AVG16 << 13) /**< Shifted mode AVG16 for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTRST (0x1UL << 14) /**< Predistortion Reset */ +#define _MODEM_CTRL4_PREDISTRST_SHIFT 14 /**< Shift value for MODEM_PREDISTRST */ +#define _MODEM_CTRL4_PREDISTRST_MASK 0x4000UL /**< Bit mask for MODEM_PREDISTRST */ +#define _MODEM_CTRL4_PREDISTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PREDISTRST_DEFAULT (_MODEM_CTRL4_PREDISTRST_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_PHASECLICKFILT_SHIFT 15 /**< Shift value for MODEM_PHASECLICKFILT */ +#define _MODEM_CTRL4_PHASECLICKFILT_MASK 0x3F8000UL /**< Bit mask for MODEM_PHASECLICKFILT */ +#define _MODEM_CTRL4_PHASECLICKFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_PHASECLICKFILT_DEFAULT (_MODEM_CTRL4_PHASECLICKFILT_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_SOFTDSSSMODE (0x1UL << 22) /**< Soft DSSS mode */ +#define _MODEM_CTRL4_SOFTDSSSMODE_SHIFT 22 /**< Shift value for MODEM_SOFTDSSSMODE */ +#define _MODEM_CTRL4_SOFTDSSSMODE_MASK 0x400000UL /**< Bit mask for MODEM_SOFTDSSSMODE */ +#define _MODEM_CTRL4_SOFTDSSSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_SOFTDSSSMODE_CORR0INV 0x00000000UL /**< Mode CORR0INV for MODEM_CTRL4 */ +#define _MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF 0x00000001UL /**< Mode CORRDIFF for MODEM_CTRL4 */ +#define MODEM_CTRL4_SOFTDSSSMODE_DEFAULT (_MODEM_CTRL4_SOFTDSSSMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_SOFTDSSSMODE_CORR0INV (_MODEM_CTRL4_SOFTDSSSMODE_CORR0INV << 22) /**< Shifted mode CORR0INV for MODEM_CTRL4 */ +#define MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF (_MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF << 22) /**< Shifted mode CORRDIFF for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_SHIFT 23 /**< Shift value for MODEM_ADCSATLEVEL */ +#define _MODEM_CTRL4_ADCSATLEVEL_MASK 0x3800000UL /**< Bit mask for MODEM_ADCSATLEVEL */ +#define _MODEM_CTRL4_ADCSATLEVEL_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS1 0x00000000UL /**< Mode CONS1 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS2 0x00000001UL /**< Mode CONS2 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS4 0x00000002UL /**< Mode CONS4 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS8 0x00000003UL /**< Mode CONS8 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS16 0x00000004UL /**< Mode CONS16 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS32 0x00000005UL /**< Mode CONS32 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATLEVEL_CONS64 0x00000006UL /**< Mode CONS64 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_DEFAULT (_MODEM_CTRL4_ADCSATLEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS1 (_MODEM_CTRL4_ADCSATLEVEL_CONS1 << 23) /**< Shifted mode CONS1 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS2 (_MODEM_CTRL4_ADCSATLEVEL_CONS2 << 23) /**< Shifted mode CONS2 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS4 (_MODEM_CTRL4_ADCSATLEVEL_CONS4 << 23) /**< Shifted mode CONS4 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS8 (_MODEM_CTRL4_ADCSATLEVEL_CONS8 << 23) /**< Shifted mode CONS8 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS16 (_MODEM_CTRL4_ADCSATLEVEL_CONS16 << 23) /**< Shifted mode CONS16 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS32 (_MODEM_CTRL4_ADCSATLEVEL_CONS32 << 23) /**< Shifted mode CONS32 for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATLEVEL_CONS64 (_MODEM_CTRL4_ADCSATLEVEL_CONS64 << 23) /**< Shifted mode CONS64 for MODEM_CTRL4 */ +#define _MODEM_CTRL4_ADCSATDENS_SHIFT 26 /**< Shift value for MODEM_ADCSATDENS */ +#define _MODEM_CTRL4_ADCSATDENS_MASK 0xC000000UL /**< Bit mask for MODEM_ADCSATDENS */ +#define _MODEM_CTRL4_ADCSATDENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_ADCSATDENS_DEFAULT (_MODEM_CTRL4_ADCSATDENS_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_OFFSETPHASEMASKING (0x1UL << 28) /**< Offset phase masking */ +#define _MODEM_CTRL4_OFFSETPHASEMASKING_SHIFT 28 /**< Shift value for MODEM_OFFSETPHASEMASKING */ +#define _MODEM_CTRL4_OFFSETPHASEMASKING_MASK 0x10000000UL /**< Bit mask for MODEM_OFFSETPHASEMASKING */ +#define _MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT (_MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_OFFSETPHASESCALING (0x1UL << 29) /**< Offset phase scaling */ +#define _MODEM_CTRL4_OFFSETPHASESCALING_SHIFT 29 /**< Shift value for MODEM_OFFSETPHASESCALING */ +#define _MODEM_CTRL4_OFFSETPHASESCALING_MASK 0x20000000UL /**< Bit mask for MODEM_OFFSETPHASESCALING */ +#define _MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */ +#define MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT (_MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL4 */ + +/* Bit fields for MODEM CTRL5 */ +#define _MODEM_CTRL5_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL5 */ +#define _MODEM_CTRL5_MASK 0x6F7FFFFEUL /**< Mask for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALEN (0x1UL << 1) /**< Baudrate calibration enable */ +#define _MODEM_CTRL5_BRCALEN_SHIFT 1 /**< Shift value for MODEM_BRCALEN */ +#define _MODEM_CTRL5_BRCALEN_MASK 0x2UL /**< Bit mask for MODEM_BRCALEN */ +#define _MODEM_CTRL5_BRCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALEN_DEFAULT (_MODEM_CTRL5_BRCALEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BRCALMODE_SHIFT 2 /**< Shift value for MODEM_BRCALMODE */ +#define _MODEM_CTRL5_BRCALMODE_MASK 0xCUL /**< Bit mask for MODEM_BRCALMODE */ +#define _MODEM_CTRL5_BRCALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BRCALMODE_PEAK 0x00000000UL /**< Mode PEAK for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BRCALMODE_ZERO 0x00000001UL /**< Mode ZERO for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BRCALMODE_PEAKZERO 0x00000002UL /**< Mode PEAKZERO for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALMODE_DEFAULT (_MODEM_CTRL5_BRCALMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALMODE_PEAK (_MODEM_CTRL5_BRCALMODE_PEAK << 2) /**< Shifted mode PEAK for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALMODE_ZERO (_MODEM_CTRL5_BRCALMODE_ZERO << 2) /**< Shifted mode ZERO for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALMODE_PEAKZERO (_MODEM_CTRL5_BRCALMODE_PEAKZERO << 2) /**< Shifted mode PEAKZERO for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BRCALAVG_SHIFT 4 /**< Shift value for MODEM_BRCALAVG */ +#define _MODEM_CTRL5_BRCALAVG_MASK 0x30UL /**< Bit mask for MODEM_BRCALAVG */ +#define _MODEM_CTRL5_BRCALAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_BRCALAVG_DEFAULT (_MODEM_CTRL5_BRCALAVG_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DETDEL_SHIFT 6 /**< Shift value for MODEM_DETDEL */ +#define _MODEM_CTRL5_DETDEL_MASK 0x1C0UL /**< Bit mask for MODEM_DETDEL */ +#define _MODEM_CTRL5_DETDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_DETDEL_DEFAULT (_MODEM_CTRL5_DETDEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_TDEDGE (0x1UL << 9) /**< Timing detection edge mode */ +#define _MODEM_CTRL5_TDEDGE_SHIFT 9 /**< Shift value for MODEM_TDEDGE */ +#define _MODEM_CTRL5_TDEDGE_MASK 0x200UL /**< Bit mask for MODEM_TDEDGE */ +#define _MODEM_CTRL5_TDEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_TDEDGE_DEFAULT (_MODEM_CTRL5_TDEDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_TREDGE (0x1UL << 10) /**< Timing resynchronization edge mode */ +#define _MODEM_CTRL5_TREDGE_SHIFT 10 /**< Shift value for MODEM_TREDGE */ +#define _MODEM_CTRL5_TREDGE_MASK 0x400UL /**< Bit mask for MODEM_TREDGE */ +#define _MODEM_CTRL5_TREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_TREDGE_DEFAULT (_MODEM_CTRL5_TREDGE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_DSSSCTD (0x1UL << 11) /**< DSSS Correlation Threshold Disable */ +#define _MODEM_CTRL5_DSSSCTD_SHIFT 11 /**< Shift value for MODEM_DSSSCTD */ +#define _MODEM_CTRL5_DSSSCTD_MASK 0x800UL /**< Bit mask for MODEM_DSSSCTD */ +#define _MODEM_CTRL5_DSSSCTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_DSSSCTD_DEFAULT (_MODEM_CTRL5_DSSSCTD_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_BBSS_SHIFT 12 /**< Shift value for MODEM_BBSS */ +#define _MODEM_CTRL5_BBSS_MASK 0xF000UL /**< Bit mask for MODEM_BBSS */ +#define _MODEM_CTRL5_BBSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_BBSS_DEFAULT (_MODEM_CTRL5_BBSS_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_POEPER_SHIFT 16 /**< Shift value for MODEM_POEPER */ +#define _MODEM_CTRL5_POEPER_MASK 0xF0000UL /**< Bit mask for MODEM_POEPER */ +#define _MODEM_CTRL5_POEPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_POEPER_DEFAULT (_MODEM_CTRL5_POEPER_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_SHIFT 20 /**< Shift value for MODEM_DEMODRAWDATASEL2 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_MASK 0x700000UL /**< Bit mask for MODEM_DEMODRAWDATASEL2 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_COH 0x00000001UL /**< Mode COH for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_CORR 0x00000002UL /**< Mode CORR for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_CHPW 0x00000003UL /**< Mode CHPW for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_BBPF 0x00000004UL /**< Mode BBPF for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_FSM 0x00000005UL /**< Mode FSM for MODEM_CTRL5 */ +#define _MODEM_CTRL5_DEMODRAWDATASEL2_HADM 0x00000006UL /**< Mode HADM for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT (_MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_DIS (_MODEM_CTRL5_DEMODRAWDATASEL2_DIS << 20) /**< Shifted mode DIS for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_COH (_MODEM_CTRL5_DEMODRAWDATASEL2_COH << 20) /**< Shifted mode COH for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_CORR (_MODEM_CTRL5_DEMODRAWDATASEL2_CORR << 20) /**< Shifted mode CORR for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_CHPW (_MODEM_CTRL5_DEMODRAWDATASEL2_CHPW << 20) /**< Shifted mode CHPW for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_BBPF (_MODEM_CTRL5_DEMODRAWDATASEL2_BBPF << 20) /**< Shifted mode BBPF for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_FSM (_MODEM_CTRL5_DEMODRAWDATASEL2_FSM << 20) /**< Shifted mode FSM for MODEM_CTRL5 */ +#define MODEM_CTRL5_DEMODRAWDATASEL2_HADM (_MODEM_CTRL5_DEMODRAWDATASEL2_HADM << 20) /**< Shifted mode HADM for MODEM_CTRL5 */ +#define _MODEM_CTRL5_FOEPREAVG_SHIFT 24 /**< Shift value for MODEM_FOEPREAVG */ +#define _MODEM_CTRL5_FOEPREAVG_MASK 0x7000000UL /**< Bit mask for MODEM_FOEPREAVG */ +#define _MODEM_CTRL5_FOEPREAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_FOEPREAVG_DEFAULT (_MODEM_CTRL5_FOEPREAVG_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_LINCORR (0x1UL << 27) /**< Linear Correlation */ +#define _MODEM_CTRL5_LINCORR_SHIFT 27 /**< Shift value for MODEM_LINCORR */ +#define _MODEM_CTRL5_LINCORR_MASK 0x8000000UL /**< Bit mask for MODEM_LINCORR */ +#define _MODEM_CTRL5_LINCORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_LINCORR_DEFAULT (_MODEM_CTRL5_LINCORR_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCBAUDTRANS (0x1UL << 29) /**< Resynchronization Baud Transitions */ +#define _MODEM_CTRL5_RESYNCBAUDTRANS_SHIFT 29 /**< Shift value for MODEM_RESYNCBAUDTRANS */ +#define _MODEM_CTRL5_RESYNCBAUDTRANS_MASK 0x20000000UL /**< Bit mask for MODEM_RESYNCBAUDTRANS */ +#define _MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT (_MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCLIMIT (0x1UL << 30) /**< Resynchronization Limit */ +#define _MODEM_CTRL5_RESYNCLIMIT_SHIFT 30 /**< Shift value for MODEM_RESYNCLIMIT */ +#define _MODEM_CTRL5_RESYNCLIMIT_MASK 0x40000000UL /**< Bit mask for MODEM_RESYNCLIMIT */ +#define _MODEM_CTRL5_RESYNCLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */ +#define _MODEM_CTRL5_RESYNCLIMIT_HALF 0x00000000UL /**< Mode HALF for MODEM_CTRL5 */ +#define _MODEM_CTRL5_RESYNCLIMIT_ALWAYS 0x00000001UL /**< Mode ALWAYS for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCLIMIT_DEFAULT (_MODEM_CTRL5_RESYNCLIMIT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCLIMIT_HALF (_MODEM_CTRL5_RESYNCLIMIT_HALF << 30) /**< Shifted mode HALF for MODEM_CTRL5 */ +#define MODEM_CTRL5_RESYNCLIMIT_ALWAYS (_MODEM_CTRL5_RESYNCLIMIT_ALWAYS << 30) /**< Shifted mode ALWAYS for MODEM_CTRL5 */ + +/* Bit fields for MODEM CTRL6 */ +#define _MODEM_CTRL6_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL6 */ +#define _MODEM_CTRL6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL6 */ +#define _MODEM_CTRL6_TDREW_SHIFT 0 /**< Shift value for MODEM_TDREW */ +#define _MODEM_CTRL6_TDREW_MASK 0x7FUL /**< Bit mask for MODEM_TDREW */ +#define _MODEM_CTRL6_TDREW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TDREW_DEFAULT (_MODEM_CTRL6_TDREW_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_PREBASES_SHIFT 7 /**< Shift value for MODEM_PREBASES */ +#define _MODEM_CTRL6_PREBASES_MASK 0x780UL /**< Bit mask for MODEM_PREBASES */ +#define _MODEM_CTRL6_PREBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PREBASES_DEFAULT (_MODEM_CTRL6_PREBASES_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT0 (0x1UL << 11) /**< Preamble Search Timing Abort Criteria 0 */ +#define _MODEM_CTRL6_PSTIMABORT0_SHIFT 11 /**< Shift value for MODEM_PSTIMABORT0 */ +#define _MODEM_CTRL6_PSTIMABORT0_MASK 0x800UL /**< Bit mask for MODEM_PSTIMABORT0 */ +#define _MODEM_CTRL6_PSTIMABORT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT0_DEFAULT (_MODEM_CTRL6_PSTIMABORT0_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT1 (0x1UL << 12) /**< Preamble Search Timing Abort Criteria 1 */ +#define _MODEM_CTRL6_PSTIMABORT1_SHIFT 12 /**< Shift value for MODEM_PSTIMABORT1 */ +#define _MODEM_CTRL6_PSTIMABORT1_MASK 0x1000UL /**< Bit mask for MODEM_PSTIMABORT1 */ +#define _MODEM_CTRL6_PSTIMABORT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT1_DEFAULT (_MODEM_CTRL6_PSTIMABORT1_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT2 (0x1UL << 13) /**< Preamble Search Timing Abort Criteria 2 */ +#define _MODEM_CTRL6_PSTIMABORT2_SHIFT 13 /**< Shift value for MODEM_PSTIMABORT2 */ +#define _MODEM_CTRL6_PSTIMABORT2_MASK 0x2000UL /**< Bit mask for MODEM_PSTIMABORT2 */ +#define _MODEM_CTRL6_PSTIMABORT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT2_DEFAULT (_MODEM_CTRL6_PSTIMABORT2_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT3 (0x1UL << 14) /**< Preamble Search Timing Abort Criteria 3 */ +#define _MODEM_CTRL6_PSTIMABORT3_SHIFT 14 /**< Shift value for MODEM_PSTIMABORT3 */ +#define _MODEM_CTRL6_PSTIMABORT3_MASK 0x4000UL /**< Bit mask for MODEM_PSTIMABORT3 */ +#define _MODEM_CTRL6_PSTIMABORT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_PSTIMABORT3_DEFAULT (_MODEM_CTRL6_PSTIMABORT3_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_ARW_SHIFT 15 /**< Shift value for MODEM_ARW */ +#define _MODEM_CTRL6_ARW_MASK 0x18000UL /**< Bit mask for MODEM_ARW */ +#define _MODEM_CTRL6_ARW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_ARW_SMALLWND 0x00000000UL /**< Mode SMALLWND for MODEM_CTRL6 */ +#define _MODEM_CTRL6_ARW_ALWAYS 0x00000001UL /**< Mode ALWAYS for MODEM_CTRL6 */ +#define _MODEM_CTRL6_ARW_NEVER 0x00000002UL /**< Mode NEVER for MODEM_CTRL6 */ +#define _MODEM_CTRL6_ARW_PSABORT 0x00000003UL /**< Mode PSABORT for MODEM_CTRL6 */ +#define MODEM_CTRL6_ARW_DEFAULT (_MODEM_CTRL6_ARW_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_ARW_SMALLWND (_MODEM_CTRL6_ARW_SMALLWND << 15) /**< Shifted mode SMALLWND for MODEM_CTRL6 */ +#define MODEM_CTRL6_ARW_ALWAYS (_MODEM_CTRL6_ARW_ALWAYS << 15) /**< Shifted mode ALWAYS for MODEM_CTRL6 */ +#define MODEM_CTRL6_ARW_NEVER (_MODEM_CTRL6_ARW_NEVER << 15) /**< Shifted mode NEVER for MODEM_CTRL6 */ +#define MODEM_CTRL6_ARW_PSABORT (_MODEM_CTRL6_ARW_PSABORT << 15) /**< Shifted mode PSABORT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_TIMTHRESHGAIN_SHIFT 17 /**< Shift value for MODEM_TIMTHRESHGAIN */ +#define _MODEM_CTRL6_TIMTHRESHGAIN_MASK 0xE0000UL /**< Bit mask for MODEM_TIMTHRESHGAIN */ +#define _MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT (_MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_CPLXCORREN (0x1UL << 20) /**< Enable Complex Correlation */ +#define _MODEM_CTRL6_CPLXCORREN_SHIFT 20 /**< Shift value for MODEM_CPLXCORREN */ +#define _MODEM_CTRL6_CPLXCORREN_MASK 0x100000UL /**< Bit mask for MODEM_CPLXCORREN */ +#define _MODEM_CTRL6_CPLXCORREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_CPLXCORREN_DEFAULT (_MODEM_CTRL6_CPLXCORREN_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_DSSS3SYMBOLSYNCEN (0x1UL << 21) /**< Enable three symbol sync detection */ +#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_SHIFT 21 /**< Shift value for MODEM_DSSS3SYMBOLSYNCEN */ +#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_MASK 0x200000UL /**< Bit mask for MODEM_DSSS3SYMBOLSYNCEN */ +#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT (_MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TXDBPSKINV (0x1UL << 22) /**< TX DBPSK modulation encode invert */ +#define _MODEM_CTRL6_TXDBPSKINV_SHIFT 22 /**< Shift value for MODEM_TXDBPSKINV */ +#define _MODEM_CTRL6_TXDBPSKINV_MASK 0x400000UL /**< Bit mask for MODEM_TXDBPSKINV */ +#define _MODEM_CTRL6_TXDBPSKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TXDBPSKINV_DEFAULT (_MODEM_CTRL6_TXDBPSKINV_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TXDBPSKRAMPEN (0x1UL << 23) /**< TX DBPSK PA Ramp Enable */ +#define _MODEM_CTRL6_TXDBPSKRAMPEN_SHIFT 23 /**< Shift value for MODEM_TXDBPSKRAMPEN */ +#define _MODEM_CTRL6_TXDBPSKRAMPEN_MASK 0x800000UL /**< Bit mask for MODEM_TXDBPSKRAMPEN */ +#define _MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT (_MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_IFADCDIGGAINCLKSEL (0x1UL << 24) /**< IFADC Output Dig Gain Clock Select */ +#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_SHIFT 24 /**< Shift value for MODEM_IFADCDIGGAINCLKSEL */ +#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_MASK 0x1000000UL /**< Bit mask for MODEM_IFADCDIGGAINCLKSEL */ +#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT (_MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_CODINGB_SHIFT 25 /**< Shift value for MODEM_CODINGB */ +#define _MODEM_CTRL6_CODINGB_MASK 0x6000000UL /**< Bit mask for MODEM_CODINGB */ +#define _MODEM_CTRL6_CODINGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define _MODEM_CTRL6_CODINGB_NRZ 0x00000000UL /**< Mode NRZ for MODEM_CTRL6 */ +#define _MODEM_CTRL6_CODINGB_MANCHESTER 0x00000001UL /**< Mode MANCHESTER for MODEM_CTRL6 */ +#define _MODEM_CTRL6_CODINGB_DSSS 0x00000002UL /**< Mode DSSS for MODEM_CTRL6 */ +#define _MODEM_CTRL6_CODINGB_LINECODE 0x00000003UL /**< Mode LINECODE for MODEM_CTRL6 */ +#define MODEM_CTRL6_CODINGB_DEFAULT (_MODEM_CTRL6_CODINGB_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_CODINGB_NRZ (_MODEM_CTRL6_CODINGB_NRZ << 25) /**< Shifted mode NRZ for MODEM_CTRL6 */ +#define MODEM_CTRL6_CODINGB_MANCHESTER (_MODEM_CTRL6_CODINGB_MANCHESTER << 25) /**< Shifted mode MANCHESTER for MODEM_CTRL6 */ +#define MODEM_CTRL6_CODINGB_DSSS (_MODEM_CTRL6_CODINGB_DSSS << 25) /**< Shifted mode DSSS for MODEM_CTRL6 */ +#define MODEM_CTRL6_CODINGB_LINECODE (_MODEM_CTRL6_CODINGB_LINECODE << 25) /**< Shifted mode LINECODE for MODEM_CTRL6 */ +#define MODEM_CTRL6_IFADCDIGGAIN (0x1UL << 27) /**< IFADC Output Dig Gain Select */ +#define _MODEM_CTRL6_IFADCDIGGAIN_SHIFT 27 /**< Shift value for MODEM_IFADCDIGGAIN */ +#define _MODEM_CTRL6_IFADCDIGGAIN_MASK 0x8000000UL /**< Bit mask for MODEM_IFADCDIGGAIN */ +#define _MODEM_CTRL6_IFADCDIGGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_IFADCDIGGAIN_DEFAULT (_MODEM_CTRL6_IFADCDIGGAIN_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_RXBRCALCDIS (0x1UL << 30) /**< RX Baudrate Calculation Disable */ +#define _MODEM_CTRL6_RXBRCALCDIS_SHIFT 30 /**< Shift value for MODEM_RXBRCALCDIS */ +#define _MODEM_CTRL6_RXBRCALCDIS_MASK 0x40000000UL /**< Bit mask for MODEM_RXBRCALCDIS */ +#define _MODEM_CTRL6_RXBRCALCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */ +#define MODEM_CTRL6_RXBRCALCDIS_DEFAULT (_MODEM_CTRL6_RXBRCALCDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL6 */ + +/* Bit fields for MODEM TXBR */ +#define _MODEM_TXBR_RESETVALUE 0x00000000UL /**< Default value for MODEM_TXBR */ +#define _MODEM_TXBR_MASK 0x00FFFFFFUL /**< Mask for MODEM_TXBR */ +#define _MODEM_TXBR_TXBRNUM_SHIFT 0 /**< Shift value for MODEM_TXBRNUM */ +#define _MODEM_TXBR_TXBRNUM_MASK 0xFFFFUL /**< Bit mask for MODEM_TXBRNUM */ +#define _MODEM_TXBR_TXBRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TXBR */ +#define MODEM_TXBR_TXBRNUM_DEFAULT (_MODEM_TXBR_TXBRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TXBR */ +#define _MODEM_TXBR_TXBRDEN_SHIFT 16 /**< Shift value for MODEM_TXBRDEN */ +#define _MODEM_TXBR_TXBRDEN_MASK 0xFF0000UL /**< Bit mask for MODEM_TXBRDEN */ +#define _MODEM_TXBR_TXBRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TXBR */ +#define MODEM_TXBR_TXBRDEN_DEFAULT (_MODEM_TXBR_TXBRDEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TXBR */ + +/* Bit fields for MODEM RXBR */ +#define _MODEM_RXBR_RESETVALUE 0x00000000UL /**< Default value for MODEM_RXBR */ +#define _MODEM_RXBR_MASK 0x00001FFFUL /**< Mask for MODEM_RXBR */ +#define _MODEM_RXBR_RXBRNUM_SHIFT 0 /**< Shift value for MODEM_RXBRNUM */ +#define _MODEM_RXBR_RXBRNUM_MASK 0x1FUL /**< Bit mask for MODEM_RXBRNUM */ +#define _MODEM_RXBR_RXBRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */ +#define MODEM_RXBR_RXBRNUM_DEFAULT (_MODEM_RXBR_RXBRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RXBR */ +#define _MODEM_RXBR_RXBRDEN_SHIFT 5 /**< Shift value for MODEM_RXBRDEN */ +#define _MODEM_RXBR_RXBRDEN_MASK 0x3E0UL /**< Bit mask for MODEM_RXBRDEN */ +#define _MODEM_RXBR_RXBRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */ +#define MODEM_RXBR_RXBRDEN_DEFAULT (_MODEM_RXBR_RXBRDEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_RXBR */ +#define _MODEM_RXBR_RXBRINT_SHIFT 10 /**< Shift value for MODEM_RXBRINT */ +#define _MODEM_RXBR_RXBRINT_MASK 0x1C00UL /**< Bit mask for MODEM_RXBRINT */ +#define _MODEM_RXBR_RXBRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */ +#define MODEM_RXBR_RXBRINT_DEFAULT (_MODEM_RXBR_RXBRINT_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_RXBR */ + +/* Bit fields for MODEM CF */ +#define _MODEM_CF_RESETVALUE 0x00000000UL /**< Default value for MODEM_CF */ +#define _MODEM_CF_MASK 0xCFFFFFFFUL /**< Mask for MODEM_CF */ +#define _MODEM_CF_DEC0_SHIFT 0 /**< Shift value for MODEM_DEC0 */ +#define _MODEM_CF_DEC0_MASK 0x7UL /**< Bit mask for MODEM_DEC0 */ +#define _MODEM_CF_DEC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */ +#define _MODEM_CF_DEC0_DF3 0x00000000UL /**< Mode DF3 for MODEM_CF */ +#define _MODEM_CF_DEC0_DF4WIDE 0x00000001UL /**< Mode DF4WIDE for MODEM_CF */ +#define _MODEM_CF_DEC0_DF4NARROW 0x00000002UL /**< Mode DF4NARROW for MODEM_CF */ +#define _MODEM_CF_DEC0_DF8WIDE 0x00000003UL /**< Mode DF8WIDE for MODEM_CF */ +#define _MODEM_CF_DEC0_DF8NARROW 0x00000004UL /**< Mode DF8NARROW for MODEM_CF */ +#define MODEM_CF_DEC0_DEFAULT (_MODEM_CF_DEC0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CF */ +#define MODEM_CF_DEC0_DF3 (_MODEM_CF_DEC0_DF3 << 0) /**< Shifted mode DF3 for MODEM_CF */ +#define MODEM_CF_DEC0_DF4WIDE (_MODEM_CF_DEC0_DF4WIDE << 0) /**< Shifted mode DF4WIDE for MODEM_CF */ +#define MODEM_CF_DEC0_DF4NARROW (_MODEM_CF_DEC0_DF4NARROW << 0) /**< Shifted mode DF4NARROW for MODEM_CF */ +#define MODEM_CF_DEC0_DF8WIDE (_MODEM_CF_DEC0_DF8WIDE << 0) /**< Shifted mode DF8WIDE for MODEM_CF */ +#define MODEM_CF_DEC0_DF8NARROW (_MODEM_CF_DEC0_DF8NARROW << 0) /**< Shifted mode DF8NARROW for MODEM_CF */ +#define _MODEM_CF_DEC1_SHIFT 3 /**< Shift value for MODEM_DEC1 */ +#define _MODEM_CF_DEC1_MASK 0x1FFF8UL /**< Bit mask for MODEM_DEC1 */ +#define _MODEM_CF_DEC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */ +#define MODEM_CF_DEC1_DEFAULT (_MODEM_CF_DEC1_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CF */ +#define _MODEM_CF_DEC2_SHIFT 17 /**< Shift value for MODEM_DEC2 */ +#define _MODEM_CF_DEC2_MASK 0x7E0000UL /**< Bit mask for MODEM_DEC2 */ +#define _MODEM_CF_DEC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */ +#define MODEM_CF_DEC2_DEFAULT (_MODEM_CF_DEC2_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_CF */ +#define _MODEM_CF_CFOSR_SHIFT 23 /**< Shift value for MODEM_CFOSR */ +#define _MODEM_CF_CFOSR_MASK 0x3800000UL /**< Bit mask for MODEM_CFOSR */ +#define _MODEM_CF_CFOSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF7 0x00000000UL /**< Mode CF7 for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF8 0x00000001UL /**< Mode CF8 for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF12 0x00000002UL /**< Mode CF12 for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF16 0x00000003UL /**< Mode CF16 for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF32 0x00000004UL /**< Mode CF32 for MODEM_CF */ +#define _MODEM_CF_CFOSR_CF0 0x00000005UL /**< Mode CF0 for MODEM_CF */ +#define MODEM_CF_CFOSR_DEFAULT (_MODEM_CF_CFOSR_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CF */ +#define MODEM_CF_CFOSR_CF7 (_MODEM_CF_CFOSR_CF7 << 23) /**< Shifted mode CF7 for MODEM_CF */ +#define MODEM_CF_CFOSR_CF8 (_MODEM_CF_CFOSR_CF8 << 23) /**< Shifted mode CF8 for MODEM_CF */ +#define MODEM_CF_CFOSR_CF12 (_MODEM_CF_CFOSR_CF12 << 23) /**< Shifted mode CF12 for MODEM_CF */ +#define MODEM_CF_CFOSR_CF16 (_MODEM_CF_CFOSR_CF16 << 23) /**< Shifted mode CF16 for MODEM_CF */ +#define MODEM_CF_CFOSR_CF32 (_MODEM_CF_CFOSR_CF32 << 23) /**< Shifted mode CF32 for MODEM_CF */ +#define MODEM_CF_CFOSR_CF0 (_MODEM_CF_CFOSR_CF0 << 23) /**< Shifted mode CF0 for MODEM_CF */ +#define _MODEM_CF_DEC1GAIN_SHIFT 26 /**< Shift value for MODEM_DEC1GAIN */ +#define _MODEM_CF_DEC1GAIN_MASK 0xC000000UL /**< Bit mask for MODEM_DEC1GAIN */ +#define _MODEM_CF_DEC1GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */ +#define _MODEM_CF_DEC1GAIN_ADD0 0x00000000UL /**< Mode ADD0 for MODEM_CF */ +#define _MODEM_CF_DEC1GAIN_ADD6 0x00000001UL /**< Mode ADD6 for MODEM_CF */ +#define _MODEM_CF_DEC1GAIN_ADD12 0x00000002UL /**< Mode ADD12 for MODEM_CF */ +#define MODEM_CF_DEC1GAIN_DEFAULT (_MODEM_CF_DEC1GAIN_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_CF */ +#define MODEM_CF_DEC1GAIN_ADD0 (_MODEM_CF_DEC1GAIN_ADD0 << 26) /**< Shifted mode ADD0 for MODEM_CF */ +#define MODEM_CF_DEC1GAIN_ADD6 (_MODEM_CF_DEC1GAIN_ADD6 << 26) /**< Shifted mode ADD6 for MODEM_CF */ +#define MODEM_CF_DEC1GAIN_ADD12 (_MODEM_CF_DEC1GAIN_ADD12 << 26) /**< Shifted mode ADD12 for MODEM_CF */ + +/* Bit fields for MODEM PRE */ +#define _MODEM_PRE_RESETVALUE 0x00000000UL /**< Default value for MODEM_PRE */ +#define _MODEM_PRE_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PRE */ +#define _MODEM_PRE_BASE_SHIFT 0 /**< Shift value for MODEM_BASE */ +#define _MODEM_PRE_BASE_MASK 0xFUL /**< Bit mask for MODEM_BASE */ +#define _MODEM_PRE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_BASE_DEFAULT (_MODEM_PRE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define _MODEM_PRE_BASEBITS_SHIFT 4 /**< Shift value for MODEM_BASEBITS */ +#define _MODEM_PRE_BASEBITS_MASK 0x30UL /**< Bit mask for MODEM_BASEBITS */ +#define _MODEM_PRE_BASEBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_BASEBITS_DEFAULT (_MODEM_PRE_BASEBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_PRESYMB4FSK (0x1UL << 6) /**< Preamble symbols 4-FSK */ +#define _MODEM_PRE_PRESYMB4FSK_SHIFT 6 /**< Shift value for MODEM_PRESYMB4FSK */ +#define _MODEM_PRE_PRESYMB4FSK_MASK 0x40UL /**< Bit mask for MODEM_PRESYMB4FSK */ +#define _MODEM_PRE_PRESYMB4FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define _MODEM_PRE_PRESYMB4FSK_OUTER 0x00000000UL /**< Mode OUTER for MODEM_PRE */ +#define _MODEM_PRE_PRESYMB4FSK_INNER 0x00000001UL /**< Mode INNER for MODEM_PRE */ +#define MODEM_PRE_PRESYMB4FSK_DEFAULT (_MODEM_PRE_PRESYMB4FSK_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_PRESYMB4FSK_OUTER (_MODEM_PRE_PRESYMB4FSK_OUTER << 6) /**< Shifted mode OUTER for MODEM_PRE */ +#define MODEM_PRE_PRESYMB4FSK_INNER (_MODEM_PRE_PRESYMB4FSK_INNER << 6) /**< Shifted mode INNER for MODEM_PRE */ +#define _MODEM_PRE_PREERRORS_SHIFT 7 /**< Shift value for MODEM_PREERRORS */ +#define _MODEM_PRE_PREERRORS_MASK 0x780UL /**< Bit mask for MODEM_PREERRORS */ +#define _MODEM_PRE_PREERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_PREERRORS_DEFAULT (_MODEM_PRE_PREERRORS_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_DSSSPRE (0x1UL << 11) /**< DSSS preamble */ +#define _MODEM_PRE_DSSSPRE_SHIFT 11 /**< Shift value for MODEM_DSSSPRE */ +#define _MODEM_PRE_DSSSPRE_MASK 0x800UL /**< Bit mask for MODEM_DSSSPRE */ +#define _MODEM_PRE_DSSSPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_DSSSPRE_DEFAULT (_MODEM_PRE_DSSSPRE_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_SYNCSYMB4FSK (0x1UL << 12) /**< Sync symbols 4FSK */ +#define _MODEM_PRE_SYNCSYMB4FSK_SHIFT 12 /**< Shift value for MODEM_SYNCSYMB4FSK */ +#define _MODEM_PRE_SYNCSYMB4FSK_MASK 0x1000UL /**< Bit mask for MODEM_SYNCSYMB4FSK */ +#define _MODEM_PRE_SYNCSYMB4FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define _MODEM_PRE_SYNCSYMB4FSK_FSK2 0x00000000UL /**< Mode FSK2 for MODEM_PRE */ +#define _MODEM_PRE_SYNCSYMB4FSK_FSK4 0x00000001UL /**< Mode FSK4 for MODEM_PRE */ +#define MODEM_PRE_SYNCSYMB4FSK_DEFAULT (_MODEM_PRE_SYNCSYMB4FSK_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_SYNCSYMB4FSK_FSK2 (_MODEM_PRE_SYNCSYMB4FSK_FSK2 << 12) /**< Shifted mode FSK2 for MODEM_PRE */ +#define MODEM_PRE_SYNCSYMB4FSK_FSK4 (_MODEM_PRE_SYNCSYMB4FSK_FSK4 << 12) /**< Shifted mode FSK4 for MODEM_PRE */ +#define MODEM_PRE_PREAMBDETEN (0x1UL << 13) /**< Binary bit preamble det enable */ +#define _MODEM_PRE_PREAMBDETEN_SHIFT 13 /**< Shift value for MODEM_PREAMBDETEN */ +#define _MODEM_PRE_PREAMBDETEN_MASK 0x2000UL /**< Bit mask for MODEM_PREAMBDETEN */ +#define _MODEM_PRE_PREAMBDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_PREAMBDETEN_DEFAULT (_MODEM_PRE_PREAMBDETEN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define _MODEM_PRE_PREWNDERRORS_SHIFT 14 /**< Shift value for MODEM_PREWNDERRORS */ +#define _MODEM_PRE_PREWNDERRORS_MASK 0xC000UL /**< Bit mask for MODEM_PREWNDERRORS */ +#define _MODEM_PRE_PREWNDERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_PREWNDERRORS_DEFAULT (_MODEM_PRE_PREWNDERRORS_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PRE */ +#define _MODEM_PRE_TXBASES_SHIFT 16 /**< Shift value for MODEM_TXBASES */ +#define _MODEM_PRE_TXBASES_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TXBASES */ +#define _MODEM_PRE_TXBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */ +#define MODEM_PRE_TXBASES_DEFAULT (_MODEM_PRE_TXBASES_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PRE */ + +/* Bit fields for MODEM SYNC0 */ +#define _MODEM_SYNC0_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNC0 */ +#define _MODEM_SYNC0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SYNC0 */ +#define _MODEM_SYNC0_SYNC0_SHIFT 0 /**< Shift value for MODEM_SYNC0 */ +#define _MODEM_SYNC0_SYNC0_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_SYNC0 */ +#define _MODEM_SYNC0_SYNC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNC0 */ +#define MODEM_SYNC0_SYNC0_DEFAULT (_MODEM_SYNC0_SYNC0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SYNC0 */ + +/* Bit fields for MODEM SYNC1 */ +#define _MODEM_SYNC1_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNC1 */ +#define _MODEM_SYNC1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SYNC1 */ +#define _MODEM_SYNC1_SYNC1_SHIFT 0 /**< Shift value for MODEM_SYNC1 */ +#define _MODEM_SYNC1_SYNC1_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_SYNC1 */ +#define _MODEM_SYNC1_SYNC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNC1 */ +#define MODEM_SYNC1_SYNC1_DEFAULT (_MODEM_SYNC1_SYNC1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SYNC1 */ + +/* Bit fields for MODEM TIMING */ +#define _MODEM_TIMING_RESETVALUE 0x00000000UL /**< Default value for MODEM_TIMING */ +#define _MODEM_TIMING_MASK 0xFFFFFFFFUL /**< Mask for MODEM_TIMING */ +#define _MODEM_TIMING_TIMTHRESH_SHIFT 0 /**< Shift value for MODEM_TIMTHRESH */ +#define _MODEM_TIMING_TIMTHRESH_MASK 0xFFUL /**< Bit mask for MODEM_TIMTHRESH */ +#define _MODEM_TIMING_TIMTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMTHRESH_DEFAULT (_MODEM_TIMING_TIMTHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_TIMINGBASES_SHIFT 8 /**< Shift value for MODEM_TIMINGBASES */ +#define _MODEM_TIMING_TIMINGBASES_MASK 0xF00UL /**< Bit mask for MODEM_TIMINGBASES */ +#define _MODEM_TIMING_TIMINGBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMINGBASES_DEFAULT (_MODEM_TIMING_TIMINGBASES_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_ADDTIMSEQ_SHIFT 12 /**< Shift value for MODEM_ADDTIMSEQ */ +#define _MODEM_TIMING_ADDTIMSEQ_MASK 0xF000UL /**< Bit mask for MODEM_ADDTIMSEQ */ +#define _MODEM_TIMING_ADDTIMSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_ADDTIMSEQ_DEFAULT (_MODEM_TIMING_ADDTIMSEQ_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMSEQINVEN (0x1UL << 16) /**< Timing sequence inversion enable */ +#define _MODEM_TIMING_TIMSEQINVEN_SHIFT 16 /**< Shift value for MODEM_TIMSEQINVEN */ +#define _MODEM_TIMING_TIMSEQINVEN_MASK 0x10000UL /**< Bit mask for MODEM_TIMSEQINVEN */ +#define _MODEM_TIMING_TIMSEQINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMSEQINVEN_DEFAULT (_MODEM_TIMING_TIMSEQINVEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMSEQSYNC (0x1UL << 17) /**< Timing sequence part of sync-word */ +#define _MODEM_TIMING_TIMSEQSYNC_SHIFT 17 /**< Shift value for MODEM_TIMSEQSYNC */ +#define _MODEM_TIMING_TIMSEQSYNC_MASK 0x20000UL /**< Bit mask for MODEM_TIMSEQSYNC */ +#define _MODEM_TIMING_TIMSEQSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TIMSEQSYNC_DEFAULT (_MODEM_TIMING_TIMSEQSYNC_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_FDM0THRESH_SHIFT 18 /**< Shift value for MODEM_FDM0THRESH */ +#define _MODEM_TIMING_FDM0THRESH_MASK 0x1C0000UL /**< Bit mask for MODEM_FDM0THRESH */ +#define _MODEM_TIMING_FDM0THRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_FDM0THRESH_DEFAULT (_MODEM_TIMING_FDM0THRESH_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_OFFSUBNUM_SHIFT 21 /**< Shift value for MODEM_OFFSUBNUM */ +#define _MODEM_TIMING_OFFSUBNUM_MASK 0x1E00000UL /**< Bit mask for MODEM_OFFSUBNUM */ +#define _MODEM_TIMING_OFFSUBNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_OFFSUBNUM_DEFAULT (_MODEM_TIMING_OFFSUBNUM_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_OFFSUBDEN_SHIFT 25 /**< Shift value for MODEM_OFFSUBDEN */ +#define _MODEM_TIMING_OFFSUBDEN_MASK 0x1E000000UL /**< Bit mask for MODEM_OFFSUBDEN */ +#define _MODEM_TIMING_OFFSUBDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_OFFSUBDEN_DEFAULT (_MODEM_TIMING_OFFSUBDEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TSAGCDEL (0x1UL << 29) /**< Timing Search AGC delay */ +#define _MODEM_TIMING_TSAGCDEL_SHIFT 29 /**< Shift value for MODEM_TSAGCDEL */ +#define _MODEM_TIMING_TSAGCDEL_MASK 0x20000000UL /**< Bit mask for MODEM_TSAGCDEL */ +#define _MODEM_TIMING_TSAGCDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_TSAGCDEL_DEFAULT (_MODEM_TIMING_TSAGCDEL_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_FASTRESYNC_SHIFT 30 /**< Shift value for MODEM_FASTRESYNC */ +#define _MODEM_TIMING_FASTRESYNC_MASK 0xC0000000UL /**< Bit mask for MODEM_FASTRESYNC */ +#define _MODEM_TIMING_FASTRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */ +#define _MODEM_TIMING_FASTRESYNC_DIS 0x00000000UL /**< Mode DIS for MODEM_TIMING */ +#define _MODEM_TIMING_FASTRESYNC_PREDET 0x00000001UL /**< Mode PREDET for MODEM_TIMING */ +#define _MODEM_TIMING_FASTRESYNC_FRAMEDET 0x00000002UL /**< Mode FRAMEDET for MODEM_TIMING */ +#define MODEM_TIMING_FASTRESYNC_DEFAULT (_MODEM_TIMING_FASTRESYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_TIMING */ +#define MODEM_TIMING_FASTRESYNC_DIS (_MODEM_TIMING_FASTRESYNC_DIS << 30) /**< Shifted mode DIS for MODEM_TIMING */ +#define MODEM_TIMING_FASTRESYNC_PREDET (_MODEM_TIMING_FASTRESYNC_PREDET << 30) /**< Shifted mode PREDET for MODEM_TIMING */ +#define MODEM_TIMING_FASTRESYNC_FRAMEDET (_MODEM_TIMING_FASTRESYNC_FRAMEDET << 30) /**< Shifted mode FRAMEDET for MODEM_TIMING */ + +/* Bit fields for MODEM DSSS0 */ +#define _MODEM_DSSS0_RESETVALUE 0x00000000UL /**< Default value for MODEM_DSSS0 */ +#define _MODEM_DSSS0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSSS0 */ +#define _MODEM_DSSS0_DSSS0_SHIFT 0 /**< Shift value for MODEM_DSSS0 */ +#define _MODEM_DSSS0_DSSS0_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_DSSS0 */ +#define _MODEM_DSSS0_DSSS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSSS0 */ +#define MODEM_DSSS0_DSSS0_DEFAULT (_MODEM_DSSS0_DSSS0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSSS0 */ + +/* Bit fields for MODEM MODINDEX */ +#define _MODEM_MODINDEX_RESETVALUE 0x00000000UL /**< Default value for MODEM_MODINDEX */ +#define _MODEM_MODINDEX_MASK 0x003F03FFUL /**< Mask for MODEM_MODINDEX */ +#define _MODEM_MODINDEX_MODINDEXM_SHIFT 0 /**< Shift value for MODEM_MODINDEXM */ +#define _MODEM_MODINDEX_MODINDEXM_MASK 0x1FUL /**< Bit mask for MODEM_MODINDEXM */ +#define _MODEM_MODINDEX_MODINDEXM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */ +#define MODEM_MODINDEX_MODINDEXM_DEFAULT (_MODEM_MODINDEX_MODINDEXM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_MODINDEX */ +#define _MODEM_MODINDEX_MODINDEXE_SHIFT 5 /**< Shift value for MODEM_MODINDEXE */ +#define _MODEM_MODINDEX_MODINDEXE_MASK 0x3E0UL /**< Bit mask for MODEM_MODINDEXE */ +#define _MODEM_MODINDEX_MODINDEXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */ +#define MODEM_MODINDEX_MODINDEXE_DEFAULT (_MODEM_MODINDEX_MODINDEXE_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_MODINDEX */ +#define _MODEM_MODINDEX_FREQGAINE_SHIFT 16 /**< Shift value for MODEM_FREQGAINE */ +#define _MODEM_MODINDEX_FREQGAINE_MASK 0x70000UL /**< Bit mask for MODEM_FREQGAINE */ +#define _MODEM_MODINDEX_FREQGAINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */ +#define MODEM_MODINDEX_FREQGAINE_DEFAULT (_MODEM_MODINDEX_FREQGAINE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_MODINDEX */ +#define _MODEM_MODINDEX_FREQGAINM_SHIFT 19 /**< Shift value for MODEM_FREQGAINM */ +#define _MODEM_MODINDEX_FREQGAINM_MASK 0x380000UL /**< Bit mask for MODEM_FREQGAINM */ +#define _MODEM_MODINDEX_FREQGAINM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */ +#define MODEM_MODINDEX_FREQGAINM_DEFAULT (_MODEM_MODINDEX_FREQGAINM_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_MODINDEX */ + +/* Bit fields for MODEM AFC */ +#define _MODEM_AFC_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFC */ +#define _MODEM_AFC_MASK 0xFFFFFC00UL /**< Mask for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_SHIFT 10 /**< Shift value for MODEM_AFCRXMODE */ +#define _MODEM_AFC_AFCRXMODE_MASK 0x1C00UL /**< Bit mask for MODEM_AFCRXMODE */ +#define _MODEM_AFC_AFCRXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_FREE 0x00000001UL /**< Mode FREE for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_FREEPRESTART 0x00000002UL /**< Mode FREEPRESTART for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_TIMLOCK 0x00000003UL /**< Mode TIMLOCK for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_PRELOCK 0x00000004UL /**< Mode PRELOCK for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_FRAMELOCK 0x00000005UL /**< Mode FRAMELOCK for MODEM_AFC */ +#define _MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART 0x00000006UL /**< Mode FRAMELOCKPRESTART for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_DEFAULT (_MODEM_AFC_AFCRXMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_DIS (_MODEM_AFC_AFCRXMODE_DIS << 10) /**< Shifted mode DIS for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_FREE (_MODEM_AFC_AFCRXMODE_FREE << 10) /**< Shifted mode FREE for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_FREEPRESTART (_MODEM_AFC_AFCRXMODE_FREEPRESTART << 10) /**< Shifted mode FREEPRESTART for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_TIMLOCK (_MODEM_AFC_AFCRXMODE_TIMLOCK << 10) /**< Shifted mode TIMLOCK for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_PRELOCK (_MODEM_AFC_AFCRXMODE_PRELOCK << 10) /**< Shifted mode PRELOCK for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_FRAMELOCK (_MODEM_AFC_AFCRXMODE_FRAMELOCK << 10) /**< Shifted mode FRAMELOCK for MODEM_AFC */ +#define MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART (_MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART << 10) /**< Shifted mode FRAMELOCKPRESTART for MODEM_AFC*/ +#define _MODEM_AFC_AFCTXMODE_SHIFT 13 /**< Shift value for MODEM_AFCTXMODE */ +#define _MODEM_AFC_AFCTXMODE_MASK 0x6000UL /**< Bit mask for MODEM_AFCTXMODE */ +#define _MODEM_AFC_AFCTXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define _MODEM_AFC_AFCTXMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_AFC */ +#define _MODEM_AFC_AFCTXMODE_PRELOCK 0x00000001UL /**< Mode PRELOCK for MODEM_AFC */ +#define _MODEM_AFC_AFCTXMODE_FRAMELOCK 0x00000002UL /**< Mode FRAMELOCK for MODEM_AFC */ +#define MODEM_AFC_AFCTXMODE_DEFAULT (_MODEM_AFC_AFCTXMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCTXMODE_DIS (_MODEM_AFC_AFCTXMODE_DIS << 13) /**< Shifted mode DIS for MODEM_AFC */ +#define MODEM_AFC_AFCTXMODE_PRELOCK (_MODEM_AFC_AFCTXMODE_PRELOCK << 13) /**< Shifted mode PRELOCK for MODEM_AFC */ +#define MODEM_AFC_AFCTXMODE_FRAMELOCK (_MODEM_AFC_AFCTXMODE_FRAMELOCK << 13) /**< Shifted mode FRAMELOCK for MODEM_AFC */ +#define MODEM_AFC_AFCRXCLR (0x1UL << 15) /**< AFCRX clear mode */ +#define _MODEM_AFC_AFCRXCLR_SHIFT 15 /**< Shift value for MODEM_AFCRXCLR */ +#define _MODEM_AFC_AFCRXCLR_MASK 0x8000UL /**< Bit mask for MODEM_AFCRXCLR */ +#define _MODEM_AFC_AFCRXCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCRXCLR_DEFAULT (_MODEM_AFC_AFCRXCLR_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define _MODEM_AFC_AFCDEL_SHIFT 16 /**< Shift value for MODEM_AFCDEL */ +#define _MODEM_AFC_AFCDEL_MASK 0x1F0000UL /**< Bit mask for MODEM_AFCDEL */ +#define _MODEM_AFC_AFCDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCDEL_DEFAULT (_MODEM_AFC_AFCDEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define _MODEM_AFC_AFCAVGPER_SHIFT 21 /**< Shift value for MODEM_AFCAVGPER */ +#define _MODEM_AFC_AFCAVGPER_MASK 0xE00000UL /**< Bit mask for MODEM_AFCAVGPER */ +#define _MODEM_AFC_AFCAVGPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCAVGPER_DEFAULT (_MODEM_AFC_AFCAVGPER_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCLIMRESET (0x1UL << 24) /**< Reset AFCADJRX value */ +#define _MODEM_AFC_AFCLIMRESET_SHIFT 24 /**< Shift value for MODEM_AFCLIMRESET */ +#define _MODEM_AFC_AFCLIMRESET_MASK 0x1000000UL /**< Bit mask for MODEM_AFCLIMRESET */ +#define _MODEM_AFC_AFCLIMRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCLIMRESET_DEFAULT (_MODEM_AFC_AFCLIMRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCONESHOT (0x1UL << 25) /**< AFC One-Shot feature */ +#define _MODEM_AFC_AFCONESHOT_SHIFT 25 /**< Shift value for MODEM_AFCONESHOT */ +#define _MODEM_AFC_AFCONESHOT_MASK 0x2000000UL /**< Bit mask for MODEM_AFCONESHOT */ +#define _MODEM_AFC_AFCONESHOT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCONESHOT_DEFAULT (_MODEM_AFC_AFCONESHOT_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCENINTCOMP (0x1UL << 26) /**< Internal frequency offset compensation */ +#define _MODEM_AFC_AFCENINTCOMP_SHIFT 26 /**< Shift value for MODEM_AFCENINTCOMP */ +#define _MODEM_AFC_AFCENINTCOMP_MASK 0x4000000UL /**< Bit mask for MODEM_AFCENINTCOMP */ +#define _MODEM_AFC_AFCENINTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCENINTCOMP_DEFAULT (_MODEM_AFC_AFCENINTCOMP_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCDSAFREQOFFEST (0x1UL << 27) /**< Consider frequency offset estimation */ +#define _MODEM_AFC_AFCDSAFREQOFFEST_SHIFT 27 /**< Shift value for MODEM_AFCDSAFREQOFFEST */ +#define _MODEM_AFC_AFCDSAFREQOFFEST_MASK 0x8000000UL /**< Bit mask for MODEM_AFCDSAFREQOFFEST */ +#define _MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT (_MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCDELDET (0x1UL << 28) /**< Delay Detection state machine */ +#define _MODEM_AFC_AFCDELDET_SHIFT 28 /**< Shift value for MODEM_AFCDELDET */ +#define _MODEM_AFC_AFCDELDET_MASK 0x10000000UL /**< Bit mask for MODEM_AFCDELDET */ +#define _MODEM_AFC_AFCDELDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCDELDET_DEFAULT (_MODEM_AFC_AFCDELDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define _MODEM_AFC_AFCGEAR_SHIFT 29 /**< Shift value for MODEM_AFCGEAR */ +#define _MODEM_AFC_AFCGEAR_MASK 0x60000000UL /**< Bit mask for MODEM_AFCGEAR */ +#define _MODEM_AFC_AFCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_AFCGEAR_DEFAULT (_MODEM_AFC_AFCGEAR_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_DISAFCCTE (0x1UL << 31) /**< Disable AFC in AoX CTE */ +#define _MODEM_AFC_DISAFCCTE_SHIFT 31 /**< Shift value for MODEM_DISAFCCTE */ +#define _MODEM_AFC_DISAFCCTE_MASK 0x80000000UL /**< Bit mask for MODEM_DISAFCCTE */ +#define _MODEM_AFC_DISAFCCTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */ +#define MODEM_AFC_DISAFCCTE_DEFAULT (_MODEM_AFC_DISAFCCTE_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_AFC */ + +/* Bit fields for MODEM AFCADJLIM */ +#define _MODEM_AFCADJLIM_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJLIM */ +#define _MODEM_AFCADJLIM_MASK 0x0003FFFFUL /**< Mask for MODEM_AFCADJLIM */ +#define _MODEM_AFCADJLIM_AFCADJLIM_SHIFT 0 /**< Shift value for MODEM_AFCADJLIM */ +#define _MODEM_AFCADJLIM_AFCADJLIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_AFCADJLIM */ +#define _MODEM_AFCADJLIM_AFCADJLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJLIM */ +#define MODEM_AFCADJLIM_AFCADJLIM_DEFAULT (_MODEM_AFCADJLIM_AFCADJLIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJLIM */ + +/* Bit fields for MODEM SHAPING0 */ +#define _MODEM_SHAPING0_RESETVALUE 0x22130A04UL /**< Default value for MODEM_SHAPING0 */ +#define _MODEM_SHAPING0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING0 */ +#define _MODEM_SHAPING0_COEFF0_SHIFT 0 /**< Shift value for MODEM_COEFF0 */ +#define _MODEM_SHAPING0_COEFF0_MASK 0xFFUL /**< Bit mask for MODEM_COEFF0 */ +#define _MODEM_SHAPING0_COEFF0_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_SHAPING0 */ +#define MODEM_SHAPING0_COEFF0_DEFAULT (_MODEM_SHAPING0_COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */ +#define _MODEM_SHAPING0_COEFF1_SHIFT 8 /**< Shift value for MODEM_COEFF1 */ +#define _MODEM_SHAPING0_COEFF1_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF1 */ +#define _MODEM_SHAPING0_COEFF1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for MODEM_SHAPING0 */ +#define MODEM_SHAPING0_COEFF1_DEFAULT (_MODEM_SHAPING0_COEFF1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */ +#define _MODEM_SHAPING0_COEFF2_SHIFT 16 /**< Shift value for MODEM_COEFF2 */ +#define _MODEM_SHAPING0_COEFF2_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF2 */ +#define _MODEM_SHAPING0_COEFF2_DEFAULT 0x00000013UL /**< Mode DEFAULT for MODEM_SHAPING0 */ +#define MODEM_SHAPING0_COEFF2_DEFAULT (_MODEM_SHAPING0_COEFF2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */ +#define _MODEM_SHAPING0_COEFF3_SHIFT 24 /**< Shift value for MODEM_COEFF3 */ +#define _MODEM_SHAPING0_COEFF3_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF3 */ +#define _MODEM_SHAPING0_COEFF3_DEFAULT 0x00000022UL /**< Mode DEFAULT for MODEM_SHAPING0 */ +#define MODEM_SHAPING0_COEFF3_DEFAULT (_MODEM_SHAPING0_COEFF3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */ + +/* Bit fields for MODEM SHAPING1 */ +#define _MODEM_SHAPING1_RESETVALUE 0x4F4A4132UL /**< Default value for MODEM_SHAPING1 */ +#define _MODEM_SHAPING1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING1 */ +#define _MODEM_SHAPING1_COEFF4_SHIFT 0 /**< Shift value for MODEM_COEFF4 */ +#define _MODEM_SHAPING1_COEFF4_MASK 0xFFUL /**< Bit mask for MODEM_COEFF4 */ +#define _MODEM_SHAPING1_COEFF4_DEFAULT 0x00000032UL /**< Mode DEFAULT for MODEM_SHAPING1 */ +#define MODEM_SHAPING1_COEFF4_DEFAULT (_MODEM_SHAPING1_COEFF4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */ +#define _MODEM_SHAPING1_COEFF5_SHIFT 8 /**< Shift value for MODEM_COEFF5 */ +#define _MODEM_SHAPING1_COEFF5_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF5 */ +#define _MODEM_SHAPING1_COEFF5_DEFAULT 0x00000041UL /**< Mode DEFAULT for MODEM_SHAPING1 */ +#define MODEM_SHAPING1_COEFF5_DEFAULT (_MODEM_SHAPING1_COEFF5_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */ +#define _MODEM_SHAPING1_COEFF6_SHIFT 16 /**< Shift value for MODEM_COEFF6 */ +#define _MODEM_SHAPING1_COEFF6_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF6 */ +#define _MODEM_SHAPING1_COEFF6_DEFAULT 0x0000004AUL /**< Mode DEFAULT for MODEM_SHAPING1 */ +#define MODEM_SHAPING1_COEFF6_DEFAULT (_MODEM_SHAPING1_COEFF6_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */ +#define _MODEM_SHAPING1_COEFF7_SHIFT 24 /**< Shift value for MODEM_COEFF7 */ +#define _MODEM_SHAPING1_COEFF7_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF7 */ +#define _MODEM_SHAPING1_COEFF7_DEFAULT 0x0000004FUL /**< Mode DEFAULT for MODEM_SHAPING1 */ +#define MODEM_SHAPING1_COEFF7_DEFAULT (_MODEM_SHAPING1_COEFF7_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */ + +/* Bit fields for MODEM SHAPING2 */ +#define _MODEM_SHAPING2_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING2 */ +#define _MODEM_SHAPING2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING2 */ +#define _MODEM_SHAPING2_COEFF8_SHIFT 0 /**< Shift value for MODEM_COEFF8 */ +#define _MODEM_SHAPING2_COEFF8_MASK 0xFFUL /**< Bit mask for MODEM_COEFF8 */ +#define _MODEM_SHAPING2_COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */ +#define MODEM_SHAPING2_COEFF8_DEFAULT (_MODEM_SHAPING2_COEFF8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */ +#define _MODEM_SHAPING2_COEFF9_SHIFT 8 /**< Shift value for MODEM_COEFF9 */ +#define _MODEM_SHAPING2_COEFF9_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF9 */ +#define _MODEM_SHAPING2_COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */ +#define MODEM_SHAPING2_COEFF9_DEFAULT (_MODEM_SHAPING2_COEFF9_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */ +#define _MODEM_SHAPING2_COEFF10_SHIFT 16 /**< Shift value for MODEM_COEFF10 */ +#define _MODEM_SHAPING2_COEFF10_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF10 */ +#define _MODEM_SHAPING2_COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */ +#define MODEM_SHAPING2_COEFF10_DEFAULT (_MODEM_SHAPING2_COEFF10_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */ +#define _MODEM_SHAPING2_COEFF11_SHIFT 24 /**< Shift value for MODEM_COEFF11 */ +#define _MODEM_SHAPING2_COEFF11_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF11 */ +#define _MODEM_SHAPING2_COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */ +#define MODEM_SHAPING2_COEFF11_DEFAULT (_MODEM_SHAPING2_COEFF11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */ + +/* Bit fields for MODEM SHAPING3 */ +#define _MODEM_SHAPING3_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING3 */ +#define _MODEM_SHAPING3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING3 */ +#define _MODEM_SHAPING3_COEFF12_SHIFT 0 /**< Shift value for MODEM_COEFF12 */ +#define _MODEM_SHAPING3_COEFF12_MASK 0xFFUL /**< Bit mask for MODEM_COEFF12 */ +#define _MODEM_SHAPING3_COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */ +#define MODEM_SHAPING3_COEFF12_DEFAULT (_MODEM_SHAPING3_COEFF12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */ +#define _MODEM_SHAPING3_COEFF13_SHIFT 8 /**< Shift value for MODEM_COEFF13 */ +#define _MODEM_SHAPING3_COEFF13_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF13 */ +#define _MODEM_SHAPING3_COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */ +#define MODEM_SHAPING3_COEFF13_DEFAULT (_MODEM_SHAPING3_COEFF13_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */ +#define _MODEM_SHAPING3_COEFF14_SHIFT 16 /**< Shift value for MODEM_COEFF14 */ +#define _MODEM_SHAPING3_COEFF14_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF14 */ +#define _MODEM_SHAPING3_COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */ +#define MODEM_SHAPING3_COEFF14_DEFAULT (_MODEM_SHAPING3_COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */ +#define _MODEM_SHAPING3_COEFF15_SHIFT 24 /**< Shift value for MODEM_COEFF15 */ +#define _MODEM_SHAPING3_COEFF15_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF15 */ +#define _MODEM_SHAPING3_COEFF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */ +#define MODEM_SHAPING3_COEFF15_DEFAULT (_MODEM_SHAPING3_COEFF15_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */ + +/* Bit fields for MODEM SHAPING4 */ +#define _MODEM_SHAPING4_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING4 */ +#define _MODEM_SHAPING4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING4 */ +#define _MODEM_SHAPING4_COEFF16_SHIFT 0 /**< Shift value for MODEM_COEFF16 */ +#define _MODEM_SHAPING4_COEFF16_MASK 0xFFUL /**< Bit mask for MODEM_COEFF16 */ +#define _MODEM_SHAPING4_COEFF16_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */ +#define MODEM_SHAPING4_COEFF16_DEFAULT (_MODEM_SHAPING4_COEFF16_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */ +#define _MODEM_SHAPING4_COEFF17_SHIFT 8 /**< Shift value for MODEM_COEFF17 */ +#define _MODEM_SHAPING4_COEFF17_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF17 */ +#define _MODEM_SHAPING4_COEFF17_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */ +#define MODEM_SHAPING4_COEFF17_DEFAULT (_MODEM_SHAPING4_COEFF17_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */ +#define _MODEM_SHAPING4_COEFF18_SHIFT 16 /**< Shift value for MODEM_COEFF18 */ +#define _MODEM_SHAPING4_COEFF18_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF18 */ +#define _MODEM_SHAPING4_COEFF18_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */ +#define MODEM_SHAPING4_COEFF18_DEFAULT (_MODEM_SHAPING4_COEFF18_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */ +#define _MODEM_SHAPING4_COEFF19_SHIFT 24 /**< Shift value for MODEM_COEFF19 */ +#define _MODEM_SHAPING4_COEFF19_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF19 */ +#define _MODEM_SHAPING4_COEFF19_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */ +#define MODEM_SHAPING4_COEFF19_DEFAULT (_MODEM_SHAPING4_COEFF19_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */ + +/* Bit fields for MODEM SHAPING5 */ +#define _MODEM_SHAPING5_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING5 */ +#define _MODEM_SHAPING5_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING5 */ +#define _MODEM_SHAPING5_COEFF20_SHIFT 0 /**< Shift value for MODEM_COEFF20 */ +#define _MODEM_SHAPING5_COEFF20_MASK 0xFFUL /**< Bit mask for MODEM_COEFF20 */ +#define _MODEM_SHAPING5_COEFF20_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */ +#define MODEM_SHAPING5_COEFF20_DEFAULT (_MODEM_SHAPING5_COEFF20_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */ +#define _MODEM_SHAPING5_COEFF21_SHIFT 8 /**< Shift value for MODEM_COEFF21 */ +#define _MODEM_SHAPING5_COEFF21_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF21 */ +#define _MODEM_SHAPING5_COEFF21_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */ +#define MODEM_SHAPING5_COEFF21_DEFAULT (_MODEM_SHAPING5_COEFF21_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */ +#define _MODEM_SHAPING5_COEFF22_SHIFT 16 /**< Shift value for MODEM_COEFF22 */ +#define _MODEM_SHAPING5_COEFF22_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF22 */ +#define _MODEM_SHAPING5_COEFF22_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */ +#define MODEM_SHAPING5_COEFF22_DEFAULT (_MODEM_SHAPING5_COEFF22_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */ +#define _MODEM_SHAPING5_COEFF23_SHIFT 24 /**< Shift value for MODEM_COEFF23 */ +#define _MODEM_SHAPING5_COEFF23_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF23 */ +#define _MODEM_SHAPING5_COEFF23_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */ +#define MODEM_SHAPING5_COEFF23_DEFAULT (_MODEM_SHAPING5_COEFF23_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */ + +/* Bit fields for MODEM SHAPING6 */ +#define _MODEM_SHAPING6_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING6 */ +#define _MODEM_SHAPING6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING6 */ +#define _MODEM_SHAPING6_COEFF24_SHIFT 0 /**< Shift value for MODEM_COEFF24 */ +#define _MODEM_SHAPING6_COEFF24_MASK 0xFFUL /**< Bit mask for MODEM_COEFF24 */ +#define _MODEM_SHAPING6_COEFF24_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */ +#define MODEM_SHAPING6_COEFF24_DEFAULT (_MODEM_SHAPING6_COEFF24_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */ +#define _MODEM_SHAPING6_COEFF25_SHIFT 8 /**< Shift value for MODEM_COEFF25 */ +#define _MODEM_SHAPING6_COEFF25_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF25 */ +#define _MODEM_SHAPING6_COEFF25_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */ +#define MODEM_SHAPING6_COEFF25_DEFAULT (_MODEM_SHAPING6_COEFF25_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */ +#define _MODEM_SHAPING6_COEFF26_SHIFT 16 /**< Shift value for MODEM_COEFF26 */ +#define _MODEM_SHAPING6_COEFF26_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF26 */ +#define _MODEM_SHAPING6_COEFF26_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */ +#define MODEM_SHAPING6_COEFF26_DEFAULT (_MODEM_SHAPING6_COEFF26_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */ +#define _MODEM_SHAPING6_COEFF27_SHIFT 24 /**< Shift value for MODEM_COEFF27 */ +#define _MODEM_SHAPING6_COEFF27_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF27 */ +#define _MODEM_SHAPING6_COEFF27_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */ +#define MODEM_SHAPING6_COEFF27_DEFAULT (_MODEM_SHAPING6_COEFF27_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */ + +/* Bit fields for MODEM SHAPING7 */ +#define _MODEM_SHAPING7_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING7 */ +#define _MODEM_SHAPING7_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING7 */ +#define _MODEM_SHAPING7_COEFF28_SHIFT 0 /**< Shift value for MODEM_COEFF28 */ +#define _MODEM_SHAPING7_COEFF28_MASK 0xFFUL /**< Bit mask for MODEM_COEFF28 */ +#define _MODEM_SHAPING7_COEFF28_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */ +#define MODEM_SHAPING7_COEFF28_DEFAULT (_MODEM_SHAPING7_COEFF28_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */ +#define _MODEM_SHAPING7_COEFF29_SHIFT 8 /**< Shift value for MODEM_COEFF29 */ +#define _MODEM_SHAPING7_COEFF29_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF29 */ +#define _MODEM_SHAPING7_COEFF29_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */ +#define MODEM_SHAPING7_COEFF29_DEFAULT (_MODEM_SHAPING7_COEFF29_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */ +#define _MODEM_SHAPING7_COEFF30_SHIFT 16 /**< Shift value for MODEM_COEFF30 */ +#define _MODEM_SHAPING7_COEFF30_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF30 */ +#define _MODEM_SHAPING7_COEFF30_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */ +#define MODEM_SHAPING7_COEFF30_DEFAULT (_MODEM_SHAPING7_COEFF30_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */ +#define _MODEM_SHAPING7_COEFF31_SHIFT 24 /**< Shift value for MODEM_COEFF31 */ +#define _MODEM_SHAPING7_COEFF31_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF31 */ +#define _MODEM_SHAPING7_COEFF31_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */ +#define MODEM_SHAPING7_COEFF31_DEFAULT (_MODEM_SHAPING7_COEFF31_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */ + +/* Bit fields for MODEM SHAPING8 */ +#define _MODEM_SHAPING8_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING8 */ +#define _MODEM_SHAPING8_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING8 */ +#define _MODEM_SHAPING8_COEFF32_SHIFT 0 /**< Shift value for MODEM_COEFF32 */ +#define _MODEM_SHAPING8_COEFF32_MASK 0xFFUL /**< Bit mask for MODEM_COEFF32 */ +#define _MODEM_SHAPING8_COEFF32_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */ +#define MODEM_SHAPING8_COEFF32_DEFAULT (_MODEM_SHAPING8_COEFF32_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */ +#define _MODEM_SHAPING8_COEFF33_SHIFT 8 /**< Shift value for MODEM_COEFF33 */ +#define _MODEM_SHAPING8_COEFF33_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF33 */ +#define _MODEM_SHAPING8_COEFF33_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */ +#define MODEM_SHAPING8_COEFF33_DEFAULT (_MODEM_SHAPING8_COEFF33_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */ +#define _MODEM_SHAPING8_COEFF34_SHIFT 16 /**< Shift value for MODEM_COEFF34 */ +#define _MODEM_SHAPING8_COEFF34_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF34 */ +#define _MODEM_SHAPING8_COEFF34_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */ +#define MODEM_SHAPING8_COEFF34_DEFAULT (_MODEM_SHAPING8_COEFF34_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */ +#define _MODEM_SHAPING8_COEFF35_SHIFT 24 /**< Shift value for MODEM_COEFF35 */ +#define _MODEM_SHAPING8_COEFF35_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF35 */ +#define _MODEM_SHAPING8_COEFF35_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */ +#define MODEM_SHAPING8_COEFF35_DEFAULT (_MODEM_SHAPING8_COEFF35_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */ + +/* Bit fields for MODEM SHAPING9 */ +#define _MODEM_SHAPING9_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING9 */ +#define _MODEM_SHAPING9_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING9 */ +#define _MODEM_SHAPING9_COEFF36_SHIFT 0 /**< Shift value for MODEM_COEFF36 */ +#define _MODEM_SHAPING9_COEFF36_MASK 0xFFUL /**< Bit mask for MODEM_COEFF36 */ +#define _MODEM_SHAPING9_COEFF36_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */ +#define MODEM_SHAPING9_COEFF36_DEFAULT (_MODEM_SHAPING9_COEFF36_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */ +#define _MODEM_SHAPING9_COEFF37_SHIFT 8 /**< Shift value for MODEM_COEFF37 */ +#define _MODEM_SHAPING9_COEFF37_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF37 */ +#define _MODEM_SHAPING9_COEFF37_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */ +#define MODEM_SHAPING9_COEFF37_DEFAULT (_MODEM_SHAPING9_COEFF37_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */ +#define _MODEM_SHAPING9_COEFF38_SHIFT 16 /**< Shift value for MODEM_COEFF38 */ +#define _MODEM_SHAPING9_COEFF38_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF38 */ +#define _MODEM_SHAPING9_COEFF38_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */ +#define MODEM_SHAPING9_COEFF38_DEFAULT (_MODEM_SHAPING9_COEFF38_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */ +#define _MODEM_SHAPING9_COEFF39_SHIFT 24 /**< Shift value for MODEM_COEFF39 */ +#define _MODEM_SHAPING9_COEFF39_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF39 */ +#define _MODEM_SHAPING9_COEFF39_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */ +#define MODEM_SHAPING9_COEFF39_DEFAULT (_MODEM_SHAPING9_COEFF39_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */ + +/* Bit fields for MODEM SHAPING10 */ +#define _MODEM_SHAPING10_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING10 */ +#define _MODEM_SHAPING10_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING10 */ +#define _MODEM_SHAPING10_COEFF40_SHIFT 0 /**< Shift value for MODEM_COEFF40 */ +#define _MODEM_SHAPING10_COEFF40_MASK 0xFFUL /**< Bit mask for MODEM_COEFF40 */ +#define _MODEM_SHAPING10_COEFF40_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */ +#define MODEM_SHAPING10_COEFF40_DEFAULT (_MODEM_SHAPING10_COEFF40_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */ +#define _MODEM_SHAPING10_COEFF41_SHIFT 8 /**< Shift value for MODEM_COEFF41 */ +#define _MODEM_SHAPING10_COEFF41_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF41 */ +#define _MODEM_SHAPING10_COEFF41_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */ +#define MODEM_SHAPING10_COEFF41_DEFAULT (_MODEM_SHAPING10_COEFF41_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */ +#define _MODEM_SHAPING10_COEFF42_SHIFT 16 /**< Shift value for MODEM_COEFF42 */ +#define _MODEM_SHAPING10_COEFF42_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF42 */ +#define _MODEM_SHAPING10_COEFF42_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */ +#define MODEM_SHAPING10_COEFF42_DEFAULT (_MODEM_SHAPING10_COEFF42_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */ +#define _MODEM_SHAPING10_COEFF43_SHIFT 24 /**< Shift value for MODEM_COEFF43 */ +#define _MODEM_SHAPING10_COEFF43_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF43 */ +#define _MODEM_SHAPING10_COEFF43_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */ +#define MODEM_SHAPING10_COEFF43_DEFAULT (_MODEM_SHAPING10_COEFF43_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */ + +/* Bit fields for MODEM SHAPING11 */ +#define _MODEM_SHAPING11_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING11 */ +#define _MODEM_SHAPING11_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING11 */ +#define _MODEM_SHAPING11_COEFF44_SHIFT 0 /**< Shift value for MODEM_COEFF44 */ +#define _MODEM_SHAPING11_COEFF44_MASK 0xFFUL /**< Bit mask for MODEM_COEFF44 */ +#define _MODEM_SHAPING11_COEFF44_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */ +#define MODEM_SHAPING11_COEFF44_DEFAULT (_MODEM_SHAPING11_COEFF44_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */ +#define _MODEM_SHAPING11_COEFF45_SHIFT 8 /**< Shift value for MODEM_COEFF45 */ +#define _MODEM_SHAPING11_COEFF45_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF45 */ +#define _MODEM_SHAPING11_COEFF45_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */ +#define MODEM_SHAPING11_COEFF45_DEFAULT (_MODEM_SHAPING11_COEFF45_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */ +#define _MODEM_SHAPING11_COEFF46_SHIFT 16 /**< Shift value for MODEM_COEFF46 */ +#define _MODEM_SHAPING11_COEFF46_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF46 */ +#define _MODEM_SHAPING11_COEFF46_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */ +#define MODEM_SHAPING11_COEFF46_DEFAULT (_MODEM_SHAPING11_COEFF46_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */ +#define _MODEM_SHAPING11_COEFF47_SHIFT 24 /**< Shift value for MODEM_COEFF47 */ +#define _MODEM_SHAPING11_COEFF47_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF47 */ +#define _MODEM_SHAPING11_COEFF47_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */ +#define MODEM_SHAPING11_COEFF47_DEFAULT (_MODEM_SHAPING11_COEFF47_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */ + +/* Bit fields for MODEM SHAPING12 */ +#define _MODEM_SHAPING12_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING12 */ +#define _MODEM_SHAPING12_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING12 */ +#define _MODEM_SHAPING12_COEFF48_SHIFT 0 /**< Shift value for MODEM_COEFF48 */ +#define _MODEM_SHAPING12_COEFF48_MASK 0xFFUL /**< Bit mask for MODEM_COEFF48 */ +#define _MODEM_SHAPING12_COEFF48_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */ +#define MODEM_SHAPING12_COEFF48_DEFAULT (_MODEM_SHAPING12_COEFF48_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */ +#define _MODEM_SHAPING12_COEFF49_SHIFT 8 /**< Shift value for MODEM_COEFF49 */ +#define _MODEM_SHAPING12_COEFF49_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF49 */ +#define _MODEM_SHAPING12_COEFF49_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */ +#define MODEM_SHAPING12_COEFF49_DEFAULT (_MODEM_SHAPING12_COEFF49_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */ +#define _MODEM_SHAPING12_COEFF50_SHIFT 16 /**< Shift value for MODEM_COEFF50 */ +#define _MODEM_SHAPING12_COEFF50_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF50 */ +#define _MODEM_SHAPING12_COEFF50_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */ +#define MODEM_SHAPING12_COEFF50_DEFAULT (_MODEM_SHAPING12_COEFF50_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */ +#define _MODEM_SHAPING12_COEFF51_SHIFT 24 /**< Shift value for MODEM_COEFF51 */ +#define _MODEM_SHAPING12_COEFF51_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF51 */ +#define _MODEM_SHAPING12_COEFF51_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */ +#define MODEM_SHAPING12_COEFF51_DEFAULT (_MODEM_SHAPING12_COEFF51_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */ + +/* Bit fields for MODEM SHAPING13 */ +#define _MODEM_SHAPING13_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING13 */ +#define _MODEM_SHAPING13_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING13 */ +#define _MODEM_SHAPING13_COEFF52_SHIFT 0 /**< Shift value for MODEM_COEFF52 */ +#define _MODEM_SHAPING13_COEFF52_MASK 0xFFUL /**< Bit mask for MODEM_COEFF52 */ +#define _MODEM_SHAPING13_COEFF52_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */ +#define MODEM_SHAPING13_COEFF52_DEFAULT (_MODEM_SHAPING13_COEFF52_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */ +#define _MODEM_SHAPING13_COEFF53_SHIFT 8 /**< Shift value for MODEM_COEFF53 */ +#define _MODEM_SHAPING13_COEFF53_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF53 */ +#define _MODEM_SHAPING13_COEFF53_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */ +#define MODEM_SHAPING13_COEFF53_DEFAULT (_MODEM_SHAPING13_COEFF53_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */ +#define _MODEM_SHAPING13_COEFF54_SHIFT 16 /**< Shift value for MODEM_COEFF54 */ +#define _MODEM_SHAPING13_COEFF54_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF54 */ +#define _MODEM_SHAPING13_COEFF54_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */ +#define MODEM_SHAPING13_COEFF54_DEFAULT (_MODEM_SHAPING13_COEFF54_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */ +#define _MODEM_SHAPING13_COEFF55_SHIFT 24 /**< Shift value for MODEM_COEFF55 */ +#define _MODEM_SHAPING13_COEFF55_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF55 */ +#define _MODEM_SHAPING13_COEFF55_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */ +#define MODEM_SHAPING13_COEFF55_DEFAULT (_MODEM_SHAPING13_COEFF55_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */ + +/* Bit fields for MODEM SHAPING14 */ +#define _MODEM_SHAPING14_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING14 */ +#define _MODEM_SHAPING14_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING14 */ +#define _MODEM_SHAPING14_COEFF56_SHIFT 0 /**< Shift value for MODEM_COEFF56 */ +#define _MODEM_SHAPING14_COEFF56_MASK 0xFFUL /**< Bit mask for MODEM_COEFF56 */ +#define _MODEM_SHAPING14_COEFF56_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */ +#define MODEM_SHAPING14_COEFF56_DEFAULT (_MODEM_SHAPING14_COEFF56_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */ +#define _MODEM_SHAPING14_COEFF57_SHIFT 8 /**< Shift value for MODEM_COEFF57 */ +#define _MODEM_SHAPING14_COEFF57_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF57 */ +#define _MODEM_SHAPING14_COEFF57_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */ +#define MODEM_SHAPING14_COEFF57_DEFAULT (_MODEM_SHAPING14_COEFF57_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */ +#define _MODEM_SHAPING14_COEFF58_SHIFT 16 /**< Shift value for MODEM_COEFF58 */ +#define _MODEM_SHAPING14_COEFF58_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF58 */ +#define _MODEM_SHAPING14_COEFF58_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */ +#define MODEM_SHAPING14_COEFF58_DEFAULT (_MODEM_SHAPING14_COEFF58_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */ +#define _MODEM_SHAPING14_COEFF59_SHIFT 24 /**< Shift value for MODEM_COEFF59 */ +#define _MODEM_SHAPING14_COEFF59_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF59 */ +#define _MODEM_SHAPING14_COEFF59_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */ +#define MODEM_SHAPING14_COEFF59_DEFAULT (_MODEM_SHAPING14_COEFF59_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */ + +/* Bit fields for MODEM SHAPING15 */ +#define _MODEM_SHAPING15_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING15 */ +#define _MODEM_SHAPING15_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING15 */ +#define _MODEM_SHAPING15_COEFF60_SHIFT 0 /**< Shift value for MODEM_COEFF60 */ +#define _MODEM_SHAPING15_COEFF60_MASK 0xFFUL /**< Bit mask for MODEM_COEFF60 */ +#define _MODEM_SHAPING15_COEFF60_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */ +#define MODEM_SHAPING15_COEFF60_DEFAULT (_MODEM_SHAPING15_COEFF60_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */ +#define _MODEM_SHAPING15_COEFF61_SHIFT 8 /**< Shift value for MODEM_COEFF61 */ +#define _MODEM_SHAPING15_COEFF61_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF61 */ +#define _MODEM_SHAPING15_COEFF61_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */ +#define MODEM_SHAPING15_COEFF61_DEFAULT (_MODEM_SHAPING15_COEFF61_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */ +#define _MODEM_SHAPING15_COEFF62_SHIFT 16 /**< Shift value for MODEM_COEFF62 */ +#define _MODEM_SHAPING15_COEFF62_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF62 */ +#define _MODEM_SHAPING15_COEFF62_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */ +#define MODEM_SHAPING15_COEFF62_DEFAULT (_MODEM_SHAPING15_COEFF62_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */ +#define _MODEM_SHAPING15_COEFF63_SHIFT 24 /**< Shift value for MODEM_COEFF63 */ +#define _MODEM_SHAPING15_COEFF63_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF63 */ +#define _MODEM_SHAPING15_COEFF63_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */ +#define MODEM_SHAPING15_COEFF63_DEFAULT (_MODEM_SHAPING15_COEFF63_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */ + +/* Bit fields for MODEM RAMPCTRL */ +#define _MODEM_RAMPCTRL_RESETVALUE 0x00000555UL /**< Default value for MODEM_RAMPCTRL */ +#define _MODEM_RAMPCTRL_MASK 0x00FF1FFFUL /**< Mask for MODEM_RAMPCTRL */ +#define _MODEM_RAMPCTRL_RAMPRATE0_SHIFT 0 /**< Shift value for MODEM_RAMPRATE0 */ +#define _MODEM_RAMPCTRL_RAMPRATE0_MASK 0xFUL /**< Bit mask for MODEM_RAMPRATE0 */ +#define _MODEM_RAMPCTRL_RAMPRATE0_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */ +#define MODEM_RAMPCTRL_RAMPRATE0_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */ +#define _MODEM_RAMPCTRL_RAMPRATE1_SHIFT 4 /**< Shift value for MODEM_RAMPRATE1 */ +#define _MODEM_RAMPCTRL_RAMPRATE1_MASK 0xF0UL /**< Bit mask for MODEM_RAMPRATE1 */ +#define _MODEM_RAMPCTRL_RAMPRATE1_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */ +#define MODEM_RAMPCTRL_RAMPRATE1_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE1_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */ +#define _MODEM_RAMPCTRL_RAMPRATE2_SHIFT 8 /**< Shift value for MODEM_RAMPRATE2 */ +#define _MODEM_RAMPCTRL_RAMPRATE2_MASK 0xF00UL /**< Bit mask for MODEM_RAMPRATE2 */ +#define _MODEM_RAMPCTRL_RAMPRATE2_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */ +#define MODEM_RAMPCTRL_RAMPRATE2_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */ + +/* Bit fields for MODEM RAMPLEV */ +#define _MODEM_RAMPLEV_RESETVALUE 0x009F9F9FUL /**< Default value for MODEM_RAMPLEV */ +#define _MODEM_RAMPLEV_MASK 0x00FFFFFFUL /**< Mask for MODEM_RAMPLEV */ +#define _MODEM_RAMPLEV_RAMPLEV0_SHIFT 0 /**< Shift value for MODEM_RAMPLEV0 */ +#define _MODEM_RAMPLEV_RAMPLEV0_MASK 0xFFUL /**< Bit mask for MODEM_RAMPLEV0 */ +#define _MODEM_RAMPLEV_RAMPLEV0_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */ +#define MODEM_RAMPLEV_RAMPLEV0_DEFAULT (_MODEM_RAMPLEV_RAMPLEV0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */ +#define _MODEM_RAMPLEV_RAMPLEV1_SHIFT 8 /**< Shift value for MODEM_RAMPLEV1 */ +#define _MODEM_RAMPLEV_RAMPLEV1_MASK 0xFF00UL /**< Bit mask for MODEM_RAMPLEV1 */ +#define _MODEM_RAMPLEV_RAMPLEV1_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */ +#define MODEM_RAMPLEV_RAMPLEV1_DEFAULT (_MODEM_RAMPLEV_RAMPLEV1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */ +#define _MODEM_RAMPLEV_RAMPLEV2_SHIFT 16 /**< Shift value for MODEM_RAMPLEV2 */ +#define _MODEM_RAMPLEV_RAMPLEV2_MASK 0xFF0000UL /**< Bit mask for MODEM_RAMPLEV2 */ +#define _MODEM_RAMPLEV_RAMPLEV2_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */ +#define MODEM_RAMPLEV_RAMPLEV2_DEFAULT (_MODEM_RAMPLEV_RAMPLEV2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */ + +/* Bit fields for MODEM ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_RESETVALUE 0x00000A00UL /**< Default value for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MASK 0x00001E06UL /**< Mask for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_RAMPOVREN (0x1UL << 1) /**< PA Analog Ramp Override */ +#define _MODEM_ANARAMPCTRL_RAMPOVREN_SHIFT 1 /**< Shift value for MODEM_RAMPOVREN */ +#define _MODEM_ANARAMPCTRL_RAMPOVREN_MASK 0x2UL /**< Bit mask for MODEM_RAMPOVREN */ +#define _MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT (_MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_RAMPOVRUPD (0x1UL << 2) /**< PA Analog Ramp Override Update Pulse */ +#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_SHIFT 2 /**< Shift value for MODEM_RAMPOVRUPD */ +#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_MASK 0x4UL /**< Bit mask for MODEM_RAMPOVRUPD */ +#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT (_MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_SHIFT 9 /**< Shift value for MODEM_VMIDCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_MASK 0x600UL /**< Bit mask for MODEM_VMIDCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_OFF 0x00000000UL /**< Mode OFF for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_MID 0x00000001UL /**< Mode MID for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_HIGH 0x00000002UL /**< Mode HIGH for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_VMIDCTRL_ON 0x00000003UL /**< Mode ON for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT (_MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_VMIDCTRL_OFF (_MODEM_ANARAMPCTRL_VMIDCTRL_OFF << 9) /**< Shifted mode OFF for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_VMIDCTRL_MID (_MODEM_ANARAMPCTRL_VMIDCTRL_MID << 9) /**< Shifted mode MID for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_VMIDCTRL_HIGH (_MODEM_ANARAMPCTRL_VMIDCTRL_HIGH << 9) /**< Shifted mode HIGH for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_VMIDCTRL_ON (_MODEM_ANARAMPCTRL_VMIDCTRL_ON << 9) /**< Shifted mode ON for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_SHIFT 11 /**< Shift value for MODEM_MUTEDLY */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_MASK 0x1800UL /**< Bit mask for MODEM_MUTEDLY */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0US 0x00000000UL /**< Mode TIME0US for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US 0x00000001UL /**< Mode TIME0P5US for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US 0x00000002UL /**< Mode TIME0P25US for MODEM_ANARAMPCTRL */ +#define _MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED 0x00000003UL /**< Mode NOTUSED for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT (_MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0US << 11) /**< Shifted mode TIME0US for MODEM_ANARAMPCTRL */ +#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US << 11) /**< Shifted mode TIME0P5US for MODEM_ANARAMPCTRL*/ +#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US << 11) /**< Shifted mode TIME0P25US for MODEM_ANARAMPCTRL*/ +#define MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED (_MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED << 11) /**< Shifted mode NOTUSED for MODEM_ANARAMPCTRL */ + +/* Bit fields for MODEM DCCOMP */ +#define _MODEM_DCCOMP_RESETVALUE 0x00000030UL /**< Default value for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_MASK 0x001FFFFFUL /**< Mask for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCESTIEN (0x1UL << 0) /**< DC Offset Estimation Enable */ +#define _MODEM_DCCOMP_DCESTIEN_SHIFT 0 /**< Shift value for MODEM_DCESTIEN */ +#define _MODEM_DCCOMP_DCESTIEN_MASK 0x1UL /**< Bit mask for MODEM_DCESTIEN */ +#define _MODEM_DCCOMP_DCESTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCESTIEN_DEFAULT (_MODEM_DCCOMP_DCESTIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCCOMPEN (0x1UL << 1) /**< DC Offset Compensation Enable */ +#define _MODEM_DCCOMP_DCCOMPEN_SHIFT 1 /**< Shift value for MODEM_DCCOMPEN */ +#define _MODEM_DCCOMP_DCCOMPEN_MASK 0x2UL /**< Bit mask for MODEM_DCCOMPEN */ +#define _MODEM_DCCOMP_DCCOMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCCOMPEN_DEFAULT (_MODEM_DCCOMP_DCCOMPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCRSTEN (0x1UL << 2) /**< DC Compensation Filter Reset Enable */ +#define _MODEM_DCCOMP_DCRSTEN_SHIFT 2 /**< Shift value for MODEM_DCRSTEN */ +#define _MODEM_DCCOMP_DCRSTEN_MASK 0x4UL /**< Bit mask for MODEM_DCRSTEN */ +#define _MODEM_DCCOMP_DCRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCRSTEN_DEFAULT (_MODEM_DCCOMP_DCRSTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCCOMPFREEZE (0x1UL << 3) /**< DC Offset Compensation Filter Freeze */ +#define _MODEM_DCCOMP_DCCOMPFREEZE_SHIFT 3 /**< Shift value for MODEM_DCCOMPFREEZE */ +#define _MODEM_DCCOMP_DCCOMPFREEZE_MASK 0x8UL /**< Bit mask for MODEM_DCCOMPFREEZE */ +#define _MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT (_MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCCOMPGEAR_SHIFT 4 /**< Shift value for MODEM_DCCOMPGEAR */ +#define _MODEM_DCCOMP_DCCOMPGEAR_MASK 0x70UL /**< Bit mask for MODEM_DCCOMPGEAR */ +#define _MODEM_DCCOMP_DCCOMPGEAR_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCCOMPGEAR_DEFAULT (_MODEM_DCCOMP_DCCOMPGEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCLIMIT_SHIFT 7 /**< Shift value for MODEM_DCLIMIT */ +#define _MODEM_DCCOMP_DCLIMIT_MASK 0x180UL /**< Bit mask for MODEM_DCLIMIT */ +#define _MODEM_DCCOMP_DCLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCLIMIT_FULLSCALE 0x00000000UL /**< Mode FULLSCALE for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 0x00000001UL /**< Mode FULLSCALEBY4 for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 0x00000002UL /**< Mode FULLSCALEBY8 for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 0x00000003UL /**< Mode FULLSCALEBY16 for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCLIMIT_DEFAULT (_MODEM_DCCOMP_DCLIMIT_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCLIMIT_FULLSCALE (_MODEM_DCCOMP_DCLIMIT_FULLSCALE << 7) /**< Shifted mode FULLSCALE for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 << 7) /**< Shifted mode FULLSCALEBY4 for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 << 7) /**< Shifted mode FULLSCALEBY8 for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 << 7) /**< Shifted mode FULLSCALEBY16 for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCGAINGEAREN (0x1UL << 9) /**< DC Offset Gain Change Filter Gear Enable */ +#define _MODEM_DCCOMP_DCGAINGEAREN_SHIFT 9 /**< Shift value for MODEM_DCGAINGEAREN */ +#define _MODEM_DCCOMP_DCGAINGEAREN_MASK 0x200UL /**< Bit mask for MODEM_DCGAINGEAREN */ +#define _MODEM_DCCOMP_DCGAINGEAREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCGAINGEAREN_DEFAULT (_MODEM_DCCOMP_DCGAINGEAREN_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCGAINGEAR_SHIFT 10 /**< Shift value for MODEM_DCGAINGEAR */ +#define _MODEM_DCCOMP_DCGAINGEAR_MASK 0x1C00UL /**< Bit mask for MODEM_DCGAINGEAR */ +#define _MODEM_DCCOMP_DCGAINGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCGAINGEAR_DEFAULT (_MODEM_DCCOMP_DCGAINGEAR_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ +#define _MODEM_DCCOMP_DCGAINGEARSMPS_SHIFT 13 /**< Shift value for MODEM_DCGAINGEARSMPS */ +#define _MODEM_DCCOMP_DCGAINGEARSMPS_MASK 0x1FE000UL /**< Bit mask for MODEM_DCGAINGEARSMPS */ +#define _MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */ +#define MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT (_MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_DCCOMP */ + +/* Bit fields for MODEM DCCOMPFILTINIT */ +#define _MODEM_DCCOMPFILTINIT_RESETVALUE 0x00000000UL /**< Default value for MODEM_DCCOMPFILTINIT */ +#define _MODEM_DCCOMPFILTINIT_MASK 0x7FFFFFFFUL /**< Mask for MODEM_DCCOMPFILTINIT */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_SHIFT 0 /**< Shift value for MODEM_DCCOMPINITVALI */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_MASK 0x7FFFUL /**< Bit mask for MODEM_DCCOMPINITVALI */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */ +#define MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_SHIFT 15 /**< Shift value for MODEM_DCCOMPINITVALQ */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_MASK 0x3FFF8000UL /**< Bit mask for MODEM_DCCOMPINITVALQ */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */ +#define MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/ +#define MODEM_DCCOMPFILTINIT_DCCOMPINIT (0x1UL << 30) /**< Initialize filter state */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_SHIFT 30 /**< Shift value for MODEM_DCCOMPINIT */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_MASK 0x40000000UL /**< Bit mask for MODEM_DCCOMPINIT */ +#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */ +#define MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/ + +/* Bit fields for MODEM DCESTI */ +#define _MODEM_DCESTI_RESETVALUE 0x00000000UL /**< Default value for MODEM_DCESTI */ +#define _MODEM_DCESTI_MASK 0x3FFFFFFFUL /**< Mask for MODEM_DCESTI */ +#define _MODEM_DCESTI_DCCOMPESTIVALI_SHIFT 0 /**< Shift value for MODEM_DCCOMPESTIVALI */ +#define _MODEM_DCESTI_DCCOMPESTIVALI_MASK 0x7FFFUL /**< Bit mask for MODEM_DCCOMPESTIVALI */ +#define _MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCESTI */ +#define MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT (_MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCESTI */ +#define _MODEM_DCESTI_DCCOMPESTIVALQ_SHIFT 15 /**< Shift value for MODEM_DCCOMPESTIVALQ */ +#define _MODEM_DCESTI_DCCOMPESTIVALQ_MASK 0x3FFF8000UL /**< Bit mask for MODEM_DCCOMPESTIVALQ */ +#define _MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCESTI */ +#define MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT (_MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_DCESTI */ + +/* Bit fields for MODEM SRCCHF */ +#define _MODEM_SRCCHF_RESETVALUE 0x00000000UL /**< Default value for MODEM_SRCCHF */ +#define _MODEM_SRCCHF_MASK 0x8FFFF000UL /**< Mask for MODEM_SRCCHF */ +#define _MODEM_SRCCHF_SRCRATIO2_SHIFT 12 /**< Shift value for MODEM_SRCRATIO2 */ +#define _MODEM_SRCCHF_SRCRATIO2_MASK 0x7FFF000UL /**< Bit mask for MODEM_SRCRATIO2 */ +#define _MODEM_SRCCHF_SRCRATIO2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */ +#define MODEM_SRCCHF_SRCRATIO2_DEFAULT (_MODEM_SRCCHF_SRCRATIO2_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SRCCHF */ +#define MODEM_SRCCHF_SRCENABLE2 (0x1UL << 27) /**< SRC2 enable */ +#define _MODEM_SRCCHF_SRCENABLE2_SHIFT 27 /**< Shift value for MODEM_SRCENABLE2 */ +#define _MODEM_SRCCHF_SRCENABLE2_MASK 0x8000000UL /**< Bit mask for MODEM_SRCENABLE2 */ +#define _MODEM_SRCCHF_SRCENABLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */ +#define MODEM_SRCCHF_SRCENABLE2_DEFAULT (_MODEM_SRCCHF_SRCENABLE2_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SRCCHF */ +#define MODEM_SRCCHF_INTOSR (0x1UL << 31) /**< Forcing Integer OSR */ +#define _MODEM_SRCCHF_INTOSR_SHIFT 31 /**< Shift value for MODEM_INTOSR */ +#define _MODEM_SRCCHF_INTOSR_MASK 0x80000000UL /**< Bit mask for MODEM_INTOSR */ +#define _MODEM_SRCCHF_INTOSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */ +#define MODEM_SRCCHF_INTOSR_DEFAULT (_MODEM_SRCCHF_INTOSR_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_SRCCHF */ + +/* Bit fields for MODEM INTAFC */ +#define _MODEM_INTAFC_RESETVALUE 0x00000000UL /**< Default value for MODEM_INTAFC */ +#define _MODEM_INTAFC_MASK 0x00FFFFFFUL /**< Mask for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG0_SHIFT 0 /**< Shift value for MODEM_FOEPREAVG0 */ +#define _MODEM_INTAFC_FOEPREAVG0_MASK 0x7UL /**< Bit mask for MODEM_FOEPREAVG0 */ +#define _MODEM_INTAFC_FOEPREAVG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG0_DEFAULT (_MODEM_INTAFC_FOEPREAVG0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG1_SHIFT 3 /**< Shift value for MODEM_FOEPREAVG1 */ +#define _MODEM_INTAFC_FOEPREAVG1_MASK 0x38UL /**< Bit mask for MODEM_FOEPREAVG1 */ +#define _MODEM_INTAFC_FOEPREAVG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG1_DEFAULT (_MODEM_INTAFC_FOEPREAVG1_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG2_SHIFT 6 /**< Shift value for MODEM_FOEPREAVG2 */ +#define _MODEM_INTAFC_FOEPREAVG2_MASK 0x1C0UL /**< Bit mask for MODEM_FOEPREAVG2 */ +#define _MODEM_INTAFC_FOEPREAVG2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG2_DEFAULT (_MODEM_INTAFC_FOEPREAVG2_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG3_SHIFT 9 /**< Shift value for MODEM_FOEPREAVG3 */ +#define _MODEM_INTAFC_FOEPREAVG3_MASK 0xE00UL /**< Bit mask for MODEM_FOEPREAVG3 */ +#define _MODEM_INTAFC_FOEPREAVG3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG3_DEFAULT (_MODEM_INTAFC_FOEPREAVG3_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG4_SHIFT 12 /**< Shift value for MODEM_FOEPREAVG4 */ +#define _MODEM_INTAFC_FOEPREAVG4_MASK 0x7000UL /**< Bit mask for MODEM_FOEPREAVG4 */ +#define _MODEM_INTAFC_FOEPREAVG4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG4_DEFAULT (_MODEM_INTAFC_FOEPREAVG4_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG5_SHIFT 15 /**< Shift value for MODEM_FOEPREAVG5 */ +#define _MODEM_INTAFC_FOEPREAVG5_MASK 0x38000UL /**< Bit mask for MODEM_FOEPREAVG5 */ +#define _MODEM_INTAFC_FOEPREAVG5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG5_DEFAULT (_MODEM_INTAFC_FOEPREAVG5_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG6_SHIFT 18 /**< Shift value for MODEM_FOEPREAVG6 */ +#define _MODEM_INTAFC_FOEPREAVG6_MASK 0x1C0000UL /**< Bit mask for MODEM_FOEPREAVG6 */ +#define _MODEM_INTAFC_FOEPREAVG6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG6_DEFAULT (_MODEM_INTAFC_FOEPREAVG6_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_INTAFC */ +#define _MODEM_INTAFC_FOEPREAVG7_SHIFT 21 /**< Shift value for MODEM_FOEPREAVG7 */ +#define _MODEM_INTAFC_FOEPREAVG7_MASK 0xE00000UL /**< Bit mask for MODEM_FOEPREAVG7 */ +#define _MODEM_INTAFC_FOEPREAVG7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */ +#define MODEM_INTAFC_FOEPREAVG7_DEFAULT (_MODEM_INTAFC_FOEPREAVG7_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_INTAFC */ + +/* Bit fields for MODEM DSATHD0 */ +#define _MODEM_DSATHD0_RESETVALUE 0x07830464UL /**< Default value for MODEM_DSATHD0 */ +#define _MODEM_DSATHD0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSATHD0 */ +#define _MODEM_DSATHD0_SPIKETHD_SHIFT 0 /**< Shift value for MODEM_SPIKETHD */ +#define _MODEM_DSATHD0_SPIKETHD_MASK 0xFFUL /**< Bit mask for MODEM_SPIKETHD */ +#define _MODEM_DSATHD0_SPIKETHD_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD0 */ +#define MODEM_DSATHD0_SPIKETHD_DEFAULT (_MODEM_DSATHD0_SPIKETHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */ +#define _MODEM_DSATHD0_UNMODTHD_SHIFT 8 /**< Shift value for MODEM_UNMODTHD */ +#define _MODEM_DSATHD0_UNMODTHD_MASK 0x3F00UL /**< Bit mask for MODEM_UNMODTHD */ +#define _MODEM_DSATHD0_UNMODTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD0 */ +#define MODEM_DSATHD0_UNMODTHD_DEFAULT (_MODEM_DSATHD0_UNMODTHD_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */ +#define _MODEM_DSATHD0_FDEVMINTHD_SHIFT 14 /**< Shift value for MODEM_FDEVMINTHD */ +#define _MODEM_DSATHD0_FDEVMINTHD_MASK 0xFC000UL /**< Bit mask for MODEM_FDEVMINTHD */ +#define _MODEM_DSATHD0_FDEVMINTHD_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_DSATHD0 */ +#define MODEM_DSATHD0_FDEVMINTHD_DEFAULT (_MODEM_DSATHD0_FDEVMINTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */ +#define _MODEM_DSATHD0_FDEVMAXTHD_SHIFT 20 /**< Shift value for MODEM_FDEVMAXTHD */ +#define _MODEM_DSATHD0_FDEVMAXTHD_MASK 0xFFF00000UL /**< Bit mask for MODEM_FDEVMAXTHD */ +#define _MODEM_DSATHD0_FDEVMAXTHD_DEFAULT 0x00000078UL /**< Mode DEFAULT for MODEM_DSATHD0 */ +#define MODEM_DSATHD0_FDEVMAXTHD_DEFAULT (_MODEM_DSATHD0_FDEVMAXTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */ + +/* Bit fields for MODEM DSATHD1 */ +#define _MODEM_DSATHD1_RESETVALUE 0x3AC81388UL /**< Default value for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_MASK 0x7FFFFFFFUL /**< Mask for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWABSTHD_SHIFT 0 /**< Shift value for MODEM_POWABSTHD */ +#define _MODEM_DSATHD1_POWABSTHD_MASK 0xFFFFUL /**< Bit mask for MODEM_POWABSTHD */ +#define _MODEM_DSATHD1_POWABSTHD_DEFAULT 0x00001388UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWABSTHD_DEFAULT (_MODEM_DSATHD1_POWABSTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWRELTHD_SHIFT 16 /**< Shift value for MODEM_POWRELTHD */ +#define _MODEM_DSATHD1_POWRELTHD_MASK 0x30000UL /**< Bit mask for MODEM_POWRELTHD */ +#define _MODEM_DSATHD1_POWRELTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWRELTHD_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWRELTHD_MODE1 0x00000001UL /**< Mode MODE1 for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWRELTHD_MODE2 0x00000002UL /**< Mode MODE2 for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_POWRELTHD_MODE3 0x00000003UL /**< Mode MODE3 for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWRELTHD_DEFAULT (_MODEM_DSATHD1_POWRELTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWRELTHD_DISABLED (_MODEM_DSATHD1_POWRELTHD_DISABLED << 16) /**< Shifted mode DISABLED for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWRELTHD_MODE1 (_MODEM_DSATHD1_POWRELTHD_MODE1 << 16) /**< Shifted mode MODE1 for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWRELTHD_MODE2 (_MODEM_DSATHD1_POWRELTHD_MODE2 << 16) /**< Shifted mode MODE2 for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_POWRELTHD_MODE3 (_MODEM_DSATHD1_POWRELTHD_MODE3 << 16) /**< Shifted mode MODE3 for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_DSARSTCNT_SHIFT 18 /**< Shift value for MODEM_DSARSTCNT */ +#define _MODEM_DSATHD1_DSARSTCNT_MASK 0x1C0000UL /**< Bit mask for MODEM_DSARSTCNT */ +#define _MODEM_DSATHD1_DSARSTCNT_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_DSARSTCNT_DEFAULT (_MODEM_DSATHD1_DSARSTCNT_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_RSSIJMPTHD_SHIFT 21 /**< Shift value for MODEM_RSSIJMPTHD */ +#define _MODEM_DSATHD1_RSSIJMPTHD_MASK 0x1E00000UL /**< Bit mask for MODEM_RSSIJMPTHD */ +#define _MODEM_DSATHD1_RSSIJMPTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_RSSIJMPTHD_DEFAULT (_MODEM_DSATHD1_RSSIJMPTHD_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define _MODEM_DSATHD1_FREQLATDLY_SHIFT 25 /**< Shift value for MODEM_FREQLATDLY */ +#define _MODEM_DSATHD1_FREQLATDLY_MASK 0x6000000UL /**< Bit mask for MODEM_FREQLATDLY */ +#define _MODEM_DSATHD1_FREQLATDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_FREQLATDLY_DEFAULT (_MODEM_DSATHD1_FREQLATDLY_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_PWRFLTBYP (0x1UL << 27) /**< Power filter bypass */ +#define _MODEM_DSATHD1_PWRFLTBYP_SHIFT 27 /**< Shift value for MODEM_PWRFLTBYP */ +#define _MODEM_DSATHD1_PWRFLTBYP_MASK 0x8000000UL /**< Bit mask for MODEM_PWRFLTBYP */ +#define _MODEM_DSATHD1_PWRFLTBYP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_PWRFLTBYP_DEFAULT (_MODEM_DSATHD1_PWRFLTBYP_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_AMPFLTBYP (0x1UL << 28) /**< Amplitude filter bypass */ +#define _MODEM_DSATHD1_AMPFLTBYP_SHIFT 28 /**< Shift value for MODEM_AMPFLTBYP */ +#define _MODEM_DSATHD1_AMPFLTBYP_MASK 0x10000000UL /**< Bit mask for MODEM_AMPFLTBYP */ +#define _MODEM_DSATHD1_AMPFLTBYP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_AMPFLTBYP_DEFAULT (_MODEM_DSATHD1_AMPFLTBYP_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_PWRDETDIS (0x1UL << 29) /**< Power detection disabled */ +#define _MODEM_DSATHD1_PWRDETDIS_SHIFT 29 /**< Shift value for MODEM_PWRDETDIS */ +#define _MODEM_DSATHD1_PWRDETDIS_MASK 0x20000000UL /**< Bit mask for MODEM_PWRDETDIS */ +#define _MODEM_DSATHD1_PWRDETDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_PWRDETDIS_DEFAULT (_MODEM_DSATHD1_PWRDETDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_FREQSCALE (0x1UL << 30) /**< Frequency scale factor */ +#define _MODEM_DSATHD1_FREQSCALE_SHIFT 30 /**< Shift value for MODEM_FREQSCALE */ +#define _MODEM_DSATHD1_FREQSCALE_MASK 0x40000000UL /**< Bit mask for MODEM_FREQSCALE */ +#define _MODEM_DSATHD1_FREQSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD1 */ +#define MODEM_DSATHD1_FREQSCALE_DEFAULT (_MODEM_DSATHD1_FREQSCALE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */ + +/* Bit fields for MODEM DSATHD2 */ +#define _MODEM_DSATHD2_RESETVALUE 0x0C660664UL /**< Default value for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_MASK 0x7FFFFEFFUL /**< Mask for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_POWABSTHDLOG_SHIFT 0 /**< Shift value for MODEM_POWABSTHDLOG */ +#define _MODEM_DSATHD2_POWABSTHDLOG_MASK 0xFFUL /**< Bit mask for MODEM_POWABSTHDLOG */ +#define _MODEM_DSATHD2_POWABSTHDLOG_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_POWABSTHDLOG_DEFAULT (_MODEM_DSATHD2_POWABSTHDLOG_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_JUMPDETEN (0x1UL << 9) /**< Power jump detection enable */ +#define _MODEM_DSATHD2_JUMPDETEN_SHIFT 9 /**< Shift value for MODEM_JUMPDETEN */ +#define _MODEM_DSATHD2_JUMPDETEN_MASK 0x200UL /**< Bit mask for MODEM_JUMPDETEN */ +#define _MODEM_DSATHD2_JUMPDETEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_JUMPDETEN_DEFAULT (_MODEM_DSATHD2_JUMPDETEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_FDADJTHD_SHIFT 10 /**< Shift value for MODEM_FDADJTHD */ +#define _MODEM_DSATHD2_FDADJTHD_MASK 0xFC00UL /**< Bit mask for MODEM_FDADJTHD */ +#define _MODEM_DSATHD2_FDADJTHD_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_FDADJTHD_DEFAULT (_MODEM_DSATHD2_FDADJTHD_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_PMDETPASSTHD_SHIFT 16 /**< Shift value for MODEM_PMDETPASSTHD */ +#define _MODEM_DSATHD2_PMDETPASSTHD_MASK 0xF0000UL /**< Bit mask for MODEM_PMDETPASSTHD */ +#define _MODEM_DSATHD2_PMDETPASSTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_PMDETPASSTHD_DEFAULT (_MODEM_DSATHD2_PMDETPASSTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_FREQESTTHD_SHIFT 20 /**< Shift value for MODEM_FREQESTTHD */ +#define _MODEM_DSATHD2_FREQESTTHD_MASK 0x1F00000UL /**< Bit mask for MODEM_FREQESTTHD */ +#define _MODEM_DSATHD2_FREQESTTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_FREQESTTHD_DEFAULT (_MODEM_DSATHD2_FREQESTTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define _MODEM_DSATHD2_INTERFERDET_SHIFT 25 /**< Shift value for MODEM_INTERFERDET */ +#define _MODEM_DSATHD2_INTERFERDET_MASK 0x3E000000UL /**< Bit mask for MODEM_INTERFERDET */ +#define _MODEM_DSATHD2_INTERFERDET_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_INTERFERDET_DEFAULT (_MODEM_DSATHD2_INTERFERDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_PMDETFORCE (0x1UL << 30) /**< Force DSA preamble detector */ +#define _MODEM_DSATHD2_PMDETFORCE_SHIFT 30 /**< Shift value for MODEM_PMDETFORCE */ +#define _MODEM_DSATHD2_PMDETFORCE_MASK 0x40000000UL /**< Bit mask for MODEM_PMDETFORCE */ +#define _MODEM_DSATHD2_PMDETFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD2 */ +#define MODEM_DSATHD2_PMDETFORCE_DEFAULT (_MODEM_DSATHD2_PMDETFORCE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */ + +/* Bit fields for MODEM DSATHD3 */ +#define _MODEM_DSATHD3_RESETVALUE 0x07830464UL /**< Default value for MODEM_DSATHD3 */ +#define _MODEM_DSATHD3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSATHD3 */ +#define _MODEM_DSATHD3_SPIKETHDLO_SHIFT 0 /**< Shift value for MODEM_SPIKETHDLO */ +#define _MODEM_DSATHD3_SPIKETHDLO_MASK 0xFFUL /**< Bit mask for MODEM_SPIKETHDLO */ +#define _MODEM_DSATHD3_SPIKETHDLO_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD3 */ +#define MODEM_DSATHD3_SPIKETHDLO_DEFAULT (_MODEM_DSATHD3_SPIKETHDLO_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */ +#define _MODEM_DSATHD3_UNMODTHDLO_SHIFT 8 /**< Shift value for MODEM_UNMODTHDLO */ +#define _MODEM_DSATHD3_UNMODTHDLO_MASK 0x3F00UL /**< Bit mask for MODEM_UNMODTHDLO */ +#define _MODEM_DSATHD3_UNMODTHDLO_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD3 */ +#define MODEM_DSATHD3_UNMODTHDLO_DEFAULT (_MODEM_DSATHD3_UNMODTHDLO_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */ +#define _MODEM_DSATHD3_FDEVMINTHDLO_SHIFT 14 /**< Shift value for MODEM_FDEVMINTHDLO */ +#define _MODEM_DSATHD3_FDEVMINTHDLO_MASK 0xFC000UL /**< Bit mask for MODEM_FDEVMINTHDLO */ +#define _MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_DSATHD3 */ +#define MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT (_MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */ +#define _MODEM_DSATHD3_FDEVMAXTHDLO_SHIFT 20 /**< Shift value for MODEM_FDEVMAXTHDLO */ +#define _MODEM_DSATHD3_FDEVMAXTHDLO_MASK 0xFFF00000UL /**< Bit mask for MODEM_FDEVMAXTHDLO */ +#define _MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT 0x00000078UL /**< Mode DEFAULT for MODEM_DSATHD3 */ +#define MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT (_MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */ + +/* Bit fields for MODEM DSATHD4 */ +#define _MODEM_DSATHD4_RESETVALUE 0x00821388UL /**< Default value for MODEM_DSATHD4 */ +#define _MODEM_DSATHD4_MASK 0x07FFFFFFUL /**< Mask for MODEM_DSATHD4 */ +#define _MODEM_DSATHD4_POWABSTHDLO_SHIFT 0 /**< Shift value for MODEM_POWABSTHDLO */ +#define _MODEM_DSATHD4_POWABSTHDLO_MASK 0xFFFFUL /**< Bit mask for MODEM_POWABSTHDLO */ +#define _MODEM_DSATHD4_POWABSTHDLO_DEFAULT 0x00001388UL /**< Mode DEFAULT for MODEM_DSATHD4 */ +#define MODEM_DSATHD4_POWABSTHDLO_DEFAULT (_MODEM_DSATHD4_POWABSTHDLO_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */ +#define _MODEM_DSATHD4_ARRTOLERTHD0LO_SHIFT 16 /**< Shift value for MODEM_ARRTOLERTHD0LO */ +#define _MODEM_DSATHD4_ARRTOLERTHD0LO_MASK 0x1F0000UL /**< Bit mask for MODEM_ARRTOLERTHD0LO */ +#define _MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSATHD4 */ +#define MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT (_MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */ +#define _MODEM_DSATHD4_ARRTOLERTHD1LO_SHIFT 21 /**< Shift value for MODEM_ARRTOLERTHD1LO */ +#define _MODEM_DSATHD4_ARRTOLERTHD1LO_MASK 0x3E00000UL /**< Bit mask for MODEM_ARRTOLERTHD1LO */ +#define _MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD4 */ +#define MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT (_MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */ +#define MODEM_DSATHD4_SWTHD (0x1UL << 26) /**< Enable switch threshold for low power */ +#define _MODEM_DSATHD4_SWTHD_SHIFT 26 /**< Shift value for MODEM_SWTHD */ +#define _MODEM_DSATHD4_SWTHD_MASK 0x4000000UL /**< Bit mask for MODEM_SWTHD */ +#define _MODEM_DSATHD4_SWTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD4 */ +#define MODEM_DSATHD4_SWTHD_DEFAULT (_MODEM_DSATHD4_SWTHD_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */ + +/* Bit fields for MODEM DSACTRL */ +#define _MODEM_DSACTRL_RESETVALUE 0x000A2090UL /**< Default value for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_MASK 0xFFEFFFFFUL /**< Mask for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_DSAMODE_SHIFT 0 /**< Shift value for MODEM_DSAMODE */ +#define _MODEM_DSACTRL_DSAMODE_MASK 0x3UL /**< Bit mask for MODEM_DSAMODE */ +#define _MODEM_DSACTRL_DSAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_DSAMODE_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_DSAMODE_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_DSACTRL */ +#define MODEM_DSACTRL_DSAMODE_DEFAULT (_MODEM_DSACTRL_DSAMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_DSAMODE_DISABLED (_MODEM_DSACTRL_DSAMODE_DISABLED << 0) /**< Shifted mode DISABLED for MODEM_DSACTRL */ +#define MODEM_DSACTRL_DSAMODE_ENABLED (_MODEM_DSACTRL_DSAMODE_ENABLED << 0) /**< Shifted mode ENABLED for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_ARRTHD_SHIFT 2 /**< Shift value for MODEM_ARRTHD */ +#define _MODEM_DSACTRL_ARRTHD_MASK 0x3CUL /**< Bit mask for MODEM_ARRTHD */ +#define _MODEM_DSACTRL_ARRTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_ARRTHD_DEFAULT (_MODEM_DSACTRL_ARRTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_ARRTOLERTHD0_SHIFT 6 /**< Shift value for MODEM_ARRTOLERTHD0 */ +#define _MODEM_DSACTRL_ARRTOLERTHD0_MASK 0x7C0UL /**< Bit mask for MODEM_ARRTOLERTHD0 */ +#define _MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT (_MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_ARRTOLERTHD1_SHIFT 11 /**< Shift value for MODEM_ARRTOLERTHD1 */ +#define _MODEM_DSACTRL_ARRTOLERTHD1_MASK 0xF800UL /**< Bit mask for MODEM_ARRTOLERTHD1 */ +#define _MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT (_MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_SCHPRD (0x1UL << 16) /**< Search period window length */ +#define _MODEM_DSACTRL_SCHPRD_SHIFT 16 /**< Shift value for MODEM_SCHPRD */ +#define _MODEM_DSACTRL_SCHPRD_MASK 0x10000UL /**< Bit mask for MODEM_SCHPRD */ +#define _MODEM_DSACTRL_SCHPRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_SCHPRD_TS2 0x00000000UL /**< Mode TS2 for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_SCHPRD_TS4 0x00000001UL /**< Mode TS4 for MODEM_DSACTRL */ +#define MODEM_DSACTRL_SCHPRD_DEFAULT (_MODEM_DSACTRL_SCHPRD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_SCHPRD_TS2 (_MODEM_DSACTRL_SCHPRD_TS2 << 16) /**< Shifted mode TS2 for MODEM_DSACTRL */ +#define MODEM_DSACTRL_SCHPRD_TS4 (_MODEM_DSACTRL_SCHPRD_TS4 << 16) /**< Shifted mode TS4 for MODEM_DSACTRL */ +#define MODEM_DSACTRL_FREQAVGSYM (0x1UL << 17) /**< DSA frequency estimation averaging */ +#define _MODEM_DSACTRL_FREQAVGSYM_SHIFT 17 /**< Shift value for MODEM_FREQAVGSYM */ +#define _MODEM_DSACTRL_FREQAVGSYM_MASK 0x20000UL /**< Bit mask for MODEM_FREQAVGSYM */ +#define _MODEM_DSACTRL_FREQAVGSYM_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_FREQAVGSYM_AVG2TS 0x00000000UL /**< Mode AVG2TS for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_FREQAVGSYM_AVG4TS 0x00000001UL /**< Mode AVG4TS for MODEM_DSACTRL */ +#define MODEM_DSACTRL_FREQAVGSYM_DEFAULT (_MODEM_DSACTRL_FREQAVGSYM_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_FREQAVGSYM_AVG2TS (_MODEM_DSACTRL_FREQAVGSYM_AVG2TS << 17) /**< Shifted mode AVG2TS for MODEM_DSACTRL */ +#define MODEM_DSACTRL_FREQAVGSYM_AVG4TS (_MODEM_DSACTRL_FREQAVGSYM_AVG4TS << 17) /**< Shifted mode AVG4TS for MODEM_DSACTRL */ +#define MODEM_DSACTRL_TRANRSTDSA (0x1UL << 18) /**< power transient detector Reset DSA */ +#define _MODEM_DSACTRL_TRANRSTDSA_SHIFT 18 /**< Shift value for MODEM_TRANRSTDSA */ +#define _MODEM_DSACTRL_TRANRSTDSA_MASK 0x40000UL /**< Bit mask for MODEM_TRANRSTDSA */ +#define _MODEM_DSACTRL_TRANRSTDSA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_TRANRSTDSA_DEFAULT (_MODEM_DSACTRL_TRANRSTDSA_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_DSARSTON (0x1UL << 19) /**< DSA detection reset */ +#define _MODEM_DSACTRL_DSARSTON_SHIFT 19 /**< Shift value for MODEM_DSARSTON */ +#define _MODEM_DSACTRL_DSARSTON_MASK 0x80000UL /**< Bit mask for MODEM_DSARSTON */ +#define _MODEM_DSACTRL_DSARSTON_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_DSARSTON_DEFAULT (_MODEM_DSACTRL_DSARSTON_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_GAINREDUCDLY_SHIFT 21 /**< Shift value for MODEM_GAINREDUCDLY */ +#define _MODEM_DSACTRL_GAINREDUCDLY_MASK 0x600000UL /**< Bit mask for MODEM_GAINREDUCDLY */ +#define _MODEM_DSACTRL_GAINREDUCDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_GAINREDUCDLY_DEFAULT (_MODEM_DSACTRL_GAINREDUCDLY_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_LOWDUTY_SHIFT 23 /**< Shift value for MODEM_LOWDUTY */ +#define _MODEM_DSACTRL_LOWDUTY_MASK 0x3800000UL /**< Bit mask for MODEM_LOWDUTY */ +#define _MODEM_DSACTRL_LOWDUTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_LOWDUTY_DEFAULT (_MODEM_DSACTRL_LOWDUTY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_RESTORE (0x1UL << 26) /**< Power detector reset of DSA */ +#define _MODEM_DSACTRL_RESTORE_SHIFT 26 /**< Shift value for MODEM_RESTORE */ +#define _MODEM_DSACTRL_RESTORE_MASK 0x4000000UL /**< Bit mask for MODEM_RESTORE */ +#define _MODEM_DSACTRL_RESTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_RESTORE_DEFAULT (_MODEM_DSACTRL_RESTORE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_AGCBAUDEN (0x1UL << 27) /**< Consider Baud_en from AGC */ +#define _MODEM_DSACTRL_AGCBAUDEN_SHIFT 27 /**< Shift value for MODEM_AGCBAUDEN */ +#define _MODEM_DSACTRL_AGCBAUDEN_MASK 0x8000000UL /**< Bit mask for MODEM_AGCBAUDEN */ +#define _MODEM_DSACTRL_AGCBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_AGCBAUDEN_DEFAULT (_MODEM_DSACTRL_AGCBAUDEN_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ +#define _MODEM_DSACTRL_AMPJUPTHD_SHIFT 28 /**< Shift value for MODEM_AMPJUPTHD */ +#define _MODEM_DSACTRL_AMPJUPTHD_MASK 0xF0000000UL /**< Bit mask for MODEM_AMPJUPTHD */ +#define _MODEM_DSACTRL_AMPJUPTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */ +#define MODEM_DSACTRL_AMPJUPTHD_DEFAULT (_MODEM_DSACTRL_AMPJUPTHD_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_DSACTRL */ + +/* Bit fields for MODEM DIGMIXCTRL */ +#define _MODEM_DIGMIXCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_DIGMIXCTRL */ +#define _MODEM_DIGMIXCTRL_MASK 0x007FFFFFUL /**< Mask for MODEM_DIGMIXCTRL */ +#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_SHIFT 0 /**< Shift value for MODEM_DIGMIXFREQ */ +#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_MASK 0xFFFFFUL /**< Bit mask for MODEM_DIGMIXFREQ */ +#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXMODE (0x1UL << 20) /**< Digital mixer frequency control */ +#define _MODEM_DIGMIXCTRL_DIGMIXMODE_SHIFT 20 /**< Shift value for MODEM_DIGMIXMODE */ +#define _MODEM_DIGMIXCTRL_DIGMIXMODE_MASK 0x100000UL /**< Bit mask for MODEM_DIGMIXMODE */ +#define _MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */ +#define _MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR 0x00000000UL /**< Mode CFOSR for MODEM_DIGMIXCTRL */ +#define _MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ 0x00000001UL /**< Mode DIGMIXFREQ for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR (_MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR << 20) /**< Shifted mode CFOSR for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ (_MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ << 20) /**< Shifted mode DIGMIXFREQ for MODEM_DIGMIXCTRL*/ +#define MODEM_DIGMIXCTRL_MIXERCONJ (0x1UL << 21) /**< Digital mixer input conjugate */ +#define _MODEM_DIGMIXCTRL_MIXERCONJ_SHIFT 21 /**< Shift value for MODEM_MIXERCONJ */ +#define _MODEM_DIGMIXCTRL_MIXERCONJ_MASK 0x200000UL /**< Bit mask for MODEM_MIXERCONJ */ +#define _MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT (_MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXFB (0x1UL << 22) /**< Digital mixer Frequency Correction */ +#define _MODEM_DIGMIXCTRL_DIGMIXFB_SHIFT 22 /**< Shift value for MODEM_DIGMIXFB */ +#define _MODEM_DIGMIXCTRL_DIGMIXFB_MASK 0x400000UL /**< Bit mask for MODEM_DIGMIXFB */ +#define _MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */ +#define MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */ + +/* Bit fields for MODEM VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_RESETVALUE 0x00206100UL /**< Default value for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_MASK 0xFFFFFFFFUL /**< Mask for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_VTDEMODEN (0x1UL << 0) /**< Viterbi demodulator enable */ +#define _MODEM_VITERBIDEMOD_VTDEMODEN_SHIFT 0 /**< Shift value for MODEM_VTDEMODEN */ +#define _MODEM_VITERBIDEMOD_VTDEMODEN_MASK 0x1UL /**< Bit mask for MODEM_VTDEMODEN */ +#define _MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT (_MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_HARDDECISION (0x1UL << 1) /**< Hard decision */ +#define _MODEM_VITERBIDEMOD_HARDDECISION_SHIFT 1 /**< Shift value for MODEM_HARDDECISION */ +#define _MODEM_VITERBIDEMOD_HARDDECISION_MASK 0x2UL /**< Bit mask for MODEM_HARDDECISION */ +#define _MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT (_MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI1_SHIFT 2 /**< Shift value for MODEM_VITERBIKSI1 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI1_MASK 0x1FCUL /**< Bit mask for MODEM_VITERBIKSI1 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT 0x00000040UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI2_SHIFT 9 /**< Shift value for MODEM_VITERBIKSI2 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI2_MASK 0xFE00UL /**< Bit mask for MODEM_VITERBIKSI2 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT 0x00000030UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI3_SHIFT 16 /**< Shift value for MODEM_VITERBIKSI3 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI3_MASK 0x7F0000UL /**< Bit mask for MODEM_VITERBIKSI3 */ +#define _MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_SYNTHAFC (0x1UL << 23) /**< Synthesizer AFC in Viterbi demod */ +#define _MODEM_VITERBIDEMOD_SYNTHAFC_SHIFT 23 /**< Shift value for MODEM_SYNTHAFC */ +#define _MODEM_VITERBIDEMOD_SYNTHAFC_MASK 0x800000UL /**< Bit mask for MODEM_SYNTHAFC */ +#define _MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT (_MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_CORRCYCLE_SHIFT 24 /**< Shift value for MODEM_CORRCYCLE */ +#define _MODEM_VITERBIDEMOD_CORRCYCLE_MASK 0xF000000UL /**< Bit mask for MODEM_CORRCYCLE */ +#define _MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT (_MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ +#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_SHIFT 28 /**< Shift value for MODEM_CORRSTPSIZE */ +#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_MASK 0xF0000000UL /**< Bit mask for MODEM_CORRSTPSIZE */ +#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */ +#define MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT (_MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */ + +/* Bit fields for MODEM VTCORRCFG0 */ +#define _MODEM_VTCORRCFG0_RESETVALUE 0x123556B7UL /**< Default value for MODEM_VTCORRCFG0 */ +#define _MODEM_VTCORRCFG0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_VTCORRCFG0 */ +#define _MODEM_VTCORRCFG0_EXPECTPATT_SHIFT 0 /**< Shift value for MODEM_EXPECTPATT */ +#define _MODEM_VTCORRCFG0_EXPECTPATT_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_EXPECTPATT */ +#define _MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT 0x123556B7UL /**< Mode DEFAULT for MODEM_VTCORRCFG0 */ +#define MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT (_MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG0 */ + +/* Bit fields for MODEM VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_RESETVALUE 0x5020C000UL /**< Default value for MODEM_VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_MASK 0xF7FDFFFFUL /**< Mask for MODEM_VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_SHIFT 0 /**< Shift value for MODEM_VITERBIKSI3WB */ +#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_MASK 0x7FUL /**< Bit mask for MODEM_VITERBIKSI3WB */ +#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT (_MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_KSI3SWENABLE (0x1UL << 7) /**< WB KSI3 Switching Enable */ +#define _MODEM_VTCORRCFG1_KSI3SWENABLE_SHIFT 7 /**< Shift value for MODEM_KSI3SWENABLE */ +#define _MODEM_VTCORRCFG1_KSI3SWENABLE_MASK 0x80UL /**< Bit mask for MODEM_KSI3SWENABLE */ +#define _MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT (_MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_VTFRQLIM_SHIFT 8 /**< Shift value for MODEM_VTFRQLIM */ +#define _MODEM_VTCORRCFG1_VTFRQLIM_MASK 0x1FF00UL /**< Bit mask for MODEM_VTFRQLIM */ +#define _MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT 0x000000C0UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT (_MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_EXPSYNCLEN_SHIFT 18 /**< Shift value for MODEM_EXPSYNCLEN */ +#define _MODEM_VTCORRCFG1_EXPSYNCLEN_MASK 0x7FC0000UL /**< Bit mask for MODEM_EXPSYNCLEN */ +#define _MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT (_MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */ +#define _MODEM_VTCORRCFG1_EXPECTHT_SHIFT 28 /**< Shift value for MODEM_EXPECTHT */ +#define _MODEM_VTCORRCFG1_EXPECTHT_MASK 0xF0000000UL /**< Bit mask for MODEM_EXPECTHT */ +#define _MODEM_VTCORRCFG1_EXPECTHT_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */ +#define MODEM_VTCORRCFG1_EXPECTHT_DEFAULT (_MODEM_VTCORRCFG1_EXPECTHT_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */ + +/* Bit fields for MODEM VTTRACK */ +#define _MODEM_VTTRACK_RESETVALUE 0x0D803B88UL /**< Default value for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_MASK 0x3FFF3FFFUL /**< Mask for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQTRACKMODE_SHIFT 0 /**< Shift value for MODEM_FREQTRACKMODE */ +#define _MODEM_VTTRACK_FREQTRACKMODE_MASK 0x3UL /**< Bit mask for MODEM_FREQTRACKMODE */ +#define _MODEM_VTTRACK_FREQTRACKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQTRACKMODE_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQTRACKMODE_MODE1 0x00000001UL /**< Mode MODE1 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQTRACKMODE_MODE2 0x00000002UL /**< Mode MODE2 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQTRACKMODE_MODE3 0x00000003UL /**< Mode MODE3 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQTRACKMODE_DEFAULT (_MODEM_VTTRACK_FREQTRACKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQTRACKMODE_DISABLED (_MODEM_VTTRACK_FREQTRACKMODE_DISABLED << 0) /**< Shifted mode DISABLED for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQTRACKMODE_MODE1 (_MODEM_VTTRACK_FREQTRACKMODE_MODE1 << 0) /**< Shifted mode MODE1 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQTRACKMODE_MODE2 (_MODEM_VTTRACK_FREQTRACKMODE_MODE2 << 0) /**< Shifted mode MODE2 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQTRACKMODE_MODE3 (_MODEM_VTTRACK_FREQTRACKMODE_MODE3 << 0) /**< Shifted mode MODE3 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMTRACKTHD_SHIFT 2 /**< Shift value for MODEM_TIMTRACKTHD */ +#define _MODEM_VTTRACK_TIMTRACKTHD_MASK 0x3CUL /**< Bit mask for MODEM_TIMTRACKTHD */ +#define _MODEM_VTTRACK_TIMTRACKTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMTRACKTHD_DEFAULT (_MODEM_VTTRACK_TIMTRACKTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMEACQUTHD_SHIFT 6 /**< Shift value for MODEM_TIMEACQUTHD */ +#define _MODEM_VTTRACK_TIMEACQUTHD_MASK 0x3FC0UL /**< Bit mask for MODEM_TIMEACQUTHD */ +#define _MODEM_VTTRACK_TIMEACQUTHD_DEFAULT 0x000000EEUL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMEACQUTHD_DEFAULT (_MODEM_VTTRACK_TIMEACQUTHD_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMGEAR_SHIFT 16 /**< Shift value for MODEM_TIMGEAR */ +#define _MODEM_VTTRACK_TIMGEAR_MASK 0x30000UL /**< Bit mask for MODEM_TIMGEAR */ +#define _MODEM_VTTRACK_TIMGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMGEAR_GEAR0 0x00000000UL /**< Mode GEAR0 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMGEAR_GEAR1 0x00000001UL /**< Mode GEAR1 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_TIMGEAR_GEAR2 0x00000002UL /**< Mode GEAR2 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMGEAR_DEFAULT (_MODEM_VTTRACK_TIMGEAR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMGEAR_GEAR0 (_MODEM_VTTRACK_TIMGEAR_GEAR0 << 16) /**< Shifted mode GEAR0 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMGEAR_GEAR1 (_MODEM_VTTRACK_TIMGEAR_GEAR1 << 16) /**< Shifted mode GEAR1 for MODEM_VTTRACK */ +#define MODEM_VTTRACK_TIMGEAR_GEAR2 (_MODEM_VTTRACK_TIMGEAR_GEAR2 << 16) /**< Shifted mode GEAR2 for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_FREQBIAS_SHIFT 18 /**< Shift value for MODEM_FREQBIAS */ +#define _MODEM_VTTRACK_FREQBIAS_MASK 0x3C0000UL /**< Bit mask for MODEM_FREQBIAS */ +#define _MODEM_VTTRACK_FREQBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_FREQBIAS_DEFAULT (_MODEM_VTTRACK_FREQBIAS_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ +#define _MODEM_VTTRACK_HIPWRTHD_SHIFT 22 /**< Shift value for MODEM_HIPWRTHD */ +#define _MODEM_VTTRACK_HIPWRTHD_MASK 0x3FC00000UL /**< Bit mask for MODEM_HIPWRTHD */ +#define _MODEM_VTTRACK_HIPWRTHD_DEFAULT 0x00000036UL /**< Mode DEFAULT for MODEM_VTTRACK */ +#define MODEM_VTTRACK_HIPWRTHD_DEFAULT (_MODEM_VTTRACK_HIPWRTHD_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_VTTRACK */ + +/* Bit fields for MODEM VTBLETIMING */ +#define _MODEM_VTBLETIMING_RESETVALUE 0x00000000UL /**< Default value for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_MASK 0x8000FFF7UL /**< Mask for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_SHIFT 0 /**< Shift value for MODEM_VTBLETIMINGSEL */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_MASK 0x3UL /**< Bit mask for MODEM_VTBLETIMINGSEL */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY 0x00000000UL /**< Mode FRAMEDET_DELAY for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE 0x00000001UL /**< Mode END_FRAME_PULSE for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME 0x00000002UL /**< Mode END_FRAME for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME 0x00000003UL /**< Mode INV_END_FRAME for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT (_MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY (_MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY << 0) /**< Shifted mode FRAMEDET_DELAY for MODEM_VTBLETIMING*/ +#define MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE (_MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE << 0) /**< Shifted mode END_FRAME_PULSE for MODEM_VTBLETIMING*/ +#define MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME (_MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME << 0) /**< Shifted mode END_FRAME for MODEM_VTBLETIMING*/ +#define MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME (_MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME << 0) /**< Shifted mode INV_END_FRAME for MODEM_VTBLETIMING*/ +#define MODEM_VTBLETIMING_VTBLETIMINGCLKSEL (0x1UL << 2) /**< Viterbi BLE timing stamp clock select */ +#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_SHIFT 2 /**< Shift value for MODEM_VTBLETIMINGCLKSEL */ +#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_MASK 0x4UL /**< Bit mask for MODEM_VTBLETIMINGCLKSEL */ +#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT (_MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_TIMINGDELAY_SHIFT 4 /**< Shift value for MODEM_TIMINGDELAY */ +#define _MODEM_VTBLETIMING_TIMINGDELAY_MASK 0xFF0UL /**< Bit mask for MODEM_TIMINGDELAY */ +#define _MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT (_MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */ +#define _MODEM_VTBLETIMING_FLENOFF_SHIFT 12 /**< Shift value for MODEM_FLENOFF */ +#define _MODEM_VTBLETIMING_FLENOFF_MASK 0xF000UL /**< Bit mask for MODEM_FLENOFF */ +#define _MODEM_VTBLETIMING_FLENOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_FLENOFF_DEFAULT (_MODEM_VTBLETIMING_FLENOFF_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_DISDEMODOF (0x1UL << 31) /**< Disable VT Demod Over Flow Detection */ +#define _MODEM_VTBLETIMING_DISDEMODOF_SHIFT 31 /**< Shift value for MODEM_DISDEMODOF */ +#define _MODEM_VTBLETIMING_DISDEMODOF_MASK 0x80000000UL /**< Bit mask for MODEM_DISDEMODOF */ +#define _MODEM_VTBLETIMING_DISDEMODOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */ +#define MODEM_VTBLETIMING_DISDEMODOF_DEFAULT (_MODEM_VTBLETIMING_DISDEMODOF_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */ + +/* Bit fields for MODEM BREST */ +#define _MODEM_BREST_RESETVALUE 0x00000000UL /**< Default value for MODEM_BREST */ +#define _MODEM_BREST_MASK 0x000007FFUL /**< Mask for MODEM_BREST */ +#define _MODEM_BREST_BRESTINT_SHIFT 0 /**< Shift value for MODEM_BRESTINT */ +#define _MODEM_BREST_BRESTINT_MASK 0x3FUL /**< Bit mask for MODEM_BRESTINT */ +#define _MODEM_BREST_BRESTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_BREST */ +#define MODEM_BREST_BRESTINT_DEFAULT (_MODEM_BREST_BRESTINT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_BREST */ +#define _MODEM_BREST_BRESTNUM_SHIFT 6 /**< Shift value for MODEM_BRESTNUM */ +#define _MODEM_BREST_BRESTNUM_MASK 0x7C0UL /**< Bit mask for MODEM_BRESTNUM */ +#define _MODEM_BREST_BRESTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_BREST */ +#define MODEM_BREST_BRESTNUM_DEFAULT (_MODEM_BREST_BRESTNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_BREST */ + +/* Bit fields for MODEM AUTOCG */ +#define _MODEM_AUTOCG_RESETVALUE 0x00000000UL /**< Default value for MODEM_AUTOCG */ +#define _MODEM_AUTOCG_MASK 0x0000FFFFUL /**< Mask for MODEM_AUTOCG */ +#define _MODEM_AUTOCG_AUTOCGEN_SHIFT 0 /**< Shift value for MODEM_AUTOCGEN */ +#define _MODEM_AUTOCG_AUTOCGEN_MASK 0xFFFFUL /**< Bit mask for MODEM_AUTOCGEN */ +#define _MODEM_AUTOCG_AUTOCGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AUTOCG */ +#define MODEM_AUTOCG_AUTOCGEN_DEFAULT (_MODEM_AUTOCG_AUTOCGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AUTOCG */ + +/* Bit fields for MODEM CGCLKSTOP */ +#define _MODEM_CGCLKSTOP_RESETVALUE 0x00000000UL /**< Default value for MODEM_CGCLKSTOP */ +#define _MODEM_CGCLKSTOP_MASK 0x0000FFFFUL /**< Mask for MODEM_CGCLKSTOP */ +#define _MODEM_CGCLKSTOP_FORCEOFF_SHIFT 0 /**< Shift value for MODEM_FORCEOFF */ +#define _MODEM_CGCLKSTOP_FORCEOFF_MASK 0xFFFFUL /**< Bit mask for MODEM_FORCEOFF */ +#define _MODEM_CGCLKSTOP_FORCEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CGCLKSTOP */ +#define MODEM_CGCLKSTOP_FORCEOFF_DEFAULT (_MODEM_CGCLKSTOP_FORCEOFF_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CGCLKSTOP */ + +/* Bit fields for MODEM POE */ +#define _MODEM_POE_RESETVALUE 0x00000000UL /**< Default value for MODEM_POE */ +#define _MODEM_POE_MASK 0x03FF03FFUL /**< Mask for MODEM_POE */ +#define _MODEM_POE_POEI_SHIFT 0 /**< Shift value for MODEM_POEI */ +#define _MODEM_POE_POEI_MASK 0x3FFUL /**< Bit mask for MODEM_POEI */ +#define _MODEM_POE_POEI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_POE */ +#define MODEM_POE_POEI_DEFAULT (_MODEM_POE_POEI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_POE */ +#define _MODEM_POE_POEQ_SHIFT 16 /**< Shift value for MODEM_POEQ */ +#define _MODEM_POE_POEQ_MASK 0x3FF0000UL /**< Bit mask for MODEM_POEQ */ +#define _MODEM_POE_POEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_POE */ +#define MODEM_POE_POEQ_DEFAULT (_MODEM_POE_POEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_POE */ + +/* Bit fields for MODEM DIRECTMODE */ +#define _MODEM_DIRECTMODE_RESETVALUE 0x0000010CUL /**< Default value for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_MASK 0x00001F0FUL /**< Mask for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_DMENABLE (0x1UL << 0) /**< Enable Direct Mode */ +#define _MODEM_DIRECTMODE_DMENABLE_SHIFT 0 /**< Shift value for MODEM_DMENABLE */ +#define _MODEM_DIRECTMODE_DMENABLE_MASK 0x1UL /**< Bit mask for MODEM_DMENABLE */ +#define _MODEM_DIRECTMODE_DMENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_DMENABLE_DEFAULT (_MODEM_DIRECTMODE_DMENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCASYNC (0x1UL << 1) /**< Choose Synchronous or Asynchronous mode */ +#define _MODEM_DIRECTMODE_SYNCASYNC_SHIFT 1 /**< Shift value for MODEM_SYNCASYNC */ +#define _MODEM_DIRECTMODE_SYNCASYNC_MASK 0x2UL /**< Bit mask for MODEM_SYNCASYNC */ +#define _MODEM_DIRECTMODE_SYNCASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCASYNC_DEFAULT (_MODEM_DIRECTMODE_SYNCASYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_SYNCPREAM_SHIFT 2 /**< Shift value for MODEM_SYNCPREAM */ +#define _MODEM_DIRECTMODE_SYNCPREAM_MASK 0xCUL /**< Bit mask for MODEM_SYNCPREAM */ +#define _MODEM_DIRECTMODE_SYNCPREAM_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_SYNCPREAM_ADD0 0x00000000UL /**< Mode ADD0 for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_SYNCPREAM_ADD8 0x00000001UL /**< Mode ADD8 for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_SYNCPREAM_ADD16 0x00000002UL /**< Mode ADD16 for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_SYNCPREAM_ADD32 0x00000003UL /**< Mode ADD32 for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCPREAM_DEFAULT (_MODEM_DIRECTMODE_SYNCPREAM_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCPREAM_ADD0 (_MODEM_DIRECTMODE_SYNCPREAM_ADD0 << 2) /**< Shifted mode ADD0 for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCPREAM_ADD8 (_MODEM_DIRECTMODE_SYNCPREAM_ADD8 << 2) /**< Shifted mode ADD8 for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCPREAM_ADD16 (_MODEM_DIRECTMODE_SYNCPREAM_ADD16 << 2) /**< Shifted mode ADD16 for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_SYNCPREAM_ADD32 (_MODEM_DIRECTMODE_SYNCPREAM_ADD32 << 2) /**< Shifted mode ADD32 for MODEM_DIRECTMODE */ +#define _MODEM_DIRECTMODE_CLKWIDTH_SHIFT 8 /**< Shift value for MODEM_CLKWIDTH */ +#define _MODEM_DIRECTMODE_CLKWIDTH_MASK 0x1F00UL /**< Bit mask for MODEM_CLKWIDTH */ +#define _MODEM_DIRECTMODE_CLKWIDTH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DIRECTMODE */ +#define MODEM_DIRECTMODE_CLKWIDTH_DEFAULT (_MODEM_DIRECTMODE_CLKWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */ + +/* Bit fields for MODEM LONGRANGE */ +#define _MODEM_LONGRANGE_RESETVALUE 0x00FA53E8UL /**< Default value for MODEM_LONGRANGE */ +#define _MODEM_LONGRANGE_MASK 0x7FFFFFFFUL /**< Mask for MODEM_LONGRANGE */ +#define _MODEM_LONGRANGE_LRCORRTHD_SHIFT 0 /**< Shift value for MODEM_LRCORRTHD */ +#define _MODEM_LONGRANGE_LRCORRTHD_MASK 0x7FFUL /**< Bit mask for MODEM_LRCORRTHD */ +#define _MODEM_LONGRANGE_LRCORRTHD_DEFAULT 0x000003E8UL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRCORRTHD_DEFAULT (_MODEM_LONGRANGE_LRCORRTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ +#define _MODEM_LONGRANGE_LRCORRSCHWIN_SHIFT 11 /**< Shift value for MODEM_LRCORRSCHWIN */ +#define _MODEM_LONGRANGE_LRCORRSCHWIN_MASK 0x7800UL /**< Bit mask for MODEM_LRCORRSCHWIN */ +#define _MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT 0x0000000AUL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT (_MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRBLE (0x1UL << 15) /**< Enable */ +#define _MODEM_LONGRANGE_LRBLE_SHIFT 15 /**< Shift value for MODEM_LRBLE */ +#define _MODEM_LONGRANGE_LRBLE_MASK 0x8000UL /**< Bit mask for MODEM_LRBLE */ +#define _MODEM_LONGRANGE_LRBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRBLE_DEFAULT (_MODEM_LONGRANGE_LRBLE_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ +#define _MODEM_LONGRANGE_LRTIMCORRTHD_SHIFT 16 /**< Shift value for MODEM_LRTIMCORRTHD */ +#define _MODEM_LONGRANGE_LRTIMCORRTHD_MASK 0x7FF0000UL /**< Bit mask for MODEM_LRTIMCORRTHD */ +#define _MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT 0x000000FAUL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT (_MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRBLEDSA (0x1UL << 27) /**< DSA enable */ +#define _MODEM_LONGRANGE_LRBLEDSA_SHIFT 27 /**< Shift value for MODEM_LRBLEDSA */ +#define _MODEM_LONGRANGE_LRBLEDSA_MASK 0x8000000UL /**< Bit mask for MODEM_LRBLEDSA */ +#define _MODEM_LONGRANGE_LRBLEDSA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRBLEDSA_DEFAULT (_MODEM_LONGRANGE_LRBLEDSA_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ +#define _MODEM_LONGRANGE_LRDEC_SHIFT 28 /**< Shift value for MODEM_LRDEC */ +#define _MODEM_LONGRANGE_LRDEC_MASK 0x70000000UL /**< Bit mask for MODEM_LRDEC */ +#define _MODEM_LONGRANGE_LRDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */ +#define MODEM_LONGRANGE_LRDEC_DEFAULT (_MODEM_LONGRANGE_LRDEC_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */ + +/* Bit fields for MODEM LONGRANGE1 */ +#define _MODEM_LONGRANGE1_RESETVALUE 0x40000000UL /**< Default value for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_MASK 0xFFFF7FFFUL /**< Mask for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_LRSS_SHIFT 0 /**< Shift value for MODEM_LRSS */ +#define _MODEM_LONGRANGE1_LRSS_MASK 0xFUL /**< Bit mask for MODEM_LRSS */ +#define _MODEM_LONGRANGE1_LRSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LRSS_DEFAULT (_MODEM_LONGRANGE1_LRSS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_SHIFT 4 /**< Shift value for MODEM_LRTIMEOUTTHD */ +#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_MASK 0x7FF0UL /**< Bit mask for MODEM_LRTIMEOUTTHD */ +#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT (_MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_SHIFT 16 /**< Shift value for MODEM_CHPWRACCUDEL */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_MASK 0x30000UL /**< Bit mask for MODEM_CHPWRACCUDEL */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 0x00000000UL /**< Mode DEL0 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 0x00000001UL /**< Mode DEL32 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 0x00000002UL /**< Mode DEL64 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 << 16) /**< Shifted mode DEL0 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 << 16) /**< Shifted mode DEL32 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 << 16) /**< Shifted mode DEL64 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_HYSVAL_SHIFT 18 /**< Shift value for MODEM_HYSVAL */ +#define _MODEM_LONGRANGE1_HYSVAL_MASK 0x1C0000UL /**< Bit mask for MODEM_HYSVAL */ +#define _MODEM_LONGRANGE1_HYSVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_HYSVAL_DEFAULT (_MODEM_LONGRANGE1_HYSVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_AVGWIN_SHIFT 21 /**< Shift value for MODEM_AVGWIN */ +#define _MODEM_LONGRANGE1_AVGWIN_MASK 0xE00000UL /**< Bit mask for MODEM_AVGWIN */ +#define _MODEM_LONGRANGE1_AVGWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_AVGWIN_DEFAULT (_MODEM_LONGRANGE1_AVGWIN_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_LRSPIKETHADD_SHIFT 24 /**< Shift value for MODEM_LRSPIKETHADD */ +#define _MODEM_LONGRANGE1_LRSPIKETHADD_MASK 0xF000000UL /**< Bit mask for MODEM_LRSPIKETHADD */ +#define _MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT (_MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LOGICBASEDPUGATE (0x1UL << 28) /**< Logic Based Phase Unwrap Gating */ +#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_SHIFT 28 /**< Shift value for MODEM_LOGICBASEDPUGATE */ +#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_MASK 0x10000000UL /**< Bit mask for MODEM_LOGICBASEDPUGATE */ +#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT (_MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE (0x1UL << 29) /**< Logic Based Long Range Demod Gating */ +#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_SHIFT 29 /**< Shift value for MODEM_LOGICBASEDLRDEMODGATE */ +#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_MASK 0x20000000UL /**< Bit mask for MODEM_LOGICBASEDLRDEMODGATE */ +#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT (_MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_PREFILTLEN_SHIFT 30 /**< Shift value for MODEM_PREFILTLEN */ +#define _MODEM_LONGRANGE1_PREFILTLEN_MASK 0xC0000000UL /**< Bit mask for MODEM_PREFILTLEN */ +#define _MODEM_LONGRANGE1_PREFILTLEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_PREFILTLEN_LEN32 0x00000000UL /**< Mode LEN32 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_PREFILTLEN_LEN64 0x00000001UL /**< Mode LEN64 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_PREFILTLEN_LEN96 0x00000002UL /**< Mode LEN96 for MODEM_LONGRANGE1 */ +#define _MODEM_LONGRANGE1_PREFILTLEN_LEN128 0x00000003UL /**< Mode LEN128 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_PREFILTLEN_DEFAULT (_MODEM_LONGRANGE1_PREFILTLEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_PREFILTLEN_LEN32 (_MODEM_LONGRANGE1_PREFILTLEN_LEN32 << 30) /**< Shifted mode LEN32 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_PREFILTLEN_LEN64 (_MODEM_LONGRANGE1_PREFILTLEN_LEN64 << 30) /**< Shifted mode LEN64 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_PREFILTLEN_LEN96 (_MODEM_LONGRANGE1_PREFILTLEN_LEN96 << 30) /**< Shifted mode LEN96 for MODEM_LONGRANGE1 */ +#define MODEM_LONGRANGE1_PREFILTLEN_LEN128 (_MODEM_LONGRANGE1_PREFILTLEN_LEN128 << 30) /**< Shifted mode LEN128 for MODEM_LONGRANGE1 */ + +/* Bit fields for MODEM LONGRANGE2 */ +#define _MODEM_LONGRANGE2_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE2 */ +#define _MODEM_LONGRANGE2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH1_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH1 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH1_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH1 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */ +#define MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH2_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH2_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */ +#define MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH3_SHIFT 16 /**< Shift value for MODEM_LRCHPWRTH3 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH3_MASK 0xFF0000UL /**< Bit mask for MODEM_LRCHPWRTH3 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */ +#define MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH4_SHIFT 24 /**< Shift value for MODEM_LRCHPWRTH4 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH4_MASK 0xFF000000UL /**< Bit mask for MODEM_LRCHPWRTH4 */ +#define _MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */ +#define MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */ + +/* Bit fields for MODEM LONGRANGE3 */ +#define _MODEM_LONGRANGE3_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE3 */ +#define _MODEM_LONGRANGE3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE3 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH5_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH5 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH5_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH5 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */ +#define MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH6_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH6 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH6_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH6 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */ +#define MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH7_SHIFT 16 /**< Shift value for MODEM_LRCHPWRTH7 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH7_MASK 0xFF0000UL /**< Bit mask for MODEM_LRCHPWRTH7 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */ +#define MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH8_SHIFT 24 /**< Shift value for MODEM_LRCHPWRTH8 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH8_MASK 0xFF000000UL /**< Bit mask for MODEM_LRCHPWRTH8 */ +#define _MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */ +#define MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */ + +/* Bit fields for MODEM LONGRANGE4 */ +#define _MODEM_LONGRANGE4_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH9_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH9 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH9_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH9 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH10_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH10 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH10_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH10 */ +#define _MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH1_SHIFT 16 /**< Shift value for MODEM_LRCHPWRSH1 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH1_MASK 0xF0000UL /**< Bit mask for MODEM_LRCHPWRSH1 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH2_SHIFT 20 /**< Shift value for MODEM_LRCHPWRSH2 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH2_MASK 0xF00000UL /**< Bit mask for MODEM_LRCHPWRSH2 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH3_SHIFT 24 /**< Shift value for MODEM_LRCHPWRSH3 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH3_MASK 0xF000000UL /**< Bit mask for MODEM_LRCHPWRSH3 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH4_SHIFT 28 /**< Shift value for MODEM_LRCHPWRSH4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH4_MASK 0xF0000000UL /**< Bit mask for MODEM_LRCHPWRSH4 */ +#define _MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */ +#define MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */ + +/* Bit fields for MODEM LONGRANGE5 */ +#define _MODEM_LONGRANGE5_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_MASK 0x0FFFFFFFUL /**< Mask for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH5_SHIFT 0 /**< Shift value for MODEM_LRCHPWRSH5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH5_MASK 0xFUL /**< Bit mask for MODEM_LRCHPWRSH5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH6_SHIFT 4 /**< Shift value for MODEM_LRCHPWRSH6 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH6_MASK 0xF0UL /**< Bit mask for MODEM_LRCHPWRSH6 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH7_SHIFT 8 /**< Shift value for MODEM_LRCHPWRSH7 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH7_MASK 0xF00UL /**< Bit mask for MODEM_LRCHPWRSH7 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH8_SHIFT 12 /**< Shift value for MODEM_LRCHPWRSH8 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH8_MASK 0xF000UL /**< Bit mask for MODEM_LRCHPWRSH8 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH9_SHIFT 16 /**< Shift value for MODEM_LRCHPWRSH9 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH9_MASK 0xF0000UL /**< Bit mask for MODEM_LRCHPWRSH9 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH10_SHIFT 20 /**< Shift value for MODEM_LRCHPWRSH10 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH10_MASK 0xF00000UL /**< Bit mask for MODEM_LRCHPWRSH10 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH11_SHIFT 24 /**< Shift value for MODEM_LRCHPWRSH11 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH11_MASK 0xF000000UL /**< Bit mask for MODEM_LRCHPWRSH11 */ +#define _MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */ +#define MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */ + +/* Bit fields for MODEM LONGRANGE6 */ +#define _MODEM_LONGRANGE6_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE6 */ +#define _MODEM_LONGRANGE6_MASK 0xFFF7FFFFUL /**< Mask for MODEM_LONGRANGE6 */ +#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_SHIFT 0 /**< Shift value for MODEM_LRCHPWRSPIKETH */ +#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRSPIKETH */ +#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */ +#define MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */ +#define _MODEM_LONGRANGE6_LRSPIKETHD_SHIFT 8 /**< Shift value for MODEM_LRSPIKETHD */ +#define _MODEM_LONGRANGE6_LRSPIKETHD_MASK 0x7FF00UL /**< Bit mask for MODEM_LRSPIKETHD */ +#define _MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */ +#define MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT (_MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */ +#define _MODEM_LONGRANGE6_LRCHPWRTH11_SHIFT 20 /**< Shift value for MODEM_LRCHPWRTH11 */ +#define _MODEM_LONGRANGE6_LRCHPWRTH11_MASK 0xFF00000UL /**< Bit mask for MODEM_LRCHPWRTH11 */ +#define _MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */ +#define MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */ +#define _MODEM_LONGRANGE6_LRCHPWRSH12_SHIFT 28 /**< Shift value for MODEM_LRCHPWRSH12 */ +#define _MODEM_LONGRANGE6_LRCHPWRSH12_MASK 0xF0000000UL /**< Bit mask for MODEM_LRCHPWRSH12 */ +#define _MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */ +#define MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */ + +/* Bit fields for MODEM LRFRC */ +#define _MODEM_LRFRC_RESETVALUE 0x00000101UL /**< Default value for MODEM_LRFRC */ +#define _MODEM_LRFRC_MASK 0x000001FFUL /**< Mask for MODEM_LRFRC */ +#define _MODEM_LRFRC_CI500_SHIFT 0 /**< Shift value for MODEM_CI500 */ +#define _MODEM_LRFRC_CI500_MASK 0x3UL /**< Bit mask for MODEM_CI500 */ +#define _MODEM_LRFRC_CI500_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LRFRC */ +#define MODEM_LRFRC_CI500_DEFAULT (_MODEM_LRFRC_CI500_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LRFRC */ +#define _MODEM_LRFRC_FRCACKTIMETHD_SHIFT 2 /**< Shift value for MODEM_FRCACKTIMETHD */ +#define _MODEM_LRFRC_FRCACKTIMETHD_MASK 0xFCUL /**< Bit mask for MODEM_FRCACKTIMETHD */ +#define _MODEM_LRFRC_FRCACKTIMETHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LRFRC */ +#define MODEM_LRFRC_FRCACKTIMETHD_DEFAULT (_MODEM_LRFRC_FRCACKTIMETHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_LRFRC */ +#define MODEM_LRFRC_LRCORRMODE (0x1UL << 8) /**< LR Correlator operation Mode */ +#define _MODEM_LRFRC_LRCORRMODE_SHIFT 8 /**< Shift value for MODEM_LRCORRMODE */ +#define _MODEM_LRFRC_LRCORRMODE_MASK 0x100UL /**< Bit mask for MODEM_LRCORRMODE */ +#define _MODEM_LRFRC_LRCORRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LRFRC */ +#define MODEM_LRFRC_LRCORRMODE_DEFAULT (_MODEM_LRFRC_LRCORRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LRFRC */ + +/* Bit fields for MODEM COH0 */ +#define _MODEM_COH0_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH0 */ +#define _MODEM_COH0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICBBSSEN (0x1UL << 0) /**< Dynamic BBSS enable bit */ +#define _MODEM_COH0_COHDYNAMICBBSSEN_SHIFT 0 /**< Shift value for MODEM_COHDYNAMICBBSSEN */ +#define _MODEM_COH0_COHDYNAMICBBSSEN_MASK 0x1UL /**< Bit mask for MODEM_COHDYNAMICBBSSEN */ +#define _MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT (_MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICSYNCTHRESH (0x1UL << 1) /**< Dynamic syncword threshold enable bit */ +#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_SHIFT 1 /**< Shift value for MODEM_COHDYNAMICSYNCTHRESH */ +#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_MASK 0x2UL /**< Bit mask for MODEM_COHDYNAMICSYNCTHRESH */ +#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT (_MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESH (0x1UL << 2) /**< Dynamic preamble threshold enable bit */ +#define _MODEM_COH0_COHDYNAMICPRETHRESH_SHIFT 2 /**< Shift value for MODEM_COHDYNAMICPRETHRESH */ +#define _MODEM_COH0_COHDYNAMICPRETHRESH_MASK 0x4UL /**< Bit mask for MODEM_COHDYNAMICPRETHRESH */ +#define _MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT (_MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRLOCK (0x1UL << 3) /**< Channel power lock */ +#define _MODEM_COH0_COHCHPWRLOCK_SHIFT 3 /**< Shift value for MODEM_COHCHPWRLOCK */ +#define _MODEM_COH0_COHCHPWRLOCK_MASK 0x8UL /**< Bit mask for MODEM_COHCHPWRLOCK */ +#define _MODEM_COH0_COHCHPWRLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define _MODEM_COH0_COHCHPWRLOCK_TIMDET 0x00000000UL /**< Mode TIMDET for MODEM_COH0 */ +#define _MODEM_COH0_COHCHPWRLOCK_DSADET 0x00000001UL /**< Mode DSADET for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRLOCK_DEFAULT (_MODEM_COH0_COHCHPWRLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRLOCK_TIMDET (_MODEM_COH0_COHCHPWRLOCK_TIMDET << 3) /**< Shifted mode TIMDET for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRLOCK_DSADET (_MODEM_COH0_COHCHPWRLOCK_DSADET << 3) /**< Shifted mode DSADET for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRRESTART (0x1UL << 4) /**< Channel power restart */ +#define _MODEM_COH0_COHCHPWRRESTART_SHIFT 4 /**< Shift value for MODEM_COHCHPWRRESTART */ +#define _MODEM_COH0_COHCHPWRRESTART_MASK 0x10UL /**< Bit mask for MODEM_COHCHPWRRESTART */ +#define _MODEM_COH0_COHCHPWRRESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRRESTART_DEFAULT (_MODEM_COH0_COHCHPWRRESTART_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SHIFT 5 /**< Shift value for MODEM_COHDYNAMICPRETHRESHSEL*/ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_MASK 0xE0UL /**< Bit mask for MODEM_COHDYNAMICPRETHRESHSEL */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 0x00000000UL /**< Mode SEL0 for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 0x00000001UL /**< Mode SEL1 for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 0x00000002UL /**< Mode SEL2 for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 0x00000003UL /**< Mode SEL3 for MODEM_COH0 */ +#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 0x00000004UL /**< Mode SEL4 for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 << 5) /**< Shifted mode SEL0 for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 << 5) /**< Shifted mode SEL1 for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 << 5) /**< Shifted mode SEL2 for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 << 5) /**< Shifted mode SEL3 for MODEM_COH0 */ +#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 << 5) /**< Shifted mode SEL4 for MODEM_COH0 */ +#define _MODEM_COH0_COHCHPWRTH0_SHIFT 8 /**< Shift value for MODEM_COHCHPWRTH0 */ +#define _MODEM_COH0_COHCHPWRTH0_MASK 0xFF00UL /**< Bit mask for MODEM_COHCHPWRTH0 */ +#define _MODEM_COH0_COHCHPWRTH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRTH0_DEFAULT (_MODEM_COH0_COHCHPWRTH0_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define _MODEM_COH0_COHCHPWRTH1_SHIFT 16 /**< Shift value for MODEM_COHCHPWRTH1 */ +#define _MODEM_COH0_COHCHPWRTH1_MASK 0xFF0000UL /**< Bit mask for MODEM_COHCHPWRTH1 */ +#define _MODEM_COH0_COHCHPWRTH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRTH1_DEFAULT (_MODEM_COH0_COHCHPWRTH1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH0 */ +#define _MODEM_COH0_COHCHPWRTH2_SHIFT 24 /**< Shift value for MODEM_COHCHPWRTH2 */ +#define _MODEM_COH0_COHCHPWRTH2_MASK 0xFF000000UL /**< Bit mask for MODEM_COHCHPWRTH2 */ +#define _MODEM_COH0_COHCHPWRTH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */ +#define MODEM_COH0_COHCHPWRTH2_DEFAULT (_MODEM_COH0_COHCHPWRTH2_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH0 */ + +/* Bit fields for MODEM COH1 */ +#define _MODEM_COH1_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH1 */ +#define _MODEM_COH1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH1 */ +#define _MODEM_COH1_SYNCTHRESH0_SHIFT 0 /**< Shift value for MODEM_SYNCTHRESH0 */ +#define _MODEM_COH1_SYNCTHRESH0_MASK 0xFFUL /**< Bit mask for MODEM_SYNCTHRESH0 */ +#define _MODEM_COH1_SYNCTHRESH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */ +#define MODEM_COH1_SYNCTHRESH0_DEFAULT (_MODEM_COH1_SYNCTHRESH0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH1 */ +#define _MODEM_COH1_SYNCTHRESH1_SHIFT 8 /**< Shift value for MODEM_SYNCTHRESH1 */ +#define _MODEM_COH1_SYNCTHRESH1_MASK 0xFF00UL /**< Bit mask for MODEM_SYNCTHRESH1 */ +#define _MODEM_COH1_SYNCTHRESH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */ +#define MODEM_COH1_SYNCTHRESH1_DEFAULT (_MODEM_COH1_SYNCTHRESH1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH1 */ +#define _MODEM_COH1_SYNCTHRESH2_SHIFT 16 /**< Shift value for MODEM_SYNCTHRESH2 */ +#define _MODEM_COH1_SYNCTHRESH2_MASK 0xFF0000UL /**< Bit mask for MODEM_SYNCTHRESH2 */ +#define _MODEM_COH1_SYNCTHRESH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */ +#define MODEM_COH1_SYNCTHRESH2_DEFAULT (_MODEM_COH1_SYNCTHRESH2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH1 */ +#define _MODEM_COH1_SYNCTHRESH3_SHIFT 24 /**< Shift value for MODEM_SYNCTHRESH3 */ +#define _MODEM_COH1_SYNCTHRESH3_MASK 0xFF000000UL /**< Bit mask for MODEM_SYNCTHRESH3 */ +#define _MODEM_COH1_SYNCTHRESH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */ +#define MODEM_COH1_SYNCTHRESH3_DEFAULT (_MODEM_COH1_SYNCTHRESH3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH1 */ + +/* Bit fields for MODEM COH2 */ +#define _MODEM_COH2_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH2 */ +#define _MODEM_COH2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA0_SHIFT 0 /**< Shift value for MODEM_SYNCTHRESHDELTA0 */ +#define _MODEM_COH2_SYNCTHRESHDELTA0_MASK 0xFUL /**< Bit mask for MODEM_SYNCTHRESHDELTA0 */ +#define _MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA1_SHIFT 4 /**< Shift value for MODEM_SYNCTHRESHDELTA1 */ +#define _MODEM_COH2_SYNCTHRESHDELTA1_MASK 0xF0UL /**< Bit mask for MODEM_SYNCTHRESHDELTA1 */ +#define _MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_COH2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA2_SHIFT 8 /**< Shift value for MODEM_SYNCTHRESHDELTA2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA2_MASK 0xF00UL /**< Bit mask for MODEM_SYNCTHRESHDELTA2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH2 */ +#define _MODEM_COH2_SYNCTHRESHDELTA3_SHIFT 12 /**< Shift value for MODEM_SYNCTHRESHDELTA3 */ +#define _MODEM_COH2_SYNCTHRESHDELTA3_MASK 0xF000UL /**< Bit mask for MODEM_SYNCTHRESHDELTA3 */ +#define _MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_COH2 */ +#define _MODEM_COH2_DSAPEAKCHPWRTH_SHIFT 16 /**< Shift value for MODEM_DSAPEAKCHPWRTH */ +#define _MODEM_COH2_DSAPEAKCHPWRTH_MASK 0xFF0000UL /**< Bit mask for MODEM_DSAPEAKCHPWRTH */ +#define _MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT (_MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH2 */ +#define _MODEM_COH2_FIXEDCDTHFORIIR_SHIFT 24 /**< Shift value for MODEM_FIXEDCDTHFORIIR */ +#define _MODEM_COH2_FIXEDCDTHFORIIR_MASK 0xFF000000UL /**< Bit mask for MODEM_FIXEDCDTHFORIIR */ +#define _MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */ +#define MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT (_MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH2 */ + +/* Bit fields for MODEM COH3 */ +#define _MODEM_COH3_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH3 */ +#define _MODEM_COH3_MASK 0x3FFFFFFFUL /**< Mask for MODEM_COH3 */ +#define MODEM_COH3_COHDSAEN (0x1UL << 0) /**< DSA enable bit */ +#define _MODEM_COH3_COHDSAEN_SHIFT 0 /**< Shift value for MODEM_COHDSAEN */ +#define _MODEM_COH3_COHDSAEN_MASK 0x1UL /**< Bit mask for MODEM_COHDSAEN */ +#define _MODEM_COH3_COHDSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSAEN_DEFAULT (_MODEM_COH3_COHDSAEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define _MODEM_COH3_COHDSAADDWNDSIZE_SHIFT 1 /**< Shift value for MODEM_COHDSAADDWNDSIZE */ +#define _MODEM_COH3_COHDSAADDWNDSIZE_MASK 0x7FEUL /**< Bit mask for MODEM_COHDSAADDWNDSIZE */ +#define _MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT (_MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define _MODEM_COH3_CDSS_SHIFT 11 /**< Shift value for MODEM_CDSS */ +#define _MODEM_COH3_CDSS_MASK 0x3800UL /**< Bit mask for MODEM_CDSS */ +#define _MODEM_COH3_CDSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_CDSS_DEFAULT (_MODEM_COH3_CDSS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DSAPEAKCHKEN (0x1UL << 14) /**< DSA Peak Checking Enable */ +#define _MODEM_COH3_DSAPEAKCHKEN_SHIFT 14 /**< Shift value for MODEM_DSAPEAKCHKEN */ +#define _MODEM_COH3_DSAPEAKCHKEN_MASK 0x4000UL /**< Bit mask for MODEM_DSAPEAKCHKEN */ +#define _MODEM_COH3_DSAPEAKCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DSAPEAKCHKEN_DEFAULT (_MODEM_COH3_DSAPEAKCHKEN_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define _MODEM_COH3_DSAPEAKINDLEN_SHIFT 15 /**< Shift value for MODEM_DSAPEAKINDLEN */ +#define _MODEM_COH3_DSAPEAKINDLEN_MASK 0x38000UL /**< Bit mask for MODEM_DSAPEAKINDLEN */ +#define _MODEM_COH3_DSAPEAKINDLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DSAPEAKINDLEN_DEFAULT (_MODEM_COH3_DSAPEAKINDLEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DSAPEAKCHPWREN (0x1UL << 18) /**< DSA Peak Check channel power enable */ +#define _MODEM_COH3_DSAPEAKCHPWREN_SHIFT 18 /**< Shift value for MODEM_DSAPEAKCHPWREN */ +#define _MODEM_COH3_DSAPEAKCHPWREN_MASK 0x40000UL /**< Bit mask for MODEM_DSAPEAKCHPWREN */ +#define _MODEM_COH3_DSAPEAKCHPWREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DSAPEAKCHPWREN_DEFAULT (_MODEM_COH3_DSAPEAKCHPWREN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_LOGICBASEDCOHDEMODGATE (0x1UL << 19) /**< Logic Based clock gate */ +#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_SHIFT 19 /**< Shift value for MODEM_LOGICBASEDCOHDEMODGATE*/ +#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_MASK 0x80000UL /**< Bit mask for MODEM_LOGICBASEDCOHDEMODGATE */ +#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT (_MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define _MODEM_COH3_DYNIIRCOEFOPTION_SHIFT 20 /**< Shift value for MODEM_DYNIIRCOEFOPTION */ +#define _MODEM_COH3_DYNIIRCOEFOPTION_MASK 0x300000UL /**< Bit mask for MODEM_DYNIIRCOEFOPTION */ +#define _MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT (_MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_ONEPEAKQUALEN (0x1UL << 22) /**< One Peak */ +#define _MODEM_COH3_ONEPEAKQUALEN_SHIFT 22 /**< Shift value for MODEM_ONEPEAKQUALEN */ +#define _MODEM_COH3_ONEPEAKQUALEN_MASK 0x400000UL /**< Bit mask for MODEM_ONEPEAKQUALEN */ +#define _MODEM_COH3_ONEPEAKQUALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_ONEPEAKQUALEN_DEFAULT (_MODEM_COH3_ONEPEAKQUALEN_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define _MODEM_COH3_PEAKCHKTIMOUT_SHIFT 23 /**< Shift value for MODEM_PEAKCHKTIMOUT */ +#define _MODEM_COH3_PEAKCHKTIMOUT_MASK 0xF800000UL /**< Bit mask for MODEM_PEAKCHKTIMOUT */ +#define _MODEM_COH3_PEAKCHKTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_PEAKCHKTIMOUT_DEFAULT (_MODEM_COH3_PEAKCHKTIMOUT_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSADETDIS (0x1UL << 28) /**< DSA Detection Disable */ +#define _MODEM_COH3_COHDSADETDIS_SHIFT 28 /**< Shift value for MODEM_COHDSADETDIS */ +#define _MODEM_COH3_COHDSADETDIS_MASK 0x10000000UL /**< Bit mask for MODEM_COHDSADETDIS */ +#define _MODEM_COH3_COHDSADETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSADETDIS_DEFAULT (_MODEM_COH3_COHDSADETDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSACMPLX (0x1UL << 29) /**< DSA Complex */ +#define _MODEM_COH3_COHDSACMPLX_SHIFT 29 /**< Shift value for MODEM_COHDSACMPLX */ +#define _MODEM_COH3_COHDSACMPLX_MASK 0x20000000UL /**< Bit mask for MODEM_COHDSACMPLX */ +#define _MODEM_COH3_COHDSACMPLX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */ +#define MODEM_COH3_COHDSACMPLX_DEFAULT (_MODEM_COH3_COHDSACMPLX_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_COH3 */ + +/* Bit fields for MODEM CMD */ +#define _MODEM_CMD_RESETVALUE 0x00000000UL /**< Default value for MODEM_CMD */ +#define _MODEM_CMD_MASK 0x0000003BUL /**< Mask for MODEM_CMD */ +#define MODEM_CMD_PRESTOP (0x1UL << 0) /**< Preamble stop */ +#define _MODEM_CMD_PRESTOP_SHIFT 0 /**< Shift value for MODEM_PRESTOP */ +#define _MODEM_CMD_PRESTOP_MASK 0x1UL /**< Bit mask for MODEM_PRESTOP */ +#define _MODEM_CMD_PRESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_PRESTOP_DEFAULT (_MODEM_CMD_PRESTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_CHPWRACCUCLR (0x1UL << 1) /**< Channel Power Accumulation Clear */ +#define _MODEM_CMD_CHPWRACCUCLR_SHIFT 1 /**< Shift value for MODEM_CHPWRACCUCLR */ +#define _MODEM_CMD_CHPWRACCUCLR_MASK 0x2UL /**< Bit mask for MODEM_CHPWRACCUCLR */ +#define _MODEM_CMD_CHPWRACCUCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_CHPWRACCUCLR_DEFAULT (_MODEM_CMD_CHPWRACCUCLR_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCTXLOCK (0x1UL << 3) /**< Lock AFC TX compensation */ +#define _MODEM_CMD_AFCTXLOCK_SHIFT 3 /**< Shift value for MODEM_AFCTXLOCK */ +#define _MODEM_CMD_AFCTXLOCK_MASK 0x8UL /**< Bit mask for MODEM_AFCTXLOCK */ +#define _MODEM_CMD_AFCTXLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCTXLOCK_DEFAULT (_MODEM_CMD_AFCTXLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCTXCLEAR (0x1UL << 4) /**< Clear AFC TX compensation. */ +#define _MODEM_CMD_AFCTXCLEAR_SHIFT 4 /**< Shift value for MODEM_AFCTXCLEAR */ +#define _MODEM_CMD_AFCTXCLEAR_MASK 0x10UL /**< Bit mask for MODEM_AFCTXCLEAR */ +#define _MODEM_CMD_AFCTXCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCTXCLEAR_DEFAULT (_MODEM_CMD_AFCTXCLEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCRXCLEAR (0x1UL << 5) /**< Clear AFC RX compensation. */ +#define _MODEM_CMD_AFCRXCLEAR_SHIFT 5 /**< Shift value for MODEM_AFCRXCLEAR */ +#define _MODEM_CMD_AFCRXCLEAR_MASK 0x20UL /**< Bit mask for MODEM_AFCRXCLEAR */ +#define _MODEM_CMD_AFCRXCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */ +#define MODEM_CMD_AFCRXCLEAR_DEFAULT (_MODEM_CMD_AFCRXCLEAR_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CMD */ + +/* Bit fields for MODEM SYNCPROPERTIES */ +#define _MODEM_SYNCPROPERTIES_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNCPROPERTIES */ +#define _MODEM_SYNCPROPERTIES_MASK 0x0001FF00UL /**< Mask for MODEM_SYNCPROPERTIES */ +#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN (0x1UL << 8) /**< Static Sync Threshold Enable */ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_SHIFT 8 /**< Shift value for MODEM_STATICSYNCTHRESHEN */ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_MASK 0x100UL /**< Bit mask for MODEM_STATICSYNCTHRESHEN */ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNCPROPERTIES */ +#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT (_MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SYNCPROPERTIES*/ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_SHIFT 9 /**< Shift value for MODEM_STATICSYNCTHRESH */ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_MASK 0x1FE00UL /**< Bit mask for MODEM_STATICSYNCTHRESH */ +#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNCPROPERTIES */ +#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT (_MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SYNCPROPERTIES*/ + +/* Bit fields for MODEM DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_MASK 0x000001FFUL /**< Mask for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINEN (0x1UL << 0) /**< Digital Gain Enable */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_SHIFT 0 /**< Shift value for MODEM_DIGIGAINEN */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_MASK 0x1UL /**< Bit mask for MODEM_DIGIGAINEN */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_SHIFT 1 /**< Shift value for MODEM_DIGIGAINSEL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_MASK 0x3EUL /**< Bit mask for MODEM_DIGIGAINSEL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 0x00000000UL /**< Mode GAINM3 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 0x00000001UL /**< Mode GAINM2P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 0x00000002UL /**< Mode GAINM2P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 0x00000003UL /**< Mode GAINM2P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 0x00000004UL /**< Mode GAINM2 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 0x00000005UL /**< Mode GAINM1P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 0x00000006UL /**< Mode GAINM1P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 0x00000007UL /**< Mode GAINM1P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 0x00000008UL /**< Mode GAINM1 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 0x00000009UL /**< Mode GAINM0P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 0x0000000AUL /**< Mode GAINM0P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 0x0000000BUL /**< Mode GAINM0P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 0x0000000CUL /**< Mode GAINM0 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 0x0000000DUL /**< Mode GAINP0P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 0x0000000EUL /**< Mode GAINP0P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 0x0000000FUL /**< Mode GAINP0P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 0x00000010UL /**< Mode GAINP1 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 0x00000011UL /**< Mode GAINP1P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 0x00000012UL /**< Mode GAINP1P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 0x00000013UL /**< Mode GAINP1P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 0x00000014UL /**< Mode GAINP2 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 0x00000015UL /**< Mode GAINP2P25 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 0x00000016UL /**< Mode GAINP2P5 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 0x00000017UL /**< Mode GAINP2P75 for MODEM_DIGIGAINCTRL */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 0x00000018UL /**< Mode GAINP3 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 << 1) /**< Shifted mode GAINM3 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 << 1) /**< Shifted mode GAINM2P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 << 1) /**< Shifted mode GAINM2P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 << 1) /**< Shifted mode GAINM2P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 << 1) /**< Shifted mode GAINM2 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 << 1) /**< Shifted mode GAINM1P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 << 1) /**< Shifted mode GAINM1P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 << 1) /**< Shifted mode GAINM1P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 << 1) /**< Shifted mode GAINM1 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 << 1) /**< Shifted mode GAINM0P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 << 1) /**< Shifted mode GAINM0P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 << 1) /**< Shifted mode GAINM0P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 << 1) /**< Shifted mode GAINM0 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 << 1) /**< Shifted mode GAINP0P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 << 1) /**< Shifted mode GAINP0P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 << 1) /**< Shifted mode GAINP0P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 << 1) /**< Shifted mode GAINP1 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 << 1) /**< Shifted mode GAINP1P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 << 1) /**< Shifted mode GAINP1P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 << 1) /**< Shifted mode GAINP1P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 << 1) /**< Shifted mode GAINP2 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 << 1) /**< Shifted mode GAINP2P25 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 << 1) /**< Shifted mode GAINP2P5 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 << 1) /**< Shifted mode GAINP2P75 for MODEM_DIGIGAINCTRL*/ +#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 << 1) /**< Shifted mode GAINP3 for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE (0x1UL << 6) /**< Digital Gain Doubled */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_SHIFT 6 /**< Shift value for MODEM_DIGIGAINDOUBLE */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_MASK 0x40UL /**< Bit mask for MODEM_DIGIGAINDOUBLE */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINHALF (0x1UL << 7) /**< Digital Gain Halved */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_SHIFT 7 /**< Shift value for MODEM_DIGIGAINHALF */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_MASK 0x80UL /**< Bit mask for MODEM_DIGIGAINHALF */ +#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DEC0GAIN (0x1UL << 8) /**< DEC0 Gain Select */ +#define _MODEM_DIGIGAINCTRL_DEC0GAIN_SHIFT 8 /**< Shift value for MODEM_DEC0GAIN */ +#define _MODEM_DIGIGAINCTRL_DEC0GAIN_MASK 0x100UL /**< Bit mask for MODEM_DEC0GAIN */ +#define _MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */ +#define MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT (_MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */ + +/* Bit fields for MODEM PRSCTRL */ +#define _MODEM_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_MASK 0x000FFFFFUL /**< Mask for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_POSTPONESEL_SHIFT 0 /**< Shift value for MODEM_POSTPONESEL */ +#define _MODEM_PRSCTRL_POSTPONESEL_MASK 0x3UL /**< Bit mask for MODEM_POSTPONESEL */ +#define _MODEM_PRSCTRL_POSTPONESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_POSTPONESEL_DEFAULT (_MODEM_PRSCTRL_POSTPONESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_ADVANCESEL_SHIFT 2 /**< Shift value for MODEM_ADVANCESEL */ +#define _MODEM_PRSCTRL_ADVANCESEL_MASK 0xCUL /**< Bit mask for MODEM_ADVANCESEL */ +#define _MODEM_PRSCTRL_ADVANCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_ADVANCESEL_DEFAULT (_MODEM_PRSCTRL_ADVANCESEL_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_NEWWNDSEL_SHIFT 4 /**< Shift value for MODEM_NEWWNDSEL */ +#define _MODEM_PRSCTRL_NEWWNDSEL_MASK 0x30UL /**< Bit mask for MODEM_NEWWNDSEL */ +#define _MODEM_PRSCTRL_NEWWNDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_NEWWNDSEL_DEFAULT (_MODEM_PRSCTRL_NEWWNDSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_WEAKSEL_SHIFT 6 /**< Shift value for MODEM_WEAKSEL */ +#define _MODEM_PRSCTRL_WEAKSEL_MASK 0xC0UL /**< Bit mask for MODEM_WEAKSEL */ +#define _MODEM_PRSCTRL_WEAKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_WEAKSEL_DEFAULT (_MODEM_PRSCTRL_WEAKSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_SYNCSENTSEL_SHIFT 8 /**< Shift value for MODEM_SYNCSENTSEL */ +#define _MODEM_PRSCTRL_SYNCSENTSEL_MASK 0x300UL /**< Bit mask for MODEM_SYNCSENTSEL */ +#define _MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT (_MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_PRESENTSEL_SHIFT 10 /**< Shift value for MODEM_PRESENTSEL */ +#define _MODEM_PRSCTRL_PRESENTSEL_MASK 0xC00UL /**< Bit mask for MODEM_PRESENTSEL */ +#define _MODEM_PRSCTRL_PRESENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_PRESENTSEL_DEFAULT (_MODEM_PRSCTRL_PRESENTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_LOWCORRSEL_SHIFT 12 /**< Shift value for MODEM_LOWCORRSEL */ +#define _MODEM_PRSCTRL_LOWCORRSEL_MASK 0x3000UL /**< Bit mask for MODEM_LOWCORRSEL */ +#define _MODEM_PRSCTRL_LOWCORRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_LOWCORRSEL_DEFAULT (_MODEM_PRSCTRL_LOWCORRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_ANT0SEL_SHIFT 14 /**< Shift value for MODEM_ANT0SEL */ +#define _MODEM_PRSCTRL_ANT0SEL_MASK 0xC000UL /**< Bit mask for MODEM_ANT0SEL */ +#define _MODEM_PRSCTRL_ANT0SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_ANT0SEL_DEFAULT (_MODEM_PRSCTRL_ANT0SEL_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_ANT1SEL_SHIFT 16 /**< Shift value for MODEM_ANT1SEL */ +#define _MODEM_PRSCTRL_ANT1SEL_MASK 0x30000UL /**< Bit mask for MODEM_ANT1SEL */ +#define _MODEM_PRSCTRL_ANT1SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_ANT1SEL_DEFAULT (_MODEM_PRSCTRL_ANT1SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ +#define _MODEM_PRSCTRL_IFADCCLKSEL_SHIFT 18 /**< Shift value for MODEM_IFADCCLKSEL */ +#define _MODEM_PRSCTRL_IFADCCLKSEL_MASK 0xC0000UL /**< Bit mask for MODEM_IFADCCLKSEL */ +#define _MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */ +#define MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT (_MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */ + +/* Bit fields for MODEM REALTIMCFE */ +#define _MODEM_REALTIMCFE_RESETVALUE 0x001F81F4UL /**< Default value for MODEM_REALTIMCFE */ +#define _MODEM_REALTIMCFE_MASK 0xE03FFFFFUL /**< Mask for MODEM_REALTIMCFE */ +#define _MODEM_REALTIMCFE_MINCOSTTHD_SHIFT 0 /**< Shift value for MODEM_MINCOSTTHD */ +#define _MODEM_REALTIMCFE_MINCOSTTHD_MASK 0x3FFUL /**< Bit mask for MODEM_MINCOSTTHD */ +#define _MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT 0x000001F4UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT (_MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define _MODEM_REALTIMCFE_RTSCHWIN_SHIFT 10 /**< Shift value for MODEM_RTSCHWIN */ +#define _MODEM_REALTIMCFE_RTSCHWIN_MASK 0x3C00UL /**< Bit mask for MODEM_RTSCHWIN */ +#define _MODEM_REALTIMCFE_RTSCHWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_RTSCHWIN_DEFAULT (_MODEM_REALTIMCFE_RTSCHWIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_RTSCHMODE (0x1UL << 14) /**< Real Time CFE searching mode */ +#define _MODEM_REALTIMCFE_RTSCHMODE_SHIFT 14 /**< Shift value for MODEM_RTSCHMODE */ +#define _MODEM_REALTIMCFE_RTSCHMODE_MASK 0x4000UL /**< Bit mask for MODEM_RTSCHMODE */ +#define _MODEM_REALTIMCFE_RTSCHMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_RTSCHMODE_DEFAULT (_MODEM_REALTIMCFE_RTSCHMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define _MODEM_REALTIMCFE_TRACKINGWIN_SHIFT 15 /**< Shift value for MODEM_TRACKINGWIN */ +#define _MODEM_REALTIMCFE_TRACKINGWIN_MASK 0x38000UL /**< Bit mask for MODEM_TRACKINGWIN */ +#define _MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT (_MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define _MODEM_REALTIMCFE_SYNCACQWIN_SHIFT 18 /**< Shift value for MODEM_SYNCACQWIN */ +#define _MODEM_REALTIMCFE_SYNCACQWIN_MASK 0x1C0000UL /**< Bit mask for MODEM_SYNCACQWIN */ +#define _MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT (_MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_EXTENSCHBYP (0x1UL << 21) /**< Bypass extending Search Time */ +#define _MODEM_REALTIMCFE_EXTENSCHBYP_SHIFT 21 /**< Shift value for MODEM_EXTENSCHBYP */ +#define _MODEM_REALTIMCFE_EXTENSCHBYP_MASK 0x200000UL /**< Bit mask for MODEM_EXTENSCHBYP */ +#define _MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT (_MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_SINEWEN (0x1UL << 29) /**< Enable SINE WEIGHT */ +#define _MODEM_REALTIMCFE_SINEWEN_SHIFT 29 /**< Shift value for MODEM_SINEWEN */ +#define _MODEM_REALTIMCFE_SINEWEN_MASK 0x20000000UL /**< Bit mask for MODEM_SINEWEN */ +#define _MODEM_REALTIMCFE_SINEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_SINEWEN_DEFAULT (_MODEM_REALTIMCFE_SINEWEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_VTAFCFRAME (0x1UL << 30) /**< Viterbi AFC FRAME Mode */ +#define _MODEM_REALTIMCFE_VTAFCFRAME_SHIFT 30 /**< Shift value for MODEM_VTAFCFRAME */ +#define _MODEM_REALTIMCFE_VTAFCFRAME_MASK 0x40000000UL /**< Bit mask for MODEM_VTAFCFRAME */ +#define _MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT (_MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_RTCFEEN (0x1UL << 31) /**< TRECS Enable */ +#define _MODEM_REALTIMCFE_RTCFEEN_SHIFT 31 /**< Shift value for MODEM_RTCFEEN */ +#define _MODEM_REALTIMCFE_RTCFEEN_MASK 0x80000000UL /**< Bit mask for MODEM_RTCFEEN */ +#define _MODEM_REALTIMCFE_RTCFEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */ +#define MODEM_REALTIMCFE_RTCFEEN_DEFAULT (_MODEM_REALTIMCFE_RTCFEEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */ + +/* Bit fields for MODEM ETSCTRL */ +#define _MODEM_ETSCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_ETSCTRL */ +#define _MODEM_ETSCTRL_MASK 0x3FFFF7FFUL /**< Mask for MODEM_ETSCTRL */ +#define _MODEM_ETSCTRL_ETSLOC_SHIFT 0 /**< Shift value for MODEM_ETSLOC */ +#define _MODEM_ETSCTRL_ETSLOC_MASK 0x3FFUL /**< Bit mask for MODEM_ETSLOC */ +#define _MODEM_ETSCTRL_ETSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */ +#define MODEM_ETSCTRL_ETSLOC_DEFAULT (_MODEM_ETSCTRL_ETSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */ +#define MODEM_ETSCTRL_CAPSIGONPRS (0x1UL << 10) /**< Capture Signal On PRS */ +#define _MODEM_ETSCTRL_CAPSIGONPRS_SHIFT 10 /**< Shift value for MODEM_CAPSIGONPRS */ +#define _MODEM_ETSCTRL_CAPSIGONPRS_MASK 0x400UL /**< Bit mask for MODEM_CAPSIGONPRS */ +#define _MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */ +#define MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT (_MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */ +#define _MODEM_ETSCTRL_CAPTRIG_SHIFT 12 /**< Shift value for MODEM_CAPTRIG */ +#define _MODEM_ETSCTRL_CAPTRIG_MASK 0x3FFFF000UL /**< Bit mask for MODEM_CAPTRIG */ +#define _MODEM_ETSCTRL_CAPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */ +#define MODEM_ETSCTRL_CAPTRIG_DEFAULT (_MODEM_ETSCTRL_CAPTRIG_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */ + +/* Bit fields for MODEM ETSTIM */ +#define _MODEM_ETSTIM_RESETVALUE 0x00000000UL /**< Default value for MODEM_ETSTIM */ +#define _MODEM_ETSTIM_MASK 0x0003FFFFUL /**< Mask for MODEM_ETSTIM */ +#define _MODEM_ETSTIM_ETSTIMVAL_SHIFT 0 /**< Shift value for MODEM_ETSTIMVAL */ +#define _MODEM_ETSTIM_ETSTIMVAL_MASK 0x1FFFFUL /**< Bit mask for MODEM_ETSTIMVAL */ +#define _MODEM_ETSTIM_ETSTIMVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSTIM */ +#define MODEM_ETSTIM_ETSTIMVAL_DEFAULT (_MODEM_ETSTIM_ETSTIMVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ETSTIM */ +#define MODEM_ETSTIM_ETSCOUNTEREN (0x1UL << 17) /**< ETSCOUNTEREN */ +#define _MODEM_ETSTIM_ETSCOUNTEREN_SHIFT 17 /**< Shift value for MODEM_ETSCOUNTEREN */ +#define _MODEM_ETSTIM_ETSCOUNTEREN_MASK 0x20000UL /**< Bit mask for MODEM_ETSCOUNTEREN */ +#define _MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSTIM */ +#define MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT (_MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ETSTIM */ + +/* Bit fields for MODEM ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_RESETVALUE 0x003C0000UL /**< Default value for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_MASK 0x01FFFFFFUL /**< Mask for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTDFLTSEL_SHIFT 0 /**< Shift value for MODEM_ANTDFLTSEL */ +#define _MODEM_ANTSWCTRL_ANTDFLTSEL_MASK 0x3FUL /**< Bit mask for MODEM_ANTDFLTSEL */ +#define _MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT (_MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTCOUNT_SHIFT 6 /**< Shift value for MODEM_ANTCOUNT */ +#define _MODEM_ANTSWCTRL_ANTCOUNT_MASK 0xFC0UL /**< Bit mask for MODEM_ANTCOUNT */ +#define _MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT (_MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_SHIFT 12 /**< Shift value for MODEM_ANTSWTYPE */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_MASK 0x3000UL /**< Bit mask for MODEM_ANTSWTYPE */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_2 0x00000000UL /**< Mode US_2 for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_4 0x00000001UL /**< Mode US_4 for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_6 0x00000002UL /**< Mode US_6 for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_8 0x00000003UL /**< Mode US_8 for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT (_MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWTYPE_US_2 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_2 << 12) /**< Shifted mode US_2 for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWTYPE_US_4 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_4 << 12) /**< Shifted mode US_4 for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWTYPE_US_6 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_6 << 12) /**< Shifted mode US_6 for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWTYPE_US_8 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_8 << 12) /**< Shifted mode US_8 for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWRST (0x1UL << 14) /**< Ant SW rst pulse */ +#define _MODEM_ANTSWCTRL_ANTSWRST_SHIFT 14 /**< Shift value for MODEM_ANTSWRST */ +#define _MODEM_ANTSWCTRL_ANTSWRST_MASK 0x4000UL /**< Bit mask for MODEM_ANTSWRST */ +#define _MODEM_ANTSWCTRL_ANTSWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWRST_DEFAULT (_MODEM_ANTSWCTRL_ANTSWRST_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_CFGANTPATTEN (0x1UL << 15) /**< Configure Ant Pattern Enable */ +#define _MODEM_ANTSWCTRL_CFGANTPATTEN_SHIFT 15 /**< Shift value for MODEM_CFGANTPATTEN */ +#define _MODEM_ANTSWCTRL_CFGANTPATTEN_MASK 0x8000UL /**< Bit mask for MODEM_CFGANTPATTEN */ +#define _MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT (_MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWENABLE (0x1UL << 16) /**< Ant sw enable */ +#define _MODEM_ANTSWCTRL_ANTSWENABLE_SHIFT 16 /**< Shift value for MODEM_ANTSWENABLE */ +#define _MODEM_ANTSWCTRL_ANTSWENABLE_MASK 0x10000UL /**< Bit mask for MODEM_ANTSWENABLE */ +#define _MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT (_MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ +#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_SHIFT 17 /**< Shift value for MODEM_EXTDSTOPPULSECNT */ +#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_MASK 0x1FE0000UL /**< Bit mask for MODEM_EXTDSTOPPULSECNT */ +#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT 0x0000001EUL /**< Mode DEFAULT for MODEM_ANTSWCTRL */ +#define MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT (_MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */ + +/* Bit fields for MODEM ANTSWCTRL1 */ +#define _MODEM_ANTSWCTRL1_RESETVALUE 0x0006AAAAUL /**< Default value for MODEM_ANTSWCTRL1 */ +#define _MODEM_ANTSWCTRL1_MASK 0x00FFFFFFUL /**< Mask for MODEM_ANTSWCTRL1 */ +#define _MODEM_ANTSWCTRL1_TIMEPERIOD_SHIFT 0 /**< Shift value for MODEM_TIMEPERIOD */ +#define _MODEM_ANTSWCTRL1_TIMEPERIOD_MASK 0xFFFFFFUL /**< Bit mask for MODEM_TIMEPERIOD */ +#define _MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT 0x0006AAAAUL /**< Mode DEFAULT for MODEM_ANTSWCTRL1 */ +#define MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT (_MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL1 */ + +/* Bit fields for MODEM ANTSWSTART */ +#define _MODEM_ANTSWSTART_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTSWSTART */ +#define _MODEM_ANTSWSTART_MASK 0x0003FFFFUL /**< Mask for MODEM_ANTSWSTART */ +#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_SHIFT 0 /**< Shift value for MODEM_ANTSWSTARTTIM */ +#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_ANTSWSTARTTIM */ +#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWSTART */ +#define MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT (_MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWSTART */ + +/* Bit fields for MODEM ANTSWEND */ +#define _MODEM_ANTSWEND_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTSWEND */ +#define _MODEM_ANTSWEND_MASK 0x0003FFFFUL /**< Mask for MODEM_ANTSWEND */ +#define _MODEM_ANTSWEND_ANTSWENDTIM_SHIFT 0 /**< Shift value for MODEM_ANTSWENDTIM */ +#define _MODEM_ANTSWEND_ANTSWENDTIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_ANTSWENDTIM */ +#define _MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWEND */ +#define MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT (_MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWEND */ + +/* Bit fields for MODEM TRECPMPATT */ +#define _MODEM_TRECPMPATT_RESETVALUE 0x55555555UL /**< Default value for MODEM_TRECPMPATT */ +#define _MODEM_TRECPMPATT_MASK 0xFFFFFFFFUL /**< Mask for MODEM_TRECPMPATT */ +#define _MODEM_TRECPMPATT_PMEXPECTPATT_SHIFT 0 /**< Shift value for MODEM_PMEXPECTPATT */ +#define _MODEM_TRECPMPATT_PMEXPECTPATT_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_PMEXPECTPATT */ +#define _MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT 0x55555555UL /**< Mode DEFAULT for MODEM_TRECPMPATT */ +#define MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT (_MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECPMPATT */ + +/* Bit fields for MODEM TRECPMDET */ +#define _MODEM_TRECPMDET_RESETVALUE 0x00000017UL /**< Default value for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_MASK 0xBEFFC3FFUL /**< Mask for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_PMACQUINGWIN_SHIFT 0 /**< Shift value for MODEM_PMACQUINGWIN */ +#define _MODEM_TRECPMDET_PMACQUINGWIN_MASK 0x7UL /**< Bit mask for MODEM_PMACQUINGWIN */ +#define _MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT (_MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_PMCOSTVALTHD_SHIFT 3 /**< Shift value for MODEM_PMCOSTVALTHD */ +#define _MODEM_TRECPMDET_PMCOSTVALTHD_MASK 0x38UL /**< Bit mask for MODEM_PMCOSTVALTHD */ +#define _MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT (_MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_PMTIMEOUTSEL_SHIFT 6 /**< Shift value for MODEM_PMTIMEOUTSEL */ +#define _MODEM_TRECPMDET_PMTIMEOUTSEL_MASK 0xC0UL /**< Bit mask for MODEM_PMTIMEOUTSEL */ +#define _MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT (_MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_PHSCALE_SHIFT 8 /**< Shift value for MODEM_PHSCALE */ +#define _MODEM_TRECPMDET_PHSCALE_MASK 0x300UL /**< Bit mask for MODEM_PHSCALE */ +#define _MODEM_TRECPMDET_PHSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PHSCALE_DEFAULT (_MODEM_TRECPMDET_PHSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_PMMINCOSTTHD_SHIFT 14 /**< Shift value for MODEM_PMMINCOSTTHD */ +#define _MODEM_TRECPMDET_PMMINCOSTTHD_MASK 0xFFC000UL /**< Bit mask for MODEM_PMMINCOSTTHD */ +#define _MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT (_MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define _MODEM_TRECPMDET_COSTHYST_SHIFT 25 /**< Shift value for MODEM_COSTHYST */ +#define _MODEM_TRECPMDET_COSTHYST_MASK 0x3E000000UL /**< Bit mask for MODEM_COSTHYST */ +#define _MODEM_TRECPMDET_COSTHYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_COSTHYST_DEFAULT (_MODEM_TRECPMDET_COSTHYST_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PREAMSCH (0x1UL << 31) /**< PM detection enable in TRECS */ +#define _MODEM_TRECPMDET_PREAMSCH_SHIFT 31 /**< Shift value for MODEM_PREAMSCH */ +#define _MODEM_TRECPMDET_PREAMSCH_MASK 0x80000000UL /**< Bit mask for MODEM_PREAMSCH */ +#define _MODEM_TRECPMDET_PREAMSCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */ +#define MODEM_TRECPMDET_PREAMSCH_DEFAULT (_MODEM_TRECPMDET_PREAMSCH_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */ + +/* Bit fields for MODEM TRECSCFG */ +#define _MODEM_TRECSCFG_RESETVALUE 0x00020004UL /**< Default value for MODEM_TRECSCFG */ +#define _MODEM_TRECSCFG_MASK 0x01FF5FFFUL /**< Mask for MODEM_TRECSCFG */ +#define _MODEM_TRECSCFG_TRECSOSR_SHIFT 0 /**< Shift value for MODEM_TRECSOSR */ +#define _MODEM_TRECSCFG_TRECSOSR_MASK 0x7UL /**< Bit mask for MODEM_TRECSOSR */ +#define _MODEM_TRECSCFG_TRECSOSR_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_TRECSCFG */ +#define MODEM_TRECSCFG_TRECSOSR_DEFAULT (_MODEM_TRECSCFG_TRECSOSR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */ +#define _MODEM_TRECSCFG_DTIMLOSSTHD_SHIFT 3 /**< Shift value for MODEM_DTIMLOSSTHD */ +#define _MODEM_TRECSCFG_DTIMLOSSTHD_MASK 0x1FF8UL /**< Bit mask for MODEM_DTIMLOSSTHD */ +#define _MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECSCFG */ +#define MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT (_MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */ +#define MODEM_TRECSCFG_DTIMLOSSEN (0x1UL << 14) /**< ENABLE TIMING LOSS DETECTION */ +#define _MODEM_TRECSCFG_DTIMLOSSEN_SHIFT 14 /**< Shift value for MODEM_DTIMLOSSEN */ +#define _MODEM_TRECSCFG_DTIMLOSSEN_MASK 0x4000UL /**< Bit mask for MODEM_DTIMLOSSEN */ +#define _MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECSCFG */ +#define MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT (_MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */ +#define _MODEM_TRECSCFG_PMOFFSET_SHIFT 16 /**< Shift value for MODEM_PMOFFSET */ +#define _MODEM_TRECSCFG_PMOFFSET_MASK 0x1FF0000UL /**< Bit mask for MODEM_PMOFFSET */ +#define _MODEM_TRECSCFG_PMOFFSET_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_TRECSCFG */ +#define MODEM_TRECSCFG_PMOFFSET_DEFAULT (_MODEM_TRECSCFG_PMOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */ + +/* Bit fields for MODEM CFGANTPATT */ +#define _MODEM_CFGANTPATT_RESETVALUE 0x00000000UL /**< Default value for MODEM_CFGANTPATT */ +#define _MODEM_CFGANTPATT_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CFGANTPATT */ +#define _MODEM_CFGANTPATT_CFGANTPATTVAL_SHIFT 0 /**< Shift value for MODEM_CFGANTPATTVAL */ +#define _MODEM_CFGANTPATT_CFGANTPATTVAL_MASK 0x3FFFFFFFUL /**< Bit mask for MODEM_CFGANTPATTVAL */ +#define _MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CFGANTPATT */ +#define MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT (_MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CFGANTPATT */ + +/* Bit fields for MODEM COCURRMODE */ +#define _MODEM_COCURRMODE_RESETVALUE 0x00000000UL /**< Default value for MODEM_COCURRMODE */ +#define _MODEM_COCURRMODE_MASK 0x80000000UL /**< Mask for MODEM_COCURRMODE */ +#define MODEM_COCURRMODE_CONCURRENT (0x1UL << 31) /**< CONCURRENT MODE Enable */ +#define _MODEM_COCURRMODE_CONCURRENT_SHIFT 31 /**< Shift value for MODEM_CONCURRENT */ +#define _MODEM_COCURRMODE_CONCURRENT_MASK 0x80000000UL /**< Bit mask for MODEM_CONCURRENT */ +#define _MODEM_COCURRMODE_CONCURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COCURRMODE */ +#define MODEM_COCURRMODE_CONCURRENT_DEFAULT (_MODEM_COCURRMODE_CONCURRENT_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_COCURRMODE */ + +/* Bit fields for MODEM CHFCOE00 */ +#define _MODEM_CHFCOE00_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE00 */ +#define _MODEM_CHFCOE00_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE00 */ +#define _MODEM_CHFCOE00_SET0COEFF0_SHIFT 0 /**< Shift value for MODEM_SET0COEFF0 */ +#define _MODEM_CHFCOE00_SET0COEFF0_MASK 0x3FFUL /**< Bit mask for MODEM_SET0COEFF0 */ +#define _MODEM_CHFCOE00_SET0COEFF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */ +#define MODEM_CHFCOE00_SET0COEFF0_DEFAULT (_MODEM_CHFCOE00_SET0COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */ +#define _MODEM_CHFCOE00_SET0COEFF1_SHIFT 10 /**< Shift value for MODEM_SET0COEFF1 */ +#define _MODEM_CHFCOE00_SET0COEFF1_MASK 0xFFC00UL /**< Bit mask for MODEM_SET0COEFF1 */ +#define _MODEM_CHFCOE00_SET0COEFF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */ +#define MODEM_CHFCOE00_SET0COEFF1_DEFAULT (_MODEM_CHFCOE00_SET0COEFF1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */ +#define _MODEM_CHFCOE00_SET0COEFF2_SHIFT 20 /**< Shift value for MODEM_SET0COEFF2 */ +#define _MODEM_CHFCOE00_SET0COEFF2_MASK 0x3FF00000UL /**< Bit mask for MODEM_SET0COEFF2 */ +#define _MODEM_CHFCOE00_SET0COEFF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */ +#define MODEM_CHFCOE00_SET0COEFF2_DEFAULT (_MODEM_CHFCOE00_SET0COEFF2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */ + +/* Bit fields for MODEM CHFCOE01 */ +#define _MODEM_CHFCOE01_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE01 */ +#define _MODEM_CHFCOE01_MASK 0x003FFFFFUL /**< Mask for MODEM_CHFCOE01 */ +#define _MODEM_CHFCOE01_SET0COEFF3_SHIFT 0 /**< Shift value for MODEM_SET0COEFF3 */ +#define _MODEM_CHFCOE01_SET0COEFF3_MASK 0x7FFUL /**< Bit mask for MODEM_SET0COEFF3 */ +#define _MODEM_CHFCOE01_SET0COEFF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE01 */ +#define MODEM_CHFCOE01_SET0COEFF3_DEFAULT (_MODEM_CHFCOE01_SET0COEFF3_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE01 */ +#define _MODEM_CHFCOE01_SET0COEFF4_SHIFT 11 /**< Shift value for MODEM_SET0COEFF4 */ +#define _MODEM_CHFCOE01_SET0COEFF4_MASK 0x3FF800UL /**< Bit mask for MODEM_SET0COEFF4 */ +#define _MODEM_CHFCOE01_SET0COEFF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE01 */ +#define MODEM_CHFCOE01_SET0COEFF4_DEFAULT (_MODEM_CHFCOE01_SET0COEFF4_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE01 */ + +/* Bit fields for MODEM CHFCOE02 */ +#define _MODEM_CHFCOE02_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE02 */ +#define _MODEM_CHFCOE02_MASK 0x007FFFFFUL /**< Mask for MODEM_CHFCOE02 */ +#define _MODEM_CHFCOE02_SET0COEFF5_SHIFT 0 /**< Shift value for MODEM_SET0COEFF5 */ +#define _MODEM_CHFCOE02_SET0COEFF5_MASK 0x7FFUL /**< Bit mask for MODEM_SET0COEFF5 */ +#define _MODEM_CHFCOE02_SET0COEFF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE02 */ +#define MODEM_CHFCOE02_SET0COEFF5_DEFAULT (_MODEM_CHFCOE02_SET0COEFF5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE02 */ +#define _MODEM_CHFCOE02_SET0COEFF6_SHIFT 11 /**< Shift value for MODEM_SET0COEFF6 */ +#define _MODEM_CHFCOE02_SET0COEFF6_MASK 0x7FF800UL /**< Bit mask for MODEM_SET0COEFF6 */ +#define _MODEM_CHFCOE02_SET0COEFF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE02 */ +#define MODEM_CHFCOE02_SET0COEFF6_DEFAULT (_MODEM_CHFCOE02_SET0COEFF6_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE02 */ + +/* Bit fields for MODEM CHFCOE03 */ +#define _MODEM_CHFCOE03_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE03 */ +#define _MODEM_CHFCOE03_MASK 0x00FFFFFFUL /**< Mask for MODEM_CHFCOE03 */ +#define _MODEM_CHFCOE03_SET0COEFF7_SHIFT 0 /**< Shift value for MODEM_SET0COEFF7 */ +#define _MODEM_CHFCOE03_SET0COEFF7_MASK 0xFFFUL /**< Bit mask for MODEM_SET0COEFF7 */ +#define _MODEM_CHFCOE03_SET0COEFF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE03 */ +#define MODEM_CHFCOE03_SET0COEFF7_DEFAULT (_MODEM_CHFCOE03_SET0COEFF7_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE03 */ +#define _MODEM_CHFCOE03_SET0COEFF8_SHIFT 12 /**< Shift value for MODEM_SET0COEFF8 */ +#define _MODEM_CHFCOE03_SET0COEFF8_MASK 0xFFF000UL /**< Bit mask for MODEM_SET0COEFF8 */ +#define _MODEM_CHFCOE03_SET0COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE03 */ +#define MODEM_CHFCOE03_SET0COEFF8_DEFAULT (_MODEM_CHFCOE03_SET0COEFF8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CHFCOE03 */ + +/* Bit fields for MODEM CHFCOE04 */ +#define _MODEM_CHFCOE04_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE04 */ +#define _MODEM_CHFCOE04_MASK 0x0FFFFFFFUL /**< Mask for MODEM_CHFCOE04 */ +#define _MODEM_CHFCOE04_SET0COEFF9_SHIFT 0 /**< Shift value for MODEM_SET0COEFF9 */ +#define _MODEM_CHFCOE04_SET0COEFF9_MASK 0x3FFFUL /**< Bit mask for MODEM_SET0COEFF9 */ +#define _MODEM_CHFCOE04_SET0COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE04 */ +#define MODEM_CHFCOE04_SET0COEFF9_DEFAULT (_MODEM_CHFCOE04_SET0COEFF9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE04 */ +#define _MODEM_CHFCOE04_SET0COEFF10_SHIFT 14 /**< Shift value for MODEM_SET0COEFF10 */ +#define _MODEM_CHFCOE04_SET0COEFF10_MASK 0xFFFC000UL /**< Bit mask for MODEM_SET0COEFF10 */ +#define _MODEM_CHFCOE04_SET0COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE04 */ +#define MODEM_CHFCOE04_SET0COEFF10_DEFAULT (_MODEM_CHFCOE04_SET0COEFF10_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE04 */ + +/* Bit fields for MODEM CHFCOE05 */ +#define _MODEM_CHFCOE05_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE05 */ +#define _MODEM_CHFCOE05_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE05 */ +#define _MODEM_CHFCOE05_SET0COEFF11_SHIFT 0 /**< Shift value for MODEM_SET0COEFF11 */ +#define _MODEM_CHFCOE05_SET0COEFF11_MASK 0x3FFFUL /**< Bit mask for MODEM_SET0COEFF11 */ +#define _MODEM_CHFCOE05_SET0COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE05 */ +#define MODEM_CHFCOE05_SET0COEFF11_DEFAULT (_MODEM_CHFCOE05_SET0COEFF11_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE05 */ +#define _MODEM_CHFCOE05_SET0COEFF12_SHIFT 14 /**< Shift value for MODEM_SET0COEFF12 */ +#define _MODEM_CHFCOE05_SET0COEFF12_MASK 0x3FFFC000UL /**< Bit mask for MODEM_SET0COEFF12 */ +#define _MODEM_CHFCOE05_SET0COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE05 */ +#define MODEM_CHFCOE05_SET0COEFF12_DEFAULT (_MODEM_CHFCOE05_SET0COEFF12_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE05 */ + +/* Bit fields for MODEM CHFCOE06 */ +#define _MODEM_CHFCOE06_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE06 */ +#define _MODEM_CHFCOE06_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CHFCOE06 */ +#define _MODEM_CHFCOE06_SET0COEFF13_SHIFT 0 /**< Shift value for MODEM_SET0COEFF13 */ +#define _MODEM_CHFCOE06_SET0COEFF13_MASK 0xFFFFUL /**< Bit mask for MODEM_SET0COEFF13 */ +#define _MODEM_CHFCOE06_SET0COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE06 */ +#define MODEM_CHFCOE06_SET0COEFF13_DEFAULT (_MODEM_CHFCOE06_SET0COEFF13_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE06 */ +#define _MODEM_CHFCOE06_SET0COEFF14_SHIFT 16 /**< Shift value for MODEM_SET0COEFF14 */ +#define _MODEM_CHFCOE06_SET0COEFF14_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SET0COEFF14 */ +#define _MODEM_CHFCOE06_SET0COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE06 */ +#define MODEM_CHFCOE06_SET0COEFF14_DEFAULT (_MODEM_CHFCOE06_SET0COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CHFCOE06 */ + +/* Bit fields for MODEM CHFCOE10 */ +#define _MODEM_CHFCOE10_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE10 */ +#define _MODEM_CHFCOE10_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE10 */ +#define _MODEM_CHFCOE10_SET1COEFF0_SHIFT 0 /**< Shift value for MODEM_SET1COEFF0 */ +#define _MODEM_CHFCOE10_SET1COEFF0_MASK 0x3FFUL /**< Bit mask for MODEM_SET1COEFF0 */ +#define _MODEM_CHFCOE10_SET1COEFF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */ +#define MODEM_CHFCOE10_SET1COEFF0_DEFAULT (_MODEM_CHFCOE10_SET1COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */ +#define _MODEM_CHFCOE10_SET1COEFF1_SHIFT 10 /**< Shift value for MODEM_SET1COEFF1 */ +#define _MODEM_CHFCOE10_SET1COEFF1_MASK 0xFFC00UL /**< Bit mask for MODEM_SET1COEFF1 */ +#define _MODEM_CHFCOE10_SET1COEFF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */ +#define MODEM_CHFCOE10_SET1COEFF1_DEFAULT (_MODEM_CHFCOE10_SET1COEFF1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */ +#define _MODEM_CHFCOE10_SET1COEFF2_SHIFT 20 /**< Shift value for MODEM_SET1COEFF2 */ +#define _MODEM_CHFCOE10_SET1COEFF2_MASK 0x3FF00000UL /**< Bit mask for MODEM_SET1COEFF2 */ +#define _MODEM_CHFCOE10_SET1COEFF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */ +#define MODEM_CHFCOE10_SET1COEFF2_DEFAULT (_MODEM_CHFCOE10_SET1COEFF2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */ + +/* Bit fields for MODEM CHFCOE11 */ +#define _MODEM_CHFCOE11_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE11 */ +#define _MODEM_CHFCOE11_MASK 0x003FFFFFUL /**< Mask for MODEM_CHFCOE11 */ +#define _MODEM_CHFCOE11_SET1COEFF3_SHIFT 0 /**< Shift value for MODEM_SET1COEFF3 */ +#define _MODEM_CHFCOE11_SET1COEFF3_MASK 0x7FFUL /**< Bit mask for MODEM_SET1COEFF3 */ +#define _MODEM_CHFCOE11_SET1COEFF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE11 */ +#define MODEM_CHFCOE11_SET1COEFF3_DEFAULT (_MODEM_CHFCOE11_SET1COEFF3_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE11 */ +#define _MODEM_CHFCOE11_SET1COEFF4_SHIFT 11 /**< Shift value for MODEM_SET1COEFF4 */ +#define _MODEM_CHFCOE11_SET1COEFF4_MASK 0x3FF800UL /**< Bit mask for MODEM_SET1COEFF4 */ +#define _MODEM_CHFCOE11_SET1COEFF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE11 */ +#define MODEM_CHFCOE11_SET1COEFF4_DEFAULT (_MODEM_CHFCOE11_SET1COEFF4_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE11 */ + +/* Bit fields for MODEM CHFCOE12 */ +#define _MODEM_CHFCOE12_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE12 */ +#define _MODEM_CHFCOE12_MASK 0x007FFFFFUL /**< Mask for MODEM_CHFCOE12 */ +#define _MODEM_CHFCOE12_SET1COEFF5_SHIFT 0 /**< Shift value for MODEM_SET1COEFF5 */ +#define _MODEM_CHFCOE12_SET1COEFF5_MASK 0x7FFUL /**< Bit mask for MODEM_SET1COEFF5 */ +#define _MODEM_CHFCOE12_SET1COEFF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE12 */ +#define MODEM_CHFCOE12_SET1COEFF5_DEFAULT (_MODEM_CHFCOE12_SET1COEFF5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE12 */ +#define _MODEM_CHFCOE12_SET1COEFF6_SHIFT 11 /**< Shift value for MODEM_SET1COEFF6 */ +#define _MODEM_CHFCOE12_SET1COEFF6_MASK 0x7FF800UL /**< Bit mask for MODEM_SET1COEFF6 */ +#define _MODEM_CHFCOE12_SET1COEFF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE12 */ +#define MODEM_CHFCOE12_SET1COEFF6_DEFAULT (_MODEM_CHFCOE12_SET1COEFF6_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE12 */ + +/* Bit fields for MODEM CHFCOE13 */ +#define _MODEM_CHFCOE13_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE13 */ +#define _MODEM_CHFCOE13_MASK 0x00FFFFFFUL /**< Mask for MODEM_CHFCOE13 */ +#define _MODEM_CHFCOE13_SET1COEFF7_SHIFT 0 /**< Shift value for MODEM_SET1COEFF7 */ +#define _MODEM_CHFCOE13_SET1COEFF7_MASK 0xFFFUL /**< Bit mask for MODEM_SET1COEFF7 */ +#define _MODEM_CHFCOE13_SET1COEFF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE13 */ +#define MODEM_CHFCOE13_SET1COEFF7_DEFAULT (_MODEM_CHFCOE13_SET1COEFF7_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE13 */ +#define _MODEM_CHFCOE13_SET1COEFF8_SHIFT 12 /**< Shift value for MODEM_SET1COEFF8 */ +#define _MODEM_CHFCOE13_SET1COEFF8_MASK 0xFFF000UL /**< Bit mask for MODEM_SET1COEFF8 */ +#define _MODEM_CHFCOE13_SET1COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE13 */ +#define MODEM_CHFCOE13_SET1COEFF8_DEFAULT (_MODEM_CHFCOE13_SET1COEFF8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CHFCOE13 */ + +/* Bit fields for MODEM CHFCOE14 */ +#define _MODEM_CHFCOE14_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE14 */ +#define _MODEM_CHFCOE14_MASK 0x0FFFFFFFUL /**< Mask for MODEM_CHFCOE14 */ +#define _MODEM_CHFCOE14_SET1COEFF9_SHIFT 0 /**< Shift value for MODEM_SET1COEFF9 */ +#define _MODEM_CHFCOE14_SET1COEFF9_MASK 0x3FFFUL /**< Bit mask for MODEM_SET1COEFF9 */ +#define _MODEM_CHFCOE14_SET1COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE14 */ +#define MODEM_CHFCOE14_SET1COEFF9_DEFAULT (_MODEM_CHFCOE14_SET1COEFF9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE14 */ +#define _MODEM_CHFCOE14_SET1COEFF10_SHIFT 14 /**< Shift value for MODEM_SET1COEFF10 */ +#define _MODEM_CHFCOE14_SET1COEFF10_MASK 0xFFFC000UL /**< Bit mask for MODEM_SET1COEFF10 */ +#define _MODEM_CHFCOE14_SET1COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE14 */ +#define MODEM_CHFCOE14_SET1COEFF10_DEFAULT (_MODEM_CHFCOE14_SET1COEFF10_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE14 */ + +/* Bit fields for MODEM CHFCOE15 */ +#define _MODEM_CHFCOE15_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE15 */ +#define _MODEM_CHFCOE15_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE15 */ +#define _MODEM_CHFCOE15_SET1COEFF11_SHIFT 0 /**< Shift value for MODEM_SET1COEFF11 */ +#define _MODEM_CHFCOE15_SET1COEFF11_MASK 0x3FFFUL /**< Bit mask for MODEM_SET1COEFF11 */ +#define _MODEM_CHFCOE15_SET1COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE15 */ +#define MODEM_CHFCOE15_SET1COEFF11_DEFAULT (_MODEM_CHFCOE15_SET1COEFF11_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE15 */ +#define _MODEM_CHFCOE15_SET1COEFF12_SHIFT 14 /**< Shift value for MODEM_SET1COEFF12 */ +#define _MODEM_CHFCOE15_SET1COEFF12_MASK 0x3FFFC000UL /**< Bit mask for MODEM_SET1COEFF12 */ +#define _MODEM_CHFCOE15_SET1COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE15 */ +#define MODEM_CHFCOE15_SET1COEFF12_DEFAULT (_MODEM_CHFCOE15_SET1COEFF12_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE15 */ + +/* Bit fields for MODEM CHFCOE16 */ +#define _MODEM_CHFCOE16_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE16 */ +#define _MODEM_CHFCOE16_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CHFCOE16 */ +#define _MODEM_CHFCOE16_SET1COEFF13_SHIFT 0 /**< Shift value for MODEM_SET1COEFF13 */ +#define _MODEM_CHFCOE16_SET1COEFF13_MASK 0xFFFFUL /**< Bit mask for MODEM_SET1COEFF13 */ +#define _MODEM_CHFCOE16_SET1COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE16 */ +#define MODEM_CHFCOE16_SET1COEFF13_DEFAULT (_MODEM_CHFCOE16_SET1COEFF13_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE16 */ +#define _MODEM_CHFCOE16_SET1COEFF14_SHIFT 16 /**< Shift value for MODEM_SET1COEFF14 */ +#define _MODEM_CHFCOE16_SET1COEFF14_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SET1COEFF14 */ +#define _MODEM_CHFCOE16_SET1COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE16 */ +#define MODEM_CHFCOE16_SET1COEFF14_DEFAULT (_MODEM_CHFCOE16_SET1COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CHFCOE16 */ + +/* Bit fields for MODEM CHFCTRL */ +#define _MODEM_CHFCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_MASK 0xB0000003UL /**< Mask for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_FWSWCOEFFEN (0x1UL << 0) /**< FW Switch CHF COE. Enable */ +#define _MODEM_CHFCTRL_FWSWCOEFFEN_SHIFT 0 /**< Shift value for MODEM_FWSWCOEFFEN */ +#define _MODEM_CHFCTRL_FWSWCOEFFEN_MASK 0x1UL /**< Bit mask for MODEM_FWSWCOEFFEN */ +#define _MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT (_MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_FWSELCOEFF (0x1UL << 1) /**< FW Select CHF COE. set */ +#define _MODEM_CHFCTRL_FWSELCOEFF_SHIFT 1 /**< Shift value for MODEM_FWSELCOEFF */ +#define _MODEM_CHFCTRL_FWSELCOEFF_MASK 0x2UL /**< Bit mask for MODEM_FWSELCOEFF */ +#define _MODEM_CHFCTRL_FWSELCOEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_FWSELCOEFF_DEFAULT (_MODEM_CHFCTRL_FWSELCOEFF_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_CHFSWSEL_SHIFT 28 /**< Shift value for MODEM_CHFSWSEL */ +#define _MODEM_CHFCTRL_CHFSWSEL_MASK 0x30000000UL /**< Bit mask for MODEM_CHFSWSEL */ +#define _MODEM_CHFCTRL_CHFSWSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_CHFSWSEL_PREDET 0x00000000UL /**< Mode PREDET for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_CHFSWSEL_FRC_SUP 0x00000001UL /**< Mode FRC_SUP for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG 0x00000002UL /**< Mode CHFSWTRIG for MODEM_CHFCTRL */ +#define _MODEM_CHFCTRL_CHFSWSEL_INVALID 0x00000003UL /**< Mode INVALID for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_CHFSWSEL_DEFAULT (_MODEM_CHFCTRL_CHFSWSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_CHFSWSEL_PREDET (_MODEM_CHFCTRL_CHFSWSEL_PREDET << 28) /**< Shifted mode PREDET for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_CHFSWSEL_FRC_SUP (_MODEM_CHFCTRL_CHFSWSEL_FRC_SUP << 28) /**< Shifted mode FRC_SUP for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG (_MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG << 28) /**< Shifted mode CHFSWTRIG for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_CHFSWSEL_INVALID (_MODEM_CHFCTRL_CHFSWSEL_INVALID << 28) /**< Shifted mode INVALID for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_SWCOEFFEN (0x1UL << 31) /**< Switch CHF COE. Enable */ +#define _MODEM_CHFCTRL_SWCOEFFEN_SHIFT 31 /**< Shift value for MODEM_SWCOEFFEN */ +#define _MODEM_CHFCTRL_SWCOEFFEN_MASK 0x80000000UL /**< Bit mask for MODEM_SWCOEFFEN */ +#define _MODEM_CHFCTRL_SWCOEFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */ +#define MODEM_CHFCTRL_SWCOEFFEN_DEFAULT (_MODEM_CHFCTRL_SWCOEFFEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */ + +/* Bit fields for MODEM CHFLATENCYCTRL */ +#define _MODEM_CHFLATENCYCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFLATENCYCTRL */ +#define _MODEM_CHFLATENCYCTRL_MASK 0x00000003UL /**< Mask for MODEM_CHFLATENCYCTRL */ +#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_SHIFT 0 /**< Shift value for MODEM_CHFLATENCY */ +#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_MASK 0x3UL /**< Bit mask for MODEM_CHFLATENCY */ +#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFLATENCYCTRL */ +#define MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT (_MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFLATENCYCTRL*/ + +/* Bit fields for MODEM FRMSCHTIME */ +#define _MODEM_FRMSCHTIME_RESETVALUE 0x00000040UL /**< Default value for MODEM_FRMSCHTIME */ +#define _MODEM_FRMSCHTIME_MASK 0xE000FFFFUL /**< Mask for MODEM_FRMSCHTIME */ +#define _MODEM_FRMSCHTIME_FRMSCHTIME_SHIFT 0 /**< Shift value for MODEM_FRMSCHTIME */ +#define _MODEM_FRMSCHTIME_FRMSCHTIME_MASK 0xFFFFUL /**< Bit mask for MODEM_FRMSCHTIME */ +#define _MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT 0x00000040UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT (_MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_PMRSTSYCNEN (0x1UL << 29) /**< ENABLE CLEAN SYNC */ +#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_SHIFT 29 /**< Shift value for MODEM_PMRSTSYCNEN */ +#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_MASK 0x20000000UL /**< Bit mask for MODEM_PMRSTSYCNEN */ +#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT (_MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_DSARSTSYCNEN (0x1UL << 30) /**< ENABLE CLEAN SYNC */ +#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_SHIFT 30 /**< Shift value for MODEM_DSARSTSYCNEN */ +#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_MASK 0x40000000UL /**< Bit mask for MODEM_DSARSTSYCNEN */ +#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT (_MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_PMENDSCHEN (0x1UL << 31) /**< EnABLE SCH PM END */ +#define _MODEM_FRMSCHTIME_PMENDSCHEN_SHIFT 31 /**< Shift value for MODEM_PMENDSCHEN */ +#define _MODEM_FRMSCHTIME_PMENDSCHEN_MASK 0x80000000UL /**< Bit mask for MODEM_PMENDSCHEN */ +#define _MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */ +#define MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT (_MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */ + +/* Bit fields for MODEM PREFILTCOEFF */ +#define _MODEM_PREFILTCOEFF_RESETVALUE 0x3B3B3B3BUL /**< Default value for MODEM_PREFILTCOEFF */ +#define _MODEM_PREFILTCOEFF_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PREFILTCOEFF */ +#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_SHIFT 0 /**< Shift value for MODEM_PREFILTCOEFF */ +#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_PREFILTCOEFF */ +#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT 0x3B3B3B3BUL /**< Mode DEFAULT for MODEM_PREFILTCOEFF */ +#define MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT (_MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PREFILTCOEFF */ + +/* Bit fields for MODEM RXRESTART */ +#define _MODEM_RXRESTART_RESETVALUE 0x00001860UL /**< Default value for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_MASK 0xC0011FF1UL /**< Mask for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTUPONMARSSI (0x1UL << 0) /**< Restart RX upon RSSI MA above threshold */ +#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_SHIFT 0 /**< Shift value for MODEM_RXRESTARTUPONMARSSI */ +#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_MASK 0x1UL /**< Bit mask for MODEM_RXRESTARTUPONMARSSI */ +#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT (_MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_SHIFT 4 /**< Shift value for MODEM_RXRESTARTMATHRESHOLD */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_MASK 0xF0UL /**< Bit mask for MODEM_RXRESTARTMATHRESHOLD */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 0x00000000UL /**< Mode DB0 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 0x00000001UL /**< Mode DB1 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 0x00000002UL /**< Mode DB2 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 0x00000003UL /**< Mode DB3 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 0x00000004UL /**< Mode DB4 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 0x00000005UL /**< Mode DB5 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 0x00000006UL /**< Mode DB6 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 0x00000007UL /**< Mode DB7 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 0x00000008UL /**< Mode DB8 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 0x00000009UL /**< Mode DB9 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 0x0000000AUL /**< Mode DB10 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 0x0000000BUL /**< Mode DB11 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 0x0000000CUL /**< Mode DB12 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 0x0000000DUL /**< Mode DB13 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 0x0000000EUL /**< Mode DB14 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 0x0000000FUL /**< Mode DB15 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 << 4) /**< Shifted mode DB0 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 << 4) /**< Shifted mode DB1 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 << 4) /**< Shifted mode DB2 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 << 4) /**< Shifted mode DB3 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 << 4) /**< Shifted mode DB4 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 << 4) /**< Shifted mode DB5 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 << 4) /**< Shifted mode DB6 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 << 4) /**< Shifted mode DB7 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 << 4) /**< Shifted mode DB8 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 << 4) /**< Shifted mode DB9 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 << 4) /**< Shifted mode DB10 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 << 4) /**< Shifted mode DB11 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 << 4) /**< Shifted mode DB12 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 << 4) /**< Shifted mode DB13 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 << 4) /**< Shifted mode DB14 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 << 4) /**< Shifted mode DB15 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_SHIFT 8 /**< Shift value for MODEM_RXRESTARTMALATCHSEL */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_MASK 0x300UL /**< Bit mask for MODEM_RXRESTARTMALATCHSEL */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET 0x00000000UL /**< Mode RE_PRE_DET for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET 0x00000001UL /**< Mode RE_SYNC_DET for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 0x00000002UL /**< Mode EITHER1 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 0x00000003UL /**< Mode EITHER2 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET << 8) /**< Shifted mode RE_PRE_DET for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET << 8) /**< Shifted mode RE_SYNC_DET for MODEM_RXRESTART*/ +#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 << 8) /**< Shifted mode EITHER1 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 << 8) /**< Shifted mode EITHER2 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_SHIFT 10 /**< Shift value for MODEM_RXRESTARTMACOMPENSEL */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_MASK 0xC00UL /**< Bit mask for MODEM_RXRESTARTMACOMPENSEL */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET 0x00000000UL /**< Mode PRE_DET for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET 0x00000001UL /**< Mode FRAME_SYNC_DET for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 0x00000002UL /**< Mode BOTH1 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 0x00000003UL /**< Mode BOTH2 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET << 10) /**< Shifted mode PRE_DET for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET << 10) /**< Shifted mode FRAME_SYNC_DET for MODEM_RXRESTART*/ +#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 << 10) /**< Shifted mode BOTH1 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 << 10) /**< Shifted mode BOTH2 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATAP (0x1UL << 12) /**< Number of taps for the MA filter */ +#define _MODEM_RXRESTART_RXRESTARTMATAP_SHIFT 12 /**< Shift value for MODEM_RXRESTARTMATAP */ +#define _MODEM_RXRESTART_RXRESTARTMATAP_MASK 0x1000UL /**< Bit mask for MODEM_RXRESTARTMATAP */ +#define _MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 0x00000000UL /**< Mode TAPS4 for MODEM_RXRESTART */ +#define _MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 0x00000001UL /**< Mode TAPS8 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT (_MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 (_MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 << 12) /**< Shifted mode TAPS4 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 (_MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 << 12) /**< Shifted mode TAPS8 for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTB4PREDET (0x1UL << 16) /**< whether to restart RX before pre det */ +#define _MODEM_RXRESTART_RXRESTARTB4PREDET_SHIFT 16 /**< Shift value for MODEM_RXRESTARTB4PREDET */ +#define _MODEM_RXRESTART_RXRESTARTB4PREDET_MASK 0x10000UL /**< Bit mask for MODEM_RXRESTARTB4PREDET */ +#define _MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT (_MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_ANTSWRSTFLTTDIS (0x1UL << 30) /**< ANT SW RESET Filter Disable */ +#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_SHIFT 30 /**< Shift value for MODEM_ANTSWRSTFLTTDIS */ +#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_MASK 0x40000000UL /**< Bit mask for MODEM_ANTSWRSTFLTTDIS */ +#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT (_MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_FLTRSTEN (0x1UL << 31) /**< RX Chain Filter reset enable */ +#define _MODEM_RXRESTART_FLTRSTEN_SHIFT 31 /**< Shift value for MODEM_FLTRSTEN */ +#define _MODEM_RXRESTART_FLTRSTEN_MASK 0x80000000UL /**< Bit mask for MODEM_FLTRSTEN */ +#define _MODEM_RXRESTART_FLTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */ +#define MODEM_RXRESTART_FLTRSTEN_DEFAULT (_MODEM_RXRESTART_FLTRSTEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_RXRESTART */ + +/* Bit fields for MODEM SQ */ +#define _MODEM_SQ_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQ */ +#define _MODEM_SQ_MASK 0xFFFF0003UL /**< Mask for MODEM_SQ */ +#define MODEM_SQ_SQEN (0x1UL << 0) /**< SQ enable */ +#define _MODEM_SQ_SQEN_SHIFT 0 /**< Shift value for MODEM_SQEN */ +#define _MODEM_SQ_SQEN_MASK 0x1UL /**< Bit mask for MODEM_SQEN */ +#define _MODEM_SQ_SQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */ +#define MODEM_SQ_SQEN_DEFAULT (_MODEM_SQ_SQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQ */ +#define MODEM_SQ_SQSWRST (0x1UL << 1) /**< SQ hold demod */ +#define _MODEM_SQ_SQSWRST_SHIFT 1 /**< Shift value for MODEM_SQSWRST */ +#define _MODEM_SQ_SQSWRST_MASK 0x2UL /**< Bit mask for MODEM_SQSWRST */ +#define _MODEM_SQ_SQSWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */ +#define MODEM_SQ_SQSWRST_DEFAULT (_MODEM_SQ_SQSWRST_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SQ */ +#define _MODEM_SQ_SQTIMOUT_SHIFT 16 /**< Shift value for MODEM_SQTIMOUT */ +#define _MODEM_SQ_SQTIMOUT_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SQTIMOUT */ +#define _MODEM_SQ_SQTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */ +#define MODEM_SQ_SQTIMOUT_DEFAULT (_MODEM_SQ_SQTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQ */ + +/* Bit fields for MODEM SQEXT */ +#define _MODEM_SQEXT_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQEXT */ +#define _MODEM_SQEXT_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SQEXT */ +#define _MODEM_SQEXT_SQSTG2TIMOUT_SHIFT 0 /**< Shift value for MODEM_SQSTG2TIMOUT */ +#define _MODEM_SQEXT_SQSTG2TIMOUT_MASK 0xFFFFUL /**< Bit mask for MODEM_SQSTG2TIMOUT */ +#define _MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQEXT */ +#define MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT (_MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQEXT */ +#define _MODEM_SQEXT_SQSTG3TIMOUT_SHIFT 16 /**< Shift value for MODEM_SQSTG3TIMOUT */ +#define _MODEM_SQEXT_SQSTG3TIMOUT_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SQSTG3TIMOUT */ +#define _MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQEXT */ +#define MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT (_MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQEXT */ + +/* Bit fields for MODEM SQI */ +#define _MODEM_SQI_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQI */ +#define _MODEM_SQI_MASK 0x00FF0001UL /**< Mask for MODEM_SQI */ +#define MODEM_SQI_SQISELECT (0x1UL << 0) /**< SQI selection bit */ +#define _MODEM_SQI_SQISELECT_SHIFT 0 /**< Shift value for MODEM_SQISELECT */ +#define _MODEM_SQI_SQISELECT_MASK 0x1UL /**< Bit mask for MODEM_SQISELECT */ +#define _MODEM_SQI_SQISELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQI */ +#define _MODEM_SQI_SQISELECT_CORR 0x00000000UL /**< Mode CORR for MODEM_SQI */ +#define _MODEM_SQI_SQISELECT_ERROR 0x00000001UL /**< Mode ERROR for MODEM_SQI */ +#define MODEM_SQI_SQISELECT_DEFAULT (_MODEM_SQI_SQISELECT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQI */ +#define MODEM_SQI_SQISELECT_CORR (_MODEM_SQI_SQISELECT_CORR << 0) /**< Shifted mode CORR for MODEM_SQI */ +#define MODEM_SQI_SQISELECT_ERROR (_MODEM_SQI_SQISELECT_ERROR << 0) /**< Shifted mode ERROR for MODEM_SQI */ +#define _MODEM_SQI_CHIPERROR_SHIFT 16 /**< Shift value for MODEM_CHIPERROR */ +#define _MODEM_SQI_CHIPERROR_MASK 0xFF0000UL /**< Bit mask for MODEM_CHIPERROR */ +#define _MODEM_SQI_CHIPERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQI */ +#define MODEM_SQI_CHIPERROR_DEFAULT (_MODEM_SQI_CHIPERROR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQI */ + +/* Bit fields for MODEM ANTDIVCTRL */ +#define _MODEM_ANTDIVCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTDIVCTRL */ +#define _MODEM_ANTDIVCTRL_MASK 0x000007FFUL /**< Mask for MODEM_ANTDIVCTRL */ +#define _MODEM_ANTDIVCTRL_ADPRETHRESH_SHIFT 0 /**< Shift value for MODEM_ADPRETHRESH */ +#define _MODEM_ANTDIVCTRL_ADPRETHRESH_MASK 0xFFUL /**< Bit mask for MODEM_ADPRETHRESH */ +#define _MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT (_MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ENADPRETHRESH (0x1UL << 8) /**< Enable Preamble threshold */ +#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_SHIFT 8 /**< Shift value for MODEM_ENADPRETHRESH */ +#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_MASK 0x100UL /**< Bit mask for MODEM_ENADPRETHRESH */ +#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */ +#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ANTDIVCTRL */ +#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT (_MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE (_MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE << 8) /**< Shifted mode DISABLE for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE (_MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE << 8) /**< Shifted mode ENABLE for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ANTDIVDISCCA (0x1UL << 9) /**< Antenna switch disable for CSMA */ +#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_SHIFT 9 /**< Shift value for MODEM_ANTDIVDISCCA */ +#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_MASK 0x200UL /**< Bit mask for MODEM_ANTDIVDISCCA */ +#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT (_MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ANTDIVSELCCA (0x1UL << 10) /**< Antenna switch selection for CSMA */ +#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_SHIFT 10 /**< Shift value for MODEM_ANTDIVSELCCA */ +#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_MASK 0x400UL /**< Bit mask for MODEM_ANTDIVSELCCA */ +#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */ +#define MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT (_MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */ + +/* Bit fields for MODEM ANTDIVFW */ +#define _MODEM_ANTDIVFW_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTDIVFW */ +#define _MODEM_ANTDIVFW_MASK 0x80000003UL /**< Mask for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWSELANT (0x1UL << 0) /**< FW antenna selection */ +#define _MODEM_ANTDIVFW_FWSELANT_SHIFT 0 /**< Shift value for MODEM_FWSELANT */ +#define _MODEM_ANTDIVFW_FWSELANT_MASK 0x1UL /**< Bit mask for MODEM_FWSELANT */ +#define _MODEM_ANTDIVFW_FWSELANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWSELANT_DEFAULT (_MODEM_ANTDIVFW_FWSELANT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWANTSWCMD (0x1UL << 1) /**< FW Antenna SW cmd */ +#define _MODEM_ANTDIVFW_FWANTSWCMD_SHIFT 1 /**< Shift value for MODEM_FWANTSWCMD */ +#define _MODEM_ANTDIVFW_FWANTSWCMD_MASK 0x2UL /**< Bit mask for MODEM_FWANTSWCMD */ +#define _MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT (_MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWANTDIVEN (0x1UL << 31) /**< Enable FW ANT-DIV mode */ +#define _MODEM_ANTDIVFW_FWANTDIVEN_SHIFT 31 /**< Shift value for MODEM_FWANTDIVEN */ +#define _MODEM_ANTDIVFW_FWANTDIVEN_MASK 0x80000000UL /**< Bit mask for MODEM_FWANTDIVEN */ +#define _MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */ +#define MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT (_MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */ + +/* Bit fields for MODEM PHDMODANTDIV */ +#define _MODEM_PHDMODANTDIV_RESETVALUE 0x0000000FUL /**< Default value for MODEM_PHDMODANTDIV */ +#define _MODEM_PHDMODANTDIV_MASK 0x40FF1FFFUL /**< Mask for MODEM_PHDMODANTDIV */ +#define _MODEM_PHDMODANTDIV_ANTWAIT_SHIFT 0 /**< Shift value for MODEM_ANTWAIT */ +#define _MODEM_PHDMODANTDIV_ANTWAIT_MASK 0x1FUL /**< Bit mask for MODEM_ANTWAIT */ +#define _MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT 0x0000000FUL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */ +#define MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT (_MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */ +#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_SHIFT 5 /**< Shift value for MODEM_SKIPRSSITHD */ +#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_MASK 0x1FE0UL /**< Bit mask for MODEM_SKIPRSSITHD */ +#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */ +#define MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT (_MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */ +#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_SHIFT 16 /**< Shift value for MODEM_SKIPCORRTHD */ +#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_MASK 0xFF0000UL /**< Bit mask for MODEM_SKIPCORRTHD */ +#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */ +#define MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT (_MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */ +#define MODEM_PHDMODANTDIV_SKIP2ANT (0x1UL << 30) /**< SKIP 2th ANTENNA Evaluate */ +#define _MODEM_PHDMODANTDIV_SKIP2ANT_SHIFT 30 /**< Shift value for MODEM_SKIP2ANT */ +#define _MODEM_PHDMODANTDIV_SKIP2ANT_MASK 0x40000000UL /**< Bit mask for MODEM_SKIP2ANT */ +#define _MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */ +#define MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT (_MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */ + +/* Bit fields for MODEM PHANTDECSION */ +#define _MODEM_PHANTDECSION_RESETVALUE 0x00000000UL /**< Default value for MODEM_PHANTDECSION */ +#define _MODEM_PHANTDECSION_MASK 0xF007FFFFUL /**< Mask for MODEM_PHANTDECSION */ +#define _MODEM_PHANTDECSION_CORRANDDIVTHD_SHIFT 0 /**< Shift value for MODEM_CORRANDDIVTHD */ +#define _MODEM_PHANTDECSION_CORRANDDIVTHD_MASK 0x3FFUL /**< Bit mask for MODEM_CORRANDDIVTHD */ +#define _MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT (_MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ +#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_SHIFT 10 /**< Shift value for MODEM_RSSIANDDIVTHD */ +#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_MASK 0x7FC00UL /**< Bit mask for MODEM_RSSIANDDIVTHD */ +#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT (_MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR0 (0x1UL << 28) /**< RSSI-CORR Selection in Region0 */ +#define _MODEM_PHANTDECSION_RSSICORR0_SHIFT 28 /**< Shift value for MODEM_RSSICORR0 */ +#define _MODEM_PHANTDECSION_RSSICORR0_MASK 0x10000000UL /**< Bit mask for MODEM_RSSICORR0 */ +#define _MODEM_PHANTDECSION_RSSICORR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR0_DEFAULT (_MODEM_PHANTDECSION_RSSICORR0_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR1 (0x1UL << 29) /**< RSSI-CORR Selection in Region1 */ +#define _MODEM_PHANTDECSION_RSSICORR1_SHIFT 29 /**< Shift value for MODEM_RSSICORR1 */ +#define _MODEM_PHANTDECSION_RSSICORR1_MASK 0x20000000UL /**< Bit mask for MODEM_RSSICORR1 */ +#define _MODEM_PHANTDECSION_RSSICORR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR1_DEFAULT (_MODEM_PHANTDECSION_RSSICORR1_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR2 (0x1UL << 30) /**< RSSI-CORR Selection in Region2 */ +#define _MODEM_PHANTDECSION_RSSICORR2_SHIFT 30 /**< Shift value for MODEM_RSSICORR2 */ +#define _MODEM_PHANTDECSION_RSSICORR2_MASK 0x40000000UL /**< Bit mask for MODEM_RSSICORR2 */ +#define _MODEM_PHANTDECSION_RSSICORR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR2_DEFAULT (_MODEM_PHANTDECSION_RSSICORR2_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR3 (0x1UL << 31) /**< RSSI-CORR Selection in Region3 */ +#define _MODEM_PHANTDECSION_RSSICORR3_SHIFT 31 /**< Shift value for MODEM_RSSICORR3 */ +#define _MODEM_PHANTDECSION_RSSICORR3_MASK 0x80000000UL /**< Bit mask for MODEM_RSSICORR3 */ +#define _MODEM_PHANTDECSION_RSSICORR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */ +#define MODEM_PHANTDECSION_RSSICORR3_DEFAULT (_MODEM_PHANTDECSION_RSSICORR3_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */ + +/* Bit fields for MODEM PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_RESETVALUE 0x01DF0004UL /**< Default value for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_PMDETTHD_SHIFT 0 /**< Shift value for MODEM_PMDETTHD */ +#define _MODEM_PHDMODCTRL_PMDETTHD_MASK 0x1FUL /**< Bit mask for MODEM_PMDETTHD */ +#define _MODEM_PHDMODCTRL_PMDETTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMDETTHD_DEFAULT (_MODEM_PHDMODCTRL_PMDETTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_SHIFT 5 /**< Shift value for MODEM_PMTIMLOSTHD */ +#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_MASK 0x1FE0UL /**< Bit mask for MODEM_PMTIMLOSTHD */ +#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT (_MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMTIMLOSEN (0x1UL << 13) /**< Preamble timing loss detection */ +#define _MODEM_PHDMODCTRL_PMTIMLOSEN_SHIFT 13 /**< Shift value for MODEM_PMTIMLOSEN */ +#define _MODEM_PHDMODCTRL_PMTIMLOSEN_MASK 0x2000UL /**< Bit mask for MODEM_PMTIMLOSEN */ +#define _MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT (_MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_RSSIFLTBYP (0x1UL << 14) /**< Bypass RSSI Filering */ +#define _MODEM_PHDMODCTRL_RSSIFLTBYP_SHIFT 14 /**< Shift value for MODEM_RSSIFLTBYP */ +#define _MODEM_PHDMODCTRL_RSSIFLTBYP_MASK 0x4000UL /**< Bit mask for MODEM_RSSIFLTBYP */ +#define _MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT (_MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMDETEN (0x1UL << 15) /**< PREAMBLE DET */ +#define _MODEM_PHDMODCTRL_PMDETEN_SHIFT 15 /**< Shift value for MODEM_PMDETEN */ +#define _MODEM_PHDMODCTRL_PMDETEN_MASK 0x8000UL /**< Bit mask for MODEM_PMDETEN */ +#define _MODEM_PHDMODCTRL_PMDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_PMDETEN_DEFAULT (_MODEM_PHDMODCTRL_PMDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_REMODOSR_SHIFT 16 /**< Shift value for MODEM_REMODOSR */ +#define _MODEM_PHDMODCTRL_REMODOSR_MASK 0x3F0000UL /**< Bit mask for MODEM_REMODOSR */ +#define _MODEM_PHDMODCTRL_REMODOSR_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_REMODOSR_DEFAULT (_MODEM_PHDMODCTRL_REMODOSR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_REMODDWN_SHIFT 22 /**< Shift value for MODEM_REMODDWN */ +#define _MODEM_PHDMODCTRL_REMODDWN_MASK 0x3C00000UL /**< Bit mask for MODEM_REMODDWN */ +#define _MODEM_PHDMODCTRL_REMODDWN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_REMODDWN_DEFAULT (_MODEM_PHDMODCTRL_REMODDWN_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define _MODEM_PHDMODCTRL_REMODOUTSEL_SHIFT 26 /**< Shift value for MODEM_REMODOUTSEL */ +#define _MODEM_PHDMODCTRL_REMODOUTSEL_MASK 0xC000000UL /**< Bit mask for MODEM_REMODOUTSEL */ +#define _MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT (_MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_REMODEN (0x1UL << 28) /**< REMOD ENABLE */ +#define _MODEM_PHDMODCTRL_REMODEN_SHIFT 28 /**< Shift value for MODEM_REMODEN */ +#define _MODEM_PHDMODCTRL_REMODEN_MASK 0x10000000UL /**< Bit mask for MODEM_REMODEN */ +#define _MODEM_PHDMODCTRL_REMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_REMODEN_DEFAULT (_MODEM_PHDMODCTRL_REMODEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRDETECTOR (0x1UL << 29) /**< Enbale BCRDMOD Dtetector ONLY */ +#define _MODEM_PHDMODCTRL_BCRDETECTOR_SHIFT 29 /**< Shift value for MODEM_BCRDETECTOR */ +#define _MODEM_PHDMODCTRL_BCRDETECTOR_MASK 0x20000000UL /**< Bit mask for MODEM_BCRDETECTOR */ +#define _MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT (_MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRTRECSCONC (0x1UL << 30) /**< BCR/LEGACY CONCURRENT MODE */ +#define _MODEM_PHDMODCTRL_BCRTRECSCONC_SHIFT 30 /**< Shift value for MODEM_BCRTRECSCONC */ +#define _MODEM_PHDMODCTRL_BCRTRECSCONC_MASK 0x40000000UL /**< Bit mask for MODEM_BCRTRECSCONC */ +#define _MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT (_MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRLEGACYCONC (0x1UL << 31) /**< BCR/TRECS CONCURRENT MODE */ +#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_SHIFT 31 /**< Shift value for MODEM_BCRLEGACYCONC */ +#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_MASK 0x80000000UL /**< Bit mask for MODEM_BCRLEGACYCONC */ +#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */ +#define MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT (_MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */ + +/* Bit fields for MODEM SICTRL0 */ +#define _MODEM_SICTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MODE_SHIFT 0 /**< Shift value for MODEM_MODE */ +#define _MODEM_SICTRL0_MODE_MASK 0x3UL /**< Bit mask for MODEM_MODE */ +#define _MODEM_SICTRL0_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MODE_ZB 0x00000001UL /**< Mode ZB for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MODE_BLE2 0x00000002UL /**< Mode BLE2 for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_MODE_BLE1 0x00000003UL /**< Mode BLE1 for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_MODE_DEFAULT (_MODEM_SICTRL0_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_MODE_DISABLE (_MODEM_SICTRL0_MODE_DISABLE << 0) /**< Shifted mode DISABLE for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_MODE_ZB (_MODEM_SICTRL0_MODE_ZB << 0) /**< Shifted mode ZB for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_MODE_BLE2 (_MODEM_SICTRL0_MODE_BLE2 << 0) /**< Shifted mode BLE2 for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_MODE_BLE1 (_MODEM_SICTRL0_MODE_BLE1 << 0) /**< Shifted mode BLE1 for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_NOISETHRESH_SHIFT 2 /**< Shift value for MODEM_NOISETHRESH */ +#define _MODEM_SICTRL0_NOISETHRESH_MASK 0x3FCUL /**< Bit mask for MODEM_NOISETHRESH */ +#define _MODEM_SICTRL0_NOISETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_NOISETHRESH_DEFAULT (_MODEM_SICTRL0_NOISETHRESH_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_SHIFT 10 /**< Shift value for MODEM_PEAKNUMTHRESHLW */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_MASK 0x7C00UL /**< Bit mask for MODEM_PEAKNUMTHRESHLW */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT (_MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_SHIFT 15 /**< Shift value for MODEM_PEAKNUMTHRESHSW */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_MASK 0x38000UL /**< Bit mask for MODEM_PEAKNUMTHRESHSW */ +#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT (_MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_SHIFT 18 /**< Shift value for MODEM_SMALLSAMPLETHRESH */ +#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_MASK 0x7C0000UL /**< Bit mask for MODEM_SMALLSAMPLETHRESH */ +#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT (_MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ +#define _MODEM_SICTRL0_FREQNOMINAL_SHIFT 23 /**< Shift value for MODEM_FREQNOMINAL */ +#define _MODEM_SICTRL0_FREQNOMINAL_MASK 0x3F800000UL /**< Bit mask for MODEM_FREQNOMINAL */ +#define _MODEM_SICTRL0_FREQNOMINAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */ +#define MODEM_SICTRL0_FREQNOMINAL_DEFAULT (_MODEM_SICTRL0_FREQNOMINAL_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */ + +/* Bit fields for MODEM SICTRL1 */ +#define _MODEM_SICTRL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_SHIFT 0 /**< Shift value for MODEM_SUPERCHIPTOLERANCE */ +#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_MASK 0x1FUL /**< Bit mask for MODEM_SUPERCHIPTOLERANCE */ +#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT (_MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_SHIFT 5 /**< Shift value for MODEM_SUPERCHIPMEDIAN */ +#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_MASK 0xFE0UL /**< Bit mask for MODEM_SUPERCHIPMEDIAN */ +#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT (_MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_CORRTHRESH_SHIFT 12 /**< Shift value for MODEM_CORRTHRESH */ +#define _MODEM_SICTRL1_CORRTHRESH_MASK 0x7FF000UL /**< Bit mask for MODEM_CORRTHRESH */ +#define _MODEM_SICTRL1_CORRTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_CORRTHRESH_DEFAULT (_MODEM_SICTRL1_CORRTHRESH_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_CORRNUM_SHIFT 23 /**< Shift value for MODEM_CORRNUM */ +#define _MODEM_SICTRL1_CORRNUM_MASK 0x3800000UL /**< Bit mask for MODEM_CORRNUM */ +#define _MODEM_SICTRL1_CORRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_CORRNUM_DEFAULT (_MODEM_SICTRL1_CORRNUM_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_FASTMODE (0x1UL << 26) /**< Zigbee fast mode */ +#define _MODEM_SICTRL1_FASTMODE_SHIFT 26 /**< Shift value for MODEM_FASTMODE */ +#define _MODEM_SICTRL1_FASTMODE_MASK 0x4000000UL /**< Bit mask for MODEM_FASTMODE */ +#define _MODEM_SICTRL1_FASTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_FASTMODE_DEFAULT (_MODEM_SICTRL1_FASTMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ +#define _MODEM_SICTRL1_NARROWPULSETHRESH_SHIFT 27 /**< Shift value for MODEM_NARROWPULSETHRESH */ +#define _MODEM_SICTRL1_NARROWPULSETHRESH_MASK 0xF8000000UL /**< Bit mask for MODEM_NARROWPULSETHRESH */ +#define _MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */ +#define MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT (_MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */ + +/* Bit fields for MODEM SISTATUS */ +#define _MODEM_SISTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_MASK 0x67FFFFFFUL /**< Mask for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_SISTATE_SHIFT 0 /**< Shift value for MODEM_SISTATE */ +#define _MODEM_SISTATUS_SISTATE_MASK 0xFUL /**< Bit mask for MODEM_SISTATE */ +#define _MODEM_SISTATUS_SISTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SISTATE_DEFAULT (_MODEM_SISTATUS_SISTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_NOISE (0x1UL << 4) /**< Noisy short window */ +#define _MODEM_SISTATUS_NOISE_SHIFT 4 /**< Shift value for MODEM_NOISE */ +#define _MODEM_SISTATUS_NOISE_MASK 0x10UL /**< Bit mask for MODEM_NOISE */ +#define _MODEM_SISTATUS_NOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_NOISE_DEFAULT (_MODEM_SISTATUS_NOISE_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_LWPEAKCOUNT_SHIFT 5 /**< Shift value for MODEM_LWPEAKCOUNT */ +#define _MODEM_SISTATUS_LWPEAKCOUNT_MASK 0x3E0UL /**< Bit mask for MODEM_LWPEAKCOUNT */ +#define _MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT (_MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_NARROWCOUNT_SHIFT 10 /**< Shift value for MODEM_NARROWCOUNT */ +#define _MODEM_SISTATUS_NARROWCOUNT_MASK 0x7C00UL /**< Bit mask for MODEM_NARROWCOUNT */ +#define _MODEM_SISTATUS_NARROWCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_NARROWCOUNT_DEFAULT (_MODEM_SISTATUS_NARROWCOUNT_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_TIMELOCK (0x1UL << 15) /**< Timing locked */ +#define _MODEM_SISTATUS_TIMELOCK_SHIFT 15 /**< Shift value for MODEM_TIMELOCK */ +#define _MODEM_SISTATUS_TIMELOCK_MASK 0x8000UL /**< Bit mask for MODEM_TIMELOCK */ +#define _MODEM_SISTATUS_TIMELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_TIMELOCK_DEFAULT (_MODEM_SISTATUS_TIMELOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SUPERCHIPFAIL (0x1UL << 16) /**< Superchip fail */ +#define _MODEM_SISTATUS_SUPERCHIPFAIL_SHIFT 16 /**< Shift value for MODEM_SUPERCHIPFAIL */ +#define _MODEM_SISTATUS_SUPERCHIPFAIL_MASK 0x10000UL /**< Bit mask for MODEM_SUPERCHIPFAIL */ +#define _MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT (_MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SUPERCHIPPASS (0x1UL << 17) /**< Superchip pass */ +#define _MODEM_SISTATUS_SUPERCHIPPASS_SHIFT 17 /**< Shift value for MODEM_SUPERCHIPPASS */ +#define _MODEM_SISTATUS_SUPERCHIPPASS_MASK 0x20000UL /**< Bit mask for MODEM_SUPERCHIPPASS */ +#define _MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT (_MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_TIMEOFFSET_SHIFT 18 /**< Shift value for MODEM_TIMEOFFSET */ +#define _MODEM_SISTATUS_TIMEOFFSET_MASK 0x1C0000UL /**< Bit mask for MODEM_TIMEOFFSET */ +#define _MODEM_SISTATUS_TIMEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_TIMEOFFSET_DEFAULT (_MODEM_SISTATUS_TIMEOFFSET_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define _MODEM_SISTATUS_CORRPASSNUM_SHIFT 21 /**< Shift value for MODEM_CORRPASSNUM */ +#define _MODEM_SISTATUS_CORRPASSNUM_MASK 0x7E00000UL /**< Bit mask for MODEM_CORRPASSNUM */ +#define _MODEM_SISTATUS_CORRPASSNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_CORRPASSNUM_DEFAULT (_MODEM_SISTATUS_CORRPASSNUM_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SNIFFDONE (0x1UL << 29) /**< Sniff done */ +#define _MODEM_SISTATUS_SNIFFDONE_SHIFT 29 /**< Shift value for MODEM_SNIFFDONE */ +#define _MODEM_SISTATUS_SNIFFDONE_MASK 0x20000000UL /**< Bit mask for MODEM_SNIFFDONE */ +#define _MODEM_SISTATUS_SNIFFDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SNIFFDONE_DEFAULT (_MODEM_SISTATUS_SNIFFDONE_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SIDET (0x1UL << 30) /**< Signal detected */ +#define _MODEM_SISTATUS_SIDET_SHIFT 30 /**< Shift value for MODEM_SIDET */ +#define _MODEM_SISTATUS_SIDET_MASK 0x40000000UL /**< Bit mask for MODEM_SIDET */ +#define _MODEM_SISTATUS_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */ +#define MODEM_SISTATUS_SIDET_DEFAULT (_MODEM_SISTATUS_SIDET_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_SISTATUS */ + +/* Bit fields for MODEM CFGANTPATTEXT */ +#define _MODEM_CFGANTPATTEXT_RESETVALUE 0x00000000UL /**< Default value for MODEM_CFGANTPATTEXT */ +#define _MODEM_CFGANTPATTEXT_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CFGANTPATTEXT */ +#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_SHIFT 0 /**< Shift value for MODEM_CFGANTPATTVALEXT */ +#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_MASK 0x3FFFFFFFUL /**< Bit mask for MODEM_CFGANTPATTVALEXT */ +#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CFGANTPATTEXT */ +#define MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT (_MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CFGANTPATTEXT*/ + +/* Bit fields for MODEM SICTRL2 */ +#define _MODEM_SICTRL2_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL2 */ +#define _MODEM_SICTRL2_MASK 0x000000FFUL /**< Mask for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTAGCMODE (0x1UL << 0) /**< SI reset by AGC */ +#define _MODEM_SICTRL2_SIRSTAGCMODE_SHIFT 0 /**< Shift value for MODEM_SIRSTAGCMODE */ +#define _MODEM_SICTRL2_SIRSTAGCMODE_MASK 0x1UL /**< Bit mask for MODEM_SIRSTAGCMODE */ +#define _MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT (_MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTPRSMODE (0x1UL << 1) /**< SI reset by PRS PAEN */ +#define _MODEM_SICTRL2_SIRSTPRSMODE_SHIFT 1 /**< Shift value for MODEM_SIRSTPRSMODE */ +#define _MODEM_SICTRL2_SIRSTPRSMODE_MASK 0x2UL /**< Bit mask for MODEM_SIRSTPRSMODE */ +#define _MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT (_MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTCCAMODE (0x1UL << 2) /**< SI reset by CCA req */ +#define _MODEM_SICTRL2_SIRSTCCAMODE_SHIFT 2 /**< Shift value for MODEM_SIRSTCCAMODE */ +#define _MODEM_SICTRL2_SIRSTCCAMODE_MASK 0x4UL /**< Bit mask for MODEM_SIRSTCCAMODE */ +#define _MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT (_MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ +#define _MODEM_SICTRL2_SUPERCHIPTHRESH_SHIFT 3 /**< Shift value for MODEM_SUPERCHIPTHRESH */ +#define _MODEM_SICTRL2_SUPERCHIPTHRESH_MASK 0x38UL /**< Bit mask for MODEM_SUPERCHIPTHRESH */ +#define _MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT (_MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_DISSIFRAMEDET (0x1UL << 6) /**< Disable SI when framedet */ +#define _MODEM_SICTRL2_DISSIFRAMEDET_SHIFT 6 /**< Shift value for MODEM_DISSIFRAMEDET */ +#define _MODEM_SICTRL2_DISSIFRAMEDET_MASK 0x40UL /**< Bit mask for MODEM_DISSIFRAMEDET */ +#define _MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT (_MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_AGCRSTUPONSI (0x1UL << 7) /**< AGC reset on SI reset */ +#define _MODEM_SICTRL2_AGCRSTUPONSI_SHIFT 7 /**< Shift value for MODEM_AGCRSTUPONSI */ +#define _MODEM_SICTRL2_AGCRSTUPONSI_MASK 0x80UL /**< Bit mask for MODEM_AGCRSTUPONSI */ +#define _MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */ +#define MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT (_MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */ + +/* Bit fields for MODEM CHFSWCTRL */ +#define _MODEM_CHFSWCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFSWCTRL */ +#define _MODEM_CHFSWCTRL_MASK 0x0003FFFFUL /**< Mask for MODEM_CHFSWCTRL */ +#define _MODEM_CHFSWCTRL_CHFSWTIME_SHIFT 0 /**< Shift value for MODEM_CHFSWTIME */ +#define _MODEM_CHFSWCTRL_CHFSWTIME_MASK 0x3FFFFUL /**< Bit mask for MODEM_CHFSWTIME */ +#define _MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFSWCTRL */ +#define MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT (_MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFSWCTRL */ + +/* Bit fields for MODEM IRCAL */ +#define _MODEM_IRCAL_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCAL */ +#define _MODEM_IRCAL_MASK 0x0000FFBFUL /**< Mask for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALEN (0x1UL << 0) /**< IRCAL enable bit */ +#define _MODEM_IRCAL_IRCALEN_SHIFT 0 /**< Shift value for MODEM_IRCALEN */ +#define _MODEM_IRCAL_IRCALEN_MASK 0x1UL /**< Bit mask for MODEM_IRCALEN */ +#define _MODEM_IRCAL_IRCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALEN_DEFAULT (_MODEM_IRCAL_IRCALEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCAL */ +#define _MODEM_IRCAL_MURSHF_SHIFT 1 /**< Shift value for MODEM_MURSHF */ +#define _MODEM_IRCAL_MURSHF_MASK 0x3EUL /**< Bit mask for MODEM_MURSHF */ +#define _MODEM_IRCAL_MURSHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_MURSHF_DEFAULT (_MODEM_IRCAL_MURSHF_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IRCAL */ +#define _MODEM_IRCAL_MUISHF_SHIFT 7 /**< Shift value for MODEM_MUISHF */ +#define _MODEM_IRCAL_MUISHF_MASK 0x1F80UL /**< Bit mask for MODEM_MUISHF */ +#define _MODEM_IRCAL_MUISHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_MUISHF_DEFAULT (_MODEM_IRCAL_MUISHF_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCORREN (0x1UL << 13) /**< IR Correction enable bit */ +#define _MODEM_IRCAL_IRCORREN_SHIFT 13 /**< Shift value for MODEM_IRCORREN */ +#define _MODEM_IRCAL_IRCORREN_MASK 0x2000UL /**< Bit mask for MODEM_IRCORREN */ +#define _MODEM_IRCAL_IRCORREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCORREN_DEFAULT (_MODEM_IRCAL_IRCORREN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALCOEFRSTCMD (0x1UL << 14) /**< IRCAL coef reset cmd */ +#define _MODEM_IRCAL_IRCALCOEFRSTCMD_SHIFT 14 /**< Shift value for MODEM_IRCALCOEFRSTCMD */ +#define _MODEM_IRCAL_IRCALCOEFRSTCMD_MASK 0x4000UL /**< Bit mask for MODEM_IRCALCOEFRSTCMD */ +#define _MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT (_MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALIFADCDBG (0x1UL << 15) /**< IRCAL IFADC DBG */ +#define _MODEM_IRCAL_IRCALIFADCDBG_SHIFT 15 /**< Shift value for MODEM_IRCALIFADCDBG */ +#define _MODEM_IRCAL_IRCALIFADCDBG_MASK 0x8000UL /**< Bit mask for MODEM_IRCALIFADCDBG */ +#define _MODEM_IRCAL_IRCALIFADCDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */ +#define MODEM_IRCAL_IRCALIFADCDBG_DEFAULT (_MODEM_IRCAL_IRCALIFADCDBG_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IRCAL */ + +/* Bit fields for MODEM IRCALCOEF */ +#define _MODEM_IRCALCOEF_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCALCOEF */ +#define _MODEM_IRCALCOEF_MASK 0x7FFF7FFFUL /**< Mask for MODEM_IRCALCOEF */ +#define _MODEM_IRCALCOEF_CRV_SHIFT 0 /**< Shift value for MODEM_CRV */ +#define _MODEM_IRCALCOEF_CRV_MASK 0x7FFFUL /**< Bit mask for MODEM_CRV */ +#define _MODEM_IRCALCOEF_CRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEF */ +#define MODEM_IRCALCOEF_CRV_DEFAULT (_MODEM_IRCALCOEF_CRV_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCALCOEF */ +#define _MODEM_IRCALCOEF_CIV_SHIFT 16 /**< Shift value for MODEM_CIV */ +#define _MODEM_IRCALCOEF_CIV_MASK 0x7FFF0000UL /**< Bit mask for MODEM_CIV */ +#define _MODEM_IRCALCOEF_CIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEF */ +#define MODEM_IRCALCOEF_CIV_DEFAULT (_MODEM_IRCALCOEF_CIV_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IRCALCOEF */ + +/* Bit fields for MODEM IRCALCOEFWR */ +#define _MODEM_IRCALCOEFWR_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCALCOEFWR */ +#define _MODEM_IRCALCOEFWR_MASK 0xFFFFFFFFUL /**< Mask for MODEM_IRCALCOEFWR */ +#define _MODEM_IRCALCOEFWR_CRVWD_SHIFT 0 /**< Shift value for MODEM_CRVWD */ +#define _MODEM_IRCALCOEFWR_CRVWD_MASK 0x7FFFUL /**< Bit mask for MODEM_CRVWD */ +#define _MODEM_IRCALCOEFWR_CRVWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CRVWD_DEFAULT (_MODEM_IRCALCOEFWR_CRVWD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CRVWEN (0x1UL << 15) /**< CIV Coefficient Write Enable */ +#define _MODEM_IRCALCOEFWR_CRVWEN_SHIFT 15 /**< Shift value for MODEM_CRVWEN */ +#define _MODEM_IRCALCOEFWR_CRVWEN_MASK 0x8000UL /**< Bit mask for MODEM_CRVWEN */ +#define _MODEM_IRCALCOEFWR_CRVWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CRVWEN_DEFAULT (_MODEM_IRCALCOEFWR_CRVWEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */ +#define _MODEM_IRCALCOEFWR_CIVWD_SHIFT 16 /**< Shift value for MODEM_CIVWD */ +#define _MODEM_IRCALCOEFWR_CIVWD_MASK 0x7FFF0000UL /**< Bit mask for MODEM_CIVWD */ +#define _MODEM_IRCALCOEFWR_CIVWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CIVWD_DEFAULT (_MODEM_IRCALCOEFWR_CIVWD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CIVWEN (0x1UL << 31) /**< CIV Coefficient Write Enable */ +#define _MODEM_IRCALCOEFWR_CIVWEN_SHIFT 31 /**< Shift value for MODEM_CIVWEN */ +#define _MODEM_IRCALCOEFWR_CIVWEN_MASK 0x80000000UL /**< Bit mask for MODEM_CIVWEN */ +#define _MODEM_IRCALCOEFWR_CIVWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */ +#define MODEM_IRCALCOEFWR_CIVWEN_DEFAULT (_MODEM_IRCALCOEFWR_CIVWEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */ + +/* Bit fields for MODEM ADCTRL1 */ +#define _MODEM_ADCTRL1_RESETVALUE 0x00080000UL /**< Default value for MODEM_ADCTRL1 */ +#define _MODEM_ADCTRL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADCTRL1 */ +#define _MODEM_ADCTRL1_ADCTRL1_SHIFT 0 /**< Shift value for MODEM_ADCTRL1 */ +#define _MODEM_ADCTRL1_ADCTRL1_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADCTRL1 */ +#define _MODEM_ADCTRL1_ADCTRL1_DEFAULT 0x00080000UL /**< Mode DEFAULT for MODEM_ADCTRL1 */ +#define MODEM_ADCTRL1_ADCTRL1_DEFAULT (_MODEM_ADCTRL1_ADCTRL1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADCTRL1 */ + +/* Bit fields for MODEM ADCTRL2 */ +#define _MODEM_ADCTRL2_RESETVALUE 0x00000001UL /**< Default value for MODEM_ADCTRL2 */ +#define _MODEM_ADCTRL2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADCTRL2 */ +#define _MODEM_ADCTRL2_ADCTRL2_SHIFT 0 /**< Shift value for MODEM_ADCTRL2 */ +#define _MODEM_ADCTRL2_ADCTRL2_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADCTRL2 */ +#define _MODEM_ADCTRL2_ADCTRL2_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADCTRL2 */ +#define MODEM_ADCTRL2_ADCTRL2_DEFAULT (_MODEM_ADCTRL2_ADCTRL2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADCTRL2 */ + +/* Bit fields for MODEM ADQUAL0 */ +#define _MODEM_ADQUAL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL0 */ +#define _MODEM_ADQUAL0_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL0 */ +#define _MODEM_ADQUAL0_ADRSSI0_SHIFT 0 /**< Shift value for MODEM_ADRSSI0 */ +#define _MODEM_ADQUAL0_ADRSSI0_MASK 0x3FFUL /**< Bit mask for MODEM_ADRSSI0 */ +#define _MODEM_ADQUAL0_ADRSSI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL0 */ +#define MODEM_ADQUAL0_ADRSSI0_DEFAULT (_MODEM_ADQUAL0_ADRSSI0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL0 */ +#define _MODEM_ADQUAL0_ADRSSI1_SHIFT 16 /**< Shift value for MODEM_ADRSSI1 */ +#define _MODEM_ADQUAL0_ADRSSI1_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSI1 */ +#define _MODEM_ADQUAL0_ADRSSI1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL0 */ +#define MODEM_ADQUAL0_ADRSSI1_DEFAULT (_MODEM_ADQUAL0_ADRSSI1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL0 */ + +/* Bit fields for MODEM ADQUAL1 */ +#define _MODEM_ADQUAL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL1 */ +#define _MODEM_ADQUAL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL1 */ +#define _MODEM_ADQUAL1_ADCORR0_SHIFT 0 /**< Shift value for MODEM_ADCORR0 */ +#define _MODEM_ADQUAL1_ADCORR0_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR0 */ +#define _MODEM_ADQUAL1_ADCORR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL1 */ +#define MODEM_ADQUAL1_ADCORR0_DEFAULT (_MODEM_ADQUAL1_ADCORR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL1 */ +#define _MODEM_ADQUAL1_ADSTAT1_SHIFT 17 /**< Shift value for MODEM_ADSTAT1 */ +#define _MODEM_ADQUAL1_ADSTAT1_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADSTAT1 */ +#define _MODEM_ADQUAL1_ADSTAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL1 */ +#define MODEM_ADQUAL1_ADSTAT1_DEFAULT (_MODEM_ADQUAL1_ADSTAT1_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL1 */ + +/* Bit fields for MODEM ADQUAL2 */ +#define _MODEM_ADQUAL2_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL2 */ +#define _MODEM_ADQUAL2_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL2 */ +#define _MODEM_ADQUAL2_ADRSSI0P_SHIFT 0 /**< Shift value for MODEM_ADRSSI0P */ +#define _MODEM_ADQUAL2_ADRSSI0P_MASK 0x3FFUL /**< Bit mask for MODEM_ADRSSI0P */ +#define _MODEM_ADQUAL2_ADRSSI0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL2 */ +#define MODEM_ADQUAL2_ADRSSI0P_DEFAULT (_MODEM_ADQUAL2_ADRSSI0P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL2 */ +#define _MODEM_ADQUAL2_ADRSSI1P_SHIFT 16 /**< Shift value for MODEM_ADRSSI1P */ +#define _MODEM_ADQUAL2_ADRSSI1P_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSI1P */ +#define _MODEM_ADQUAL2_ADRSSI1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL2 */ +#define MODEM_ADQUAL2_ADRSSI1P_DEFAULT (_MODEM_ADQUAL2_ADRSSI1P_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL2 */ + +/* Bit fields for MODEM ADQUAL3 */ +#define _MODEM_ADQUAL3_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL3 */ +#define _MODEM_ADQUAL3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL3 */ +#define _MODEM_ADQUAL3_ADCORR0P_SHIFT 0 /**< Shift value for MODEM_ADCORR0P */ +#define _MODEM_ADQUAL3_ADCORR0P_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR0P */ +#define _MODEM_ADQUAL3_ADCORR0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL3 */ +#define MODEM_ADQUAL3_ADCORR0P_DEFAULT (_MODEM_ADQUAL3_ADCORR0P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL3 */ +#define _MODEM_ADQUAL3_ADSTAT2_SHIFT 17 /**< Shift value for MODEM_ADSTAT2 */ +#define _MODEM_ADQUAL3_ADSTAT2_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADSTAT2 */ +#define _MODEM_ADQUAL3_ADSTAT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL3 */ +#define MODEM_ADQUAL3_ADSTAT2_DEFAULT (_MODEM_ADQUAL3_ADSTAT2_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL3 */ + +/* Bit fields for MODEM ADQUAL4 */ +#define _MODEM_ADQUAL4_RESETVALUE 0x0200003FUL /**< Default value for MODEM_ADQUAL4 */ +#define _MODEM_ADQUAL4_MASK 0xC3FF003FUL /**< Mask for MODEM_ADQUAL4 */ +#define _MODEM_ADQUAL4_ADAGCGRTHR_SHIFT 0 /**< Shift value for MODEM_ADAGCGRTHR */ +#define _MODEM_ADQUAL4_ADAGCGRTHR_MASK 0x3FUL /**< Bit mask for MODEM_ADAGCGRTHR */ +#define _MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT 0x0000003FUL /**< Mode DEFAULT for MODEM_ADQUAL4 */ +#define MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT (_MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */ +#define _MODEM_ADQUAL4_ADRSSIGRTHR_SHIFT 16 /**< Shift value for MODEM_ADRSSIGRTHR */ +#define _MODEM_ADQUAL4_ADRSSIGRTHR_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSIGRTHR */ +#define _MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT 0x00000200UL /**< Mode DEFAULT for MODEM_ADQUAL4 */ +#define MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT (_MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */ +#define _MODEM_ADQUAL4_ADGRMODE_SHIFT 30 /**< Shift value for MODEM_ADGRMODE */ +#define _MODEM_ADQUAL4_ADGRMODE_MASK 0xC0000000UL /**< Bit mask for MODEM_ADGRMODE */ +#define _MODEM_ADQUAL4_ADGRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL4 */ +#define MODEM_ADQUAL4_ADGRMODE_DEFAULT (_MODEM_ADQUAL4_ADGRMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */ + +/* Bit fields for MODEM ADQUAL5 */ +#define _MODEM_ADQUAL5_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL5 */ +#define _MODEM_ADQUAL5_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL5 */ +#define _MODEM_ADQUAL5_ADDIRECTCORR_SHIFT 0 /**< Shift value for MODEM_ADDIRECTCORR */ +#define _MODEM_ADQUAL5_ADDIRECTCORR_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADDIRECTCORR */ +#define _MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL5 */ +#define MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT (_MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL5 */ + +/* Bit fields for MODEM ADQUAL6 */ +#define _MODEM_ADQUAL6_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL6 */ +#define _MODEM_ADQUAL6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL6 */ +#define _MODEM_ADQUAL6_ADBACORRTHR_SHIFT 0 /**< Shift value for MODEM_ADBACORRTHR */ +#define _MODEM_ADQUAL6_ADBACORRTHR_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADBACORRTHR */ +#define _MODEM_ADQUAL6_ADBACORRTHR_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL6 */ +#define MODEM_ADQUAL6_ADBACORRTHR_DEFAULT (_MODEM_ADQUAL6_ADBACORRTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL6 */ +#define _MODEM_ADQUAL6_ADBACORRDIFF_SHIFT 17 /**< Shift value for MODEM_ADBACORRDIFF */ +#define _MODEM_ADQUAL6_ADBACORRDIFF_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADBACORRDIFF */ +#define _MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL6 */ +#define MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT (_MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL6 */ + +/* Bit fields for MODEM ADQUAL7 */ +#define _MODEM_ADQUAL7_RESETVALUE 0x000003FFUL /**< Default value for MODEM_ADQUAL7 */ +#define _MODEM_ADQUAL7_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL7 */ +#define _MODEM_ADQUAL7_ADBARSSITHR_SHIFT 0 /**< Shift value for MODEM_ADBARSSITHR */ +#define _MODEM_ADQUAL7_ADBARSSITHR_MASK 0x3FFUL /**< Bit mask for MODEM_ADBARSSITHR */ +#define _MODEM_ADQUAL7_ADBARSSITHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for MODEM_ADQUAL7 */ +#define MODEM_ADQUAL7_ADBARSSITHR_DEFAULT (_MODEM_ADQUAL7_ADBARSSITHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL7 */ +#define _MODEM_ADQUAL7_ADBARSSIDIFF_SHIFT 16 /**< Shift value for MODEM_ADBARSSIDIFF */ +#define _MODEM_ADQUAL7_ADBARSSIDIFF_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADBARSSIDIFF */ +#define _MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL7 */ +#define MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT (_MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL7 */ + +/* Bit fields for MODEM ADQUAL8 */ +#define _MODEM_ADQUAL8_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL8 */ +#define _MODEM_ADQUAL8_MASK 0x3F31FFFFUL /**< Mask for MODEM_ADQUAL8 */ +#define _MODEM_ADQUAL8_ADBACORRTHR2_SHIFT 0 /**< Shift value for MODEM_ADBACORRTHR2 */ +#define _MODEM_ADQUAL8_ADBACORRTHR2_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADBACORRTHR2 */ +#define _MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL8 */ +#define MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT (_MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */ +#define _MODEM_ADQUAL8_ADBAMODE_SHIFT 20 /**< Shift value for MODEM_ADBAMODE */ +#define _MODEM_ADQUAL8_ADBAMODE_MASK 0x300000UL /**< Bit mask for MODEM_ADBAMODE */ +#define _MODEM_ADQUAL8_ADBAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL8 */ +#define MODEM_ADQUAL8_ADBAMODE_DEFAULT (_MODEM_ADQUAL8_ADBAMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */ +#define _MODEM_ADQUAL8_ADBAAGCTHR_SHIFT 24 /**< Shift value for MODEM_ADBAAGCTHR */ +#define _MODEM_ADQUAL8_ADBAAGCTHR_MASK 0x3F000000UL /**< Bit mask for MODEM_ADBAAGCTHR */ +#define _MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL8 */ +#define MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT (_MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */ + +/* Bit fields for MODEM ADQUAL9 */ +#define _MODEM_ADQUAL9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL9 */ +#define _MODEM_ADQUAL9_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL9 */ +#define _MODEM_ADQUAL9_ADCORR1_SHIFT 0 /**< Shift value for MODEM_ADCORR1 */ +#define _MODEM_ADQUAL9_ADCORR1_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR1 */ +#define _MODEM_ADQUAL9_ADCORR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL9 */ +#define MODEM_ADQUAL9_ADCORR1_DEFAULT (_MODEM_ADQUAL9_ADCORR1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL9 */ + +/* Bit fields for MODEM ADQUAL10 */ +#define _MODEM_ADQUAL10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL10 */ +#define _MODEM_ADQUAL10_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL10 */ +#define _MODEM_ADQUAL10_ADCORR1P_SHIFT 0 /**< Shift value for MODEM_ADCORR1P */ +#define _MODEM_ADQUAL10_ADCORR1P_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR1P */ +#define _MODEM_ADQUAL10_ADCORR1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL10 */ +#define MODEM_ADQUAL10_ADCORR1P_DEFAULT (_MODEM_ADQUAL10_ADCORR1P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL10 */ + +/* Bit fields for MODEM ADFSM0 */ +#define _MODEM_ADFSM0_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_MASK 0x7FFFFFFFUL /**< Mask for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTATEC_SHIFT 0 /**< Shift value for MODEM_ADSTATEC */ +#define _MODEM_ADFSM0_ADSTATEC_MASK 0xFUL /**< Bit mask for MODEM_ADSTATEC */ +#define _MODEM_ADFSM0_ADSTATEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATEC_DEFAULT (_MODEM_ADFSM0_ADSTATEC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTATEP_SHIFT 4 /**< Shift value for MODEM_ADSTATEP */ +#define _MODEM_ADFSM0_ADSTATEP_MASK 0xF0UL /**< Bit mask for MODEM_ADSTATEP */ +#define _MODEM_ADFSM0_ADSTATEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATEP_DEFAULT (_MODEM_ADFSM0_ADSTATEP_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTATEP2_SHIFT 8 /**< Shift value for MODEM_ADSTATEP2 */ +#define _MODEM_ADFSM0_ADSTATEP2_MASK 0xF00UL /**< Bit mask for MODEM_ADSTATEP2 */ +#define _MODEM_ADFSM0_ADSTATEP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATEP2_DEFAULT (_MODEM_ADFSM0_ADSTATEP2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTATEN_SHIFT 12 /**< Shift value for MODEM_ADSTATEN */ +#define _MODEM_ADFSM0_ADSTATEN_MASK 0xF000UL /**< Bit mask for MODEM_ADSTATEN */ +#define _MODEM_ADFSM0_ADSTATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATEN_DEFAULT (_MODEM_ADFSM0_ADSTATEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD0 (0x1UL << 16) /**< timdet0 */ +#define _MODEM_ADFSM0_ADTD0_SHIFT 16 /**< Shift value for MODEM_ADTD0 */ +#define _MODEM_ADFSM0_ADTD0_MASK 0x10000UL /**< Bit mask for MODEM_ADTD0 */ +#define _MODEM_ADFSM0_ADTD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD0_DEFAULT (_MODEM_ADFSM0_ADTD0_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD0P (0x1UL << 17) /**< timdet0p */ +#define _MODEM_ADFSM0_ADTD0P_SHIFT 17 /**< Shift value for MODEM_ADTD0P */ +#define _MODEM_ADFSM0_ADTD0P_MASK 0x20000UL /**< Bit mask for MODEM_ADTD0P */ +#define _MODEM_ADFSM0_ADTD0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD0P_DEFAULT (_MODEM_ADFSM0_ADTD0P_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD1 (0x1UL << 18) /**< timdet1 */ +#define _MODEM_ADFSM0_ADTD1_SHIFT 18 /**< Shift value for MODEM_ADTD1 */ +#define _MODEM_ADFSM0_ADTD1_MASK 0x40000UL /**< Bit mask for MODEM_ADTD1 */ +#define _MODEM_ADFSM0_ADTD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD1_DEFAULT (_MODEM_ADFSM0_ADTD1_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD1P (0x1UL << 19) /**< timdet1p */ +#define _MODEM_ADFSM0_ADTD1P_SHIFT 19 /**< Shift value for MODEM_ADTD1P */ +#define _MODEM_ADFSM0_ADTD1P_MASK 0x80000UL /**< Bit mask for MODEM_ADTD1P */ +#define _MODEM_ADFSM0_ADTD1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADTD1P_DEFAULT (_MODEM_ADFSM0_ADTD1P_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATREAD (0x1UL << 20) /**< ADSTATREAD */ +#define _MODEM_ADFSM0_ADSTATREAD_SHIFT 20 /**< Shift value for MODEM_ADSTATREAD */ +#define _MODEM_ADFSM0_ADSTATREAD_MASK 0x100000UL /**< Bit mask for MODEM_ADSTATREAD */ +#define _MODEM_ADFSM0_ADSTATREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTATREAD_DEFAULT (_MODEM_ADFSM0_ADSTATREAD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTAT1SEL_SHIFT 21 /**< Shift value for MODEM_ADSTAT1SEL */ +#define _MODEM_ADFSM0_ADSTAT1SEL_MASK 0x3E00000UL /**< Bit mask for MODEM_ADSTAT1SEL */ +#define _MODEM_ADFSM0_ADSTAT1SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTAT1SEL_DEFAULT (_MODEM_ADFSM0_ADSTAT1SEL_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ +#define _MODEM_ADFSM0_ADSTAT2SEL_SHIFT 26 /**< Shift value for MODEM_ADSTAT2SEL */ +#define _MODEM_ADFSM0_ADSTAT2SEL_MASK 0x7C000000UL /**< Bit mask for MODEM_ADSTAT2SEL */ +#define _MODEM_ADFSM0_ADSTAT2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */ +#define MODEM_ADFSM0_ADSTAT2SEL_DEFAULT (_MODEM_ADFSM0_ADSTAT2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */ + +/* Bit fields for MODEM ADFSM1 */ +#define _MODEM_ADFSM1_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM1 */ +#define _MODEM_ADFSM1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM1 */ +#define _MODEM_ADFSM1_ADOSETANT0_SHIFT 0 /**< Shift value for MODEM_ADOSETANT0 */ +#define _MODEM_ADFSM1_ADOSETANT0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSETANT0 */ +#define _MODEM_ADFSM1_ADOSETANT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM1 */ +#define MODEM_ADFSM1_ADOSETANT0_DEFAULT (_MODEM_ADFSM1_ADOSETANT0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM1 */ +#define _MODEM_ADFSM1_ADOSETANT1_SHIFT 16 /**< Shift value for MODEM_ADOSETANT1 */ +#define _MODEM_ADFSM1_ADOSETANT1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOSETANT1 */ +#define _MODEM_ADFSM1_ADOSETANT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM1 */ +#define MODEM_ADFSM1_ADOSETANT1_DEFAULT (_MODEM_ADFSM1_ADOSETANT1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM1 */ + +/* Bit fields for MODEM ADFSM2 */ +#define _MODEM_ADFSM2_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM2 */ +#define _MODEM_ADFSM2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM2 */ +#define _MODEM_ADFSM2_ADOSWITCHANT_SHIFT 0 /**< Shift value for MODEM_ADOSWITCHANT */ +#define _MODEM_ADFSM2_ADOSWITCHANT_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSWITCHANT */ +#define _MODEM_ADFSM2_ADOSWITCHANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM2 */ +#define MODEM_ADFSM2_ADOSWITCHANT_DEFAULT (_MODEM_ADFSM2_ADOSWITCHANT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM2 */ +#define _MODEM_ADFSM2_ADORESTARTRX_SHIFT 16 /**< Shift value for MODEM_ADORESTARTRX */ +#define _MODEM_ADFSM2_ADORESTARTRX_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADORESTARTRX */ +#define _MODEM_ADFSM2_ADORESTARTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM2 */ +#define MODEM_ADFSM2_ADORESTARTRX_DEFAULT (_MODEM_ADFSM2_ADORESTARTRX_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM2 */ + +/* Bit fields for MODEM ADFSM3 */ +#define _MODEM_ADFSM3_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM3 */ +#define _MODEM_ADFSM3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM3 */ +#define _MODEM_ADFSM3_ADOQUAL0UPDATE_SHIFT 0 /**< Shift value for MODEM_ADOQUAL0UPDATE */ +#define _MODEM_ADFSM3_ADOQUAL0UPDATE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUAL0UPDATE */ +#define _MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM3 */ +#define MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT (_MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM3 */ +#define _MODEM_ADFSM3_ADOQUAL1UPDATE_SHIFT 16 /**< Shift value for MODEM_ADOQUAL1UPDATE */ +#define _MODEM_ADFSM3_ADOQUAL1UPDATE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUAL1UPDATE */ +#define _MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM3 */ +#define MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT (_MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM3 */ + +/* Bit fields for MODEM ADFSM4 */ +#define _MODEM_ADFSM4_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM4 */ +#define _MODEM_ADFSM4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM4 */ +#define _MODEM_ADFSM4_ADOQUAL0CLEAR_SHIFT 0 /**< Shift value for MODEM_ADOQUAL0CLEAR */ +#define _MODEM_ADFSM4_ADOQUAL0CLEAR_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUAL0CLEAR */ +#define _MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM4 */ +#define MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT (_MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM4 */ +#define _MODEM_ADFSM4_ADOQUAL1CLEAR_SHIFT 16 /**< Shift value for MODEM_ADOQUAL1CLEAR */ +#define _MODEM_ADFSM4_ADOQUAL1CLEAR_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUAL1CLEAR */ +#define _MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM4 */ +#define MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT (_MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM4 */ + +/* Bit fields for MODEM ADFSM5 */ +#define _MODEM_ADFSM5_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM5 */ +#define _MODEM_ADFSM5_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM5 */ +#define _MODEM_ADFSM5_ADOMUX_SHIFT 0 /**< Shift value for MODEM_ADOMUX */ +#define _MODEM_ADFSM5_ADOMUX_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADOMUX */ +#define _MODEM_ADFSM5_ADOMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM5 */ +#define MODEM_ADFSM5_ADOMUX_DEFAULT (_MODEM_ADFSM5_ADOMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM5 */ + +/* Bit fields for MODEM ADFSM6 */ +#define _MODEM_ADFSM6_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM6 */ +#define _MODEM_ADFSM6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM6 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW0_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW0 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW0 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM6 */ +#define MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT (_MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM6 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW1_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW1 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW1 */ +#define _MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM6 */ +#define MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT (_MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM6 */ + +/* Bit fields for MODEM ADFSM7 */ +#define _MODEM_ADFSM7_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM7 */ +#define _MODEM_ADFSM7_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM7 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW2_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW2 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW2_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW2 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM7 */ +#define MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT (_MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM7 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW3_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW3 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW3_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW3 */ +#define _MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM7 */ +#define MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT (_MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM7 */ + +/* Bit fields for MODEM ADFSM8 */ +#define _MODEM_ADFSM8_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM8 */ +#define _MODEM_ADFSM8_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM8 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW4_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW4 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW4_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW4 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM8 */ +#define MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT (_MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM8 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW5_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW5 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW5_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW5 */ +#define _MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM8 */ +#define MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT (_MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM8 */ + +/* Bit fields for MODEM ADFSM9 */ +#define _MODEM_ADFSM9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM9 */ +#define _MODEM_ADFSM9_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM9 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW6_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW6 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW6_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW6 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM9 */ +#define MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT (_MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM9 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW7_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW7 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW7_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW7 */ +#define _MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM9 */ +#define MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT (_MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM9 */ + +/* Bit fields for MODEM ADFSM10 */ +#define _MODEM_ADFSM10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM10 */ +#define _MODEM_ADFSM10_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM10 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW8_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW8 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW8_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW8 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM10 */ +#define MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT (_MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM10 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW9_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW9 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW9_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW9 */ +#define _MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM10 */ +#define MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT (_MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM10 */ + +/* Bit fields for MODEM ADFSM11 */ +#define _MODEM_ADFSM11_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM11 */ +#define _MODEM_ADFSM11_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM11 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW10_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW10 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW10_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW10 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM11 */ +#define MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT (_MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM11 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW11_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW11 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW11_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW11 */ +#define _MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM11 */ +#define MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT (_MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM11 */ + +/* Bit fields for MODEM ADFSM12 */ +#define _MODEM_ADFSM12_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM12 */ +#define _MODEM_ADFSM12_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM12 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW12_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW12 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW12_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW12 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM12 */ +#define MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT (_MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM12 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW13_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW13 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW13_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW13 */ +#define _MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM12 */ +#define MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT (_MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM12 */ + +/* Bit fields for MODEM ADFSM13 */ +#define _MODEM_ADFSM13_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM13 */ +#define _MODEM_ADFSM13_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM13 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW14_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW14 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW14_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW14 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM13 */ +#define MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT (_MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM13 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW15_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW15 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW15_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW15 */ +#define _MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM13 */ +#define MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT (_MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM13 */ + +/* Bit fields for MODEM ADFSM14 */ +#define _MODEM_ADFSM14_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM14 */ +#define _MODEM_ADFSM14_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM14 */ +#define _MODEM_ADFSM14_ADFSMCOND0ENA_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENA */ +#define _MODEM_ADFSM14_ADFSMCOND0ENA_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENA */ +#define _MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM14 */ +#define MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT (_MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM14 */ +#define _MODEM_ADFSM14_ADFSMCOND1ENA_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENA */ +#define _MODEM_ADFSM14_ADFSMCOND1ENA_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENA */ +#define _MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM14 */ +#define MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT (_MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM14 */ + +/* Bit fields for MODEM ADFSM15 */ +#define _MODEM_ADFSM15_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM15 */ +#define _MODEM_ADFSM15_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM15 */ +#define _MODEM_ADFSM15_ADFSMCOND2ENA_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENA */ +#define _MODEM_ADFSM15_ADFSMCOND2ENA_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENA */ +#define _MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM15 */ +#define MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT (_MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM15 */ +#define _MODEM_ADFSM15_ADFSMCOND3ENA_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENA */ +#define _MODEM_ADFSM15_ADFSMCOND3ENA_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENA */ +#define _MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM15 */ +#define MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT (_MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM15 */ + +/* Bit fields for MODEM ADFSM16 */ +#define _MODEM_ADFSM16_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM16 */ +#define _MODEM_ADFSM16_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM16 */ +#define _MODEM_ADFSM16_ADFSMCOND0ENB_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENB */ +#define _MODEM_ADFSM16_ADFSMCOND0ENB_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENB */ +#define _MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM16 */ +#define MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT (_MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM16 */ +#define _MODEM_ADFSM16_ADFSMCOND1ENB_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENB */ +#define _MODEM_ADFSM16_ADFSMCOND1ENB_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENB */ +#define _MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM16 */ +#define MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT (_MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM16 */ + +/* Bit fields for MODEM ADFSM17 */ +#define _MODEM_ADFSM17_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM17 */ +#define _MODEM_ADFSM17_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM17 */ +#define _MODEM_ADFSM17_ADFSMCOND2ENB_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENB */ +#define _MODEM_ADFSM17_ADFSMCOND2ENB_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENB */ +#define _MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM17 */ +#define MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT (_MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM17 */ +#define _MODEM_ADFSM17_ADFSMCOND3ENB_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENB */ +#define _MODEM_ADFSM17_ADFSMCOND3ENB_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENB */ +#define _MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM17 */ +#define MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT (_MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM17 */ + +/* Bit fields for MODEM ADFSM18 */ +#define _MODEM_ADFSM18_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM18 */ +#define _MODEM_ADFSM18_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM18 */ +#define _MODEM_ADFSM18_ADFSMCONDSEL_SHIFT 0 /**< Shift value for MODEM_ADFSMCONDSEL */ +#define _MODEM_ADFSM18_ADFSMCONDSEL_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADFSMCONDSEL */ +#define _MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM18 */ +#define MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT (_MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM18 */ + +/* Bit fields for MODEM ADFSM19 */ +#define _MODEM_ADFSM19_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM19 */ +#define _MODEM_ADFSM19_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM19 */ +#define _MODEM_ADFSM19_ADFSMNEXTFORCE_SHIFT 0 /**< Shift value for MODEM_ADFSMNEXTFORCE */ +#define _MODEM_ADFSM19_ADFSMNEXTFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMNEXTFORCE */ +#define _MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM19 */ +#define MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT (_MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM19 */ +#define _MODEM_ADFSM19_ADFSMCONDTRUE_SHIFT 16 /**< Shift value for MODEM_ADFSMCONDTRUE */ +#define _MODEM_ADFSM19_ADFSMCONDTRUE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCONDTRUE */ +#define _MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM19 */ +#define MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT (_MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM19 */ + +/* Bit fields for MODEM ADFSM20 */ +#define _MODEM_ADFSM20_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM20 */ +#define _MODEM_ADFSM20_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM20 */ +#define _MODEM_ADFSM20_ADITENTEREN_SHIFT 0 /**< Shift value for MODEM_ADITENTEREN */ +#define _MODEM_ADFSM20_ADITENTEREN_MASK 0xFFFFUL /**< Bit mask for MODEM_ADITENTEREN */ +#define _MODEM_ADFSM20_ADITENTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM20 */ +#define MODEM_ADFSM20_ADITENTEREN_DEFAULT (_MODEM_ADFSM20_ADITENTEREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM20 */ +#define _MODEM_ADFSM20_ADITLEAVEEN_SHIFT 16 /**< Shift value for MODEM_ADITLEAVEEN */ +#define _MODEM_ADFSM20_ADITLEAVEEN_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADITLEAVEEN */ +#define _MODEM_ADFSM20_ADITLEAVEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM20 */ +#define MODEM_ADFSM20_ADITLEAVEEN_DEFAULT (_MODEM_ADFSM20_ADITLEAVEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM20 */ + +/* Bit fields for MODEM ADFSM21 */ +#define _MODEM_ADFSM21_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM21 */ +#define _MODEM_ADFSM21_MASK 0x000101FFUL /**< Mask for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADENTERFREEZEEN (0x1UL << 0) /**< AD FSM enter freeze enable */ +#define _MODEM_ADFSM21_ADENTERFREEZEEN_SHIFT 0 /**< Shift value for MODEM_ADENTERFREEZEEN */ +#define _MODEM_ADFSM21_ADENTERFREEZEEN_MASK 0x1UL /**< Bit mask for MODEM_ADENTERFREEZEEN */ +#define _MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT (_MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADLEAVEFREEZEEN (0x1UL << 1) /**< AD FSM leave freeze enable */ +#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_SHIFT 1 /**< Shift value for MODEM_ADLEAVEFREEZEEN */ +#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_MASK 0x2UL /**< Bit mask for MODEM_ADLEAVEFREEZEEN */ +#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT (_MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADFROZEN (0x1UL << 2) /**< AD FSM frozen */ +#define _MODEM_ADFSM21_ADFROZEN_SHIFT 2 /**< Shift value for MODEM_ADFROZEN */ +#define _MODEM_ADFSM21_ADFROZEN_MASK 0x4UL /**< Bit mask for MODEM_ADFROZEN */ +#define _MODEM_ADFSM21_ADFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADFROZEN_DEFAULT (_MODEM_ADFSM21_ADFROZEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define _MODEM_ADFSM21_ADUNFREEZENEXT_SHIFT 3 /**< Shift value for MODEM_ADUNFREEZENEXT */ +#define _MODEM_ADFSM21_ADUNFREEZENEXT_MASK 0x78UL /**< Bit mask for MODEM_ADUNFREEZENEXT */ +#define _MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT (_MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADAS (0x1UL << 7) /**< antsel */ +#define _MODEM_ADFSM21_ADAS_SHIFT 7 /**< Shift value for MODEM_ADAS */ +#define _MODEM_ADFSM21_ADAS_MASK 0x80UL /**< Bit mask for MODEM_ADAS */ +#define _MODEM_ADFSM21_ADAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADAS_DEFAULT (_MODEM_ADFSM21_ADAS_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADBA (0x1UL << 8) /**< best_antenna */ +#define _MODEM_ADFSM21_ADBA_SHIFT 8 /**< Shift value for MODEM_ADBA */ +#define _MODEM_ADFSM21_ADBA_MASK 0x100UL /**< Bit mask for MODEM_ADBA */ +#define _MODEM_ADFSM21_ADBA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADBA_DEFAULT (_MODEM_ADFSM21_ADBA_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADUNFREEZE (0x1UL << 16) /**< AD FSM unfreeze */ +#define _MODEM_ADFSM21_ADUNFREEZE_SHIFT 16 /**< Shift value for MODEM_ADUNFREEZE */ +#define _MODEM_ADFSM21_ADUNFREEZE_MASK 0x10000UL /**< Bit mask for MODEM_ADUNFREEZE */ +#define _MODEM_ADFSM21_ADUNFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */ +#define MODEM_ADFSM21_ADUNFREEZE_DEFAULT (_MODEM_ADFSM21_ADUNFREEZE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */ + +/* Bit fields for MODEM ADFSM22 */ +#define _MODEM_ADFSM22_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM22 */ +#define _MODEM_ADFSM22_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM22 */ +#define _MODEM_ADFSM22_ADITENTERSTATUS_SHIFT 0 /**< Shift value for MODEM_ADITENTERSTATUS */ +#define _MODEM_ADFSM22_ADITENTERSTATUS_MASK 0xFFFFUL /**< Bit mask for MODEM_ADITENTERSTATUS */ +#define _MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM22 */ +#define MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT (_MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM22 */ +#define _MODEM_ADFSM22_ADITLEAVESTATUS_SHIFT 16 /**< Shift value for MODEM_ADITLEAVESTATUS */ +#define _MODEM_ADFSM22_ADITLEAVESTATUS_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADITLEAVESTATUS */ +#define _MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM22 */ +#define MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT (_MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM22 */ + +/* Bit fields for MODEM ADFSM23 */ +#define _MODEM_ADFSM23_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM23 */ +#define _MODEM_ADFSM23_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM23 */ +#define _MODEM_ADFSM23_ADFSMCOND0ENC_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENC */ +#define _MODEM_ADFSM23_ADFSMCOND0ENC_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENC */ +#define _MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM23 */ +#define MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT (_MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM23 */ +#define _MODEM_ADFSM23_ADFSMCOND1ENC_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENC */ +#define _MODEM_ADFSM23_ADFSMCOND1ENC_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENC */ +#define _MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM23 */ +#define MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT (_MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM23 */ + +/* Bit fields for MODEM ADFSM24 */ +#define _MODEM_ADFSM24_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM24 */ +#define _MODEM_ADFSM24_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM24 */ +#define _MODEM_ADFSM24_ADFSMCOND2ENC_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENC */ +#define _MODEM_ADFSM24_ADFSMCOND2ENC_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENC */ +#define _MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM24 */ +#define MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT (_MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM24 */ +#define _MODEM_ADFSM24_ADFSMCOND3ENC_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENC */ +#define _MODEM_ADFSM24_ADFSMCOND3ENC_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENC */ +#define _MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM24 */ +#define MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT (_MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM24 */ + +/* Bit fields for MODEM ADFSM25 */ +#define _MODEM_ADFSM25_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM25 */ +#define _MODEM_ADFSM25_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM25 */ +#define _MODEM_ADFSM25_ADFSMCONDOR0_SHIFT 0 /**< Shift value for MODEM_ADFSMCONDOR0 */ +#define _MODEM_ADFSM25_ADFSMCONDOR0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCONDOR0 */ +#define _MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM25 */ +#define MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT (_MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM25 */ +#define _MODEM_ADFSM25_ADFSMCONDOR1_SHIFT 16 /**< Shift value for MODEM_ADFSMCONDOR1 */ +#define _MODEM_ADFSM25_ADFSMCONDOR1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCONDOR1 */ +#define _MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM25 */ +#define MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT (_MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM25 */ + +/* Bit fields for MODEM ADFSM26 */ +#define _MODEM_ADFSM26_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM26 */ +#define _MODEM_ADFSM26_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM26 */ +#define _MODEM_ADFSM26_ADFSMCOND0END_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0END */ +#define _MODEM_ADFSM26_ADFSMCOND0END_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0END */ +#define _MODEM_ADFSM26_ADFSMCOND0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM26 */ +#define MODEM_ADFSM26_ADFSMCOND0END_DEFAULT (_MODEM_ADFSM26_ADFSMCOND0END_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM26 */ +#define _MODEM_ADFSM26_ADFSMCOND1END_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1END */ +#define _MODEM_ADFSM26_ADFSMCOND1END_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1END */ +#define _MODEM_ADFSM26_ADFSMCOND1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM26 */ +#define MODEM_ADFSM26_ADFSMCOND1END_DEFAULT (_MODEM_ADFSM26_ADFSMCOND1END_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM26 */ + +/* Bit fields for MODEM ADFSM27 */ +#define _MODEM_ADFSM27_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM27 */ +#define _MODEM_ADFSM27_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM27 */ +#define _MODEM_ADFSM27_ADFSMCOND2END_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2END */ +#define _MODEM_ADFSM27_ADFSMCOND2END_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2END */ +#define _MODEM_ADFSM27_ADFSMCOND2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM27 */ +#define MODEM_ADFSM27_ADFSMCOND2END_DEFAULT (_MODEM_ADFSM27_ADFSMCOND2END_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM27 */ +#define _MODEM_ADFSM27_ADFSMCOND3END_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3END */ +#define _MODEM_ADFSM27_ADFSMCOND3END_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3END */ +#define _MODEM_ADFSM27_ADFSMCOND3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM27 */ +#define MODEM_ADFSM27_ADFSMCOND3END_DEFAULT (_MODEM_ADFSM27_ADFSMCOND3END_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM27 */ + +/* Bit fields for MODEM ADFSM28 */ +#define _MODEM_ADFSM28_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM28 */ +#define _MODEM_ADFSM28_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM28 */ +#define _MODEM_ADFSM28_ADOSETANTFORCE_SHIFT 0 /**< Shift value for MODEM_ADOSETANTFORCE */ +#define _MODEM_ADFSM28_ADOSETANTFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSETANTFORCE */ +#define _MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM28 */ +#define MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT (_MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM28 */ +#define _MODEM_ADFSM28_ADORESTARTRXFORCE_SHIFT 16 /**< Shift value for MODEM_ADORESTARTRXFORCE */ +#define _MODEM_ADFSM28_ADORESTARTRXFORCE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADORESTARTRXFORCE */ +#define _MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM28 */ +#define MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT (_MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM28 */ + +/* Bit fields for MODEM ADFSM29 */ +#define _MODEM_ADFSM29_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM29 */ +#define _MODEM_ADFSM29_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM29 */ +#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_SHIFT 0 /**< Shift value for MODEM_ADOQUALUPDATEFORCE */ +#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUALUPDATEFORCE */ +#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM29 */ +#define MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT (_MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM29 */ +#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_SHIFT 16 /**< Shift value for MODEM_ADOQUALCLEARFORCE */ +#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUALCLEARFORCE */ +#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM29 */ +#define MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT (_MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM29 */ + +/* Bit fields for MODEM ADFSM30 */ +#define _MODEM_ADFSM30_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM30 */ +#define _MODEM_ADFSM30_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM30 */ +#define _MODEM_ADFSM30_ADODEMODRXREQ_SHIFT 0 /**< Shift value for MODEM_ADODEMODRXREQ */ +#define _MODEM_ADFSM30_ADODEMODRXREQ_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADODEMODRXREQ */ +#define _MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM30 */ +#define MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT (_MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM30 */ + +/* Bit fields for MODEM ADPC1 */ +#define _MODEM_ADPC1_RESETVALUE 0x01200040UL /**< Default value for MODEM_ADPC1 */ +#define _MODEM_ADPC1_MASK 0xFFFF7FFFUL /**< Mask for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCEN (0x1UL << 0) /**< ADPC enable */ +#define _MODEM_ADPC1_ADPCEN_SHIFT 0 /**< Shift value for MODEM_ADPCEN */ +#define _MODEM_ADPC1_ADPCEN_MASK 0x1UL /**< Bit mask for MODEM_ADPCEN */ +#define _MODEM_ADPC1_ADPCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCEN_DEFAULT (_MODEM_ADPC1_ADPCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ +#define _MODEM_ADPC1_ADPCWNDSIZECHIP_SHIFT 1 /**< Shift value for MODEM_ADPCWNDSIZECHIP */ +#define _MODEM_ADPC1_ADPCWNDSIZECHIP_MASK 0xFEUL /**< Bit mask for MODEM_ADPCWNDSIZECHIP */ +#define _MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT (_MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ +#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_SHIFT 8 /**< Shift value for MODEM_ADPCCORROFFSETCHIP */ +#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_MASK 0x7F00UL /**< Bit mask for MODEM_ADPCCORROFFSETCHIP */ +#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT (_MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ +#define _MODEM_ADPC1_ADPCTIMINGBAUDS_SHIFT 16 /**< Shift value for MODEM_ADPCTIMINGBAUDS */ +#define _MODEM_ADPC1_ADPCTIMINGBAUDS_MASK 0xFF0000UL /**< Bit mask for MODEM_ADPCTIMINGBAUDS */ +#define _MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT (_MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ +#define _MODEM_ADPC1_ADPCWNDCNT_SHIFT 24 /**< Shift value for MODEM_ADPCWNDCNT */ +#define _MODEM_ADPC1_ADPCWNDCNT_MASK 0x7000000UL /**< Bit mask for MODEM_ADPCWNDCNT */ +#define _MODEM_ADPC1_ADPCWNDCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCWNDCNT_DEFAULT (_MODEM_ADPC1_ADPCWNDCNT_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ +#define _MODEM_ADPC1_ADPCSKIPCHIPS_SHIFT 27 /**< Shift value for MODEM_ADPCSKIPCHIPS */ +#define _MODEM_ADPC1_ADPCSKIPCHIPS_MASK 0xF8000000UL /**< Bit mask for MODEM_ADPCSKIPCHIPS */ +#define _MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */ +#define MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT (_MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_ADPC1 */ + +/* Bit fields for MODEM ADPC2 */ +#define _MODEM_ADPC2_RESETVALUE 0x000000A0UL /**< Default value for MODEM_ADPC2 */ +#define _MODEM_ADPC2_MASK 0x3FFFFFFFUL /**< Mask for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADPCCORRSAMPLES_SHIFT 0 /**< Shift value for MODEM_ADPCCORRSAMPLES */ +#define _MODEM_ADPC2_ADPCCORRSAMPLES_MASK 0x3FFUL /**< Bit mask for MODEM_ADPCCORRSAMPLES */ +#define _MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT 0x000000A0UL /**< Mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT (_MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_SHIFT 10 /**< Shift value for MODEM_ADPCPRETIMINGBAUDS */ +#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_MASK 0x3FC00UL /**< Bit mask for MODEM_ADPCPRETIMINGBAUDS */ +#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT (_MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADENCORR32 (0x1UL << 18) /**< ADPC enable correlators 16-31 */ +#define _MODEM_ADPC2_ADENCORR32_SHIFT 18 /**< Shift value for MODEM_ADENCORR32 */ +#define _MODEM_ADPC2_ADENCORR32_MASK 0x40000UL /**< Bit mask for MODEM_ADENCORR32 */ +#define _MODEM_ADPC2_ADENCORR32_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADENCORR32_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADENCORR32_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADENCORR32_DEFAULT (_MODEM_ADPC2_ADENCORR32_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADENCORR32_DISABLE (_MODEM_ADPC2_ADENCORR32_DISABLE << 18) /**< Shifted mode DISABLE for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADENCORR32_ENABLE (_MODEM_ADPC2_ADENCORR32_ENABLE << 18) /**< Shifted mode ENABLE for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADPCSIGAMPTHR_SHIFT 19 /**< Shift value for MODEM_ADPCSIGAMPTHR */ +#define _MODEM_ADPC2_ADPCSIGAMPTHR_MASK 0x7F80000UL /**< Bit mask for MODEM_ADPCSIGAMPTHR */ +#define _MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT (_MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_ADPC2 */ +#define _MODEM_ADPC2_ADPCWNDCNTRST_SHIFT 27 /**< Shift value for MODEM_ADPCWNDCNTRST */ +#define _MODEM_ADPC2_ADPCWNDCNTRST_MASK 0x38000000UL /**< Bit mask for MODEM_ADPCWNDCNTRST */ +#define _MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */ +#define MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT (_MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_ADPC2 */ + +/* Bit fields for MODEM ADPC3 */ +#define _MODEM_ADPC3_RESETVALUE 0x01005008UL /**< Default value for MODEM_ADPC3 */ +#define _MODEM_ADPC3_MASK 0x03FFFFFFUL /**< Mask for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSEN (0x1UL << 0) /**< ADBBSS enable */ +#define _MODEM_ADPC3_ADBBSSEN_SHIFT 0 /**< Shift value for MODEM_ADBBSSEN */ +#define _MODEM_ADPC3_ADBBSSEN_MASK 0x1UL /**< Bit mask for MODEM_ADBBSSEN */ +#define _MODEM_ADPC3_ADBBSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSEN_DEFAULT (_MODEM_ADPC3_ADBBSSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSFILTLENGTH_SHIFT 1 /**< Shift value for MODEM_ADBBSSFILTLENGTH */ +#define _MODEM_ADPC3_ADBBSSFILTLENGTH_MASK 0xEUL /**< Bit mask for MODEM_ADBBSSFILTLENGTH */ +#define _MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT (_MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGEN (0x1UL << 4) /**< ADBBSS average enable */ +#define _MODEM_ADPC3_ADBBSSAVGEN_SHIFT 4 /**< Shift value for MODEM_ADBBSSAVGEN */ +#define _MODEM_ADPC3_ADBBSSAVGEN_MASK 0x10UL /**< Bit mask for MODEM_ADBBSSAVGEN */ +#define _MODEM_ADPC3_ADBBSSAVGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGEN_DEFAULT (_MODEM_ADPC3_ADBBSSAVGEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSAVGPER_SHIFT 5 /**< Shift value for MODEM_ADBBSSAVGPER */ +#define _MODEM_ADPC3_ADBBSSAVGPER_MASK 0xE0UL /**< Bit mask for MODEM_ADBBSSAVGPER */ +#define _MODEM_ADPC3_ADBBSSAVGPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGPER_DEFAULT (_MODEM_ADPC3_ADBBSSAVGPER_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSAMPMANT_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPMANT */ +#define _MODEM_ADPC3_ADBBSSAMPMANT_MASK 0xF00UL /**< Bit mask for MODEM_ADBBSSAMPMANT */ +#define _MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT (_MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSAMPEXP_SHIFT 12 /**< Shift value for MODEM_ADBBSSAMPEXP */ +#define _MODEM_ADPC3_ADBBSSAMPEXP_MASK 0xF000UL /**< Bit mask for MODEM_ADBBSSAMPEXP */ +#define _MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT (_MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSAVGWAIT_SHIFT 16 /**< Shift value for MODEM_ADBBSSAVGWAIT */ +#define _MODEM_ADPC3_ADBBSSAVGWAIT_MASK 0xFF0000UL /**< Bit mask for MODEM_ADBBSSAVGWAIT */ +#define _MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT (_MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGFREEZE (0x1UL << 24) /**< ADBBSS average freeze */ +#define _MODEM_ADPC3_ADBBSSAVGFREEZE_SHIFT 24 /**< Shift value for MODEM_ADBBSSAVGFREEZE */ +#define _MODEM_ADPC3_ADBBSSAVGFREEZE_MASK 0x1000000UL /**< Bit mask for MODEM_ADBBSSAVGFREEZE */ +#define _MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT (_MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSSELWRDATA (0x1UL << 25) /**< ADBBSS select RAM write data */ +#define _MODEM_ADPC3_ADBBSSSELWRDATA_SHIFT 25 /**< Shift value for MODEM_ADBBSSSELWRDATA */ +#define _MODEM_ADPC3_ADBBSSSELWRDATA_MASK 0x2000000UL /**< Bit mask for MODEM_ADBBSSSELWRDATA */ +#define _MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS 0x00000000UL /**< Mode ADBBSS for MODEM_ADPC3 */ +#define _MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER 0x00000001UL /**< Mode DATAFILTER for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT (_MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS (_MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS << 25) /**< Shifted mode ADBBSS for MODEM_ADPC3 */ +#define MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER (_MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER << 25) /**< Shifted mode DATAFILTER for MODEM_ADPC3 */ + +/* Bit fields for MODEM ADPC4 */ +#define _MODEM_ADPC4_RESETVALUE 0x1F1F1F1FUL /**< Default value for MODEM_ADPC4 */ +#define _MODEM_ADPC4_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC4 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT0_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT0 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT0_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT0 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */ +#define MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC4 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT1_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT1 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT1_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT1 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */ +#define MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC4 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT2_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT2 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT2_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT2 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */ +#define MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC4 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT3_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT3 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT3_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT3 */ +#define _MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */ +#define MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC4 */ + +/* Bit fields for MODEM ADPC5 */ +#define _MODEM_ADPC5_RESETVALUE 0x1B1F1F1FUL /**< Default value for MODEM_ADPC5 */ +#define _MODEM_ADPC5_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT4_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT4 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT4_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT4 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */ +#define MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT5_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT5_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */ +#define MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT6_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT6 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT6_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT6 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */ +#define MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC5 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT7_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT7 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT7_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT7 */ +#define _MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT 0x0000001BUL /**< Mode DEFAULT for MODEM_ADPC5 */ +#define MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC5 */ + +/* Bit fields for MODEM ADPC6 */ +#define _MODEM_ADPC6_RESETVALUE 0x11131518UL /**< Default value for MODEM_ADPC6 */ +#define _MODEM_ADPC6_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC6 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT8_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT8 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT8_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT8 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT 0x00000018UL /**< Mode DEFAULT for MODEM_ADPC6 */ +#define MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC6 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT9_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT9 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT9_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT9 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT 0x00000015UL /**< Mode DEFAULT for MODEM_ADPC6 */ +#define MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC6 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT10_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT10 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT10_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT10 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT 0x00000013UL /**< Mode DEFAULT for MODEM_ADPC6 */ +#define MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC6 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT11_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT11 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT11_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT11 */ +#define _MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT 0x00000011UL /**< Mode DEFAULT for MODEM_ADPC6 */ +#define MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC6 */ + +/* Bit fields for MODEM ADPC7 */ +#define _MODEM_ADPC7_RESETVALUE 0x0C0D0E10UL /**< Default value for MODEM_ADPC7 */ +#define _MODEM_ADPC7_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC7 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT12_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT12 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT12_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT12 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT 0x00000010UL /**< Mode DEFAULT for MODEM_ADPC7 */ +#define MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC7 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT13_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT13 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT13_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT13 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT 0x0000000EUL /**< Mode DEFAULT for MODEM_ADPC7 */ +#define MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC7 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT14_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT14 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT14_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT14 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT 0x0000000DUL /**< Mode DEFAULT for MODEM_ADPC7 */ +#define MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC7 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT15_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT15 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT15_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT15 */ +#define _MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_ADPC7 */ +#define MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC7 */ + +/* Bit fields for MODEM ADPC8 */ +#define _MODEM_ADPC8_RESETVALUE 0x2F87C145UL /**< Default value for MODEM_ADPC8 */ +#define _MODEM_ADPC8_MASK 0xFFFFFF7FUL /**< Mask for MODEM_ADPC8 */ +#define _MODEM_ADPC8_ADPCOSR_SHIFT 0 /**< Shift value for MODEM_ADPCOSR */ +#define _MODEM_ADPC8_ADPCOSR_MASK 0x7UL /**< Bit mask for MODEM_ADPCOSR */ +#define _MODEM_ADPC8_ADPCOSR_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCOSR_DEFAULT (_MODEM_ADPC8_ADPCOSR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ +#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_SHIFT 3 /**< Shift value for MODEM_ADPCANTSAMPOFFSET */ +#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_MASK 0x38UL /**< Bit mask for MODEM_ADPCANTSAMPOFFSET */ +#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT (0x1UL << 6) /**< ADPCANTSAMPSWITCHWAIT */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_SHIFT 6 /**< Shift value for MODEM_ADPCANTSAMPSWITCHWAIT */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_MASK 0x40UL /**< Bit mask for MODEM_ADPCANTSAMPSWITCHWAIT */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ +#define _MODEM_ADPC8_ADPCANTSAMPBUF_SHIFT 8 /**< Shift value for MODEM_ADPCANTSAMPBUF */ +#define _MODEM_ADPC8_ADPCANTSAMPBUF_MASK 0x3F00UL /**< Bit mask for MODEM_ADPCANTSAMPBUF */ +#define _MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ +#define _MODEM_ADPC8_ADPCANTSAMPWRITE_SHIFT 14 /**< Shift value for MODEM_ADPCANTSAMPWRITE */ +#define _MODEM_ADPC8_ADPCANTSAMPWRITE_MASK 0x3FC000UL /**< Bit mask for MODEM_ADPCANTSAMPWRITE */ +#define _MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_SHIFT 22 /**< Shift value for MODEM_ADPCANTSAMPSWITCH */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_MASK 0xFFC00000UL /**< Bit mask for MODEM_ADPCANTSAMPSWITCH */ +#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT 0x000000BEUL /**< Mode DEFAULT for MODEM_ADPC8 */ +#define MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_ADPC8 */ + +/* Bit fields for MODEM ADPC9 */ +#define _MODEM_ADPC9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADPC9 */ +#define _MODEM_ADPC9_MASK 0x01FFFFFFUL /**< Mask for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPAVGLIM */ +#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_MASK 0xFFUL /**< Bit mask for MODEM_ADBBSSAMPAVGLIM */ +#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT (_MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSAMPTHR_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPTHR */ +#define _MODEM_ADPC9_ADBBSSAMPTHR_MASK 0xFF00UL /**< Bit mask for MODEM_ADBBSSAMPTHR */ +#define _MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT (_MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSSYNCEN (0x1UL << 16) /**< Enable sync of BBSS */ +#define _MODEM_ADPC9_ADBBSSSYNCEN_SHIFT 16 /**< Shift value for MODEM_ADBBSSSYNCEN */ +#define _MODEM_ADPC9_ADBBSSSYNCEN_MASK 0x10000UL /**< Bit mask for MODEM_ADBBSSSYNCEN */ +#define _MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSSYNCEN_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSSYNCEN_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT (_MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSSYNCEN_DISABLE (_MODEM_ADPC9_ADBBSSSYNCEN_DISABLE << 16) /**< Shifted mode DISABLE for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSSYNCEN_ENABLE (_MODEM_ADPC9_ADBBSSSYNCEN_ENABLE << 16) /**< Shifted mode ENABLE for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSUPTHR_SHIFT 17 /**< Shift value for MODEM_ADBBSSUPTHR */ +#define _MODEM_ADPC9_ADBBSSUPTHR_MASK 0x1E0000UL /**< Bit mask for MODEM_ADBBSSUPTHR */ +#define _MODEM_ADPC9_ADBBSSUPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSUPTHR_DEFAULT (_MODEM_ADPC9_ADBBSSUPTHR_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADPC9 */ +#define _MODEM_ADPC9_ADBBSSDNTHR_SHIFT 21 /**< Shift value for MODEM_ADBBSSDNTHR */ +#define _MODEM_ADPC9_ADBBSSDNTHR_MASK 0x1E00000UL /**< Bit mask for MODEM_ADBBSSDNTHR */ +#define _MODEM_ADPC9_ADBBSSDNTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */ +#define MODEM_ADPC9_ADBBSSDNTHR_DEFAULT (_MODEM_ADPC9_ADBBSSDNTHR_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_ADPC9 */ + +/* Bit fields for MODEM ADPC10 */ +#define _MODEM_ADPC10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADPC10 */ +#define _MODEM_ADPC10_MASK 0x0001FFFFUL /**< Mask for MODEM_ADPC10 */ +#define _MODEM_ADPC10_ADBBSSAMPJUMP_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPJUMP */ +#define _MODEM_ADPC10_ADBBSSAMPJUMP_MASK 0xFFUL /**< Bit mask for MODEM_ADBBSSAMPJUMP */ +#define _MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT (_MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHANGEEN (0x1UL << 8) /**< ADBBSSCHANGEEN */ +#define _MODEM_ADPC10_ADBBSSCHANGEEN_SHIFT 8 /**< Shift value for MODEM_ADBBSSCHANGEEN */ +#define _MODEM_ADPC10_ADBBSSCHANGEEN_MASK 0x100UL /**< Bit mask for MODEM_ADBBSSCHANGEEN */ +#define _MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */ +#define _MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC10 */ +#define _MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT (_MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE (_MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE << 8) /**< Shifted mode DISABLE for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE (_MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE << 8) /**< Shifted mode ENABLE for MODEM_ADPC10 */ +#define _MODEM_ADPC10_ADBBSSCHGUPTHR_SHIFT 9 /**< Shift value for MODEM_ADBBSSCHGUPTHR */ +#define _MODEM_ADPC10_ADBBSSCHGUPTHR_MASK 0x1E00UL /**< Bit mask for MODEM_ADBBSSCHGUPTHR */ +#define _MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT (_MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ADPC10 */ +#define _MODEM_ADPC10_ADBBSSCHGDNTHR_SHIFT 13 /**< Shift value for MODEM_ADBBSSCHGDNTHR */ +#define _MODEM_ADPC10_ADBBSSCHGDNTHR_MASK 0x1E000UL /**< Bit mask for MODEM_ADBBSSCHGDNTHR */ +#define _MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */ +#define MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT (_MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_ADPC10 */ + +/* Bit fields for MODEM HADMCTRL0 */ +#define _MODEM_HADMCTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_MASK 0xFC00703FUL /**< Mask for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_HADMEN (0x1UL << 0) /**< Enable HADM */ +#define _MODEM_HADMCTRL0_HADMEN_SHIFT 0 /**< Shift value for MODEM_HADMEN */ +#define _MODEM_HADMCTRL0_HADMEN_MASK 0x1UL /**< Bit mask for MODEM_HADMEN */ +#define _MODEM_HADMCTRL0_HADMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_HADMEN_DEFAULT (_MODEM_HADMCTRL0_HADMEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_TESEN (0x1UL << 1) /**< Tone Exchange Step Enable */ +#define _MODEM_HADMCTRL0_TESEN_SHIFT 1 /**< Shift value for MODEM_TESEN */ +#define _MODEM_HADMCTRL0_TESEN_MASK 0x2UL /**< Bit mask for MODEM_TESEN */ +#define _MODEM_HADMCTRL0_TESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_TESEN_DEFAULT (_MODEM_HADMCTRL0_TESEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PESEN (0x1UL << 2) /**< Packet Exchange Step Enable */ +#define _MODEM_HADMCTRL0_PESEN_SHIFT 2 /**< Shift value for MODEM_PESEN */ +#define _MODEM_HADMCTRL0_PESEN_MASK 0x4UL /**< Bit mask for MODEM_PESEN */ +#define _MODEM_HADMCTRL0_PESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PESEN_DEFAULT (_MODEM_HADMCTRL0_PESEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SNDSEQEN (0x1UL << 3) /**< Sounding Sequence Enable */ +#define _MODEM_HADMCTRL0_SNDSEQEN_SHIFT 3 /**< Shift value for MODEM_SNDSEQEN */ +#define _MODEM_HADMCTRL0_SNDSEQEN_MASK 0x8UL /**< Bit mask for MODEM_SNDSEQEN */ +#define _MODEM_HADMCTRL0_SNDSEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SNDSEQEN_DEFAULT (_MODEM_HADMCTRL0_SNDSEQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_ROLE (0x1UL << 4) /**< HADM Role */ +#define _MODEM_HADMCTRL0_ROLE_SHIFT 4 /**< Shift value for MODEM_ROLE */ +#define _MODEM_HADMCTRL0_ROLE_MASK 0x10UL /**< Bit mask for MODEM_ROLE */ +#define _MODEM_HADMCTRL0_ROLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_ROLE_INITIATOR 0x00000000UL /**< Mode INITIATOR for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_ROLE_REFLECTOR 0x00000001UL /**< Mode REFLECTOR for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_ROLE_DEFAULT (_MODEM_HADMCTRL0_ROLE_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_ROLE_INITIATOR (_MODEM_HADMCTRL0_ROLE_INITIATOR << 4) /**< Shifted mode INITIATOR for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_ROLE_REFLECTOR (_MODEM_HADMCTRL0_ROLE_REFLECTOR << 4) /**< Shifted mode REFLECTOR for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_RTTPHY (0x1UL << 5) /**< PHY Used for RTT Packets */ +#define _MODEM_HADMCTRL0_RTTPHY_SHIFT 5 /**< Shift value for MODEM_RTTPHY */ +#define _MODEM_HADMCTRL0_RTTPHY_MASK 0x20UL /**< Bit mask for MODEM_RTTPHY */ +#define _MODEM_HADMCTRL0_RTTPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_RTTPHY_DEFAULT (_MODEM_HADMCTRL0_RTTPHY_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_PM_SHIFT 12 /**< Shift value for MODEM_PM */ +#define _MODEM_HADMCTRL0_PM_MASK 0x3000UL /**< Bit mask for MODEM_PM */ +#define _MODEM_HADMCTRL0_PM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PM_DEFAULT (_MODEM_HADMCTRL0_PM_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_AVGMODE (0x1UL << 14) /**< Averaging Mode */ +#define _MODEM_HADMCTRL0_AVGMODE_SHIFT 14 /**< Shift value for MODEM_AVGMODE */ +#define _MODEM_HADMCTRL0_AVGMODE_MASK 0x4000UL /**< Bit mask for MODEM_AVGMODE */ +#define _MODEM_HADMCTRL0_AVGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_AVGMODE_PHASEAMP 0x00000000UL /**< Mode PHASEAMP for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_AVGMODE_IQ 0x00000001UL /**< Mode IQ for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_AVGMODE_DEFAULT (_MODEM_HADMCTRL0_AVGMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_AVGMODE_PHASEAMP (_MODEM_HADMCTRL0_AVGMODE_PHASEAMP << 14) /**< Shifted mode PHASEAMP for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_AVGMODE_IQ (_MODEM_HADMCTRL0_AVGMODE_IQ << 14) /**< Shifted mode IQ for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_DFTSCALE_SHIFT 26 /**< Shift value for MODEM_DFTSCALE */ +#define _MODEM_HADMCTRL0_DFTSCALE_MASK 0xC000000UL /**< Bit mask for MODEM_DFTSCALE */ +#define _MODEM_HADMCTRL0_DFTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_DFTSCALE_DEFAULT (_MODEM_HADMCTRL0_DFTSCALE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PKTSENTSEL (0x1UL << 28) /**< RTT Packet Sent Selection */ +#define _MODEM_HADMCTRL0_PKTSENTSEL_SHIFT 28 /**< Shift value for MODEM_PKTSENTSEL */ +#define _MODEM_HADMCTRL0_PKTSENTSEL_MASK 0x10000000UL /**< Bit mask for MODEM_PKTSENTSEL */ +#define _MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT 0x00000000UL /**< Mode BAUD_PRESENT for MODEM_HADMCTRL0 */ +#define _MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT 0x00000001UL /**< Mode MOD_PRESENT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT (_MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT (_MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT << 28) /**< Shifted mode BAUD_PRESENT for MODEM_HADMCTRL0*/ +#define MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT (_MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT << 28) /**< Shifted mode MOD_PRESENT for MODEM_HADMCTRL0*/ +#define MODEM_HADMCTRL0_TXUPSAMPOSR4 (0x1UL << 29) /**< TX symbol UP Sampling by 4 */ +#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_SHIFT 29 /**< Shift value for MODEM_TXUPSAMPOSR4 */ +#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_MASK 0x20000000UL /**< Bit mask for MODEM_TXUPSAMPOSR4 */ +#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT (_MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SSAFCGEAR (0x1UL << 30) /**< SS AFC Gear SW */ +#define _MODEM_HADMCTRL0_SSAFCGEAR_SHIFT 30 /**< Shift value for MODEM_SSAFCGEAR */ +#define _MODEM_HADMCTRL0_SSAFCGEAR_MASK 0x40000000UL /**< Bit mask for MODEM_SSAFCGEAR */ +#define _MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT (_MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SRC2AUTOSCALE (0x1UL << 31) /**< SRC2 Autoscaling Debug Output */ +#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_SHIFT 31 /**< Shift value for MODEM_SRC2AUTOSCALE */ +#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_MASK 0x80000000UL /**< Bit mask for MODEM_SRC2AUTOSCALE */ +#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */ +#define MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT (_MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */ + +/* Bit fields for MODEM HADMCTRL1 */ +#define _MODEM_HADMCTRL1_RESETVALUE 0x00040000UL /**< Default value for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_MASK 0xFFC7FF07UL /**< Mask for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_SHIFT 0 /**< Shift value for MODEM_STEPSTATE */ +#define _MODEM_HADMCTRL1_STEPSTATE_MASK 0x7UL /**< Bit mask for MODEM_STEPSTATE */ +#define _MODEM_HADMCTRL1_STEPSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP 0x00000001UL /**< Mode I_FREQ_COMP for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS 0x00000002UL /**< Mode R_FREQ_COMP_FREQ_MEAS for MODEM_HADMCTRL1*/ +#define _MODEM_HADMCTRL1_STEPSTATE_I_PES 0x00000003UL /**< Mode I_PES for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_R_PES 0x00000004UL /**< Mode R_PES for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_R_PES_TES 0x00000005UL /**< Mode R_PES_TES for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_R_TES 0x00000006UL /**< Mode R_TES for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_STEPSTATE_I_TES 0x00000007UL /**< Mode I_TES for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_DEFAULT (_MODEM_HADMCTRL1_STEPSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_IDLE (_MODEM_HADMCTRL1_STEPSTATE_IDLE << 0) /**< Shifted mode IDLE for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP (_MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP << 0) /**< Shifted mode I_FREQ_COMP for MODEM_HADMCTRL1*/ +#define MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS (_MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS << 0) /**< Shifted mode R_FREQ_COMP_FREQ_MEAS for MODEM_HADMCTRL1*/ +#define MODEM_HADMCTRL1_STEPSTATE_I_PES (_MODEM_HADMCTRL1_STEPSTATE_I_PES << 0) /**< Shifted mode I_PES for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_R_PES (_MODEM_HADMCTRL1_STEPSTATE_R_PES << 0) /**< Shifted mode R_PES for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_R_PES_TES (_MODEM_HADMCTRL1_STEPSTATE_R_PES_TES << 0) /**< Shifted mode R_PES_TES for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_R_TES (_MODEM_HADMCTRL1_STEPSTATE_R_TES << 0) /**< Shifted mode R_TES for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_STEPSTATE_I_TES (_MODEM_HADMCTRL1_STEPSTATE_I_TES << 0) /**< Shifted mode I_TES for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_DFTSTARTOFF_SHIFT 8 /**< Shift value for MODEM_DFTSTARTOFF */ +#define _MODEM_HADMCTRL1_DFTSTARTOFF_MASK 0x7F00UL /**< Bit mask for MODEM_DFTSTARTOFF */ +#define _MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT (_MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_MAXSCHWIN_SHIFT 15 /**< Shift value for MODEM_MAXSCHWIN */ +#define _MODEM_HADMCTRL1_MAXSCHWIN_MASK 0x78000UL /**< Bit mask for MODEM_MAXSCHWIN */ +#define _MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT 0x00000008UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT (_MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */ +#define _MODEM_HADMCTRL1_AVGSTARTOFF_SHIFT 22 /**< Shift value for MODEM_AVGSTARTOFF */ +#define _MODEM_HADMCTRL1_AVGSTARTOFF_MASK 0xFFC00000UL /**< Bit mask for MODEM_AVGSTARTOFF */ +#define _MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */ +#define MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT (_MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */ + +/* Bit fields for MODEM HADMSTATUS0 */ +#define _MODEM_HADMSTATUS0_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS0 */ +#define _MODEM_HADMSTATUS0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_HADMSTATUS0 */ +#define _MODEM_HADMSTATUS0_AVG0_SHIFT 0 /**< Shift value for MODEM_AVG0 */ +#define _MODEM_HADMSTATUS0_AVG0_MASK 0xFFFFUL /**< Bit mask for MODEM_AVG0 */ +#define _MODEM_HADMSTATUS0_AVG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS0 */ +#define MODEM_HADMSTATUS0_AVG0_DEFAULT (_MODEM_HADMSTATUS0_AVG0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS0 */ +#define _MODEM_HADMSTATUS0_AVG1_SHIFT 16 /**< Shift value for MODEM_AVG1 */ +#define _MODEM_HADMSTATUS0_AVG1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_AVG1 */ +#define _MODEM_HADMSTATUS0_AVG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS0 */ +#define MODEM_HADMSTATUS0_AVG1_DEFAULT (_MODEM_HADMSTATUS0_AVG1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS0 */ + +/* Bit fields for MODEM HADMSTATUS1 */ +#define _MODEM_HADMSTATUS1_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS1 */ +#define _MODEM_HADMSTATUS1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_HADMSTATUS1 */ +#define _MODEM_HADMSTATUS1_FREQOFFSET_SHIFT 0 /**< Shift value for MODEM_FREQOFFSET */ +#define _MODEM_HADMSTATUS1_FREQOFFSET_MASK 0xFFFFUL /**< Bit mask for MODEM_FREQOFFSET */ +#define _MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS1 */ +#define MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT (_MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS1 */ +#define _MODEM_HADMSTATUS1_TIMETOX_SHIFT 16 /**< Shift value for MODEM_TIMETOX */ +#define _MODEM_HADMSTATUS1_TIMETOX_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TIMETOX */ +#define _MODEM_HADMSTATUS1_TIMETOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS1 */ +#define MODEM_HADMSTATUS1_TIMETOX_DEFAULT (_MODEM_HADMSTATUS1_TIMETOX_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS1 */ + +/* Bit fields for MODEM HADMSTATUS2 */ +#define _MODEM_HADMSTATUS2_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS2 */ +#define _MODEM_HADMSTATUS2_MASK 0x3FFFFFFFUL /**< Mask for MODEM_HADMSTATUS2 */ +#define _MODEM_HADMSTATUS2_COSTLATE1_SHIFT 0 /**< Shift value for MODEM_COSTLATE1 */ +#define _MODEM_HADMSTATUS2_COSTLATE1_MASK 0x3FFUL /**< Bit mask for MODEM_COSTLATE1 */ +#define _MODEM_HADMSTATUS2_COSTLATE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */ +#define MODEM_HADMSTATUS2_COSTLATE1_DEFAULT (_MODEM_HADMSTATUS2_COSTLATE1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */ +#define _MODEM_HADMSTATUS2_COSTCURR1_SHIFT 10 /**< Shift value for MODEM_COSTCURR1 */ +#define _MODEM_HADMSTATUS2_COSTCURR1_MASK 0xFFC00UL /**< Bit mask for MODEM_COSTCURR1 */ +#define _MODEM_HADMSTATUS2_COSTCURR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */ +#define MODEM_HADMSTATUS2_COSTCURR1_DEFAULT (_MODEM_HADMSTATUS2_COSTCURR1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */ +#define _MODEM_HADMSTATUS2_COSTEARL1_SHIFT 20 /**< Shift value for MODEM_COSTEARL1 */ +#define _MODEM_HADMSTATUS2_COSTEARL1_MASK 0x3FF00000UL /**< Bit mask for MODEM_COSTEARL1 */ +#define _MODEM_HADMSTATUS2_COSTEARL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */ +#define MODEM_HADMSTATUS2_COSTEARL1_DEFAULT (_MODEM_HADMSTATUS2_COSTEARL1_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */ + +/* Bit fields for MODEM HADMSTATUS3 */ +#define _MODEM_HADMSTATUS3_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS3 */ +#define _MODEM_HADMSTATUS3_MASK 0x3FFFFFFFUL /**< Mask for MODEM_HADMSTATUS3 */ +#define _MODEM_HADMSTATUS3_COSTLATE0_SHIFT 0 /**< Shift value for MODEM_COSTLATE0 */ +#define _MODEM_HADMSTATUS3_COSTLATE0_MASK 0x3FFUL /**< Bit mask for MODEM_COSTLATE0 */ +#define _MODEM_HADMSTATUS3_COSTLATE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */ +#define MODEM_HADMSTATUS3_COSTLATE0_DEFAULT (_MODEM_HADMSTATUS3_COSTLATE0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */ +#define _MODEM_HADMSTATUS3_COSTCURR0_SHIFT 10 /**< Shift value for MODEM_COSTCURR0 */ +#define _MODEM_HADMSTATUS3_COSTCURR0_MASK 0xFFC00UL /**< Bit mask for MODEM_COSTCURR0 */ +#define _MODEM_HADMSTATUS3_COSTCURR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */ +#define MODEM_HADMSTATUS3_COSTCURR0_DEFAULT (_MODEM_HADMSTATUS3_COSTCURR0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */ +#define _MODEM_HADMSTATUS3_COSTEARL0_SHIFT 20 /**< Shift value for MODEM_COSTEARL0 */ +#define _MODEM_HADMSTATUS3_COSTEARL0_MASK 0x3FF00000UL /**< Bit mask for MODEM_COSTEARL0 */ +#define _MODEM_HADMSTATUS3_COSTEARL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */ +#define MODEM_HADMSTATUS3_COSTEARL0_DEFAULT (_MODEM_HADMSTATUS3_COSTEARL0_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */ + +/* Bit fields for MODEM HADMSTATUS4 */ +#define _MODEM_HADMSTATUS4_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS4 */ +#define _MODEM_HADMSTATUS4_MASK 0x7FFF7FFFUL /**< Mask for MODEM_HADMSTATUS4 */ +#define _MODEM_HADMSTATUS4_SBSP500I_SHIFT 0 /**< Shift value for MODEM_SBSP500I */ +#define _MODEM_HADMSTATUS4_SBSP500I_MASK 0x7FFFUL /**< Bit mask for MODEM_SBSP500I */ +#define _MODEM_HADMSTATUS4_SBSP500I_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS4 */ +#define MODEM_HADMSTATUS4_SBSP500I_DEFAULT (_MODEM_HADMSTATUS4_SBSP500I_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS4 */ +#define _MODEM_HADMSTATUS4_SBSP500Q_SHIFT 16 /**< Shift value for MODEM_SBSP500Q */ +#define _MODEM_HADMSTATUS4_SBSP500Q_MASK 0x7FFF0000UL /**< Bit mask for MODEM_SBSP500Q */ +#define _MODEM_HADMSTATUS4_SBSP500Q_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS4 */ +#define MODEM_HADMSTATUS4_SBSP500Q_DEFAULT (_MODEM_HADMSTATUS4_SBSP500Q_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS4 */ + +/* Bit fields for MODEM HADMSTATUS5 */ +#define _MODEM_HADMSTATUS5_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS5 */ +#define _MODEM_HADMSTATUS5_MASK 0x7FFF7FFFUL /**< Mask for MODEM_HADMSTATUS5 */ +#define _MODEM_HADMSTATUS5_SBSM500I_SHIFT 0 /**< Shift value for MODEM_SBSM500I */ +#define _MODEM_HADMSTATUS5_SBSM500I_MASK 0x7FFFUL /**< Bit mask for MODEM_SBSM500I */ +#define _MODEM_HADMSTATUS5_SBSM500I_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS5 */ +#define MODEM_HADMSTATUS5_SBSM500I_DEFAULT (_MODEM_HADMSTATUS5_SBSM500I_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS5 */ +#define _MODEM_HADMSTATUS5_SBSM500Q_SHIFT 16 /**< Shift value for MODEM_SBSM500Q */ +#define _MODEM_HADMSTATUS5_SBSM500Q_MASK 0x7FFF0000UL /**< Bit mask for MODEM_SBSM500Q */ +#define _MODEM_HADMSTATUS5_SBSM500Q_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS5 */ +#define MODEM_HADMSTATUS5_SBSM500Q_DEFAULT (_MODEM_HADMSTATUS5_SBSM500Q_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS5 */ + +/* Bit fields for MODEM HADMSTATUS6 */ +#define _MODEM_HADMSTATUS6_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS6 */ +#define _MODEM_HADMSTATUS6_MASK 0xFFF0FFFFUL /**< Mask for MODEM_HADMSTATUS6 */ +#define _MODEM_HADMSTATUS6_FREQMEAS_SHIFT 0 /**< Shift value for MODEM_FREQMEAS */ +#define _MODEM_HADMSTATUS6_FREQMEAS_MASK 0xFFFFUL /**< Bit mask for MODEM_FREQMEAS */ +#define _MODEM_HADMSTATUS6_FREQMEAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */ +#define MODEM_HADMSTATUS6_FREQMEAS_DEFAULT (_MODEM_HADMSTATUS6_FREQMEAS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */ +#define _MODEM_HADMSTATUS6_SBSPSCALE_SHIFT 20 /**< Shift value for MODEM_SBSPSCALE */ +#define _MODEM_HADMSTATUS6_SBSPSCALE_MASK 0x3F00000UL /**< Bit mask for MODEM_SBSPSCALE */ +#define _MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */ +#define MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT (_MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */ +#define _MODEM_HADMSTATUS6_SBSMSCALE_SHIFT 26 /**< Shift value for MODEM_SBSMSCALE */ +#define _MODEM_HADMSTATUS6_SBSMSCALE_MASK 0xFC000000UL /**< Bit mask for MODEM_SBSMSCALE */ +#define _MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */ +#define MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT (_MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */ + +/* Bit fields for MODEM SRC2NCOCTRL */ +#define _MODEM_SRC2NCOCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_SRC2NCOCTRL */ +#define _MODEM_SRC2NCOCTRL_MASK 0x00007FFFUL /**< Mask for MODEM_SRC2NCOCTRL */ +#define MODEM_SRC2NCOCTRL_SRC2NCOEN (0x1UL << 0) /**< Enable SRC2 NCO supplemental clock */ +#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_SHIFT 0 /**< Shift value for MODEM_SRC2NCOEN */ +#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_MASK 0x1UL /**< Bit mask for MODEM_SRC2NCOEN */ +#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRC2NCOCTRL */ +#define MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT (_MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SRC2NCOCTRL */ +#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_SHIFT 1 /**< Shift value for MODEM_PHASEPERCLK */ +#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_MASK 0x7FFEUL /**< Bit mask for MODEM_PHASEPERCLK */ +#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRC2NCOCTRL */ +#define MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT (_MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SRC2NCOCTRL */ + +/* Bit fields for MODEM SPARE */ +#define _MODEM_SPARE_RESETVALUE 0x00000000UL /**< Default value for MODEM_SPARE */ +#define _MODEM_SPARE_MASK 0x000000FFUL /**< Mask for MODEM_SPARE */ +#define _MODEM_SPARE_SPARE_SHIFT 0 /**< Shift value for MODEM_SPARE */ +#define _MODEM_SPARE_SPARE_MASK 0xFFUL /**< Bit mask for MODEM_SPARE */ +#define _MODEM_SPARE_SPARE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SPARE */ +#define MODEM_SPARE_SPARE_DEFAULT (_MODEM_SPARE_SPARE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SPARE */ + +/** @} End of group EFR32MG24_MODEM_BitFields */ +/** @} End of group EFR32MG24_MODEM */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_MODEM_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_mpahbram.h b/EFR32MG24/Device/Include/efr32mg24_mpahbram.h new file mode 100644 index 0000000..ae62eb6 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_mpahbram.h @@ -0,0 +1,443 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MPAHBRAM_H +#define EFR32MG24_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM + * @{ + * @brief EFR32MG24 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t RAMBANKSVALID; /**< New Register */ + __IOM uint32_t CFGSRTOP; /**< Sequential Region on Top */ + __IOM uint32_t CFGSRMAP; /**< Sequential Region Map */ + __IOM uint32_t CFGIU0MAP; /**< Interleaving Unit 0 Map */ + __IOM uint32_t CFGIU1MAP; /**< Interleaving Unit 1 Map */ + __IOM uint32_t CFGIU2MAP; /**< Interleaving Unit 2 Map */ + __IOM uint32_t CFGIU3MAP; /**< Interleaving Unit 3 Map */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t RAMBANKSVALID_SET; /**< New Register */ + __IOM uint32_t CFGSRTOP_SET; /**< Sequential Region on Top */ + __IOM uint32_t CFGSRMAP_SET; /**< Sequential Region Map */ + __IOM uint32_t CFGIU0MAP_SET; /**< Interleaving Unit 0 Map */ + __IOM uint32_t CFGIU1MAP_SET; /**< Interleaving Unit 1 Map */ + __IOM uint32_t CFGIU2MAP_SET; /**< Interleaving Unit 2 Map */ + __IOM uint32_t CFGIU3MAP_SET; /**< Interleaving Unit 3 Map */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t RAMBANKSVALID_CLR; /**< New Register */ + __IOM uint32_t CFGSRTOP_CLR; /**< Sequential Region on Top */ + __IOM uint32_t CFGSRMAP_CLR; /**< Sequential Region Map */ + __IOM uint32_t CFGIU0MAP_CLR; /**< Interleaving Unit 0 Map */ + __IOM uint32_t CFGIU1MAP_CLR; /**< Interleaving Unit 1 Map */ + __IOM uint32_t CFGIU2MAP_CLR; /**< Interleaving Unit 2 Map */ + __IOM uint32_t CFGIU3MAP_CLR; /**< Interleaving Unit 3 Map */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t RAMBANKSVALID_TGL; /**< New Register */ + __IOM uint32_t CFGSRTOP_TGL; /**< Sequential Region on Top */ + __IOM uint32_t CFGSRMAP_TGL; /**< Sequential Region Map */ + __IOM uint32_t CFGIU0MAP_TGL; /**< Interleaving Unit 0 Map */ + __IOM uint32_t CFGIU1MAP_TGL; /**< Interleaving Unit 1 Map */ + __IOM uint32_t CFGIU2MAP_TGL; /**< Interleaving Unit 2 Map */ + __IOM uint32_t CFGIU3MAP_TGL; /**< Interleaving Unit 3 Map */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group EFR32MG24_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MPAHBRAM + * @{ + * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ +#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ +#define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ + +/* Bit fields for MPAHBRAM ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ +#define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/* Bit fields for MPAHBRAM RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_SHIFT 0 /**< Shift value for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 0x00000001UL /**< Mode BLK0 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 0x00000007UL /**< Mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 0x0000001FUL /**< Mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 0x0000003FUL /**< Mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 0x0000007FUL /**< Mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 0x000001FFUL /**< Mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 0x000003FFUL /**< Mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 0x000007FFUL /**< Mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 0x00000FFFUL /**< Mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 0x00001FFFUL /**< Mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 0x00003FFFUL /**< Mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 0x00007FFFUL /**< Mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID */ +#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 0x0000FFFFUL /**< Mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID */ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 << 0) /**< Shifted mode BLK0 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 << 0) /**< Shifted mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 << 0) /**< Shifted mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 << 0) /**< Shifted mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 << 0) /**< Shifted mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 << 0) /**< Shifted mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 << 0) /**< Shifted mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 << 0) /**< Shifted mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 << 0) /**< Shifted mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 << 0) /**< Shifted mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 << 0) /**< Shifted mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 << 0) /**< Shifted mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID*/ +#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 << 0) /**< Shifted mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID*/ + +/* Bit fields for MPAHBRAM CFGSRTOP */ +#define _MPAHBRAM_CFGSRTOP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGSRTOP */ +#define _MPAHBRAM_CFGSRTOP_MASK 0x00000001UL /**< Mask for MPAHBRAM_CFGSRTOP */ +#define MPAHBRAM_CFGSRTOP_SRTOP (0x1UL << 0) /**< Sequential region on top */ +#define _MPAHBRAM_CFGSRTOP_SRTOP_SHIFT 0 /**< Shift value for MPAHBRAM_SRTOP */ +#define _MPAHBRAM_CFGSRTOP_SRTOP_MASK 0x1UL /**< Bit mask for MPAHBRAM_SRTOP */ +#define _MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGSRTOP */ +#define MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT (_MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRTOP */ + +/* Bit fields for MPAHBRAM CFGSRMAP */ +#define _MPAHBRAM_CFGSRMAP_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_CFGSRMAP */ +#define _MPAHBRAM_CFGSRMAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGSRMAP */ +#define _MPAHBRAM_CFGSRMAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGSRMAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGSRMAP_MAP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_CFGSRMAP */ +#define MPAHBRAM_CFGSRMAP_MAP_DEFAULT (_MPAHBRAM_CFGSRMAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRMAP */ + +/* Bit fields for MPAHBRAM CFGIU0MAP */ +#define _MPAHBRAM_CFGIU0MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU0MAP */ +#define _MPAHBRAM_CFGIU0MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU0MAP */ +#define _MPAHBRAM_CFGIU0MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU0MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU0MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU0MAP */ +#define MPAHBRAM_CFGIU0MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU0MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU0MAP */ + +/* Bit fields for MPAHBRAM CFGIU1MAP */ +#define _MPAHBRAM_CFGIU1MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU1MAP */ +#define _MPAHBRAM_CFGIU1MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU1MAP */ +#define _MPAHBRAM_CFGIU1MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU1MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU1MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU1MAP */ +#define MPAHBRAM_CFGIU1MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU1MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU1MAP */ + +/* Bit fields for MPAHBRAM CFGIU2MAP */ +#define _MPAHBRAM_CFGIU2MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU2MAP */ +#define _MPAHBRAM_CFGIU2MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU2MAP */ +#define _MPAHBRAM_CFGIU2MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU2MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU2MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU2MAP */ +#define MPAHBRAM_CFGIU2MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU2MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU2MAP */ + +/* Bit fields for MPAHBRAM CFGIU3MAP */ +#define _MPAHBRAM_CFGIU3MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU3MAP */ +#define _MPAHBRAM_CFGIU3MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU3MAP */ +#define _MPAHBRAM_CFGIU3MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU3MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ +#define _MPAHBRAM_CFGIU3MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU3MAP */ +#define MPAHBRAM_CFGIU3MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU3MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU3MAP */ + +/** @} End of group EFR32MG24_MPAHBRAM_BitFields */ +/** @} End of group EFR32MG24_MPAHBRAM */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_MPAHBRAM_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_msc.h b/EFR32MG24/Device/Include/efr32mg24_msc.h new file mode 100644 index 0000000..253e6ff --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_msc.h @@ -0,0 +1,546 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MSC_H +#define EFR32MG24_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MSC MSC + * @{ + * @brief EFR32MG24 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5; /**< Main space page 160-191 lock word */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[12U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_SET; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_SET; /**< Main space page 160-191 lock word */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[12U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[8U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_CLR; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_CLR; /**< Main space page 160-191 lock word */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[12U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[8U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_TGL; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_TGL; /**< Main space page 160-191 lock word */ + uint32_t RESERVED39[2U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[12U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[8U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32MG24_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MSC + * @{ + * @defgroup EFR32MG24_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< The Current Flash Erase Operation Aborte */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write command is in queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write command timeout flag */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/* Bit fields for MSC PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ + +/* Bit fields for MSC PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ + +/* Bit fields for MSC PAGELOCK4 */ +#define _MSC_PAGELOCK4_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK4 */ +#define _MSC_PAGELOCK4_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK4 */ +#define _MSC_PAGELOCK4_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK4_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK4_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK4 */ +#define MSC_PAGELOCK4_LOCKBIT_DEFAULT (_MSC_PAGELOCK4_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK4 */ + +/* Bit fields for MSC PAGELOCK5 */ +#define _MSC_PAGELOCK5_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK5 */ +#define _MSC_PAGELOCK5_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK5 */ +#define _MSC_PAGELOCK5_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK5_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK5_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK5 */ +#define MSC_PAGELOCK5_LOCKBIT_DEFAULT (_MSC_PAGELOCK5_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK5 */ + +/** @} End of group EFR32MG24_MSC_BitFields */ +/** @} End of group EFR32MG24_MSC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_MSC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_mvp.h b/EFR32MG24/Device/Include/efr32mg24_mvp.h new file mode 100644 index 0000000..2cf1f28 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_mvp.h @@ -0,0 +1,1386 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 MVP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MVP_H +#define EFR32MG24_MVP_H +#define MVP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MVP MVP + * @{ + * @brief EFR32MG24 MVP Register Declaration. + *****************************************************************************/ + +/** MVP PERF Register Group Declaration. */ +typedef struct { + __IM uint32_t CNT; /**< Run Counter */ +} MVP_PERF_TypeDef; + +/** MVP ARRAYST Register Group Declaration. */ +typedef struct { + __IOM uint32_t INDEXSTATE; /**< Index State */ +} MVP_ARRAYST_TypeDef; + +/** MVP LOOPST Register Group Declaration. */ +typedef struct { + __IOM uint32_t STATE; /**< Loop State */ +} MVP_LOOPST_TypeDef; + +/** MVP ALU Register Group Declaration. */ +typedef struct { + __IOM uint32_t REGSTATE; /**< ALU Rn Register */ +} MVP_ALU_TypeDef; + +/** MVP ARRAY Register Group Declaration. */ +typedef struct { + __IOM uint32_t ADDRCFG; /**< Array Base Address */ + __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ + __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ + __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ +} MVP_ARRAY_TypeDef; + +/** MVP LOOP Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Loop Configuration */ + __IOM uint32_t RST; /**< Loop Reset */ +} MVP_LOOP_TypeDef; + +/** MVP INSTR Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ + __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ + __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ +} MVP_INSTR_TypeDef; + +/** MVP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Configuration */ + __IM uint32_t STATUS; /**< Status */ + MVP_PERF_TypeDef PERF[2U]; /**< */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS; /**< Fault Status */ + __IM uint32_t FAULTADDR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ + MVP_ALU_TypeDef ALU[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ + MVP_LOOP_TypeDef LOOP[8U]; /**< */ + MVP_INSTR_TypeDef INSTR[8U]; /**< */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ + uint32_t RESERVED1[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IM uint32_t STATUS_SET; /**< Status */ + MVP_PERF_TypeDef PERF_SET[2U]; /**< */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ + __IM uint32_t FAULTADDR_SET; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ + MVP_ALU_TypeDef ALU_SET[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ + uint32_t RESERVED3[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IM uint32_t STATUS_CLR; /**< Status */ + MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ + __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ + MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ + uint32_t RESERVED5[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IM uint32_t STATUS_TGL; /**< Status */ + MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ + __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ + MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ +} MVP_TypeDef; +/** @} End of group EFR32MG24_MVP */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MVP + * @{ + * @defgroup EFR32MG24_MVP_BitFields MVP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MVP IPVERSION */ +#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ +#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ +#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ + +/* Bit fields for MVP EN */ +#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ +#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ +#define MVP_EN_EN (0x1UL << 0) /**< Enable */ +#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ +#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ +#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ +#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ +#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ + +/* Bit fields for MVP SWRST */ +#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ +#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ +#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ +#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ +#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ + +/* Bit fields for MVP CFG */ +#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ +#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ +#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ +#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ +#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ +#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ +#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ + +/* Bit fields for MVP STATUS */ +#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ +#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ +#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ +#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ +#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ +#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ +#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ +#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ + +/* Bit fields for MVP PERFCNT */ +#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ +#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ +#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ +#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ + +/* Bit fields for MVP IF */ +#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ +#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ +#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ +#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ +#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ +#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ +#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ +#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ +#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ +#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ +#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ +#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ +#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ +#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ +#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ + +/* Bit fields for MVP IEN */ +#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ +#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ +#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ +#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ +#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ +#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ +#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ +#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ +#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ +#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ +#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ +#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ +#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ +#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ +#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ + +/* Bit fields for MVP FAULTSTATUS */ +#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ +#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ + +/* Bit fields for MVP FAULTADDR */ +#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ +#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ + +/* Bit fields for MVP PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ +#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ + +/* Bit fields for MVP ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ + +/* Bit fields for MVP LOOPSTATE */ +#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ +#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ + +/* Bit fields for MVP ALUREGSTATE */ +#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ + +/* Bit fields for MVP ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ +#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ + +/* Bit fields for MVP ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ + +/* Bit fields for MVP ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ + +/* Bit fields for MVP ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ + +/* Bit fields for MVP LOOPCFG */ +#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ + +/* Bit fields for MVP LOOPRST */ +#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ +#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ + +/* Bit fields for MVP INSTRCFG0 */ +#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ + +/* Bit fields for MVP INSTRCFG1 */ +#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ + +/* Bit fields for MVP INSTRCFG2 */ +#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ +#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ + +/* Bit fields for MVP CMD */ +#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ +#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ +#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ +#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ +#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ +#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ +#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ +#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ +#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ +#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ +#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ +#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ +#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ +#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ +#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ + +/* Bit fields for MVP DEBUGEN */ +#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ +#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ + +/* Bit fields for MVP DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ +#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ + +/** @} End of group EFR32MG24_MVP_BitFields */ +/** @} End of group EFR32MG24_MVP */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_MVP_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_pcnt.h b/EFR32MG24/Device/Include/efr32mg24_pcnt.h new file mode 100644 index 0000000..e2f2efc --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_pcnt.h @@ -0,0 +1,482 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 PCNT register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PCNT_H +#define EFR32MG24_PCNT_H +#define PCNT_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_PCNT PCNT + * @{ + * @brief EFR32MG24 PCNT Register Declaration. + *****************************************************************************/ + +/** PCNT Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} PCNT_TypeDef; +/** @} End of group EFR32MG24_PCNT */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_PCNT + * @{ + * @defgroup EFR32MG24_PCNT_BitFields PCNT Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ + +/* Bit fields for PCNT EN */ +#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ +#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ +#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ +#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ +#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ +#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ + +/* Bit fields for PCNT SWRST */ +#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ +#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ +#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ + +/* Bit fields for PCNT CFG */ +#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ +#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ +#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ +#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ +#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ +#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ +#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ +#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ +#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ +#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ +#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ +#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ +#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ +#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ +#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ +#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT OVSCTRL */ +#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ +#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ +#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT LOCK */ +#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ +#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ + +/** @} End of group EFR32MG24_PCNT_BitFields */ +/** @} End of group EFR32MG24_PCNT */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_PCNT_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_protimer.h b/EFR32MG24/Device/Include/efr32mg24_protimer.h new file mode 100644 index 0000000..be8578a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_protimer.h @@ -0,0 +1,1838 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 PROTIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PROTIMER_H +#define EFR32MG24_PROTIMER_H +#define PROTIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_PROTIMER PROTIMER + * @{ + * @brief EFR32MG24 PROTIMER Register Declaration. + *****************************************************************************/ + +/** PROTIMER CC Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t PRE; /**< CC Channel PRE Value Register */ + __IOM uint32_t BASE; /**< CC Channel BASE Value Register */ + __IOM uint32_t WRAP; /**< CC Channel WRAP Value Register */ +} PROTIMER_CC_TypeDef; + +/** PROTIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< EN */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t PRSCTRL; /**< PRS Channel selection */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t PRECNT; /**< Pre Counter Value */ + __IOM uint32_t BASECNT; /**< Base Counter Value */ + __IOM uint32_t WRAPCNT; /**< Wrap Counter Value */ + __IM uint32_t BASEPRE; /**< Base and Pre counter values */ + __IM uint32_t LWRAPCNT; /**< Latched Wrap Counter Value */ + __IOM uint32_t PRECNTTOPADJ; /**< PRECNT Top Adjust Value */ + __IOM uint32_t PRECNTTOP; /**< PRECNT Top Value */ + __IOM uint32_t BASECNTTOP; /**< BASECNT Top Value */ + __IOM uint32_t WRAPCNTTOP; /**< WRAPCNT Top Value Register */ + __IOM uint32_t TOUT0CNT; /**< TOUT0CNT Value Register */ + __IOM uint32_t TOUT0CNTTOP; /**< TOUT0CNTTOP Value Register. */ + __IOM uint32_t TOUT0COMP; /**< TOUT0COMP Register */ + __IOM uint32_t TOUT1CNT; /**< TOUT1CNT Value Register */ + __IOM uint32_t TOUT1CNTTOP; /**< TOUT1CNTTOP Value Register. */ + __IOM uint32_t TOUT1COMP; /**< TOUT1COMP Register */ + __IOM uint32_t LBTCTRL; /**< Listen Before Talk Wait Control */ + __IOM uint32_t LBTPRSCTRL; /**< PRS Channel selection */ + __IOM uint32_t LBTSTATE; /**< Listen Before Talk State */ + __IOM uint32_t RANDOM; /**< Pseudo Random Generator Value Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t RXCTRL; /**< RX request signal from Protimer */ + __IOM uint32_t TXCTRL; /**< TX request signal from Protimer */ + __IOM uint32_t ETSI; /**< Support ETSI LBT */ + __IOM uint32_t LBTSTATE1; /**< Listen Before Talk State */ + __IOM uint32_t RANDOMFW0; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW1; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW2; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t SEQIF; /**< SEQ Interrupt Flagh Register */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED1[26U]; /**< Reserved for future use */ + PROTIMER_CC_TypeDef CC[8U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[928U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< EN */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t PRSCTRL_SET; /**< PRS Channel selection */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t PRECNT_SET; /**< Pre Counter Value */ + __IOM uint32_t BASECNT_SET; /**< Base Counter Value */ + __IOM uint32_t WRAPCNT_SET; /**< Wrap Counter Value */ + __IM uint32_t BASEPRE_SET; /**< Base and Pre counter values */ + __IM uint32_t LWRAPCNT_SET; /**< Latched Wrap Counter Value */ + __IOM uint32_t PRECNTTOPADJ_SET; /**< PRECNT Top Adjust Value */ + __IOM uint32_t PRECNTTOP_SET; /**< PRECNT Top Value */ + __IOM uint32_t BASECNTTOP_SET; /**< BASECNT Top Value */ + __IOM uint32_t WRAPCNTTOP_SET; /**< WRAPCNT Top Value Register */ + __IOM uint32_t TOUT0CNT_SET; /**< TOUT0CNT Value Register */ + __IOM uint32_t TOUT0CNTTOP_SET; /**< TOUT0CNTTOP Value Register. */ + __IOM uint32_t TOUT0COMP_SET; /**< TOUT0COMP Register */ + __IOM uint32_t TOUT1CNT_SET; /**< TOUT1CNT Value Register */ + __IOM uint32_t TOUT1CNTTOP_SET; /**< TOUT1CNTTOP Value Register. */ + __IOM uint32_t TOUT1COMP_SET; /**< TOUT1COMP Register */ + __IOM uint32_t LBTCTRL_SET; /**< Listen Before Talk Wait Control */ + __IOM uint32_t LBTPRSCTRL_SET; /**< PRS Channel selection */ + __IOM uint32_t LBTSTATE_SET; /**< Listen Before Talk State */ + __IOM uint32_t RANDOM_SET; /**< Pseudo Random Generator Value Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t RXCTRL_SET; /**< RX request signal from Protimer */ + __IOM uint32_t TXCTRL_SET; /**< TX request signal from Protimer */ + __IOM uint32_t ETSI_SET; /**< Support ETSI LBT */ + __IOM uint32_t LBTSTATE1_SET; /**< Listen Before Talk State */ + __IOM uint32_t RANDOMFW0_SET; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW1_SET; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW2_SET; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flagh Register */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED4[26U]; /**< Reserved for future use */ + PROTIMER_CC_TypeDef CC_SET[8U]; /**< Compare/Capture Channel */ + uint32_t RESERVED5[928U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< EN */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t PRSCTRL_CLR; /**< PRS Channel selection */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre Counter Value */ + __IOM uint32_t BASECNT_CLR; /**< Base Counter Value */ + __IOM uint32_t WRAPCNT_CLR; /**< Wrap Counter Value */ + __IM uint32_t BASEPRE_CLR; /**< Base and Pre counter values */ + __IM uint32_t LWRAPCNT_CLR; /**< Latched Wrap Counter Value */ + __IOM uint32_t PRECNTTOPADJ_CLR; /**< PRECNT Top Adjust Value */ + __IOM uint32_t PRECNTTOP_CLR; /**< PRECNT Top Value */ + __IOM uint32_t BASECNTTOP_CLR; /**< BASECNT Top Value */ + __IOM uint32_t WRAPCNTTOP_CLR; /**< WRAPCNT Top Value Register */ + __IOM uint32_t TOUT0CNT_CLR; /**< TOUT0CNT Value Register */ + __IOM uint32_t TOUT0CNTTOP_CLR; /**< TOUT0CNTTOP Value Register. */ + __IOM uint32_t TOUT0COMP_CLR; /**< TOUT0COMP Register */ + __IOM uint32_t TOUT1CNT_CLR; /**< TOUT1CNT Value Register */ + __IOM uint32_t TOUT1CNTTOP_CLR; /**< TOUT1CNTTOP Value Register. */ + __IOM uint32_t TOUT1COMP_CLR; /**< TOUT1COMP Register */ + __IOM uint32_t LBTCTRL_CLR; /**< Listen Before Talk Wait Control */ + __IOM uint32_t LBTPRSCTRL_CLR; /**< PRS Channel selection */ + __IOM uint32_t LBTSTATE_CLR; /**< Listen Before Talk State */ + __IOM uint32_t RANDOM_CLR; /**< Pseudo Random Generator Value Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t RXCTRL_CLR; /**< RX request signal from Protimer */ + __IOM uint32_t TXCTRL_CLR; /**< TX request signal from Protimer */ + __IOM uint32_t ETSI_CLR; /**< Support ETSI LBT */ + __IOM uint32_t LBTSTATE1_CLR; /**< Listen Before Talk State */ + __IOM uint32_t RANDOMFW0_CLR; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW1_CLR; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW2_CLR; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flagh Register */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED7[26U]; /**< Reserved for future use */ + PROTIMER_CC_TypeDef CC_CLR[8U]; /**< Compare/Capture Channel */ + uint32_t RESERVED8[928U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< EN */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t PRSCTRL_TGL; /**< PRS Channel selection */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre Counter Value */ + __IOM uint32_t BASECNT_TGL; /**< Base Counter Value */ + __IOM uint32_t WRAPCNT_TGL; /**< Wrap Counter Value */ + __IM uint32_t BASEPRE_TGL; /**< Base and Pre counter values */ + __IM uint32_t LWRAPCNT_TGL; /**< Latched Wrap Counter Value */ + __IOM uint32_t PRECNTTOPADJ_TGL; /**< PRECNT Top Adjust Value */ + __IOM uint32_t PRECNTTOP_TGL; /**< PRECNT Top Value */ + __IOM uint32_t BASECNTTOP_TGL; /**< BASECNT Top Value */ + __IOM uint32_t WRAPCNTTOP_TGL; /**< WRAPCNT Top Value Register */ + __IOM uint32_t TOUT0CNT_TGL; /**< TOUT0CNT Value Register */ + __IOM uint32_t TOUT0CNTTOP_TGL; /**< TOUT0CNTTOP Value Register. */ + __IOM uint32_t TOUT0COMP_TGL; /**< TOUT0COMP Register */ + __IOM uint32_t TOUT1CNT_TGL; /**< TOUT1CNT Value Register */ + __IOM uint32_t TOUT1CNTTOP_TGL; /**< TOUT1CNTTOP Value Register. */ + __IOM uint32_t TOUT1COMP_TGL; /**< TOUT1COMP Register */ + __IOM uint32_t LBTCTRL_TGL; /**< Listen Before Talk Wait Control */ + __IOM uint32_t LBTPRSCTRL_TGL; /**< PRS Channel selection */ + __IOM uint32_t LBTSTATE_TGL; /**< Listen Before Talk State */ + __IOM uint32_t RANDOM_TGL; /**< Pseudo Random Generator Value Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t RXCTRL_TGL; /**< RX request signal from Protimer */ + __IOM uint32_t TXCTRL_TGL; /**< TX request signal from Protimer */ + __IOM uint32_t ETSI_TGL; /**< Support ETSI LBT */ + __IOM uint32_t LBTSTATE1_TGL; /**< Listen Before Talk State */ + __IOM uint32_t RANDOMFW0_TGL; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW1_TGL; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t RANDOMFW2_TGL; /**< GENERATED LINEAR RANDOM VALUE */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flagh Register */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED10[26U]; /**< Reserved for future use */ + PROTIMER_CC_TypeDef CC_TGL[8U]; /**< Compare/Capture Channel */ +} PROTIMER_TypeDef; +/** @} End of group EFR32MG24_PROTIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_PROTIMER + * @{ + * @defgroup EFR32MG24_PROTIMER_BitFields PROTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PROTIMER IPVERSION */ +#define _PROTIMER_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PROTIMER_IPVERSION */ +#define _PROTIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_IPVERSION */ +#define _PROTIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PROTIMER_IPVERSION */ +#define _PROTIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_IPVERSION */ +#define _PROTIMER_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PROTIMER_IPVERSION */ +#define PROTIMER_IPVERSION_IPVERSION_DEFAULT (_PROTIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IPVERSION */ + +/* Bit fields for PROTIMER EN */ +#define _PROTIMER_EN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_EN */ +#define _PROTIMER_EN_MASK 0x00000001UL /**< Mask for PROTIMER_EN */ +#define PROTIMER_EN_EN (0x1UL << 0) /**< EN */ +#define _PROTIMER_EN_EN_SHIFT 0 /**< Shift value for PROTIMER_EN */ +#define _PROTIMER_EN_EN_MASK 0x1UL /**< Bit mask for PROTIMER_EN */ +#define _PROTIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_EN */ +#define PROTIMER_EN_EN_DEFAULT (_PROTIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_EN */ + +/* Bit fields for PROTIMER CTRL */ +#define _PROTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_MASK 0x3FF33336UL /**< Mask for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _PROTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for PROTIMER_DEBUGRUN */ +#define _PROTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for PROTIMER_DEBUGRUN */ +#define _PROTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DEBUGRUN_DEFAULT (_PROTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DEBUGRUN_X0 (_PROTIMER_CTRL_DEBUGRUN_X0 << 1) /**< Shifted mode X0 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DEBUGRUN_X1 (_PROTIMER_CTRL_DEBUGRUN_X1 << 1) /**< Shifted mode X1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DMACLRACT (0x1UL << 2) /**< DMA Request Clear on Active */ +#define _PROTIMER_CTRL_DMACLRACT_SHIFT 2 /**< Shift value for PROTIMER_DMACLRACT */ +#define _PROTIMER_CTRL_DMACLRACT_MASK 0x4UL /**< Bit mask for PROTIMER_DMACLRACT */ +#define _PROTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_DMACLRACT_DEFAULT (_PROTIMER_CTRL_DMACLRACT_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-Shot Mode Enable */ +#define _PROTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for PROTIMER_OSMEN */ +#define _PROTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for PROTIMER_OSMEN */ +#define _PROTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_OSMEN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_OSMEN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_OSMEN_DEFAULT (_PROTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_OSMEN_X0 (_PROTIMER_CTRL_OSMEN_X0 << 4) /**< Shifted mode X0 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_OSMEN_X1 (_PROTIMER_CTRL_OSMEN_X1 << 4) /**< Shifted mode X1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_ZEROSTARTEN (0x1UL << 5) /**< Start from zero enable */ +#define _PROTIMER_CTRL_ZEROSTARTEN_SHIFT 5 /**< Shift value for PROTIMER_ZEROSTARTEN */ +#define _PROTIMER_CTRL_ZEROSTARTEN_MASK 0x20UL /**< Bit mask for PROTIMER_ZEROSTARTEN */ +#define _PROTIMER_CTRL_ZEROSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_ZEROSTARTEN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_ZEROSTARTEN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_ZEROSTARTEN_DEFAULT (_PROTIMER_CTRL_ZEROSTARTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_ZEROSTARTEN_X0 (_PROTIMER_CTRL_ZEROSTARTEN_X0 << 5) /**< Shifted mode X0 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_ZEROSTARTEN_X1 (_PROTIMER_CTRL_ZEROSTARTEN_X1 << 5) /**< Shifted mode X1 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_PRECNTSRC_SHIFT 8 /**< Shift value for PROTIMER_PRECNTSRC */ +#define _PROTIMER_CTRL_PRECNTSRC_MASK 0x300UL /**< Bit mask for PROTIMER_PRECNTSRC */ +#define _PROTIMER_CTRL_PRECNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_PRECNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_PRECNTSRC_CLOCK 0x00000001UL /**< Mode CLOCK for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_PRECNTSRC_UNUSED0 0x00000002UL /**< Mode UNUSED0 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_PRECNTSRC_UNUSED1 0x00000003UL /**< Mode UNUSED1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_PRECNTSRC_DEFAULT (_PROTIMER_CTRL_PRECNTSRC_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_PRECNTSRC_DISABLED (_PROTIMER_CTRL_PRECNTSRC_DISABLED << 8) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_PRECNTSRC_CLOCK (_PROTIMER_CTRL_PRECNTSRC_CLOCK << 8) /**< Shifted mode CLOCK for PROTIMER_CTRL */ +#define PROTIMER_CTRL_PRECNTSRC_UNUSED0 (_PROTIMER_CTRL_PRECNTSRC_UNUSED0 << 8) /**< Shifted mode UNUSED0 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_PRECNTSRC_UNUSED1 (_PROTIMER_CTRL_PRECNTSRC_UNUSED1 << 8) /**< Shifted mode UNUSED1 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_BASECNTSRC_SHIFT 12 /**< Shift value for PROTIMER_BASECNTSRC */ +#define _PROTIMER_CTRL_BASECNTSRC_MASK 0x3000UL /**< Bit mask for PROTIMER_BASECNTSRC */ +#define _PROTIMER_CTRL_BASECNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_BASECNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_BASECNTSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_BASECNTSRC_UNUSED0 0x00000002UL /**< Mode UNUSED0 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_BASECNTSRC_UNUSED1 0x00000003UL /**< Mode UNUSED1 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_BASECNTSRC_DEFAULT (_PROTIMER_CTRL_BASECNTSRC_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_BASECNTSRC_DISABLED (_PROTIMER_CTRL_BASECNTSRC_DISABLED << 12) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_BASECNTSRC_PRECNTOF (_PROTIMER_CTRL_BASECNTSRC_PRECNTOF << 12) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_BASECNTSRC_UNUSED0 (_PROTIMER_CTRL_BASECNTSRC_UNUSED0 << 12) /**< Shifted mode UNUSED0 for PROTIMER_CTRL */ +#define PROTIMER_CTRL_BASECNTSRC_UNUSED1 (_PROTIMER_CTRL_BASECNTSRC_UNUSED1 << 12) /**< Shifted mode UNUSED1 for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_WRAPCNTSRC_SHIFT 16 /**< Shift value for PROTIMER_WRAPCNTSRC */ +#define _PROTIMER_CTRL_WRAPCNTSRC_MASK 0x30000UL /**< Bit mask for PROTIMER_WRAPCNTSRC */ +#define _PROTIMER_CTRL_WRAPCNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_WRAPCNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_WRAPCNTSRC_UNUSED 0x00000003UL /**< Mode UNUSED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_WRAPCNTSRC_DEFAULT (_PROTIMER_CTRL_WRAPCNTSRC_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_WRAPCNTSRC_DISABLED (_PROTIMER_CTRL_WRAPCNTSRC_DISABLED << 16) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF (_PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF << 16) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF (_PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF << 16) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_WRAPCNTSRC_UNUSED (_PROTIMER_CTRL_WRAPCNTSRC_UNUSED << 16) /**< Shifted mode UNUSED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SRC_SHIFT 20 /**< Shift value for PROTIMER_TOUT0SRC */ +#define _PROTIMER_CTRL_TOUT0SRC_MASK 0x300000UL /**< Bit mask for PROTIMER_TOUT0SRC */ +#define _PROTIMER_CTRL_TOUT0SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SRC_DEFAULT (_PROTIMER_CTRL_TOUT0SRC_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SRC_DISABLED (_PROTIMER_CTRL_TOUT0SRC_DISABLED << 20) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SRC_PRECNTOF (_PROTIMER_CTRL_TOUT0SRC_PRECNTOF << 20) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SRC_BASECNTOF (_PROTIMER_CTRL_TOUT0SRC_BASECNTOF << 20) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF << 20) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_SHIFT 22 /**< Shift value for PROTIMER_TOUT0SYNCSRC */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_MASK 0xC00000UL /**< Bit mask for PROTIMER_TOUT0SYNCSRC */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT (_PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED (_PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED << 22) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF << 22) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF << 22) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF << 22) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SRC_SHIFT 24 /**< Shift value for PROTIMER_TOUT1SRC */ +#define _PROTIMER_CTRL_TOUT1SRC_MASK 0x3000000UL /**< Bit mask for PROTIMER_TOUT1SRC */ +#define _PROTIMER_CTRL_TOUT1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SRC_DEFAULT (_PROTIMER_CTRL_TOUT1SRC_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SRC_DISABLED (_PROTIMER_CTRL_TOUT1SRC_DISABLED << 24) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SRC_PRECNTOF (_PROTIMER_CTRL_TOUT1SRC_PRECNTOF << 24) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SRC_BASECNTOF (_PROTIMER_CTRL_TOUT1SRC_BASECNTOF << 24) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF << 24) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_SHIFT 26 /**< Shift value for PROTIMER_TOUT1SYNCSRC */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_MASK 0xC000000UL /**< Bit mask for PROTIMER_TOUT1SYNCSRC */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT (_PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED (_PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED << 26) /**< Shifted mode DISABLED for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF << 26) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF << 26) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF << 26) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0MODE (0x1UL << 28) /**< Repeat Mode */ +#define _PROTIMER_CTRL_TOUT0MODE_SHIFT 28 /**< Shift value for PROTIMER_TOUT0MODE */ +#define _PROTIMER_CTRL_TOUT0MODE_MASK 0x10000000UL /**< Bit mask for PROTIMER_TOUT0MODE */ +#define _PROTIMER_CTRL_TOUT0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0MODE_FREE 0x00000000UL /**< Mode FREE for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT0MODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0MODE_DEFAULT (_PROTIMER_CTRL_TOUT0MODE_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0MODE_FREE (_PROTIMER_CTRL_TOUT0MODE_FREE << 28) /**< Shifted mode FREE for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT0MODE_ONESHOT (_PROTIMER_CTRL_TOUT0MODE_ONESHOT << 28) /**< Shifted mode ONESHOT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1MODE (0x1UL << 29) /**< Repeat Mode */ +#define _PROTIMER_CTRL_TOUT1MODE_SHIFT 29 /**< Shift value for PROTIMER_TOUT1MODE */ +#define _PROTIMER_CTRL_TOUT1MODE_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT1MODE */ +#define _PROTIMER_CTRL_TOUT1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1MODE_FREE 0x00000000UL /**< Mode FREE for PROTIMER_CTRL */ +#define _PROTIMER_CTRL_TOUT1MODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1MODE_DEFAULT (_PROTIMER_CTRL_TOUT1MODE_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1MODE_FREE (_PROTIMER_CTRL_TOUT1MODE_FREE << 29) /**< Shifted mode FREE for PROTIMER_CTRL */ +#define PROTIMER_CTRL_TOUT1MODE_ONESHOT (_PROTIMER_CTRL_TOUT1MODE_ONESHOT << 29) /**< Shifted mode ONESHOT for PROTIMER_CTRL */ + +/* Bit fields for PROTIMER CMD */ +#define _PROTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CMD */ +#define _PROTIMER_CMD_MASK 0x000707F7UL /**< Mask for PROTIMER_CMD */ +#define PROTIMER_CMD_START (0x1UL << 0) /**< Start PROTIMER */ +#define _PROTIMER_CMD_START_SHIFT 0 /**< Shift value for PROTIMER_START */ +#define _PROTIMER_CMD_START_MASK 0x1UL /**< Bit mask for PROTIMER_START */ +#define _PROTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_START_DEFAULT (_PROTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_RTCSYNCSTART (0x1UL << 1) /**< Start PROTIMER Synchronized with RTCC */ +#define _PROTIMER_CMD_RTCSYNCSTART_SHIFT 1 /**< Shift value for PROTIMER_RTCSYNCSTART */ +#define _PROTIMER_CMD_RTCSYNCSTART_MASK 0x2UL /**< Bit mask for PROTIMER_RTCSYNCSTART */ +#define _PROTIMER_CMD_RTCSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_RTCSYNCSTART_DEFAULT (_PROTIMER_CMD_RTCSYNCSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_STOP (0x1UL << 2) /**< Stop PROTIMER */ +#define _PROTIMER_CMD_STOP_SHIFT 2 /**< Shift value for PROTIMER_STOP */ +#define _PROTIMER_CMD_STOP_MASK 0x4UL /**< Bit mask for PROTIMER_STOP */ +#define _PROTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_STOP_DEFAULT (_PROTIMER_CMD_STOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT0START (0x1UL << 4) /**< Start Timeout counter 0 */ +#define _PROTIMER_CMD_TOUT0START_SHIFT 4 /**< Shift value for PROTIMER_TOUT0START */ +#define _PROTIMER_CMD_TOUT0START_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0START */ +#define _PROTIMER_CMD_TOUT0START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT0START_DEFAULT (_PROTIMER_CMD_TOUT0START_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT0STOP (0x1UL << 5) /**< Stop Timeout counter 0 */ +#define _PROTIMER_CMD_TOUT0STOP_SHIFT 5 /**< Shift value for PROTIMER_TOUT0STOP */ +#define _PROTIMER_CMD_TOUT0STOP_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT0STOP */ +#define _PROTIMER_CMD_TOUT0STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT0STOP_DEFAULT (_PROTIMER_CMD_TOUT0STOP_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT1START (0x1UL << 6) /**< Start Timeout counter 1 */ +#define _PROTIMER_CMD_TOUT1START_SHIFT 6 /**< Shift value for PROTIMER_TOUT1START */ +#define _PROTIMER_CMD_TOUT1START_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT1START */ +#define _PROTIMER_CMD_TOUT1START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT1START_DEFAULT (_PROTIMER_CMD_TOUT1START_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT1STOP (0x1UL << 7) /**< Stop Timeout counter 0 */ +#define _PROTIMER_CMD_TOUT1STOP_SHIFT 7 /**< Shift value for PROTIMER_TOUT1STOP */ +#define _PROTIMER_CMD_TOUT1STOP_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1STOP */ +#define _PROTIMER_CMD_TOUT1STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_TOUT1STOP_DEFAULT (_PROTIMER_CMD_TOUT1STOP_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCETXIDLE (0x1UL << 8) /**< Force to Idle state of tx_state */ +#define _PROTIMER_CMD_FORCETXIDLE_SHIFT 8 /**< Shift value for PROTIMER_FORCETXIDLE */ +#define _PROTIMER_CMD_FORCETXIDLE_MASK 0x100UL /**< Bit mask for PROTIMER_FORCETXIDLE */ +#define _PROTIMER_CMD_FORCETXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCETXIDLE_DEFAULT (_PROTIMER_CMD_FORCETXIDLE_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCERXIDLE (0x1UL << 9) /**< Force to Idle state of rx_state */ +#define _PROTIMER_CMD_FORCERXIDLE_SHIFT 9 /**< Shift value for PROTIMER_FORCERXIDLE */ +#define _PROTIMER_CMD_FORCERXIDLE_MASK 0x200UL /**< Bit mask for PROTIMER_FORCERXIDLE */ +#define _PROTIMER_CMD_FORCERXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCERXIDLE_DEFAULT (_PROTIMER_CMD_FORCERXIDLE_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCERXRX (0x1UL << 10) /**< Force to Rx state of rx_state */ +#define _PROTIMER_CMD_FORCERXRX_SHIFT 10 /**< Shift value for PROTIMER_FORCERXRX */ +#define _PROTIMER_CMD_FORCERXRX_MASK 0x400UL /**< Bit mask for PROTIMER_FORCERXRX */ +#define _PROTIMER_CMD_FORCERXRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_FORCERXRX_DEFAULT (_PROTIMER_CMD_FORCERXRX_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTSTART (0x1UL << 16) /**< LBT sequence start */ +#define _PROTIMER_CMD_LBTSTART_SHIFT 16 /**< Shift value for PROTIMER_LBTSTART */ +#define _PROTIMER_CMD_LBTSTART_MASK 0x10000UL /**< Bit mask for PROTIMER_LBTSTART */ +#define _PROTIMER_CMD_LBTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTSTART_DEFAULT (_PROTIMER_CMD_LBTSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTPAUSE (0x1UL << 17) /**< Pause LBT sequence */ +#define _PROTIMER_CMD_LBTPAUSE_SHIFT 17 /**< Shift value for PROTIMER_LBTPAUSE */ +#define _PROTIMER_CMD_LBTPAUSE_MASK 0x20000UL /**< Bit mask for PROTIMER_LBTPAUSE */ +#define _PROTIMER_CMD_LBTPAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTPAUSE_DEFAULT (_PROTIMER_CMD_LBTPAUSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTSTOP (0x1UL << 18) /**< LBT sequence stop */ +#define _PROTIMER_CMD_LBTSTOP_SHIFT 18 /**< Shift value for PROTIMER_LBTSTOP */ +#define _PROTIMER_CMD_LBTSTOP_MASK 0x40000UL /**< Bit mask for PROTIMER_LBTSTOP */ +#define _PROTIMER_CMD_LBTSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */ +#define PROTIMER_CMD_LBTSTOP_DEFAULT (_PROTIMER_CMD_LBTSTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_CMD */ + +/* Bit fields for PROTIMER PRSCTRL */ +#define _PROTIMER_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_MASK 0x000E0E0EUL /**< Mask for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTPRSEN (0x1UL << 1) /**< Enable Protimer start commands from PRS. */ +#define _PROTIMER_PRSCTRL_STARTPRSEN_SHIFT 1 /**< Shift value for PROTIMER_STARTPRSEN */ +#define _PROTIMER_PRSCTRL_STARTPRSEN_MASK 0x2UL /**< Bit mask for PROTIMER_STARTPRSEN */ +#define _PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT (_PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STARTEDGE_SHIFT 2 /**< Shift value for PROTIMER_STARTEDGE */ +#define _PROTIMER_PRSCTRL_STARTEDGE_MASK 0xCUL /**< Bit mask for PROTIMER_STARTEDGE */ +#define _PROTIMER_PRSCTRL_STARTEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STARTEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STARTEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STARTEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STARTEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTEDGE_DEFAULT (_PROTIMER_PRSCTRL_STARTEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTEDGE_RISING (_PROTIMER_PRSCTRL_STARTEDGE_RISING << 2) /**< Shifted mode RISING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTEDGE_FALLING (_PROTIMER_PRSCTRL_STARTEDGE_FALLING << 2) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTEDGE_BOTH (_PROTIMER_PRSCTRL_STARTEDGE_BOTH << 2) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STARTEDGE_DISABLED (_PROTIMER_PRSCTRL_STARTEDGE_DISABLED << 2) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPPRSEN (0x1UL << 9) /**< Enable Protimer stop commands from PRS. */ +#define _PROTIMER_PRSCTRL_STOPPRSEN_SHIFT 9 /**< Shift value for PROTIMER_STOPPRSEN */ +#define _PROTIMER_PRSCTRL_STOPPRSEN_MASK 0x200UL /**< Bit mask for PROTIMER_STOPPRSEN */ +#define _PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT (_PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STOPEDGE_SHIFT 10 /**< Shift value for PROTIMER_STOPEDGE */ +#define _PROTIMER_PRSCTRL_STOPEDGE_MASK 0xC00UL /**< Bit mask for PROTIMER_STOPEDGE */ +#define _PROTIMER_PRSCTRL_STOPEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STOPEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STOPEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STOPEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_STOPEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPEDGE_DEFAULT (_PROTIMER_PRSCTRL_STOPEDGE_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPEDGE_RISING (_PROTIMER_PRSCTRL_STOPEDGE_RISING << 10) /**< Shifted mode RISING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPEDGE_FALLING (_PROTIMER_PRSCTRL_STOPEDGE_FALLING << 10) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPEDGE_BOTH (_PROTIMER_PRSCTRL_STOPEDGE_BOTH << 10) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_STOPEDGE_DISABLED (_PROTIMER_PRSCTRL_STOPEDGE_DISABLED << 10) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN (0x1UL << 17) /**< Enable RTCC Trigger from PRS. */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_SHIFT 17 /**< Shift value for PROTIMER_RTCCTRIGGERPRSEN */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_MASK 0x20000UL /**< Bit mask for PROTIMER_RTCCTRIGGERPRSEN */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT (_PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_SHIFT 18 /**< Shift value for PROTIMER_RTCCTRIGGEREDGE */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_MASK 0xC0000UL /**< Bit mask for PROTIMER_RTCCTRIGGEREDGE */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */ +#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING << 18) /**< Shifted mode RISING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING << 18) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH << 18) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */ +#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED << 18) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */ + +/* Bit fields for PROTIMER STATUS */ +#define _PROTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_MASK 0x0000FFFFUL /**< Mask for PROTIMER_STATUS */ +#define PROTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _PROTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for PROTIMER_RUNNING */ +#define _PROTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for PROTIMER_RUNNING */ +#define _PROTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_RUNNING_DEFAULT (_PROTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTSYNC (0x1UL << 1) /**< LBT Synchronizing */ +#define _PROTIMER_STATUS_LBTSYNC_SHIFT 1 /**< Shift value for PROTIMER_LBTSYNC */ +#define _PROTIMER_STATUS_LBTSYNC_MASK 0x2UL /**< Bit mask for PROTIMER_LBTSYNC */ +#define _PROTIMER_STATUS_LBTSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTSYNC_DEFAULT (_PROTIMER_STATUS_LBTSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTRUNNING (0x1UL << 2) /**< LBT Running */ +#define _PROTIMER_STATUS_LBTRUNNING_SHIFT 2 /**< Shift value for PROTIMER_LBTRUNNING */ +#define _PROTIMER_STATUS_LBTRUNNING_MASK 0x4UL /**< Bit mask for PROTIMER_LBTRUNNING */ +#define _PROTIMER_STATUS_LBTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTRUNNING_DEFAULT (_PROTIMER_STATUS_LBTRUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTPAUSED (0x1UL << 3) /**< LBT has been paused. */ +#define _PROTIMER_STATUS_LBTPAUSED_SHIFT 3 /**< Shift value for PROTIMER_LBTPAUSED */ +#define _PROTIMER_STATUS_LBTPAUSED_MASK 0x8UL /**< Bit mask for PROTIMER_LBTPAUSED */ +#define _PROTIMER_STATUS_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_LBTPAUSED_DEFAULT (_PROTIMER_STATUS_LBTPAUSED_DEFAULT << 3) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT0RUNNING (0x1UL << 4) /**< Timeout Counter 0 Running */ +#define _PROTIMER_STATUS_TOUT0RUNNING_SHIFT 4 /**< Shift value for PROTIMER_TOUT0RUNNING */ +#define _PROTIMER_STATUS_TOUT0RUNNING_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0RUNNING */ +#define _PROTIMER_STATUS_TOUT0RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT0RUNNING_DEFAULT (_PROTIMER_STATUS_TOUT0RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT0SYNC (0x1UL << 5) /**< Timeout Counter 0 Synchronizing */ +#define _PROTIMER_STATUS_TOUT0SYNC_SHIFT 5 /**< Shift value for PROTIMER_TOUT0SYNC */ +#define _PROTIMER_STATUS_TOUT0SYNC_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT0SYNC */ +#define _PROTIMER_STATUS_TOUT0SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT0SYNC_DEFAULT (_PROTIMER_STATUS_TOUT0SYNC_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT1RUNNING (0x1UL << 6) /**< Timeout Counter 1 Running */ +#define _PROTIMER_STATUS_TOUT1RUNNING_SHIFT 6 /**< Shift value for PROTIMER_TOUT1RUNNING */ +#define _PROTIMER_STATUS_TOUT1RUNNING_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT1RUNNING */ +#define _PROTIMER_STATUS_TOUT1RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT1RUNNING_DEFAULT (_PROTIMER_STATUS_TOUT1RUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT1SYNC (0x1UL << 7) /**< Timeout Counter 1 Synchronizing */ +#define _PROTIMER_STATUS_TOUT1SYNC_SHIFT 7 /**< Shift value for PROTIMER_TOUT1SYNC */ +#define _PROTIMER_STATUS_TOUT1SYNC_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1SYNC */ +#define _PROTIMER_STATUS_TOUT1SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_TOUT1SYNC_DEFAULT (_PROTIMER_STATUS_TOUT1SYNC_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV0 (0x1UL << 8) /**< CC0 Capture Valid */ +#define _PROTIMER_STATUS_ICV0_SHIFT 8 /**< Shift value for PROTIMER_ICV0 */ +#define _PROTIMER_STATUS_ICV0_MASK 0x100UL /**< Bit mask for PROTIMER_ICV0 */ +#define _PROTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV0_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV0_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV0_DEFAULT (_PROTIMER_STATUS_ICV0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV0_X0 (_PROTIMER_STATUS_ICV0_X0 << 8) /**< Shifted mode X0 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV0_X1 (_PROTIMER_STATUS_ICV0_X1 << 8) /**< Shifted mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV1 (0x1UL << 9) /**< CC1 Capture Valid */ +#define _PROTIMER_STATUS_ICV1_SHIFT 9 /**< Shift value for PROTIMER_ICV1 */ +#define _PROTIMER_STATUS_ICV1_MASK 0x200UL /**< Bit mask for PROTIMER_ICV1 */ +#define _PROTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV1_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV1_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV1_DEFAULT (_PROTIMER_STATUS_ICV1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV1_X0 (_PROTIMER_STATUS_ICV1_X0 << 9) /**< Shifted mode X0 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV1_X1 (_PROTIMER_STATUS_ICV1_X1 << 9) /**< Shifted mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV2 (0x1UL << 10) /**< CC2 Capture Valid */ +#define _PROTIMER_STATUS_ICV2_SHIFT 10 /**< Shift value for PROTIMER_ICV2 */ +#define _PROTIMER_STATUS_ICV2_MASK 0x400UL /**< Bit mask for PROTIMER_ICV2 */ +#define _PROTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV2_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV2_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV2_DEFAULT (_PROTIMER_STATUS_ICV2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV2_X0 (_PROTIMER_STATUS_ICV2_X0 << 10) /**< Shifted mode X0 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV2_X1 (_PROTIMER_STATUS_ICV2_X1 << 10) /**< Shifted mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV3 (0x1UL << 11) /**< CC3 Capture Valid */ +#define _PROTIMER_STATUS_ICV3_SHIFT 11 /**< Shift value for PROTIMER_ICV3 */ +#define _PROTIMER_STATUS_ICV3_MASK 0x800UL /**< Bit mask for PROTIMER_ICV3 */ +#define _PROTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV3_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV3_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV3_DEFAULT (_PROTIMER_STATUS_ICV3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV3_X0 (_PROTIMER_STATUS_ICV3_X0 << 11) /**< Shifted mode X0 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV3_X1 (_PROTIMER_STATUS_ICV3_X1 << 11) /**< Shifted mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV4 (0x1UL << 12) /**< CC4 Capture Valid */ +#define _PROTIMER_STATUS_ICV4_SHIFT 12 /**< Shift value for PROTIMER_ICV4 */ +#define _PROTIMER_STATUS_ICV4_MASK 0x1000UL /**< Bit mask for PROTIMER_ICV4 */ +#define _PROTIMER_STATUS_ICV4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV4_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */ +#define _PROTIMER_STATUS_ICV4_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV4_DEFAULT (_PROTIMER_STATUS_ICV4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV4_X0 (_PROTIMER_STATUS_ICV4_X0 << 12) /**< Shifted mode X0 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV4_X1 (_PROTIMER_STATUS_ICV4_X1 << 12) /**< Shifted mode X1 for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV5 (0x1UL << 13) /**< CC5 Capture Valid */ +#define _PROTIMER_STATUS_ICV5_SHIFT 13 /**< Shift value for PROTIMER_ICV5 */ +#define _PROTIMER_STATUS_ICV5_MASK 0x2000UL /**< Bit mask for PROTIMER_ICV5 */ +#define _PROTIMER_STATUS_ICV5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV5_DEFAULT (_PROTIMER_STATUS_ICV5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV6 (0x1UL << 14) /**< CC6 Capture Valid */ +#define _PROTIMER_STATUS_ICV6_SHIFT 14 /**< Shift value for PROTIMER_ICV6 */ +#define _PROTIMER_STATUS_ICV6_MASK 0x4000UL /**< Bit mask for PROTIMER_ICV6 */ +#define _PROTIMER_STATUS_ICV6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV6_DEFAULT (_PROTIMER_STATUS_ICV6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV7 (0x1UL << 15) /**< CC7 Capture Valid */ +#define _PROTIMER_STATUS_ICV7_SHIFT 15 /**< Shift value for PROTIMER_ICV7 */ +#define _PROTIMER_STATUS_ICV7_MASK 0x8000UL /**< Bit mask for PROTIMER_ICV7 */ +#define _PROTIMER_STATUS_ICV7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */ +#define PROTIMER_STATUS_ICV7_DEFAULT (_PROTIMER_STATUS_ICV7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_STATUS */ + +/* Bit fields for PROTIMER PRECNT */ +#define _PROTIMER_PRECNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRECNT */ +#define _PROTIMER_PRECNT_MASK 0x0000FFFFUL /**< Mask for PROTIMER_PRECNT */ +#define _PROTIMER_PRECNT_PRECNT_SHIFT 0 /**< Shift value for PROTIMER_PRECNT */ +#define _PROTIMER_PRECNT_PRECNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNT */ +#define _PROTIMER_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNT */ +#define PROTIMER_PRECNT_PRECNT_DEFAULT (_PROTIMER_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNT */ + +/* Bit fields for PROTIMER BASECNT */ +#define _PROTIMER_BASECNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_BASECNT */ +#define _PROTIMER_BASECNT_MASK 0x0000FFFFUL /**< Mask for PROTIMER_BASECNT */ +#define _PROTIMER_BASECNT_BASECNT_SHIFT 0 /**< Shift value for PROTIMER_BASECNT */ +#define _PROTIMER_BASECNT_BASECNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASECNT */ +#define _PROTIMER_BASECNT_BASECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASECNT */ +#define PROTIMER_BASECNT_BASECNT_DEFAULT (_PROTIMER_BASECNT_BASECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASECNT */ + +/* Bit fields for PROTIMER WRAPCNT */ +#define _PROTIMER_WRAPCNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_WRAPCNT */ +#define _PROTIMER_WRAPCNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_WRAPCNT */ +#define _PROTIMER_WRAPCNT_WRAPCNT_SHIFT 0 /**< Shift value for PROTIMER_WRAPCNT */ +#define _PROTIMER_WRAPCNT_WRAPCNT_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAPCNT */ +#define _PROTIMER_WRAPCNT_WRAPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_WRAPCNT */ +#define PROTIMER_WRAPCNT_WRAPCNT_DEFAULT (_PROTIMER_WRAPCNT_WRAPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_WRAPCNT */ + +/* Bit fields for PROTIMER BASEPRE */ +#define _PROTIMER_BASEPRE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_BASEPRE */ +#define _PROTIMER_BASEPRE_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_BASEPRE */ +#define _PROTIMER_BASEPRE_PRECNTV_SHIFT 0 /**< Shift value for PROTIMER_PRECNTV */ +#define _PROTIMER_BASEPRE_PRECNTV_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNTV */ +#define _PROTIMER_BASEPRE_PRECNTV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASEPRE */ +#define PROTIMER_BASEPRE_PRECNTV_DEFAULT (_PROTIMER_BASEPRE_PRECNTV_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASEPRE */ +#define _PROTIMER_BASEPRE_BASECNTV_SHIFT 16 /**< Shift value for PROTIMER_BASECNTV */ +#define _PROTIMER_BASEPRE_BASECNTV_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_BASECNTV */ +#define _PROTIMER_BASEPRE_BASECNTV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASEPRE */ +#define PROTIMER_BASEPRE_BASECNTV_DEFAULT (_PROTIMER_BASEPRE_BASECNTV_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_BASEPRE */ + +/* Bit fields for PROTIMER LWRAPCNT */ +#define _PROTIMER_LWRAPCNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LWRAPCNT */ +#define _PROTIMER_LWRAPCNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_LWRAPCNT */ +#define _PROTIMER_LWRAPCNT_LWRAPCNT_SHIFT 0 /**< Shift value for PROTIMER_LWRAPCNT */ +#define _PROTIMER_LWRAPCNT_LWRAPCNT_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_LWRAPCNT */ +#define _PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LWRAPCNT */ +#define PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT (_PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LWRAPCNT */ + +/* Bit fields for PROTIMER PRECNTTOPADJ */ +#define _PROTIMER_PRECNTTOPADJ_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRECNTTOPADJ */ +#define _PROTIMER_PRECNTTOPADJ_MASK 0x0000FFFFUL /**< Mask for PROTIMER_PRECNTTOPADJ */ +#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_SHIFT 0 /**< Shift value for PROTIMER_PRECNTTOPADJ */ +#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNTTOPADJ */ +#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNTTOPADJ */ +#define PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT (_PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOPADJ*/ + +/* Bit fields for PROTIMER PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_RESETVALUE 0x00FFFF00UL /**< Default value for PROTIMER_PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_MASK 0x00FFFFFFUL /**< Mask for PROTIMER_PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_SHIFT 0 /**< Shift value for PROTIMER_PRECNTTOPFRAC */ +#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_MASK 0xFFUL /**< Bit mask for PROTIMER_PRECNTTOPFRAC */ +#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNTTOP */ +#define PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT (_PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_PRECNTTOP_SHIFT 8 /**< Shift value for PROTIMER_PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_PRECNTTOP_MASK 0xFFFF00UL /**< Bit mask for PROTIMER_PRECNTTOP */ +#define _PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PROTIMER_PRECNTTOP */ +#define PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT (_PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOP */ + +/* Bit fields for PROTIMER BASECNTTOP */ +#define _PROTIMER_BASECNTTOP_RESETVALUE 0x0000FFFFUL /**< Default value for PROTIMER_BASECNTTOP */ +#define _PROTIMER_BASECNTTOP_MASK 0x0000FFFFUL /**< Mask for PROTIMER_BASECNTTOP */ +#define _PROTIMER_BASECNTTOP_BASECNTTOP_SHIFT 0 /**< Shift value for PROTIMER_BASECNTTOP */ +#define _PROTIMER_BASECNTTOP_BASECNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASECNTTOP */ +#define _PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PROTIMER_BASECNTTOP */ +#define PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT (_PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASECNTTOP*/ + +/* Bit fields for PROTIMER WRAPCNTTOP */ +#define _PROTIMER_WRAPCNTTOP_RESETVALUE 0xFFFFFFFFUL /**< Default value for PROTIMER_WRAPCNTTOP */ +#define _PROTIMER_WRAPCNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_WRAPCNTTOP */ +#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_WRAPCNTTOP */ +#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAPCNTTOP */ +#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for PROTIMER_WRAPCNTTOP */ +#define PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT (_PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_WRAPCNTTOP*/ + +/* Bit fields for PROTIMER TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_TOUT0PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNT */ +#define _PROTIMER_TOUT0CNT_TOUT0PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNT */ +#define _PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0CNT */ +#define PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT (_PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_TOUT0CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_TOUT0CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNT */ +#define _PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0CNT */ +#define PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT (_PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNT */ + +/* Bit fields for PROTIMER TOUT0CNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_RESETVALUE 0x00FF00FFUL /**< Default value for PROTIMER_TOUT0CNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0CNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT0CNTTOP */ +#define PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT (_PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNTTOP*/ +#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNTTOP */ +#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT0CNTTOP */ +#define PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT (_PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNTTOP*/ + +/* Bit fields for PROTIMER TOUT0COMP */ +#define _PROTIMER_TOUT0COMP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT0COMP */ +#define _PROTIMER_TOUT0COMP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0COMP */ +#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNTCOMP */ +#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNTCOMP */ +#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0COMP */ +#define PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT (_PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0COMP */ +#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNTCOMP */ +#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNTCOMP */ +#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0COMP */ +#define PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT (_PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0COMP */ + +/* Bit fields for PROTIMER TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_TOUT1PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNT */ +#define _PROTIMER_TOUT1CNT_TOUT1PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNT */ +#define _PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1CNT */ +#define PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT (_PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_TOUT1CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_TOUT1CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNT */ +#define _PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1CNT */ +#define PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT (_PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNT */ + +/* Bit fields for PROTIMER TOUT1CNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_RESETVALUE 0x00FF00FFUL /**< Default value for PROTIMER_TOUT1CNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1CNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT1CNTTOP */ +#define PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT (_PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNTTOP*/ +#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNTTOP */ +#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT1CNTTOP */ +#define PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT (_PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNTTOP*/ + +/* Bit fields for PROTIMER TOUT1COMP */ +#define _PROTIMER_TOUT1COMP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT1COMP */ +#define _PROTIMER_TOUT1COMP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1COMP */ +#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNTCOMP */ +#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNTCOMP */ +#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1COMP */ +#define PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT (_PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1COMP */ +#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNTCOMP */ +#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNTCOMP */ +#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1COMP */ +#define PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT (_PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1COMP */ + +/* Bit fields for PROTIMER LBTCTRL */ +#define _PROTIMER_LBTCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MASK 0x0F1F1FFFUL /**< Mask for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_SHIFT 0 /**< Shift value for PROTIMER_STARTEXP */ +#define _PROTIMER_LBTCTRL_STARTEXP_MASK 0xFUL /**< Bit mask for PROTIMER_STARTEXP */ +#define _PROTIMER_LBTCTRL_STARTEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP0 0x00000000UL /**< Mode EXP0 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP1 0x00000001UL /**< Mode EXP1 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP2 0x00000002UL /**< Mode EXP2 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP3 0x00000003UL /**< Mode EXP3 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP4 0x00000004UL /**< Mode EXP4 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP5 0x00000005UL /**< Mode EXP5 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP6 0x00000006UL /**< Mode EXP6 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP7 0x00000007UL /**< Mode EXP7 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_STARTEXP_EXP8 0x00000008UL /**< Mode EXP8 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_DEFAULT (_PROTIMER_LBTCTRL_STARTEXP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP0 (_PROTIMER_LBTCTRL_STARTEXP_EXP0 << 0) /**< Shifted mode EXP0 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP1 (_PROTIMER_LBTCTRL_STARTEXP_EXP1 << 0) /**< Shifted mode EXP1 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP2 (_PROTIMER_LBTCTRL_STARTEXP_EXP2 << 0) /**< Shifted mode EXP2 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP3 (_PROTIMER_LBTCTRL_STARTEXP_EXP3 << 0) /**< Shifted mode EXP3 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP4 (_PROTIMER_LBTCTRL_STARTEXP_EXP4 << 0) /**< Shifted mode EXP4 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP5 (_PROTIMER_LBTCTRL_STARTEXP_EXP5 << 0) /**< Shifted mode EXP5 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP6 (_PROTIMER_LBTCTRL_STARTEXP_EXP6 << 0) /**< Shifted mode EXP6 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP7 (_PROTIMER_LBTCTRL_STARTEXP_EXP7 << 0) /**< Shifted mode EXP7 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_STARTEXP_EXP8 (_PROTIMER_LBTCTRL_STARTEXP_EXP8 << 0) /**< Shifted mode EXP8 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_SHIFT 4 /**< Shift value for PROTIMER_MAXEXP */ +#define _PROTIMER_LBTCTRL_MAXEXP_MASK 0xF0UL /**< Bit mask for PROTIMER_MAXEXP */ +#define _PROTIMER_LBTCTRL_MAXEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP0 0x00000000UL /**< Mode EXP0 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP1 0x00000001UL /**< Mode EXP1 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP2 0x00000002UL /**< Mode EXP2 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP3 0x00000003UL /**< Mode EXP3 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP4 0x00000004UL /**< Mode EXP4 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP5 0x00000005UL /**< Mode EXP5 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP6 0x00000006UL /**< Mode EXP6 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP7 0x00000007UL /**< Mode EXP7 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_MAXEXP_EXP8 0x00000008UL /**< Mode EXP8 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_DEFAULT (_PROTIMER_LBTCTRL_MAXEXP_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP0 (_PROTIMER_LBTCTRL_MAXEXP_EXP0 << 4) /**< Shifted mode EXP0 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP1 (_PROTIMER_LBTCTRL_MAXEXP_EXP1 << 4) /**< Shifted mode EXP1 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP2 (_PROTIMER_LBTCTRL_MAXEXP_EXP2 << 4) /**< Shifted mode EXP2 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP3 (_PROTIMER_LBTCTRL_MAXEXP_EXP3 << 4) /**< Shifted mode EXP3 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP4 (_PROTIMER_LBTCTRL_MAXEXP_EXP4 << 4) /**< Shifted mode EXP4 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP5 (_PROTIMER_LBTCTRL_MAXEXP_EXP5 << 4) /**< Shifted mode EXP5 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP6 (_PROTIMER_LBTCTRL_MAXEXP_EXP6 << 4) /**< Shifted mode EXP6 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP7 (_PROTIMER_LBTCTRL_MAXEXP_EXP7 << 4) /**< Shifted mode EXP7 for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_MAXEXP_EXP8 (_PROTIMER_LBTCTRL_MAXEXP_EXP8 << 4) /**< Shifted mode EXP8 for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_CCADELAY_SHIFT 8 /**< Shift value for PROTIMER_CCADELAY */ +#define _PROTIMER_LBTCTRL_CCADELAY_MASK 0x1F00UL /**< Bit mask for PROTIMER_CCADELAY */ +#define _PROTIMER_LBTCTRL_CCADELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_CCADELAY_DEFAULT (_PROTIMER_LBTCTRL_CCADELAY_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_CCAREPEAT_SHIFT 16 /**< Shift value for PROTIMER_CCAREPEAT */ +#define _PROTIMER_LBTCTRL_CCAREPEAT_MASK 0xF0000UL /**< Bit mask for PROTIMER_CCAREPEAT */ +#define _PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT (_PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_FIXEDBACKOFF (0x1UL << 20) /**< Fixed backoff */ +#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_SHIFT 20 /**< Shift value for PROTIMER_FIXEDBACKOFF */ +#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_MASK 0x100000UL /**< Bit mask for PROTIMER_FIXEDBACKOFF */ +#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT (_PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ +#define _PROTIMER_LBTCTRL_RETRYLIMIT_SHIFT 24 /**< Shift value for PROTIMER_RETRYLIMIT */ +#define _PROTIMER_LBTCTRL_RETRYLIMIT_MASK 0xF000000UL /**< Bit mask for PROTIMER_RETRYLIMIT */ +#define _PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */ +#define PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT (_PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */ + +/* Bit fields for PROTIMER LBTPRSCTRL */ +#define _PROTIMER_LBTPRSCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTPRSCTRL */ +#define _PROTIMER_LBTPRSCTRL_MASK 0x01010100UL /**< Mask for PROTIMER_LBTPRSCTRL */ +#define PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN (0x1UL << 8) /**< Enable LBT start commands from PRS. */ +#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_SHIFT 8 /**< Shift value for PROTIMER_LBTSTARTPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_MASK 0x100UL /**< Bit mask for PROTIMER_LBTSTARTPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */ +#define PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/ +#define PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN (0x1UL << 16) /**< Enable LBT pause commands from PRS. */ +#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_SHIFT 16 /**< Shift value for PROTIMER_LBTPAUSEPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_MASK 0x10000UL /**< Bit mask for PROTIMER_LBTPAUSEPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */ +#define PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/ +#define PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN (0x1UL << 24) /**< Enable LBT stop commands from PRS. */ +#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_SHIFT 24 /**< Shift value for PROTIMER_LBTSTOPPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSTOPPRSEN */ +#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */ +#define PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/ + +/* Bit fields for PROTIMER LBTSTATE */ +#define _PROTIMER_LBTSTATE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTSTATE */ +#define _PROTIMER_LBTSTATE_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_LBTSTATE */ +#define _PROTIMER_LBTSTATE_TOUT0PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNT */ +#define _PROTIMER_LBTSTATE_TOUT0PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNT */ +#define _PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE */ +#define PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT (_PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE */ +#define _PROTIMER_LBTSTATE_TOUT0CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNT */ +#define _PROTIMER_LBTSTATE_TOUT0CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNT */ +#define _PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE */ +#define PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT (_PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE */ + +/* Bit fields for PROTIMER RANDOM */ +#define _PROTIMER_RANDOM_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOM */ +#define _PROTIMER_RANDOM_MASK 0x0000FFFFUL /**< Mask for PROTIMER_RANDOM */ +#define _PROTIMER_RANDOM_RANDOM_SHIFT 0 /**< Shift value for PROTIMER_RANDOM */ +#define _PROTIMER_RANDOM_RANDOM_MASK 0xFFFFUL /**< Bit mask for PROTIMER_RANDOM */ +#define _PROTIMER_RANDOM_RANDOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOM */ +#define PROTIMER_RANDOM_RANDOM_DEFAULT (_PROTIMER_RANDOM_RANDOM_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOM */ + +/* Bit fields for PROTIMER IF */ +#define _PROTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_IF */ +#define _PROTIMER_IF_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_IF */ +#define PROTIMER_IF_PRECNTOF (0x1UL << 0) /**< PRECNT Overflow Interrupt Flag */ +#define _PROTIMER_IF_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */ +#define _PROTIMER_IF_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */ +#define _PROTIMER_IF_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_PRECNTOF_DEFAULT (_PROTIMER_IF_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_BASECNTOF (0x1UL << 1) /**< BASECNT Overflow Interrupt Flag */ +#define _PROTIMER_IF_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */ +#define _PROTIMER_IF_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */ +#define _PROTIMER_IF_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_BASECNTOF_DEFAULT (_PROTIMER_IF_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_WRAPCNTOF (0x1UL << 2) /**< WRAPCNT Overflow Interrupt Flag */ +#define _PROTIMER_IF_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_IF_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_IF_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_WRAPCNTOF_DEFAULT (_PROTIMER_IF_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0 (0x1UL << 4) /**< TOUT0 underflow interrupt flag */ +#define _PROTIMER_IF_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */ +#define _PROTIMER_IF_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */ +#define _PROTIMER_IF_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0_DEFAULT (_PROTIMER_IF_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT1 (0x1UL << 5) /**< TOUT1 underflow interrupt flag */ +#define _PROTIMER_IF_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */ +#define _PROTIMER_IF_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */ +#define _PROTIMER_IF_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT1_DEFAULT (_PROTIMER_IF_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0MATCH (0x1UL << 6) /**< TOUT0 compare match interrupt flag */ +#define _PROTIMER_IF_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_IF_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_IF_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0MATCH_DEFAULT (_PROTIMER_IF_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT1MATCH (0x1UL << 7) /**< TOUT1 compare match interrupt flag */ +#define _PROTIMER_IF_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_IF_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_IF_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT1MATCH_DEFAULT (_PROTIMER_IF_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC0 (0x1UL << 8) /**< CC Channel 0 Interrupt Flag */ +#define _PROTIMER_IF_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */ +#define _PROTIMER_IF_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */ +#define _PROTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC0_DEFAULT (_PROTIMER_IF_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC1 (0x1UL << 9) /**< CC Channel 1 Interrupt Flag */ +#define _PROTIMER_IF_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */ +#define _PROTIMER_IF_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */ +#define _PROTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC1_DEFAULT (_PROTIMER_IF_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC2 (0x1UL << 10) /**< CC Channel 2 Interrupt Flag */ +#define _PROTIMER_IF_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */ +#define _PROTIMER_IF_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */ +#define _PROTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC2_DEFAULT (_PROTIMER_IF_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC3 (0x1UL << 11) /**< CC Channel 3 Interrupt Flag */ +#define _PROTIMER_IF_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */ +#define _PROTIMER_IF_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */ +#define _PROTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC3_DEFAULT (_PROTIMER_IF_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC4 (0x1UL << 12) /**< CC Channel 4 Interrupt Flag */ +#define _PROTIMER_IF_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */ +#define _PROTIMER_IF_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */ +#define _PROTIMER_IF_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC4_DEFAULT (_PROTIMER_IF_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC5 (0x1UL << 13) /**< CC Channel 5 Interrupt Flag */ +#define _PROTIMER_IF_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */ +#define _PROTIMER_IF_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */ +#define _PROTIMER_IF_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC5_DEFAULT (_PROTIMER_IF_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC6 (0x1UL << 14) /**< CC Channel 6 Interrupt Flag */ +#define _PROTIMER_IF_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */ +#define _PROTIMER_IF_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */ +#define _PROTIMER_IF_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC6_DEFAULT (_PROTIMER_IF_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC7 (0x1UL << 15) /**< CC Channel 7 Interrupt Flag */ +#define _PROTIMER_IF_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */ +#define _PROTIMER_IF_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */ +#define _PROTIMER_IF_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_CC7_DEFAULT (_PROTIMER_IF_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF0 (0x1UL << 16) /**< CC Channel 0 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */ +#define _PROTIMER_IF_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */ +#define _PROTIMER_IF_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF0_DEFAULT (_PROTIMER_IF_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF1 (0x1UL << 17) /**< CC Channel 1 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */ +#define _PROTIMER_IF_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */ +#define _PROTIMER_IF_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF1_DEFAULT (_PROTIMER_IF_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF2 (0x1UL << 18) /**< CC Channel 2 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */ +#define _PROTIMER_IF_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */ +#define _PROTIMER_IF_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF2_DEFAULT (_PROTIMER_IF_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF3 (0x1UL << 19) /**< CC Channel 3 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */ +#define _PROTIMER_IF_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */ +#define _PROTIMER_IF_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF3_DEFAULT (_PROTIMER_IF_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF4 (0x1UL << 20) /**< CC Channel 4 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */ +#define _PROTIMER_IF_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */ +#define _PROTIMER_IF_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF4_DEFAULT (_PROTIMER_IF_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF5 (0x1UL << 21) /**< CC Channel 5 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */ +#define _PROTIMER_IF_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */ +#define _PROTIMER_IF_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF5_DEFAULT (_PROTIMER_IF_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF6 (0x1UL << 22) /**< CC Channel 6 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */ +#define _PROTIMER_IF_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */ +#define _PROTIMER_IF_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF6_DEFAULT (_PROTIMER_IF_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF7 (0x1UL << 23) /**< CC Channel 7 Overflow Interrupt Flag */ +#define _PROTIMER_IF_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */ +#define _PROTIMER_IF_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */ +#define _PROTIMER_IF_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_COF7_DEFAULT (_PROTIMER_IF_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTSUCCESS (0x1UL << 24) /**< Listen Before Talk Success */ +#define _PROTIMER_IF_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_IF_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_IF_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTSUCCESS_DEFAULT (_PROTIMER_IF_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTFAILURE (0x1UL << 25) /**< Listen Before Talk Failure */ +#define _PROTIMER_IF_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */ +#define _PROTIMER_IF_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */ +#define _PROTIMER_IF_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTFAILURE_DEFAULT (_PROTIMER_IF_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTPAUSED (0x1UL << 26) /**< Listen Before Talk Paused */ +#define _PROTIMER_IF_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */ +#define _PROTIMER_IF_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */ +#define _PROTIMER_IF_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTPAUSED_DEFAULT (_PROTIMER_IF_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTRETRY (0x1UL << 27) /**< Listen Before Talk Retry */ +#define _PROTIMER_IF_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */ +#define _PROTIMER_IF_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */ +#define _PROTIMER_IF_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_LBTRETRY_DEFAULT (_PROTIMER_IF_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_RTCCSYNCHED (0x1UL << 28) /**< PROTIMER synchronized with the RTCC */ +#define _PROTIMER_IF_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_IF_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_IF_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_RTCCSYNCHED_DEFAULT (_PROTIMER_IF_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0 compare match interrupt flag */ +#define _PROTIMER_IF_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_IF_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_IF_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */ +#define PROTIMER_IF_TOUT0MATCHLBT_DEFAULT (_PROTIMER_IF_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_IF */ + +/* Bit fields for PROTIMER IEN */ +#define _PROTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_IEN */ +#define _PROTIMER_IEN_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_IEN */ +#define PROTIMER_IEN_PRECNTOF (0x1UL << 0) /**< PRECNTOF Interrupt Enable */ +#define _PROTIMER_IEN_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */ +#define _PROTIMER_IEN_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */ +#define _PROTIMER_IEN_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_PRECNTOF_DEFAULT (_PROTIMER_IEN_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_BASECNTOF (0x1UL << 1) /**< BASECNTOF Interrupt Enable */ +#define _PROTIMER_IEN_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */ +#define _PROTIMER_IEN_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */ +#define _PROTIMER_IEN_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_BASECNTOF_DEFAULT (_PROTIMER_IEN_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_WRAPCNTOF (0x1UL << 2) /**< WRAPCNTOF Interrupt Enable */ +#define _PROTIMER_IEN_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_IEN_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_IEN_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_WRAPCNTOF_DEFAULT (_PROTIMER_IEN_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0 (0x1UL << 4) /**< TOUT0 Interrupt Enable */ +#define _PROTIMER_IEN_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */ +#define _PROTIMER_IEN_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */ +#define _PROTIMER_IEN_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0_DEFAULT (_PROTIMER_IEN_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT1 (0x1UL << 5) /**< TOUT1 Interrupt Enable */ +#define _PROTIMER_IEN_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */ +#define _PROTIMER_IEN_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */ +#define _PROTIMER_IEN_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT1_DEFAULT (_PROTIMER_IEN_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0MATCH (0x1UL << 6) /**< TOUT0MATCH Interrupt Enable */ +#define _PROTIMER_IEN_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_IEN_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_IEN_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0MATCH_DEFAULT (_PROTIMER_IEN_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT1MATCH (0x1UL << 7) /**< TOUT1MATCH Interrupt Enable */ +#define _PROTIMER_IEN_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_IEN_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_IEN_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT1MATCH_DEFAULT (_PROTIMER_IEN_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC0 (0x1UL << 8) /**< CC0 Interrupt Enable */ +#define _PROTIMER_IEN_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */ +#define _PROTIMER_IEN_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */ +#define _PROTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC0_DEFAULT (_PROTIMER_IEN_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC1 (0x1UL << 9) /**< CC1 Interrupt Enable */ +#define _PROTIMER_IEN_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */ +#define _PROTIMER_IEN_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */ +#define _PROTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC1_DEFAULT (_PROTIMER_IEN_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC2 (0x1UL << 10) /**< CC2 Interrupt Enable */ +#define _PROTIMER_IEN_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */ +#define _PROTIMER_IEN_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */ +#define _PROTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC2_DEFAULT (_PROTIMER_IEN_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC3 (0x1UL << 11) /**< CC3 Interrupt Enable */ +#define _PROTIMER_IEN_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */ +#define _PROTIMER_IEN_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */ +#define _PROTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC3_DEFAULT (_PROTIMER_IEN_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC4 (0x1UL << 12) /**< CC4 Interrupt Enable */ +#define _PROTIMER_IEN_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */ +#define _PROTIMER_IEN_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */ +#define _PROTIMER_IEN_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC4_DEFAULT (_PROTIMER_IEN_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC5 (0x1UL << 13) /**< CC5 Interrupt Enable */ +#define _PROTIMER_IEN_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */ +#define _PROTIMER_IEN_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */ +#define _PROTIMER_IEN_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC5_DEFAULT (_PROTIMER_IEN_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC6 (0x1UL << 14) /**< CC6 Interrupt Enable */ +#define _PROTIMER_IEN_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */ +#define _PROTIMER_IEN_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */ +#define _PROTIMER_IEN_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC6_DEFAULT (_PROTIMER_IEN_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC7 (0x1UL << 15) /**< CC7 Interrupt Enable */ +#define _PROTIMER_IEN_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */ +#define _PROTIMER_IEN_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */ +#define _PROTIMER_IEN_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_CC7_DEFAULT (_PROTIMER_IEN_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF0 (0x1UL << 16) /**< COF0 Interrupt Enable */ +#define _PROTIMER_IEN_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */ +#define _PROTIMER_IEN_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */ +#define _PROTIMER_IEN_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF0_DEFAULT (_PROTIMER_IEN_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF1 (0x1UL << 17) /**< COF1 Interrupt Enable */ +#define _PROTIMER_IEN_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */ +#define _PROTIMER_IEN_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */ +#define _PROTIMER_IEN_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF1_DEFAULT (_PROTIMER_IEN_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF2 (0x1UL << 18) /**< COF2 Interrupt Enable */ +#define _PROTIMER_IEN_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */ +#define _PROTIMER_IEN_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */ +#define _PROTIMER_IEN_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF2_DEFAULT (_PROTIMER_IEN_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF3 (0x1UL << 19) /**< COF3 Interrupt Enable */ +#define _PROTIMER_IEN_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */ +#define _PROTIMER_IEN_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */ +#define _PROTIMER_IEN_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF3_DEFAULT (_PROTIMER_IEN_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF4 (0x1UL << 20) /**< COF4 Interrupt Enable */ +#define _PROTIMER_IEN_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */ +#define _PROTIMER_IEN_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */ +#define _PROTIMER_IEN_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF4_DEFAULT (_PROTIMER_IEN_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF5 (0x1UL << 21) /**< COF5 Interrupt Enable */ +#define _PROTIMER_IEN_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */ +#define _PROTIMER_IEN_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */ +#define _PROTIMER_IEN_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF5_DEFAULT (_PROTIMER_IEN_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF6 (0x1UL << 22) /**< COF6 Interrupt Enable */ +#define _PROTIMER_IEN_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */ +#define _PROTIMER_IEN_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */ +#define _PROTIMER_IEN_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF6_DEFAULT (_PROTIMER_IEN_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF7 (0x1UL << 23) /**< COF7 Interrupt Enable */ +#define _PROTIMER_IEN_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */ +#define _PROTIMER_IEN_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */ +#define _PROTIMER_IEN_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_COF7_DEFAULT (_PROTIMER_IEN_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTSUCCESS (0x1UL << 24) /**< LBTSUCCESS Interrupt Enable */ +#define _PROTIMER_IEN_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_IEN_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_IEN_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTSUCCESS_DEFAULT (_PROTIMER_IEN_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTFAILURE (0x1UL << 25) /**< LBTFAILURE Interrupt Enable */ +#define _PROTIMER_IEN_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */ +#define _PROTIMER_IEN_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */ +#define _PROTIMER_IEN_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTFAILURE_DEFAULT (_PROTIMER_IEN_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTPAUSED (0x1UL << 26) /**< LBTPAUSED Interrupt Enable */ +#define _PROTIMER_IEN_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */ +#define _PROTIMER_IEN_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */ +#define _PROTIMER_IEN_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTPAUSED_DEFAULT (_PROTIMER_IEN_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTRETRY (0x1UL << 27) /**< LBTRETRY Interrupt Enable */ +#define _PROTIMER_IEN_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */ +#define _PROTIMER_IEN_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */ +#define _PROTIMER_IEN_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_LBTRETRY_DEFAULT (_PROTIMER_IEN_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_RTCCSYNCHED (0x1UL << 28) /**< RTCCSYNCHED Interrupt Enable */ +#define _PROTIMER_IEN_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_IEN_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_IEN_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_RTCCSYNCHED_DEFAULT (_PROTIMER_IEN_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0MATCHLBT Interrupt Enable */ +#define _PROTIMER_IEN_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_IEN_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */ +#define PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT (_PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_IEN */ + +/* Bit fields for PROTIMER RXCTRL */ +#define _PROTIMER_RXCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_MASK 0x1F1F1F1FUL /**< Mask for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_SHIFT 0 /**< Shift value for PROTIMER_RXSETEVENT1 */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_MASK 0x1FUL /**< Bit mask for PROTIMER_RXSETEVENT1 */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS 0x00000001UL /**< Mode ALWAYS for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF 0x00000002UL /**< Mode PRECNTOF for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF 0x00000003UL /**< Mode BASECNTOF for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF 0x00000004UL /**< Mode WRAPCNTOF for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF 0x00000005UL /**< Mode TOUT0UF for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF 0x00000006UL /**< Mode TOUT1UF for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH 0x00000007UL /**< Mode TOUT0MATCH for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH 0x00000008UL /**< Mode TOUT1MATCH for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CC0 0x00000009UL /**< Mode CC0 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CC1 0x0000000AUL /**< Mode CC1 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CC2 0x0000000BUL /**< Mode CC2 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CC3 0x0000000CUL /**< Mode CC3 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CC4 0x0000000DUL /**< Mode CC4 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TXDONE 0x0000000EUL /**< Mode TXDONE for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_RXDONE 0x0000000FUL /**< Mode RXDONE for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE 0x00000010UL /**< Mode TXORRXDONE for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET0 0x00000011UL /**< Mode FDET0 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET1 0x00000012UL /**< Mode FDET1 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 0x00000013UL /**< Mode FDET0OR1 for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS 0x00000014UL /**< Mode LBTSUCCESS for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY 0x00000015UL /**< Mode LBTRETRY for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE 0x00000016UL /**< Mode LBTFAILURE for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT 0x00000017UL /**< Mode ANYLBT for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CCAACK 0x00000018UL /**< Mode CCAACK for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_CCA 0x00000019UL /**< Mode CCA for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA 0x0000001AUL /**< Mode NOTCCA for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT 0x0000001BUL /**< Mode TOUT0MATCHLBT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT (_PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_DISABLED (_PROTIMER_RXCTRL_RXSETEVENT1_DISABLED << 0) /**< Shifted mode DISABLED for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS (_PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS << 0) /**< Shifted mode ALWAYS for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF << 0) /**< Shifted mode PRECNTOF for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF << 0) /**< Shifted mode BASECNTOF for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF << 0) /**< Shifted mode WRAPCNTOF for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF << 0) /**< Shifted mode TOUT0UF for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF << 0) /**< Shifted mode TOUT1UF for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH << 0) /**< Shifted mode TOUT0MATCH for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH << 0) /**< Shifted mode TOUT1MATCH for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CC0 (_PROTIMER_RXCTRL_RXSETEVENT1_CC0 << 0) /**< Shifted mode CC0 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CC1 (_PROTIMER_RXCTRL_RXSETEVENT1_CC1 << 0) /**< Shifted mode CC1 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CC2 (_PROTIMER_RXCTRL_RXSETEVENT1_CC2 << 0) /**< Shifted mode CC2 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CC3 (_PROTIMER_RXCTRL_RXSETEVENT1_CC3 << 0) /**< Shifted mode CC3 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CC4 (_PROTIMER_RXCTRL_RXSETEVENT1_CC4 << 0) /**< Shifted mode CC4 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_TXDONE << 0) /**< Shifted mode TXDONE for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_RXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_RXDONE << 0) /**< Shifted mode RXDONE for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE << 0) /**< Shifted mode TXORRXDONE for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_FDET0 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET0 << 0) /**< Shifted mode FDET0 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_FDET1 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET1 << 0) /**< Shifted mode FDET1 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 << 0) /**< Shifted mode FDET0OR1 for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS (_PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS << 0) /**< Shifted mode LBTSUCCESS for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY (_PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY << 0) /**< Shifted mode LBTRETRY for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE (_PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE << 0) /**< Shifted mode LBTFAILURE for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT (_PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT << 0) /**< Shifted mode ANYLBT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CCAACK (_PROTIMER_RXCTRL_RXSETEVENT1_CCAACK << 0) /**< Shifted mode CCAACK for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_CCA (_PROTIMER_RXCTRL_RXSETEVENT1_CCA << 0) /**< Shifted mode CCA for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA (_PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA << 0) /**< Shifted mode NOTCCA for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT << 0) /**< Shifted mode TOUT0MATCHLBT for PROTIMER_RXCTRL*/ +#define _PROTIMER_RXCTRL_RXSETEVENT2_SHIFT 8 /**< Shift value for PROTIMER_RXSETEVENT2 */ +#define _PROTIMER_RXCTRL_RXSETEVENT2_MASK 0x1F00UL /**< Bit mask for PROTIMER_RXSETEVENT2 */ +#define _PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT (_PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXCLREVENT1_SHIFT 16 /**< Shift value for PROTIMER_RXCLREVENT1 */ +#define _PROTIMER_RXCTRL_RXCLREVENT1_MASK 0x1F0000UL /**< Bit mask for PROTIMER_RXCLREVENT1 */ +#define _PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT (_PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */ +#define _PROTIMER_RXCTRL_RXCLREVENT2_SHIFT 24 /**< Shift value for PROTIMER_RXCLREVENT2 */ +#define _PROTIMER_RXCTRL_RXCLREVENT2_MASK 0x1F000000UL /**< Bit mask for PROTIMER_RXCLREVENT2 */ +#define _PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */ +#define PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT (_PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */ + +/* Bit fields for PROTIMER TXCTRL */ +#define _PROTIMER_TXCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_MASK 0x00001F1FUL /**< Mask for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_SHIFT 0 /**< Shift value for PROTIMER_TXSETEVENT1 */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_MASK 0x1FUL /**< Bit mask for PROTIMER_TXSETEVENT1 */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS 0x00000001UL /**< Mode ALWAYS for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF 0x00000002UL /**< Mode PRECNTOF for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF 0x00000003UL /**< Mode BASECNTOF for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF 0x00000004UL /**< Mode WRAPCNTOF for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF 0x00000005UL /**< Mode TOUT0UF for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF 0x00000006UL /**< Mode TOUT1UF for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH 0x00000007UL /**< Mode TOUT0MATCH for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH 0x00000008UL /**< Mode TOUT1MATCH for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CC0 0x00000009UL /**< Mode CC0 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CC1 0x0000000AUL /**< Mode CC1 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CC2 0x0000000BUL /**< Mode CC2 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CC3 0x0000000CUL /**< Mode CC3 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CC4 0x0000000DUL /**< Mode CC4 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TXDONE 0x0000000EUL /**< Mode TXDONE for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_RXDONE 0x0000000FUL /**< Mode RXDONE for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE 0x00000010UL /**< Mode TXORRXDONE for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET0 0x00000011UL /**< Mode FDET0 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET1 0x00000012UL /**< Mode FDET1 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 0x00000013UL /**< Mode FDET0OR1 for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS 0x00000014UL /**< Mode LBTSUCCESS for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY 0x00000015UL /**< Mode LBTRETRY for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE 0x00000016UL /**< Mode LBTFAILURE for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT 0x00000017UL /**< Mode ANYLBT for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CCAACK 0x00000018UL /**< Mode CCAACK for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_CCA 0x00000019UL /**< Mode CCA for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA 0x0000001AUL /**< Mode NOTCCA for PROTIMER_TXCTRL */ +#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT 0x0000001BUL /**< Mode TOUT0MATCHLBT for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT (_PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_DISABLED (_PROTIMER_TXCTRL_TXSETEVENT1_DISABLED << 0) /**< Shifted mode DISABLED for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS (_PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS << 0) /**< Shifted mode ALWAYS for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF << 0) /**< Shifted mode PRECNTOF for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF << 0) /**< Shifted mode BASECNTOF for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF << 0) /**< Shifted mode WRAPCNTOF for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF << 0) /**< Shifted mode TOUT0UF for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF << 0) /**< Shifted mode TOUT1UF for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH << 0) /**< Shifted mode TOUT0MATCH for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH << 0) /**< Shifted mode TOUT1MATCH for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CC0 (_PROTIMER_TXCTRL_TXSETEVENT1_CC0 << 0) /**< Shifted mode CC0 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CC1 (_PROTIMER_TXCTRL_TXSETEVENT1_CC1 << 0) /**< Shifted mode CC1 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CC2 (_PROTIMER_TXCTRL_TXSETEVENT1_CC2 << 0) /**< Shifted mode CC2 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CC3 (_PROTIMER_TXCTRL_TXSETEVENT1_CC3 << 0) /**< Shifted mode CC3 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CC4 (_PROTIMER_TXCTRL_TXSETEVENT1_CC4 << 0) /**< Shifted mode CC4 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_TXDONE << 0) /**< Shifted mode TXDONE for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_RXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_RXDONE << 0) /**< Shifted mode RXDONE for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE << 0) /**< Shifted mode TXORRXDONE for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_FDET0 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET0 << 0) /**< Shifted mode FDET0 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_FDET1 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET1 << 0) /**< Shifted mode FDET1 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 << 0) /**< Shifted mode FDET0OR1 for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS (_PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS << 0) /**< Shifted mode LBTSUCCESS for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY (_PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY << 0) /**< Shifted mode LBTRETRY for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE (_PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE << 0) /**< Shifted mode LBTFAILURE for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT (_PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT << 0) /**< Shifted mode ANYLBT for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CCAACK (_PROTIMER_TXCTRL_TXSETEVENT1_CCAACK << 0) /**< Shifted mode CCAACK for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_CCA (_PROTIMER_TXCTRL_TXSETEVENT1_CCA << 0) /**< Shifted mode CCA for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA (_PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA << 0) /**< Shifted mode NOTCCA for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT << 0) /**< Shifted mode TOUT0MATCHLBT for PROTIMER_TXCTRL*/ +#define _PROTIMER_TXCTRL_TXSETEVENT2_SHIFT 8 /**< Shift value for PROTIMER_TXSETEVENT2 */ +#define _PROTIMER_TXCTRL_TXSETEVENT2_MASK 0x1F00UL /**< Bit mask for PROTIMER_TXSETEVENT2 */ +#define _PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TXCTRL */ +#define PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT (_PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_TXCTRL */ + +/* Bit fields for PROTIMER ETSI */ +#define _PROTIMER_ETSI_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_ETSI */ +#define _PROTIMER_ETSI_MASK 0x03FFFFFFUL /**< Mask for PROTIMER_ETSI */ +#define PROTIMER_ETSI_ETSIEN (0x1UL << 0) /**< ETSI LBT enabling */ +#define _PROTIMER_ETSI_ETSIEN_SHIFT 0 /**< Shift value for PROTIMER_ETSIEN */ +#define _PROTIMER_ETSI_ETSIEN_MASK 0x1UL /**< Bit mask for PROTIMER_ETSIEN */ +#define _PROTIMER_ETSI_ETSIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */ +#define PROTIMER_ETSI_ETSIEN_DEFAULT (_PROTIMER_ETSI_ETSIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_ETSI */ +#define PROTIMER_ETSI_GRANULARLESSTHANRXWARM (0x1UL << 1) /**< Granular less than RXWARM */ +#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_SHIFT 1 /**< Shift value for PROTIMER_GRANULARLESSTHANRXWARM*/ +#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_MASK 0x2UL /**< Bit mask for PROTIMER_GRANULARLESSTHANRXWARM*/ +#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */ +#define PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT (_PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_ETSI */ +#define _PROTIMER_ETSI_RXWARMTHLD_SHIFT 2 /**< Shift value for PROTIMER_RXWARMTHLD */ +#define _PROTIMER_ETSI_RXWARMTHLD_MASK 0x3FCUL /**< Bit mask for PROTIMER_RXWARMTHLD */ +#define _PROTIMER_ETSI_RXWARMTHLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */ +#define PROTIMER_ETSI_RXWARMTHLD_DEFAULT (_PROTIMER_ETSI_RXWARMTHLD_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_ETSI */ +#define _PROTIMER_ETSI_CCAFIXED_SHIFT 10 /**< Shift value for PROTIMER_CCAFIXED */ +#define _PROTIMER_ETSI_CCAFIXED_MASK 0x3FFFC00UL /**< Bit mask for PROTIMER_CCAFIXED */ +#define _PROTIMER_ETSI_CCAFIXED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */ +#define PROTIMER_ETSI_CCAFIXED_DEFAULT (_PROTIMER_ETSI_CCAFIXED_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_ETSI */ + +/* Bit fields for PROTIMER LBTSTATE1 */ +#define _PROTIMER_LBTSTATE1_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTSTATE1 */ +#define _PROTIMER_LBTSTATE1_MASK 0x00000FFFUL /**< Mask for PROTIMER_LBTSTATE1 */ +#define _PROTIMER_LBTSTATE1_CCACNT_SHIFT 0 /**< Shift value for PROTIMER_CCACNT */ +#define _PROTIMER_LBTSTATE1_CCACNT_MASK 0xFUL /**< Bit mask for PROTIMER_CCACNT */ +#define _PROTIMER_LBTSTATE1_CCACNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */ +#define PROTIMER_LBTSTATE1_CCACNT_DEFAULT (_PROTIMER_LBTSTATE1_CCACNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */ +#define _PROTIMER_LBTSTATE1_EXP_SHIFT 4 /**< Shift value for PROTIMER_EXP */ +#define _PROTIMER_LBTSTATE1_EXP_MASK 0xF0UL /**< Bit mask for PROTIMER_EXP */ +#define _PROTIMER_LBTSTATE1_EXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */ +#define PROTIMER_LBTSTATE1_EXP_DEFAULT (_PROTIMER_LBTSTATE1_EXP_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */ +#define _PROTIMER_LBTSTATE1_RETRYCNT_SHIFT 8 /**< Shift value for PROTIMER_RETRYCNT */ +#define _PROTIMER_LBTSTATE1_RETRYCNT_MASK 0xF00UL /**< Bit mask for PROTIMER_RETRYCNT */ +#define _PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */ +#define PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT (_PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */ + +/* Bit fields for PROTIMER RANDOMFW0 */ +#define _PROTIMER_RANDOMFW0_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW0 */ +#define _PROTIMER_RANDOMFW0_MASK 0x07FFFFFFUL /**< Mask for PROTIMER_RANDOMFW0 */ +#define _PROTIMER_RANDOMFW0_RANDOM0_SHIFT 0 /**< Shift value for PROTIMER_RANDOM0 */ +#define _PROTIMER_RANDOMFW0_RANDOM0_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM0 */ +#define _PROTIMER_RANDOMFW0_RANDOM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */ +#define PROTIMER_RANDOMFW0_RANDOM0_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM0_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */ +#define _PROTIMER_RANDOMFW0_RANDOM1_SHIFT 9 /**< Shift value for PROTIMER_RANDOM1 */ +#define _PROTIMER_RANDOMFW0_RANDOM1_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM1 */ +#define _PROTIMER_RANDOMFW0_RANDOM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */ +#define PROTIMER_RANDOMFW0_RANDOM1_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */ +#define _PROTIMER_RANDOMFW0_RANDOM2_SHIFT 18 /**< Shift value for PROTIMER_RANDOM2 */ +#define _PROTIMER_RANDOMFW0_RANDOM2_MASK 0x7FC0000UL /**< Bit mask for PROTIMER_RANDOM2 */ +#define _PROTIMER_RANDOMFW0_RANDOM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */ +#define PROTIMER_RANDOMFW0_RANDOM2_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */ + +/* Bit fields for PROTIMER RANDOMFW1 */ +#define _PROTIMER_RANDOMFW1_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW1 */ +#define _PROTIMER_RANDOMFW1_MASK 0x07FFFFFFUL /**< Mask for PROTIMER_RANDOMFW1 */ +#define _PROTIMER_RANDOMFW1_RANDOM3_SHIFT 0 /**< Shift value for PROTIMER_RANDOM3 */ +#define _PROTIMER_RANDOMFW1_RANDOM3_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM3 */ +#define _PROTIMER_RANDOMFW1_RANDOM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */ +#define PROTIMER_RANDOMFW1_RANDOM3_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM3_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */ +#define _PROTIMER_RANDOMFW1_RANDOM4_SHIFT 9 /**< Shift value for PROTIMER_RANDOM4 */ +#define _PROTIMER_RANDOMFW1_RANDOM4_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM4 */ +#define _PROTIMER_RANDOMFW1_RANDOM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */ +#define PROTIMER_RANDOMFW1_RANDOM4_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM4_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */ +#define _PROTIMER_RANDOMFW1_RANDOM5_SHIFT 18 /**< Shift value for PROTIMER_RANDOM5 */ +#define _PROTIMER_RANDOMFW1_RANDOM5_MASK 0x7FC0000UL /**< Bit mask for PROTIMER_RANDOM5 */ +#define _PROTIMER_RANDOMFW1_RANDOM5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */ +#define PROTIMER_RANDOMFW1_RANDOM5_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM5_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */ + +/* Bit fields for PROTIMER RANDOMFW2 */ +#define _PROTIMER_RANDOMFW2_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW2 */ +#define _PROTIMER_RANDOMFW2_MASK 0x0003FFFFUL /**< Mask for PROTIMER_RANDOMFW2 */ +#define _PROTIMER_RANDOMFW2_RANDOM6_SHIFT 0 /**< Shift value for PROTIMER_RANDOM6 */ +#define _PROTIMER_RANDOMFW2_RANDOM6_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM6 */ +#define _PROTIMER_RANDOMFW2_RANDOM6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW2 */ +#define PROTIMER_RANDOMFW2_RANDOM6_DEFAULT (_PROTIMER_RANDOMFW2_RANDOM6_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW2 */ +#define _PROTIMER_RANDOMFW2_RANDOM7_SHIFT 9 /**< Shift value for PROTIMER_RANDOM7 */ +#define _PROTIMER_RANDOMFW2_RANDOM7_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM7 */ +#define _PROTIMER_RANDOMFW2_RANDOM7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW2 */ +#define PROTIMER_RANDOMFW2_RANDOM7_DEFAULT (_PROTIMER_RANDOMFW2_RANDOM7_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW2 */ + +/* Bit fields for PROTIMER SEQIF */ +#define _PROTIMER_SEQIF_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_SEQIF */ +#define _PROTIMER_SEQIF_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_PRECNTOF (0x1UL << 0) /**< PRECNT Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */ +#define _PROTIMER_SEQIF_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */ +#define _PROTIMER_SEQIF_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_PRECNTOF_DEFAULT (_PROTIMER_SEQIF_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_BASECNTOF (0x1UL << 1) /**< BASECNT Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */ +#define _PROTIMER_SEQIF_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */ +#define _PROTIMER_SEQIF_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_BASECNTOF_DEFAULT (_PROTIMER_SEQIF_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_WRAPCNTOF (0x1UL << 2) /**< WRAPCNT Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_SEQIF_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_SEQIF_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_WRAPCNTOF_DEFAULT (_PROTIMER_SEQIF_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0 (0x1UL << 4) /**< TOUT0 underflow interrupt flag */ +#define _PROTIMER_SEQIF_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */ +#define _PROTIMER_SEQIF_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */ +#define _PROTIMER_SEQIF_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0_DEFAULT (_PROTIMER_SEQIF_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT1 (0x1UL << 5) /**< TOUT1 underflow interrupt flag */ +#define _PROTIMER_SEQIF_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */ +#define _PROTIMER_SEQIF_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */ +#define _PROTIMER_SEQIF_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT1_DEFAULT (_PROTIMER_SEQIF_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0MATCH (0x1UL << 6) /**< TOUT0 compare match interrupt flag */ +#define _PROTIMER_SEQIF_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_SEQIF_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_SEQIF_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0MATCH_DEFAULT (_PROTIMER_SEQIF_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT1MATCH (0x1UL << 7) /**< TOUT1 compare match interrupt flag */ +#define _PROTIMER_SEQIF_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_SEQIF_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_SEQIF_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT1MATCH_DEFAULT (_PROTIMER_SEQIF_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC0 (0x1UL << 8) /**< CC Channel 0 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */ +#define _PROTIMER_SEQIF_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */ +#define _PROTIMER_SEQIF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC0_DEFAULT (_PROTIMER_SEQIF_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC1 (0x1UL << 9) /**< CC Channel 1 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */ +#define _PROTIMER_SEQIF_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */ +#define _PROTIMER_SEQIF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC1_DEFAULT (_PROTIMER_SEQIF_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC2 (0x1UL << 10) /**< CC Channel 2 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */ +#define _PROTIMER_SEQIF_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */ +#define _PROTIMER_SEQIF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC2_DEFAULT (_PROTIMER_SEQIF_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC3 (0x1UL << 11) /**< CC Channel 3 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */ +#define _PROTIMER_SEQIF_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */ +#define _PROTIMER_SEQIF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC3_DEFAULT (_PROTIMER_SEQIF_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC4 (0x1UL << 12) /**< CC Channel 4 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */ +#define _PROTIMER_SEQIF_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */ +#define _PROTIMER_SEQIF_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC4_DEFAULT (_PROTIMER_SEQIF_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC5 (0x1UL << 13) /**< CC Channel 5 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */ +#define _PROTIMER_SEQIF_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */ +#define _PROTIMER_SEQIF_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC5_DEFAULT (_PROTIMER_SEQIF_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC6 (0x1UL << 14) /**< CC Channel 6 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */ +#define _PROTIMER_SEQIF_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */ +#define _PROTIMER_SEQIF_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC6_DEFAULT (_PROTIMER_SEQIF_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC7 (0x1UL << 15) /**< CC Channel 7 Interrupt Flag */ +#define _PROTIMER_SEQIF_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */ +#define _PROTIMER_SEQIF_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */ +#define _PROTIMER_SEQIF_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_CC7_DEFAULT (_PROTIMER_SEQIF_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF0 (0x1UL << 16) /**< CC Channel 0 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */ +#define _PROTIMER_SEQIF_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */ +#define _PROTIMER_SEQIF_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF0_DEFAULT (_PROTIMER_SEQIF_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF1 (0x1UL << 17) /**< CC Channel 1 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */ +#define _PROTIMER_SEQIF_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */ +#define _PROTIMER_SEQIF_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF1_DEFAULT (_PROTIMER_SEQIF_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF2 (0x1UL << 18) /**< CC Channel 2 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */ +#define _PROTIMER_SEQIF_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */ +#define _PROTIMER_SEQIF_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF2_DEFAULT (_PROTIMER_SEQIF_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF3 (0x1UL << 19) /**< CC Channel 3 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */ +#define _PROTIMER_SEQIF_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */ +#define _PROTIMER_SEQIF_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF3_DEFAULT (_PROTIMER_SEQIF_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF4 (0x1UL << 20) /**< CC Channel 4 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */ +#define _PROTIMER_SEQIF_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */ +#define _PROTIMER_SEQIF_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF4_DEFAULT (_PROTIMER_SEQIF_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF5 (0x1UL << 21) /**< CC Channel 5 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */ +#define _PROTIMER_SEQIF_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */ +#define _PROTIMER_SEQIF_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF5_DEFAULT (_PROTIMER_SEQIF_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF6 (0x1UL << 22) /**< CC Channel 6 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */ +#define _PROTIMER_SEQIF_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */ +#define _PROTIMER_SEQIF_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF6_DEFAULT (_PROTIMER_SEQIF_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF7 (0x1UL << 23) /**< CC Channel 7 Overflow Interrupt Flag */ +#define _PROTIMER_SEQIF_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */ +#define _PROTIMER_SEQIF_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */ +#define _PROTIMER_SEQIF_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_COF7_DEFAULT (_PROTIMER_SEQIF_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTSUCCESS (0x1UL << 24) /**< Listen Before Talk Success */ +#define _PROTIMER_SEQIF_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_SEQIF_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_SEQIF_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTSUCCESS_DEFAULT (_PROTIMER_SEQIF_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTFAILURE (0x1UL << 25) /**< Listen Before Talk Failure */ +#define _PROTIMER_SEQIF_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */ +#define _PROTIMER_SEQIF_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */ +#define _PROTIMER_SEQIF_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTFAILURE_DEFAULT (_PROTIMER_SEQIF_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTPAUSED (0x1UL << 26) /**< Listen Before Talk Paused */ +#define _PROTIMER_SEQIF_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */ +#define _PROTIMER_SEQIF_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */ +#define _PROTIMER_SEQIF_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTPAUSED_DEFAULT (_PROTIMER_SEQIF_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTRETRY (0x1UL << 27) /**< Listen Before Talk Retry */ +#define _PROTIMER_SEQIF_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */ +#define _PROTIMER_SEQIF_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */ +#define _PROTIMER_SEQIF_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_LBTRETRY_DEFAULT (_PROTIMER_SEQIF_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_RTCCSYNCHED (0x1UL << 28) /**< PROTIMER synchronized with the RTCC */ +#define _PROTIMER_SEQIF_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_SEQIF_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT (_PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0 compare match interrupt flag */ +#define _PROTIMER_SEQIF_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_SEQIF_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */ +#define PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT (_PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */ + +/* Bit fields for PROTIMER SEQIEN */ +#define _PROTIMER_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_SEQIEN */ +#define _PROTIMER_SEQIEN_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_PRECNTOF (0x1UL << 0) /**< PRECNTOF Interrupt Enable */ +#define _PROTIMER_SEQIEN_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */ +#define _PROTIMER_SEQIEN_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */ +#define _PROTIMER_SEQIEN_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_PRECNTOF_DEFAULT (_PROTIMER_SEQIEN_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_BASECNTOF (0x1UL << 1) /**< BASECNTOF Interrupt Enable */ +#define _PROTIMER_SEQIEN_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */ +#define _PROTIMER_SEQIEN_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */ +#define _PROTIMER_SEQIEN_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_BASECNTOF_DEFAULT (_PROTIMER_SEQIEN_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_WRAPCNTOF (0x1UL << 2) /**< WRAPCNTOF Interrupt Enable */ +#define _PROTIMER_SEQIEN_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_SEQIEN_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */ +#define _PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT (_PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0 (0x1UL << 4) /**< TOUT0 Interrupt Enable */ +#define _PROTIMER_SEQIEN_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */ +#define _PROTIMER_SEQIEN_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */ +#define _PROTIMER_SEQIEN_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0_DEFAULT (_PROTIMER_SEQIEN_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT1 (0x1UL << 5) /**< TOUT1 Interrupt Enable */ +#define _PROTIMER_SEQIEN_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */ +#define _PROTIMER_SEQIEN_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */ +#define _PROTIMER_SEQIEN_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT1_DEFAULT (_PROTIMER_SEQIEN_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0MATCH (0x1UL << 6) /**< TOUT0MATCH Interrupt Enable */ +#define _PROTIMER_SEQIEN_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_SEQIEN_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */ +#define _PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT (_PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT1MATCH (0x1UL << 7) /**< TOUT1MATCH Interrupt Enable */ +#define _PROTIMER_SEQIEN_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_SEQIEN_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */ +#define _PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT (_PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC0 (0x1UL << 8) /**< CC0 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */ +#define _PROTIMER_SEQIEN_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */ +#define _PROTIMER_SEQIEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC0_DEFAULT (_PROTIMER_SEQIEN_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC1 (0x1UL << 9) /**< CC1 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */ +#define _PROTIMER_SEQIEN_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */ +#define _PROTIMER_SEQIEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC1_DEFAULT (_PROTIMER_SEQIEN_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC2 (0x1UL << 10) /**< CC2 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */ +#define _PROTIMER_SEQIEN_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */ +#define _PROTIMER_SEQIEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC2_DEFAULT (_PROTIMER_SEQIEN_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC3 (0x1UL << 11) /**< CC3 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */ +#define _PROTIMER_SEQIEN_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */ +#define _PROTIMER_SEQIEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC3_DEFAULT (_PROTIMER_SEQIEN_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC4 (0x1UL << 12) /**< CC4 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */ +#define _PROTIMER_SEQIEN_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */ +#define _PROTIMER_SEQIEN_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC4_DEFAULT (_PROTIMER_SEQIEN_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC5 (0x1UL << 13) /**< CC5 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */ +#define _PROTIMER_SEQIEN_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */ +#define _PROTIMER_SEQIEN_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC5_DEFAULT (_PROTIMER_SEQIEN_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC6 (0x1UL << 14) /**< CC6 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */ +#define _PROTIMER_SEQIEN_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */ +#define _PROTIMER_SEQIEN_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC6_DEFAULT (_PROTIMER_SEQIEN_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC7 (0x1UL << 15) /**< CC7 Interrupt Enable */ +#define _PROTIMER_SEQIEN_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */ +#define _PROTIMER_SEQIEN_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */ +#define _PROTIMER_SEQIEN_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_CC7_DEFAULT (_PROTIMER_SEQIEN_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF0 (0x1UL << 16) /**< COF0 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */ +#define _PROTIMER_SEQIEN_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */ +#define _PROTIMER_SEQIEN_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF0_DEFAULT (_PROTIMER_SEQIEN_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF1 (0x1UL << 17) /**< COF1 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */ +#define _PROTIMER_SEQIEN_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */ +#define _PROTIMER_SEQIEN_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF1_DEFAULT (_PROTIMER_SEQIEN_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF2 (0x1UL << 18) /**< COF2 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */ +#define _PROTIMER_SEQIEN_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */ +#define _PROTIMER_SEQIEN_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF2_DEFAULT (_PROTIMER_SEQIEN_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF3 (0x1UL << 19) /**< COF3 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */ +#define _PROTIMER_SEQIEN_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */ +#define _PROTIMER_SEQIEN_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF3_DEFAULT (_PROTIMER_SEQIEN_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF4 (0x1UL << 20) /**< COF4 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */ +#define _PROTIMER_SEQIEN_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */ +#define _PROTIMER_SEQIEN_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF4_DEFAULT (_PROTIMER_SEQIEN_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF5 (0x1UL << 21) /**< COF5 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */ +#define _PROTIMER_SEQIEN_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */ +#define _PROTIMER_SEQIEN_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF5_DEFAULT (_PROTIMER_SEQIEN_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF6 (0x1UL << 22) /**< COF6 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */ +#define _PROTIMER_SEQIEN_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */ +#define _PROTIMER_SEQIEN_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF6_DEFAULT (_PROTIMER_SEQIEN_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF7 (0x1UL << 23) /**< COF7 Interrupt Enable */ +#define _PROTIMER_SEQIEN_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */ +#define _PROTIMER_SEQIEN_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */ +#define _PROTIMER_SEQIEN_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_COF7_DEFAULT (_PROTIMER_SEQIEN_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTSUCCESS (0x1UL << 24) /**< LBTSUCCESS Interrupt Enable */ +#define _PROTIMER_SEQIEN_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_SEQIEN_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */ +#define _PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT (_PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTFAILURE (0x1UL << 25) /**< LBTFAILURE Interrupt Enable */ +#define _PROTIMER_SEQIEN_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */ +#define _PROTIMER_SEQIEN_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */ +#define _PROTIMER_SEQIEN_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTFAILURE_DEFAULT (_PROTIMER_SEQIEN_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTPAUSED (0x1UL << 26) /**< LBTPAUSED Interrupt Enable */ +#define _PROTIMER_SEQIEN_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */ +#define _PROTIMER_SEQIEN_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */ +#define _PROTIMER_SEQIEN_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTPAUSED_DEFAULT (_PROTIMER_SEQIEN_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTRETRY (0x1UL << 27) /**< LBTRETRY Interrupt Enable */ +#define _PROTIMER_SEQIEN_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */ +#define _PROTIMER_SEQIEN_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */ +#define _PROTIMER_SEQIEN_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_LBTRETRY_DEFAULT (_PROTIMER_SEQIEN_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_RTCCSYNCHED (0x1UL << 28) /**< RTCCSYNCHED Interrupt Enable */ +#define _PROTIMER_SEQIEN_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_SEQIEN_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */ +#define _PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT (_PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0MATCHLBT Interrupt Enable */ +#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */ +#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */ +#define PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT (_PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */ + +/* Bit fields for PROTIMER CC_CTRL */ +#define _PROTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MASK 0x07E07F7FUL /**< Mask for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ENABLE (0x1UL << 0) /**< Channel Enable */ +#define _PROTIMER_CC_CTRL_ENABLE_SHIFT 0 /**< Shift value for PROTIMER_ENABLE */ +#define _PROTIMER_CC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for PROTIMER_ENABLE */ +#define _PROTIMER_CC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ENABLE_DEFAULT (_PROTIMER_CC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_CCMODE (0x1UL << 1) /**< Compare/Capture mode */ +#define _PROTIMER_CC_CTRL_CCMODE_SHIFT 1 /**< Shift value for PROTIMER_CCMODE */ +#define _PROTIMER_CC_CTRL_CCMODE_MASK 0x2UL /**< Bit mask for PROTIMER_CCMODE */ +#define _PROTIMER_CC_CTRL_CCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_CCMODE_COMPARE 0x00000000UL /**< Mode COMPARE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_CCMODE_CAPTURE 0x00000001UL /**< Mode CAPTURE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_CCMODE_DEFAULT (_PROTIMER_CC_CTRL_CCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_CCMODE_COMPARE (_PROTIMER_CC_CTRL_CCMODE_COMPARE << 1) /**< Shifted mode COMPARE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_CCMODE_CAPTURE (_PROTIMER_CC_CTRL_CCMODE_CAPTURE << 1) /**< Shifted mode CAPTURE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PREMATCHEN (0x1UL << 2) /**< Enable PRECNT matching */ +#define _PROTIMER_CC_CTRL_PREMATCHEN_SHIFT 2 /**< Shift value for PROTIMER_PREMATCHEN */ +#define _PROTIMER_CC_CTRL_PREMATCHEN_MASK 0x4UL /**< Bit mask for PROTIMER_PREMATCHEN */ +#define _PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_BASEMATCHEN (0x1UL << 3) /**< Enable BASECNT matching */ +#define _PROTIMER_CC_CTRL_BASEMATCHEN_SHIFT 3 /**< Shift value for PROTIMER_BASEMATCHEN */ +#define _PROTIMER_CC_CTRL_BASEMATCHEN_MASK 0x8UL /**< Bit mask for PROTIMER_BASEMATCHEN */ +#define _PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_WRAPMATCHEN (0x1UL << 4) /**< Enable WRAPCNT matching */ +#define _PROTIMER_CC_CTRL_WRAPMATCHEN_SHIFT 4 /**< Shift value for PROTIMER_WRAPMATCHEN */ +#define _PROTIMER_CC_CTRL_WRAPMATCHEN_MASK 0x10UL /**< Bit mask for PROTIMER_WRAPMATCHEN */ +#define _PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OIST (0x1UL << 5) /**< Output Initial State */ +#define _PROTIMER_CC_CTRL_OIST_SHIFT 5 /**< Shift value for PROTIMER_OIST */ +#define _PROTIMER_CC_CTRL_OIST_MASK 0x20UL /**< Bit mask for PROTIMER_OIST */ +#define _PROTIMER_CC_CTRL_OIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OIST_DEFAULT (_PROTIMER_CC_CTRL_OIST_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OUTINV (0x1UL << 6) /**< Output Invert */ +#define _PROTIMER_CC_CTRL_OUTINV_SHIFT 6 /**< Shift value for PROTIMER_OUTINV */ +#define _PROTIMER_CC_CTRL_OUTINV_MASK 0x40UL /**< Bit mask for PROTIMER_OUTINV */ +#define _PROTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OUTINV_DEFAULT (_PROTIMER_CC_CTRL_OUTINV_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MOA_SHIFT 8 /**< Shift value for PROTIMER_MOA */ +#define _PROTIMER_CC_CTRL_MOA_MASK 0x300UL /**< Bit mask for PROTIMER_MOA */ +#define _PROTIMER_CC_CTRL_MOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MOA_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MOA_CLEAR 0x00000002UL /**< Mode CLEAR for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_MOA_SET 0x00000003UL /**< Mode SET for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_MOA_DEFAULT (_PROTIMER_CC_CTRL_MOA_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_MOA_DISABLED (_PROTIMER_CC_CTRL_MOA_DISABLED << 8) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_MOA_TOGGLE (_PROTIMER_CC_CTRL_MOA_TOGGLE << 8) /**< Shifted mode TOGGLE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_MOA_CLEAR (_PROTIMER_CC_CTRL_MOA_CLEAR << 8) /**< Shifted mode CLEAR for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_MOA_SET (_PROTIMER_CC_CTRL_MOA_SET << 8) /**< Shifted mode SET for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFOA_SHIFT 10 /**< Shift value for PROTIMER_OFOA */ +#define _PROTIMER_CC_CTRL_OFOA_MASK 0xC00UL /**< Bit mask for PROTIMER_OFOA */ +#define _PROTIMER_CC_CTRL_OFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFOA_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFOA_CLEAR 0x00000002UL /**< Mode CLEAR for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFOA_SET 0x00000003UL /**< Mode SET for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFOA_DEFAULT (_PROTIMER_CC_CTRL_OFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFOA_DISABLED (_PROTIMER_CC_CTRL_OFOA_DISABLED << 10) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFOA_TOGGLE (_PROTIMER_CC_CTRL_OFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFOA_CLEAR (_PROTIMER_CC_CTRL_OFOA_CLEAR << 10) /**< Shifted mode CLEAR for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFOA_SET (_PROTIMER_CC_CTRL_OFOA_SET << 10) /**< Shifted mode SET for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFSEL_SHIFT 12 /**< Shift value for PROTIMER_OFSEL */ +#define _PROTIMER_CC_CTRL_OFSEL_MASK 0x3000UL /**< Bit mask for PROTIMER_OFSEL */ +#define _PROTIMER_CC_CTRL_OFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFSEL_PRECNT 0x00000000UL /**< Mode PRECNT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFSEL_BASECNT 0x00000001UL /**< Mode BASECNT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFSEL_WRAPCNT 0x00000002UL /**< Mode WRAPCNT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_OFSEL_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFSEL_DEFAULT (_PROTIMER_CC_CTRL_OFSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFSEL_PRECNT (_PROTIMER_CC_CTRL_OFSEL_PRECNT << 12) /**< Shifted mode PRECNT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFSEL_BASECNT (_PROTIMER_CC_CTRL_OFSEL_BASECNT << 12) /**< Shifted mode BASECNT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFSEL_WRAPCNT (_PROTIMER_CC_CTRL_OFSEL_WRAPCNT << 12) /**< Shifted mode WRAPCNT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_OFSEL_DISABLED (_PROTIMER_CC_CTRL_OFSEL_DISABLED << 12) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PRSCONF (0x1UL << 14) /**< PRS Configuration */ +#define _PROTIMER_CC_CTRL_PRSCONF_SHIFT 14 /**< Shift value for PROTIMER_PRSCONF */ +#define _PROTIMER_CC_CTRL_PRSCONF_MASK 0x4000UL /**< Bit mask for PROTIMER_PRSCONF */ +#define _PROTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PRSCONF_DEFAULT (_PROTIMER_CC_CTRL_PRSCONF_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PRSCONF_PULSE (_PROTIMER_CC_CTRL_PRSCONF_PULSE << 14) /**< Shifted mode PULSE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_PRSCONF_LEVEL (_PROTIMER_CC_CTRL_PRSCONF_LEVEL << 14) /**< Shifted mode LEVEL for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_SHIFT 21 /**< Shift value for PROTIMER_INSEL */ +#define _PROTIMER_CC_CTRL_INSEL_MASK 0x1E00000UL /**< Bit mask for PROTIMER_INSEL */ +#define _PROTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_PRS 0x00000000UL /**< Mode PRS for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_TXDONE 0x00000001UL /**< Mode TXDONE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_RXDONE 0x00000002UL /**< Mode RXDONE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_TXORRXDONE 0x00000003UL /**< Mode TXORRXDONE for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_FRAMEDET0 0x00000004UL /**< Mode FRAMEDET0 for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_FRAMEDET1 0x00000005UL /**< Mode FRAMEDET1 for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_FDET0OR1 0x00000006UL /**< Mode FDET0OR1 for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_MODSYNCSENT 0x00000007UL /**< Mode MODSYNCSENT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_RXEOF 0x00000008UL /**< Mode RXEOF for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_PRORTC0 0x00000009UL /**< Mode PRORTC0 for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_INSEL_PRORTC1 0x0000000AUL /**< Mode PRORTC1 for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_DEFAULT (_PROTIMER_CC_CTRL_INSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_PRS (_PROTIMER_CC_CTRL_INSEL_PRS << 21) /**< Shifted mode PRS for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_TXDONE (_PROTIMER_CC_CTRL_INSEL_TXDONE << 21) /**< Shifted mode TXDONE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_RXDONE (_PROTIMER_CC_CTRL_INSEL_RXDONE << 21) /**< Shifted mode RXDONE for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_TXORRXDONE (_PROTIMER_CC_CTRL_INSEL_TXORRXDONE << 21) /**< Shifted mode TXORRXDONE for PROTIMER_CC_CTRL*/ +#define PROTIMER_CC_CTRL_INSEL_FRAMEDET0 (_PROTIMER_CC_CTRL_INSEL_FRAMEDET0 << 21) /**< Shifted mode FRAMEDET0 for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_FRAMEDET1 (_PROTIMER_CC_CTRL_INSEL_FRAMEDET1 << 21) /**< Shifted mode FRAMEDET1 for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_FDET0OR1 (_PROTIMER_CC_CTRL_INSEL_FDET0OR1 << 21) /**< Shifted mode FDET0OR1 for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_MODSYNCSENT (_PROTIMER_CC_CTRL_INSEL_MODSYNCSENT << 21) /**< Shifted mode MODSYNCSENT for PROTIMER_CC_CTRL*/ +#define PROTIMER_CC_CTRL_INSEL_RXEOF (_PROTIMER_CC_CTRL_INSEL_RXEOF << 21) /**< Shifted mode RXEOF for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_PRORTC0 (_PROTIMER_CC_CTRL_INSEL_PRORTC0 << 21) /**< Shifted mode PRORTC0 for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_INSEL_PRORTC1 (_PROTIMER_CC_CTRL_INSEL_PRORTC1 << 21) /**< Shifted mode PRORTC1 for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_ICEDGE_SHIFT 25 /**< Shift value for PROTIMER_ICEDGE */ +#define _PROTIMER_CC_CTRL_ICEDGE_MASK 0x6000000UL /**< Bit mask for PROTIMER_ICEDGE */ +#define _PROTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_CC_CTRL */ +#define _PROTIMER_CC_CTRL_ICEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ICEDGE_DEFAULT (_PROTIMER_CC_CTRL_ICEDGE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ICEDGE_RISING (_PROTIMER_CC_CTRL_ICEDGE_RISING << 25) /**< Shifted mode RISING for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ICEDGE_FALLING (_PROTIMER_CC_CTRL_ICEDGE_FALLING << 25) /**< Shifted mode FALLING for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ICEDGE_BOTH (_PROTIMER_CC_CTRL_ICEDGE_BOTH << 25) /**< Shifted mode BOTH for PROTIMER_CC_CTRL */ +#define PROTIMER_CC_CTRL_ICEDGE_DISABLED (_PROTIMER_CC_CTRL_ICEDGE_DISABLED << 25) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */ + +/* Bit fields for PROTIMER CC_PRE */ +#define _PROTIMER_CC_PRE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_PRE */ +#define _PROTIMER_CC_PRE_MASK 0x0000FFFFUL /**< Mask for PROTIMER_CC_PRE */ +#define _PROTIMER_CC_PRE_PRE_SHIFT 0 /**< Shift value for PROTIMER_PRE */ +#define _PROTIMER_CC_PRE_PRE_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRE */ +#define _PROTIMER_CC_PRE_PRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_PRE */ +#define PROTIMER_CC_PRE_PRE_DEFAULT (_PROTIMER_CC_PRE_PRE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_PRE */ + +/* Bit fields for PROTIMER CC_BASE */ +#define _PROTIMER_CC_BASE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_BASE */ +#define _PROTIMER_CC_BASE_MASK 0x0000FFFFUL /**< Mask for PROTIMER_CC_BASE */ +#define _PROTIMER_CC_BASE_BASE_SHIFT 0 /**< Shift value for PROTIMER_BASE */ +#define _PROTIMER_CC_BASE_BASE_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASE */ +#define _PROTIMER_CC_BASE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_BASE */ +#define PROTIMER_CC_BASE_BASE_DEFAULT (_PROTIMER_CC_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_BASE */ + +/* Bit fields for PROTIMER CC_WRAP */ +#define _PROTIMER_CC_WRAP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_WRAP */ +#define _PROTIMER_CC_WRAP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_CC_WRAP */ +#define _PROTIMER_CC_WRAP_WRAP_SHIFT 0 /**< Shift value for PROTIMER_WRAP */ +#define _PROTIMER_CC_WRAP_WRAP_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAP */ +#define _PROTIMER_CC_WRAP_WRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_WRAP */ +#define PROTIMER_CC_WRAP_WRAP_DEFAULT (_PROTIMER_CC_WRAP_WRAP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_WRAP */ + +/** @} End of group EFR32MG24_PROTIMER_BitFields */ +/** @} End of group EFR32MG24_PROTIMER */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_PROTIMER_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_prs.h b/EFR32MG24/Device/Include/efr32mg24_prs.h new file mode 100644 index 0000000..3909690 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_prs.h @@ -0,0 +1,1621 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PRS_H +#define EFR32MG24_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_PRS PRS + * @{ + * @brief EFR32MG24 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_SET; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED8[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_CLR; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED14[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_TGL; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED20[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group EFR32MG24_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_PRS + * @{ + * @defgroup EFR32MG24_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_ASYNC_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL_DEFAULT (_PRS_ASYNC_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 current value */ +#define _PRS_ASYNC_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL_DEFAULT (_PRS_ASYNC_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 current value */ +#define _PRS_ASYNC_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL_DEFAULT (_PRS_ASYNC_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 current value */ +#define _PRS_ASYNC_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL_DEFAULT (_PRS_ASYNC_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_PAEN */ +#define PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_PAEN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ + +/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ + +/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ + +/** @} End of group EFR32MG24_PRS_BitFields */ +/** @} End of group EFR32MG24_PRS */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_PRS_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_prs_signals.h b/EFR32MG24/Device/Include/efr32mg24_prs_signals.h new file mode 100644 index 0000000..b8dcbe6 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_prs_signals.h @@ -0,0 +1,971 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000008UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (0x00000001UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC) +#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC) +#define PRS_SYNC_VDAC1_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC) +#define PRS_SYNC_VDAC1_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (0x00000014UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000015UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000016UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000017UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x00000018UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000019UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000035UL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_MODEMH_SI (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT) +#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR) +#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF) +#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0) +#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1) +#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0) +#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1) +#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS) +#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM) +#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM) +#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC) +#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC) +#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF) +#define PRS_ASYNC_VDAC1L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM) +#define PRS_ASYNC_VDAC1L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM) +#define PRS_ASYNC_VDAC1L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC) +#define PRS_ASYNC_VDAC1L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC) +#define PRS_ASYNC_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_MODEMH_SI (PRS_ASYNC_MODEMH_SI) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT) +#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR) +#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF) +#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0) +#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1) +#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0) +#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1) +#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS) +#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM) +#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM) +#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC) +#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC) +#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF) +#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF) +#define PRS_VDAC1L_CH0WARM (PRS_ASYNC_VDAC1L_CH0WARM) +#define PRS_VDAC1L_CH1WARM (PRS_ASYNC_VDAC1L_CH1WARM) +#define PRS_VDAC1L_CH0DONEASYNC (PRS_ASYNC_VDAC1L_CH0DONEASYNC) +#define PRS_VDAC1L_CH1DONEASYNC (PRS_ASYNC_VDAC1L_CH1DONEASYNC) +#define PRS_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_VDAC1L_INTERNALTIMEROF) +#define PRS_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_VDAC1L_REFRESHTIMEROF) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) diff --git a/EFR32MG24/Device/Include/efr32mg24_rac.h b/EFR32MG24/Device/Include/efr32mg24_rac.h new file mode 100644 index 0000000..1cc8ee4 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_rac.h @@ -0,0 +1,5773 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 RAC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_RAC_H +#define EFR32MG24_RAC_H +#define RAC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_RAC RAC + * @{ + * @brief EFR32MG24 RAC Register Declaration. + *****************************************************************************/ + +/** RAC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IOM uint32_t RXENSRCEN; /**< RXEN Source Enable */ + __IM uint32_t STATUS; /**< Radio State Machine Status */ + __IOM uint32_t CMD; /**< Radio Commands */ + __IOM uint32_t CTRL; /**< Radio Control Register */ + __IOM uint32_t FORCESTATE; /**< Force state transition */ + __IOM uint32_t IF; /**< Radio Controller Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TESTCTRL; /**< Test Control Register */ + __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + __IM uint32_t STATUS1; /**< Radio State Machine Status */ + __IM uint32_t STIMER; /**< Sequencer Timer Value */ + __IOM uint32_t STIMERCOMP; /**< Sequencer Timer Compare Value */ + __IOM uint32_t SEQCTRL; /**< Sequencer Control Register */ + __IOM uint32_t PRESC; /**< Sequencer prescaler Register */ + __IOM uint32_t SR0; /**< Storage Register 0 */ + __IOM uint32_t SR1; /**< Storage Register 1 */ + __IOM uint32_t SR2; /**< Storage Register 2 */ + __IOM uint32_t SR3; /**< Storage Register 3 */ + __IOM uint32_t STCTRL; /**< Sys tick timer Control Register */ + __IOM uint32_t FRCTXWORD; /**< FRC wordbuffer write */ + __IM uint32_t FRCRXWORD; /**< FRC wordbuffer read */ + __IOM uint32_t EM1PCSR; /**< Radio EM1P Control and Status Register */ + uint32_t RESERVED0[13U]; /**< Reserved for future use */ + __IOM uint32_t SYNTHENCTRL; /**< Synthesizer Enable Control Register */ + __IOM uint32_t SYNTHREGCTRL; /**< Synthesizer Regulator Enable Control */ + __IOM uint32_t VCOCTRL; /**< VCO Control Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS2; /**< Radio State Machine Status 2 */ + __IOM uint32_t IFPGACTRL; /**< IF PGA Control Register */ + __IOM uint32_t PAENCTRL; /**< PA Enable Control Register */ + __IOM uint32_t APC; /**< Automatic Power Control Register */ + __IOM uint32_t ANTDIV; /**< ANTDIV */ + __IOM uint32_t AUXADCTRIM; /**< AUXADCTRIM */ + __IOM uint32_t AUXADCEN; /**< AUXADCEN */ + __IOM uint32_t AUXADCCTRL0; /**< Auxiliary ADC register control */ + __IOM uint32_t AUXADCCTRL1; /**< AUXADCCTRL1 */ + __IM uint32_t AUXADCOUT; /**< Auxiliary ADC digital output */ + __IOM uint32_t CLKMULTEN0; /**< CLKMULTEN0 */ + __IOM uint32_t CLKMULTEN1; /**< CLKMULTEN1 */ + __IOM uint32_t CLKMULTCTRL; /**< CLKMULTCTRL */ + __IM uint32_t CLKMULTSTATUS; /**< CLKMULTSTATUS */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IFADCTRIM0; /**< IFADCTRIM0 */ + __IOM uint32_t IFADCTRIM1; /**< IFADCTRIM1 */ + __IOM uint32_t IFADCCAL; /**< IFADCCAL */ + __IM uint32_t IFADCSTATUS; /**< IFADCSTATUS */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LNAMIXTRIM0; /**< LNAMIXTRIM0 */ + __IOM uint32_t LNAMIXTRIM1; /**< LNAMIXTRIM1 */ + __IOM uint32_t LNAMIXTRIM2; /**< LNAMIXTRIM2 */ + __IOM uint32_t LNAMIXTRIM3; /**< LNAMIXTRIM3 */ + __IOM uint32_t LNAMIXTRIM4; /**< LNAMIXTRIM4 */ + __IOM uint32_t LNAMIXCAL; /**< LNAMIXCAL */ + __IOM uint32_t LNAMIXEN; /**< LNAMIXEN */ + __IOM uint32_t PRECTRL; /**< PRECTRL */ + __IOM uint32_t PATRIM0; /**< PATRIM0 */ + __IOM uint32_t PATRIM1; /**< PATRIM1 */ + __IOM uint32_t PATRIM2; /**< PATRIM2 */ + __IOM uint32_t PATRIM3; /**< PATRIM3 */ + __IOM uint32_t PATRIM4; /**< PATRIM4 */ + __IOM uint32_t PATRIM5; /**< PATRIM5 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t TXPOWER; /**< TXPOWER */ + __IOM uint32_t TXRAMP; /**< TXRAMP */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t PGATRIM; /**< PGATRIM */ + __IOM uint32_t PGACAL; /**< PGACAL */ + __IOM uint32_t PGACTRL; /**< PGACTRL */ + __IOM uint32_t RFBIASCAL; /**< RFBIASCAL */ + __IOM uint32_t RFBIASCTRL; /**< RFBIASCTRL */ + __IOM uint32_t RADIOEN; /**< RADIOEN */ + __IOM uint32_t RFPATHEN0; /**< RFPATHEN0 */ + __IOM uint32_t RFPATHEN1; /**< RFPATHEN1 */ + __IOM uint32_t RX; /**< RX */ + __IOM uint32_t TX; /**< TX */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t SYTRIM0; /**< SYTRIM0 */ + __IOM uint32_t SYTRIM1; /**< SYTRIM1 */ + __IOM uint32_t SYCAL; /**< SYCAL */ + __IOM uint32_t SYEN; /**< SYEN */ + __IOM uint32_t SYLOEN; /**< SYLOEN */ + __IOM uint32_t SYMMDCTRL; /**< SYMMDCTRL */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t DIGCLKRETIMECTRL; /**< DIGCLKRETIMECTRL */ + __IM uint32_t DIGCLKRETIMESTATUS; /**< DIGCLKRETIMESTATUS */ + __IOM uint32_t XORETIMECTRL; /**< XORETIMECTRL */ + __IM uint32_t XORETIMESTATUS; /**< XORETIMESTATUS */ + __IOM uint32_t AGCOVERWRITE0; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE1; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE2; /**< OVERWRITE AGC */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t PACTRL; /**< PACTRL */ + __IOM uint32_t FENOTCH0; /**< FENOTCH0 */ + __IOM uint32_t FENOTCH1; /**< FENOTCH1 */ + uint32_t RESERVED10[131U]; /**< Reserved for future use */ + __IOM uint32_t SCRATCH0; /**< SCRATCH0 */ + __IOM uint32_t SCRATCH1; /**< SCRATCH1 */ + __IOM uint32_t SCRATCH2; /**< SCRATCH2 */ + __IOM uint32_t SCRATCH3; /**< SCRATCH3 */ + __IOM uint32_t SCRATCH4; /**< SCRATCH4 */ + __IOM uint32_t SCRATCH5; /**< SCRATCH5 */ + __IOM uint32_t SCRATCH6; /**< SCRATCH6 */ + __IOM uint32_t SCRATCH7; /**< SCRATCH7 */ + uint32_t RESERVED11[250U]; /**< Reserved for future use */ + __IOM uint32_t THMSW; /**< Thermister control */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[513U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IOM uint32_t RXENSRCEN_SET; /**< RXEN Source Enable */ + __IM uint32_t STATUS_SET; /**< Radio State Machine Status */ + __IOM uint32_t CMD_SET; /**< Radio Commands */ + __IOM uint32_t CTRL_SET; /**< Radio Control Register */ + __IOM uint32_t FORCESTATE_SET; /**< Force state transition */ + __IOM uint32_t IF_SET; /**< Radio Controller Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TESTCTRL_SET; /**< Test Control Register */ + __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + __IM uint32_t STATUS1_SET; /**< Radio State Machine Status */ + __IM uint32_t STIMER_SET; /**< Sequencer Timer Value */ + __IOM uint32_t STIMERCOMP_SET; /**< Sequencer Timer Compare Value */ + __IOM uint32_t SEQCTRL_SET; /**< Sequencer Control Register */ + __IOM uint32_t PRESC_SET; /**< Sequencer prescaler Register */ + __IOM uint32_t SR0_SET; /**< Storage Register 0 */ + __IOM uint32_t SR1_SET; /**< Storage Register 1 */ + __IOM uint32_t SR2_SET; /**< Storage Register 2 */ + __IOM uint32_t SR3_SET; /**< Storage Register 3 */ + __IOM uint32_t STCTRL_SET; /**< Sys tick timer Control Register */ + __IOM uint32_t FRCTXWORD_SET; /**< FRC wordbuffer write */ + __IM uint32_t FRCRXWORD_SET; /**< FRC wordbuffer read */ + __IOM uint32_t EM1PCSR_SET; /**< Radio EM1P Control and Status Register */ + uint32_t RESERVED16[13U]; /**< Reserved for future use */ + __IOM uint32_t SYNTHENCTRL_SET; /**< Synthesizer Enable Control Register */ + __IOM uint32_t SYNTHREGCTRL_SET; /**< Synthesizer Regulator Enable Control */ + __IOM uint32_t VCOCTRL_SET; /**< VCO Control Register */ + uint32_t RESERVED17[2U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS2_SET; /**< Radio State Machine Status 2 */ + __IOM uint32_t IFPGACTRL_SET; /**< IF PGA Control Register */ + __IOM uint32_t PAENCTRL_SET; /**< PA Enable Control Register */ + __IOM uint32_t APC_SET; /**< Automatic Power Control Register */ + __IOM uint32_t ANTDIV_SET; /**< ANTDIV */ + __IOM uint32_t AUXADCTRIM_SET; /**< AUXADCTRIM */ + __IOM uint32_t AUXADCEN_SET; /**< AUXADCEN */ + __IOM uint32_t AUXADCCTRL0_SET; /**< Auxiliary ADC register control */ + __IOM uint32_t AUXADCCTRL1_SET; /**< AUXADCCTRL1 */ + __IM uint32_t AUXADCOUT_SET; /**< Auxiliary ADC digital output */ + __IOM uint32_t CLKMULTEN0_SET; /**< CLKMULTEN0 */ + __IOM uint32_t CLKMULTEN1_SET; /**< CLKMULTEN1 */ + __IOM uint32_t CLKMULTCTRL_SET; /**< CLKMULTCTRL */ + __IM uint32_t CLKMULTSTATUS_SET; /**< CLKMULTSTATUS */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t IFADCTRIM0_SET; /**< IFADCTRIM0 */ + __IOM uint32_t IFADCTRIM1_SET; /**< IFADCTRIM1 */ + __IOM uint32_t IFADCCAL_SET; /**< IFADCCAL */ + __IM uint32_t IFADCSTATUS_SET; /**< IFADCSTATUS */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t LNAMIXTRIM0_SET; /**< LNAMIXTRIM0 */ + __IOM uint32_t LNAMIXTRIM1_SET; /**< LNAMIXTRIM1 */ + __IOM uint32_t LNAMIXTRIM2_SET; /**< LNAMIXTRIM2 */ + __IOM uint32_t LNAMIXTRIM3_SET; /**< LNAMIXTRIM3 */ + __IOM uint32_t LNAMIXTRIM4_SET; /**< LNAMIXTRIM4 */ + __IOM uint32_t LNAMIXCAL_SET; /**< LNAMIXCAL */ + __IOM uint32_t LNAMIXEN_SET; /**< LNAMIXEN */ + __IOM uint32_t PRECTRL_SET; /**< PRECTRL */ + __IOM uint32_t PATRIM0_SET; /**< PATRIM0 */ + __IOM uint32_t PATRIM1_SET; /**< PATRIM1 */ + __IOM uint32_t PATRIM2_SET; /**< PATRIM2 */ + __IOM uint32_t PATRIM3_SET; /**< PATRIM3 */ + __IOM uint32_t PATRIM4_SET; /**< PATRIM4 */ + __IOM uint32_t PATRIM5_SET; /**< PATRIM5 */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t TXPOWER_SET; /**< TXPOWER */ + __IOM uint32_t TXRAMP_SET; /**< TXRAMP */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t PGATRIM_SET; /**< PGATRIM */ + __IOM uint32_t PGACAL_SET; /**< PGACAL */ + __IOM uint32_t PGACTRL_SET; /**< PGACTRL */ + __IOM uint32_t RFBIASCAL_SET; /**< RFBIASCAL */ + __IOM uint32_t RFBIASCTRL_SET; /**< RFBIASCTRL */ + __IOM uint32_t RADIOEN_SET; /**< RADIOEN */ + __IOM uint32_t RFPATHEN0_SET; /**< RFPATHEN0 */ + __IOM uint32_t RFPATHEN1_SET; /**< RFPATHEN1 */ + __IOM uint32_t RX_SET; /**< RX */ + __IOM uint32_t TX_SET; /**< TX */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t SYTRIM0_SET; /**< SYTRIM0 */ + __IOM uint32_t SYTRIM1_SET; /**< SYTRIM1 */ + __IOM uint32_t SYCAL_SET; /**< SYCAL */ + __IOM uint32_t SYEN_SET; /**< SYEN */ + __IOM uint32_t SYLOEN_SET; /**< SYLOEN */ + __IOM uint32_t SYMMDCTRL_SET; /**< SYMMDCTRL */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t DIGCLKRETIMECTRL_SET; /**< DIGCLKRETIMECTRL */ + __IM uint32_t DIGCLKRETIMESTATUS_SET; /**< DIGCLKRETIMESTATUS */ + __IOM uint32_t XORETIMECTRL_SET; /**< XORETIMECTRL */ + __IM uint32_t XORETIMESTATUS_SET; /**< XORETIMESTATUS */ + __IOM uint32_t AGCOVERWRITE0_SET; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE1_SET; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE2_SET; /**< OVERWRITE AGC */ + uint32_t RESERVED25[7U]; /**< Reserved for future use */ + __IOM uint32_t PACTRL_SET; /**< PACTRL */ + __IOM uint32_t FENOTCH0_SET; /**< FENOTCH0 */ + __IOM uint32_t FENOTCH1_SET; /**< FENOTCH1 */ + uint32_t RESERVED26[131U]; /**< Reserved for future use */ + __IOM uint32_t SCRATCH0_SET; /**< SCRATCH0 */ + __IOM uint32_t SCRATCH1_SET; /**< SCRATCH1 */ + __IOM uint32_t SCRATCH2_SET; /**< SCRATCH2 */ + __IOM uint32_t SCRATCH3_SET; /**< SCRATCH3 */ + __IOM uint32_t SCRATCH4_SET; /**< SCRATCH4 */ + __IOM uint32_t SCRATCH5_SET; /**< SCRATCH5 */ + __IOM uint32_t SCRATCH6_SET; /**< SCRATCH6 */ + __IOM uint32_t SCRATCH7_SET; /**< SCRATCH7 */ + uint32_t RESERVED27[250U]; /**< Reserved for future use */ + __IOM uint32_t THMSW_SET; /**< Thermister control */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[513U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IOM uint32_t RXENSRCEN_CLR; /**< RXEN Source Enable */ + __IM uint32_t STATUS_CLR; /**< Radio State Machine Status */ + __IOM uint32_t CMD_CLR; /**< Radio Commands */ + __IOM uint32_t CTRL_CLR; /**< Radio Control Register */ + __IOM uint32_t FORCESTATE_CLR; /**< Force state transition */ + __IOM uint32_t IF_CLR; /**< Radio Controller Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TESTCTRL_CLR; /**< Test Control Register */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + __IM uint32_t STATUS1_CLR; /**< Radio State Machine Status */ + __IM uint32_t STIMER_CLR; /**< Sequencer Timer Value */ + __IOM uint32_t STIMERCOMP_CLR; /**< Sequencer Timer Compare Value */ + __IOM uint32_t SEQCTRL_CLR; /**< Sequencer Control Register */ + __IOM uint32_t PRESC_CLR; /**< Sequencer prescaler Register */ + __IOM uint32_t SR0_CLR; /**< Storage Register 0 */ + __IOM uint32_t SR1_CLR; /**< Storage Register 1 */ + __IOM uint32_t SR2_CLR; /**< Storage Register 2 */ + __IOM uint32_t SR3_CLR; /**< Storage Register 3 */ + __IOM uint32_t STCTRL_CLR; /**< Sys tick timer Control Register */ + __IOM uint32_t FRCTXWORD_CLR; /**< FRC wordbuffer write */ + __IM uint32_t FRCRXWORD_CLR; /**< FRC wordbuffer read */ + __IOM uint32_t EM1PCSR_CLR; /**< Radio EM1P Control and Status Register */ + uint32_t RESERVED32[13U]; /**< Reserved for future use */ + __IOM uint32_t SYNTHENCTRL_CLR; /**< Synthesizer Enable Control Register */ + __IOM uint32_t SYNTHREGCTRL_CLR; /**< Synthesizer Regulator Enable Control */ + __IOM uint32_t VCOCTRL_CLR; /**< VCO Control Register */ + uint32_t RESERVED33[2U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS2_CLR; /**< Radio State Machine Status 2 */ + __IOM uint32_t IFPGACTRL_CLR; /**< IF PGA Control Register */ + __IOM uint32_t PAENCTRL_CLR; /**< PA Enable Control Register */ + __IOM uint32_t APC_CLR; /**< Automatic Power Control Register */ + __IOM uint32_t ANTDIV_CLR; /**< ANTDIV */ + __IOM uint32_t AUXADCTRIM_CLR; /**< AUXADCTRIM */ + __IOM uint32_t AUXADCEN_CLR; /**< AUXADCEN */ + __IOM uint32_t AUXADCCTRL0_CLR; /**< Auxiliary ADC register control */ + __IOM uint32_t AUXADCCTRL1_CLR; /**< AUXADCCTRL1 */ + __IM uint32_t AUXADCOUT_CLR; /**< Auxiliary ADC digital output */ + __IOM uint32_t CLKMULTEN0_CLR; /**< CLKMULTEN0 */ + __IOM uint32_t CLKMULTEN1_CLR; /**< CLKMULTEN1 */ + __IOM uint32_t CLKMULTCTRL_CLR; /**< CLKMULTCTRL */ + __IM uint32_t CLKMULTSTATUS_CLR; /**< CLKMULTSTATUS */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t IFADCTRIM0_CLR; /**< IFADCTRIM0 */ + __IOM uint32_t IFADCTRIM1_CLR; /**< IFADCTRIM1 */ + __IOM uint32_t IFADCCAL_CLR; /**< IFADCCAL */ + __IM uint32_t IFADCSTATUS_CLR; /**< IFADCSTATUS */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t LNAMIXTRIM0_CLR; /**< LNAMIXTRIM0 */ + __IOM uint32_t LNAMIXTRIM1_CLR; /**< LNAMIXTRIM1 */ + __IOM uint32_t LNAMIXTRIM2_CLR; /**< LNAMIXTRIM2 */ + __IOM uint32_t LNAMIXTRIM3_CLR; /**< LNAMIXTRIM3 */ + __IOM uint32_t LNAMIXTRIM4_CLR; /**< LNAMIXTRIM4 */ + __IOM uint32_t LNAMIXCAL_CLR; /**< LNAMIXCAL */ + __IOM uint32_t LNAMIXEN_CLR; /**< LNAMIXEN */ + __IOM uint32_t PRECTRL_CLR; /**< PRECTRL */ + __IOM uint32_t PATRIM0_CLR; /**< PATRIM0 */ + __IOM uint32_t PATRIM1_CLR; /**< PATRIM1 */ + __IOM uint32_t PATRIM2_CLR; /**< PATRIM2 */ + __IOM uint32_t PATRIM3_CLR; /**< PATRIM3 */ + __IOM uint32_t PATRIM4_CLR; /**< PATRIM4 */ + __IOM uint32_t PATRIM5_CLR; /**< PATRIM5 */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t TXPOWER_CLR; /**< TXPOWER */ + __IOM uint32_t TXRAMP_CLR; /**< TXRAMP */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t PGATRIM_CLR; /**< PGATRIM */ + __IOM uint32_t PGACAL_CLR; /**< PGACAL */ + __IOM uint32_t PGACTRL_CLR; /**< PGACTRL */ + __IOM uint32_t RFBIASCAL_CLR; /**< RFBIASCAL */ + __IOM uint32_t RFBIASCTRL_CLR; /**< RFBIASCTRL */ + __IOM uint32_t RADIOEN_CLR; /**< RADIOEN */ + __IOM uint32_t RFPATHEN0_CLR; /**< RFPATHEN0 */ + __IOM uint32_t RFPATHEN1_CLR; /**< RFPATHEN1 */ + __IOM uint32_t RX_CLR; /**< RX */ + __IOM uint32_t TX_CLR; /**< TX */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t SYTRIM0_CLR; /**< SYTRIM0 */ + __IOM uint32_t SYTRIM1_CLR; /**< SYTRIM1 */ + __IOM uint32_t SYCAL_CLR; /**< SYCAL */ + __IOM uint32_t SYEN_CLR; /**< SYEN */ + __IOM uint32_t SYLOEN_CLR; /**< SYLOEN */ + __IOM uint32_t SYMMDCTRL_CLR; /**< SYMMDCTRL */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IOM uint32_t DIGCLKRETIMECTRL_CLR; /**< DIGCLKRETIMECTRL */ + __IM uint32_t DIGCLKRETIMESTATUS_CLR; /**< DIGCLKRETIMESTATUS */ + __IOM uint32_t XORETIMECTRL_CLR; /**< XORETIMECTRL */ + __IM uint32_t XORETIMESTATUS_CLR; /**< XORETIMESTATUS */ + __IOM uint32_t AGCOVERWRITE0_CLR; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE1_CLR; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE2_CLR; /**< OVERWRITE AGC */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + __IOM uint32_t PACTRL_CLR; /**< PACTRL */ + __IOM uint32_t FENOTCH0_CLR; /**< FENOTCH0 */ + __IOM uint32_t FENOTCH1_CLR; /**< FENOTCH1 */ + uint32_t RESERVED42[131U]; /**< Reserved for future use */ + __IOM uint32_t SCRATCH0_CLR; /**< SCRATCH0 */ + __IOM uint32_t SCRATCH1_CLR; /**< SCRATCH1 */ + __IOM uint32_t SCRATCH2_CLR; /**< SCRATCH2 */ + __IOM uint32_t SCRATCH3_CLR; /**< SCRATCH3 */ + __IOM uint32_t SCRATCH4_CLR; /**< SCRATCH4 */ + __IOM uint32_t SCRATCH5_CLR; /**< SCRATCH5 */ + __IOM uint32_t SCRATCH6_CLR; /**< SCRATCH6 */ + __IOM uint32_t SCRATCH7_CLR; /**< SCRATCH7 */ + uint32_t RESERVED43[250U]; /**< Reserved for future use */ + __IOM uint32_t THMSW_CLR; /**< Thermister control */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[2U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[513U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IOM uint32_t RXENSRCEN_TGL; /**< RXEN Source Enable */ + __IM uint32_t STATUS_TGL; /**< Radio State Machine Status */ + __IOM uint32_t CMD_TGL; /**< Radio Commands */ + __IOM uint32_t CTRL_TGL; /**< Radio Control Register */ + __IOM uint32_t FORCESTATE_TGL; /**< Force state transition */ + __IOM uint32_t IF_TGL; /**< Radio Controller Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TESTCTRL_TGL; /**< Test Control Register */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ + __IM uint32_t STATUS1_TGL; /**< Radio State Machine Status */ + __IM uint32_t STIMER_TGL; /**< Sequencer Timer Value */ + __IOM uint32_t STIMERCOMP_TGL; /**< Sequencer Timer Compare Value */ + __IOM uint32_t SEQCTRL_TGL; /**< Sequencer Control Register */ + __IOM uint32_t PRESC_TGL; /**< Sequencer prescaler Register */ + __IOM uint32_t SR0_TGL; /**< Storage Register 0 */ + __IOM uint32_t SR1_TGL; /**< Storage Register 1 */ + __IOM uint32_t SR2_TGL; /**< Storage Register 2 */ + __IOM uint32_t SR3_TGL; /**< Storage Register 3 */ + __IOM uint32_t STCTRL_TGL; /**< Sys tick timer Control Register */ + __IOM uint32_t FRCTXWORD_TGL; /**< FRC wordbuffer write */ + __IM uint32_t FRCRXWORD_TGL; /**< FRC wordbuffer read */ + __IOM uint32_t EM1PCSR_TGL; /**< Radio EM1P Control and Status Register */ + uint32_t RESERVED48[13U]; /**< Reserved for future use */ + __IOM uint32_t SYNTHENCTRL_TGL; /**< Synthesizer Enable Control Register */ + __IOM uint32_t SYNTHREGCTRL_TGL; /**< Synthesizer Regulator Enable Control */ + __IOM uint32_t VCOCTRL_TGL; /**< VCO Control Register */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS2_TGL; /**< Radio State Machine Status 2 */ + __IOM uint32_t IFPGACTRL_TGL; /**< IF PGA Control Register */ + __IOM uint32_t PAENCTRL_TGL; /**< PA Enable Control Register */ + __IOM uint32_t APC_TGL; /**< Automatic Power Control Register */ + __IOM uint32_t ANTDIV_TGL; /**< ANTDIV */ + __IOM uint32_t AUXADCTRIM_TGL; /**< AUXADCTRIM */ + __IOM uint32_t AUXADCEN_TGL; /**< AUXADCEN */ + __IOM uint32_t AUXADCCTRL0_TGL; /**< Auxiliary ADC register control */ + __IOM uint32_t AUXADCCTRL1_TGL; /**< AUXADCCTRL1 */ + __IM uint32_t AUXADCOUT_TGL; /**< Auxiliary ADC digital output */ + __IOM uint32_t CLKMULTEN0_TGL; /**< CLKMULTEN0 */ + __IOM uint32_t CLKMULTEN1_TGL; /**< CLKMULTEN1 */ + __IOM uint32_t CLKMULTCTRL_TGL; /**< CLKMULTCTRL */ + __IM uint32_t CLKMULTSTATUS_TGL; /**< CLKMULTSTATUS */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t IFADCTRIM0_TGL; /**< IFADCTRIM0 */ + __IOM uint32_t IFADCTRIM1_TGL; /**< IFADCTRIM1 */ + __IOM uint32_t IFADCCAL_TGL; /**< IFADCCAL */ + __IM uint32_t IFADCSTATUS_TGL; /**< IFADCSTATUS */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IOM uint32_t LNAMIXTRIM0_TGL; /**< LNAMIXTRIM0 */ + __IOM uint32_t LNAMIXTRIM1_TGL; /**< LNAMIXTRIM1 */ + __IOM uint32_t LNAMIXTRIM2_TGL; /**< LNAMIXTRIM2 */ + __IOM uint32_t LNAMIXTRIM3_TGL; /**< LNAMIXTRIM3 */ + __IOM uint32_t LNAMIXTRIM4_TGL; /**< LNAMIXTRIM4 */ + __IOM uint32_t LNAMIXCAL_TGL; /**< LNAMIXCAL */ + __IOM uint32_t LNAMIXEN_TGL; /**< LNAMIXEN */ + __IOM uint32_t PRECTRL_TGL; /**< PRECTRL */ + __IOM uint32_t PATRIM0_TGL; /**< PATRIM0 */ + __IOM uint32_t PATRIM1_TGL; /**< PATRIM1 */ + __IOM uint32_t PATRIM2_TGL; /**< PATRIM2 */ + __IOM uint32_t PATRIM3_TGL; /**< PATRIM3 */ + __IOM uint32_t PATRIM4_TGL; /**< PATRIM4 */ + __IOM uint32_t PATRIM5_TGL; /**< PATRIM5 */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t TXPOWER_TGL; /**< TXPOWER */ + __IOM uint32_t TXRAMP_TGL; /**< TXRAMP */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ + __IOM uint32_t PGATRIM_TGL; /**< PGATRIM */ + __IOM uint32_t PGACAL_TGL; /**< PGACAL */ + __IOM uint32_t PGACTRL_TGL; /**< PGACTRL */ + __IOM uint32_t RFBIASCAL_TGL; /**< RFBIASCAL */ + __IOM uint32_t RFBIASCTRL_TGL; /**< RFBIASCTRL */ + __IOM uint32_t RADIOEN_TGL; /**< RADIOEN */ + __IOM uint32_t RFPATHEN0_TGL; /**< RFPATHEN0 */ + __IOM uint32_t RFPATHEN1_TGL; /**< RFPATHEN1 */ + __IOM uint32_t RX_TGL; /**< RX */ + __IOM uint32_t TX_TGL; /**< TX */ + uint32_t RESERVED55[1U]; /**< Reserved for future use */ + __IOM uint32_t SYTRIM0_TGL; /**< SYTRIM0 */ + __IOM uint32_t SYTRIM1_TGL; /**< SYTRIM1 */ + __IOM uint32_t SYCAL_TGL; /**< SYCAL */ + __IOM uint32_t SYEN_TGL; /**< SYEN */ + __IOM uint32_t SYLOEN_TGL; /**< SYLOEN */ + __IOM uint32_t SYMMDCTRL_TGL; /**< SYMMDCTRL */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + __IOM uint32_t DIGCLKRETIMECTRL_TGL; /**< DIGCLKRETIMECTRL */ + __IM uint32_t DIGCLKRETIMESTATUS_TGL; /**< DIGCLKRETIMESTATUS */ + __IOM uint32_t XORETIMECTRL_TGL; /**< XORETIMECTRL */ + __IM uint32_t XORETIMESTATUS_TGL; /**< XORETIMESTATUS */ + __IOM uint32_t AGCOVERWRITE0_TGL; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE1_TGL; /**< OVERWRITE AGC */ + __IOM uint32_t AGCOVERWRITE2_TGL; /**< OVERWRITE AGC */ + uint32_t RESERVED57[7U]; /**< Reserved for future use */ + __IOM uint32_t PACTRL_TGL; /**< PACTRL */ + __IOM uint32_t FENOTCH0_TGL; /**< FENOTCH0 */ + __IOM uint32_t FENOTCH1_TGL; /**< FENOTCH1 */ + uint32_t RESERVED58[131U]; /**< Reserved for future use */ + __IOM uint32_t SCRATCH0_TGL; /**< SCRATCH0 */ + __IOM uint32_t SCRATCH1_TGL; /**< SCRATCH1 */ + __IOM uint32_t SCRATCH2_TGL; /**< SCRATCH2 */ + __IOM uint32_t SCRATCH3_TGL; /**< SCRATCH3 */ + __IOM uint32_t SCRATCH4_TGL; /**< SCRATCH4 */ + __IOM uint32_t SCRATCH5_TGL; /**< SCRATCH5 */ + __IOM uint32_t SCRATCH6_TGL; /**< SCRATCH6 */ + __IOM uint32_t SCRATCH7_TGL; /**< SCRATCH7 */ + uint32_t RESERVED59[250U]; /**< Reserved for future use */ + __IOM uint32_t THMSW_TGL; /**< Thermister control */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + uint32_t RESERVED61[2U]; /**< Reserved for future use */ + uint32_t RESERVED62[1U]; /**< Reserved for future use */ +} RAC_TypeDef; +/** @} End of group EFR32MG24_RAC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_RAC + * @{ + * @defgroup EFR32MG24_RAC_BitFields RAC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for RAC IPVERSION */ +#define _RAC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for RAC_IPVERSION */ +#define _RAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RAC_IPVERSION */ +#define _RAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RAC_IPVERSION */ +#define _RAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_IPVERSION */ +#define _RAC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IPVERSION */ +#define RAC_IPVERSION_IPVERSION_DEFAULT (_RAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IPVERSION */ + +/* Bit fields for RAC EN */ +#define _RAC_EN_RESETVALUE 0x00000000UL /**< Default value for RAC_EN */ +#define _RAC_EN_MASK 0x00000001UL /**< Mask for RAC_EN */ +#define RAC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _RAC_EN_EN_SHIFT 0 /**< Shift value for RAC_EN */ +#define _RAC_EN_EN_MASK 0x1UL /**< Bit mask for RAC_EN */ +#define _RAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EN */ +#define RAC_EN_EN_DEFAULT (_RAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_EN */ + +/* Bit fields for RAC RXENSRCEN */ +#define _RAC_RXENSRCEN_RESETVALUE 0x00000000UL /**< Default value for RAC_RXENSRCEN */ +#define _RAC_RXENSRCEN_MASK 0x00003FFFUL /**< Mask for RAC_RXENSRCEN */ +#define _RAC_RXENSRCEN_SWRXEN_SHIFT 0 /**< Shift value for RAC_SWRXEN */ +#define _RAC_RXENSRCEN_SWRXEN_MASK 0xFFUL /**< Bit mask for RAC_SWRXEN */ +#define _RAC_RXENSRCEN_SWRXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_SWRXEN_DEFAULT (_RAC_RXENSRCEN_SWRXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_CHANNELBUSYEN (0x1UL << 8) /**< Channel Busy Enable */ +#define _RAC_RXENSRCEN_CHANNELBUSYEN_SHIFT 8 /**< Shift value for RAC_CHANNELBUSYEN */ +#define _RAC_RXENSRCEN_CHANNELBUSYEN_MASK 0x100UL /**< Bit mask for RAC_CHANNELBUSYEN */ +#define _RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT (_RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_TIMDETEN (0x1UL << 9) /**< Timing Detected Enable */ +#define _RAC_RXENSRCEN_TIMDETEN_SHIFT 9 /**< Shift value for RAC_TIMDETEN */ +#define _RAC_RXENSRCEN_TIMDETEN_MASK 0x200UL /**< Bit mask for RAC_TIMDETEN */ +#define _RAC_RXENSRCEN_TIMDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_TIMDETEN_DEFAULT (_RAC_RXENSRCEN_TIMDETEN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_PREDETEN (0x1UL << 10) /**< Preamble Detected Enable */ +#define _RAC_RXENSRCEN_PREDETEN_SHIFT 10 /**< Shift value for RAC_PREDETEN */ +#define _RAC_RXENSRCEN_PREDETEN_MASK 0x400UL /**< Bit mask for RAC_PREDETEN */ +#define _RAC_RXENSRCEN_PREDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_PREDETEN_DEFAULT (_RAC_RXENSRCEN_PREDETEN_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_FRAMEDETEN (0x1UL << 11) /**< Frame Detected Enable */ +#define _RAC_RXENSRCEN_FRAMEDETEN_SHIFT 11 /**< Shift value for RAC_FRAMEDETEN */ +#define _RAC_RXENSRCEN_FRAMEDETEN_MASK 0x800UL /**< Bit mask for RAC_FRAMEDETEN */ +#define _RAC_RXENSRCEN_FRAMEDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_FRAMEDETEN_DEFAULT (_RAC_RXENSRCEN_FRAMEDETEN_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_DEMODRXREQEN (0x1UL << 12) /**< DEMOD RX Request Enable */ +#define _RAC_RXENSRCEN_DEMODRXREQEN_SHIFT 12 /**< Shift value for RAC_DEMODRXREQEN */ +#define _RAC_RXENSRCEN_DEMODRXREQEN_MASK 0x1000UL /**< Bit mask for RAC_DEMODRXREQEN */ +#define _RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT (_RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_PRSRXEN (0x1UL << 13) /**< PRS RX Enable */ +#define _RAC_RXENSRCEN_PRSRXEN_SHIFT 13 /**< Shift value for RAC_PRSRXEN */ +#define _RAC_RXENSRCEN_PRSRXEN_MASK 0x2000UL /**< Bit mask for RAC_PRSRXEN */ +#define _RAC_RXENSRCEN_PRSRXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */ +#define RAC_RXENSRCEN_PRSRXEN_DEFAULT (_RAC_RXENSRCEN_PRSRXEN_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */ + +/* Bit fields for RAC STATUS */ +#define _RAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS */ +#define _RAC_STATUS_MASK 0xFFF8FFFFUL /**< Mask for RAC_STATUS */ +#define _RAC_STATUS_RXMASK_SHIFT 0 /**< Shift value for RAC_RXMASK */ +#define _RAC_STATUS_RXMASK_MASK 0xFFFFUL /**< Bit mask for RAC_RXMASK */ +#define _RAC_STATUS_RXMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_RXMASK_DEFAULT (_RAC_STATUS_RXMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_FORCESTATEACTIVE (0x1UL << 19) /**< FSM state force active */ +#define _RAC_STATUS_FORCESTATEACTIVE_SHIFT 19 /**< Shift value for RAC_FORCESTATEACTIVE */ +#define _RAC_STATUS_FORCESTATEACTIVE_MASK 0x80000UL /**< Bit mask for RAC_FORCESTATEACTIVE */ +#define _RAC_STATUS_FORCESTATEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_FORCESTATEACTIVE_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */ +#define _RAC_STATUS_FORCESTATEACTIVE_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */ +#define RAC_STATUS_FORCESTATEACTIVE_DEFAULT (_RAC_STATUS_FORCESTATEACTIVE_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_FORCESTATEACTIVE_X0 (_RAC_STATUS_FORCESTATEACTIVE_X0 << 19) /**< Shifted mode X0 for RAC_STATUS */ +#define RAC_STATUS_FORCESTATEACTIVE_X1 (_RAC_STATUS_FORCESTATEACTIVE_X1 << 19) /**< Shifted mode X1 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEPEND (0x1UL << 20) /**< TX After Frame Pending */ +#define _RAC_STATUS_TXAFTERFRAMEPEND_SHIFT 20 /**< Shift value for RAC_TXAFTERFRAMEPEND */ +#define _RAC_STATUS_TXAFTERFRAMEPEND_MASK 0x100000UL /**< Bit mask for RAC_TXAFTERFRAMEPEND */ +#define _RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_TXAFTERFRAMEPEND_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */ +#define _RAC_STATUS_TXAFTERFRAMEPEND_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT (_RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEPEND_X0 (_RAC_STATUS_TXAFTERFRAMEPEND_X0 << 20) /**< Shifted mode X0 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEPEND_X1 (_RAC_STATUS_TXAFTERFRAMEPEND_X1 << 20) /**< Shifted mode X1 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEACTIVE (0x1UL << 21) /**< TX After Frame Active */ +#define _RAC_STATUS_TXAFTERFRAMEACTIVE_SHIFT 21 /**< Shift value for RAC_TXAFTERFRAMEACTIVE */ +#define _RAC_STATUS_TXAFTERFRAMEACTIVE_MASK 0x200000UL /**< Bit mask for RAC_TXAFTERFRAMEACTIVE */ +#define _RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_TXAFTERFRAMEACTIVE_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */ +#define _RAC_STATUS_TXAFTERFRAMEACTIVE_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT (_RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEACTIVE_X0 (_RAC_STATUS_TXAFTERFRAMEACTIVE_X0 << 21) /**< Shifted mode X0 for RAC_STATUS */ +#define RAC_STATUS_TXAFTERFRAMEACTIVE_X1 (_RAC_STATUS_TXAFTERFRAMEACTIVE_X1 << 21) /**< Shifted mode X1 for RAC_STATUS */ +#define RAC_STATUS_SEQSLEEPING (0x1UL << 22) /**< SEQ in sleeping */ +#define _RAC_STATUS_SEQSLEEPING_SHIFT 22 /**< Shift value for RAC_SEQSLEEPING */ +#define _RAC_STATUS_SEQSLEEPING_MASK 0x400000UL /**< Bit mask for RAC_SEQSLEEPING */ +#define _RAC_STATUS_SEQSLEEPING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_SEQSLEEPING_DEFAULT (_RAC_STATUS_SEQSLEEPING_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_SEQSLEEPDEEP (0x1UL << 23) /**< SEQ in deep sleep */ +#define _RAC_STATUS_SEQSLEEPDEEP_SHIFT 23 /**< Shift value for RAC_SEQSLEEPDEEP */ +#define _RAC_STATUS_SEQSLEEPDEEP_MASK 0x800000UL /**< Bit mask for RAC_SEQSLEEPDEEP */ +#define _RAC_STATUS_SEQSLEEPDEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_SEQSLEEPDEEP_DEFAULT (_RAC_STATUS_SEQSLEEPDEEP_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_STATE_SHIFT 24 /**< Shift value for RAC_STATE */ +#define _RAC_STATUS_STATE_MASK 0xF000000UL /**< Bit mask for RAC_STATE */ +#define _RAC_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_STATE_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS */ +#define _RAC_STATUS_STATE_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS */ +#define _RAC_STATUS_STATE_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS */ +#define _RAC_STATUS_STATE_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS */ +#define _RAC_STATUS_STATE_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS */ +#define _RAC_STATUS_STATE_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS */ +#define _RAC_STATUS_STATE_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS */ +#define _RAC_STATUS_STATE_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS */ +#define _RAC_STATUS_STATE_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS */ +#define _RAC_STATUS_STATE_TX 0x00000009UL /**< Mode TX for RAC_STATUS */ +#define _RAC_STATUS_STATE_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS */ +#define _RAC_STATUS_STATE_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS */ +#define _RAC_STATUS_STATE_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS */ +#define _RAC_STATUS_STATE_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS */ +#define _RAC_STATUS_STATE_POR 0x0000000EUL /**< Mode POR for RAC_STATUS */ +#define RAC_STATUS_STATE_DEFAULT (_RAC_STATUS_STATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_STATE_OFF (_RAC_STATUS_STATE_OFF << 24) /**< Shifted mode OFF for RAC_STATUS */ +#define RAC_STATUS_STATE_RXWARM (_RAC_STATUS_STATE_RXWARM << 24) /**< Shifted mode RXWARM for RAC_STATUS */ +#define RAC_STATUS_STATE_RXSEARCH (_RAC_STATUS_STATE_RXSEARCH << 24) /**< Shifted mode RXSEARCH for RAC_STATUS */ +#define RAC_STATUS_STATE_RXFRAME (_RAC_STATUS_STATE_RXFRAME << 24) /**< Shifted mode RXFRAME for RAC_STATUS */ +#define RAC_STATUS_STATE_RXPD (_RAC_STATUS_STATE_RXPD << 24) /**< Shifted mode RXPD for RAC_STATUS */ +#define RAC_STATUS_STATE_RX2RX (_RAC_STATUS_STATE_RX2RX << 24) /**< Shifted mode RX2RX for RAC_STATUS */ +#define RAC_STATUS_STATE_RXOVERFLOW (_RAC_STATUS_STATE_RXOVERFLOW << 24) /**< Shifted mode RXOVERFLOW for RAC_STATUS */ +#define RAC_STATUS_STATE_RX2TX (_RAC_STATUS_STATE_RX2TX << 24) /**< Shifted mode RX2TX for RAC_STATUS */ +#define RAC_STATUS_STATE_TXWARM (_RAC_STATUS_STATE_TXWARM << 24) /**< Shifted mode TXWARM for RAC_STATUS */ +#define RAC_STATUS_STATE_TX (_RAC_STATUS_STATE_TX << 24) /**< Shifted mode TX for RAC_STATUS */ +#define RAC_STATUS_STATE_TXPD (_RAC_STATUS_STATE_TXPD << 24) /**< Shifted mode TXPD for RAC_STATUS */ +#define RAC_STATUS_STATE_TX2RX (_RAC_STATUS_STATE_TX2RX << 24) /**< Shifted mode TX2RX for RAC_STATUS */ +#define RAC_STATUS_STATE_TX2TX (_RAC_STATUS_STATE_TX2TX << 24) /**< Shifted mode TX2TX for RAC_STATUS */ +#define RAC_STATUS_STATE_SHUTDOWN (_RAC_STATUS_STATE_SHUTDOWN << 24) /**< Shifted mode SHUTDOWN for RAC_STATUS */ +#define RAC_STATUS_STATE_POR (_RAC_STATUS_STATE_POR << 24) /**< Shifted mode POR for RAC_STATUS */ +#define RAC_STATUS_SEQACTIVE (0x1UL << 28) /**< SEQ active */ +#define _RAC_STATUS_SEQACTIVE_SHIFT 28 /**< Shift value for RAC_SEQACTIVE */ +#define _RAC_STATUS_SEQACTIVE_MASK 0x10000000UL /**< Bit mask for RAC_SEQACTIVE */ +#define _RAC_STATUS_SEQACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_SEQACTIVE_DEFAULT (_RAC_STATUS_SEQACTIVE_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_TXENS (0x1UL << 30) /**< TXEN Status */ +#define _RAC_STATUS_TXENS_SHIFT 30 /**< Shift value for RAC_TXENS */ +#define _RAC_STATUS_TXENS_MASK 0x40000000UL /**< Bit mask for RAC_TXENS */ +#define _RAC_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_TXENS_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */ +#define _RAC_STATUS_TXENS_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */ +#define RAC_STATUS_TXENS_DEFAULT (_RAC_STATUS_TXENS_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_TXENS_X0 (_RAC_STATUS_TXENS_X0 << 30) /**< Shifted mode X0 for RAC_STATUS */ +#define RAC_STATUS_TXENS_X1 (_RAC_STATUS_TXENS_X1 << 30) /**< Shifted mode X1 for RAC_STATUS */ +#define RAC_STATUS_RXENS (0x1UL << 31) /**< RXEN Status */ +#define _RAC_STATUS_RXENS_SHIFT 31 /**< Shift value for RAC_RXENS */ +#define _RAC_STATUS_RXENS_MASK 0x80000000UL /**< Bit mask for RAC_RXENS */ +#define _RAC_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */ +#define _RAC_STATUS_RXENS_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */ +#define _RAC_STATUS_RXENS_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */ +#define RAC_STATUS_RXENS_DEFAULT (_RAC_STATUS_RXENS_DEFAULT << 31) /**< Shifted mode DEFAULT for RAC_STATUS */ +#define RAC_STATUS_RXENS_X0 (_RAC_STATUS_RXENS_X0 << 31) /**< Shifted mode X0 for RAC_STATUS */ +#define RAC_STATUS_RXENS_X1 (_RAC_STATUS_RXENS_X1 << 31) /**< Shifted mode X1 for RAC_STATUS */ + +/* Bit fields for RAC CMD */ +#define _RAC_CMD_RESETVALUE 0x00000000UL /**< Default value for RAC_CMD */ +#define _RAC_CMD_MASK 0xC000FDFFUL /**< Mask for RAC_CMD */ +#define RAC_CMD_TXEN (0x1UL << 0) /**< Transmitter Enable */ +#define _RAC_CMD_TXEN_SHIFT 0 /**< Shift value for RAC_TXEN */ +#define _RAC_CMD_TXEN_MASK 0x1UL /**< Bit mask for RAC_TXEN */ +#define _RAC_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXEN_DEFAULT (_RAC_CMD_TXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FORCETX (0x1UL << 1) /**< Force TX Command */ +#define _RAC_CMD_FORCETX_SHIFT 1 /**< Shift value for RAC_FORCETX */ +#define _RAC_CMD_FORCETX_MASK 0x2UL /**< Bit mask for RAC_FORCETX */ +#define _RAC_CMD_FORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FORCETX_DEFAULT (_RAC_CMD_FORCETX_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXONCCA (0x1UL << 2) /**< Transmit On CCA */ +#define _RAC_CMD_TXONCCA_SHIFT 2 /**< Shift value for RAC_TXONCCA */ +#define _RAC_CMD_TXONCCA_MASK 0x4UL /**< Bit mask for RAC_TXONCCA */ +#define _RAC_CMD_TXONCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXONCCA_DEFAULT (_RAC_CMD_TXONCCA_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_CLEARTXEN (0x1UL << 3) /**< Clear TX Enable */ +#define _RAC_CMD_CLEARTXEN_SHIFT 3 /**< Shift value for RAC_CLEARTXEN */ +#define _RAC_CMD_CLEARTXEN_MASK 0x8UL /**< Bit mask for RAC_CLEARTXEN */ +#define _RAC_CMD_CLEARTXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_CLEARTXEN_DEFAULT (_RAC_CMD_CLEARTXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXAFTERFRAME (0x1UL << 4) /**< TX After Frame */ +#define _RAC_CMD_TXAFTERFRAME_SHIFT 4 /**< Shift value for RAC_TXAFTERFRAME */ +#define _RAC_CMD_TXAFTERFRAME_MASK 0x10UL /**< Bit mask for RAC_TXAFTERFRAME */ +#define _RAC_CMD_TXAFTERFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXAFTERFRAME_DEFAULT (_RAC_CMD_TXAFTERFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXDIS (0x1UL << 5) /**< TX Disable */ +#define _RAC_CMD_TXDIS_SHIFT 5 /**< Shift value for RAC_TXDIS */ +#define _RAC_CMD_TXDIS_MASK 0x20UL /**< Bit mask for RAC_TXDIS */ +#define _RAC_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_TXDIS_DEFAULT (_RAC_CMD_TXDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_CLEARRXOVERFLOW (0x1UL << 6) /**< Clear RX Overflow */ +#define _RAC_CMD_CLEARRXOVERFLOW_SHIFT 6 /**< Shift value for RAC_CLEARRXOVERFLOW */ +#define _RAC_CMD_CLEARRXOVERFLOW_MASK 0x40UL /**< Bit mask for RAC_CLEARRXOVERFLOW */ +#define _RAC_CMD_CLEARRXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_CLEARRXOVERFLOW_DEFAULT (_RAC_CMD_CLEARRXOVERFLOW_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_RXCAL (0x1UL << 7) /**< Start an RX Calibration */ +#define _RAC_CMD_RXCAL_SHIFT 7 /**< Shift value for RAC_RXCAL */ +#define _RAC_CMD_RXCAL_MASK 0x80UL /**< Bit mask for RAC_RXCAL */ +#define _RAC_CMD_RXCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_RXCAL_DEFAULT (_RAC_CMD_RXCAL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_RXDIS (0x1UL << 8) /**< RX Disable */ +#define _RAC_CMD_RXDIS_SHIFT 8 /**< Shift value for RAC_RXDIS */ +#define _RAC_CMD_RXDIS_MASK 0x100UL /**< Bit mask for RAC_RXDIS */ +#define _RAC_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_RXDIS_DEFAULT (_RAC_CMD_RXDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FRCWR (0x1UL << 10) /**< FRC write cmd */ +#define _RAC_CMD_FRCWR_SHIFT 10 /**< Shift value for RAC_FRCWR */ +#define _RAC_CMD_FRCWR_MASK 0x400UL /**< Bit mask for RAC_FRCWR */ +#define _RAC_CMD_FRCWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FRCWR_DEFAULT (_RAC_CMD_FRCWR_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FRCRD (0x1UL << 11) /**< FRC read cmd */ +#define _RAC_CMD_FRCRD_SHIFT 11 /**< Shift value for RAC_FRCRD */ +#define _RAC_CMD_FRCRD_MASK 0x800UL /**< Bit mask for RAC_FRCRD */ +#define _RAC_CMD_FRCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_FRCRD_DEFAULT (_RAC_CMD_FRCRD_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_PAENSET (0x1UL << 12) /**< PAEN Set */ +#define _RAC_CMD_PAENSET_SHIFT 12 /**< Shift value for RAC_PAENSET */ +#define _RAC_CMD_PAENSET_MASK 0x1000UL /**< Bit mask for RAC_PAENSET */ +#define _RAC_CMD_PAENSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_PAENSET_DEFAULT (_RAC_CMD_PAENSET_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_PAENCLEAR (0x1UL << 13) /**< PAEN Clear */ +#define _RAC_CMD_PAENCLEAR_SHIFT 13 /**< Shift value for RAC_PAENCLEAR */ +#define _RAC_CMD_PAENCLEAR_MASK 0x2000UL /**< Bit mask for RAC_PAENCLEAR */ +#define _RAC_CMD_PAENCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_PAENCLEAR_DEFAULT (_RAC_CMD_PAENCLEAR_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_LNAENSET (0x1UL << 14) /**< LNAEN Set */ +#define _RAC_CMD_LNAENSET_SHIFT 14 /**< Shift value for RAC_LNAENSET */ +#define _RAC_CMD_LNAENSET_MASK 0x4000UL /**< Bit mask for RAC_LNAENSET */ +#define _RAC_CMD_LNAENSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_LNAENSET_DEFAULT (_RAC_CMD_LNAENSET_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CMD */ +#define RAC_CMD_LNAENCLEAR (0x1UL << 15) /**< LNAEN Clear */ +#define _RAC_CMD_LNAENCLEAR_SHIFT 15 /**< Shift value for RAC_LNAENCLEAR */ +#define _RAC_CMD_LNAENCLEAR_MASK 0x8000UL /**< Bit mask for RAC_LNAENCLEAR */ +#define _RAC_CMD_LNAENCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */ +#define RAC_CMD_LNAENCLEAR_DEFAULT (_RAC_CMD_LNAENCLEAR_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_CMD */ + +/* Bit fields for RAC CTRL */ +#define _RAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_CTRL */ +#define _RAC_CTRL_MASK 0x1F0107EFUL /**< Mask for RAC_CTRL */ +#define RAC_CTRL_FORCEDISABLE (0x1UL << 0) /**< Force Radio Disable */ +#define _RAC_CTRL_FORCEDISABLE_SHIFT 0 /**< Shift value for RAC_FORCEDISABLE */ +#define _RAC_CTRL_FORCEDISABLE_MASK 0x1UL /**< Bit mask for RAC_FORCEDISABLE */ +#define _RAC_CTRL_FORCEDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_FORCEDISABLE_DEFAULT (_RAC_CTRL_FORCEDISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSTXEN (0x1UL << 1) /**< PRS TX Enable */ +#define _RAC_CTRL_PRSTXEN_SHIFT 1 /**< Shift value for RAC_PRSTXEN */ +#define _RAC_CTRL_PRSTXEN_MASK 0x2UL /**< Bit mask for RAC_PRSTXEN */ +#define _RAC_CTRL_PRSTXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSTXEN_DEFAULT (_RAC_CTRL_PRSTXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_TXAFTERRX (0x1UL << 2) /**< TX After RX */ +#define _RAC_CTRL_TXAFTERRX_SHIFT 2 /**< Shift value for RAC_TXAFTERRX */ +#define _RAC_CTRL_TXAFTERRX_MASK 0x4UL /**< Bit mask for RAC_TXAFTERRX */ +#define _RAC_CTRL_TXAFTERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_TXAFTERRX_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_TXAFTERRX_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_TXAFTERRX_DEFAULT (_RAC_CTRL_TXAFTERRX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_TXAFTERRX_X0 (_RAC_CTRL_TXAFTERRX_X0 << 2) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_TXAFTERRX_X1 (_RAC_CTRL_TXAFTERRX_X1 << 2) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_PRSMODE (0x1UL << 3) /**< PRS RXEN Mode */ +#define _RAC_CTRL_PRSMODE_SHIFT 3 /**< Shift value for RAC_PRSMODE */ +#define _RAC_CTRL_PRSMODE_MASK 0x8UL /**< Bit mask for RAC_PRSMODE */ +#define _RAC_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_PRSMODE_DIRECT 0x00000000UL /**< Mode DIRECT for RAC_CTRL */ +#define _RAC_CTRL_PRSMODE_PULSE 0x00000001UL /**< Mode PULSE for RAC_CTRL */ +#define RAC_CTRL_PRSMODE_DEFAULT (_RAC_CTRL_PRSMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSMODE_DIRECT (_RAC_CTRL_PRSMODE_DIRECT << 3) /**< Shifted mode DIRECT for RAC_CTRL */ +#define RAC_CTRL_PRSMODE_PULSE (_RAC_CTRL_PRSMODE_PULSE << 3) /**< Shifted mode PULSE for RAC_CTRL */ +#define RAC_CTRL_PRSCLR (0x1UL << 5) /**< PRS RXEN Clear */ +#define _RAC_CTRL_PRSCLR_SHIFT 5 /**< Shift value for RAC_PRSCLR */ +#define _RAC_CTRL_PRSCLR_MASK 0x20UL /**< Bit mask for RAC_PRSCLR */ +#define _RAC_CTRL_PRSCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_PRSCLR_RXSEARCH 0x00000000UL /**< Mode RXSEARCH for RAC_CTRL */ +#define _RAC_CTRL_PRSCLR_PRSCH 0x00000001UL /**< Mode PRSCH for RAC_CTRL */ +#define RAC_CTRL_PRSCLR_DEFAULT (_RAC_CTRL_PRSCLR_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSCLR_RXSEARCH (_RAC_CTRL_PRSCLR_RXSEARCH << 5) /**< Shifted mode RXSEARCH for RAC_CTRL */ +#define RAC_CTRL_PRSCLR_PRSCH (_RAC_CTRL_PRSCLR_PRSCH << 5) /**< Shifted mode PRSCH for RAC_CTRL */ +#define RAC_CTRL_TXPOSTPONE (0x1UL << 6) /**< TX Postpone */ +#define _RAC_CTRL_TXPOSTPONE_SHIFT 6 /**< Shift value for RAC_TXPOSTPONE */ +#define _RAC_CTRL_TXPOSTPONE_MASK 0x40UL /**< Bit mask for RAC_TXPOSTPONE */ +#define _RAC_CTRL_TXPOSTPONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_TXPOSTPONE_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_TXPOSTPONE_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_TXPOSTPONE_DEFAULT (_RAC_CTRL_TXPOSTPONE_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_TXPOSTPONE_X0 (_RAC_CTRL_TXPOSTPONE_X0 << 6) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_TXPOSTPONE_X1 (_RAC_CTRL_TXPOSTPONE_X1 << 6) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_ACTIVEPOL (0x1UL << 7) /**< ACTIVE signal polarity */ +#define _RAC_CTRL_ACTIVEPOL_SHIFT 7 /**< Shift value for RAC_ACTIVEPOL */ +#define _RAC_CTRL_ACTIVEPOL_MASK 0x80UL /**< Bit mask for RAC_ACTIVEPOL */ +#define _RAC_CTRL_ACTIVEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_ACTIVEPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_ACTIVEPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_ACTIVEPOL_DEFAULT (_RAC_CTRL_ACTIVEPOL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_ACTIVEPOL_X0 (_RAC_CTRL_ACTIVEPOL_X0 << 7) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_ACTIVEPOL_X1 (_RAC_CTRL_ACTIVEPOL_X1 << 7) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_PAENPOL (0x1UL << 8) /**< PAEN signal polarity */ +#define _RAC_CTRL_PAENPOL_SHIFT 8 /**< Shift value for RAC_PAENPOL */ +#define _RAC_CTRL_PAENPOL_MASK 0x100UL /**< Bit mask for RAC_PAENPOL */ +#define _RAC_CTRL_PAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_PAENPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_PAENPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_PAENPOL_DEFAULT (_RAC_CTRL_PAENPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PAENPOL_X0 (_RAC_CTRL_PAENPOL_X0 << 8) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_PAENPOL_X1 (_RAC_CTRL_PAENPOL_X1 << 8) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_LNAENPOL (0x1UL << 9) /**< LNAEN signal polarity */ +#define _RAC_CTRL_LNAENPOL_SHIFT 9 /**< Shift value for RAC_LNAENPOL */ +#define _RAC_CTRL_LNAENPOL_MASK 0x200UL /**< Bit mask for RAC_LNAENPOL */ +#define _RAC_CTRL_LNAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_LNAENPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_LNAENPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_LNAENPOL_DEFAULT (_RAC_CTRL_LNAENPOL_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_LNAENPOL_X0 (_RAC_CTRL_LNAENPOL_X0 << 9) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_LNAENPOL_X1 (_RAC_CTRL_LNAENPOL_X1 << 9) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_PRSRXDIS (0x1UL << 10) /**< PRS RX Disable */ +#define _RAC_CTRL_PRSRXDIS_SHIFT 10 /**< Shift value for RAC_PRSRXDIS */ +#define _RAC_CTRL_PRSRXDIS_MASK 0x400UL /**< Bit mask for RAC_PRSRXDIS */ +#define _RAC_CTRL_PRSRXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_PRSRXDIS_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_PRSRXDIS_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_PRSRXDIS_DEFAULT (_RAC_CTRL_PRSRXDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSRXDIS_X0 (_RAC_CTRL_PRSRXDIS_X0 << 10) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_PRSRXDIS_X1 (_RAC_CTRL_PRSRXDIS_X1 << 10) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_PRSFORCETX (0x1UL << 16) /**< PRS Force RX */ +#define _RAC_CTRL_PRSFORCETX_SHIFT 16 /**< Shift value for RAC_PRSFORCETX */ +#define _RAC_CTRL_PRSFORCETX_MASK 0x10000UL /**< Bit mask for RAC_PRSFORCETX */ +#define _RAC_CTRL_PRSFORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define _RAC_CTRL_PRSFORCETX_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */ +#define _RAC_CTRL_PRSFORCETX_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */ +#define RAC_CTRL_PRSFORCETX_DEFAULT (_RAC_CTRL_PRSFORCETX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_PRSFORCETX_X0 (_RAC_CTRL_PRSFORCETX_X0 << 16) /**< Shifted mode X0 for RAC_CTRL */ +#define RAC_CTRL_PRSFORCETX_X1 (_RAC_CTRL_PRSFORCETX_X1 << 16) /**< Shifted mode X1 for RAC_CTRL */ +#define RAC_CTRL_SEQRESET (0x1UL << 24) /**< SEQ reset */ +#define _RAC_CTRL_SEQRESET_SHIFT 24 /**< Shift value for RAC_SEQRESET */ +#define _RAC_CTRL_SEQRESET_MASK 0x1000000UL /**< Bit mask for RAC_SEQRESET */ +#define _RAC_CTRL_SEQRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_SEQRESET_DEFAULT (_RAC_CTRL_SEQRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_EXITSHUTDOWNDIS (0x1UL << 25) /**< Exit SHUTDOWN state Disable */ +#define _RAC_CTRL_EXITSHUTDOWNDIS_SHIFT 25 /**< Shift value for RAC_EXITSHUTDOWNDIS */ +#define _RAC_CTRL_EXITSHUTDOWNDIS_MASK 0x2000000UL /**< Bit mask for RAC_EXITSHUTDOWNDIS */ +#define _RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT (_RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_CPUWAITDIS (0x1UL << 26) /**< SEQ CPU Wait Disable */ +#define _RAC_CTRL_CPUWAITDIS_SHIFT 26 /**< Shift value for RAC_CPUWAITDIS */ +#define _RAC_CTRL_CPUWAITDIS_MASK 0x4000000UL /**< Bit mask for RAC_CPUWAITDIS */ +#define _RAC_CTRL_CPUWAITDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_CPUWAITDIS_DEFAULT (_RAC_CTRL_CPUWAITDIS_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_SEQCLKDIS (0x1UL << 27) /**< SEQ Clk Disable */ +#define _RAC_CTRL_SEQCLKDIS_SHIFT 27 /**< Shift value for RAC_SEQCLKDIS */ +#define _RAC_CTRL_SEQCLKDIS_MASK 0x8000000UL /**< Bit mask for RAC_SEQCLKDIS */ +#define _RAC_CTRL_SEQCLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_SEQCLKDIS_DEFAULT (_RAC_CTRL_SEQCLKDIS_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_RXOFDIS (0x1UL << 28) /**< Switch to RXOVERFLOW Disable */ +#define _RAC_CTRL_RXOFDIS_SHIFT 28 /**< Shift value for RAC_RXOFDIS */ +#define _RAC_CTRL_RXOFDIS_MASK 0x10000000UL /**< Bit mask for RAC_RXOFDIS */ +#define _RAC_CTRL_RXOFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */ +#define RAC_CTRL_RXOFDIS_DEFAULT (_RAC_CTRL_RXOFDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_CTRL */ + +/* Bit fields for RAC FORCESTATE */ +#define _RAC_FORCESTATE_RESETVALUE 0x00000000UL /**< Default value for RAC_FORCESTATE */ +#define _RAC_FORCESTATE_MASK 0x0000000FUL /**< Mask for RAC_FORCESTATE */ +#define _RAC_FORCESTATE_FORCESTATE_SHIFT 0 /**< Shift value for RAC_FORCESTATE */ +#define _RAC_FORCESTATE_FORCESTATE_MASK 0xFUL /**< Bit mask for RAC_FORCESTATE */ +#define _RAC_FORCESTATE_FORCESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FORCESTATE */ +#define RAC_FORCESTATE_FORCESTATE_DEFAULT (_RAC_FORCESTATE_FORCESTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FORCESTATE */ + +/* Bit fields for RAC IF */ +#define _RAC_IF_RESETVALUE 0x00000000UL /**< Default value for RAC_IF */ +#define _RAC_IF_MASK 0x00FF000FUL /**< Mask for RAC_IF */ +#define RAC_IF_STATECHANGE (0x1UL << 0) /**< Radio State Change */ +#define _RAC_IF_STATECHANGE_SHIFT 0 /**< Shift value for RAC_STATECHANGE */ +#define _RAC_IF_STATECHANGE_MASK 0x1UL /**< Bit mask for RAC_STATECHANGE */ +#define _RAC_IF_STATECHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */ +#define RAC_IF_STATECHANGE_DEFAULT (_RAC_IF_STATECHANGE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IF */ +#define RAC_IF_STIMCMPEV (0x1UL << 1) /**< STIMER Compare Event */ +#define _RAC_IF_STIMCMPEV_SHIFT 1 /**< Shift value for RAC_STIMCMPEV */ +#define _RAC_IF_STIMCMPEV_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEV */ +#define _RAC_IF_STIMCMPEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */ +#define RAC_IF_STIMCMPEV_DEFAULT (_RAC_IF_STIMCMPEV_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IF */ +#define RAC_IF_SEQLOCKUP (0x1UL << 2) /**< SEQ locked up */ +#define _RAC_IF_SEQLOCKUP_SHIFT 2 /**< Shift value for RAC_SEQLOCKUP */ +#define _RAC_IF_SEQLOCKUP_MASK 0x4UL /**< Bit mask for RAC_SEQLOCKUP */ +#define _RAC_IF_SEQLOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */ +#define RAC_IF_SEQLOCKUP_DEFAULT (_RAC_IF_SEQLOCKUP_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IF */ +#define RAC_IF_SEQRESETREQ (0x1UL << 3) /**< SEQ reset request */ +#define _RAC_IF_SEQRESETREQ_SHIFT 3 /**< Shift value for RAC_SEQRESETREQ */ +#define _RAC_IF_SEQRESETREQ_MASK 0x8UL /**< Bit mask for RAC_SEQRESETREQ */ +#define _RAC_IF_SEQRESETREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */ +#define RAC_IF_SEQRESETREQ_DEFAULT (_RAC_IF_SEQRESETREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IF */ +#define _RAC_IF_SEQ_SHIFT 16 /**< Shift value for RAC_SEQ */ +#define _RAC_IF_SEQ_MASK 0xFF0000UL /**< Bit mask for RAC_SEQ */ +#define _RAC_IF_SEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */ +#define RAC_IF_SEQ_DEFAULT (_RAC_IF_SEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IF */ + +/* Bit fields for RAC IEN */ +#define _RAC_IEN_RESETVALUE 0x00000000UL /**< Default value for RAC_IEN */ +#define _RAC_IEN_MASK 0x00FF000FUL /**< Mask for RAC_IEN */ +#define RAC_IEN_STATECHANGE (0x1UL << 0) /**< Radio State Change Interrupt Enable */ +#define _RAC_IEN_STATECHANGE_SHIFT 0 /**< Shift value for RAC_STATECHANGE */ +#define _RAC_IEN_STATECHANGE_MASK 0x1UL /**< Bit mask for RAC_STATECHANGE */ +#define _RAC_IEN_STATECHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */ +#define RAC_IEN_STATECHANGE_DEFAULT (_RAC_IEN_STATECHANGE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IEN */ +#define RAC_IEN_STIMCMPEV (0x1UL << 1) /**< STIMER Compare Event Interrupt Enable */ +#define _RAC_IEN_STIMCMPEV_SHIFT 1 /**< Shift value for RAC_STIMCMPEV */ +#define _RAC_IEN_STIMCMPEV_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEV */ +#define _RAC_IEN_STIMCMPEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */ +#define RAC_IEN_STIMCMPEV_DEFAULT (_RAC_IEN_STIMCMPEV_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IEN */ +#define RAC_IEN_SEQLOCKUP (0x1UL << 2) /**< SEQ locked up Interrupt Enable */ +#define _RAC_IEN_SEQLOCKUP_SHIFT 2 /**< Shift value for RAC_SEQLOCKUP */ +#define _RAC_IEN_SEQLOCKUP_MASK 0x4UL /**< Bit mask for RAC_SEQLOCKUP */ +#define _RAC_IEN_SEQLOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */ +#define RAC_IEN_SEQLOCKUP_DEFAULT (_RAC_IEN_SEQLOCKUP_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IEN */ +#define RAC_IEN_SEQRESETREQ (0x1UL << 3) /**< SEQ reset request Interrupt Enable */ +#define _RAC_IEN_SEQRESETREQ_SHIFT 3 /**< Shift value for RAC_SEQRESETREQ */ +#define _RAC_IEN_SEQRESETREQ_MASK 0x8UL /**< Bit mask for RAC_SEQRESETREQ */ +#define _RAC_IEN_SEQRESETREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */ +#define RAC_IEN_SEQRESETREQ_DEFAULT (_RAC_IEN_SEQRESETREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IEN */ +#define _RAC_IEN_SEQ_SHIFT 16 /**< Shift value for RAC_SEQ */ +#define _RAC_IEN_SEQ_MASK 0xFF0000UL /**< Bit mask for RAC_SEQ */ +#define _RAC_IEN_SEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */ +#define RAC_IEN_SEQ_DEFAULT (_RAC_IEN_SEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IEN */ + +/* Bit fields for RAC TESTCTRL */ +#define _RAC_TESTCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_TESTCTRL */ +#define _RAC_TESTCTRL_MASK 0x00000003UL /**< Mask for RAC_TESTCTRL */ +#define RAC_TESTCTRL_MODEN (0x1UL << 0) /**< Modulator enable */ +#define _RAC_TESTCTRL_MODEN_SHIFT 0 /**< Shift value for RAC_MODEN */ +#define _RAC_TESTCTRL_MODEN_MASK 0x1UL /**< Bit mask for RAC_MODEN */ +#define _RAC_TESTCTRL_MODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TESTCTRL */ +#define RAC_TESTCTRL_MODEN_DEFAULT (_RAC_TESTCTRL_MODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TESTCTRL */ +#define RAC_TESTCTRL_DEMODEN (0x1UL << 1) /**< Demodulator enable */ +#define _RAC_TESTCTRL_DEMODEN_SHIFT 1 /**< Shift value for RAC_DEMODEN */ +#define _RAC_TESTCTRL_DEMODEN_MASK 0x2UL /**< Bit mask for RAC_DEMODEN */ +#define _RAC_TESTCTRL_DEMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TESTCTRL */ +#define RAC_TESTCTRL_DEMODEN_DEFAULT (_RAC_TESTCTRL_DEMODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_TESTCTRL */ + +/* Bit fields for RAC SEQIF */ +#define _RAC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQIF */ +#define _RAC_SEQIF_MASK 0x3FFF000FUL /**< Mask for RAC_SEQIF */ +#define RAC_SEQIF_STATECHANGESEQ (0x1UL << 0) /**< Radio State Change */ +#define _RAC_SEQIF_STATECHANGESEQ_SHIFT 0 /**< Shift value for RAC_STATECHANGESEQ */ +#define _RAC_SEQIF_STATECHANGESEQ_MASK 0x1UL /**< Bit mask for RAC_STATECHANGESEQ */ +#define _RAC_SEQIF_STATECHANGESEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATECHANGESEQ_DEFAULT (_RAC_SEQIF_STATECHANGESEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STIMCMPEVSEQ (0x1UL << 1) /**< STIMER Compare Event */ +#define _RAC_SEQIF_STIMCMPEVSEQ_SHIFT 1 /**< Shift value for RAC_STIMCMPEVSEQ */ +#define _RAC_SEQIF_STIMCMPEVSEQ_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEVSEQ */ +#define _RAC_SEQIF_STIMCMPEVSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STIMCMPEVSEQ_DEFAULT (_RAC_SEQIF_STIMCMPEVSEQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_DEMODRXREQCLRSEQ (0x1UL << 2) /**< Demod RX request clear */ +#define _RAC_SEQIF_DEMODRXREQCLRSEQ_SHIFT 2 /**< Shift value for RAC_DEMODRXREQCLRSEQ */ +#define _RAC_SEQIF_DEMODRXREQCLRSEQ_MASK 0x4UL /**< Bit mask for RAC_DEMODRXREQCLRSEQ */ +#define _RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT (_RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_PRSEVENTSEQ (0x1UL << 3) /**< SEQ PRS Event */ +#define _RAC_SEQIF_PRSEVENTSEQ_SHIFT 3 /**< Shift value for RAC_PRSEVENTSEQ */ +#define _RAC_SEQIF_PRSEVENTSEQ_MASK 0x8UL /**< Bit mask for RAC_PRSEVENTSEQ */ +#define _RAC_SEQIF_PRSEVENTSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_PRSEVENTSEQ_DEFAULT (_RAC_SEQIF_PRSEVENTSEQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATEOFF (0x1UL << 16) /**< entering STATE_OFF */ +#define _RAC_SEQIF_STATEOFF_SHIFT 16 /**< Shift value for RAC_STATEOFF */ +#define _RAC_SEQIF_STATEOFF_MASK 0x10000UL /**< Bit mask for RAC_STATEOFF */ +#define _RAC_SEQIF_STATEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATEOFF_DEFAULT (_RAC_SEQIF_STATEOFF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXWARM (0x1UL << 17) /**< entering STATE_RXWARM */ +#define _RAC_SEQIF_STATERXWARM_SHIFT 17 /**< Shift value for RAC_STATERXWARM */ +#define _RAC_SEQIF_STATERXWARM_MASK 0x20000UL /**< Bit mask for RAC_STATERXWARM */ +#define _RAC_SEQIF_STATERXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXWARM_DEFAULT (_RAC_SEQIF_STATERXWARM_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXSEARCH (0x1UL << 18) /**< entering STATE_RXSEARCH */ +#define _RAC_SEQIF_STATERXSEARCH_SHIFT 18 /**< Shift value for RAC_STATERXSEARCH */ +#define _RAC_SEQIF_STATERXSEARCH_MASK 0x40000UL /**< Bit mask for RAC_STATERXSEARCH */ +#define _RAC_SEQIF_STATERXSEARCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXSEARCH_DEFAULT (_RAC_SEQIF_STATERXSEARCH_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXFRAME (0x1UL << 19) /**< entering STATE_RXFRAME */ +#define _RAC_SEQIF_STATERXFRAME_SHIFT 19 /**< Shift value for RAC_STATERXFRAME */ +#define _RAC_SEQIF_STATERXFRAME_MASK 0x80000UL /**< Bit mask for RAC_STATERXFRAME */ +#define _RAC_SEQIF_STATERXFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXFRAME_DEFAULT (_RAC_SEQIF_STATERXFRAME_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXPD (0x1UL << 20) /**< entering STATE_RXPD */ +#define _RAC_SEQIF_STATERXPD_SHIFT 20 /**< Shift value for RAC_STATERXPD */ +#define _RAC_SEQIF_STATERXPD_MASK 0x100000UL /**< Bit mask for RAC_STATERXPD */ +#define _RAC_SEQIF_STATERXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXPD_DEFAULT (_RAC_SEQIF_STATERXPD_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERX2RX (0x1UL << 21) /**< entering STATE_RX2RX */ +#define _RAC_SEQIF_STATERX2RX_SHIFT 21 /**< Shift value for RAC_STATERX2RX */ +#define _RAC_SEQIF_STATERX2RX_MASK 0x200000UL /**< Bit mask for RAC_STATERX2RX */ +#define _RAC_SEQIF_STATERX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERX2RX_DEFAULT (_RAC_SEQIF_STATERX2RX_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXOVERFLOW (0x1UL << 22) /**< entering STATE_RXOVERFLOW */ +#define _RAC_SEQIF_STATERXOVERFLOW_SHIFT 22 /**< Shift value for RAC_STATERXOVERFLOW */ +#define _RAC_SEQIF_STATERXOVERFLOW_MASK 0x400000UL /**< Bit mask for RAC_STATERXOVERFLOW */ +#define _RAC_SEQIF_STATERXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERXOVERFLOW_DEFAULT (_RAC_SEQIF_STATERXOVERFLOW_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERX2TX (0x1UL << 23) /**< entering STATE_RX2TX */ +#define _RAC_SEQIF_STATERX2TX_SHIFT 23 /**< Shift value for RAC_STATERX2TX */ +#define _RAC_SEQIF_STATERX2TX_MASK 0x800000UL /**< Bit mask for RAC_STATERX2TX */ +#define _RAC_SEQIF_STATERX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATERX2TX_DEFAULT (_RAC_SEQIF_STATERX2TX_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETXWARM (0x1UL << 24) /**< entering STATE_TXWARM */ +#define _RAC_SEQIF_STATETXWARM_SHIFT 24 /**< Shift value for RAC_STATETXWARM */ +#define _RAC_SEQIF_STATETXWARM_MASK 0x1000000UL /**< Bit mask for RAC_STATETXWARM */ +#define _RAC_SEQIF_STATETXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETXWARM_DEFAULT (_RAC_SEQIF_STATETXWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX (0x1UL << 25) /**< entering STATE_TX */ +#define _RAC_SEQIF_STATETX_SHIFT 25 /**< Shift value for RAC_STATETX */ +#define _RAC_SEQIF_STATETX_MASK 0x2000000UL /**< Bit mask for RAC_STATETX */ +#define _RAC_SEQIF_STATETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX_DEFAULT (_RAC_SEQIF_STATETX_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETXPD (0x1UL << 26) /**< entering STATE_TXPD */ +#define _RAC_SEQIF_STATETXPD_SHIFT 26 /**< Shift value for RAC_STATETXPD */ +#define _RAC_SEQIF_STATETXPD_MASK 0x4000000UL /**< Bit mask for RAC_STATETXPD */ +#define _RAC_SEQIF_STATETXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETXPD_DEFAULT (_RAC_SEQIF_STATETXPD_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX2RX (0x1UL << 27) /**< entering STATE_TX2RX */ +#define _RAC_SEQIF_STATETX2RX_SHIFT 27 /**< Shift value for RAC_STATETX2RX */ +#define _RAC_SEQIF_STATETX2RX_MASK 0x8000000UL /**< Bit mask for RAC_STATETX2RX */ +#define _RAC_SEQIF_STATETX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX2RX_DEFAULT (_RAC_SEQIF_STATETX2RX_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX2TX (0x1UL << 28) /**< entering STATE_TX2TX */ +#define _RAC_SEQIF_STATETX2TX_SHIFT 28 /**< Shift value for RAC_STATETX2TX */ +#define _RAC_SEQIF_STATETX2TX_MASK 0x10000000UL /**< Bit mask for RAC_STATETX2TX */ +#define _RAC_SEQIF_STATETX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATETX2TX_DEFAULT (_RAC_SEQIF_STATETX2TX_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATESHUTDOWN (0x1UL << 29) /**< entering STATE_SHUTDOWN */ +#define _RAC_SEQIF_STATESHUTDOWN_SHIFT 29 /**< Shift value for RAC_STATESHUTDOWN */ +#define _RAC_SEQIF_STATESHUTDOWN_MASK 0x20000000UL /**< Bit mask for RAC_STATESHUTDOWN */ +#define _RAC_SEQIF_STATESHUTDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */ +#define RAC_SEQIF_STATESHUTDOWN_DEFAULT (_RAC_SEQIF_STATESHUTDOWN_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_SEQIF */ + +/* Bit fields for RAC SEQIEN */ +#define _RAC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQIEN */ +#define _RAC_SEQIEN_MASK 0x3FFF000FUL /**< Mask for RAC_SEQIEN */ +#define RAC_SEQIEN_STATECHANGESEQ (0x1UL << 0) /**< Radio State Change Interrupt Enable */ +#define _RAC_SEQIEN_STATECHANGESEQ_SHIFT 0 /**< Shift value for RAC_STATECHANGESEQ */ +#define _RAC_SEQIEN_STATECHANGESEQ_MASK 0x1UL /**< Bit mask for RAC_STATECHANGESEQ */ +#define _RAC_SEQIEN_STATECHANGESEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATECHANGESEQ_DEFAULT (_RAC_SEQIEN_STATECHANGESEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STIMCMPEVSEQ (0x1UL << 1) /**< STIMER Compare Event Interrupt Enable */ +#define _RAC_SEQIEN_STIMCMPEVSEQ_SHIFT 1 /**< Shift value for RAC_STIMCMPEVSEQ */ +#define _RAC_SEQIEN_STIMCMPEVSEQ_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEVSEQ */ +#define _RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT (_RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_DEMODRXREQCLRSEQ (0x1UL << 2) /**< Demod RX req clr Interrupt Enable */ +#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_SHIFT 2 /**< Shift value for RAC_DEMODRXREQCLRSEQ */ +#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_MASK 0x4UL /**< Bit mask for RAC_DEMODRXREQCLRSEQ */ +#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT (_RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_PRSEVENTSEQ (0x1UL << 3) /**< PRS SEQ EVENT Interrupt Enable */ +#define _RAC_SEQIEN_PRSEVENTSEQ_SHIFT 3 /**< Shift value for RAC_PRSEVENTSEQ */ +#define _RAC_SEQIEN_PRSEVENTSEQ_MASK 0x8UL /**< Bit mask for RAC_PRSEVENTSEQ */ +#define _RAC_SEQIEN_PRSEVENTSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_PRSEVENTSEQ_DEFAULT (_RAC_SEQIEN_PRSEVENTSEQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATEOFF (0x1UL << 16) /**< STATE_OFF Interrupt Enable */ +#define _RAC_SEQIEN_STATEOFF_SHIFT 16 /**< Shift value for RAC_STATEOFF */ +#define _RAC_SEQIEN_STATEOFF_MASK 0x10000UL /**< Bit mask for RAC_STATEOFF */ +#define _RAC_SEQIEN_STATEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATEOFF_DEFAULT (_RAC_SEQIEN_STATEOFF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXWARM (0x1UL << 17) /**< STATE_RXWARM Interrupt Enable */ +#define _RAC_SEQIEN_STATERXWARM_SHIFT 17 /**< Shift value for RAC_STATERXWARM */ +#define _RAC_SEQIEN_STATERXWARM_MASK 0x20000UL /**< Bit mask for RAC_STATERXWARM */ +#define _RAC_SEQIEN_STATERXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXWARM_DEFAULT (_RAC_SEQIEN_STATERXWARM_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXSEARCH (0x1UL << 18) /**< STATE_RXSEARC Interrupt Enable */ +#define _RAC_SEQIEN_STATERXSEARCH_SHIFT 18 /**< Shift value for RAC_STATERXSEARCH */ +#define _RAC_SEQIEN_STATERXSEARCH_MASK 0x40000UL /**< Bit mask for RAC_STATERXSEARCH */ +#define _RAC_SEQIEN_STATERXSEARCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXSEARCH_DEFAULT (_RAC_SEQIEN_STATERXSEARCH_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXFRAME (0x1UL << 19) /**< STATE_RXFRAME Interrupt Enable */ +#define _RAC_SEQIEN_STATERXFRAME_SHIFT 19 /**< Shift value for RAC_STATERXFRAME */ +#define _RAC_SEQIEN_STATERXFRAME_MASK 0x80000UL /**< Bit mask for RAC_STATERXFRAME */ +#define _RAC_SEQIEN_STATERXFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXFRAME_DEFAULT (_RAC_SEQIEN_STATERXFRAME_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXPD (0x1UL << 20) /**< STATE_RXPD Interrupt Enable */ +#define _RAC_SEQIEN_STATERXPD_SHIFT 20 /**< Shift value for RAC_STATERXPD */ +#define _RAC_SEQIEN_STATERXPD_MASK 0x100000UL /**< Bit mask for RAC_STATERXPD */ +#define _RAC_SEQIEN_STATERXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXPD_DEFAULT (_RAC_SEQIEN_STATERXPD_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERX2RX (0x1UL << 21) /**< STATE_RX2RX Interrupt Enable */ +#define _RAC_SEQIEN_STATERX2RX_SHIFT 21 /**< Shift value for RAC_STATERX2RX */ +#define _RAC_SEQIEN_STATERX2RX_MASK 0x200000UL /**< Bit mask for RAC_STATERX2RX */ +#define _RAC_SEQIEN_STATERX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERX2RX_DEFAULT (_RAC_SEQIEN_STATERX2RX_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXOVERFLOW (0x1UL << 22) /**< STATE_RXOVERFLOW Interrupt Enable */ +#define _RAC_SEQIEN_STATERXOVERFLOW_SHIFT 22 /**< Shift value for RAC_STATERXOVERFLOW */ +#define _RAC_SEQIEN_STATERXOVERFLOW_MASK 0x400000UL /**< Bit mask for RAC_STATERXOVERFLOW */ +#define _RAC_SEQIEN_STATERXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERXOVERFLOW_DEFAULT (_RAC_SEQIEN_STATERXOVERFLOW_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERX2TX (0x1UL << 23) /**< STATE_RX2TX Interrupt Enable */ +#define _RAC_SEQIEN_STATERX2TX_SHIFT 23 /**< Shift value for RAC_STATERX2TX */ +#define _RAC_SEQIEN_STATERX2TX_MASK 0x800000UL /**< Bit mask for RAC_STATERX2TX */ +#define _RAC_SEQIEN_STATERX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATERX2TX_DEFAULT (_RAC_SEQIEN_STATERX2TX_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETXWARM (0x1UL << 24) /**< STATE_TXWARM Interrupt Enable */ +#define _RAC_SEQIEN_STATETXWARM_SHIFT 24 /**< Shift value for RAC_STATETXWARM */ +#define _RAC_SEQIEN_STATETXWARM_MASK 0x1000000UL /**< Bit mask for RAC_STATETXWARM */ +#define _RAC_SEQIEN_STATETXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETXWARM_DEFAULT (_RAC_SEQIEN_STATETXWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX (0x1UL << 25) /**< STATE_TX Interrupt Enable */ +#define _RAC_SEQIEN_STATETX_SHIFT 25 /**< Shift value for RAC_STATETX */ +#define _RAC_SEQIEN_STATETX_MASK 0x2000000UL /**< Bit mask for RAC_STATETX */ +#define _RAC_SEQIEN_STATETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX_DEFAULT (_RAC_SEQIEN_STATETX_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETXPD (0x1UL << 26) /**< STATE_TXPD Interrupt Enable */ +#define _RAC_SEQIEN_STATETXPD_SHIFT 26 /**< Shift value for RAC_STATETXPD */ +#define _RAC_SEQIEN_STATETXPD_MASK 0x4000000UL /**< Bit mask for RAC_STATETXPD */ +#define _RAC_SEQIEN_STATETXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETXPD_DEFAULT (_RAC_SEQIEN_STATETXPD_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX2RX (0x1UL << 27) /**< STATE_TX2RX Interrupt Enable */ +#define _RAC_SEQIEN_STATETX2RX_SHIFT 27 /**< Shift value for RAC_STATETX2RX */ +#define _RAC_SEQIEN_STATETX2RX_MASK 0x8000000UL /**< Bit mask for RAC_STATETX2RX */ +#define _RAC_SEQIEN_STATETX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX2RX_DEFAULT (_RAC_SEQIEN_STATETX2RX_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX2TX (0x1UL << 28) /**< STATE_TX2TX Interrupt Enable */ +#define _RAC_SEQIEN_STATETX2TX_SHIFT 28 /**< Shift value for RAC_STATETX2TX */ +#define _RAC_SEQIEN_STATETX2TX_MASK 0x10000000UL /**< Bit mask for RAC_STATETX2TX */ +#define _RAC_SEQIEN_STATETX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATETX2TX_DEFAULT (_RAC_SEQIEN_STATETX2TX_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATESHUTDOWN (0x1UL << 29) /**< STATE_SHUTDOWN Interrupt Enable */ +#define _RAC_SEQIEN_STATESHUTDOWN_SHIFT 29 /**< Shift value for RAC_STATESHUTDOWN */ +#define _RAC_SEQIEN_STATESHUTDOWN_MASK 0x20000000UL /**< Bit mask for RAC_STATESHUTDOWN */ +#define _RAC_SEQIEN_STATESHUTDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */ +#define RAC_SEQIEN_STATESHUTDOWN_DEFAULT (_RAC_SEQIEN_STATESHUTDOWN_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_SEQIEN */ + +/* Bit fields for RAC STATUS1 */ +#define _RAC_STATUS1_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS1 */ +#define _RAC_STATUS1_MASK 0x000000FFUL /**< Mask for RAC_STATUS1 */ +#define _RAC_STATUS1_TXMASK_SHIFT 0 /**< Shift value for RAC_TXMASK */ +#define _RAC_STATUS1_TXMASK_MASK 0xFFUL /**< Bit mask for RAC_TXMASK */ +#define _RAC_STATUS1_TXMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS1 */ +#define RAC_STATUS1_TXMASK_DEFAULT (_RAC_STATUS1_TXMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS1 */ + +/* Bit fields for RAC STIMER */ +#define _RAC_STIMER_RESETVALUE 0x00000000UL /**< Default value for RAC_STIMER */ +#define _RAC_STIMER_MASK 0x0000FFFFUL /**< Mask for RAC_STIMER */ +#define _RAC_STIMER_STIMER_SHIFT 0 /**< Shift value for RAC_STIMER */ +#define _RAC_STIMER_STIMER_MASK 0xFFFFUL /**< Bit mask for RAC_STIMER */ +#define _RAC_STIMER_STIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STIMER */ +#define RAC_STIMER_STIMER_DEFAULT (_RAC_STIMER_STIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STIMER */ + +/* Bit fields for RAC STIMERCOMP */ +#define _RAC_STIMERCOMP_RESETVALUE 0x00000000UL /**< Default value for RAC_STIMERCOMP */ +#define _RAC_STIMERCOMP_MASK 0x0000FFFFUL /**< Mask for RAC_STIMERCOMP */ +#define _RAC_STIMERCOMP_STIMERCOMP_SHIFT 0 /**< Shift value for RAC_STIMERCOMP */ +#define _RAC_STIMERCOMP_STIMERCOMP_MASK 0xFFFFUL /**< Bit mask for RAC_STIMERCOMP */ +#define _RAC_STIMERCOMP_STIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STIMERCOMP */ +#define RAC_STIMERCOMP_STIMERCOMP_DEFAULT (_RAC_STIMERCOMP_STIMERCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STIMERCOMP */ + +/* Bit fields for RAC SEQCTRL */ +#define _RAC_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_MASK 0x0300007FUL /**< Mask for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPACT (0x1UL << 0) /**< STIMER Compare Action */ +#define _RAC_SEQCTRL_COMPACT_SHIFT 0 /**< Shift value for RAC_COMPACT */ +#define _RAC_SEQCTRL_COMPACT_MASK 0x1UL /**< Bit mask for RAC_COMPACT */ +#define _RAC_SEQCTRL_COMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPACT_WRAP 0x00000000UL /**< Mode WRAP for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPACT_CONTINUE 0x00000001UL /**< Mode CONTINUE for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPACT_DEFAULT (_RAC_SEQCTRL_COMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPACT_WRAP (_RAC_SEQCTRL_COMPACT_WRAP << 0) /**< Shifted mode WRAP for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPACT_CONTINUE (_RAC_SEQCTRL_COMPACT_CONTINUE << 0) /**< Shifted mode CONTINUE for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPINVALMODE_SHIFT 1 /**< Shift value for RAC_COMPINVALMODE */ +#define _RAC_SEQCTRL_COMPINVALMODE_MASK 0x6UL /**< Bit mask for RAC_COMPINVALMODE */ +#define _RAC_SEQCTRL_COMPINVALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPINVALMODE_NEVER 0x00000000UL /**< Mode NEVER for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPINVALMODE_STATECHANGE 0x00000001UL /**< Mode STATECHANGE for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPINVALMODE_COMPEVENT 0x00000002UL /**< Mode COMPEVENT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_COMPINVALMODE_STATECOMP 0x00000003UL /**< Mode STATECOMP for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPINVALMODE_DEFAULT (_RAC_SEQCTRL_COMPINVALMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPINVALMODE_NEVER (_RAC_SEQCTRL_COMPINVALMODE_NEVER << 1) /**< Shifted mode NEVER for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPINVALMODE_STATECHANGE (_RAC_SEQCTRL_COMPINVALMODE_STATECHANGE << 1) /**< Shifted mode STATECHANGE for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPINVALMODE_COMPEVENT (_RAC_SEQCTRL_COMPINVALMODE_COMPEVENT << 1) /**< Shifted mode COMPEVENT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_COMPINVALMODE_STATECOMP (_RAC_SEQCTRL_COMPINVALMODE_STATECOMP << 1) /**< Shifted mode STATECOMP for RAC_SEQCTRL */ +#define RAC_SEQCTRL_RELATIVE (0x1UL << 3) /**< STIMER Compare value relative */ +#define _RAC_SEQCTRL_RELATIVE_SHIFT 3 /**< Shift value for RAC_RELATIVE */ +#define _RAC_SEQCTRL_RELATIVE_MASK 0x8UL /**< Bit mask for RAC_RELATIVE */ +#define _RAC_SEQCTRL_RELATIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_RELATIVE_Absolute 0x00000000UL /**< Mode Absolute for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_RELATIVE_Relative 0x00000001UL /**< Mode Relative for RAC_SEQCTRL */ +#define RAC_SEQCTRL_RELATIVE_DEFAULT (_RAC_SEQCTRL_RELATIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_RELATIVE_Absolute (_RAC_SEQCTRL_RELATIVE_Absolute << 3) /**< Shifted mode Absolute for RAC_SEQCTRL */ +#define RAC_SEQCTRL_RELATIVE_Relative (_RAC_SEQCTRL_RELATIVE_Relative << 3) /**< Shifted mode Relative for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERALWAYSRUN (0x1UL << 4) /**< STIMER always Run */ +#define _RAC_SEQCTRL_STIMERALWAYSRUN_SHIFT 4 /**< Shift value for RAC_STIMERALWAYSRUN */ +#define _RAC_SEQCTRL_STIMERALWAYSRUN_MASK 0x10UL /**< Bit mask for RAC_STIMERALWAYSRUN */ +#define _RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT (_RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERDEBUGRUN (0x1UL << 5) /**< STIMER Debug Run */ +#define _RAC_SEQCTRL_STIMERDEBUGRUN_SHIFT 5 /**< Shift value for RAC_STIMERDEBUGRUN */ +#define _RAC_SEQCTRL_STIMERDEBUGRUN_MASK 0x20UL /**< Bit mask for RAC_STIMERDEBUGRUN */ +#define _RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_STIMERDEBUGRUN_X0 0x00000000UL /**< Mode X0 for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_STIMERDEBUGRUN_X1 0x00000001UL /**< Mode X1 for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT (_RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERDEBUGRUN_X0 (_RAC_SEQCTRL_STIMERDEBUGRUN_X0 << 5) /**< Shifted mode X0 for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STIMERDEBUGRUN_X1 (_RAC_SEQCTRL_STIMERDEBUGRUN_X1 << 5) /**< Shifted mode X1 for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STATEDEBUGRUN (0x1UL << 6) /**< FSM state Debug Run */ +#define _RAC_SEQCTRL_STATEDEBUGRUN_SHIFT 6 /**< Shift value for RAC_STATEDEBUGRUN */ +#define _RAC_SEQCTRL_STATEDEBUGRUN_MASK 0x40UL /**< Bit mask for RAC_STATEDEBUGRUN */ +#define _RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_STATEDEBUGRUN_X0 0x00000000UL /**< Mode X0 for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_STATEDEBUGRUN_X1 0x00000001UL /**< Mode X1 for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT (_RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STATEDEBUGRUN_X0 (_RAC_SEQCTRL_STATEDEBUGRUN_X0 << 6) /**< Shifted mode X0 for RAC_SEQCTRL */ +#define RAC_SEQCTRL_STATEDEBUGRUN_X1 (_RAC_SEQCTRL_STATEDEBUGRUN_X1 << 6) /**< Shifted mode X1 for RAC_SEQCTRL */ +#define _RAC_SEQCTRL_SWIRQ_SHIFT 24 /**< Shift value for RAC_SWIRQ */ +#define _RAC_SEQCTRL_SWIRQ_MASK 0x3000000UL /**< Bit mask for RAC_SWIRQ */ +#define _RAC_SEQCTRL_SWIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */ +#define RAC_SEQCTRL_SWIRQ_DEFAULT (_RAC_SEQCTRL_SWIRQ_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQCTRL */ + +/* Bit fields for RAC PRESC */ +#define _RAC_PRESC_RESETVALUE 0x00000007UL /**< Default value for RAC_PRESC */ +#define _RAC_PRESC_MASK 0x0000007FUL /**< Mask for RAC_PRESC */ +#define _RAC_PRESC_STIMER_SHIFT 0 /**< Shift value for RAC_STIMER */ +#define _RAC_PRESC_STIMER_MASK 0x7FUL /**< Bit mask for RAC_STIMER */ +#define _RAC_PRESC_STIMER_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PRESC */ +#define RAC_PRESC_STIMER_DEFAULT (_RAC_PRESC_STIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PRESC */ + +/* Bit fields for RAC SR0 */ +#define _RAC_SR0_RESETVALUE 0x00000000UL /**< Default value for RAC_SR0 */ +#define _RAC_SR0_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR0 */ +#define _RAC_SR0_SR0_SHIFT 0 /**< Shift value for RAC_SR0 */ +#define _RAC_SR0_SR0_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR0 */ +#define _RAC_SR0_SR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR0 */ +#define RAC_SR0_SR0_DEFAULT (_RAC_SR0_SR0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR0 */ + +/* Bit fields for RAC SR1 */ +#define _RAC_SR1_RESETVALUE 0x00000000UL /**< Default value for RAC_SR1 */ +#define _RAC_SR1_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR1 */ +#define _RAC_SR1_SR1_SHIFT 0 /**< Shift value for RAC_SR1 */ +#define _RAC_SR1_SR1_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR1 */ +#define _RAC_SR1_SR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR1 */ +#define RAC_SR1_SR1_DEFAULT (_RAC_SR1_SR1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR1 */ + +/* Bit fields for RAC SR2 */ +#define _RAC_SR2_RESETVALUE 0x00000000UL /**< Default value for RAC_SR2 */ +#define _RAC_SR2_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR2 */ +#define _RAC_SR2_SR2_SHIFT 0 /**< Shift value for RAC_SR2 */ +#define _RAC_SR2_SR2_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR2 */ +#define _RAC_SR2_SR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR2 */ +#define RAC_SR2_SR2_DEFAULT (_RAC_SR2_SR2_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR2 */ + +/* Bit fields for RAC SR3 */ +#define _RAC_SR3_RESETVALUE 0x00000000UL /**< Default value for RAC_SR3 */ +#define _RAC_SR3_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR3 */ +#define _RAC_SR3_SR3_SHIFT 0 /**< Shift value for RAC_SR3 */ +#define _RAC_SR3_SR3_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR3 */ +#define _RAC_SR3_SR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR3 */ +#define RAC_SR3_SR3_DEFAULT (_RAC_SR3_SR3_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR3 */ + +/* Bit fields for RAC STCTRL */ +#define _RAC_STCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_STCTRL */ +#define _RAC_STCTRL_MASK 0x01FFFFFFUL /**< Mask for RAC_STCTRL */ +#define _RAC_STCTRL_STCAL_SHIFT 0 /**< Shift value for RAC_STCAL */ +#define _RAC_STCTRL_STCAL_MASK 0xFFFFFFUL /**< Bit mask for RAC_STCAL */ +#define _RAC_STCTRL_STCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STCTRL */ +#define RAC_STCTRL_STCAL_DEFAULT (_RAC_STCTRL_STCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STCTRL */ +#define RAC_STCTRL_STSKEW (0x1UL << 24) /**< Systick timer skew */ +#define _RAC_STCTRL_STSKEW_SHIFT 24 /**< Shift value for RAC_STSKEW */ +#define _RAC_STCTRL_STSKEW_MASK 0x1000000UL /**< Bit mask for RAC_STSKEW */ +#define _RAC_STCTRL_STSKEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STCTRL */ +#define RAC_STCTRL_STSKEW_DEFAULT (_RAC_STCTRL_STSKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_STCTRL */ + +/* Bit fields for RAC FRCTXWORD */ +#define _RAC_FRCTXWORD_RESETVALUE 0x00000000UL /**< Default value for RAC_FRCTXWORD */ +#define _RAC_FRCTXWORD_MASK 0x000000FFUL /**< Mask for RAC_FRCTXWORD */ +#define _RAC_FRCTXWORD_WDATA_SHIFT 0 /**< Shift value for RAC_WDATA */ +#define _RAC_FRCTXWORD_WDATA_MASK 0xFFUL /**< Bit mask for RAC_WDATA */ +#define _RAC_FRCTXWORD_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FRCTXWORD */ +#define RAC_FRCTXWORD_WDATA_DEFAULT (_RAC_FRCTXWORD_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FRCTXWORD */ + +/* Bit fields for RAC FRCRXWORD */ +#define _RAC_FRCRXWORD_RESETVALUE 0x00000000UL /**< Default value for RAC_FRCRXWORD */ +#define _RAC_FRCRXWORD_MASK 0x000000FFUL /**< Mask for RAC_FRCRXWORD */ +#define _RAC_FRCRXWORD_RDATA_SHIFT 0 /**< Shift value for RAC_RDATA */ +#define _RAC_FRCRXWORD_RDATA_MASK 0xFFUL /**< Bit mask for RAC_RDATA */ +#define _RAC_FRCRXWORD_RDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FRCRXWORD */ +#define RAC_FRCRXWORD_RDATA_DEFAULT (_RAC_FRCRXWORD_RDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FRCRXWORD */ + +/* Bit fields for RAC EM1PCSR */ +#define _RAC_EM1PCSR_RESETVALUE 0x00000000UL /**< Default value for RAC_EM1PCSR */ +#define _RAC_EM1PCSR_MASK 0x00070033UL /**< Mask for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PMODE (0x1UL << 0) /**< */ +#define _RAC_EM1PCSR_RADIOEM1PMODE_SHIFT 0 /**< Shift value for RAC_RADIOEM1PMODE */ +#define _RAC_EM1PCSR_RADIOEM1PMODE_MASK 0x1UL /**< Bit mask for RAC_RADIOEM1PMODE */ +#define _RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define _RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL 0x00000000UL /**< Mode HWCTRL for RAC_EM1PCSR */ +#define _RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL 0x00000001UL /**< Mode SWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT (_RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL (_RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL << 0) /**< Shifted mode HWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL (_RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL << 0) /**< Shifted mode SWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PDISSWREQ (0x1UL << 1) /**< */ +#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_SHIFT 1 /**< Shift value for RAC_RADIOEM1PDISSWREQ */ +#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_MASK 0x2UL /**< Bit mask for RAC_RADIOEM1PDISSWREQ */ +#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PMODE (0x1UL << 4) /**< */ +#define _RAC_EM1PCSR_MCUEM1PMODE_SHIFT 4 /**< Shift value for RAC_MCUEM1PMODE */ +#define _RAC_EM1PCSR_MCUEM1PMODE_MASK 0x10UL /**< Bit mask for RAC_MCUEM1PMODE */ +#define _RAC_EM1PCSR_MCUEM1PMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define _RAC_EM1PCSR_MCUEM1PMODE_HWCTRL 0x00000000UL /**< Mode HWCTRL for RAC_EM1PCSR */ +#define _RAC_EM1PCSR_MCUEM1PMODE_SWCTRL 0x00000001UL /**< Mode SWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PMODE_DEFAULT (_RAC_EM1PCSR_MCUEM1PMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PMODE_HWCTRL (_RAC_EM1PCSR_MCUEM1PMODE_HWCTRL << 4) /**< Shifted mode HWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PMODE_SWCTRL (_RAC_EM1PCSR_MCUEM1PMODE_SWCTRL << 4) /**< Shifted mode SWCTRL for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PDISSWREQ (0x1UL << 5) /**< */ +#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_SHIFT 5 /**< Shift value for RAC_MCUEM1PDISSWREQ */ +#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_MASK 0x20UL /**< Bit mask for RAC_MCUEM1PDISSWREQ */ +#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT (_RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PREQ (0x1UL << 16) /**< */ +#define _RAC_EM1PCSR_RADIOEM1PREQ_SHIFT 16 /**< Shift value for RAC_RADIOEM1PREQ */ +#define _RAC_EM1PCSR_RADIOEM1PREQ_MASK 0x10000UL /**< Bit mask for RAC_RADIOEM1PREQ */ +#define _RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PACK (0x1UL << 17) /**< */ +#define _RAC_EM1PCSR_RADIOEM1PACK_SHIFT 17 /**< Shift value for RAC_RADIOEM1PACK */ +#define _RAC_EM1PCSR_RADIOEM1PACK_MASK 0x20000UL /**< Bit mask for RAC_RADIOEM1PACK */ +#define _RAC_EM1PCSR_RADIOEM1PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PACK_DEFAULT (_RAC_EM1PCSR_RADIOEM1PACK_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PHWREQ (0x1UL << 18) /**< */ +#define _RAC_EM1PCSR_RADIOEM1PHWREQ_SHIFT 18 /**< Shift value for RAC_RADIOEM1PHWREQ */ +#define _RAC_EM1PCSR_RADIOEM1PHWREQ_MASK 0x40000UL /**< Bit mask for RAC_RADIOEM1PHWREQ */ +#define _RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */ +#define RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_EM1PCSR */ + +/* Bit fields for RAC SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_MASK 0x00100682UL /**< Mask for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCOSTARTUP (0x1UL << 1) /**< SYVCOFASTSTARTUP */ +#define _RAC_SYNTHENCTRL_VCOSTARTUP_SHIFT 1 /**< Shift value for RAC_VCOSTARTUP */ +#define _RAC_SYNTHENCTRL_VCOSTARTUP_MASK 0x2UL /**< Bit mask for RAC_VCOSTARTUP */ +#define _RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 0x00000000UL /**< Mode fast_start_up_0 for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 0x00000001UL /**< Mode fast_start_up_1 for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT (_RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 (_RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 << 1) /**< Shifted mode fast_start_up_0 for RAC_SYNTHENCTRL*/ +#define RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 (_RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 << 1) /**< Shifted mode fast_start_up_1 for RAC_SYNTHENCTRL*/ +#define RAC_SYNTHENCTRL_VCBUFEN (0x1UL << 7) /**< SYLPFVCBUFEN */ +#define _RAC_SYNTHENCTRL_VCBUFEN_SHIFT 7 /**< Shift value for RAC_VCBUFEN */ +#define _RAC_SYNTHENCTRL_VCBUFEN_MASK 0x80UL /**< Bit mask for RAC_VCBUFEN */ +#define _RAC_SYNTHENCTRL_VCBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_VCBUFEN_Disabled 0x00000000UL /**< Mode Disabled for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_VCBUFEN_Enabled 0x00000001UL /**< Mode Enabled for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCBUFEN_DEFAULT (_RAC_SYNTHENCTRL_VCBUFEN_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCBUFEN_Disabled (_RAC_SYNTHENCTRL_VCBUFEN_Disabled << 7) /**< Shifted mode Disabled for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_VCBUFEN_Enabled (_RAC_SYNTHENCTRL_VCBUFEN_Enabled << 7) /**< Shifted mode Enabled for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE (0x1UL << 10) /**< SYMMDPOWERBALANCEENB */ +#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_SHIFT 10 /**< Shift value for RAC_MMDPOWERBALANCEDISABLE */ +#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_MASK 0x400UL /**< Bit mask for RAC_MMDPOWERBALANCEDISABLE */ +#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed 0x00000000UL /**< Mode EnablePowerbleed for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed 0x00000001UL /**< Mode DisablePowerBleed for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed << 10) /**< Shifted mode EnablePowerbleed for RAC_SYNTHENCTRL*/ +#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed << 10) /**< Shifted mode DisablePowerBleed for RAC_SYNTHENCTRL*/ +#define RAC_SYNTHENCTRL_LPFBWSEL (0x1UL << 20) /**< LPF bandwidth register selection */ +#define _RAC_SYNTHENCTRL_LPFBWSEL_SHIFT 20 /**< Shift value for RAC_LPFBWSEL */ +#define _RAC_SYNTHENCTRL_LPFBWSEL_MASK 0x100000UL /**< Bit mask for RAC_LPFBWSEL */ +#define _RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX 0x00000000UL /**< Mode LPFBWRX for RAC_SYNTHENCTRL */ +#define _RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX 0x00000001UL /**< Mode LPFBWTX for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT (_RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX (_RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX << 20) /**< Shifted mode LPFBWRX for RAC_SYNTHENCTRL */ +#define RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX (_RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX << 20) /**< Shifted mode LPFBWTX for RAC_SYNTHENCTRL */ + +/* Bit fields for RAC SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_RESETVALUE 0x04000000UL /**< Default value for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MASK 0x07001C00UL /**< Mask for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_SHIFT 10 /**< Shift value for RAC_MMDLDOVREFTRIM */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_MASK 0x1C00UL /**< Bit mask for RAC_MMDLDOVREFTRIM */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 0x00000000UL /**< Mode vref0p6000 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 0x00000001UL /**< Mode vref0p6125 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 0x00000002UL /**< Mode vref0p6250 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 0x00000003UL /**< Mode vref0p6375 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 0x00000004UL /**< Mode vref0p6500 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 0x00000005UL /**< Mode vref0p6625 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 0x00000006UL /**< Mode vref0p6750 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 0x00000007UL /**< Mode vref0p6875 for RAC_SYNTHREGCTRL */ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYNTHREGCTRL */ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 << 10) /**< Shifted mode vref0p6000 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 << 10) /**< Shifted mode vref0p6125 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 << 10) /**< Shifted mode vref0p6250 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 << 10) /**< Shifted mode vref0p6375 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 << 10) /**< Shifted mode vref0p6500 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 << 10) /**< Shifted mode vref0p6625 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 << 10) /**< Shifted mode vref0p6750 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 << 10) /**< Shifted mode vref0p6875 for RAC_SYNTHREGCTRL*/ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_SHIFT 24 /**< Shift value for RAC_CHPLDOVREFTRIM */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_MASK 0x7000000UL /**< Bit mask for RAC_CHPLDOVREFTRIM */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 0x00000000UL /**< Mode vref0p6000 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 0x00000001UL /**< Mode vref0p6125 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 0x00000002UL /**< Mode vref0p6250 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 0x00000003UL /**< Mode vref0p6375 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 0x00000004UL /**< Mode vref0p6500 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 0x00000005UL /**< Mode vref0p6625 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 0x00000006UL /**< Mode vref0p6750 for RAC_SYNTHREGCTRL */ +#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 0x00000007UL /**< Mode vref0p6875 for RAC_SYNTHREGCTRL */ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYNTHREGCTRL */ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 << 24) /**< Shifted mode vref0p6000 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 << 24) /**< Shifted mode vref0p6125 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 << 24) /**< Shifted mode vref0p6250 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 << 24) /**< Shifted mode vref0p6375 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 << 24) /**< Shifted mode vref0p6500 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 << 24) /**< Shifted mode vref0p6625 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 << 24) /**< Shifted mode vref0p6750 for RAC_SYNTHREGCTRL*/ +#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 << 24) /**< Shifted mode vref0p6875 for RAC_SYNTHREGCTRL*/ + +/* Bit fields for RAC VCOCTRL */ +#define _RAC_VCOCTRL_RESETVALUE 0x0000044CUL /**< Default value for RAC_VCOCTRL */ +#define _RAC_VCOCTRL_MASK 0x00000FFFUL /**< Mask for RAC_VCOCTRL */ +#define _RAC_VCOCTRL_VCOAMPLITUDE_SHIFT 0 /**< Shift value for RAC_VCOAMPLITUDE */ +#define _RAC_VCOCTRL_VCOAMPLITUDE_MASK 0xFUL /**< Bit mask for RAC_VCOAMPLITUDE */ +#define _RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT 0x0000000CUL /**< Mode DEFAULT for RAC_VCOCTRL */ +#define RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT (_RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_VCOCTRL */ +#define _RAC_VCOCTRL_VCODETAMPLITUDERX_SHIFT 4 /**< Shift value for RAC_VCODETAMPLITUDERX */ +#define _RAC_VCOCTRL_VCODETAMPLITUDERX_MASK 0xF0UL /**< Bit mask for RAC_VCODETAMPLITUDERX */ +#define _RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_VCOCTRL */ +#define RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT (_RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_VCOCTRL */ +#define _RAC_VCOCTRL_VCODETAMPLITUDETX_SHIFT 8 /**< Shift value for RAC_VCODETAMPLITUDETX */ +#define _RAC_VCOCTRL_VCODETAMPLITUDETX_MASK 0xF00UL /**< Bit mask for RAC_VCODETAMPLITUDETX */ +#define _RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_VCOCTRL */ +#define RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT (_RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_VCOCTRL */ + +/* Bit fields for RAC STATUS2 */ +#define _RAC_STATUS2_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS2 */ +#define _RAC_STATUS2_MASK 0x0000FFFFUL /**< Mask for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_SHIFT 0 /**< Shift value for RAC_PREVSTATE1 */ +#define _RAC_STATUS2_PREVSTATE1_MASK 0xFUL /**< Bit mask for RAC_PREVSTATE1 */ +#define _RAC_STATUS2_PREVSTATE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE1_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_DEFAULT (_RAC_STATUS2_PREVSTATE1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_OFF (_RAC_STATUS2_PREVSTATE1_OFF << 0) /**< Shifted mode OFF for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RXWARM (_RAC_STATUS2_PREVSTATE1_RXWARM << 0) /**< Shifted mode RXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RXSEARCH (_RAC_STATUS2_PREVSTATE1_RXSEARCH << 0) /**< Shifted mode RXSEARCH for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RXFRAME (_RAC_STATUS2_PREVSTATE1_RXFRAME << 0) /**< Shifted mode RXFRAME for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RXPD (_RAC_STATUS2_PREVSTATE1_RXPD << 0) /**< Shifted mode RXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RX2RX (_RAC_STATUS2_PREVSTATE1_RX2RX << 0) /**< Shifted mode RX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RXOVERFLOW (_RAC_STATUS2_PREVSTATE1_RXOVERFLOW << 0) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_RX2TX (_RAC_STATUS2_PREVSTATE1_RX2TX << 0) /**< Shifted mode RX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_TXWARM (_RAC_STATUS2_PREVSTATE1_TXWARM << 0) /**< Shifted mode TXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_TX (_RAC_STATUS2_PREVSTATE1_TX << 0) /**< Shifted mode TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_TXPD (_RAC_STATUS2_PREVSTATE1_TXPD << 0) /**< Shifted mode TXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_TX2RX (_RAC_STATUS2_PREVSTATE1_TX2RX << 0) /**< Shifted mode TX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_TX2TX (_RAC_STATUS2_PREVSTATE1_TX2TX << 0) /**< Shifted mode TX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_SHUTDOWN (_RAC_STATUS2_PREVSTATE1_SHUTDOWN << 0) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE1_POR (_RAC_STATUS2_PREVSTATE1_POR << 0) /**< Shifted mode POR for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_SHIFT 4 /**< Shift value for RAC_PREVSTATE2 */ +#define _RAC_STATUS2_PREVSTATE2_MASK 0xF0UL /**< Bit mask for RAC_PREVSTATE2 */ +#define _RAC_STATUS2_PREVSTATE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE2_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_DEFAULT (_RAC_STATUS2_PREVSTATE2_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_OFF (_RAC_STATUS2_PREVSTATE2_OFF << 4) /**< Shifted mode OFF for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RXWARM (_RAC_STATUS2_PREVSTATE2_RXWARM << 4) /**< Shifted mode RXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RXSEARCH (_RAC_STATUS2_PREVSTATE2_RXSEARCH << 4) /**< Shifted mode RXSEARCH for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RXFRAME (_RAC_STATUS2_PREVSTATE2_RXFRAME << 4) /**< Shifted mode RXFRAME for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RXPD (_RAC_STATUS2_PREVSTATE2_RXPD << 4) /**< Shifted mode RXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RX2RX (_RAC_STATUS2_PREVSTATE2_RX2RX << 4) /**< Shifted mode RX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RXOVERFLOW (_RAC_STATUS2_PREVSTATE2_RXOVERFLOW << 4) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_RX2TX (_RAC_STATUS2_PREVSTATE2_RX2TX << 4) /**< Shifted mode RX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_TXWARM (_RAC_STATUS2_PREVSTATE2_TXWARM << 4) /**< Shifted mode TXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_TX (_RAC_STATUS2_PREVSTATE2_TX << 4) /**< Shifted mode TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_TXPD (_RAC_STATUS2_PREVSTATE2_TXPD << 4) /**< Shifted mode TXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_TX2RX (_RAC_STATUS2_PREVSTATE2_TX2RX << 4) /**< Shifted mode TX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_TX2TX (_RAC_STATUS2_PREVSTATE2_TX2TX << 4) /**< Shifted mode TX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_SHUTDOWN (_RAC_STATUS2_PREVSTATE2_SHUTDOWN << 4) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE2_POR (_RAC_STATUS2_PREVSTATE2_POR << 4) /**< Shifted mode POR for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_SHIFT 8 /**< Shift value for RAC_PREVSTATE3 */ +#define _RAC_STATUS2_PREVSTATE3_MASK 0xF00UL /**< Bit mask for RAC_PREVSTATE3 */ +#define _RAC_STATUS2_PREVSTATE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */ +#define _RAC_STATUS2_PREVSTATE3_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_DEFAULT (_RAC_STATUS2_PREVSTATE3_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_OFF (_RAC_STATUS2_PREVSTATE3_OFF << 8) /**< Shifted mode OFF for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RXWARM (_RAC_STATUS2_PREVSTATE3_RXWARM << 8) /**< Shifted mode RXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RXSEARCH (_RAC_STATUS2_PREVSTATE3_RXSEARCH << 8) /**< Shifted mode RXSEARCH for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RXFRAME (_RAC_STATUS2_PREVSTATE3_RXFRAME << 8) /**< Shifted mode RXFRAME for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RXPD (_RAC_STATUS2_PREVSTATE3_RXPD << 8) /**< Shifted mode RXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RX2RX (_RAC_STATUS2_PREVSTATE3_RX2RX << 8) /**< Shifted mode RX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RXOVERFLOW (_RAC_STATUS2_PREVSTATE3_RXOVERFLOW << 8) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_RX2TX (_RAC_STATUS2_PREVSTATE3_RX2TX << 8) /**< Shifted mode RX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_TXWARM (_RAC_STATUS2_PREVSTATE3_TXWARM << 8) /**< Shifted mode TXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_TX (_RAC_STATUS2_PREVSTATE3_TX << 8) /**< Shifted mode TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_TXPD (_RAC_STATUS2_PREVSTATE3_TXPD << 8) /**< Shifted mode TXPD for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_TX2RX (_RAC_STATUS2_PREVSTATE3_TX2RX << 8) /**< Shifted mode TX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_TX2TX (_RAC_STATUS2_PREVSTATE3_TX2TX << 8) /**< Shifted mode TX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_SHUTDOWN (_RAC_STATUS2_PREVSTATE3_SHUTDOWN << 8) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */ +#define RAC_STATUS2_PREVSTATE3_POR (_RAC_STATUS2_PREVSTATE3_POR << 8) /**< Shifted mode POR for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_SHIFT 12 /**< Shift value for RAC_CURRSTATE */ +#define _RAC_STATUS2_CURRSTATE_MASK 0xF000UL /**< Bit mask for RAC_CURRSTATE */ +#define _RAC_STATUS2_CURRSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */ +#define _RAC_STATUS2_CURRSTATE_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_DEFAULT (_RAC_STATUS2_CURRSTATE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_OFF (_RAC_STATUS2_CURRSTATE_OFF << 12) /**< Shifted mode OFF for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RXWARM (_RAC_STATUS2_CURRSTATE_RXWARM << 12) /**< Shifted mode RXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RXSEARCH (_RAC_STATUS2_CURRSTATE_RXSEARCH << 12) /**< Shifted mode RXSEARCH for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RXFRAME (_RAC_STATUS2_CURRSTATE_RXFRAME << 12) /**< Shifted mode RXFRAME for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RXPD (_RAC_STATUS2_CURRSTATE_RXPD << 12) /**< Shifted mode RXPD for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RX2RX (_RAC_STATUS2_CURRSTATE_RX2RX << 12) /**< Shifted mode RX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RXOVERFLOW (_RAC_STATUS2_CURRSTATE_RXOVERFLOW << 12) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_RX2TX (_RAC_STATUS2_CURRSTATE_RX2TX << 12) /**< Shifted mode RX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_TXWARM (_RAC_STATUS2_CURRSTATE_TXWARM << 12) /**< Shifted mode TXWARM for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_TX (_RAC_STATUS2_CURRSTATE_TX << 12) /**< Shifted mode TX for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_TXPD (_RAC_STATUS2_CURRSTATE_TXPD << 12) /**< Shifted mode TXPD for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_TX2RX (_RAC_STATUS2_CURRSTATE_TX2RX << 12) /**< Shifted mode TX2RX for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_TX2TX (_RAC_STATUS2_CURRSTATE_TX2TX << 12) /**< Shifted mode TX2TX for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_SHUTDOWN (_RAC_STATUS2_CURRSTATE_SHUTDOWN << 12) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */ +#define RAC_STATUS2_CURRSTATE_POR (_RAC_STATUS2_CURRSTATE_POR << 12) /**< Shifted mode POR for RAC_STATUS2 */ + +/* Bit fields for RAC IFPGACTRL */ +#define _RAC_IFPGACTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_MASK 0x0FF80000UL /**< Mask for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALON (0x1UL << 19) /**< Enable/Disable DCCAL in DEMOD */ +#define _RAC_IFPGACTRL_DCCALON_SHIFT 19 /**< Shift value for RAC_DCCALON */ +#define _RAC_IFPGACTRL_DCCALON_MASK 0x80000UL /**< Bit mask for RAC_DCCALON */ +#define _RAC_IFPGACTRL_DCCALON_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALON_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALON_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALON_DEFAULT (_RAC_IFPGACTRL_DCCALON_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALON_DISABLE (_RAC_IFPGACTRL_DCCALON_DISABLE << 19) /**< Shifted mode DISABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALON_ENABLE (_RAC_IFPGACTRL_DCCALON_ENABLE << 19) /**< Shifted mode ENABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCRSTEN (0x1UL << 20) /**< DC Compensation Filter Reset Enable */ +#define _RAC_IFPGACTRL_DCRSTEN_SHIFT 20 /**< Shift value for RAC_DCRSTEN */ +#define _RAC_IFPGACTRL_DCRSTEN_MASK 0x100000UL /**< Bit mask for RAC_DCRSTEN */ +#define _RAC_IFPGACTRL_DCRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCRSTEN_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCRSTEN_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCRSTEN_DEFAULT (_RAC_IFPGACTRL_DCRSTEN_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCRSTEN_DISABLE (_RAC_IFPGACTRL_DCRSTEN_DISABLE << 20) /**< Shifted mode DISABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCRSTEN_ENABLE (_RAC_IFPGACTRL_DCRSTEN_ENABLE << 20) /**< Shifted mode ENABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCESTIEN (0x1UL << 21) /**< DCESTIEN Override for RAC */ +#define _RAC_IFPGACTRL_DCESTIEN_SHIFT 21 /**< Shift value for RAC_DCESTIEN */ +#define _RAC_IFPGACTRL_DCESTIEN_MASK 0x200000UL /**< Bit mask for RAC_DCESTIEN */ +#define _RAC_IFPGACTRL_DCESTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCESTIEN_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCESTIEN_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCESTIEN_DEFAULT (_RAC_IFPGACTRL_DCESTIEN_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCESTIEN_DISABLE (_RAC_IFPGACTRL_DCESTIEN_DISABLE << 21) /**< Shifted mode DISABLE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCESTIEN_ENABLE (_RAC_IFPGACTRL_DCESTIEN_ENABLE << 21) /**< Shifted mode ENABLE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_SHIFT 22 /**< Shift value for RAC_DCCALDEC0 */ +#define _RAC_IFPGACTRL_DCCALDEC0_MASK 0x1C00000UL /**< Bit mask for RAC_DCCALDEC0 */ +#define _RAC_IFPGACTRL_DCCALDEC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_DF3 0x00000000UL /**< Mode DF3 for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_DF4WIDE 0x00000001UL /**< Mode DF4WIDE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_DF4NARROW 0x00000002UL /**< Mode DF4NARROW for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_DF8WIDE 0x00000003UL /**< Mode DF8WIDE for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDEC0_DF8NARROW 0x00000004UL /**< Mode DF8NARROW for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DEFAULT (_RAC_IFPGACTRL_DCCALDEC0_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DF3 (_RAC_IFPGACTRL_DCCALDEC0_DF3 << 22) /**< Shifted mode DF3 for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DF4WIDE (_RAC_IFPGACTRL_DCCALDEC0_DF4WIDE << 22) /**< Shifted mode DF4WIDE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DF4NARROW (_RAC_IFPGACTRL_DCCALDEC0_DF4NARROW << 22) /**< Shifted mode DF4NARROW for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DF8WIDE (_RAC_IFPGACTRL_DCCALDEC0_DF8WIDE << 22) /**< Shifted mode DF8WIDE for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDEC0_DF8NARROW (_RAC_IFPGACTRL_DCCALDEC0_DF8NARROW << 22) /**< Shifted mode DF8NARROW for RAC_IFPGACTRL */ +#define _RAC_IFPGACTRL_DCCALDCGEAR_SHIFT 25 /**< Shift value for RAC_DCCALDCGEAR */ +#define _RAC_IFPGACTRL_DCCALDCGEAR_MASK 0xE000000UL /**< Bit mask for RAC_DCCALDCGEAR */ +#define _RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */ +#define RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT (_RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */ + +/* Bit fields for RAC PAENCTRL */ +#define _RAC_PAENCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_PAENCTRL */ +#define _RAC_PAENCTRL_MASK 0x00070100UL /**< Mask for RAC_PAENCTRL */ +#define RAC_PAENCTRL_PARAMP (0x1UL << 8) /**< PA output level ramping */ +#define _RAC_PAENCTRL_PARAMP_SHIFT 8 /**< Shift value for RAC_PARAMP */ +#define _RAC_PAENCTRL_PARAMP_MASK 0x100UL /**< Bit mask for RAC_PARAMP */ +#define _RAC_PAENCTRL_PARAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_PARAMP_DEFAULT (_RAC_PAENCTRL_PARAMP_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_INVRAMPCLK (0x1UL << 16) /**< Invert PA ramping clock */ +#define _RAC_PAENCTRL_INVRAMPCLK_SHIFT 16 /**< Shift value for RAC_INVRAMPCLK */ +#define _RAC_PAENCTRL_INVRAMPCLK_MASK 0x10000UL /**< Bit mask for RAC_INVRAMPCLK */ +#define _RAC_PAENCTRL_INVRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_INVRAMPCLK_DEFAULT (_RAC_PAENCTRL_INVRAMPCLK_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_DIV2RAMPCLK (0x1UL << 17) /**< Div PA ramping clock by 2 */ +#define _RAC_PAENCTRL_DIV2RAMPCLK_SHIFT 17 /**< Shift value for RAC_DIV2RAMPCLK */ +#define _RAC_PAENCTRL_DIV2RAMPCLK_MASK 0x20000UL /**< Bit mask for RAC_DIV2RAMPCLK */ +#define _RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT (_RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_RSTDIV2RAMPCLK (0x1UL << 18) /**< Reset Div2 PA ramping clock */ +#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_SHIFT 18 /**< Shift value for RAC_RSTDIV2RAMPCLK */ +#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_MASK 0x40000UL /**< Bit mask for RAC_RSTDIV2RAMPCLK */ +#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */ +#define RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT (_RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_PAENCTRL */ + +/* Bit fields for RAC APC */ +#define _RAC_APC_RESETVALUE 0xFF000000UL /**< Default value for RAC_APC */ +#define _RAC_APC_MASK 0xFF000004UL /**< Mask for RAC_APC */ +#define RAC_APC_ENAPCSW (0x1UL << 2) /**< software control bit for apc */ +#define _RAC_APC_ENAPCSW_SHIFT 2 /**< Shift value for RAC_ENAPCSW */ +#define _RAC_APC_ENAPCSW_MASK 0x4UL /**< Bit mask for RAC_ENAPCSW */ +#define _RAC_APC_ENAPCSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_APC */ +#define _RAC_APC_ENAPCSW_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_APC */ +#define _RAC_APC_ENAPCSW_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_APC */ +#define RAC_APC_ENAPCSW_DEFAULT (_RAC_APC_ENAPCSW_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_APC */ +#define RAC_APC_ENAPCSW_DISABLE (_RAC_APC_ENAPCSW_DISABLE << 2) /**< Shifted mode DISABLE for RAC_APC */ +#define RAC_APC_ENAPCSW_ENABLE (_RAC_APC_ENAPCSW_ENABLE << 2) /**< Shifted mode ENABLE for RAC_APC */ +#define _RAC_APC_AMPCONTROLLIMITSW_SHIFT 24 /**< Shift value for RAC_AMPCONTROLLIMITSW */ +#define _RAC_APC_AMPCONTROLLIMITSW_MASK 0xFF000000UL /**< Bit mask for RAC_AMPCONTROLLIMITSW */ +#define _RAC_APC_AMPCONTROLLIMITSW_DEFAULT 0x000000FFUL /**< Mode DEFAULT for RAC_APC */ +#define RAC_APC_AMPCONTROLLIMITSW_DEFAULT (_RAC_APC_AMPCONTROLLIMITSW_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_APC */ + +/* Bit fields for RAC ANTDIV */ +#define _RAC_ANTDIV_RESETVALUE 0x00000000UL /**< Default value for RAC_ANTDIV */ +#define _RAC_ANTDIV_MASK 0x00000FBDUL /**< Mask for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXEN0 (0x1UL << 0) /**< INTDIVLNAMIXEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN0_SHIFT 0 /**< Shift value for RAC_INTDIVLNAMIXEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN0_MASK 0x1UL /**< Bit mask for RAC_INTDIVLNAMIXEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0 (0x1UL << 2) /**< INTDIVLNAMIXRFATTDCEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_SHIFT 2 /**< Shift value for RAC_INTDIVLNAMIXRFATTDCEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_MASK 0x4UL /**< Bit mask for RAC_INTDIVLNAMIXRFATTDCEN0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0 (0x1UL << 3) /**< INTDIVLNAMIXRFPKDENRF0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_SHIFT 3 /**< Shift value for RAC_INTDIVLNAMIXRFPKDENRF0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_MASK 0x8UL /**< Bit mask for RAC_INTDIVLNAMIXRFPKDENRF0 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN (0x1UL << 4) /**< INTDIVSYLODIVRLO02G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_SHIFT 4 /**< Shift value for RAC_INTDIVSYLODIVRLO02G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_MASK 0x10UL /**< Bit mask for RAC_INTDIVSYLODIVRLO02G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT (_RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXEN1 (0x1UL << 5) /**< INTDIVLNAMIXEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN1_SHIFT 5 /**< Shift value for RAC_INTDIVLNAMIXEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN1_MASK 0x20UL /**< Bit mask for RAC_INTDIVLNAMIXEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1 (0x1UL << 7) /**< INTDIVLNAMIXRFATTDCEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_SHIFT 7 /**< Shift value for RAC_INTDIVLNAMIXRFATTDCEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_MASK 0x80UL /**< Bit mask for RAC_INTDIVLNAMIXRFATTDCEN1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1 (0x1UL << 8) /**< INTDIVLNAMIXRFPKDENRF1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_SHIFT 8 /**< Shift value for RAC_INTDIVLNAMIXRFPKDENRF1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_MASK 0x100UL /**< Bit mask for RAC_INTDIVLNAMIXRFPKDENRF1 */ +#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN (0x1UL << 9) /**< INTDIVSYLODIVRLO12G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_SHIFT 9 /**< Shift value for RAC_INTDIVSYLODIVRLO12G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_MASK 0x200UL /**< Bit mask for RAC_INTDIVSYLODIVRLO12G4EN */ +#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT (_RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define _RAC_ANTDIV_ANTDIVSTATUS_SHIFT 10 /**< Shift value for RAC_ANTDIVSTATUS */ +#define _RAC_ANTDIV_ANTDIVSTATUS_MASK 0xC00UL /**< Bit mask for RAC_ANTDIVSTATUS */ +#define _RAC_ANTDIV_ANTDIVSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */ +#define _RAC_ANTDIV_ANTDIVSTATUS_OFF 0x00000000UL /**< Mode OFF for RAC_ANTDIV */ +#define _RAC_ANTDIV_ANTDIVSTATUS_ANT1 0x00000001UL /**< Mode ANT1 for RAC_ANTDIV */ +#define _RAC_ANTDIV_ANTDIVSTATUS_ANT2 0x00000002UL /**< Mode ANT2 for RAC_ANTDIV */ +#define _RAC_ANTDIV_ANTDIVSTATUS_BOTH 0x00000003UL /**< Mode BOTH for RAC_ANTDIV */ +#define RAC_ANTDIV_ANTDIVSTATUS_DEFAULT (_RAC_ANTDIV_ANTDIVSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_ANTDIV */ +#define RAC_ANTDIV_ANTDIVSTATUS_OFF (_RAC_ANTDIV_ANTDIVSTATUS_OFF << 10) /**< Shifted mode OFF for RAC_ANTDIV */ +#define RAC_ANTDIV_ANTDIVSTATUS_ANT1 (_RAC_ANTDIV_ANTDIVSTATUS_ANT1 << 10) /**< Shifted mode ANT1 for RAC_ANTDIV */ +#define RAC_ANTDIV_ANTDIVSTATUS_ANT2 (_RAC_ANTDIV_ANTDIVSTATUS_ANT2 << 10) /**< Shifted mode ANT2 for RAC_ANTDIV */ +#define RAC_ANTDIV_ANTDIVSTATUS_BOTH (_RAC_ANTDIV_ANTDIVSTATUS_BOTH << 10) /**< Shifted mode BOTH for RAC_ANTDIV */ + +/* Bit fields for RAC AUXADCTRIM */ +#define _RAC_AUXADCTRIM_RESETVALUE 0x06D55502UL /**< Default value for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_MASK 0x1FFFFFFFUL /**< Mask for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCCLKINVERT (0x1UL << 0) /**< AUXADCCLKINVERT */ +#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_SHIFT 0 /**< Shift value for RAC_AUXADCCLKINVERT */ +#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_MASK 0x1UL /**< Bit mask for RAC_AUXADCCLKINVERT */ +#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert 0x00000000UL /**< Mode Disable_Invert for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert 0x00000001UL /**< Mode Enable_Invert for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT (_RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert (_RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert << 0) /**< Shifted mode Disable_Invert for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert (_RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert << 0) /**< Shifted mode Enable_Invert for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_SHIFT 1 /**< Shift value for RAC_AUXADCLDOVREFTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_MASK 0x6UL /**< Bit mask for RAC_AUXADCLDOVREFTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 0x00000000UL /**< Mode TRIM1p27 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 0x00000001UL /**< Mode TRIM1p3 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 0x00000002UL /**< Mode TRIM1p35 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 0x00000003UL /**< Mode TRIM1p4 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 << 1) /**< Shifted mode TRIM1p27 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 << 1) /**< Shifted mode TRIM1p3 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 << 1) /**< Shifted mode TRIM1p35 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 << 1) /**< Shifted mode TRIM1p4 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT (0x1UL << 3) /**< AUXADCOUTPUTINVERT */ +#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_SHIFT 3 /**< Shift value for RAC_AUXADCOUTPUTINVERT */ +#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_MASK 0x8UL /**< Bit mask for RAC_AUXADCOUTPUTINVERT */ +#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled << 3) /**< Shifted mode Disabled for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled << 3) /**< Shifted mode Enabled for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCRCTUNE_SHIFT 4 /**< Shift value for RAC_AUXADCRCTUNE */ +#define _RAC_AUXADCTRIM_AUXADCRCTUNE_MASK 0x1F0UL /**< Bit mask for RAC_AUXADCRCTUNE */ +#define _RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT 0x00000010UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT (_RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_SHIFT 9 /**< Shift value for RAC_AUXADCTRIMADCINPUTRES */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_MASK 0x600UL /**< Bit mask for RAC_AUXADCTRIMADCINPUTRES */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k 0x00000000UL /**< Mode RES200k for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k 0x00000001UL /**< Mode RES250k for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k 0x00000002UL /**< Mode RES300k for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k 0x00000003UL /**< Mode RES350k for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k << 9) /**< Shifted mode RES200k for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k << 9) /**< Shifted mode RES250k for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k << 9) /**< Shifted mode RES300k for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k << 9) /**< Shifted mode RES350k for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_SHIFT 11 /**< Shift value for RAC_AUXADCTRIMCURRINPUTBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_MASK 0x1800UL /**< Bit mask for RAC_AUXADCTRIMCURRINPUTBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct << 11) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct << 11) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ << 11) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct << 11) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_SHIFT 13 /**< Shift value for RAC_AUXADCTRIMCURROPA1 */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_MASK 0x6000UL /**< Bit mask for RAC_AUXADCTRIMCURROPA1 */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct << 13) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct << 13) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ << 13) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct << 13) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_SHIFT 15 /**< Shift value for RAC_AUXADCTRIMCURROPA2 */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_MASK 0x18000UL /**< Bit mask for RAC_AUXADCTRIMCURROPA2 */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct << 15) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct << 15) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ << 15) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct << 15) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_SHIFT 17 /**< Shift value for RAC_AUXADCTRIMCURRREFBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_MASK 0x60000UL /**< Bit mask for RAC_AUXADCTRIMCURRREFBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct << 17) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct << 17) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ << 17) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct << 17) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_SHIFT 19 /**< Shift value for RAC_AUXADCTRIMCURRTSENSE */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_MASK 0x180000UL /**< Bit mask for RAC_AUXADCTRIMCURRTSENSE */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct << 19) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct << 19) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ << 19) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct << 19) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_SHIFT 21 /**< Shift value for RAC_AUXADCTRIMCURRVCMBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_MASK 0x600000UL /**< Bit mask for RAC_AUXADCTRIMCURRVCMBUF */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct << 21) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct << 21) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ << 21) /**< Shifted mode Typ for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct << 21) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT (0x1UL << 23) /**< AUXADCTRIMLDOHIGHCURRENT */ +#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_SHIFT 23 /**< Shift value for RAC_AUXADCTRIMLDOHIGHCURRENT*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_MASK 0x800000UL /**< Bit mask for RAC_AUXADCTRIMLDOHIGHCURRENT */ +#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode 0x00000000UL /**< Mode LowCurrentMode for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode 0x00000001UL /**< Mode HighCurrentMode for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode << 23) /**< Shifted mode LowCurrentMode for RAC_AUXADCTRIM*/ +#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode << 23) /**< Shifted mode HighCurrentMode for RAC_AUXADCTRIM*/ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_SHIFT 24 /**< Shift value for RAC_AUXADCTRIMREFP */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_MASK 0x3000000UL /**< Bit mask for RAC_AUXADCTRIMREFP */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 0x00000000UL /**< Mode REF1p05 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 0x00000001UL /**< Mode REF1p16 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 0x00000002UL /**< Mode REF1p2 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 0x00000003UL /**< Mode REF1p25 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 << 24) /**< Shifted mode REF1p05 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 << 24) /**< Shifted mode REF1p16 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 << 24) /**< Shifted mode REF1p2 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 << 24) /**< Shifted mode REF1p25 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_SHIFT 26 /**< Shift value for RAC_AUXADCTRIMVREFVCM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_MASK 0xC000000UL /**< Bit mask for RAC_AUXADCTRIMVREFVCM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 0x00000000UL /**< Mode Trim0p6 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 0x00000001UL /**< Mode Trim0p65 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 0x00000002UL /**< Mode Trim0p7 for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 0x00000003UL /**< Mode Trim0p75 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 << 26) /**< Shifted mode Trim0p6 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 << 26) /**< Shifted mode Trim0p65 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 << 26) /**< Shifted mode Trim0p7 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 << 26) /**< Shifted mode Trim0p75 for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2 (0x1UL << 28) /**< AUXADCTSENSETRIMVBE2 */ +#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_SHIFT 28 /**< Shift value for RAC_AUXADCTSENSETRIMVBE2 */ +#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_MASK 0x10000000UL /**< Bit mask for RAC_AUXADCTSENSETRIMVBE2 */ +#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA 0x00000000UL /**< Mode VBE_16uA for RAC_AUXADCTRIM */ +#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA 0x00000001UL /**< Mode VBE_32uA for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA << 28) /**< Shifted mode VBE_16uA for RAC_AUXADCTRIM */ +#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA << 28) /**< Shifted mode VBE_32uA for RAC_AUXADCTRIM */ + +/* Bit fields for RAC AUXADCEN */ +#define _RAC_AUXADCEN_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_MASK 0x000003FFUL /**< Mask for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENAUXADC (0x1UL << 0) /**< AUXADCENAUXADC */ +#define _RAC_AUXADCEN_AUXADCENAUXADC_SHIFT 0 /**< Shift value for RAC_AUXADCENAUXADC */ +#define _RAC_AUXADCEN_AUXADCENAUXADC_MASK 0x1UL /**< Bit mask for RAC_AUXADCENAUXADC */ +#define _RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENAUXADC_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENAUXADC_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT (_RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENAUXADC_Disabled (_RAC_AUXADCEN_AUXADCENAUXADC_Disabled << 0) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENAUXADC_Enabled (_RAC_AUXADCEN_AUXADCENAUXADC_Enabled << 0) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENINPUTBUFFER (0x1UL << 1) /**< AUXADCENINPUTBUFFER */ +#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_SHIFT 1 /**< Shift value for RAC_AUXADCENINPUTBUFFER */ +#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_MASK 0x2UL /**< Bit mask for RAC_AUXADCENINPUTBUFFER */ +#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled << 1) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled << 1) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENLDO (0x1UL << 2) /**< AUXADCENLDO */ +#define _RAC_AUXADCEN_AUXADCENLDO_SHIFT 2 /**< Shift value for RAC_AUXADCENLDO */ +#define _RAC_AUXADCEN_AUXADCENLDO_MASK 0x4UL /**< Bit mask for RAC_AUXADCENLDO */ +#define _RAC_AUXADCEN_AUXADCENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENLDO_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENLDO_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENLDO_DEFAULT (_RAC_AUXADCEN_AUXADCENLDO_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENLDO_Disabled (_RAC_AUXADCEN_AUXADCENLDO_Disabled << 2) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENLDO_Enabled (_RAC_AUXADCEN_AUXADCENLDO_Enabled << 2) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENOUTPUTDRV (0x1UL << 3) /**< AUXADCENOUTPUTDRV */ +#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_SHIFT 3 /**< Shift value for RAC_AUXADCENOUTPUTDRV */ +#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_MASK 0x8UL /**< Bit mask for RAC_AUXADCENOUTPUTDRV */ +#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled << 3) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled << 3) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENPMON (0x1UL << 4) /**< AUXADCENPMON */ +#define _RAC_AUXADCEN_AUXADCENPMON_SHIFT 4 /**< Shift value for RAC_AUXADCENPMON */ +#define _RAC_AUXADCEN_AUXADCENPMON_MASK 0x10UL /**< Bit mask for RAC_AUXADCENPMON */ +#define _RAC_AUXADCEN_AUXADCENPMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENPMON_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENPMON_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENPMON_DEFAULT (_RAC_AUXADCEN_AUXADCENPMON_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENPMON_Disabled (_RAC_AUXADCEN_AUXADCENPMON_Disabled << 4) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENPMON_Enabled (_RAC_AUXADCEN_AUXADCENPMON_Enabled << 4) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENRESONDIAGA (0x1UL << 5) /**< AUXADCENRESONDIAGA */ +#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_SHIFT 5 /**< Shift value for RAC_AUXADCENRESONDIAGA */ +#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_MASK 0x20UL /**< Bit mask for RAC_AUXADCENRESONDIAGA */ +#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT (_RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled (_RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled << 5) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled (_RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled << 5) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSE (0x1UL << 6) /**< AUXADCENTSENSE */ +#define _RAC_AUXADCEN_AUXADCENTSENSE_SHIFT 6 /**< Shift value for RAC_AUXADCENTSENSE */ +#define _RAC_AUXADCEN_AUXADCENTSENSE_MASK 0x40UL /**< Bit mask for RAC_AUXADCENTSENSE */ +#define _RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENTSENSE_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENTSENSE_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT (_RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSE_Disabled (_RAC_AUXADCEN_AUXADCENTSENSE_Disabled << 6) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSE_Enabled (_RAC_AUXADCEN_AUXADCENTSENSE_Enabled << 6) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSECAL (0x1UL << 7) /**< AUXADCENTSENSECAL */ +#define _RAC_AUXADCEN_AUXADCENTSENSECAL_SHIFT 7 /**< Shift value for RAC_AUXADCENTSENSECAL */ +#define _RAC_AUXADCEN_AUXADCENTSENSECAL_MASK 0x80UL /**< Bit mask for RAC_AUXADCENTSENSECAL */ +#define _RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT (_RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled (_RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled << 7) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled (_RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled << 7) /**< Shifted mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS (0x1UL << 8) /**< AUXADCINPUTBUFFERBYPASS */ +#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_SHIFT 8 /**< Shift value for RAC_AUXADCINPUTBUFFERBYPASS */ +#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_MASK 0x100UL /**< Bit mask for RAC_AUXADCINPUTBUFFERBYPASS */ +#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed 0x00000000UL /**< Mode Not_Bypassed for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed 0x00000001UL /**< Mode Bypassed for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed << 8) /**< Shifted mode Not_Bypassed for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed << 8) /**< Shifted mode Bypassed for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR (0x1UL << 9) /**< AUXADCENMEASTHERMISTOR */ +#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_SHIFT 9 /**< Shift value for RAC_AUXADCENMEASTHERMISTOR */ +#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_MASK 0x200UL /**< Bit mask for RAC_AUXADCENMEASTHERMISTOR */ +#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */ +#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled << 9) /**< Shifted mode Disabled for RAC_AUXADCEN */ +#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled << 9) /**< Shifted mode Enabled for RAC_AUXADCEN */ + +/* Bit fields for RAC AUXADCCTRL0 */ +#define _RAC_AUXADCCTRL0_RESETVALUE 0x00000100UL /**< Default value for RAC_AUXADCCTRL0 */ +#define _RAC_AUXADCCTRL0_MASK 0x00003FFFUL /**< Mask for RAC_AUXADCCTRL0 */ +#define _RAC_AUXADCCTRL0_CYCLES_SHIFT 0 /**< Shift value for RAC_CYCLES */ +#define _RAC_AUXADCCTRL0_CYCLES_MASK 0x3FFUL /**< Bit mask for RAC_CYCLES */ +#define _RAC_AUXADCCTRL0_CYCLES_DEFAULT 0x00000100UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_CYCLES_DEFAULT (_RAC_AUXADCCTRL0_CYCLES_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */ +#define _RAC_AUXADCCTRL0_MUXSEL_SHIFT 10 /**< Shift value for RAC_MUXSEL */ +#define _RAC_AUXADCCTRL0_MUXSEL_MASK 0xC00UL /**< Bit mask for RAC_MUXSEL */ +#define _RAC_AUXADCCTRL0_MUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_MUXSEL_DEFAULT (_RAC_AUXADCCTRL0_MUXSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_CLRCOUNTER (0x1UL << 12) /**< Clear counter */ +#define _RAC_AUXADCCTRL0_CLRCOUNTER_SHIFT 12 /**< Shift value for RAC_CLRCOUNTER */ +#define _RAC_AUXADCCTRL0_CLRCOUNTER_MASK 0x1000UL /**< Bit mask for RAC_CLRCOUNTER */ +#define _RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT (_RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_CLRFILTER (0x1UL << 13) /**< Clear accumulators */ +#define _RAC_AUXADCCTRL0_CLRFILTER_SHIFT 13 /**< Shift value for RAC_CLRFILTER */ +#define _RAC_AUXADCCTRL0_CLRFILTER_MASK 0x2000UL /**< Bit mask for RAC_CLRFILTER */ +#define _RAC_AUXADCCTRL0_CLRFILTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */ +#define RAC_AUXADCCTRL0_CLRFILTER_DEFAULT (_RAC_AUXADCCTRL0_CLRFILTER_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */ + +/* Bit fields for RAC AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_MASK 0xF31F0FFFUL /**< Mask for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_SHIFT 0 /**< Shift value for RAC_AUXADCINPUTRESSEL */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_MASK 0xFUL /**< Bit mask for RAC_AUXADCINPUTRESSEL */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm 0x00000000UL /**< Mode RES640kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm 0x00000001UL /**< Mode RES320kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm 0x00000002UL /**< Mode RES160kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm 0x00000003UL /**< Mode RES80kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm 0x00000004UL /**< Mode RES40kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm 0x00000005UL /**< Mode RES20kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm 0x00000006UL /**< Mode RES10kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm 0x00000007UL /**< Mode RES5kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm 0x00000008UL /**< Mode RES2p5kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm 0x00000009UL /**< Mode RES1p25kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm 0x0000000AUL /**< Mode RES0p6kOhm for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch 0x0000000BUL /**< Mode RES_switch for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm << 0) /**< Shifted mode RES640kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm << 0) /**< Shifted mode RES320kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm << 0) /**< Shifted mode RES160kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm << 0) /**< Shifted mode RES80kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm << 0) /**< Shifted mode RES40kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm << 0) /**< Shifted mode RES20kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm << 0) /**< Shifted mode RES10kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm << 0) /**< Shifted mode RES5kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm << 0) /**< Shifted mode RES2p5kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm << 0) /**< Shifted mode RES1p25kOhm for RAC_AUXADCCTRL1*/ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm << 0) /**< Shifted mode RES0p6kOhm for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch << 0) /**< Shifted mode RES_switch for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SHIFT 4 /**< Shift value for RAC_AUXADCINPUTSELECT */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_MASK 0xF0UL /**< Bit mask for RAC_AUXADCINPUTSELECT */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 0x00000000UL /**< Mode SEL0 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 0x00000001UL /**< Mode SEL1 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 0x00000002UL /**< Mode SEL2 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 0x00000003UL /**< Mode SEL3 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 0x00000004UL /**< Mode SEL4 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 0x00000005UL /**< Mode SEL5 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 0x00000006UL /**< Mode SEL6 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 0x00000007UL /**< Mode SEL7 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 0x00000008UL /**< Mode SEL8 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 0x00000009UL /**< Mode SEL9 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 << 4) /**< Shifted mode SEL0 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 << 4) /**< Shifted mode SEL1 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 << 4) /**< Shifted mode SEL2 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 << 4) /**< Shifted mode SEL3 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 << 4) /**< Shifted mode SEL4 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 << 4) /**< Shifted mode SEL5 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 << 4) /**< Shifted mode SEL6 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 << 4) /**< Shifted mode SEL7 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 << 4) /**< Shifted mode SEL8 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 << 4) /**< Shifted mode SEL9 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_SHIFT 8 /**< Shift value for RAC_AUXADCPMONSELECT */ +#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_MASK 0xF00UL /**< Bit mask for RAC_AUXADCPMONSELECT */ +#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT (_RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_SHIFT 16 /**< Shift value for RAC_AUXADCTSENSESELCURR */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_MASK 0x1F0000UL /**< Bit mask for RAC_AUXADCTSENSESELCURR */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCRESET (0x1UL << 24) /**< AUXADCRESET */ +#define _RAC_AUXADCCTRL1_AUXADCRESET_SHIFT 24 /**< Shift value for RAC_AUXADCRESET */ +#define _RAC_AUXADCCTRL1_AUXADCRESET_MASK 0x1000000UL /**< Bit mask for RAC_AUXADCRESET */ +#define _RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled 0x00000000UL /**< Mode Reset_Disabled for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled 0x00000001UL /**< Mode Reset_Enabled for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT (_RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled (_RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled << 24) /**< Shifted mode Reset_Disabled for RAC_AUXADCCTRL1*/ +#define RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled (_RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled << 24) /**< Shifted mode Reset_Enabled for RAC_AUXADCCTRL1*/ +#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE (0x1UL << 25) /**< AUXADCTSENSESELVBE */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_SHIFT 25 /**< Shift value for RAC_AUXADCTSENSESELVBE */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_MASK 0x2000000UL /**< Bit mask for RAC_AUXADCTSENSESELVBE */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 0x00000000UL /**< Mode VBE1 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 0x00000001UL /**< Mode VBE2 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 << 25) /**< Shifted mode VBE1 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 << 25) /**< Shifted mode VBE2 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_SHIFT 28 /**< Shift value for RAC_AUXADCTHERMISTORFREQSEL */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_MASK 0xF0000000UL /**< Bit mask for RAC_AUXADCTHERMISTORFREQSEL */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 0x00000000UL /**< Mode DIV1 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 0x00000001UL /**< Mode DIV2 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 0x00000002UL /**< Mode DIV4 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 0x00000003UL /**< Mode DIV8 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 0x00000004UL /**< Mode DIV16 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 0x00000005UL /**< Mode DIV32 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 0x00000006UL /**< Mode DIV64 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 0x00000007UL /**< Mode DIV128 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 0x00000008UL /**< Mode DIV256 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 0x00000009UL /**< Mode DIV512 for RAC_AUXADCCTRL1 */ +#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 0x0000000AUL /**< Mode DIV1024 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 << 28) /**< Shifted mode DIV1 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 << 28) /**< Shifted mode DIV2 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 << 28) /**< Shifted mode DIV4 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 << 28) /**< Shifted mode DIV8 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 << 28) /**< Shifted mode DIV16 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 << 28) /**< Shifted mode DIV32 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 << 28) /**< Shifted mode DIV64 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 << 28) /**< Shifted mode DIV128 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 << 28) /**< Shifted mode DIV256 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 << 28) /**< Shifted mode DIV512 for RAC_AUXADCCTRL1 */ +#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 << 28) /**< Shifted mode DIV1024 for RAC_AUXADCCTRL1 */ + +/* Bit fields for RAC AUXADCOUT */ +#define _RAC_AUXADCOUT_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCOUT */ +#define _RAC_AUXADCOUT_MASK 0x0FFFFFFFUL /**< Mask for RAC_AUXADCOUT */ +#define _RAC_AUXADCOUT_AUXADCOUT_SHIFT 0 /**< Shift value for RAC_AUXADCOUT */ +#define _RAC_AUXADCOUT_AUXADCOUT_MASK 0xFFFFFFFUL /**< Bit mask for RAC_AUXADCOUT */ +#define _RAC_AUXADCOUT_AUXADCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCOUT */ +#define RAC_AUXADCOUT_AUXADCOUT_DEFAULT (_RAC_AUXADCOUT_AUXADCOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCOUT */ + +/* Bit fields for RAC CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_RESETVALUE 0xAA400005UL /**< Default value for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_MASK 0xFFDFFFFFUL /**< Mask for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_SHIFT 0 /**< Shift value for RAC_CLKMULTBWCAL */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_MASK 0x3UL /**< Bit mask for RAC_CLKMULTBWCAL */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb 0x00000000UL /**< Mode bw_1lsb for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb 0x00000001UL /**< Mode bw_2lsb for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb 0x00000002UL /**< Mode bw_3lsb for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb 0x00000003UL /**< Mode bw_4lsb for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT (_RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb << 0) /**< Shifted mode bw_1lsb for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb << 0) /**< Shifted mode bw_2lsb for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb << 0) /**< Shifted mode bw_3lsb for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb << 0) /**< Shifted mode bw_4lsb for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTDISICO (0x1UL << 2) /**< CLKMULTDISICO */ +#define _RAC_CLKMULTEN0_CLKMULTDISICO_SHIFT 2 /**< Shift value for RAC_CLKMULTDISICO */ +#define _RAC_CLKMULTEN0_CLKMULTDISICO_MASK 0x4UL /**< Bit mask for RAC_CLKMULTDISICO */ +#define _RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTDISICO_enable 0x00000000UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTDISICO_disable 0x00000001UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT (_RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTDISICO_enable (_RAC_CLKMULTEN0_CLKMULTDISICO_enable << 2) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTDISICO_disable (_RAC_CLKMULTEN0_CLKMULTDISICO_disable << 2) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBDET (0x1UL << 3) /**< CLKMULTENBBDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBDET_SHIFT 3 /**< Shift value for RAC_CLKMULTENBBDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBDET_MASK 0x8UL /**< Bit mask for RAC_CLKMULTENBBDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBDET_disable << 3) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBDET_enable << 3) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXLDET (0x1UL << 4) /**< CLKMULTENBBXLDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_SHIFT 4 /**< Shift value for RAC_CLKMULTENBBXLDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_MASK 0x10UL /**< Bit mask for RAC_CLKMULTENBBXLDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable << 4) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable << 4) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXMDET (0x1UL << 5) /**< CLKMULTENBBXMDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_SHIFT 5 /**< Shift value for RAC_CLKMULTENBBXMDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_MASK 0x20UL /**< Bit mask for RAC_CLKMULTENBBXMDET */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable << 5) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable << 5) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENCFDET (0x1UL << 6) /**< CLKMULTENCFDET */ +#define _RAC_CLKMULTEN0_CLKMULTENCFDET_SHIFT 6 /**< Shift value for RAC_CLKMULTENCFDET */ +#define _RAC_CLKMULTEN0_CLKMULTENCFDET_MASK 0x40UL /**< Bit mask for RAC_CLKMULTENCFDET */ +#define _RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENCFDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENCFDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENCFDET_disable (_RAC_CLKMULTEN0_CLKMULTENCFDET_disable << 6) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENCFDET_enable (_RAC_CLKMULTEN0_CLKMULTENCFDET_enable << 6) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDITHER (0x1UL << 7) /**< CLKMULTENDITHER */ +#define _RAC_CLKMULTEN0_CLKMULTENDITHER_SHIFT 7 /**< Shift value for RAC_CLKMULTENDITHER */ +#define _RAC_CLKMULTEN0_CLKMULTENDITHER_MASK 0x80UL /**< Bit mask for RAC_CLKMULTENDITHER */ +#define _RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDITHER_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDITHER_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDITHER_disable (_RAC_CLKMULTEN0_CLKMULTENDITHER_disable << 7) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDITHER_enable (_RAC_CLKMULTEN0_CLKMULTENDITHER_enable << 7) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVADC (0x1UL << 8) /**< CLKMULTENDRVADC */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_SHIFT 8 /**< Shift value for RAC_CLKMULTENDRVADC */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_MASK 0x100UL /**< Bit mask for RAC_CLKMULTENDRVADC */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVADC_disable (_RAC_CLKMULTEN0_CLKMULTENDRVADC_disable << 8) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVADC_enable (_RAC_CLKMULTEN0_CLKMULTENDRVADC_enable << 8) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVN (0x1UL << 9) /**< CLKMULTENDRVN */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVN_SHIFT 9 /**< Shift value for RAC_CLKMULTENDRVN */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVN_MASK 0x200UL /**< Bit mask for RAC_CLKMULTENDRVN */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVN_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVN_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVN_disable (_RAC_CLKMULTEN0_CLKMULTENDRVN_disable << 9) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVN_enable (_RAC_CLKMULTEN0_CLKMULTENDRVN_enable << 9) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVP (0x1UL << 10) /**< CLKMULTENDRVP */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVP_SHIFT 10 /**< Shift value for RAC_CLKMULTENDRVP */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVP_MASK 0x400UL /**< Bit mask for RAC_CLKMULTENDRVP */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVP_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVP_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVP_disable (_RAC_CLKMULTEN0_CLKMULTENDRVP_disable << 10) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVP_enable (_RAC_CLKMULTEN0_CLKMULTENDRVP_enable << 10) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G (0x1UL << 11) /**< CLKMULTENDRVRX2P4G */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_SHIFT 11 /**< Shift value for RAC_CLKMULTENDRVRX2P4G */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_MASK 0x800UL /**< Bit mask for RAC_CLKMULTENDRVRX2P4G */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable << 11) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable << 11) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENFBDIV (0x1UL << 14) /**< CLKMULTENFBDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_SHIFT 14 /**< Shift value for RAC_CLKMULTENFBDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_MASK 0x4000UL /**< Bit mask for RAC_CLKMULTENFBDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENFBDIV_disable (_RAC_CLKMULTEN0_CLKMULTENFBDIV_disable << 14) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENFBDIV_enable (_RAC_CLKMULTEN0_CLKMULTENFBDIV_enable << 14) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREFDIV (0x1UL << 15) /**< CLKMULTENREFDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_SHIFT 15 /**< Shift value for RAC_CLKMULTENREFDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_MASK 0x8000UL /**< Bit mask for RAC_CLKMULTENREFDIV */ +#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREFDIV_disable (_RAC_CLKMULTEN0_CLKMULTENREFDIV_disable << 15) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREFDIV_enable (_RAC_CLKMULTEN0_CLKMULTENREFDIV_enable << 15) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG1 (0x1UL << 16) /**< CLKMULTENREG1 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG1_SHIFT 16 /**< Shift value for RAC_CLKMULTENREG1 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG1_MASK 0x10000UL /**< Bit mask for RAC_CLKMULTENREG1 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG1_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG1_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG1_disable (_RAC_CLKMULTEN0_CLKMULTENREG1_disable << 16) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG1_enable (_RAC_CLKMULTEN0_CLKMULTENREG1_enable << 16) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG2 (0x1UL << 17) /**< CLKMULTENREG2 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG2_SHIFT 17 /**< Shift value for RAC_CLKMULTENREG2 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG2_MASK 0x20000UL /**< Bit mask for RAC_CLKMULTENREG2 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG2_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG2_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG2_disable (_RAC_CLKMULTEN0_CLKMULTENREG2_disable << 17) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG2_enable (_RAC_CLKMULTEN0_CLKMULTENREG2_enable << 17) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG3 (0x1UL << 18) /**< CLKMULTENREG3 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG3_SHIFT 18 /**< Shift value for RAC_CLKMULTENREG3 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG3_MASK 0x40000UL /**< Bit mask for RAC_CLKMULTENREG3 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG3_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENREG3_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG3_disable (_RAC_CLKMULTEN0_CLKMULTENREG3_disable << 18) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENREG3_enable (_RAC_CLKMULTEN0_CLKMULTENREG3_enable << 18) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENROTDET (0x1UL << 19) /**< CLKMULTENROTDET */ +#define _RAC_CLKMULTEN0_CLKMULTENROTDET_SHIFT 19 /**< Shift value for RAC_CLKMULTENROTDET */ +#define _RAC_CLKMULTEN0_CLKMULTENROTDET_MASK 0x80000UL /**< Bit mask for RAC_CLKMULTENROTDET */ +#define _RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENROTDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENROTDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENROTDET_disable (_RAC_CLKMULTEN0_CLKMULTENROTDET_disable << 19) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENROTDET_enable (_RAC_CLKMULTEN0_CLKMULTENROTDET_enable << 19) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ (0x1UL << 20) /**< CLKMULTENBYPASS40MHZ */ +#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_SHIFT 20 /**< Shift value for RAC_CLKMULTENBYPASS40MHZ */ +#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_MASK 0x100000UL /**< Bit mask for RAC_CLKMULTENBYPASS40MHZ */ +#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable << 20) /**< Shifted mode disable for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable << 20) /**< Shifted mode enable for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_SHIFT 22 /**< Shift value for RAC_CLKMULTFREQCAL */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_MASK 0xC00000UL /**< Bit mask for RAC_CLKMULTFREQCAL */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA 0x00000000UL /**< Mode pedes_14uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA 0x00000001UL /**< Mode pedes_22uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA 0x00000002UL /**< Mode pedes_30uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA 0x00000003UL /**< Mode pedes_38uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT (_RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA << 22) /**< Shifted mode pedes_14uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA << 22) /**< Shifted mode pedes_22uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA << 22) /**< Shifted mode pedes_30uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA << 22) /**< Shifted mode pedes_38uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_SHIFT 24 /**< Shift value for RAC_CLKMULTREG2ADJI */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_MASK 0x3000000UL /**< Bit mask for RAC_CLKMULTREG2ADJI */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA 0x00000000UL /**< Mode I_80uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA 0x00000001UL /**< Mode I_100uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA 0x00000002UL /**< Mode I_120uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA 0x00000003UL /**< Mode I_140uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA << 24) /**< Shifted mode I_80uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA << 24) /**< Shifted mode I_100uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA << 24) /**< Shifted mode I_120uA for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA << 24) /**< Shifted mode I_140uA for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_SHIFT 26 /**< Shift value for RAC_CLKMULTREG1ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_MASK 0xC000000UL /**< Bit mask for RAC_CLKMULTREG1ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 0x00000000UL /**< Mode v1p28 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 0x00000001UL /**< Mode v1p32 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 0x00000002UL /**< Mode v1p33 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 0x00000003UL /**< Mode v1p38 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 << 26) /**< Shifted mode v1p28 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 << 26) /**< Shifted mode v1p32 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 << 26) /**< Shifted mode v1p33 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 << 26) /**< Shifted mode v1p38 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_SHIFT 28 /**< Shift value for RAC_CLKMULTREG2ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_MASK 0x30000000UL /**< Bit mask for RAC_CLKMULTREG2ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 0x00000000UL /**< Mode v1p03 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 0x00000001UL /**< Mode v1p09 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 0x00000002UL /**< Mode v1p10 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 0x00000003UL /**< Mode v1p16 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 << 28) /**< Shifted mode v1p03 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 << 28) /**< Shifted mode v1p09 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 << 28) /**< Shifted mode v1p10 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 << 28) /**< Shifted mode v1p16 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_SHIFT 30 /**< Shift value for RAC_CLKMULTREG3ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_MASK 0xC0000000UL /**< Bit mask for RAC_CLKMULTREG3ADJV */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 0x00000000UL /**< Mode v1p03 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 0x00000001UL /**< Mode v1p06 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 0x00000002UL /**< Mode v1p07 for RAC_CLKMULTEN0 */ +#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 0x00000003UL /**< Mode v1p09 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 << 30) /**< Shifted mode v1p03 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 << 30) /**< Shifted mode v1p06 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 << 30) /**< Shifted mode v1p07 for RAC_CLKMULTEN0 */ +#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 << 30) /**< Shifted mode v1p09 for RAC_CLKMULTEN0 */ + +/* Bit fields for RAC CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_RESETVALUE 0x00000188UL /**< Default value for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_MASK 0x0001FDEFUL /**< Mask for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_SHIFT 0 /**< Shift value for RAC_CLKMULTINNIBBLE */ +#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_MASK 0xFUL /**< Bit mask for RAC_CLKMULTINNIBBLE */ +#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT (_RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDFNIB (0x1UL << 5) /**< CLKMULTLDFNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_SHIFT 5 /**< Shift value for RAC_CLKMULTLDFNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_MASK 0x20UL /**< Bit mask for RAC_CLKMULTLDFNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDFNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDFNIB_disable << 5) /**< Shifted mode disable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDFNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDFNIB_enable << 5) /**< Shifted mode enable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDMNIB (0x1UL << 6) /**< CLKMULTLDMNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_SHIFT 6 /**< Shift value for RAC_CLKMULTLDMNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_MASK 0x40UL /**< Bit mask for RAC_CLKMULTLDMNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDMNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDMNIB_disable << 6) /**< Shifted mode disable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDMNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDMNIB_enable << 6) /**< Shifted mode enable for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_SHIFT 7 /**< Shift value for RAC_CLKMULTRDNIBBLE */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_MASK 0x180UL /**< Bit mask for RAC_CLKMULTRDNIBBLE */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble 0x00000000UL /**< Mode quarter_nibble for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble 0x00000001UL /**< Mode fine_nibble for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble 0x00000002UL /**< Mode moderate_nibble for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble 0x00000003UL /**< Mode coarse_nibble for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble << 7) /**< Shifted mode quarter_nibble for RAC_CLKMULTEN1*/ +#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble << 7) /**< Shifted mode fine_nibble for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble << 7) /**< Shifted mode moderate_nibble for RAC_CLKMULTEN1*/ +#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble << 7) /**< Shifted mode coarse_nibble for RAC_CLKMULTEN1*/ +#define RAC_CLKMULTEN1_CLKMULTLDCNIB (0x1UL << 10) /**< CLKMULTLDCNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_SHIFT 10 /**< Shift value for RAC_CLKMULTLDCNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_MASK 0x400UL /**< Bit mask for RAC_CLKMULTLDCNIB */ +#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDCNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDCNIB_disable << 10) /**< Shifted mode disable for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTLDCNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDCNIB_enable << 10) /**< Shifted mode enable for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_SHIFT 11 /**< Shift value for RAC_CLKMULTDRVAMPSEL */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_MASK 0x1F800UL /**< Bit mask for RAC_CLKMULTDRVAMPSEL */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off 0x00000000UL /**< Mode off for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 0x00000001UL /**< Mode slide_x1 for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 0x00000003UL /**< Mode slide_x2 for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 0x00000007UL /**< Mode slide_x3 for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 0x0000000FUL /**< Mode slide_x4 for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 0x0000001FUL /**< Mode slide_x5 for RAC_CLKMULTEN1 */ +#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 0x0000003FUL /**< Mode slide_x6 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off << 11) /**< Shifted mode off for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 << 11) /**< Shifted mode slide_x1 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 << 11) /**< Shifted mode slide_x2 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 << 11) /**< Shifted mode slide_x3 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 << 11) /**< Shifted mode slide_x4 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 << 11) /**< Shifted mode slide_x5 for RAC_CLKMULTEN1 */ +#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 << 11) /**< Shifted mode slide_x6 for RAC_CLKMULTEN1 */ + +/* Bit fields for RAC CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_RESETVALUE 0x000000C0UL /**< Default value for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_MASK 0x00007FFFUL /**< Mask for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVN_SHIFT 0 /**< Shift value for RAC_CLKMULTDIVN */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVN_MASK 0x7FUL /**< Bit mask for RAC_CLKMULTDIVN */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT 0x00000040UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVR_SHIFT 7 /**< Shift value for RAC_CLKMULTDIVR */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVR_MASK 0x380UL /**< Bit mask for RAC_CLKMULTDIVR */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_SHIFT 10 /**< Shift value for RAC_CLKMULTDIVX */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_MASK 0x1C00UL /**< Bit mask for RAC_CLKMULTDIVX */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 0x00000000UL /**< Mode div_1 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 0x00000001UL /**< Mode div_2 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 0x00000002UL /**< Mode div_4 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 0x00000003UL /**< Mode div_6 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 0x00000004UL /**< Mode div_8 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div10 0x00000005UL /**< Mode div10 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div12 0x00000006UL /**< Mode div12 for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div14 0x00000007UL /**< Mode div14 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 << 10) /**< Shifted mode div_1 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 << 10) /**< Shifted mode div_2 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 << 10) /**< Shifted mode div_4 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 << 10) /**< Shifted mode div_6 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 << 10) /**< Shifted mode div_8 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div10 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div10 << 10) /**< Shifted mode div10 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div12 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div12 << 10) /**< Shifted mode div12 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTDIVX_div14 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div14 << 10) /**< Shifted mode div14 for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTENRESYNC (0x1UL << 13) /**< CLKMULTENRESYNC */ +#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_SHIFT 13 /**< Shift value for RAC_CLKMULTENRESYNC */ +#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_MASK 0x2000UL /**< Bit mask for RAC_CLKMULTENRESYNC */ +#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync 0x00000000UL /**< Mode disable_sync for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync 0x00000001UL /**< Mode enable_sync for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync << 13) /**< Shifted mode disable_sync for RAC_CLKMULTCTRL*/ +#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync << 13) /**< Shifted mode enable_sync for RAC_CLKMULTCTRL*/ +#define RAC_CLKMULTCTRL_CLKMULTVALID (0x1UL << 14) /**< CLKMULTVALID */ +#define _RAC_CLKMULTCTRL_CLKMULTVALID_SHIFT 14 /**< Shift value for RAC_CLKMULTVALID */ +#define _RAC_CLKMULTCTRL_CLKMULTVALID_MASK 0x4000UL /**< Bit mask for RAC_CLKMULTVALID */ +#define _RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTVALID_invalid 0x00000000UL /**< Mode invalid for RAC_CLKMULTCTRL */ +#define _RAC_CLKMULTCTRL_CLKMULTVALID_valid 0x00000001UL /**< Mode valid for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTVALID_invalid (_RAC_CLKMULTCTRL_CLKMULTVALID_invalid << 14) /**< Shifted mode invalid for RAC_CLKMULTCTRL */ +#define RAC_CLKMULTCTRL_CLKMULTVALID_valid (_RAC_CLKMULTCTRL_CLKMULTVALID_valid << 14) /**< Shifted mode valid for RAC_CLKMULTCTRL */ + +/* Bit fields for RAC CLKMULTSTATUS */ +#define _RAC_CLKMULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_CLKMULTSTATUS */ +#define _RAC_CLKMULTSTATUS_MASK 0x0000001FUL /**< Mask for RAC_CLKMULTSTATUS */ +#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_SHIFT 0 /**< Shift value for RAC_CLKMULTOUTNIBBLE */ +#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_MASK 0xFUL /**< Bit mask for RAC_CLKMULTOUTNIBBLE */ +#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTSTATUS */ +#define RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT (_RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTSTATUS */ +#define RAC_CLKMULTSTATUS_CLKMULTACKVALID (0x1UL << 4) /**< CLKMULTACKVALID */ +#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_SHIFT 4 /**< Shift value for RAC_CLKMULTACKVALID */ +#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_MASK 0x10UL /**< Bit mask for RAC_CLKMULTACKVALID */ +#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTSTATUS */ +#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid 0x00000000UL /**< Mode invalid for RAC_CLKMULTSTATUS */ +#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid 0x00000001UL /**< Mode valid for RAC_CLKMULTSTATUS */ +#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CLKMULTSTATUS */ +#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid << 4) /**< Shifted mode invalid for RAC_CLKMULTSTATUS */ +#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid << 4) /**< Shifted mode valid for RAC_CLKMULTSTATUS */ + +/* Bit fields for RAC IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_RESETVALUE 0x11512C6CUL /**< Default value for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_MASK 0x7FFFFFFDUL /**< Mask for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCCLKSEL (0x1UL << 0) /**< IFADCCLKSEL */ +#define _RAC_IFADCTRIM0_IFADCCLKSEL_SHIFT 0 /**< Shift value for RAC_IFADCCLKSEL */ +#define _RAC_IFADCTRIM0_IFADCCLKSEL_MASK 0x1UL /**< Bit mask for RAC_IFADCCLKSEL */ +#define _RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g 0x00000000UL /**< Mode clk_2p4g for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg 0x00000001UL /**< Mode clk_subg for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT (_RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g (_RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g << 0) /**< Shifted mode clk_2p4g for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg (_RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg << 0) /**< Shifted mode clk_subg for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_SHIFT 2 /**< Shift value for RAC_IFADCLDOSERIESAMPLVL */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_MASK 0x1CUL /**< Bit mask for RAC_IFADCLDOSERIESAMPLVL */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 0x00000000UL /**< Mode v1p225 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 0x00000001UL /**< Mode v1p250 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 0x00000002UL /**< Mode v1p275 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 0x00000003UL /**< Mode v1p300 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 0x00000004UL /**< Mode v1p325 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 0x00000005UL /**< Mode v1p350 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 0x00000006UL /**< Mode v1p375 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 0x00000007UL /**< Mode v1p400 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 << 2) /**< Shifted mode v1p225 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 << 2) /**< Shifted mode v1p250 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 << 2) /**< Shifted mode v1p275 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 << 2) /**< Shifted mode v1p300 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 << 2) /**< Shifted mode v1p325 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 << 2) /**< Shifted mode v1p350 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 << 2) /**< Shifted mode v1p375 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 << 2) /**< Shifted mode v1p400 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_SHIFT 5 /**< Shift value for RAC_IFADCLDOSHUNTAMPLVL1 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_MASK 0xE0UL /**< Bit mask for RAC_IFADCLDOSHUNTAMPLVL1 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 0x00000000UL /**< Mode v1p125 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 0x00000001UL /**< Mode v1p150 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 0x00000002UL /**< Mode v1p175 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 0x00000003UL /**< Mode v1p200 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 0x00000004UL /**< Mode v1p225 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 0x00000005UL /**< Mode v1p250 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 0x00000006UL /**< Mode v1p275 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 0x00000007UL /**< Mode v1p300 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 << 5) /**< Shifted mode v1p125 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 << 5) /**< Shifted mode v1p150 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 << 5) /**< Shifted mode v1p175 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 << 5) /**< Shifted mode v1p200 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 << 5) /**< Shifted mode v1p225 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 << 5) /**< Shifted mode v1p250 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 << 5) /**< Shifted mode v1p275 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 << 5) /**< Shifted mode v1p300 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2 (0x1UL << 8) /**< IFADCLDOSHUNTAMPLVL2 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_SHIFT 8 /**< Shift value for RAC_IFADCLDOSHUNTAMPLVL2 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_MASK 0x100UL /**< Bit mask for RAC_IFADCLDOSHUNTAMPLVL2 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable 0x00000000UL /**< Mode disable for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable 0x00000001UL /**< Mode enable for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable << 8) /**< Shifted mode disable for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable << 8) /**< Shifted mode enable for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_SHIFT 9 /**< Shift value for RAC_IFADCLDOSHUNTCURLVL1 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_MASK 0xE00UL /**< Bit mask for RAC_IFADCLDOSHUNTCURLVL1 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT 0x00000006UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u 0x00000000UL /**< Mode i55u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u 0x00000001UL /**< Mode i65u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u 0x00000002UL /**< Mode i70u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u 0x00000003UL /**< Mode i85u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 0x00000004UL /**< Mode i85u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u 0x00000005UL /**< Mode i95u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u 0x00000006UL /**< Mode i100u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u 0x00000007UL /**< Mode i110u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u << 9) /**< Shifted mode i55u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u << 9) /**< Shifted mode i65u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u << 9) /**< Shifted mode i70u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u << 9) /**< Shifted mode i85u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 << 9) /**< Shifted mode i85u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u << 9) /**< Shifted mode i95u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u << 9) /**< Shifted mode i100u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u << 9) /**< Shifted mode i110u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_SHIFT 12 /**< Shift value for RAC_IFADCLDOSHUNTCURLVL2 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_MASK 0x7000UL /**< Bit mask for RAC_IFADCLDOSHUNTCURLVL2 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u 0x00000000UL /**< Mode i4u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u 0x00000001UL /**< Mode i4p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u 0x00000002UL /**< Mode i5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u 0x00000003UL /**< Mode i5p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 0x00000004UL /**< Mode i5u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 0x00000005UL /**< Mode i5p5u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u 0x00000006UL /**< Mode i6u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u 0x00000007UL /**< Mode i6p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u << 12) /**< Shifted mode i4u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u << 12) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u << 12) /**< Shifted mode i5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u << 12) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 << 12) /**< Shifted mode i5u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 << 12) /**< Shifted mode i5p5u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u << 12) /**< Shifted mode i6u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u << 12) /**< Shifted mode i6p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_SHIFT 15 /**< Shift value for RAC_IFADCOTACURRENT */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_MASK 0x38000UL /**< Bit mask for RAC_IFADCOTACURRENT */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i3u 0x00000000UL /**< Mode i3u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u 0x00000001UL /**< Mode i3p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4u 0x00000002UL /**< Mode i4u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u 0x00000003UL /**< Mode i4p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 0x00000004UL /**< Mode i4u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 0x00000005UL /**< Mode i4p5u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i5u 0x00000006UL /**< Mode i5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u 0x00000007UL /**< Mode i5p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT (_RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i3u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i3u << 15) /**< Shifted mode i3u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u << 15) /**< Shifted mode i3p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4u << 15) /**< Shifted mode i4u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u << 15) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 << 15) /**< Shifted mode i4u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 << 15) /**< Shifted mode i4p5u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i5u << 15) /**< Shifted mode i5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u << 15) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_SHIFT 18 /**< Shift value for RAC_IFADCREFBUFAMPLVL */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_MASK 0x1C0000UL /**< Bit mask for RAC_IFADCREFBUFAMPLVL */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 0x00000000UL /**< Mode v0p88 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 0x00000001UL /**< Mode v0p91 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 0x00000002UL /**< Mode v0p94 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 0x00000003UL /**< Mode v0p97 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 0x00000004UL /**< Mode v1p00 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 0x00000005UL /**< Mode v1p03 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 0x00000006UL /**< Mode v1p06 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 0x00000007UL /**< Mode v1p09 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 << 18) /**< Shifted mode v0p88 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 << 18) /**< Shifted mode v0p91 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 << 18) /**< Shifted mode v0p94 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 << 18) /**< Shifted mode v0p97 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 << 18) /**< Shifted mode v1p00 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 << 18) /**< Shifted mode v1p03 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 << 18) /**< Shifted mode v1p06 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 << 18) /**< Shifted mode v1p09 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_SHIFT 21 /**< Shift value for RAC_IFADCREFBUFCURLVL */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_MASK 0xE00000UL /**< Bit mask for RAC_IFADCREFBUFCURLVL */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u 0x00000000UL /**< Mode i4u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u 0x00000001UL /**< Mode i4p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u 0x00000002UL /**< Mode i5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u 0x00000003UL /**< Mode i5p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 0x00000004UL /**< Mode i5u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 0x00000005UL /**< Mode i5p5u2 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u 0x00000006UL /**< Mode i6u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u 0x00000007UL /**< Mode i6p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u << 21) /**< Shifted mode i4u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u << 21) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u << 21) /**< Shifted mode i5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u << 21) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 << 21) /**< Shifted mode i5u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 << 21) /**< Shifted mode i5p5u2 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u << 21) /**< Shifted mode i6u for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u << 21) /**< Shifted mode i6p5u for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_SHIFT 24 /**< Shift value for RAC_IFADCSIDETONEAMP */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_MASK 0x7000000UL /**< Bit mask for RAC_IFADCSIDETONEAMP */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV 0x00000000UL /**< Mode diff_5p68mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV 0x00000001UL /**< Mode diff_29p1mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV 0x00000002UL /**< Mode diff_9p73mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV 0x00000003UL /**< Mode diff_76p9mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV 0x00000004UL /**< Mode diff_9p68_mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV 0x00000005UL /**< Mode diff_51_mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV 0x00000006UL /**< Mode diff_17p2_mV for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable 0x00000007UL /**< Mode disable for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV << 24) /**< Shifted mode diff_5p68mV for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV << 24) /**< Shifted mode diff_29p1mV for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV << 24) /**< Shifted mode diff_9p73mV for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV << 24) /**< Shifted mode diff_76p9mV for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV << 24) /**< Shifted mode diff_9p68_mV for RAC_IFADCTRIM0*/ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV << 24) /**< Shifted mode diff_51_mV for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV << 24) /**< Shifted mode diff_17p2_mV for RAC_IFADCTRIM0*/ +#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable << 24) /**< Shifted mode disable for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_SHIFT 27 /**< Shift value for RAC_IFADCSIDETONEFREQ */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_MASK 0x38000000UL /**< Bit mask for RAC_IFADCSIDETONEFREQ */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 0x00000000UL /**< Mode na0 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 0x00000001UL /**< Mode div_128 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 0x00000002UL /**< Mode div_64 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 0x00000003UL /**< Mode div_32 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 0x00000004UL /**< Mode div_16 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 0x00000005UL /**< Mode div_8 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 0x00000006UL /**< Mode div_4 for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 0x00000007UL /**< Mode na7 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 << 27) /**< Shifted mode na0 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 << 27) /**< Shifted mode div_128 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 << 27) /**< Shifted mode div_64 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 << 27) /**< Shifted mode div_32 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 << 27) /**< Shifted mode div_16 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 << 27) /**< Shifted mode div_8 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 << 27) /**< Shifted mode div_4 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 << 27) /**< Shifted mode na7 for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCENHALFMODE (0x1UL << 30) /**< IFADCENHALFMODE */ +#define _RAC_IFADCTRIM0_IFADCENHALFMODE_SHIFT 30 /**< Shift value for RAC_IFADCENHALFMODE */ +#define _RAC_IFADCTRIM0_IFADCENHALFMODE_MASK 0x40000000UL /**< Bit mask for RAC_IFADCENHALFMODE */ +#define _RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode 0x00000000UL /**< Mode full_speed_mode for RAC_IFADCTRIM0 */ +#define _RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode 0x00000001UL /**< Mode half_speed_mode for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT (_RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */ +#define RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode (_RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode << 30) /**< Shifted mode full_speed_mode for RAC_IFADCTRIM0*/ +#define RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode (_RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode << 30) /**< Shifted mode half_speed_mode for RAC_IFADCTRIM0*/ + +/* Bit fields for RAC IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_RESETVALUE 0x00000123UL /**< Default value for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_MASK 0x000001FFUL /**< Mask for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_SHIFT 0 /**< Shift value for RAC_IFADCVCMLVL */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_MASK 0x7UL /**< Bit mask for RAC_IFADCVCMLVL */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV 0x00000000UL /**< Mode vcm_475mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV 0x00000001UL /**< Mode vcm_500mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV 0x00000002UL /**< Mode vcm_525mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV 0x00000003UL /**< Mode vcm_550mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV 0x00000004UL /**< Mode vcm_575mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV 0x00000005UL /**< Mode vcm_600mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV 0x00000006UL /**< Mode vcm_625mV for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV 0x00000007UL /**< Mode cm_650mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT (_RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV << 0) /**< Shifted mode vcm_475mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV << 0) /**< Shifted mode vcm_500mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV << 0) /**< Shifted mode vcm_525mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV << 0) /**< Shifted mode vcm_550mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV << 0) /**< Shifted mode vcm_575mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV << 0) /**< Shifted mode vcm_600mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV << 0) /**< Shifted mode vcm_625mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV (_RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV << 0) /**< Shifted mode cm_650mV for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCENNEGRES (0x1UL << 3) /**< IFADCENNEGRES */ +#define _RAC_IFADCTRIM1_IFADCENNEGRES_SHIFT 3 /**< Shift value for RAC_IFADCENNEGRES */ +#define _RAC_IFADCTRIM1_IFADCENNEGRES_MASK 0x8UL /**< Bit mask for RAC_IFADCENNEGRES */ +#define _RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCENNEGRES_disable 0x00000000UL /**< Mode disable for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCENNEGRES_enable 0x00000001UL /**< Mode enable for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT (_RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCENNEGRES_disable (_RAC_IFADCTRIM1_IFADCENNEGRES_disable << 3) /**< Shifted mode disable for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCENNEGRES_enable (_RAC_IFADCTRIM1_IFADCENNEGRES_enable << 3) /**< Shifted mode enable for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_SHIFT 4 /**< Shift value for RAC_IFADCNEGRESCURRENT */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_MASK 0x70UL /**< Bit mask for RAC_IFADCNEGRESCURRENT */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u 0x00000000UL /**< Mode i1p0u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u 0x00000001UL /**< Mode i1p5u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u 0x00000002UL /**< Mode i2p0u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u 0x00000003UL /**< Mode i2p5u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 0x00000004UL /**< Mode i2p0u2 for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 0x00000005UL /**< Mode i2p5u2 for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u 0x00000006UL /**< Mode i3p0u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u 0x00000007UL /**< Mode i3p5u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u << 4) /**< Shifted mode i1p0u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u << 4) /**< Shifted mode i1p5u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u << 4) /**< Shifted mode i2p0u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u << 4) /**< Shifted mode i2p5u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 << 4) /**< Shifted mode i2p0u2 for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 << 4) /**< Shifted mode i2p5u2 for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u << 4) /**< Shifted mode i3p0u for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u << 4) /**< Shifted mode i3p5u for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_SHIFT 7 /**< Shift value for RAC_IFADCNEGRESVCM */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_MASK 0x180UL /**< Bit mask for RAC_IFADCNEGRESVCM */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA 0x00000000UL /**< Mode r210k_x_1uA for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 0x00000001UL /**< Mode r210k_x_1uA2 for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA 0x00000002UL /**< Mode r100k_x_2uA for RAC_IFADCTRIM1 */ +#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA 0x00000003UL /**< Mode r50k_x_3uA for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT (_RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA << 7) /**< Shifted mode r210k_x_1uA for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 << 7) /**< Shifted mode r210k_x_1uA2 for RAC_IFADCTRIM1*/ +#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA << 7) /**< Shifted mode r100k_x_2uA for RAC_IFADCTRIM1 */ +#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA << 7) /**< Shifted mode r50k_x_3uA for RAC_IFADCTRIM1 */ + +/* Bit fields for RAC IFADCCAL */ +#define _RAC_IFADCCAL_RESETVALUE 0x00000C00UL /**< Default value for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_MASK 0x00FF1F03UL /**< Mask for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCENRCCAL (0x1UL << 0) /**< IFADCENRCCAL */ +#define _RAC_IFADCCAL_IFADCENRCCAL_SHIFT 0 /**< Shift value for RAC_IFADCENRCCAL */ +#define _RAC_IFADCCAL_IFADCENRCCAL_MASK 0x1UL /**< Bit mask for RAC_IFADCENRCCAL */ +#define _RAC_IFADCCAL_IFADCENRCCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCENRCCAL_rccal_disable 0x00000000UL /**< Mode rccal_disable for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCENRCCAL_rccal_enable 0x00000001UL /**< Mode rccal_enable for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCENRCCAL_DEFAULT (_RAC_IFADCCAL_IFADCENRCCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCENRCCAL_rccal_disable (_RAC_IFADCCAL_IFADCENRCCAL_rccal_disable << 0) /**< Shifted mode rccal_disable for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCENRCCAL_rccal_enable (_RAC_IFADCCAL_IFADCENRCCAL_rccal_enable << 0) /**< Shifted mode rccal_enable for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCTUNERCCALMODE (0x1UL << 1) /**< IFADCTUNERCCALMODE */ +#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_SHIFT 1 /**< Shift value for RAC_IFADCTUNERCCALMODE */ +#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_MASK 0x2UL /**< Bit mask for RAC_IFADCTUNERCCALMODE */ +#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode 0x00000000UL /**< Mode SYmode for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode 0x00000001UL /**< Mode ADCmode for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT (_RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode (_RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode << 1) /**< Shifted mode SYmode for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode (_RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode << 1) /**< Shifted mode ADCmode for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCTUNERC_SHIFT 8 /**< Shift value for RAC_IFADCTUNERC */ +#define _RAC_IFADCCAL_IFADCTUNERC_MASK 0x1F00UL /**< Bit mask for RAC_IFADCTUNERC */ +#define _RAC_IFADCCAL_IFADCTUNERC_DEFAULT 0x0000000CUL /**< Mode DEFAULT for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCTUNERC_DEFAULT (_RAC_IFADCCAL_IFADCTUNERC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_IFADCCAL */ +#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_SHIFT 16 /**< Shift value for RAC_IFADCRCCALCOUNTERSTARTVAL*/ +#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_MASK 0xFF0000UL /**< Bit mask for RAC_IFADCRCCALCOUNTERSTARTVAL */ +#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */ +#define RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT (_RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IFADCCAL */ + +/* Bit fields for RAC IFADCSTATUS */ +#define _RAC_IFADCSTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_IFADCSTATUS */ +#define _RAC_IFADCSTATUS_MASK 0x00000001UL /**< Mask for RAC_IFADCSTATUS */ +#define RAC_IFADCSTATUS_IFADCRCCALOUT (0x1UL << 0) /**< IFADCRCCALOUT */ +#define _RAC_IFADCSTATUS_IFADCRCCALOUT_SHIFT 0 /**< Shift value for RAC_IFADCRCCALOUT */ +#define _RAC_IFADCSTATUS_IFADCRCCALOUT_MASK 0x1UL /**< Bit mask for RAC_IFADCRCCALOUT */ +#define _RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCSTATUS */ +#define _RAC_IFADCSTATUS_IFADCRCCALOUT_lo 0x00000000UL /**< Mode lo for RAC_IFADCSTATUS */ +#define _RAC_IFADCSTATUS_IFADCRCCALOUT_hi 0x00000001UL /**< Mode hi for RAC_IFADCSTATUS */ +#define RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT (_RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCSTATUS */ +#define RAC_IFADCSTATUS_IFADCRCCALOUT_lo (_RAC_IFADCSTATUS_IFADCRCCALOUT_lo << 0) /**< Shifted mode lo for RAC_IFADCSTATUS */ +#define RAC_IFADCSTATUS_IFADCRCCALOUT_hi (_RAC_IFADCSTATUS_IFADCRCCALOUT_hi << 0) /**< Shifted mode hi for RAC_IFADCSTATUS */ + +/* Bit fields for RAC LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_RESETVALUE 0x00000110UL /**< Default value for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_MASK 0x000001FFUL /**< Mask for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_SHIFT 0 /**< Shift value for RAC_LNAMIXCAPSEL0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_MASK 0x7UL /**< Bit mask for RAC_LNAMIXCAPSEL0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_SHIFT 3 /**< Shift value for RAC_LNAMIXMXRBIAS0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_MASK 0x18UL /**< Bit mask for RAC_LNAMIXMXRBIAS0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V 0x00000000UL /**< Mode bias_1V for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m 0x00000002UL /**< Mode bias_900m for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m 0x00000003UL /**< Mode bias_800m for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V << 3) /**< Shifted mode bias_1V for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused << 3) /**< Shifted mode unused for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m << 3) /**< Shifted mode bias_900m for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m << 3) /**< Shifted mode bias_800m for RAC_LNAMIXTRIM0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_SHIFT 5 /**< Shift value for RAC_LNAMIXVOUTADJ0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_MASK 0x1E0UL /**< Bit mask for RAC_LNAMIXVOUTADJ0 */ +#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */ +#define RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */ + +/* Bit fields for RAC LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_RESETVALUE 0x00000110UL /**< Default value for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_MASK 0x000001FFUL /**< Mask for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_SHIFT 0 /**< Shift value for RAC_LNAMIXCAPSEL1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_MASK 0x7UL /**< Bit mask for RAC_LNAMIXCAPSEL1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_SHIFT 3 /**< Shift value for RAC_LNAMIXMXRBIAS1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_MASK 0x18UL /**< Bit mask for RAC_LNAMIXMXRBIAS1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V 0x00000000UL /**< Mode bias_1V for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m 0x00000002UL /**< Mode bias_900m for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m 0x00000003UL /**< Mode bias_800m for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V << 3) /**< Shifted mode bias_1V for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused << 3) /**< Shifted mode unused for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m << 3) /**< Shifted mode bias_900m for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m << 3) /**< Shifted mode bias_800m for RAC_LNAMIXTRIM1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_SHIFT 5 /**< Shift value for RAC_LNAMIXVOUTADJ1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_MASK 0x1E0UL /**< Bit mask for RAC_LNAMIXVOUTADJ1 */ +#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */ +#define RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */ + +/* Bit fields for RAC LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_RESETVALUE 0x545033D0UL /**< Default value for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_MASK 0x7FF8FFF0UL /**< Mask for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_SHIFT 4 /**< Shift value for RAC_LNAMIXCURCTRL */ +#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_MASK 0x3F0UL /**< Bit mask for RAC_LNAMIXCURCTRL */ +#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT 0x0000003DUL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_SHIFT 10 /**< Shift value for RAC_LNAMIXHIGHCUR */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_MASK 0xC00UL /**< Bit mask for RAC_LNAMIXHIGHCUR */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA 0x00000000UL /**< Mode current_470uA for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA 0x00000001UL /**< Mode current_530uA for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused 0x00000002UL /**< Mode unused for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA 0x00000003UL /**< Mode current_590uA for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA << 10) /**< Shifted mode current_470uA for RAC_LNAMIXTRIM2*/ +#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA << 10) /**< Shifted mode current_530uA for RAC_LNAMIXTRIM2*/ +#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused << 10) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA << 10) /**< Shifted mode current_590uA for RAC_LNAMIXTRIM2*/ +#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_SHIFT 12 /**< Shift value for RAC_LNAMIXLOWCUR */ +#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_MASK 0xF000UL /**< Bit mask for RAC_LNAMIXLOWCUR */ +#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_SHIFT 19 /**< Shift value for RAC_LNAMIXNCASADJ0 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_MASK 0x180000UL /**< Bit mask for RAC_LNAMIXNCASADJ0 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V 0x00000000UL /**< Mode ncas_1V for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m 0x00000002UL /**< Mode ncas_950m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m 0x00000003UL /**< Mode ncas_900m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V << 19) /**< Shifted mode ncas_1V for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused << 19) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m << 19) /**< Shifted mode ncas_950m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m << 19) /**< Shifted mode ncas_900m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_SHIFT 21 /**< Shift value for RAC_LNAMIXPCASADJ0 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_MASK 0x600000UL /**< Bit mask for RAC_LNAMIXPCASADJ0 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m 0x00000000UL /**< Mode pcas_250m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m 0x00000002UL /**< Mode pcas_300m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m 0x00000003UL /**< Mode pcas_350m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m << 21) /**< Shifted mode pcas_250m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused << 21) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m << 21) /**< Shifted mode pcas_300m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m << 21) /**< Shifted mode pcas_350m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_SHIFT 23 /**< Shift value for RAC_LNAMIXTRIMVREG */ +#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_MASK 0x7800000UL /**< Bit mask for RAC_LNAMIXTRIMVREG */ +#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_SHIFT 27 /**< Shift value for RAC_LNAMIXNCASADJ1 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_MASK 0x18000000UL /**< Bit mask for RAC_LNAMIXNCASADJ1 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V 0x00000000UL /**< Mode ncas_1V for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m 0x00000002UL /**< Mode ncas_950m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m 0x00000003UL /**< Mode ncas_900m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V << 27) /**< Shifted mode ncas_1V for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused << 27) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m << 27) /**< Shifted mode ncas_950m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m << 27) /**< Shifted mode ncas_900m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_SHIFT 29 /**< Shift value for RAC_LNAMIXPCASADJ1 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_MASK 0x60000000UL /**< Bit mask for RAC_LNAMIXPCASADJ1 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m 0x00000000UL /**< Mode pcas_250m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m 0x00000002UL /**< Mode pcas_300m for RAC_LNAMIXTRIM2 */ +#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m 0x00000003UL /**< Mode pcas_350m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m << 29) /**< Shifted mode pcas_250m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused << 29) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m << 29) /**< Shifted mode pcas_300m for RAC_LNAMIXTRIM2 */ +#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m << 29) /**< Shifted mode pcas_350m for RAC_LNAMIXTRIM2 */ + +/* Bit fields for RAC LNAMIXTRIM3 */ +#define _RAC_LNAMIXTRIM3_RESETVALUE 0x00000208UL /**< Default value for RAC_LNAMIXTRIM3 */ +#define _RAC_LNAMIXTRIM3_MASK 0x00000FFFUL /**< Mask for RAC_LNAMIXTRIM3 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_SHIFT 0 /**< Shift value for RAC_LNAMIXIBIASADJ0 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_MASK 0x3FUL /**< Bit mask for RAC_LNAMIXIBIASADJ0 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM3 */ +#define RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT (_RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM3 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_SHIFT 6 /**< Shift value for RAC_LNAMIXIBIASADJ1 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_MASK 0xFC0UL /**< Bit mask for RAC_LNAMIXIBIASADJ1 */ +#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM3 */ +#define RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT (_RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM3 */ + +/* Bit fields for RAC LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_RESETVALUE 0x88082002UL /**< Default value for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_MASK 0xFF0FFF03UL /**< Mask for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_SHIFT 0 /**< Shift value for RAC_LNAMIXRFPKDBWSEL */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_MASK 0x3UL /**< Bit mask for RAC_LNAMIXRFPKDBWSEL */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_SHIFT 8 /**< Shift value for RAC_LNAMIXRFPKDCALCMLO */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_MASK 0x3F00UL /**< Bit mask for RAC_LNAMIXRFPKDCALCMLO */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_SHIFT 14 /**< Shift value for RAC_LNAMIXRFPKDCALCMHI */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_MASK 0xFC000UL /**< Bit mask for RAC_LNAMIXRFPKDCALCMHI */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_SHIFT 24 /**< Shift value for RAC_LNAMIXRFPKDTHRESHSELLO */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_MASK 0xF000000UL /**< Bit mask for RAC_LNAMIXRFPKDTHRESHSELLO */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_SHIFT 28 /**< Shift value for RAC_LNAMIXRFPKDTHRESHSELHI */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_MASK 0xF0000000UL /**< Bit mask for RAC_LNAMIXRFPKDTHRESHSELHI */ +#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */ +#define RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */ + +/* Bit fields for RAC LNAMIXCAL */ +#define _RAC_LNAMIXCAL_RESETVALUE 0x000007E0UL /**< Default value for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_MASK 0x000007FDUL /**< Mask for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALEN (0x1UL << 0) /**< LNAMIXCALPMOSEN */ +#define _RAC_LNAMIXCAL_LNAMIXCALEN_SHIFT 0 /**< Shift value for RAC_LNAMIXCALEN */ +#define _RAC_LNAMIXCAL_LNAMIXCALEN_MASK 0x1UL /**< Bit mask for RAC_LNAMIXCALEN */ +#define _RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable 0x00000000UL /**< Mode cal_disable for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable 0x00000001UL /**< Mode cal_enable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT (_RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable (_RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable << 0) /**< Shifted mode cal_disable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable (_RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable << 0) /**< Shifted mode cal_enable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALVMODE (0x1UL << 2) /**< LNAMIXCALVMODE */ +#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_SHIFT 2 /**< Shift value for RAC_LNAMIXCALVMODE */ +#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_MASK 0x4UL /**< Bit mask for RAC_LNAMIXCALVMODE */ +#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode 0x00000000UL /**< Mode current_mode for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode 0x00000001UL /**< Mode voltage_mode for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT (_RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode (_RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode << 2) /**< Shifted mode current_mode for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode (_RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode << 2) /**< Shifted mode voltage_mode for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL0 (0x1UL << 3) /**< LNAMIXENIRCAL0 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_SHIFT 3 /**< Shift value for RAC_LNAMIXENIRCAL0 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENIRCAL0 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable << 3) /**< Shifted mode disable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable << 3) /**< Shifted mode enable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL1 (0x1UL << 4) /**< LNAMIXENIRCAL1 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_SHIFT 4 /**< Shift value for RAC_LNAMIXENIRCAL1 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_MASK 0x10UL /**< Bit mask for RAC_LNAMIXENIRCAL1 */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable << 4) /**< Shifted mode disable for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable << 4) /**< Shifted mode enable for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_SHIFT 5 /**< Shift value for RAC_LNAMIXIRCALAMP0 */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_MASK 0xE0UL /**< Bit mask for RAC_LNAMIXIRCALAMP0 */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT (_RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_SHIFT 8 /**< Shift value for RAC_LNAMIXIRCALAMP1 */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_MASK 0x700UL /**< Bit mask for RAC_LNAMIXIRCALAMP1 */ +#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_LNAMIXCAL */ +#define RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT (_RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */ + +/* Bit fields for RAC LNAMIXEN */ +#define _RAC_LNAMIXEN_RESETVALUE 0x00000000UL /**< Default value for RAC_LNAMIXEN */ +#define _RAC_LNAMIXEN_MASK 0x00000008UL /**< Mask for RAC_LNAMIXEN */ +#define RAC_LNAMIXEN_LNAMIXENLDO (0x1UL << 3) /**< LNAMIXENLDO */ +#define _RAC_LNAMIXEN_LNAMIXENLDO_SHIFT 3 /**< Shift value for RAC_LNAMIXENLDO */ +#define _RAC_LNAMIXEN_LNAMIXENLDO_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENLDO */ +#define _RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXEN */ +#define _RAC_LNAMIXEN_LNAMIXENLDO_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXEN */ +#define _RAC_LNAMIXEN_LNAMIXENLDO_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXEN */ +#define RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT (_RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXEN */ +#define RAC_LNAMIXEN_LNAMIXENLDO_disable (_RAC_LNAMIXEN_LNAMIXENLDO_disable << 3) /**< Shifted mode disable for RAC_LNAMIXEN */ +#define RAC_LNAMIXEN_LNAMIXENLDO_enable (_RAC_LNAMIXEN_LNAMIXENLDO_enable << 3) /**< Shifted mode enable for RAC_LNAMIXEN */ + +/* Bit fields for RAC PRECTRL */ +#define _RAC_PRECTRL_RESETVALUE 0x00000026UL /**< Default value for RAC_PRECTRL */ +#define _RAC_PRECTRL_MASK 0x0000003FUL /**< Mask for RAC_PRECTRL */ +#define RAC_PRECTRL_PREBYPFORCE (0x1UL << 0) /**< PREBYPFORCE */ +#define _RAC_PRECTRL_PREBYPFORCE_SHIFT 0 /**< Shift value for RAC_PREBYPFORCE */ +#define _RAC_PRECTRL_PREBYPFORCE_MASK 0x1UL /**< Bit mask for RAC_PREBYPFORCE */ +#define _RAC_PRECTRL_PREBYPFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREBYPFORCE_not_forced 0x00000000UL /**< Mode not_forced for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREBYPFORCE_forced 0x00000001UL /**< Mode forced for RAC_PRECTRL */ +#define RAC_PRECTRL_PREBYPFORCE_DEFAULT (_RAC_PRECTRL_PREBYPFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PRECTRL */ +#define RAC_PRECTRL_PREBYPFORCE_not_forced (_RAC_PRECTRL_PREBYPFORCE_not_forced << 0) /**< Shifted mode not_forced for RAC_PRECTRL */ +#define RAC_PRECTRL_PREBYPFORCE_forced (_RAC_PRECTRL_PREBYPFORCE_forced << 0) /**< Shifted mode forced for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_SHIFT 1 /**< Shift value for RAC_PREREGTRIM */ +#define _RAC_PRECTRL_PREREGTRIM_MASK 0xEUL /**< Bit mask for RAC_PREREGTRIM */ +#define _RAC_PRECTRL_PREREGTRIM_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p61 0x00000000UL /**< Mode v1p61 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p68 0x00000001UL /**< Mode v1p68 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p74 0x00000002UL /**< Mode v1p74 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p80 0x00000003UL /**< Mode v1p80 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p86 0x00000004UL /**< Mode v1p86 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p91 0x00000005UL /**< Mode v1p91 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v1p96 0x00000006UL /**< Mode v1p96 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREREGTRIM_v2p00 0x00000007UL /**< Mode v2p00 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_DEFAULT (_RAC_PRECTRL_PREREGTRIM_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p61 (_RAC_PRECTRL_PREREGTRIM_v1p61 << 1) /**< Shifted mode v1p61 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p68 (_RAC_PRECTRL_PREREGTRIM_v1p68 << 1) /**< Shifted mode v1p68 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p74 (_RAC_PRECTRL_PREREGTRIM_v1p74 << 1) /**< Shifted mode v1p74 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p80 (_RAC_PRECTRL_PREREGTRIM_v1p80 << 1) /**< Shifted mode v1p80 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p86 (_RAC_PRECTRL_PREREGTRIM_v1p86 << 1) /**< Shifted mode v1p86 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p91 (_RAC_PRECTRL_PREREGTRIM_v1p91 << 1) /**< Shifted mode v1p91 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v1p96 (_RAC_PRECTRL_PREREGTRIM_v1p96 << 1) /**< Shifted mode v1p96 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREREGTRIM_v2p00 (_RAC_PRECTRL_PREREGTRIM_v2p00 << 1) /**< Shifted mode v2p00 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREVREFTRIM_SHIFT 4 /**< Shift value for RAC_PREVREFTRIM */ +#define _RAC_PRECTRL_PREVREFTRIM_MASK 0x30UL /**< Bit mask for RAC_PREVREFTRIM */ +#define _RAC_PRECTRL_PREVREFTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREVREFTRIM_v0p675 0x00000000UL /**< Mode v0p675 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREVREFTRIM_v0p688 0x00000001UL /**< Mode v0p688 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREVREFTRIM_v0p700 0x00000002UL /**< Mode v0p700 for RAC_PRECTRL */ +#define _RAC_PRECTRL_PREVREFTRIM_v0p713 0x00000003UL /**< Mode v0p713 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREVREFTRIM_DEFAULT (_RAC_PRECTRL_PREVREFTRIM_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PRECTRL */ +#define RAC_PRECTRL_PREVREFTRIM_v0p675 (_RAC_PRECTRL_PREVREFTRIM_v0p675 << 4) /**< Shifted mode v0p675 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREVREFTRIM_v0p688 (_RAC_PRECTRL_PREVREFTRIM_v0p688 << 4) /**< Shifted mode v0p688 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREVREFTRIM_v0p700 (_RAC_PRECTRL_PREVREFTRIM_v0p700 << 4) /**< Shifted mode v0p700 for RAC_PRECTRL */ +#define RAC_PRECTRL_PREVREFTRIM_v0p713 (_RAC_PRECTRL_PREVREFTRIM_v0p713 << 4) /**< Shifted mode v0p713 for RAC_PRECTRL */ + +/* Bit fields for RAC PATRIM0 */ +#define _RAC_PATRIM0_RESETVALUE 0x00000077UL /**< Default value for RAC_PATRIM0 */ +#define _RAC_PATRIM0_MASK 0x0101FFFFUL /**< Mask for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMBIASN */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_MASK 0xFUL /**< Bit mask for RAC_TX0DBMTRIMBIASN */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m 0x00000000UL /**< Mode v_367m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m 0x00000001UL /**< Mode v_380m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m 0x00000002UL /**< Mode v_393m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m 0x00000003UL /**< Mode v_406m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m 0x00000004UL /**< Mode v_419m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m 0x00000005UL /**< Mode v_432m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m 0x00000006UL /**< Mode v_445m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m 0x00000007UL /**< Mode v_default_458m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m 0x00000008UL /**< Mode v_483m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m 0x00000009UL /**< Mode v_496m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m 0x0000000AUL /**< Mode v_509m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m 0x0000000BUL /**< Mode v_522m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m 0x0000000CUL /**< Mode v_535m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m 0x0000000DUL /**< Mode v_548m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m 0x0000000EUL /**< Mode v_561m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m 0x0000000FUL /**< Mode v_574m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT (_RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m << 0) /**< Shifted mode v_367m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m << 0) /**< Shifted mode v_380m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m << 0) /**< Shifted mode v_393m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m << 0) /**< Shifted mode v_406m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m << 0) /**< Shifted mode v_419m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m << 0) /**< Shifted mode v_432m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m << 0) /**< Shifted mode v_445m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m << 0) /**< Shifted mode v_default_458m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m << 0) /**< Shifted mode v_483m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m << 0) /**< Shifted mode v_496m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m << 0) /**< Shifted mode v_509m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m << 0) /**< Shifted mode v_522m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m << 0) /**< Shifted mode v_535m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m << 0) /**< Shifted mode v_548m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m << 0) /**< Shifted mode v_561m for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m << 0) /**< Shifted mode v_574m for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMBIASP */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_MASK 0xF0UL /**< Bit mask for RAC_TX0DBMTRIMBIASP */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 0x00000000UL /**< Mode v_1p186 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 0x00000001UL /**< Mode v_1p173 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 0x00000002UL /**< Mode v_1p16 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 0x00000003UL /**< Mode v_1p147 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 0x00000004UL /**< Mode v_1p134 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 0x00000005UL /**< Mode v_1p121 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 0x00000006UL /**< Mode v_1p108 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 0x00000007UL /**< Mode v_default_1p095 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 0x00000008UL /**< Mode v_1p083 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 0x00000009UL /**< Mode v_1p07 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 0x0000000AUL /**< Mode v_1p057 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 0x0000000BUL /**< Mode v_1p044 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 0x0000000CUL /**< Mode v_1p031 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 0x0000000DUL /**< Mode v_1p019 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 0x0000000EUL /**< Mode v_1p006 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 0x0000000FUL /**< Mode v_0p993 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT (_RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 << 4) /**< Shifted mode v_1p186 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 << 4) /**< Shifted mode v_1p173 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 << 4) /**< Shifted mode v_1p16 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 << 4) /**< Shifted mode v_1p147 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 << 4) /**< Shifted mode v_1p134 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 << 4) /**< Shifted mode v_1p121 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 << 4) /**< Shifted mode v_1p108 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 << 4) /**< Shifted mode v_default_1p095 for RAC_PATRIM0*/ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 << 4) /**< Shifted mode v_1p083 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 << 4) /**< Shifted mode v_1p07 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 << 4) /**< Shifted mode v_1p057 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 << 4) /**< Shifted mode v_1p044 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 << 4) /**< Shifted mode v_1p031 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 << 4) /**< Shifted mode v_1p019 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 << 4) /**< Shifted mode v_1p006 for RAC_PATRIM0 */ +#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 << 4) /**< Shifted mode v_0p993 for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TXPAAMPCTRL_SHIFT 8 /**< Shift value for RAC_TXPAAMPCTRL */ +#define _RAC_PATRIM0_TXPAAMPCTRL_MASK 0xFF00UL /**< Bit mask for RAC_TXPAAMPCTRL */ +#define _RAC_PATRIM0_TXPAAMPCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_TXPAAMPCTRL_DEFAULT (_RAC_PATRIM0_TXPAAMPCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_TXPABYPASSREG (0x1UL << 16) /**< TXPABYPASSREG */ +#define _RAC_PATRIM0_TXPABYPASSREG_SHIFT 16 /**< Shift value for RAC_TXPABYPASSREG */ +#define _RAC_PATRIM0_TXPABYPASSREG_MASK 0x10000UL /**< Bit mask for RAC_TXPABYPASSREG */ +#define _RAC_PATRIM0_TXPABYPASSREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TXPABYPASSREG_not_bypass 0x00000000UL /**< Mode not_bypass for RAC_PATRIM0 */ +#define _RAC_PATRIM0_TXPABYPASSREG_bypass 0x00000001UL /**< Mode bypass for RAC_PATRIM0 */ +#define RAC_PATRIM0_TXPABYPASSREG_DEFAULT (_RAC_PATRIM0_TXPABYPASSREG_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_TXPABYPASSREG_not_bypass (_RAC_PATRIM0_TXPABYPASSREG_not_bypass << 16) /**< Shifted mode not_bypass for RAC_PATRIM0 */ +#define RAC_PATRIM0_TXPABYPASSREG_bypass (_RAC_PATRIM0_TXPABYPASSREG_bypass << 16) /**< Shifted mode bypass for RAC_PATRIM0 */ +#define RAC_PATRIM0_ENAMPCTRLREG (0x1UL << 24) /**< ENAMPCTRLREG */ +#define _RAC_PATRIM0_ENAMPCTRLREG_SHIFT 24 /**< Shift value for RAC_ENAMPCTRLREG */ +#define _RAC_PATRIM0_ENAMPCTRLREG_MASK 0x1000000UL /**< Bit mask for RAC_ENAMPCTRLREG */ +#define _RAC_PATRIM0_ENAMPCTRLREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */ +#define RAC_PATRIM0_ENAMPCTRLREG_DEFAULT (_RAC_PATRIM0_ENAMPCTRLREG_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM0 */ + +/* Bit fields for RAC PATRIM1 */ +#define _RAC_PATRIM1_RESETVALUE 0x03034373UL /**< Default value for RAC_PATRIM1 */ +#define _RAC_PATRIM1_MASK 0x0777F3F7UL /**< Mask for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGIBCORE*/ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_MASK 0x3UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGIBCORE */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u 0x00000000UL /**< Mode i_4u for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u 0x00000001UL /**< Mode i_5u for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u 0x00000002UL /**< Mode i_6u for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u 0x00000003UL /**< Mode i_default_7u for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u << 0) /**< Shifted mode i_4u for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u << 0) /**< Shifted mode i_5u for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u << 0) /**< Shifted mode i_6u for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u << 0) /**< Shifted mode i_default_7u for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR (0x1UL << 2) /**< TX0DBMTRIMPREDRVREGPSR */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_SHIFT 2 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGPSR */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_MASK 0x4UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGPSR */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable 0x00000000UL /**< Mode disable for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable 0x00000001UL /**< Mode enable for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable << 2) /**< Shifted mode disable for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable << 2) /**< Shifted mode enable for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGIBNDIO*/ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_MASK 0xF0UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGIBNDIO */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 0x00000000UL /**< Mode vreg_1p127 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 0x00000001UL /**< Mode vreg_1p171 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 0x00000002UL /**< Mode vreg_1p209 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 0x00000003UL /**< Mode vreg_1p244 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 0x00000004UL /**< Mode vreg_1p275 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 0x00000005UL /**< Mode vreg_1p305 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 0x00000006UL /**< Mode vreg_1p335 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 0x00000007UL /**< Mode vreg_default_1p362 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 0x00000008UL /**< Mode vreg_1p388 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 0x00000009UL /**< Mode vreg_1p414 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 0x0000000AUL /**< Mode vreg_1p439 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 0x0000000BUL /**< Mode vreg_1p463 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 0x0000000CUL /**< Mode vreg_1p486 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 0x0000000DUL /**< Mode vreg_1p509 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 0x0000000EUL /**< Mode vreg_1p532 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 0x0000000FUL /**< Mode vreg_1p555 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 << 4) /**< Shifted mode vreg_1p127 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 << 4) /**< Shifted mode vreg_1p171 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 << 4) /**< Shifted mode vreg_1p209 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 << 4) /**< Shifted mode vreg_1p244 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 << 4) /**< Shifted mode vreg_1p275 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 << 4) /**< Shifted mode vreg_1p305 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 << 4) /**< Shifted mode vreg_1p335 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 << 4) /**< Shifted mode vreg_default_1p362 for RAC_PATRIM1*/ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 << 4) /**< Shifted mode vreg_1p388 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 << 4) /**< Shifted mode vreg_1p414 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 << 4) /**< Shifted mode vreg_1p439 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 << 4) /**< Shifted mode vreg_1p463 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 << 4) /**< Shifted mode vreg_1p486 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 << 4) /**< Shifted mode vreg_1p509 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 << 4) /**< Shifted mode vreg_1p532 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 << 4) /**< Shifted mode vreg_1p555 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_SHIFT 8 /**< Shift value for RAC_TX0DBMTRIMPREDRVSLOPE */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_MASK 0x300UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVSLOPE */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 0x00000000UL /**< Mode slope_0 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 0x00000001UL /**< Mode slope_1 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 0x00000002UL /**< Mode slope_2 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max 0x00000003UL /**< Mode slope_default_max for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 << 8) /**< Shifted mode slope_0 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 << 8) /**< Shifted mode slope_1 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 << 8) /**< Shifted mode slope_2 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max << 8) /**< Shifted mode slope_default_max for RAC_PATRIM1*/ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_SHIFT 12 /**< Shift value for RAC_TX0DBMTRIMREGFB */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_MASK 0xF000UL /**< Bit mask for RAC_TX0DBMTRIMREGFB */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 0x00000000UL /**< Mode v_1p976 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 0x00000001UL /**< Mode v_1p878 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 0x00000002UL /**< Mode v_1p788 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 0x00000003UL /**< Mode v_1p707 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 0x00000004UL /**< Mode v_default_1p633 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 0x00000005UL /**< Mode v_1p565 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 0x00000006UL /**< Mode v_1p503 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 0x00000007UL /**< Mode v_1p445 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 0x00000008UL /**< Mode v_1p392 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 0x00000009UL /**< Mode v_1p342 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 0x0000000AUL /**< Mode v_1p296 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 0x0000000BUL /**< Mode v_1p253 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 0x0000000CUL /**< Mode v_1p213 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 0x0000000DUL /**< Mode v_1p175 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 0x0000000EUL /**< Mode v_1p14 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 0x0000000FUL /**< Mode v_1p106 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 << 12) /**< Shifted mode v_1p976 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 << 12) /**< Shifted mode v_1p878 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 << 12) /**< Shifted mode v_1p788 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 << 12) /**< Shifted mode v_1p707 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 << 12) /**< Shifted mode v_default_1p633 for RAC_PATRIM1*/ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 << 12) /**< Shifted mode v_1p565 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 << 12) /**< Shifted mode v_1p503 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 << 12) /**< Shifted mode v_1p445 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 << 12) /**< Shifted mode v_1p392 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 << 12) /**< Shifted mode v_1p342 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 << 12) /**< Shifted mode v_1p296 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 << 12) /**< Shifted mode v_1p253 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 << 12) /**< Shifted mode v_1p213 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 << 12) /**< Shifted mode v_1p175 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 << 12) /**< Shifted mode v_1p14 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 << 12) /**< Shifted mode v_1p106 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_SHIFT 16 /**< Shift value for RAC_TX0DBMTRIMREGVREF */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_MASK 0x70000UL /**< Bit mask for RAC_TX0DBMTRIMREGVREF */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 0x00000000UL /**< Mode v_1p572 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 0x00000001UL /**< Mode v_1p593 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 0x00000002UL /**< Mode v_1p613 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 0x00000003UL /**< Mode v_default_1p634 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 0x00000004UL /**< Mode v_1p654 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 0x00000005UL /**< Mode v_1p674 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 0x00000006UL /**< Mode v_1p694 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 0x00000007UL /**< Mode v_1p714 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 << 16) /**< Shifted mode v_1p572 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 << 16) /**< Shifted mode v_1p593 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 << 16) /**< Shifted mode v_1p613 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 << 16) /**< Shifted mode v_default_1p634 for RAC_PATRIM1*/ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 << 16) /**< Shifted mode v_1p654 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 << 16) /**< Shifted mode v_1p674 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 << 16) /**< Shifted mode v_1p694 for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 << 16) /**< Shifted mode v_1p714 for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_SHIFT 20 /**< Shift value for RAC_TX0DBMTRIMTAPCAP100F */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_MASK 0x700000UL /**< Bit mask for RAC_TX0DBMTRIMTAPCAP100F */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f 0x00000000UL /**< Mode Ctap_plus_0f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f 0x00000001UL /**< Mode Ctap_plus_100f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f 0x00000002UL /**< Mode Ctap_plus_200f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f 0x00000003UL /**< Mode Ctap_plus_300f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f 0x00000004UL /**< Mode Ctap_plus_400f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f 0x00000005UL /**< Mode Ctap_plus_500f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f 0x00000006UL /**< Mode Ctap_plus_600f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f 0x00000007UL /**< Mode Ctap_plus_700f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f << 20) /**< Shifted mode Ctap_plus_0f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f << 20) /**< Shifted mode Ctap_plus_100f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f << 20) /**< Shifted mode Ctap_plus_200f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f << 20) /**< Shifted mode Ctap_plus_300f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f << 20) /**< Shifted mode Ctap_plus_400f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f << 20) /**< Shifted mode Ctap_plus_500f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f << 20) /**< Shifted mode Ctap_plus_600f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f << 20) /**< Shifted mode Ctap_plus_700f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_SHIFT 24 /**< Shift value for RAC_TX0DBMTRIMTAPCAP200F */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_MASK 0x7000000UL /**< Bit mask for RAC_TX0DBMTRIMTAPCAP200F */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f 0x00000000UL /**< Mode Ctap_plus_0f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f 0x00000001UL /**< Mode Ctap_plus_200f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f 0x00000002UL /**< Mode Ctap_plus_400f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f 0x00000003UL /**< Mode Ctap_plus_600f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f 0x00000004UL /**< Mode Ctap_plus_800f for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p 0x00000005UL /**< Mode Ctap_plus_1p for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p 0x00000006UL /**< Mode Ctap_plus_1p2p for RAC_PATRIM1 */ +#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p 0x00000007UL /**< Mode Ctap_plus_1p4p for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f << 24) /**< Shifted mode Ctap_plus_0f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f << 24) /**< Shifted mode Ctap_plus_200f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f << 24) /**< Shifted mode Ctap_plus_400f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f << 24) /**< Shifted mode Ctap_plus_600f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f << 24) /**< Shifted mode Ctap_plus_800f for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p << 24) /**< Shifted mode Ctap_plus_1p for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p << 24) /**< Shifted mode Ctap_plus_1p2p for RAC_PATRIM1 */ +#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p << 24) /**< Shifted mode Ctap_plus_1p4p for RAC_PATRIM1 */ + +/* Bit fields for RAC PATRIM2 */ +#define _RAC_PATRIM2_RESETVALUE 0x00000000UL /**< Default value for RAC_PATRIM2 */ +#define _RAC_PATRIM2_MASK 0x00007777UL /**< Mask for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMDUTYCYN */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_MASK 0x7UL /**< Bit mask for RAC_TX0DBMTRIMDUTYCYN */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct 0x00000000UL /**< Mode up_0pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct 0x00000001UL /**< Mode up_1pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct 0x00000002UL /**< Mode up_2pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct 0x00000003UL /**< Mode up_3pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct 0x00000004UL /**< Mode up_4pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct 0x00000005UL /**< Mode up_5pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct 0x00000006UL /**< Mode up_6pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct << 0) /**< Shifted mode up_0pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct << 0) /**< Shifted mode up_1pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct << 0) /**< Shifted mode up_2pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct << 0) /**< Shifted mode up_3pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct << 0) /**< Shifted mode up_4pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct << 0) /**< Shifted mode up_5pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct << 0) /**< Shifted mode up_6pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na << 0) /**< Shifted mode na for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMDUTYCYP */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_MASK 0x70UL /**< Bit mask for RAC_TX0DBMTRIMDUTYCYP */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct 0x00000000UL /**< Mode dn_0pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct 0x00000001UL /**< Mode dn_1pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct 0x00000002UL /**< Mode dn_2pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct 0x00000003UL /**< Mode dn_3pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct 0x00000004UL /**< Mode dn_4pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct 0x00000005UL /**< Mode dn_5pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct 0x00000006UL /**< Mode dn_6pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct << 4) /**< Shifted mode dn_0pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct << 4) /**< Shifted mode dn_1pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct << 4) /**< Shifted mode dn_2pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct << 4) /**< Shifted mode dn_3pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct << 4) /**< Shifted mode dn_4pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct << 4) /**< Shifted mode dn_5pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct << 4) /**< Shifted mode dn_6pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na << 4) /**< Shifted mode na for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_SHIFT 8 /**< Shift value for RAC_TXPATRIM10DBMDUTYCYN */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_MASK 0x700UL /**< Bit mask for RAC_TXPATRIM10DBMDUTYCYN */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct 0x00000000UL /**< Mode up_0pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct 0x00000001UL /**< Mode up_1pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct 0x00000002UL /**< Mode up_2pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct 0x00000003UL /**< Mode up_3pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct 0x00000004UL /**< Mode up_4pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct 0x00000005UL /**< Mode up_5pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct 0x00000006UL /**< Mode up_6pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct << 8) /**< Shifted mode up_0pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct << 8) /**< Shifted mode up_1pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct << 8) /**< Shifted mode up_2pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct << 8) /**< Shifted mode up_3pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct << 8) /**< Shifted mode up_4pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct << 8) /**< Shifted mode up_5pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct << 8) /**< Shifted mode up_6pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na << 8) /**< Shifted mode na for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_SHIFT 12 /**< Shift value for RAC_TXPATRIM10DBMDUTYCYP */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_MASK 0x7000UL /**< Bit mask for RAC_TXPATRIM10DBMDUTYCYP */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct 0x00000000UL /**< Mode dn_0pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct 0x00000001UL /**< Mode dn_1pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct 0x00000002UL /**< Mode dn_2pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct 0x00000003UL /**< Mode dn_3pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct 0x00000004UL /**< Mode dn_4pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct 0x00000005UL /**< Mode dn_5pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct 0x00000006UL /**< Mode dn_6pct for RAC_PATRIM2 */ +#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct << 12) /**< Shifted mode dn_0pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct << 12) /**< Shifted mode dn_1pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct << 12) /**< Shifted mode dn_2pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct << 12) /**< Shifted mode dn_3pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct << 12) /**< Shifted mode dn_4pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct << 12) /**< Shifted mode dn_5pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct << 12) /**< Shifted mode dn_6pct for RAC_PATRIM2 */ +#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na << 12) /**< Shifted mode na for RAC_PATRIM2 */ + +/* Bit fields for RAC PATRIM3 */ +#define _RAC_PATRIM3_RESETVALUE 0x008D33AAUL /**< Default value for RAC_PATRIM3 */ +#define _RAC_PATRIM3_MASK 0x00FF73FEUL /**< Mask for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG (0x1UL << 1) /**< TXPATRIMBLEEDAUTOREG */ +#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_SHIFT 1 /**< Shift value for RAC_TXPATRIMBLEEDAUTOREG */ +#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_MASK 0x2UL /**< Bit mask for RAC_TXPATRIMBLEEDAUTOREG */ +#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic 0x00000000UL /**< Mode not_automatic for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic 0x00000001UL /**< Mode automatic for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic << 1) /**< Shifted mode not_automatic for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic << 1) /**< Shifted mode automatic for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_SHIFT 2 /**< Shift value for RAC_TXPATRIMIBIASMASTER */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_MASK 0xCUL /**< Bit mask for RAC_TXPATRIMIBIASMASTER */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u 0x00000000UL /**< Mode Ibias_is_45u for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u 0x00000001UL /**< Mode Ibias_is_47p5u for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u 0x00000002UL /**< Mode Ibias_is_50u for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u 0x00000003UL /**< Mode Ibias_is_52p5u for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT (_RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u << 2) /**< Shifted mode Ibias_is_45u for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u << 2) /**< Shifted mode Ibias_is_47p5u for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u << 2) /**< Shifted mode Ibias_is_50u for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u << 2) /**< Shifted mode Ibias_is_52p5u for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_SHIFT 4 /**< Shift value for RAC_TXPATRIMPREDRVREGFB */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_MASK 0x30UL /**< Bit mask for RAC_TXPATRIMPREDRVREGFB */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 0x00000000UL /**< Mode vreg_1p22 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 0x00000001UL /**< Mode vreg_1p28 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 0x00000002UL /**< Mode vreg_1p35 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 0x00000003UL /**< Mode vreg_1p44 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 << 4) /**< Shifted mode vreg_1p22 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 << 4) /**< Shifted mode vreg_1p28 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 << 4) /**< Shifted mode vreg_1p35 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 << 4) /**< Shifted mode vreg_1p44 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT (0x1UL << 6) /**< TXPATRIMPREDRVREGFBKATT */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_SHIFT 6 /**< Shift value for RAC_TXPATRIMPREDRVREGFBKATT */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_MASK 0x40UL /**< Bit mask for RAC_TXPATRIMPREDRVREGFBKATT */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw 0x00000000UL /**< Mode less_bw for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw 0x00000001UL /**< Mode more_bw for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw << 6) /**< Shifted mode less_bw for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw << 6) /**< Shifted mode more_bw for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR (0x1UL << 7) /**< TXPATRIMPREDRVREGPSR */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_SHIFT 7 /**< Shift value for RAC_TXPATRIMPREDRVREGPSR */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_MASK 0x80UL /**< Bit mask for RAC_TXPATRIMPREDRVREGPSR */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr 0x00000000UL /**< Mode low_psr for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr 0x00000001UL /**< Mode high_psr for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr << 7) /**< Shifted mode low_psr for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr << 7) /**< Shifted mode high_psr for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_SHIFT 8 /**< Shift value for RAC_TXPATRIMPREDRVREGSLICES */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_MASK 0x300UL /**< Bit mask for RAC_TXPATRIMPREDRVREGSLICES */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA 0x00000000UL /**< Mode iload_7p5mA for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA 0x00000001UL /**< Mode iload_15mA for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA 0x00000002UL /**< Mode iload_22p5mA for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA 0x00000003UL /**< Mode iload_30mA for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA << 8) /**< Shifted mode iload_7p5mA for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA << 8) /**< Shifted mode iload_15mA for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA << 8) /**< Shifted mode iload_22p5mA for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA << 8) /**< Shifted mode iload_30mA for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_SHIFT 12 /**< Shift value for RAC_TXPATRIMPREDRVREGVREF */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_MASK 0x7000UL /**< Bit mask for RAC_TXPATRIMPREDRVREGVREF */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 0x00000000UL /**< Mode vref_0p675 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 0x00000001UL /**< Mode vref_0p700 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 0x00000002UL /**< Mode vref_0p725 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 0x00000003UL /**< Mode vref_0p750 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 0x00000004UL /**< Mode vref_0p775 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 0x00000005UL /**< Mode vref_0p800 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 0x00000006UL /**< Mode vref_0p825 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 0x00000007UL /**< Mode vref_0p850 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 << 12) /**< Shifted mode vref_0p675 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 << 12) /**< Shifted mode vref_0p700 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 << 12) /**< Shifted mode vref_0p725 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 << 12) /**< Shifted mode vref_0p750 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 << 12) /**< Shifted mode vref_0p775 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 << 12) /**< Shifted mode vref_0p800 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 << 12) /**< Shifted mode vref_0p825 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 << 12) /**< Shifted mode vref_0p850 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_SHIFT 16 /**< Shift value for RAC_TXPATRIMREGFB */ +#define _RAC_PATRIM3_TXPATRIMREGFB_MASK 0x70000UL /**< Bit mask for RAC_TXPATRIMREGFB */ +#define _RAC_PATRIM3_TXPATRIMREGFB_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 0x00000000UL /**< Mode vreg_1p678 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 0x00000001UL /**< Mode vreg_1p735 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 0x00000002UL /**< Mode vreg_1p801 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 0x00000003UL /**< Mode vreg_1p875 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 0x00000004UL /**< Mode vreg_3p00 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 0x00000005UL /**< Mode vreg_3p14 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 0x00000006UL /**< Mode vreg_3p3 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 0x00000007UL /**< Mode vreg_3p477 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_DEFAULT (_RAC_PATRIM3_TXPATRIMREGFB_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 << 16) /**< Shifted mode vreg_1p678 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 << 16) /**< Shifted mode vreg_1p735 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 << 16) /**< Shifted mode vreg_1p801 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 << 16) /**< Shifted mode vreg_1p875 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 << 16) /**< Shifted mode vreg_3p00 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 << 16) /**< Shifted mode vreg_3p14 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 << 16) /**< Shifted mode vreg_3p3 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 << 16) /**< Shifted mode vreg_3p477 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGPSR (0x1UL << 19) /**< TXPATRIMREGPSR */ +#define _RAC_PATRIM3_TXPATRIMREGPSR_SHIFT 19 /**< Shift value for RAC_TXPATRIMREGPSR */ +#define _RAC_PATRIM3_TXPATRIMREGPSR_MASK 0x80000UL /**< Bit mask for RAC_TXPATRIMREGPSR */ +#define _RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGPSR_low_psr 0x00000000UL /**< Mode low_psr for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGPSR_high_psr 0x00000001UL /**< Mode high_psr for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT (_RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGPSR_low_psr (_RAC_PATRIM3_TXPATRIMREGPSR_low_psr << 19) /**< Shifted mode low_psr for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGPSR_high_psr (_RAC_PATRIM3_TXPATRIMREGPSR_high_psr << 19) /**< Shifted mode high_psr for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_SHIFT 20 /**< Shift value for RAC_TXPATRIMREGVREF */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_MASK 0xF00000UL /**< Bit mask for RAC_TXPATRIMREGVREF */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 0x00000000UL /**< Mode vref_0p651 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 0x00000001UL /**< Mode vref_0p663 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 0x00000002UL /**< Mode vref_0p676 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 0x00000003UL /**< Mode vref_0p688 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 0x00000004UL /**< Mode vref_0p701 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 0x00000005UL /**< Mode vref_0p713 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 0x00000006UL /**< Mode vref_0p726 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 0x00000007UL /**< Mode vref_0p738 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 0x00000008UL /**< Mode vref_0p751 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 0x00000009UL /**< Mode vref_0p763 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 0x0000000AUL /**< Mode vref_0p776 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 0x0000000BUL /**< Mode vref_0p788 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 0x0000000CUL /**< Mode vref_0p801 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 0x0000000DUL /**< Mode vref_0p813 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 0x0000000EUL /**< Mode vref_0p826 for RAC_PATRIM3 */ +#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 0x0000000FUL /**< Mode vref_0p838 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT (_RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 << 20) /**< Shifted mode vref_0p651 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 << 20) /**< Shifted mode vref_0p663 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 << 20) /**< Shifted mode vref_0p676 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 << 20) /**< Shifted mode vref_0p688 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 << 20) /**< Shifted mode vref_0p701 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 << 20) /**< Shifted mode vref_0p713 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 << 20) /**< Shifted mode vref_0p726 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 << 20) /**< Shifted mode vref_0p738 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 << 20) /**< Shifted mode vref_0p751 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 << 20) /**< Shifted mode vref_0p763 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 << 20) /**< Shifted mode vref_0p776 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 << 20) /**< Shifted mode vref_0p788 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 << 20) /**< Shifted mode vref_0p801 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 << 20) /**< Shifted mode vref_0p813 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 << 20) /**< Shifted mode vref_0p826 for RAC_PATRIM3 */ +#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 << 20) /**< Shifted mode vref_0p838 for RAC_PATRIM3 */ + +/* Bit fields for RAC PATRIM4 */ +#define _RAC_PATRIM4_RESETVALUE 0x00006000UL /**< Default value for RAC_PATRIM4 */ +#define _RAC_PATRIM4_MASK 0x03FFFFFFUL /**< Mask for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_SHIFT 0 /**< Shift value for RAC_TXPATRIM10DBMCTAP */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_MASK 0xFUL /**< Bit mask for RAC_TXPATRIM10DBMCTAP */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 0x00000000UL /**< Mode ctap_trim_0 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 0x00000001UL /**< Mode ctap_trim_1 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 0x00000002UL /**< Mode ctap_trim_2 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 0x00000003UL /**< Mode ctap_trim_3 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 0x00000004UL /**< Mode ctap_trim_4 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 0x00000005UL /**< Mode ctap_trim_5 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 0x00000006UL /**< Mode ctap_trim_6 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 0x00000007UL /**< Mode ctap_trim_7 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 0x00000008UL /**< Mode ctap_trim_8 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 << 0) /**< Shifted mode ctap_trim_0 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 << 0) /**< Shifted mode ctap_trim_1 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 << 0) /**< Shifted mode ctap_trim_2 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 << 0) /**< Shifted mode ctap_trim_3 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 << 0) /**< Shifted mode ctap_trim_4 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 << 0) /**< Shifted mode ctap_trim_5 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 << 0) /**< Shifted mode ctap_trim_6 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 << 0) /**< Shifted mode ctap_trim_7 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 << 0) /**< Shifted mode ctap_trim_8 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_SHIFT 4 /**< Shift value for RAC_TXPATRIM10DBMPREDRVCAP */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_MASK 0x30UL /**< Bit mask for RAC_TXPATRIM10DBMPREDRVCAP */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 0x00000000UL /**< Mode cap_0 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 0x00000001UL /**< Mode cap_1 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 0x00000002UL /**< Mode cap_2 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 0x00000003UL /**< Mode cap_3 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 << 4) /**< Shifted mode cap_0 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 << 4) /**< Shifted mode cap_1 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 << 4) /**< Shifted mode cap_2 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 << 4) /**< Shifted mode cap_3 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_SHIFT 6 /**< Shift value for RAC_TXPATRIM10DBMPREDRVSLC */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_MASK 0xC0UL /**< Bit mask for RAC_TXPATRIM10DBMPREDRVSLC */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 0x00000000UL /**< Mode slc_0 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 0x00000001UL /**< Mode slc_1 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 0x00000002UL /**< Mode slc_2 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 0x00000003UL /**< Mode slc_3 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 << 6) /**< Shifted mode slc_0 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 << 6) /**< Shifted mode slc_1 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 << 6) /**< Shifted mode slc_2 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 << 6) /**< Shifted mode slc_3 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_SHIFT 8 /**< Shift value for RAC_TXPATRIM20DBMCTAP */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_MASK 0xF00UL /**< Bit mask for RAC_TXPATRIM20DBMCTAP */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 0x00000000UL /**< Mode ctap_trim_0 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 0x00000001UL /**< Mode ctap_trim_1 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 0x00000002UL /**< Mode ctap_trim_2 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 0x00000003UL /**< Mode ctap_trim_3 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 0x00000004UL /**< Mode ctap_trim_4 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 0x00000005UL /**< Mode ctap_trim_5 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 0x00000006UL /**< Mode ctap_trim_6 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 0x00000007UL /**< Mode ctap_trim_7 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 0x00000008UL /**< Mode ctap_trim_8 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT (_RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 << 8) /**< Shifted mode ctap_trim_0 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 << 8) /**< Shifted mode ctap_trim_1 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 << 8) /**< Shifted mode ctap_trim_2 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 << 8) /**< Shifted mode ctap_trim_3 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 << 8) /**< Shifted mode ctap_trim_4 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 << 8) /**< Shifted mode ctap_trim_5 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 << 8) /**< Shifted mode ctap_trim_6 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 << 8) /**< Shifted mode ctap_trim_7 for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 << 8) /**< Shifted mode ctap_trim_8 for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_SHIFT 12 /**< Shift value for RAC_TXPATRIM20DBMPREDRV */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_MASK 0xF000UL /**< Bit mask for RAC_TXPATRIM20DBMPREDRV */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT 0x00000006UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps 0x00000000UL /**< Mode trise_137ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps 0x00000001UL /**< Mode trise_127ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps 0x00000002UL /**< Mode trise_117ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps 0x00000003UL /**< Mode trise_110ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps 0x00000004UL /**< Mode trise_75ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps 0x00000005UL /**< Mode trise_73ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps 0x00000006UL /**< Mode trise_71ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps 0x00000007UL /**< Mode trise_70ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps << 12) /**< Shifted mode trise_137ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps << 12) /**< Shifted mode trise_127ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps << 12) /**< Shifted mode trise_117ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps << 12) /**< Shifted mode trise_110ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps << 12) /**< Shifted mode trise_75ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps << 12) /**< Shifted mode trise_73ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps << 12) /**< Shifted mode trise_71ps for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps << 12) /**< Shifted mode trise_70ps for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_SHIFT 16 /**< Shift value for RAC_TXPATRIMCAPPAOUTM */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_MASK 0xF0000UL /**< Bit mask for RAC_TXPATRIMCAPPAOUTM */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT (_RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_SHIFT 20 /**< Shift value for RAC_TXPATRIMCAPPAOUTP */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_MASK 0xF00000UL /**< Bit mask for RAC_TXPATRIMCAPPAOUTP */ +#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT (_RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ +#define _RAC_PATRIM4_TXPATRIMCMGAIN_SHIFT 24 /**< Shift value for RAC_TXPATRIMCMGAIN */ +#define _RAC_PATRIM4_TXPATRIMCMGAIN_MASK 0x3000000UL /**< Bit mask for RAC_TXPATRIMCMGAIN */ +#define _RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */ +#define RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT (_RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM4 */ + +/* Bit fields for RAC PATRIM5 */ +#define _RAC_PATRIM5_RESETVALUE 0x00181800UL /**< Default value for RAC_PATRIM5 */ +#define _RAC_PATRIM5_MASK 0x033F3F7FUL /**< Mask for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDACGLITCH (0x1UL << 0) /**< TXPATRIMDACGLITCH */ +#define _RAC_PATRIM5_TXPATRIMDACGLITCH_SHIFT 0 /**< Shift value for RAC_TXPATRIMDACGLITCH */ +#define _RAC_PATRIM5_TXPATRIMDACGLITCH_MASK 0x1UL /**< Bit mask for RAC_TXPATRIMDACGLITCH */ +#define _RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch 0x00000000UL /**< Mode larger_glitch for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch 0x00000001UL /**< Mode smaller_glitch for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT (_RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch (_RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch << 0) /**< Shifted mode larger_glitch for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch (_RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch << 0) /**< Shifted mode smaller_glitch for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_SHIFT 1 /**< Shift value for RAC_TXPATRIMDLY0 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_MASK 0xEUL /**< Bit mask for RAC_TXPATRIMDLY0 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps 0x00000000UL /**< Mode tdly_0ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps 0x00000001UL /**< Mode tdly_64ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps 0x00000002UL /**< Mode tdly_65ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps 0x00000003UL /**< Mode tdly_66ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps 0x00000004UL /**< Mode tdly_68ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps 0x00000005UL /**< Mode tdly_70ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps 0x00000006UL /**< Mode tdly_75ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps 0x00000007UL /**< Mode tdly_83ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_DEFAULT (_RAC_PATRIM5_TXPATRIMDLY0_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps << 1) /**< Shifted mode tdly_0ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps << 1) /**< Shifted mode tdly_64ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps << 1) /**< Shifted mode tdly_65ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps << 1) /**< Shifted mode tdly_66ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps << 1) /**< Shifted mode tdly_68ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps << 1) /**< Shifted mode tdly_70ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps << 1) /**< Shifted mode tdly_75ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps << 1) /**< Shifted mode tdly_83ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_SHIFT 4 /**< Shift value for RAC_TXPATRIMDLY1 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_MASK 0x70UL /**< Bit mask for RAC_TXPATRIMDLY1 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps 0x00000000UL /**< Mode tdly_0ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps 0x00000001UL /**< Mode tdly_64ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps 0x00000002UL /**< Mode tdly_65ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps 0x00000003UL /**< Mode tdly_66ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps 0x00000004UL /**< Mode tdly_68ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps 0x00000005UL /**< Mode tdly_70ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps 0x00000006UL /**< Mode tdly_75ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps 0x00000007UL /**< Mode tdly_83ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_DEFAULT (_RAC_PATRIM5_TXPATRIMDLY1_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps << 4) /**< Shifted mode tdly_0ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps << 4) /**< Shifted mode tdly_64ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps << 4) /**< Shifted mode tdly_65ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps << 4) /**< Shifted mode tdly_66ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps << 4) /**< Shifted mode tdly_68ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps << 4) /**< Shifted mode tdly_70ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps << 4) /**< Shifted mode tdly_75ps for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps << 4) /**< Shifted mode tdly_83ps for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_SHIFT 8 /**< Shift value for RAC_TXPATRIMNBIAS */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_MASK 0xF00UL /**< Bit mask for RAC_TXPATRIMNBIAS */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv 0x00000000UL /**< Mode vnbias_dn104mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv 0x00000001UL /**< Mode vnbias_dn91mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv 0x00000002UL /**< Mode vnbias_dn78mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv 0x00000003UL /**< Mode vnbias_dn65mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv 0x00000004UL /**< Mode vnbias_dn52mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv 0x00000005UL /**< Mode vnbias_dn39mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv 0x00000006UL /**< Mode vnbias_dn26mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv 0x00000007UL /**< Mode vnbias_dn13mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default 0x00000008UL /**< Mode vnbias_default for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv 0x00000009UL /**< Mode vnbias_up13mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv 0x0000000AUL /**< Mode vnbias_up26mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv 0x0000000BUL /**< Mode vnbias_up39mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv 0x0000000CUL /**< Mode vnbias_up52mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv 0x0000000DUL /**< Mode vnbias_up65mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv 0x0000000EUL /**< Mode vnbias_up78mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv 0x0000000FUL /**< Mode vnbias_up91mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT (_RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv << 8) /**< Shifted mode vnbias_dn104mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv << 8) /**< Shifted mode vnbias_dn91mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv << 8) /**< Shifted mode vnbias_dn78mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv << 8) /**< Shifted mode vnbias_dn65mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv << 8) /**< Shifted mode vnbias_dn52mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv << 8) /**< Shifted mode vnbias_dn39mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv << 8) /**< Shifted mode vnbias_dn26mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv << 8) /**< Shifted mode vnbias_dn13mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default << 8) /**< Shifted mode vnbias_default for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv << 8) /**< Shifted mode vnbias_up13mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv << 8) /**< Shifted mode vnbias_up26mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv << 8) /**< Shifted mode vnbias_up39mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv << 8) /**< Shifted mode vnbias_up52mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv << 8) /**< Shifted mode vnbias_up65mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv << 8) /**< Shifted mode vnbias_up78mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv << 8) /**< Shifted mode vnbias_up91mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNCASC_SHIFT 12 /**< Shift value for RAC_TXPATRIMNCASC */ +#define _RAC_PATRIM5_TXPATRIMNCASC_MASK 0x3000UL /**< Bit mask for RAC_TXPATRIMNCASC */ +#define _RAC_PATRIM5_TXPATRIMNCASC_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv 0x00000000UL /**< Mode ncbias_m50mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault 0x00000001UL /**< Mode ncbiasdefault for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv 0x00000002UL /**< Mode ncbias_p50mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv 0x00000003UL /**< Mode ncbias_p100mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNCASC_DEFAULT (_RAC_PATRIM5_TXPATRIMNCASC_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv << 12) /**< Shifted mode ncbias_m50mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault (_RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault << 12) /**< Shifted mode ncbiasdefault for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv << 12) /**< Shifted mode ncbias_p50mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv << 12) /**< Shifted mode ncbias_p100mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_SHIFT 16 /**< Shift value for RAC_TXPATRIMPBIAS */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_MASK 0xF0000UL /**< Bit mask for RAC_TXPATRIMPBIAS */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv 0x00000000UL /**< Mode vpbias_up104mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv 0x00000001UL /**< Mode vpbias_up91mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv 0x00000002UL /**< Mode vpbias_up78mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv 0x00000003UL /**< Mode vpbias_up65mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv 0x00000004UL /**< Mode vpbias_up52mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv 0x00000005UL /**< Mode vpbias_up39mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv 0x00000006UL /**< Mode vpbias_up26mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv 0x00000007UL /**< Mode vpbias_up13mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default 0x00000008UL /**< Mode vpbias_default for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv 0x00000009UL /**< Mode vpbias_dn13mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv 0x0000000AUL /**< Mode vpbias_dn26mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv 0x0000000BUL /**< Mode vpbias_dn38mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv 0x0000000CUL /**< Mode vpbias_dn52mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv 0x0000000DUL /**< Mode vpbias_dn65mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv 0x0000000EUL /**< Mode vpbias_dn78mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv 0x0000000FUL /**< Mode vpbias_dn91mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT (_RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv << 16) /**< Shifted mode vpbias_up104mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv << 16) /**< Shifted mode vpbias_up91mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv << 16) /**< Shifted mode vpbias_up78mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv << 16) /**< Shifted mode vpbias_up65mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv << 16) /**< Shifted mode vpbias_up52mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv << 16) /**< Shifted mode vpbias_up39mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv << 16) /**< Shifted mode vpbias_up26mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv << 16) /**< Shifted mode vpbias_up13mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default << 16) /**< Shifted mode vpbias_default for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv << 16) /**< Shifted mode vpbias_dn13mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv << 16) /**< Shifted mode vpbias_dn26mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv << 16) /**< Shifted mode vpbias_dn38mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv << 16) /**< Shifted mode vpbias_dn52mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv << 16) /**< Shifted mode vpbias_dn65mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv << 16) /**< Shifted mode vpbias_dn78mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv << 16) /**< Shifted mode vpbias_dn91mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPCASC_SHIFT 20 /**< Shift value for RAC_TXPATRIMPCASC */ +#define _RAC_PATRIM5_TXPATRIMPCASC_MASK 0x300000UL /**< Bit mask for RAC_TXPATRIMPCASC */ +#define _RAC_PATRIM5_TXPATRIMPCASC_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv 0x00000000UL /**< Mode pcbias_n50mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_default 0x00000001UL /**< Mode pcbias_default for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv 0x00000002UL /**< Mode pcbias_m50mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv 0x00000003UL /**< Mode pcbias_m100mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPCASC_DEFAULT (_RAC_PATRIM5_TXPATRIMPCASC_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv << 20) /**< Shifted mode pcbias_n50mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_default (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_default << 20) /**< Shifted mode pcbias_default for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv << 20) /**< Shifted mode pcbias_m50mv for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv << 20) /**< Shifted mode pcbias_m100mv for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_SHIFT 24 /**< Shift value for RAC_TXPATRIMREGSLICES */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_MASK 0x3000000UL /**< Bit mask for RAC_TXPATRIMREGSLICES */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare1 0x00000000UL /**< Mode spare1 for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare2 0x00000001UL /**< Mode spare2 for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare3 0x00000002UL /**< Mode spare3 for RAC_PATRIM5 */ +#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare4 0x00000003UL /**< Mode spare4 for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT (_RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMREGSLICES_spare1 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare1 << 24) /**< Shifted mode spare1 for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMREGSLICES_spare2 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare2 << 24) /**< Shifted mode spare2 for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMREGSLICES_spare3 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare3 << 24) /**< Shifted mode spare3 for RAC_PATRIM5 */ +#define RAC_PATRIM5_TXPATRIMREGSLICES_spare4 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare4 << 24) /**< Shifted mode spare4 for RAC_PATRIM5 */ + +/* Bit fields for RAC TXPOWER */ +#define _RAC_TXPOWER_RESETVALUE 0x00000010UL /**< Default value for RAC_TXPOWER */ +#define _RAC_TXPOWER_MASK 0x0000003FUL /**< Mask for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMPOWER_SHIFT 0 /**< Shift value for RAC_TX0DBMPOWER */ +#define _RAC_TXPOWER_TX0DBMPOWER_MASK 0xFUL /**< Bit mask for RAC_TX0DBMPOWER */ +#define _RAC_TXPOWER_TX0DBMPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 0x00000000UL /**< Mode on_stripe_0 for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 0x0000000FUL /**< Mode on_stripe_15 for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMPOWER_DEFAULT (_RAC_TXPOWER_TX0DBMPOWER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 (_RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 << 0) /**< Shifted mode on_stripe_0 for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 (_RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 << 0) /**< Shifted mode on_stripe_15 for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_SHIFT 4 /**< Shift value for RAC_TX0DBMSELSLICE */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_MASK 0x30UL /**< Bit mask for RAC_TX0DBMSELSLICE */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice 0x00000000UL /**< Mode on_0_slice for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice 0x00000001UL /**< Mode on_1_slice for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_NA 0x00000002UL /**< Mode NA for RAC_TXPOWER */ +#define _RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices 0x00000003UL /**< Mode on_1_slices for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT (_RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice (_RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice << 4) /**< Shifted mode on_0_slice for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice (_RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice << 4) /**< Shifted mode on_1_slice for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMSELSLICE_NA (_RAC_TXPOWER_TX0DBMSELSLICE_NA << 4) /**< Shifted mode NA for RAC_TXPOWER */ +#define RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices (_RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices << 4) /**< Shifted mode on_1_slices for RAC_TXPOWER */ + +/* Bit fields for RAC TXRAMP */ +#define _RAC_TXRAMP_RESETVALUE 0x00000000UL /**< Default value for RAC_TXRAMP */ +#define _RAC_TXRAMP_MASK 0x00000001UL /**< Mask for RAC_TXRAMP */ +#define RAC_TXRAMP_PARAMPMODE (0x1UL << 0) /**< PARAMPMODE */ +#define _RAC_TXRAMP_PARAMPMODE_SHIFT 0 /**< Shift value for RAC_PARAMPMODE */ +#define _RAC_TXRAMP_PARAMPMODE_MASK 0x1UL /**< Bit mask for RAC_PARAMPMODE */ +#define _RAC_TXRAMP_PARAMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TXRAMP */ +#define RAC_TXRAMP_PARAMPMODE_DEFAULT (_RAC_TXRAMP_PARAMPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TXRAMP */ + +/* Bit fields for RAC PGATRIM */ +#define _RAC_PGATRIM_RESETVALUE 0x00000B15UL /**< Default value for RAC_PGATRIM */ +#define _RAC_PGATRIM_MASK 0x00000FDFUL /**< Mask for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGACTUNE_SHIFT 0 /**< Shift value for RAC_PGACTUNE */ +#define _RAC_PGATRIM_PGACTUNE_MASK 0x1FUL /**< Bit mask for RAC_PGACTUNE */ +#define _RAC_PGATRIM_PGACTUNE_DEFAULT 0x00000015UL /**< Mode DEFAULT for RAC_PGATRIM */ +#define RAC_PGATRIM_PGACTUNE_DEFAULT (_RAC_PGATRIM_PGACTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_SHIFT 6 /**< Shift value for RAC_PGAVCMOUTTRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_MASK 0x1C0UL /**< Bit mask for RAC_PGAVCMOUTTRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 0x00000000UL /**< Mode vcm_out_475 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 0x00000001UL /**< Mode vcm_out_500 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 0x00000002UL /**< Mode vcm_out_525 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 0x00000003UL /**< Mode vcm_out_550 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 0x00000004UL /**< Mode vcm_out_575 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 0x00000005UL /**< Mode vcm_out_600 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 0x00000006UL /**< Mode vcm_out_625 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 0x00000007UL /**< Mode vcm_out_650 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT (_RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 << 6) /**< Shifted mode vcm_out_475 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 << 6) /**< Shifted mode vcm_out_500 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 << 6) /**< Shifted mode vcm_out_525 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 << 6) /**< Shifted mode vcm_out_550 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 << 6) /**< Shifted mode vcm_out_575 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 << 6) /**< Shifted mode vcm_out_600 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 << 6) /**< Shifted mode vcm_out_625 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 << 6) /**< Shifted mode vcm_out_650 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_SHIFT 9 /**< Shift value for RAC_PGAVLDOTRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_MASK 0xE00UL /**< Bit mask for RAC_PGAVLDOTRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 0x00000000UL /**< Mode vdda_1225 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 0x00000001UL /**< Mode vdda_1250 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 0x00000002UL /**< Mode vdda_1275 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 0x00000003UL /**< Mode vdda_1300 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 0x00000004UL /**< Mode vdda_1325 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 0x00000005UL /**< Mode vdda_1350 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 0x00000006UL /**< Mode vdda_1375 for RAC_PGATRIM */ +#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 0x00000007UL /**< Mode vdda_1400 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_DEFAULT (_RAC_PGATRIM_PGAVLDOTRIM_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 << 9) /**< Shifted mode vdda_1225 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 << 9) /**< Shifted mode vdda_1250 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 << 9) /**< Shifted mode vdda_1275 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 << 9) /**< Shifted mode vdda_1300 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 << 9) /**< Shifted mode vdda_1325 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 << 9) /**< Shifted mode vdda_1350 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 << 9) /**< Shifted mode vdda_1375 for RAC_PGATRIM */ +#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 << 9) /**< Shifted mode vdda_1400 for RAC_PGATRIM */ + +/* Bit fields for RAC PGACAL */ +#define _RAC_PGACAL_RESETVALUE 0x00002020UL /**< Default value for RAC_PGACAL */ +#define _RAC_PGACAL_MASK 0x00003F3FUL /**< Mask for RAC_PGACAL */ +#define _RAC_PGACAL_PGAOFFCALI_SHIFT 0 /**< Shift value for RAC_PGAOFFCALI */ +#define _RAC_PGACAL_PGAOFFCALI_MASK 0x3FUL /**< Bit mask for RAC_PGAOFFCALI */ +#define _RAC_PGACAL_PGAOFFCALI_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_PGACAL */ +#define RAC_PGACAL_PGAOFFCALI_DEFAULT (_RAC_PGACAL_PGAOFFCALI_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGACAL */ +#define _RAC_PGACAL_PGAOFFCALQ_SHIFT 8 /**< Shift value for RAC_PGAOFFCALQ */ +#define _RAC_PGACAL_PGAOFFCALQ_MASK 0x3F00UL /**< Bit mask for RAC_PGAOFFCALQ */ +#define _RAC_PGACAL_PGAOFFCALQ_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_PGACAL */ +#define RAC_PGACAL_PGAOFFCALQ_DEFAULT (_RAC_PGACAL_PGAOFFCALQ_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PGACAL */ + +/* Bit fields for RAC PGACTRL */ +#define _RAC_PGACTRL_RESETVALUE 0x00008001UL /**< Default value for RAC_PGACTRL */ +#define _RAC_PGACTRL_MASK 0x01FFEFFFUL /**< Mask for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGABWMODE_SHIFT 0 /**< Shift value for RAC_PGABWMODE */ +#define _RAC_PGACTRL_PGABWMODE_MASK 0xFUL /**< Bit mask for RAC_PGABWMODE */ +#define _RAC_PGACTRL_PGABWMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGABWMODE_DEFAULT (_RAC_PGACTRL_PGABWMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENGHZ (0x1UL << 4) /**< PGAENGHZ */ +#define _RAC_PGACTRL_PGAENGHZ_SHIFT 4 /**< Shift value for RAC_PGAENGHZ */ +#define _RAC_PGACTRL_PGAENGHZ_MASK 0x10UL /**< Bit mask for RAC_PGAENGHZ */ +#define _RAC_PGACTRL_PGAENGHZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENGHZ_ghz_disable 0x00000000UL /**< Mode ghz_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENGHZ_ghz_enable 0x00000001UL /**< Mode ghz_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENGHZ_DEFAULT (_RAC_PGACTRL_PGAENGHZ_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENGHZ_ghz_disable (_RAC_PGACTRL_PGAENGHZ_ghz_disable << 4) /**< Shifted mode ghz_disable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENGHZ_ghz_enable (_RAC_PGACTRL_PGAENGHZ_ghz_enable << 4) /**< Shifted mode ghz_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENBIAS (0x1UL << 5) /**< PGAENBIAS */ +#define _RAC_PGACTRL_PGAENBIAS_SHIFT 5 /**< Shift value for RAC_PGAENBIAS */ +#define _RAC_PGACTRL_PGAENBIAS_MASK 0x20UL /**< Bit mask for RAC_PGAENBIAS */ +#define _RAC_PGACTRL_PGAENBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENBIAS_bias_disable 0x00000000UL /**< Mode bias_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENBIAS_bias_enable 0x00000001UL /**< Mode bias_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENBIAS_DEFAULT (_RAC_PGACTRL_PGAENBIAS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENBIAS_bias_disable (_RAC_PGACTRL_PGAENBIAS_bias_disable << 5) /**< Shifted mode bias_disable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENBIAS_bias_enable (_RAC_PGACTRL_PGAENBIAS_bias_enable << 5) /**< Shifted mode bias_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLATCHI (0x1UL << 6) /**< PGAENLATCHI */ +#define _RAC_PGACTRL_PGAENLATCHI_SHIFT 6 /**< Shift value for RAC_PGAENLATCHI */ +#define _RAC_PGACTRL_PGAENLATCHI_MASK 0x40UL /**< Bit mask for RAC_PGAENLATCHI */ +#define _RAC_PGACTRL_PGAENLATCHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable 0x00000000UL /**< Mode pkd_latch_i_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable 0x00000001UL /**< Mode pkd_latch_i_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLATCHI_DEFAULT (_RAC_PGACTRL_PGAENLATCHI_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable (_RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable << 6) /**< Shifted mode pkd_latch_i_disable for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable (_RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable << 6) /**< Shifted mode pkd_latch_i_enable for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENLATCHQ (0x1UL << 7) /**< PGAENLATCHQ */ +#define _RAC_PGACTRL_PGAENLATCHQ_SHIFT 7 /**< Shift value for RAC_PGAENLATCHQ */ +#define _RAC_PGACTRL_PGAENLATCHQ_MASK 0x80UL /**< Bit mask for RAC_PGAENLATCHQ */ +#define _RAC_PGACTRL_PGAENLATCHQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable 0x00000000UL /**< Mode pkd_latch_q_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable 0x00000001UL /**< Mode pkd_latch_q_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLATCHQ_DEFAULT (_RAC_PGACTRL_PGAENLATCHQ_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable (_RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable << 7) /**< Shifted mode pkd_latch_q_disable for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable (_RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable << 7) /**< Shifted mode pkd_latch_q_enable for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENLDOLOAD (0x1UL << 8) /**< PGAENLDOLOAD */ +#define _RAC_PGACTRL_PGAENLDOLOAD_SHIFT 8 /**< Shift value for RAC_PGAENLDOLOAD */ +#define _RAC_PGACTRL_PGAENLDOLOAD_MASK 0x100UL /**< Bit mask for RAC_PGAENLDOLOAD */ +#define _RAC_PGACTRL_PGAENLDOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load 0x00000000UL /**< Mode disable_ldo_load for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load 0x00000001UL /**< Mode enable_ldo_load for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLDOLOAD_DEFAULT (_RAC_PGACTRL_PGAENLDOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load (_RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load << 8) /**< Shifted mode disable_ldo_load for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load (_RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load << 8) /**< Shifted mode enable_ldo_load for RAC_PGACTRL*/ +#define RAC_PGACTRL_PGAENPGAI (0x1UL << 9) /**< PGAENPGAI */ +#define _RAC_PGACTRL_PGAENPGAI_SHIFT 9 /**< Shift value for RAC_PGAENPGAI */ +#define _RAC_PGACTRL_PGAENPGAI_MASK 0x200UL /**< Bit mask for RAC_PGAENPGAI */ +#define _RAC_PGACTRL_PGAENPGAI_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPGAI_pgai_disable 0x00000000UL /**< Mode pgai_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPGAI_pgai_enable 0x00000001UL /**< Mode pgai_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAI_DEFAULT (_RAC_PGACTRL_PGAENPGAI_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAI_pgai_disable (_RAC_PGACTRL_PGAENPGAI_pgai_disable << 9) /**< Shifted mode pgai_disable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAI_pgai_enable (_RAC_PGACTRL_PGAENPGAI_pgai_enable << 9) /**< Shifted mode pgai_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAQ (0x1UL << 10) /**< PGAENPGAQ */ +#define _RAC_PGACTRL_PGAENPGAQ_SHIFT 10 /**< Shift value for RAC_PGAENPGAQ */ +#define _RAC_PGACTRL_PGAENPGAQ_MASK 0x400UL /**< Bit mask for RAC_PGAENPGAQ */ +#define _RAC_PGACTRL_PGAENPGAQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPGAQ_pgaq_disable 0x00000000UL /**< Mode pgaq_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPGAQ_pgaq_enable 0x00000001UL /**< Mode pgaq_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAQ_DEFAULT (_RAC_PGACTRL_PGAENPGAQ_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAQ_pgaq_disable (_RAC_PGACTRL_PGAENPGAQ_pgaq_disable << 10) /**< Shifted mode pgaq_disable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPGAQ_pgaq_enable (_RAC_PGACTRL_PGAENPGAQ_pgaq_enable << 10) /**< Shifted mode pgaq_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPKD (0x1UL << 11) /**< PGAENPKD */ +#define _RAC_PGACTRL_PGAENPKD_SHIFT 11 /**< Shift value for RAC_PGAENPKD */ +#define _RAC_PGACTRL_PGAENPKD_MASK 0x800UL /**< Bit mask for RAC_PGAENPKD */ +#define _RAC_PGACTRL_PGAENPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPKD_pkd_disable 0x00000000UL /**< Mode pkd_disable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAENPKD_pkd_enable 0x00000001UL /**< Mode pkd_enable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPKD_DEFAULT (_RAC_PGACTRL_PGAENPKD_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPKD_pkd_disable (_RAC_PGACTRL_PGAENPKD_pkd_disable << 11) /**< Shifted mode pkd_disable for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAENPKD_pkd_enable (_RAC_PGACTRL_PGAENPKD_pkd_enable << 11) /**< Shifted mode pkd_enable for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_SHIFT 14 /**< Shift value for RAC_PGAPOWERMODE */ +#define _RAC_PGACTRL_PGAPOWERMODE_MASK 0x1C000UL /**< Bit mask for RAC_PGAPOWERMODE */ +#define _RAC_PGACTRL_PGAPOWERMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 0x00000000UL /**< Mode pm0_3u0 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 0x00000001UL /**< Mode pm1_3u5 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 0x00000002UL /**< Mode pm2_4u0 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 0x00000003UL /**< Mode pm3_4u5 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 0x00000004UL /**< Mode pm4_4u0 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 0x00000005UL /**< Mode pm5_4u5 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 0x00000006UL /**< Mode pm6_5u0 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 0x00000007UL /**< Mode pm7_5u5 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_DEFAULT (_RAC_PGACTRL_PGAPOWERMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 (_RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 << 14) /**< Shifted mode pm0_3u0 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 (_RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 << 14) /**< Shifted mode pm1_3u5 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 (_RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 << 14) /**< Shifted mode pm2_4u0 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 (_RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 << 14) /**< Shifted mode pm3_4u5 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 (_RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 << 14) /**< Shifted mode pm4_4u0 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 (_RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 << 14) /**< Shifted mode pm5_4u5 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 (_RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 << 14) /**< Shifted mode pm6_5u0 for RAC_PGACTRL */ +#define RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 (_RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 << 14) /**< Shifted mode pm7_5u5 for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_SHIFT 17 /**< Shift value for RAC_PGATHRPKDLOSEL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_MASK 0x1E0000UL /**< Bit mask for RAC_PGATHRPKDLOSEL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv 0x00000000UL /**< Mode vref50mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv 0x00000001UL /**< Mode vref75mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv 0x00000002UL /**< Mode vref100mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv 0x00000003UL /**< Mode vref125mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv 0x00000004UL /**< Mode vref150mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv 0x00000005UL /**< Mode vref175mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv 0x00000006UL /**< Mode vref200mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv 0x00000007UL /**< Mode vref225mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv 0x00000008UL /**< Mode vref250mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv 0x00000009UL /**< Mode vref275mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv 0x0000000AUL /**< Mode vref300mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT (_RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv << 17) /**< Shifted mode vref50mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv << 17) /**< Shifted mode vref75mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv << 17) /**< Shifted mode vref100mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv << 17) /**< Shifted mode vref125mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv << 17) /**< Shifted mode vref150mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv << 17) /**< Shifted mode vref175mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv << 17) /**< Shifted mode vref200mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv << 17) /**< Shifted mode vref225mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv << 17) /**< Shifted mode vref250mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv << 17) /**< Shifted mode vref275mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv << 17) /**< Shifted mode vref300mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_SHIFT 21 /**< Shift value for RAC_PGATHRPKDHISEL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_MASK 0x1E00000UL /**< Bit mask for RAC_PGATHRPKDHISEL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref50mv 0x00000000UL /**< Mode vref50mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref75mv 0x00000001UL /**< Mode vref75mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref100mv 0x00000002UL /**< Mode vref100mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref125mv 0x00000003UL /**< Mode vref125mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_verf150mv 0x00000004UL /**< Mode verf150mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref175mv 0x00000005UL /**< Mode vref175mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref200mv 0x00000006UL /**< Mode vref200mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref225mv 0x00000007UL /**< Mode vref225mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref250mv 0x00000008UL /**< Mode vref250mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref275mv 0x00000009UL /**< Mode vref275mv for RAC_PGACTRL */ +#define _RAC_PGACTRL_PGATHRPKDHISEL_vref300mv 0x0000000AUL /**< Mode vref300mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT (_RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref50mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref50mv << 21) /**< Shifted mode vref50mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref75mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref75mv << 21) /**< Shifted mode vref75mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref100mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref100mv << 21) /**< Shifted mode vref100mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref125mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref125mv << 21) /**< Shifted mode vref125mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_verf150mv (_RAC_PGACTRL_PGATHRPKDHISEL_verf150mv << 21) /**< Shifted mode verf150mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref175mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref175mv << 21) /**< Shifted mode vref175mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref200mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref200mv << 21) /**< Shifted mode vref200mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref225mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref225mv << 21) /**< Shifted mode vref225mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref250mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref250mv << 21) /**< Shifted mode vref250mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref275mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref275mv << 21) /**< Shifted mode vref275mv for RAC_PGACTRL */ +#define RAC_PGACTRL_PGATHRPKDHISEL_vref300mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref300mv << 21) /**< Shifted mode vref300mv for RAC_PGACTRL */ + +/* Bit fields for RAC RFBIASCAL */ +#define _RAC_RFBIASCAL_RESETVALUE 0x30201A20UL /**< Default value for RAC_RFBIASCAL */ +#define _RAC_RFBIASCAL_MASK 0x3F3F3F3FUL /**< Mask for RAC_RFBIASCAL */ +#define _RAC_RFBIASCAL_RFBIASCALBIAS_SHIFT 0 /**< Shift value for RAC_RFBIASCALBIAS */ +#define _RAC_RFBIASCAL_RFBIASCALBIAS_MASK 0x3FUL /**< Bit mask for RAC_RFBIASCALBIAS */ +#define _RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_RFBIASCAL */ +#define RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT (_RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */ +#define _RAC_RFBIASCAL_RFBIASCALTC_SHIFT 8 /**< Shift value for RAC_RFBIASCALTC */ +#define _RAC_RFBIASCAL_RFBIASCALTC_MASK 0x3F00UL /**< Bit mask for RAC_RFBIASCALTC */ +#define _RAC_RFBIASCAL_RFBIASCALTC_DEFAULT 0x0000001AUL /**< Mode DEFAULT for RAC_RFBIASCAL */ +#define RAC_RFBIASCAL_RFBIASCALTC_DEFAULT (_RAC_RFBIASCAL_RFBIASCALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */ +#define _RAC_RFBIASCAL_RFBIASCALVREF_SHIFT 16 /**< Shift value for RAC_RFBIASCALVREF */ +#define _RAC_RFBIASCAL_RFBIASCALVREF_MASK 0x3F0000UL /**< Bit mask for RAC_RFBIASCALVREF */ +#define _RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_RFBIASCAL */ +#define RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT (_RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */ +#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_SHIFT 24 /**< Shift value for RAC_RFBIASCALVREFSTARTUP */ +#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_MASK 0x3F000000UL /**< Bit mask for RAC_RFBIASCALVREFSTARTUP */ +#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT 0x00000030UL /**< Mode DEFAULT for RAC_RFBIASCAL */ +#define RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT (_RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */ + +/* Bit fields for RAC RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RESETVALUE 0x00040000UL /**< Default value for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_MASK 0x000F001FUL /**< Mask for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP (0x1UL << 0) /**< RFBIASDISABLEBOOTSTRAP */ +#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_SHIFT 0 /**< Shift value for RAC_RFBIASDISABLEBOOTSTRAP */ +#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_MASK 0x1UL /**< Bit mask for RAC_RFBIASDISABLEBOOTSTRAP */ +#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup 0x00000000UL /**< Mode enable_startup for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup 0x00000001UL /**< Mode disable_startup for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup << 0) /**< Shifted mode enable_startup for RAC_RFBIASCTRL*/ +#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup << 0) /**< Shifted mode disable_startup for RAC_RFBIASCTRL*/ +#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT (0x1UL << 1) /**< RFBIASLDOHIGHCURRENT */ +#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_SHIFT 1 /**< Shift value for RAC_RFBIASLDOHIGHCURRENT */ +#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_MASK 0x2UL /**< Bit mask for RAC_RFBIASLDOHIGHCURRENT */ +#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current 0x00000000UL /**< Mode low_current for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current 0x00000001UL /**< Mode high_current for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current << 1) /**< Shifted mode low_current for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current << 1) /**< Shifted mode high_current for RAC_RFBIASCTRL*/ +#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE (0x1UL << 2) /**< RFBIASNONFLASHMODE */ +#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_SHIFT 2 /**< Shift value for RAC_RFBIASNONFLASHMODE */ +#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_MASK 0x4UL /**< Bit mask for RAC_RFBIASNONFLASHMODE */ +#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process 0x00000000UL /**< Mode flash_process for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process 0x00000001UL /**< Mode non_flash_process for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process << 2) /**< Shifted mode flash_process for RAC_RFBIASCTRL*/ +#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process << 2) /**< Shifted mode non_flash_process for RAC_RFBIASCTRL*/ +#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE (0x1UL << 3) /**< RFBIASSTARTUPCORE */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_SHIFT 3 /**< Shift value for RAC_RFBIASSTARTUPCORE */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_MASK 0x8UL /**< Bit mask for RAC_RFBIASSTARTUPCORE */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default 0x00000000UL /**< Mode default for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start 0x00000001UL /**< Mode force_start for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default << 3) /**< Shifted mode default for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start << 3) /**< Shifted mode force_start for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY (0x1UL << 4) /**< RFBIASSTARTUPSUPPLY */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_SHIFT 4 /**< Shift value for RAC_RFBIASSTARTUPSUPPLY */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_MASK 0x10UL /**< Bit mask for RAC_RFBIASSTARTUPSUPPLY */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default 0x00000000UL /**< Mode default for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start 0x00000001UL /**< Mode forc_start for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default << 4) /**< Shifted mode default for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start << 4) /**< Shifted mode forc_start for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_SHIFT 16 /**< Shift value for RAC_RFBIASLDOVREFTRIM */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_MASK 0xF0000UL /**< Bit mask for RAC_RFBIASLDOVREFTRIM */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 0x00000000UL /**< Mode vref_v0p800 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 0x00000001UL /**< Mode vref_v0p813 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 0x00000002UL /**< Mode vref_v0p825 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 0x00000003UL /**< Mode vref_v0p837 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 0x00000004UL /**< Mode vref_v0p850 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 0x00000005UL /**< Mode vref_v0p863 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 0x00000006UL /**< Mode vref_v0p875 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 0x00000007UL /**< Mode vref_v0p887 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 0x00000008UL /**< Mode vref_v0p900 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 0x00000009UL /**< Mode vref_v0p913 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 0x0000000AUL /**< Mode vref_v0p925 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 0x0000000BUL /**< Mode vref_v0p938 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 0x0000000CUL /**< Mode vref_v0p950 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 0x0000000DUL /**< Mode vref_v0p963 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 0x0000000EUL /**< Mode vref_v0p975 for RAC_RFBIASCTRL */ +#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 0x0000000FUL /**< Mode vref_v0p988 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 << 16) /**< Shifted mode vref_v0p800 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 << 16) /**< Shifted mode vref_v0p813 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 << 16) /**< Shifted mode vref_v0p825 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 << 16) /**< Shifted mode vref_v0p837 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 << 16) /**< Shifted mode vref_v0p850 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 << 16) /**< Shifted mode vref_v0p863 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 << 16) /**< Shifted mode vref_v0p875 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 << 16) /**< Shifted mode vref_v0p887 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 << 16) /**< Shifted mode vref_v0p900 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 << 16) /**< Shifted mode vref_v0p913 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 << 16) /**< Shifted mode vref_v0p925 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 << 16) /**< Shifted mode vref_v0p938 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 << 16) /**< Shifted mode vref_v0p950 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 << 16) /**< Shifted mode vref_v0p963 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 << 16) /**< Shifted mode vref_v0p975 for RAC_RFBIASCTRL */ +#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 << 16) /**< Shifted mode vref_v0p988 for RAC_RFBIASCTRL */ + +/* Bit fields for RAC RADIOEN */ +#define _RAC_RADIOEN_RESETVALUE 0x00000000UL /**< Default value for RAC_RADIOEN */ +#define _RAC_RADIOEN_MASK 0x00000007UL /**< Mask for RAC_RADIOEN */ +#define RAC_RADIOEN_PREEN (0x1UL << 0) /**< PREEN */ +#define _RAC_RADIOEN_PREEN_SHIFT 0 /**< Shift value for RAC_PREEN */ +#define _RAC_RADIOEN_PREEN_MASK 0x1UL /**< Bit mask for RAC_PREEN */ +#define _RAC_RADIOEN_PREEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */ +#define _RAC_RADIOEN_PREEN_powered_off 0x00000000UL /**< Mode powered_off for RAC_RADIOEN */ +#define _RAC_RADIOEN_PREEN_powered_on 0x00000001UL /**< Mode powered_on for RAC_RADIOEN */ +#define RAC_RADIOEN_PREEN_DEFAULT (_RAC_RADIOEN_PREEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RADIOEN */ +#define RAC_RADIOEN_PREEN_powered_off (_RAC_RADIOEN_PREEN_powered_off << 0) /**< Shifted mode powered_off for RAC_RADIOEN */ +#define RAC_RADIOEN_PREEN_powered_on (_RAC_RADIOEN_PREEN_powered_on << 0) /**< Shifted mode powered_on for RAC_RADIOEN */ +#define RAC_RADIOEN_PRESTB100UDIS (0x1UL << 1) /**< PRESTB100UDIS */ +#define _RAC_RADIOEN_PRESTB100UDIS_SHIFT 1 /**< Shift value for RAC_PRESTB100UDIS */ +#define _RAC_RADIOEN_PRESTB100UDIS_MASK 0x2UL /**< Bit mask for RAC_PRESTB100UDIS */ +#define _RAC_RADIOEN_PRESTB100UDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */ +#define _RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled 0x00000000UL /**< Mode i100ua_enabled for RAC_RADIOEN */ +#define _RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled 0x00000001UL /**< Mode i100ua_disabled for RAC_RADIOEN */ +#define RAC_RADIOEN_PRESTB100UDIS_DEFAULT (_RAC_RADIOEN_PRESTB100UDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RADIOEN */ +#define RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled (_RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled << 1) /**< Shifted mode i100ua_enabled for RAC_RADIOEN */ +#define RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled (_RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled << 1) /**< Shifted mode i100ua_disabled for RAC_RADIOEN*/ +#define RAC_RADIOEN_RFBIASEN (0x1UL << 2) /**< RFBIASEN */ +#define _RAC_RADIOEN_RFBIASEN_SHIFT 2 /**< Shift value for RAC_RFBIASEN */ +#define _RAC_RADIOEN_RFBIASEN_MASK 0x4UL /**< Bit mask for RAC_RFBIASEN */ +#define _RAC_RADIOEN_RFBIASEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */ +#define _RAC_RADIOEN_RFBIASEN_disable_rfis_vtr 0x00000000UL /**< Mode disable_rfis_vtr for RAC_RADIOEN */ +#define _RAC_RADIOEN_RFBIASEN_enable_rfis_vtr 0x00000001UL /**< Mode enable_rfis_vtr for RAC_RADIOEN */ +#define RAC_RADIOEN_RFBIASEN_DEFAULT (_RAC_RADIOEN_RFBIASEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RADIOEN */ +#define RAC_RADIOEN_RFBIASEN_disable_rfis_vtr (_RAC_RADIOEN_RFBIASEN_disable_rfis_vtr << 2) /**< Shifted mode disable_rfis_vtr for RAC_RADIOEN*/ +#define RAC_RADIOEN_RFBIASEN_enable_rfis_vtr (_RAC_RADIOEN_RFBIASEN_enable_rfis_vtr << 2) /**< Shifted mode enable_rfis_vtr for RAC_RADIOEN*/ + +/* Bit fields for RAC RFPATHEN0 */ +#define _RAC_RFPATHEN0_RESETVALUE 0x00000002UL /**< Default value for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_MASK 0x0000004FUL /**< Mask for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXEN0 (0x1UL << 0) /**< LNAMIXEN0 */ +#define _RAC_RFPATHEN0_LNAMIXEN0_SHIFT 0 /**< Shift value for RAC_LNAMIXEN0 */ +#define _RAC_RFPATHEN0_LNAMIXEN0_MASK 0x1UL /**< Bit mask for RAC_LNAMIXEN0 */ +#define _RAC_RFPATHEN0_LNAMIXEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXEN0_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXEN0_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXEN0_DEFAULT (_RAC_RFPATHEN0_LNAMIXEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXEN0_disable (_RAC_RFPATHEN0_LNAMIXEN0_disable << 0) /**< Shifted mode disable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXEN0_enable (_RAC_RFPATHEN0_LNAMIXEN0_enable << 0) /**< Shifted mode enable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0 (0x1UL << 1) /**< LNAMIXRFATTDCEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_SHIFT 1 /**< Shift value for RAC_LNAMIXRFATTDCEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_MASK 0x2UL /**< Bit mask for RAC_LNAMIXRFATTDCEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc 0x00000000UL /**< Mode disable_dc for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc 0x00000001UL /**< Mode enable_dc for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc << 1) /**< Shifted mode disable_dc for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc << 1) /**< Shifted mode enable_dc for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0 (0x1UL << 2) /**< LNAMIXRFPKDENRF0 */ +#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_SHIFT 2 /**< Shift value for RAC_LNAMIXRFPKDENRF0 */ +#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_MASK 0x4UL /**< Bit mask for RAC_LNAMIXRFPKDENRF0 */ +#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path 0x00000001UL /**< Mode enable_path for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable << 2) /**< Shifted mode disable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path << 2) /**< Shifted mode enable_path for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_SYLODIVRLO02G4EN (0x1UL << 3) /**< SYLODIVRLO02G4EN */ +#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_SHIFT 3 /**< Shift value for RAC_SYLODIVRLO02G4EN */ +#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVRLO02G4EN */ +#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable << 3) /**< Shifted mode disable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable << 3) /**< Shifted mode enable for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXTRSW0 (0x1UL << 6) /**< LNAMIXTRSW0 */ +#define _RAC_RFPATHEN0_LNAMIXTRSW0_SHIFT 6 /**< Shift value for RAC_LNAMIXTRSW0 */ +#define _RAC_RFPATHEN0_LNAMIXTRSW0_MASK 0x40UL /**< Bit mask for RAC_LNAMIXTRSW0 */ +#define _RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXTRSW0_disabled 0x00000000UL /**< Mode disabled for RAC_RFPATHEN0 */ +#define _RAC_RFPATHEN0_LNAMIXTRSW0_enabled 0x00000001UL /**< Mode enabled for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT (_RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXTRSW0_disabled (_RAC_RFPATHEN0_LNAMIXTRSW0_disabled << 6) /**< Shifted mode disabled for RAC_RFPATHEN0 */ +#define RAC_RFPATHEN0_LNAMIXTRSW0_enabled (_RAC_RFPATHEN0_LNAMIXTRSW0_enabled << 6) /**< Shifted mode enabled for RAC_RFPATHEN0 */ + +/* Bit fields for RAC RFPATHEN1 */ +#define _RAC_RFPATHEN1_RESETVALUE 0x00000002UL /**< Default value for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_MASK 0x0000004FUL /**< Mask for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXEN1 (0x1UL << 0) /**< LNAMIXEN1 */ +#define _RAC_RFPATHEN1_LNAMIXEN1_SHIFT 0 /**< Shift value for RAC_LNAMIXEN1 */ +#define _RAC_RFPATHEN1_LNAMIXEN1_MASK 0x1UL /**< Bit mask for RAC_LNAMIXEN1 */ +#define _RAC_RFPATHEN1_LNAMIXEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXEN1_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXEN1_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXEN1_DEFAULT (_RAC_RFPATHEN1_LNAMIXEN1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXEN1_disable (_RAC_RFPATHEN1_LNAMIXEN1_disable << 0) /**< Shifted mode disable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXEN1_enable (_RAC_RFPATHEN1_LNAMIXEN1_enable << 0) /**< Shifted mode enable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1 (0x1UL << 1) /**< LNAMIXRFATTDCEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_SHIFT 1 /**< Shift value for RAC_LNAMIXRFATTDCEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_MASK 0x2UL /**< Bit mask for RAC_LNAMIXRFATTDCEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc 0x00000000UL /**< Mode disable_dc for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc 0x00000001UL /**< Mode enable_dc for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc << 1) /**< Shifted mode disable_dc for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc << 1) /**< Shifted mode enable_dc for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1 (0x1UL << 2) /**< LNAMIXRFPKDENRF1 */ +#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_SHIFT 2 /**< Shift value for RAC_LNAMIXRFPKDENRF1 */ +#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_MASK 0x4UL /**< Bit mask for RAC_LNAMIXRFPKDENRF1 */ +#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path 0x00000001UL /**< Mode enable_path for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable << 2) /**< Shifted mode disable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path << 2) /**< Shifted mode enable_path for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_SYLODIVRLO12G4EN (0x1UL << 3) /**< SYLODIVRLO12G4EN */ +#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_SHIFT 3 /**< Shift value for RAC_SYLODIVRLO12G4EN */ +#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVRLO12G4EN */ +#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable << 3) /**< Shifted mode disable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable << 3) /**< Shifted mode enable for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXTRSW1 (0x1UL << 6) /**< LNAMIXTRSW1 */ +#define _RAC_RFPATHEN1_LNAMIXTRSW1_SHIFT 6 /**< Shift value for RAC_LNAMIXTRSW1 */ +#define _RAC_RFPATHEN1_LNAMIXTRSW1_MASK 0x40UL /**< Bit mask for RAC_LNAMIXTRSW1 */ +#define _RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXTRSW1_disabled 0x00000000UL /**< Mode disabled for RAC_RFPATHEN1 */ +#define _RAC_RFPATHEN1_LNAMIXTRSW1_enabled 0x00000001UL /**< Mode enabled for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT (_RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXTRSW1_disabled (_RAC_RFPATHEN1_LNAMIXTRSW1_disabled << 6) /**< Shifted mode disabled for RAC_RFPATHEN1 */ +#define RAC_RFPATHEN1_LNAMIXTRSW1_enabled (_RAC_RFPATHEN1_LNAMIXTRSW1_enabled << 6) /**< Shifted mode enabled for RAC_RFPATHEN1 */ + +/* Bit fields for RAC RX */ +#define _RAC_RX_RESETVALUE 0x00000020UL /**< Default value for RAC_RX */ +#define _RAC_RX_MASK 0x000703BFUL /**< Mask for RAC_RX */ +#define RAC_RX_IFADCCAPRESET (0x1UL << 0) /**< IFADCCAPRESET */ +#define _RAC_RX_IFADCCAPRESET_SHIFT 0 /**< Shift value for RAC_IFADCCAPRESET */ +#define _RAC_RX_IFADCCAPRESET_MASK 0x1UL /**< Bit mask for RAC_IFADCCAPRESET */ +#define _RAC_RX_IFADCCAPRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_IFADCCAPRESET_cap_reset_disable 0x00000000UL /**< Mode cap_reset_disable for RAC_RX */ +#define _RAC_RX_IFADCCAPRESET_cap_reset_enable 0x00000001UL /**< Mode cap_reset_enable for RAC_RX */ +#define RAC_RX_IFADCCAPRESET_DEFAULT (_RAC_RX_IFADCCAPRESET_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_IFADCCAPRESET_cap_reset_disable (_RAC_RX_IFADCCAPRESET_cap_reset_disable << 0) /**< Shifted mode cap_reset_disable for RAC_RX */ +#define RAC_RX_IFADCCAPRESET_cap_reset_enable (_RAC_RX_IFADCCAPRESET_cap_reset_enable << 0) /**< Shifted mode cap_reset_enable for RAC_RX */ +#define RAC_RX_IFADCENLDOSERIES (0x1UL << 1) /**< IFADCENLDOSERIES */ +#define _RAC_RX_IFADCENLDOSERIES_SHIFT 1 /**< Shift value for RAC_IFADCENLDOSERIES */ +#define _RAC_RX_IFADCENLDOSERIES_MASK 0x2UL /**< Bit mask for RAC_IFADCENLDOSERIES */ +#define _RAC_RX_IFADCENLDOSERIES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_IFADCENLDOSERIES_series_ldo_disable 0x00000000UL /**< Mode series_ldo_disable for RAC_RX */ +#define _RAC_RX_IFADCENLDOSERIES_series_ldo_enable 0x00000001UL /**< Mode series_ldo_enable for RAC_RX */ +#define RAC_RX_IFADCENLDOSERIES_DEFAULT (_RAC_RX_IFADCENLDOSERIES_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_IFADCENLDOSERIES_series_ldo_disable (_RAC_RX_IFADCENLDOSERIES_series_ldo_disable << 1) /**< Shifted mode series_ldo_disable for RAC_RX */ +#define RAC_RX_IFADCENLDOSERIES_series_ldo_enable (_RAC_RX_IFADCENLDOSERIES_series_ldo_enable << 1) /**< Shifted mode series_ldo_enable for RAC_RX */ +#define RAC_RX_IFADCENLDOSHUNT (0x1UL << 2) /**< IFADCENLDOSHUNT */ +#define _RAC_RX_IFADCENLDOSHUNT_SHIFT 2 /**< Shift value for RAC_IFADCENLDOSHUNT */ +#define _RAC_RX_IFADCENLDOSHUNT_MASK 0x4UL /**< Bit mask for RAC_IFADCENLDOSHUNT */ +#define _RAC_RX_IFADCENLDOSHUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable 0x00000000UL /**< Mode shunt_ldo_disable for RAC_RX */ +#define _RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable 0x00000001UL /**< Mode shunt_ldo_enable for RAC_RX */ +#define RAC_RX_IFADCENLDOSHUNT_DEFAULT (_RAC_RX_IFADCENLDOSHUNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable (_RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable << 2) /**< Shifted mode shunt_ldo_disable for RAC_RX */ +#define RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable (_RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable << 2) /**< Shifted mode shunt_ldo_enable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKD (0x1UL << 3) /**< LNAMIXENRFPKD */ +#define _RAC_RX_LNAMIXENRFPKD_SHIFT 3 /**< Shift value for RAC_LNAMIXENRFPKD */ +#define _RAC_RX_LNAMIXENRFPKD_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENRFPKD */ +#define _RAC_RX_LNAMIXENRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_LNAMIXENRFPKD_disable 0x00000000UL /**< Mode disable for RAC_RX */ +#define _RAC_RX_LNAMIXENRFPKD_enable 0x00000001UL /**< Mode enable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKD_DEFAULT (_RAC_RX_LNAMIXENRFPKD_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKD_disable (_RAC_RX_LNAMIXENRFPKD_disable << 3) /**< Shifted mode disable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKD_enable (_RAC_RX_LNAMIXENRFPKD_enable << 3) /**< Shifted mode enable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKDLOTHRESH (0x1UL << 4) /**< LNAMIXENRFPKDLOTHRESH */ +#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_SHIFT 4 /**< Shift value for RAC_LNAMIXENRFPKDLOTHRESH */ +#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_MASK 0x10UL /**< Bit mask for RAC_LNAMIXENRFPKDLOTHRESH */ +#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_disable 0x00000000UL /**< Mode disable for RAC_RX */ +#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_enable 0x00000001UL /**< Mode enable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT (_RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKDLOTHRESH_disable (_RAC_RX_LNAMIXENRFPKDLOTHRESH_disable << 4) /**< Shifted mode disable for RAC_RX */ +#define RAC_RX_LNAMIXENRFPKDLOTHRESH_enable (_RAC_RX_LNAMIXENRFPKDLOTHRESH_enable << 4) /**< Shifted mode enable for RAC_RX */ +#define RAC_RX_LNAMIXLDOLOWCUR (0x1UL << 5) /**< LNAMIXLDOLOWCUR */ +#define _RAC_RX_LNAMIXLDOLOWCUR_SHIFT 5 /**< Shift value for RAC_LNAMIXLDOLOWCUR */ +#define _RAC_RX_LNAMIXLDOLOWCUR_MASK 0x20UL /**< Bit mask for RAC_LNAMIXLDOLOWCUR */ +#define _RAC_RX_LNAMIXLDOLOWCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_LNAMIXLDOLOWCUR_regular_mode 0x00000000UL /**< Mode regular_mode for RAC_RX */ +#define _RAC_RX_LNAMIXLDOLOWCUR_low_current_mode 0x00000001UL /**< Mode low_current_mode for RAC_RX */ +#define RAC_RX_LNAMIXLDOLOWCUR_DEFAULT (_RAC_RX_LNAMIXLDOLOWCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_LNAMIXLDOLOWCUR_regular_mode (_RAC_RX_LNAMIXLDOLOWCUR_regular_mode << 5) /**< Shifted mode regular_mode for RAC_RX */ +#define RAC_RX_LNAMIXLDOLOWCUR_low_current_mode (_RAC_RX_LNAMIXLDOLOWCUR_low_current_mode << 5) /**< Shifted mode low_current_mode for RAC_RX */ +#define RAC_RX_LNAMIXREGLOADEN (0x1UL << 7) /**< LNAMIXREGLOADEN */ +#define _RAC_RX_LNAMIXREGLOADEN_SHIFT 7 /**< Shift value for RAC_LNAMIXREGLOADEN */ +#define _RAC_RX_LNAMIXREGLOADEN_MASK 0x80UL /**< Bit mask for RAC_LNAMIXREGLOADEN */ +#define _RAC_RX_LNAMIXREGLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_LNAMIXREGLOADEN_disable_resistor 0x00000000UL /**< Mode disable_resistor for RAC_RX */ +#define _RAC_RX_LNAMIXREGLOADEN_enable_resistor 0x00000001UL /**< Mode enable_resistor for RAC_RX */ +#define RAC_RX_LNAMIXREGLOADEN_DEFAULT (_RAC_RX_LNAMIXREGLOADEN_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_LNAMIXREGLOADEN_disable_resistor (_RAC_RX_LNAMIXREGLOADEN_disable_resistor << 7) /**< Shifted mode disable_resistor for RAC_RX */ +#define RAC_RX_LNAMIXREGLOADEN_enable_resistor (_RAC_RX_LNAMIXREGLOADEN_enable_resistor << 7) /**< Shifted mode enable_resistor for RAC_RX */ +#define RAC_RX_PGAENLDO (0x1UL << 8) /**< PGAENLDO */ +#define _RAC_RX_PGAENLDO_SHIFT 8 /**< Shift value for RAC_PGAENLDO */ +#define _RAC_RX_PGAENLDO_MASK 0x100UL /**< Bit mask for RAC_PGAENLDO */ +#define _RAC_RX_PGAENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_PGAENLDO_disable_ldo 0x00000000UL /**< Mode disable_ldo for RAC_RX */ +#define _RAC_RX_PGAENLDO_enable_ldo 0x00000001UL /**< Mode enable_ldo for RAC_RX */ +#define RAC_RX_PGAENLDO_DEFAULT (_RAC_RX_PGAENLDO_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_PGAENLDO_disable_ldo (_RAC_RX_PGAENLDO_disable_ldo << 8) /**< Shifted mode disable_ldo for RAC_RX */ +#define RAC_RX_PGAENLDO_enable_ldo (_RAC_RX_PGAENLDO_enable_ldo << 8) /**< Shifted mode enable_ldo for RAC_RX */ +#define RAC_RX_SYCHPQNC3EN (0x1UL << 9) /**< SYCHPQNC3EN */ +#define _RAC_RX_SYCHPQNC3EN_SHIFT 9 /**< Shift value for RAC_SYCHPQNC3EN */ +#define _RAC_RX_SYCHPQNC3EN_MASK 0x200UL /**< Bit mask for RAC_SYCHPQNC3EN */ +#define _RAC_RX_SYCHPQNC3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_SYCHPQNC3EN_qnc_2 0x00000000UL /**< Mode qnc_2 for RAC_RX */ +#define _RAC_RX_SYCHPQNC3EN_qnc_3 0x00000001UL /**< Mode qnc_3 for RAC_RX */ +#define RAC_RX_SYCHPQNC3EN_DEFAULT (_RAC_RX_SYCHPQNC3EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_SYCHPQNC3EN_qnc_2 (_RAC_RX_SYCHPQNC3EN_qnc_2 << 9) /**< Shifted mode qnc_2 for RAC_RX */ +#define RAC_RX_SYCHPQNC3EN_qnc_3 (_RAC_RX_SYCHPQNC3EN_qnc_3 << 9) /**< Shifted mode qnc_3 for RAC_RX */ +#define RAC_RX_SYCHPBIASTRIMBUFRX (0x1UL << 16) /**< SYCHPBIASTRIMBUFRX */ +#define _RAC_RX_SYCHPBIASTRIMBUFRX_SHIFT 16 /**< Shift value for RAC_SYCHPBIASTRIMBUFRX */ +#define _RAC_RX_SYCHPBIASTRIMBUFRX_MASK 0x10000UL /**< Bit mask for RAC_SYCHPBIASTRIMBUFRX */ +#define _RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u 0x00000000UL /**< Mode i_tail_10u for RAC_RX */ +#define _RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u 0x00000001UL /**< Mode i_tail_20u for RAC_RX */ +#define RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT (_RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u (_RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u << 16) /**< Shifted mode i_tail_10u for RAC_RX */ +#define RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u (_RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u << 16) /**< Shifted mode i_tail_20u for RAC_RX */ +#define RAC_RX_SYPFDCHPLPENRX (0x1UL << 17) /**< SYPFDCHPLPENRX */ +#define _RAC_RX_SYPFDCHPLPENRX_SHIFT 17 /**< Shift value for RAC_SYPFDCHPLPENRX */ +#define _RAC_RX_SYPFDCHPLPENRX_MASK 0x20000UL /**< Bit mask for RAC_SYPFDCHPLPENRX */ +#define _RAC_RX_SYPFDCHPLPENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_SYPFDCHPLPENRX_disable 0x00000000UL /**< Mode disable for RAC_RX */ +#define _RAC_RX_SYPFDCHPLPENRX_enable 0x00000001UL /**< Mode enable for RAC_RX */ +#define RAC_RX_SYPFDCHPLPENRX_DEFAULT (_RAC_RX_SYPFDCHPLPENRX_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_SYPFDCHPLPENRX_disable (_RAC_RX_SYPFDCHPLPENRX_disable << 17) /**< Shifted mode disable for RAC_RX */ +#define RAC_RX_SYPFDCHPLPENRX_enable (_RAC_RX_SYPFDCHPLPENRX_enable << 17) /**< Shifted mode enable for RAC_RX */ +#define RAC_RX_SYPFDFPWENRX (0x1UL << 18) /**< SYPFDFPWENRX */ +#define _RAC_RX_SYPFDFPWENRX_SHIFT 18 /**< Shift value for RAC_SYPFDFPWENRX */ +#define _RAC_RX_SYPFDFPWENRX_MASK 0x40000UL /**< Bit mask for RAC_SYPFDFPWENRX */ +#define _RAC_RX_SYPFDFPWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */ +#define _RAC_RX_SYPFDFPWENRX_disable 0x00000000UL /**< Mode disable for RAC_RX */ +#define _RAC_RX_SYPFDFPWENRX_enable 0x00000001UL /**< Mode enable for RAC_RX */ +#define RAC_RX_SYPFDFPWENRX_DEFAULT (_RAC_RX_SYPFDFPWENRX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_RX */ +#define RAC_RX_SYPFDFPWENRX_disable (_RAC_RX_SYPFDFPWENRX_disable << 18) /**< Shifted mode disable for RAC_RX */ +#define RAC_RX_SYPFDFPWENRX_enable (_RAC_RX_SYPFDFPWENRX_enable << 18) /**< Shifted mode enable for RAC_RX */ + +/* Bit fields for RAC TX */ +#define _RAC_TX_RESETVALUE 0x00000000UL /**< Default value for RAC_TX */ +#define _RAC_TX_MASK 0xFFFFF7EFUL /**< Mask for RAC_TX */ +#define RAC_TX_TXPAENREG (0x1UL << 0) /**< TXPAENREG */ +#define _RAC_TX_TXPAENREG_SHIFT 0 /**< Shift value for RAC_TXPAENREG */ +#define _RAC_TX_TXPAENREG_MASK 0x1UL /**< Bit mask for RAC_TXPAENREG */ +#define _RAC_TX_TXPAENREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAENREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAENREG_DEFAULT (_RAC_TX_TXPAENREG_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENREG_disable (_RAC_TX_TXPAENREG_disable << 0) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAENREG_enable (_RAC_TX_TXPAENREG_enable << 0) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAENRAMPCLK (0x1UL << 1) /**< TXPAENRAMPCLK */ +#define _RAC_TX_TXPAENRAMPCLK_SHIFT 1 /**< Shift value for RAC_TXPAENRAMPCLK */ +#define _RAC_TX_TXPAENRAMPCLK_MASK 0x2UL /**< Bit mask for RAC_TXPAENRAMPCLK */ +#define _RAC_TX_TXPAENRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENRAMPCLK_silence_clk 0x00000000UL /**< Mode silence_clk for RAC_TX */ +#define _RAC_TX_TXPAENRAMPCLK_en_clk 0x00000001UL /**< Mode en_clk for RAC_TX */ +#define RAC_TX_TXPAENRAMPCLK_DEFAULT (_RAC_TX_TXPAENRAMPCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENRAMPCLK_silence_clk (_RAC_TX_TXPAENRAMPCLK_silence_clk << 1) /**< Shifted mode silence_clk for RAC_TX */ +#define RAC_TX_TXPAENRAMPCLK_en_clk (_RAC_TX_TXPAENRAMPCLK_en_clk << 1) /**< Shifted mode en_clk for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDREG (0x1UL << 2) /**< TX0DBMENBLEEDREG */ +#define _RAC_TX_TX0DBMENBLEEDREG_SHIFT 2 /**< Shift value for RAC_TX0DBMENBLEEDREG */ +#define _RAC_TX_TX0DBMENBLEEDREG_MASK 0x4UL /**< Bit mask for RAC_TX0DBMENBLEEDREG */ +#define _RAC_TX_TX0DBMENBLEEDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENBLEEDREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENBLEEDREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDREG_DEFAULT (_RAC_TX_TX0DBMENBLEEDREG_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDREG_disable (_RAC_TX_TX0DBMENBLEEDREG_disable << 2) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDREG_enable (_RAC_TX_TX0DBMENBLEEDREG_enable << 2) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENREG (0x1UL << 3) /**< TX0DBMENREG */ +#define _RAC_TX_TX0DBMENREG_SHIFT 3 /**< Shift value for RAC_TX0DBMENREG */ +#define _RAC_TX_TX0DBMENREG_MASK 0x8UL /**< Bit mask for RAC_TX0DBMENREG */ +#define _RAC_TX_TX0DBMENREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENREG_DEFAULT (_RAC_TX_TX0DBMENREG_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENREG_disable (_RAC_TX_TX0DBMENREG_disable << 3) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENREG_enable (_RAC_TX_TX0DBMENREG_enable << 3) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENBIAS (0x1UL << 5) /**< TX0DBMENBIAS */ +#define _RAC_TX_TX0DBMENBIAS_SHIFT 5 /**< Shift value for RAC_TX0DBMENBIAS */ +#define _RAC_TX_TX0DBMENBIAS_MASK 0x20UL /**< Bit mask for RAC_TX0DBMENBIAS */ +#define _RAC_TX_TX0DBMENBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENBIAS_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENBIAS_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENBIAS_DEFAULT (_RAC_TX_TX0DBMENBIAS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENBIAS_disable (_RAC_TX_TX0DBMENBIAS_disable << 5) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENBIAS_enable (_RAC_TX_TX0DBMENBIAS_enable << 5) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRV (0x1UL << 6) /**< TX0DBMENPREDRV */ +#define _RAC_TX_TX0DBMENPREDRV_SHIFT 6 /**< Shift value for RAC_TX0DBMENPREDRV */ +#define _RAC_TX_TX0DBMENPREDRV_MASK 0x40UL /**< Bit mask for RAC_TX0DBMENPREDRV */ +#define _RAC_TX_TX0DBMENPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRV_DEFAULT (_RAC_TX_TX0DBMENPREDRV_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRV_disable (_RAC_TX_TX0DBMENPREDRV_disable << 6) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRV_enable (_RAC_TX_TX0DBMENPREDRV_enable << 6) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREG (0x1UL << 7) /**< TX0DBMENPREDRVREG */ +#define _RAC_TX_TX0DBMENPREDRVREG_SHIFT 7 /**< Shift value for RAC_TX0DBMENPREDRVREG */ +#define _RAC_TX_TX0DBMENPREDRVREG_MASK 0x80UL /**< Bit mask for RAC_TX0DBMENPREDRVREG */ +#define _RAC_TX_TX0DBMENPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREG_DEFAULT (_RAC_TX_TX0DBMENPREDRVREG_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREG_disable (_RAC_TX_TX0DBMENPREDRVREG_disable << 7) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREG_enable (_RAC_TX_TX0DBMENPREDRVREG_enable << 7) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREGBIAS (0x1UL << 8) /**< TX0DBMENPREDRVREGBIAS */ +#define _RAC_TX_TX0DBMENPREDRVREGBIAS_SHIFT 8 /**< Shift value for RAC_TX0DBMENPREDRVREGBIAS */ +#define _RAC_TX_TX0DBMENPREDRVREGBIAS_MASK 0x100UL /**< Bit mask for RAC_TX0DBMENPREDRVREGBIAS */ +#define _RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRVREGBIAS_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENPREDRVREGBIAS_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT (_RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREGBIAS_disable (_RAC_TX_TX0DBMENPREDRVREGBIAS_disable << 8) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENPREDRVREGBIAS_enable (_RAC_TX_TX0DBMENPREDRVREGBIAS_enable << 8) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENRAMPCLK (0x1UL << 9) /**< TX0DBMENRAMPCLK */ +#define _RAC_TX_TX0DBMENRAMPCLK_SHIFT 9 /**< Shift value for RAC_TX0DBMENRAMPCLK */ +#define _RAC_TX_TX0DBMENRAMPCLK_MASK 0x200UL /**< Bit mask for RAC_TX0DBMENRAMPCLK */ +#define _RAC_TX_TX0DBMENRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENRAMPCLK_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENRAMPCLK_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENRAMPCLK_DEFAULT (_RAC_TX_TX0DBMENRAMPCLK_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENRAMPCLK_disable (_RAC_TX_TX0DBMENRAMPCLK_disable << 9) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENRAMPCLK_enable (_RAC_TX_TX0DBMENRAMPCLK_enable << 9) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDPREDRVREG (0x1UL << 10) /**< TX0DBMENBLEEDPREDRVREG */ +#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_SHIFT 10 /**< Shift value for RAC_TX0DBMENBLEEDPREDRVREG */ +#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_MASK 0x400UL /**< Bit mask for RAC_TX0DBMENBLEEDPREDRVREG */ +#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT (_RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDPREDRVREG_disable (_RAC_TX_TX0DBMENBLEEDPREDRVREG_disable << 10) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TX0DBMENBLEEDPREDRVREG_enable (_RAC_TX_TX0DBMENBLEEDPREDRVREG_enable << 10) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDPREDRVREG (0x1UL << 12) /**< TXPAENBLEEDPREDRVREG */ +#define _RAC_TX_TXPAENBLEEDPREDRVREG_SHIFT 12 /**< Shift value for RAC_TXPAENBLEEDPREDRVREG */ +#define _RAC_TX_TXPAENBLEEDPREDRVREG_MASK 0x1000UL /**< Bit mask for RAC_TXPAENBLEEDPREDRVREG */ +#define _RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENBLEEDPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAENBLEEDPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT (_RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENBLEEDPREDRVREG_disable (_RAC_TX_TXPAENBLEEDPREDRVREG_disable << 12) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDPREDRVREG_enable (_RAC_TX_TXPAENBLEEDPREDRVREG_enable << 12) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDREG (0x1UL << 13) /**< TXPAENBLEEDREG */ +#define _RAC_TX_TXPAENBLEEDREG_SHIFT 13 /**< Shift value for RAC_TXPAENBLEEDREG */ +#define _RAC_TX_TXPAENBLEEDREG_MASK 0x2000UL /**< Bit mask for RAC_TXPAENBLEEDREG */ +#define _RAC_TX_TXPAENBLEEDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENBLEEDREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAENBLEEDREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDREG_DEFAULT (_RAC_TX_TXPAENBLEEDREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENBLEEDREG_disable (_RAC_TX_TXPAENBLEEDREG_disable << 13) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAENBLEEDREG_enable (_RAC_TX_TXPAENBLEEDREG_enable << 13) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAENPAOUT (0x1UL << 14) /**< TXPAENPAOUT */ +#define _RAC_TX_TXPAENPAOUT_SHIFT 14 /**< Shift value for RAC_TXPAENPAOUT */ +#define _RAC_TX_TXPAENPAOUT_MASK 0x4000UL /**< Bit mask for RAC_TXPAENPAOUT */ +#define _RAC_TX_TXPAENPAOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENPAOUT_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAENPAOUT_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAENPAOUT_DEFAULT (_RAC_TX_TXPAENPAOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENPAOUT_disable (_RAC_TX_TXPAENPAOUT_disable << 14) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAENPAOUT_enable (_RAC_TX_TXPAENPAOUT_enable << 14) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAENPREDRVREG (0x1UL << 15) /**< TXPAENPREDRVREG */ +#define _RAC_TX_TXPAENPREDRVREG_SHIFT 15 /**< Shift value for RAC_TXPAENPREDRVREG */ +#define _RAC_TX_TXPAENPREDRVREG_MASK 0x8000UL /**< Bit mask for RAC_TXPAENPREDRVREG */ +#define _RAC_TX_TXPAENPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAENPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAENPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAENPREDRVREG_DEFAULT (_RAC_TX_TXPAENPREDRVREG_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAENPREDRVREG_disable (_RAC_TX_TXPAENPREDRVREG_disable << 15) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAENPREDRVREG_enable (_RAC_TX_TXPAENPREDRVREG_enable << 15) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_SYCHPBIASTRIMBUFTX (0x1UL << 16) /**< SYCHPBIASTRIMBUFTX */ +#define _RAC_TX_SYCHPBIASTRIMBUFTX_SHIFT 16 /**< Shift value for RAC_SYCHPBIASTRIMBUFTX */ +#define _RAC_TX_SYCHPBIASTRIMBUFTX_MASK 0x10000UL /**< Bit mask for RAC_SYCHPBIASTRIMBUFTX */ +#define _RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u 0x00000000UL /**< Mode i_tail_10u for RAC_TX */ +#define _RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u 0x00000001UL /**< Mode i_tail_20u for RAC_TX */ +#define RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT (_RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u (_RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u << 16) /**< Shifted mode i_tail_10u for RAC_TX */ +#define RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u (_RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u << 16) /**< Shifted mode i_tail_20u for RAC_TX */ +#define RAC_TX_SYPFDCHPLPENTX (0x1UL << 17) /**< SYPFDCHPLPENTX */ +#define _RAC_TX_SYPFDCHPLPENTX_SHIFT 17 /**< Shift value for RAC_SYPFDCHPLPENTX */ +#define _RAC_TX_SYPFDCHPLPENTX_MASK 0x20000UL /**< Bit mask for RAC_SYPFDCHPLPENTX */ +#define _RAC_TX_SYPFDCHPLPENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_SYPFDCHPLPENTX_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_SYPFDCHPLPENTX_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_SYPFDCHPLPENTX_DEFAULT (_RAC_TX_SYPFDCHPLPENTX_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_SYPFDCHPLPENTX_disable (_RAC_TX_SYPFDCHPLPENTX_disable << 17) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_SYPFDCHPLPENTX_enable (_RAC_TX_SYPFDCHPLPENTX_enable << 17) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_SYPFDFPWENTX (0x1UL << 18) /**< SYPFDFPWENTX */ +#define _RAC_TX_SYPFDFPWENTX_SHIFT 18 /**< Shift value for RAC_SYPFDFPWENTX */ +#define _RAC_TX_SYPFDFPWENTX_MASK 0x40000UL /**< Bit mask for RAC_SYPFDFPWENTX */ +#define _RAC_TX_SYPFDFPWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_SYPFDFPWENTX_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_SYPFDFPWENTX_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_SYPFDFPWENTX_DEFAULT (_RAC_TX_SYPFDFPWENTX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_SYPFDFPWENTX_disable (_RAC_TX_SYPFDFPWENTX_disable << 18) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_SYPFDFPWENTX_enable (_RAC_TX_SYPFDFPWENTX_enable << 18) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBM (0x1UL << 19) /**< TXPAEN10DBM */ +#define _RAC_TX_TXPAEN10DBM_SHIFT 19 /**< Shift value for RAC_TXPAEN10DBM */ +#define _RAC_TX_TXPAEN10DBM_MASK 0x80000UL /**< Bit mask for RAC_TXPAEN10DBM */ +#define _RAC_TX_TXPAEN10DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN10DBM_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN10DBM_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBM_DEFAULT (_RAC_TX_TXPAEN10DBM_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN10DBM_disable (_RAC_TX_TXPAEN10DBM_disable << 19) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN10DBM_enable (_RAC_TX_TXPAEN10DBM_enable << 19) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMMAINCTAP (0x1UL << 20) /**< TXPAEN10DBMMAINCTAP */ +#define _RAC_TX_TXPAEN10DBMMAINCTAP_SHIFT 20 /**< Shift value for RAC_TXPAEN10DBMMAINCTAP */ +#define _RAC_TX_TXPAEN10DBMMAINCTAP_MASK 0x100000UL /**< Bit mask for RAC_TXPAEN10DBMMAINCTAP */ +#define _RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis 0x00000000UL /**< Mode ctap_main_dis for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en 0x00000001UL /**< Mode ctap_main_en for RAC_TX */ +#define RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT (_RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis (_RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis << 20) /**< Shifted mode ctap_main_dis for RAC_TX */ +#define RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en (_RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en << 20) /**< Shifted mode ctap_main_en for RAC_TX */ +#define RAC_TX_TXPAEN10DBMPREDRV (0x1UL << 21) /**< TXPAEN10DBMPREDRV */ +#define _RAC_TX_TXPAEN10DBMPREDRV_SHIFT 21 /**< Shift value for RAC_TXPAEN10DBMPREDRV */ +#define _RAC_TX_TXPAEN10DBMPREDRV_MASK 0x200000UL /**< Bit mask for RAC_TXPAEN10DBMPREDRV */ +#define _RAC_TX_TXPAEN10DBMPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMPREDRV_DEFAULT (_RAC_TX_TXPAEN10DBMPREDRV_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN10DBMPREDRV_disable (_RAC_TX_TXPAEN10DBMPREDRV_disable << 21) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMPREDRV_enable (_RAC_TX_TXPAEN10DBMPREDRV_enable << 21) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMVMID (0x1UL << 22) /**< TXPAEN10DBMVMID */ +#define _RAC_TX_TXPAEN10DBMVMID_SHIFT 22 /**< Shift value for RAC_TXPAEN10DBMVMID */ +#define _RAC_TX_TXPAEN10DBMVMID_MASK 0x400000UL /**< Bit mask for RAC_TXPAEN10DBMVMID */ +#define _RAC_TX_TXPAEN10DBMVMID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMVMID_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN10DBMVMID_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMVMID_DEFAULT (_RAC_TX_TXPAEN10DBMVMID_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN10DBMVMID_disable (_RAC_TX_TXPAEN10DBMVMID_disable << 22) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN10DBMVMID_enable (_RAC_TX_TXPAEN10DBMVMID_enable << 22) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBM (0x1UL << 23) /**< TXPAEN20DBM */ +#define _RAC_TX_TXPAEN20DBM_SHIFT 23 /**< Shift value for RAC_TXPAEN20DBM */ +#define _RAC_TX_TXPAEN20DBM_MASK 0x800000UL /**< Bit mask for RAC_TXPAEN20DBM */ +#define _RAC_TX_TXPAEN20DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN20DBM_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN20DBM_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBM_DEFAULT (_RAC_TX_TXPAEN20DBM_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN20DBM_disable (_RAC_TX_TXPAEN20DBM_disable << 23) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN20DBM_enable (_RAC_TX_TXPAEN20DBM_enable << 23) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMMAINCTAP (0x1UL << 24) /**< TXPAEN20DBMMAINCTAP */ +#define _RAC_TX_TXPAEN20DBMMAINCTAP_SHIFT 24 /**< Shift value for RAC_TXPAEN20DBMMAINCTAP */ +#define _RAC_TX_TXPAEN20DBMMAINCTAP_MASK 0x1000000UL /**< Bit mask for RAC_TXPAEN20DBMMAINCTAP */ +#define _RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis 0x00000000UL /**< Mode ctap_main_dis for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en 0x00000001UL /**< Mode ctap_main_en for RAC_TX */ +#define RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT (_RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis (_RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis << 24) /**< Shifted mode ctap_main_dis for RAC_TX */ +#define RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en (_RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en << 24) /**< Shifted mode ctap_main_en for RAC_TX */ +#define RAC_TX_TXPAEN20DBMPREDRV (0x1UL << 25) /**< TXPAEN20DBMPREDRV */ +#define _RAC_TX_TXPAEN20DBMPREDRV_SHIFT 25 /**< Shift value for RAC_TXPAEN20DBMPREDRV */ +#define _RAC_TX_TXPAEN20DBMPREDRV_MASK 0x2000000UL /**< Bit mask for RAC_TXPAEN20DBMPREDRV */ +#define _RAC_TX_TXPAEN20DBMPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMPREDRV_DEFAULT (_RAC_TX_TXPAEN20DBMPREDRV_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN20DBMPREDRV_disable (_RAC_TX_TXPAEN20DBMPREDRV_disable << 25) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMPREDRV_enable (_RAC_TX_TXPAEN20DBMPREDRV_enable << 25) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVMID (0x1UL << 26) /**< TXPAEN20DBMVMID */ +#define _RAC_TX_TXPAEN20DBMVMID_SHIFT 26 /**< Shift value for RAC_TXPAEN20DBMVMID */ +#define _RAC_TX_TXPAEN20DBMVMID_MASK 0x4000000UL /**< Bit mask for RAC_TXPAEN20DBMVMID */ +#define _RAC_TX_TXPAEN20DBMVMID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMVMID_disable 0x00000000UL /**< Mode disable for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMVMID_enable 0x00000001UL /**< Mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVMID_DEFAULT (_RAC_TX_TXPAEN20DBMVMID_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVMID_disable (_RAC_TX_TXPAEN20DBMVMID_disable << 26) /**< Shifted mode disable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVMID_enable (_RAC_TX_TXPAEN20DBMVMID_enable << 26) /**< Shifted mode enable for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVBIASHF (0x1UL << 27) /**< TXPAEN20DBMVBIASHF */ +#define _RAC_TX_TXPAEN20DBMVBIASHF_SHIFT 27 /**< Shift value for RAC_TXPAEN20DBMVBIASHF */ +#define _RAC_TX_TXPAEN20DBMVBIASHF_MASK 0x8000000UL /**< Bit mask for RAC_TXPAEN20DBMVBIASHF */ +#define _RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMVBIASHF_disable_bias 0x00000000UL /**< Mode disable_bias for RAC_TX */ +#define _RAC_TX_TXPAEN20DBMVBIASHF_enable_bias 0x00000001UL /**< Mode enable_bias for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT (_RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVBIASHF_disable_bias (_RAC_TX_TXPAEN20DBMVBIASHF_disable_bias << 27) /**< Shifted mode disable_bias for RAC_TX */ +#define RAC_TX_TXPAEN20DBMVBIASHF_enable_bias (_RAC_TX_TXPAEN20DBMVBIASHF_enable_bias << 27) /**< Shifted mode enable_bias for RAC_TX */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_SHIFT 28 /**< Shift value for RAC_TXPATRIM20DBMVBIASHF */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_MASK 0x30000000UL /**< Bit mask for RAC_TXPATRIM20DBMVBIASHF */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss 0x00000000UL /**< Mode bias_avss for RAC_TX */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_low 0x00000001UL /**< Mode bias_low for RAC_TX */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid 0x00000002UL /**< Mode bias_mid for RAC_TX */ +#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_high 0x00000003UL /**< Mode bias_high for RAC_TX */ +#define RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT (_RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss << 28) /**< Shifted mode bias_avss for RAC_TX */ +#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_low (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_low << 28) /**< Shifted mode bias_low for RAC_TX */ +#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid << 28) /**< Shifted mode bias_mid for RAC_TX */ +#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_high (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_high << 28) /**< Shifted mode bias_high for RAC_TX */ +#define RAC_TX_ENPAPOWER (0x1UL << 30) /**< Override */ +#define _RAC_TX_ENPAPOWER_SHIFT 30 /**< Shift value for RAC_ENPAPOWER */ +#define _RAC_TX_ENPAPOWER_MASK 0x40000000UL /**< Bit mask for RAC_ENPAPOWER */ +#define _RAC_TX_ENPAPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define RAC_TX_ENPAPOWER_DEFAULT (_RAC_TX_ENPAPOWER_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_TX */ +#define RAC_TX_ENPASELSLICE (0x1UL << 31) /**< Override */ +#define _RAC_TX_ENPASELSLICE_SHIFT 31 /**< Shift value for RAC_ENPASELSLICE */ +#define _RAC_TX_ENPASELSLICE_MASK 0x80000000UL /**< Bit mask for RAC_ENPASELSLICE */ +#define _RAC_TX_ENPASELSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */ +#define RAC_TX_ENPASELSLICE_DEFAULT (_RAC_TX_ENPASELSLICE_DEFAULT << 31) /**< Shifted mode DEFAULT for RAC_TX */ + +/* Bit fields for RAC SYTRIM0 */ +#define _RAC_SYTRIM0_RESETVALUE 0x018FF169UL /**< Default value for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_MASK 0x0FFFFFFFUL /**< Mask for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPBIAS_SHIFT 0 /**< Shift value for RAC_SYCHPBIAS */ +#define _RAC_SYTRIM0_SYCHPBIAS_MASK 0x7UL /**< Bit mask for RAC_SYCHPBIAS */ +#define _RAC_SYTRIM0_SYCHPBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPBIAS_bias_0 0x00000000UL /**< Mode bias_0 for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPBIAS_bias_1 0x00000001UL /**< Mode bias_1 for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPBIAS_bias_2 0x00000003UL /**< Mode bias_2 for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPBIAS_bias_3 0x00000007UL /**< Mode bias_3 for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPBIAS_DEFAULT (_RAC_SYTRIM0_SYCHPBIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPBIAS_bias_0 (_RAC_SYTRIM0_SYCHPBIAS_bias_0 << 0) /**< Shifted mode bias_0 for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPBIAS_bias_1 (_RAC_SYTRIM0_SYCHPBIAS_bias_1 << 0) /**< Shifted mode bias_1 for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPBIAS_bias_2 (_RAC_SYTRIM0_SYCHPBIAS_bias_2 << 0) /**< Shifted mode bias_2 for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPBIAS_bias_3 (_RAC_SYTRIM0_SYCHPBIAS_bias_3 << 0) /**< Shifted mode bias_3 for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_SHIFT 3 /**< Shift value for RAC_SYCHPCURRRX */ +#define _RAC_SYTRIM0_SYCHPCURRRX_MASK 0x38UL /**< Bit mask for RAC_SYCHPCURRRX */ +#define _RAC_SYTRIM0_SYCHPCURRRX_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA 0x00000000UL /**< Mode curr_1p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA 0x00000001UL /**< Mode curr_2p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA 0x00000002UL /**< Mode curr_2p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA 0x00000003UL /**< Mode curr_3p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA 0x00000004UL /**< Mode curr_3p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA 0x00000005UL /**< Mode curr_4p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA 0x00000006UL /**< Mode curr_4p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA 0x00000007UL /**< Mode curr_5p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_DEFAULT (_RAC_SYTRIM0_SYCHPCURRRX_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA << 3) /**< Shifted mode curr_1p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA << 3) /**< Shifted mode curr_2p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA << 3) /**< Shifted mode curr_2p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA << 3) /**< Shifted mode curr_3p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA << 3) /**< Shifted mode curr_3p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA << 3) /**< Shifted mode curr_4p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA << 3) /**< Shifted mode curr_4p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA << 3) /**< Shifted mode curr_5p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_SHIFT 6 /**< Shift value for RAC_SYCHPCURRTX */ +#define _RAC_SYTRIM0_SYCHPCURRTX_MASK 0x1C0UL /**< Bit mask for RAC_SYCHPCURRTX */ +#define _RAC_SYTRIM0_SYCHPCURRTX_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA 0x00000000UL /**< Mode curr_1p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA 0x00000001UL /**< Mode curr_2p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA 0x00000002UL /**< Mode curr_2p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA 0x00000003UL /**< Mode curr_3p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA 0x00000004UL /**< Mode curr_3p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA 0x00000005UL /**< Mode curr_4p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA 0x00000006UL /**< Mode curr_4p5uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA 0x00000007UL /**< Mode curr_5p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_DEFAULT (_RAC_SYTRIM0_SYCHPCURRTX_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA << 6) /**< Shifted mode curr_1p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA << 6) /**< Shifted mode curr_2p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA << 6) /**< Shifted mode curr_2p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA << 6) /**< Shifted mode curr_3p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA << 6) /**< Shifted mode curr_3p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA << 6) /**< Shifted mode curr_4p0uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA << 6) /**< Shifted mode curr_4p5uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA << 6) /**< Shifted mode curr_5p0uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVNSRC_SHIFT 9 /**< Shift value for RAC_SYCHPLEVNSRC */ +#define _RAC_SYTRIM0_SYCHPLEVNSRC_MASK 0xE00UL /**< Bit mask for RAC_SYCHPLEVNSRC */ +#define _RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT (_RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_SHIFT 12 /**< Shift value for RAC_SYCHPLEVPSRCRX */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_MASK 0x7000UL /**< Bit mask for RAC_SYCHPLEVPSRCRX */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m 0x00000000UL /**< Mode vsrcp_n105m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m 0x00000001UL /**< Mode vsrcp_n90m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m 0x00000002UL /**< Mode vsrcp_n75m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m 0x00000003UL /**< Mode vsrcp_n60m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m 0x00000004UL /**< Mode vsrcp_n45m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m 0x00000005UL /**< Mode vsrcp_n30m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m 0x00000006UL /**< Mode vsrcp_n15m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m 0x00000007UL /**< Mode vsrcp_n0m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT (_RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m << 12) /**< Shifted mode vsrcp_n105m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m << 12) /**< Shifted mode vsrcp_n90m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m << 12) /**< Shifted mode vsrcp_n75m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m << 12) /**< Shifted mode vsrcp_n60m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m << 12) /**< Shifted mode vsrcp_n45m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m << 12) /**< Shifted mode vsrcp_n30m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m << 12) /**< Shifted mode vsrcp_n15m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m << 12) /**< Shifted mode vsrcp_n0m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_SHIFT 15 /**< Shift value for RAC_SYCHPLEVPSRCTX */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_MASK 0x38000UL /**< Bit mask for RAC_SYCHPLEVPSRCTX */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m 0x00000000UL /**< Mode vsrcp_n105m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m 0x00000001UL /**< Mode vsrcp_n90m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m 0x00000002UL /**< Mode vsrcp_n75m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m 0x00000003UL /**< Mode vsrcp_n60m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m 0x00000004UL /**< Mode vsrcp_n45m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m 0x00000005UL /**< Mode vsrcp_n30m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m 0x00000006UL /**< Mode vsrcp_n15m for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m 0x00000007UL /**< Mode vsrcp_n0m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT (_RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m << 15) /**< Shifted mode vsrcp_n105m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m << 15) /**< Shifted mode vsrcp_n90m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m << 15) /**< Shifted mode vsrcp_n75m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m << 15) /**< Shifted mode vsrcp_n60m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m << 15) /**< Shifted mode vsrcp_n45m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m << 15) /**< Shifted mode vsrcp_n30m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m << 15) /**< Shifted mode vsrcp_n15m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m << 15) /**< Shifted mode vsrcp_n0m for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENRX (0x1UL << 18) /**< SYCHPSRCENRX */ +#define _RAC_SYTRIM0_SYCHPSRCENRX_SHIFT 18 /**< Shift value for RAC_SYCHPSRCENRX */ +#define _RAC_SYTRIM0_SYCHPSRCENRX_MASK 0x40000UL /**< Bit mask for RAC_SYCHPSRCENRX */ +#define _RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPSRCENRX_disable 0x00000000UL /**< Mode disable for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPSRCENRX_enable 0x00000001UL /**< Mode enable for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT (_RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENRX_disable (_RAC_SYTRIM0_SYCHPSRCENRX_disable << 18) /**< Shifted mode disable for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENRX_enable (_RAC_SYTRIM0_SYCHPSRCENRX_enable << 18) /**< Shifted mode enable for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENTX (0x1UL << 19) /**< SYCHPSRCENTX */ +#define _RAC_SYTRIM0_SYCHPSRCENTX_SHIFT 19 /**< Shift value for RAC_SYCHPSRCENTX */ +#define _RAC_SYTRIM0_SYCHPSRCENTX_MASK 0x80000UL /**< Bit mask for RAC_SYCHPSRCENTX */ +#define _RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPSRCENTX_disable 0x00000000UL /**< Mode disable for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPSRCENTX_enable 0x00000001UL /**< Mode enable for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT (_RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENTX_disable (_RAC_SYTRIM0_SYCHPSRCENTX_disable << 19) /**< Shifted mode disable for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPSRCENTX_enable (_RAC_SYTRIM0_SYCHPSRCENTX_enable << 19) /**< Shifted mode enable for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_SHIFT 20 /**< Shift value for RAC_SYCHPREPLICACURRADJ */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_MASK 0x700000UL /**< Bit mask for RAC_SYCHPREPLICACURRADJ */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua 0x00000000UL /**< Mode load_8ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua 0x00000001UL /**< Mode load_16ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua 0x00000002UL /**< Mode load_20ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua 0x00000003UL /**< Mode load_28ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua 0x00000004UL /**< Mode load_24ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua 0x00000005UL /**< Mode load_32ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua 0x00000006UL /**< Mode load_36ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua 0x00000007UL /**< Mode load_44ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua << 20) /**< Shifted mode load_8ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua << 20) /**< Shifted mode load_16ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua << 20) /**< Shifted mode load_20ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua << 20) /**< Shifted mode load_28ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua << 20) /**< Shifted mode load_24ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua << 20) /**< Shifted mode load_32ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua << 20) /**< Shifted mode load_36ua for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua << 20) /**< Shifted mode load_44ua for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_SHIFT 23 /**< Shift value for RAC_SYTRIMCHPREGAMPBIAS */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_MASK 0x3800000UL /**< Bit mask for RAC_SYTRIMCHPREGAMPBIAS */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA 0x00000000UL /**< Mode bias_14uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA 0x00000001UL /**< Mode bias_20uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA 0x00000002UL /**< Mode bias_26uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA 0x00000003UL /**< Mode bias_32uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA 0x00000004UL /**< Mode bias_38uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA 0x00000005UL /**< Mode bias_44uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA 0x00000006UL /**< Mode bias_50uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA 0x00000007UL /**< Mode bias_56uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA << 23) /**< Shifted mode bias_14uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA << 23) /**< Shifted mode bias_20uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA << 23) /**< Shifted mode bias_26uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA << 23) /**< Shifted mode bias_32uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA << 23) /**< Shifted mode bias_38uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA << 23) /**< Shifted mode bias_44uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA << 23) /**< Shifted mode bias_50uA for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA << 23) /**< Shifted mode bias_56uA for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_SHIFT 26 /**< Shift value for RAC_SYTRIMCHPREGAMPBW */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_MASK 0xC000000UL /**< Bit mask for RAC_SYTRIMCHPREGAMPBW */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f 0x00000000UL /**< Mode C_000f for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f 0x00000001UL /**< Mode C_300f for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f 0x00000002UL /**< Mode C_600f for RAC_SYTRIM0 */ +#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f 0x00000003UL /**< Mode C_900f for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f << 26) /**< Shifted mode C_000f for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f << 26) /**< Shifted mode C_300f for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f << 26) /**< Shifted mode C_600f for RAC_SYTRIM0 */ +#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f << 26) /**< Shifted mode C_900f for RAC_SYTRIM0 */ + +/* Bit fields for RAC SYTRIM1 */ +#define _RAC_SYTRIM1_RESETVALUE 0x1FE00410UL /**< Default value for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_MASK 0xFFFC0FFFUL /**< Mask for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_SHIFT 0 /**< Shift value for RAC_SYLODIVLDOTRIMCORERX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_MASK 0x3UL /**< Bit mask for RAC_SYLODIVLDOTRIMCORERX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO 0x00000000UL /**< Mode RXLO for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO 0x00000003UL /**< Mode TXLO for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO << 0) /**< Shifted mode RXLO for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO << 0) /**< Shifted mode TXLO for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_SHIFT 2 /**< Shift value for RAC_SYLODIVLDOTRIMCORETX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_MASK 0xCUL /**< Bit mask for RAC_SYLODIVLDOTRIMCORETX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO 0x00000000UL /**< Mode RXLO for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO 0x00000003UL /**< Mode TXLO for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO << 2) /**< Shifted mode RXLO for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO << 2) /**< Shifted mode TXLO for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_SHIFT 4 /**< Shift value for RAC_SYLODIVLDOTRIMNDIORX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_MASK 0xF0UL /**< Bit mask for RAC_SYLODIVLDOTRIMNDIORX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 0x00000000UL /**< Mode vreg_1p08 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 0x00000001UL /**< Mode vreg_1p11 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 0x00000002UL /**< Mode vreg_1p15 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 0x00000003UL /**< Mode vreg_1p18 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 0x00000004UL /**< Mode vreg_1p21 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 0x00000005UL /**< Mode vreg_1p24 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 0x00000006UL /**< Mode vreg_1p27 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 0x00000007UL /**< Mode vreg_1p29 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 0x00000008UL /**< Mode vreg_1p32 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 0x00000009UL /**< Mode vreg_1p34 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 << 4) /**< Shifted mode vreg_1p08 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 << 4) /**< Shifted mode vreg_1p11 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 << 4) /**< Shifted mode vreg_1p15 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 << 4) /**< Shifted mode vreg_1p18 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 << 4) /**< Shifted mode vreg_1p21 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 << 4) /**< Shifted mode vreg_1p24 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 << 4) /**< Shifted mode vreg_1p27 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 << 4) /**< Shifted mode vreg_1p29 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 << 4) /**< Shifted mode vreg_1p32 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 << 4) /**< Shifted mode vreg_1p34 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_SHIFT 8 /**< Shift value for RAC_SYLODIVLDOTRIMNDIOTX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_MASK 0xF00UL /**< Bit mask for RAC_SYLODIVLDOTRIMNDIOTX */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 0x00000000UL /**< Mode vreg_1p08 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 0x00000001UL /**< Mode vreg_1p11 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 0x00000002UL /**< Mode vreg_1p15 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 0x00000003UL /**< Mode vreg_1p18 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 0x00000004UL /**< Mode vreg_1p21 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 0x00000005UL /**< Mode vreg_1p24 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 0x00000006UL /**< Mode vreg_1p27 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 0x00000007UL /**< Mode vreg_1p29 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 0x00000008UL /**< Mode vreg_1p32 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 0x00000009UL /**< Mode vreg_1p34 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 << 8) /**< Shifted mode vreg_1p08 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 << 8) /**< Shifted mode vreg_1p11 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 << 8) /**< Shifted mode vreg_1p15 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 << 8) /**< Shifted mode vreg_1p18 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 << 8) /**< Shifted mode vreg_1p21 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 << 8) /**< Shifted mode vreg_1p24 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 << 8) /**< Shifted mode vreg_1p27 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 << 8) /**< Shifted mode vreg_1p29 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 << 8) /**< Shifted mode vreg_1p32 for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 << 8) /**< Shifted mode vreg_1p34 for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_SHIFT 18 /**< Shift value for RAC_SYLODIVTLO20DBM2G4DELAY */ +#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_MASK 0x1C0000UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4DELAY */ +#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT (_RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_SHIFT 21 /**< Shift value for RAC_SYMMDREPLICA1CURRADJ */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_MASK 0xE00000UL /**< Bit mask for RAC_SYMMDREPLICA1CURRADJ */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua 0x00000000UL /**< Mode load_8ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u 0x00000001UL /**< Mode load_16u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua 0x00000002UL /**< Mode load_20ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua 0x00000003UL /**< Mode load_28ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua 0x00000004UL /**< Mode load_24ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua 0x00000005UL /**< Mode load_32ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua 0x00000006UL /**< Mode load_36ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua 0x00000007UL /**< Mode load_44ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua << 21) /**< Shifted mode load_8ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u << 21) /**< Shifted mode load_16u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua << 21) /**< Shifted mode load_20ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua << 21) /**< Shifted mode load_28ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua << 21) /**< Shifted mode load_24ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua << 21) /**< Shifted mode load_32ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua << 21) /**< Shifted mode load_36ua for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua << 21) /**< Shifted mode load_44ua for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_SHIFT 24 /**< Shift value for RAC_SYMMDREPLICA2CURRADJ */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_MASK 0x7000000UL /**< Bit mask for RAC_SYMMDREPLICA2CURRADJ */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u 0x00000000UL /**< Mode load_32u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u 0x00000001UL /**< Mode load_64u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u 0x00000002UL /**< Mode load_96u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u 0x00000003UL /**< Mode load_128u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u 0x00000004UL /**< Mode load_160u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u 0x00000005UL /**< Mode load_192u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u 0x00000006UL /**< Mode load_224u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u 0x00000007UL /**< Mode load_256u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u << 24) /**< Shifted mode load_32u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u << 24) /**< Shifted mode load_64u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u << 24) /**< Shifted mode load_96u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u << 24) /**< Shifted mode load_128u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u << 24) /**< Shifted mode load_160u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u << 24) /**< Shifted mode load_192u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u << 24) /**< Shifted mode load_224u for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u << 24) /**< Shifted mode load_256u for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_SHIFT 27 /**< Shift value for RAC_SYTRIMMMDREGAMPBIAS */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_MASK 0x38000000UL /**< Bit mask for RAC_SYTRIMMMDREGAMPBIAS */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA 0x00000000UL /**< Mode bias_14uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA 0x00000001UL /**< Mode bias_20uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA 0x00000002UL /**< Mode bias_26uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA 0x00000003UL /**< Mode bias_32uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA 0x00000004UL /**< Mode bias_38uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA 0x00000005UL /**< Mode bias_44uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA 0x00000006UL /**< Mode bias_50uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA 0x00000007UL /**< Mode bias_56uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA << 27) /**< Shifted mode bias_14uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA << 27) /**< Shifted mode bias_20uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA << 27) /**< Shifted mode bias_26uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA << 27) /**< Shifted mode bias_32uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA << 27) /**< Shifted mode bias_38uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA << 27) /**< Shifted mode bias_44uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA << 27) /**< Shifted mode bias_50uA for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA << 27) /**< Shifted mode bias_56uA for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_SHIFT 30 /**< Shift value for RAC_SYTRIMMMDREGAMPBW */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_MASK 0xC0000000UL /**< Bit mask for RAC_SYTRIMMMDREGAMPBW */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f 0x00000000UL /**< Mode C_000f for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f 0x00000001UL /**< Mode C_300f for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f 0x00000002UL /**< Mode C_600f for RAC_SYTRIM1 */ +#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f 0x00000003UL /**< Mode C_900f for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f << 30) /**< Shifted mode C_000f for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f << 30) /**< Shifted mode C_300f for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f << 30) /**< Shifted mode C_600f for RAC_SYTRIM1 */ +#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f << 30) /**< Shifted mode C_900f for RAC_SYTRIM1 */ + +/* Bit fields for RAC SYCAL */ +#define _RAC_SYCAL_RESETVALUE 0x01008100UL /**< Default value for RAC_SYCAL */ +#define _RAC_SYCAL_MASK 0x03018700UL /**< Mask for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMODEPKD (0x1UL << 8) /**< SYVCOMODEPKD */ +#define _RAC_SYCAL_SYVCOMODEPKD_SHIFT 8 /**< Shift value for RAC_SYVCOMODEPKD */ +#define _RAC_SYCAL_SYVCOMODEPKD_MASK 0x100UL /**< Bit mask for RAC_SYVCOMODEPKD */ +#define _RAC_SYCAL_SYVCOMODEPKD_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 0x00000000UL /**< Mode t_openloop_0 for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 0x00000001UL /**< Mode t_pkdetect_1 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMODEPKD_DEFAULT (_RAC_SYCAL_SYVCOMODEPKD_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 (_RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 << 8) /**< Shifted mode t_openloop_0 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 (_RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 << 8) /**< Shifted mode t_pkdetect_1 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMORECURRENT (0x1UL << 9) /**< SYVCOMORECURRENT */ +#define _RAC_SYCAL_SYVCOMORECURRENT_SHIFT 9 /**< Shift value for RAC_SYVCOMORECURRENT */ +#define _RAC_SYCAL_SYVCOMORECURRENT_MASK 0x200UL /**< Bit mask for RAC_SYVCOMORECURRENT */ +#define _RAC_SYCAL_SYVCOMORECURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOMORECURRENT_more_current_0 0x00000000UL /**< Mode more_current_0 for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOMORECURRENT_more_current_1 0x00000001UL /**< Mode more_current_1 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMORECURRENT_DEFAULT (_RAC_SYCAL_SYVCOMORECURRENT_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMORECURRENT_more_current_0 (_RAC_SYCAL_SYVCOMORECURRENT_more_current_0 << 9) /**< Shifted mode more_current_0 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOMORECURRENT_more_current_1 (_RAC_SYCAL_SYVCOMORECURRENT_more_current_1 << 9) /**< Shifted mode more_current_1 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOSLOWNOISEFILTER (0x1UL << 10) /**< SYVCOSLOWNOISEFILTER */ +#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_SHIFT 10 /**< Shift value for RAC_SYVCOSLOWNOISEFILTER */ +#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_MASK 0x400UL /**< Bit mask for RAC_SYVCOSLOWNOISEFILTER */ +#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 0x00000000UL /**< Mode slow_noise_filter_0 for RAC_SYCAL */ +#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 0x00000001UL /**< Mode slow_noise_filter_1 for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 << 10) /**< Shifted mode slow_noise_filter_0 for RAC_SYCAL*/ +#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 << 10) /**< Shifted mode slow_noise_filter_1 for RAC_SYCAL*/ +#define _RAC_SYCAL_SYVCOVCAPVCM_SHIFT 15 /**< Shift value for RAC_SYVCOVCAPVCM */ +#define _RAC_SYCAL_SYVCOVCAPVCM_MASK 0x18000UL /**< Bit mask for RAC_SYVCOVCAPVCM */ +#define _RAC_SYCAL_SYVCOVCAPVCM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */ +#define RAC_SYCAL_SYVCOVCAPVCM_DEFAULT (_RAC_SYCAL_SYVCOVCAPVCM_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_SYCAL */ +#define _RAC_SYCAL_SYHILOADCHPREG_SHIFT 24 /**< Shift value for RAC_SYHILOADCHPREG */ +#define _RAC_SYCAL_SYHILOADCHPREG_MASK 0x3000000UL /**< Bit mask for RAC_SYHILOADCHPREG */ +#define _RAC_SYCAL_SYHILOADCHPREG_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */ +#define _RAC_SYCAL_SYHILOADCHPREG_i_350uA 0x00000000UL /**< Mode i_350uA for RAC_SYCAL */ +#define _RAC_SYCAL_SYHILOADCHPREG_i_500uA 0x00000001UL /**< Mode i_500uA for RAC_SYCAL */ +#define _RAC_SYCAL_SYHILOADCHPREG_i_550uA 0x00000002UL /**< Mode i_550uA for RAC_SYCAL */ +#define _RAC_SYCAL_SYHILOADCHPREG_i_700uA 0x00000003UL /**< Mode i_700uA for RAC_SYCAL */ +#define RAC_SYCAL_SYHILOADCHPREG_DEFAULT (_RAC_SYCAL_SYHILOADCHPREG_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYCAL */ +#define RAC_SYCAL_SYHILOADCHPREG_i_350uA (_RAC_SYCAL_SYHILOADCHPREG_i_350uA << 24) /**< Shifted mode i_350uA for RAC_SYCAL */ +#define RAC_SYCAL_SYHILOADCHPREG_i_500uA (_RAC_SYCAL_SYHILOADCHPREG_i_500uA << 24) /**< Shifted mode i_500uA for RAC_SYCAL */ +#define RAC_SYCAL_SYHILOADCHPREG_i_550uA (_RAC_SYCAL_SYHILOADCHPREG_i_550uA << 24) /**< Shifted mode i_550uA for RAC_SYCAL */ +#define RAC_SYCAL_SYHILOADCHPREG_i_700uA (_RAC_SYCAL_SYHILOADCHPREG_i_700uA << 24) /**< Shifted mode i_700uA for RAC_SYCAL */ + +/* Bit fields for RAC SYEN */ +#define _RAC_SYEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SYEN */ +#define _RAC_SYEN_MASK 0x000067FFUL /**< Mask for RAC_SYEN */ +#define RAC_SYEN_SYCHPEN (0x1UL << 0) /**< SYCHPEN */ +#define _RAC_SYEN_SYCHPEN_SHIFT 0 /**< Shift value for RAC_SYCHPEN */ +#define _RAC_SYEN_SYCHPEN_MASK 0x1UL /**< Bit mask for RAC_SYCHPEN */ +#define _RAC_SYEN_SYCHPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYCHPEN_disable 0x00000000UL /**< Mode disable for RAC_SYEN */ +#define _RAC_SYEN_SYCHPEN_enable 0x00000001UL /**< Mode enable for RAC_SYEN */ +#define RAC_SYEN_SYCHPEN_DEFAULT (_RAC_SYEN_SYCHPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYCHPEN_disable (_RAC_SYEN_SYCHPEN_disable << 0) /**< Shifted mode disable for RAC_SYEN */ +#define RAC_SYEN_SYCHPEN_enable (_RAC_SYEN_SYCHPEN_enable << 0) /**< Shifted mode enable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENRX (0x1UL << 1) /**< SYCHPLPENRX */ +#define _RAC_SYEN_SYCHPLPENRX_SHIFT 1 /**< Shift value for RAC_SYCHPLPENRX */ +#define _RAC_SYEN_SYCHPLPENRX_MASK 0x2UL /**< Bit mask for RAC_SYCHPLPENRX */ +#define _RAC_SYEN_SYCHPLPENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYCHPLPENRX_disable 0x00000000UL /**< Mode disable for RAC_SYEN */ +#define _RAC_SYEN_SYCHPLPENRX_enable 0x00000001UL /**< Mode enable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENRX_DEFAULT (_RAC_SYEN_SYCHPLPENRX_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENRX_disable (_RAC_SYEN_SYCHPLPENRX_disable << 1) /**< Shifted mode disable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENRX_enable (_RAC_SYEN_SYCHPLPENRX_enable << 1) /**< Shifted mode enable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENTX (0x1UL << 2) /**< SYCHPLPENTX */ +#define _RAC_SYEN_SYCHPLPENTX_SHIFT 2 /**< Shift value for RAC_SYCHPLPENTX */ +#define _RAC_SYEN_SYCHPLPENTX_MASK 0x4UL /**< Bit mask for RAC_SYCHPLPENTX */ +#define _RAC_SYEN_SYCHPLPENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYCHPLPENTX_disable 0x00000000UL /**< Mode disable for RAC_SYEN */ +#define _RAC_SYEN_SYCHPLPENTX_enable 0x00000001UL /**< Mode enable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENTX_DEFAULT (_RAC_SYEN_SYCHPLPENTX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENTX_disable (_RAC_SYEN_SYCHPLPENTX_disable << 2) /**< Shifted mode disable for RAC_SYEN */ +#define RAC_SYEN_SYCHPLPENTX_enable (_RAC_SYEN_SYCHPLPENTX_enable << 2) /**< Shifted mode enable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREG (0x1UL << 3) /**< SYENCHPREG */ +#define _RAC_SYEN_SYENCHPREG_SHIFT 3 /**< Shift value for RAC_SYENCHPREG */ +#define _RAC_SYEN_SYENCHPREG_MASK 0x8UL /**< Bit mask for RAC_SYENCHPREG */ +#define _RAC_SYEN_SYENCHPREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENCHPREG_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */ +#define _RAC_SYEN_SYENCHPREG_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREG_DEFAULT (_RAC_SYEN_SYENCHPREG_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREG_Disable (_RAC_SYEN_SYENCHPREG_Disable << 3) /**< Shifted mode Disable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREG_Enable (_RAC_SYEN_SYENCHPREG_Enable << 3) /**< Shifted mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREPLICA (0x1UL << 4) /**< SYENCHPREPLICA */ +#define _RAC_SYEN_SYENCHPREPLICA_SHIFT 4 /**< Shift value for RAC_SYENCHPREPLICA */ +#define _RAC_SYEN_SYENCHPREPLICA_MASK 0x10UL /**< Bit mask for RAC_SYENCHPREPLICA */ +#define _RAC_SYEN_SYENCHPREPLICA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENCHPREPLICA_disable 0x00000000UL /**< Mode disable for RAC_SYEN */ +#define _RAC_SYEN_SYENCHPREPLICA_enable 0x00000001UL /**< Mode enable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREPLICA_DEFAULT (_RAC_SYEN_SYENCHPREPLICA_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREPLICA_disable (_RAC_SYEN_SYENCHPREPLICA_disable << 4) /**< Shifted mode disable for RAC_SYEN */ +#define RAC_SYEN_SYENCHPREPLICA_enable (_RAC_SYEN_SYENCHPREPLICA_enable << 4) /**< Shifted mode enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREG (0x1UL << 5) /**< SYENMMDREG */ +#define _RAC_SYEN_SYENMMDREG_SHIFT 5 /**< Shift value for RAC_SYENMMDREG */ +#define _RAC_SYEN_SYENMMDREG_MASK 0x20UL /**< Bit mask for RAC_SYENMMDREG */ +#define _RAC_SYEN_SYENMMDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREG_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREG_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREG_DEFAULT (_RAC_SYEN_SYENMMDREG_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREG_Disable (_RAC_SYEN_SYENMMDREG_Disable << 5) /**< Shifted mode Disable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREG_Enable (_RAC_SYEN_SYENMMDREG_Enable << 5) /**< Shifted mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA1 (0x1UL << 6) /**< SYENMMDREPLICA1 */ +#define _RAC_SYEN_SYENMMDREPLICA1_SHIFT 6 /**< Shift value for RAC_SYENMMDREPLICA1 */ +#define _RAC_SYEN_SYENMMDREPLICA1_MASK 0x40UL /**< Bit mask for RAC_SYENMMDREPLICA1 */ +#define _RAC_SYEN_SYENMMDREPLICA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREPLICA1_disable 0x00000000UL /**< Mode disable for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREPLICA1_enable 0x00000001UL /**< Mode enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA1_DEFAULT (_RAC_SYEN_SYENMMDREPLICA1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA1_disable (_RAC_SYEN_SYENMMDREPLICA1_disable << 6) /**< Shifted mode disable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA1_enable (_RAC_SYEN_SYENMMDREPLICA1_enable << 6) /**< Shifted mode enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA2 (0x1UL << 7) /**< SYENMMDREPLICA2 */ +#define _RAC_SYEN_SYENMMDREPLICA2_SHIFT 7 /**< Shift value for RAC_SYENMMDREPLICA2 */ +#define _RAC_SYEN_SYENMMDREPLICA2_MASK 0x80UL /**< Bit mask for RAC_SYENMMDREPLICA2 */ +#define _RAC_SYEN_SYENMMDREPLICA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREPLICA2_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */ +#define _RAC_SYEN_SYENMMDREPLICA2_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA2_DEFAULT (_RAC_SYEN_SYENMMDREPLICA2_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA2_Disable (_RAC_SYEN_SYENMMDREPLICA2_Disable << 7) /**< Shifted mode Disable for RAC_SYEN */ +#define RAC_SYEN_SYENMMDREPLICA2_Enable (_RAC_SYEN_SYENMMDREPLICA2_Enable << 7) /**< Shifted mode Enable for RAC_SYEN */ +#define RAC_SYEN_SYENVCOBIAS (0x1UL << 8) /**< SYENVCOBIAS */ +#define _RAC_SYEN_SYENVCOBIAS_SHIFT 8 /**< Shift value for RAC_SYENVCOBIAS */ +#define _RAC_SYEN_SYENVCOBIAS_MASK 0x100UL /**< Bit mask for RAC_SYENVCOBIAS */ +#define _RAC_SYEN_SYENVCOBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 0x00000000UL /**< Mode en_vco_bias_0 for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 0x00000001UL /**< Mode en_vco_bias_1 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOBIAS_DEFAULT (_RAC_SYEN_SYENVCOBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 (_RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 << 8) /**< Shifted mode en_vco_bias_0 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 (_RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 << 8) /**< Shifted mode en_vco_bias_1 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOPFET (0x1UL << 9) /**< SYENVCOPFET */ +#define _RAC_SYEN_SYENVCOPFET_SHIFT 9 /**< Shift value for RAC_SYENVCOPFET */ +#define _RAC_SYEN_SYENVCOPFET_MASK 0x200UL /**< Bit mask for RAC_SYENVCOPFET */ +#define _RAC_SYEN_SYENVCOPFET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 0x00000000UL /**< Mode en_vco_pfet_0 for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 0x00000001UL /**< Mode en_vco_pfet_1 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOPFET_DEFAULT (_RAC_SYEN_SYENVCOPFET_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 (_RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 << 9) /**< Shifted mode en_vco_pfet_0 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 (_RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 << 9) /**< Shifted mode en_vco_pfet_1 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOREG (0x1UL << 10) /**< SYENVCOREG */ +#define _RAC_SYEN_SYENVCOREG_SHIFT 10 /**< Shift value for RAC_SYENVCOREG */ +#define _RAC_SYEN_SYENVCOREG_MASK 0x400UL /**< Bit mask for RAC_SYENVCOREG */ +#define _RAC_SYEN_SYENVCOREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOREG_en_vco_reg_0 0x00000000UL /**< Mode en_vco_reg_0 for RAC_SYEN */ +#define _RAC_SYEN_SYENVCOREG_en_vco_reg_1 0x00000001UL /**< Mode en_vco_reg_1 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOREG_DEFAULT (_RAC_SYEN_SYENVCOREG_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYENVCOREG_en_vco_reg_0 (_RAC_SYEN_SYENVCOREG_en_vco_reg_0 << 10) /**< Shifted mode en_vco_reg_0 for RAC_SYEN */ +#define RAC_SYEN_SYENVCOREG_en_vco_reg_1 (_RAC_SYEN_SYENVCOREG_en_vco_reg_1 << 10) /**< Shifted mode en_vco_reg_1 for RAC_SYEN */ +#define RAC_SYEN_SYSTARTCHPREG (0x1UL << 13) /**< SYSTARTCHPREG */ +#define _RAC_SYEN_SYSTARTCHPREG_SHIFT 13 /**< Shift value for RAC_SYSTARTCHPREG */ +#define _RAC_SYEN_SYSTARTCHPREG_MASK 0x2000UL /**< Bit mask for RAC_SYSTARTCHPREG */ +#define _RAC_SYEN_SYSTARTCHPREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYSTARTCHPREG_no_fast_startup 0x00000000UL /**< Mode no_fast_startup for RAC_SYEN */ +#define _RAC_SYEN_SYSTARTCHPREG_fast_startup 0x00000001UL /**< Mode fast_startup for RAC_SYEN */ +#define RAC_SYEN_SYSTARTCHPREG_DEFAULT (_RAC_SYEN_SYSTARTCHPREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYSTARTCHPREG_no_fast_startup (_RAC_SYEN_SYSTARTCHPREG_no_fast_startup << 13) /**< Shifted mode no_fast_startup for RAC_SYEN */ +#define RAC_SYEN_SYSTARTCHPREG_fast_startup (_RAC_SYEN_SYSTARTCHPREG_fast_startup << 13) /**< Shifted mode fast_startup for RAC_SYEN */ +#define RAC_SYEN_SYSTARTMMDREG (0x1UL << 14) /**< SYSTARTMMDREG */ +#define _RAC_SYEN_SYSTARTMMDREG_SHIFT 14 /**< Shift value for RAC_SYSTARTMMDREG */ +#define _RAC_SYEN_SYSTARTMMDREG_MASK 0x4000UL /**< Bit mask for RAC_SYSTARTMMDREG */ +#define _RAC_SYEN_SYSTARTMMDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */ +#define _RAC_SYEN_SYSTARTMMDREG_no_fast_startup 0x00000000UL /**< Mode no_fast_startup for RAC_SYEN */ +#define _RAC_SYEN_SYSTARTMMDREG_fast_startup 0x00000001UL /**< Mode fast_startup for RAC_SYEN */ +#define RAC_SYEN_SYSTARTMMDREG_DEFAULT (_RAC_SYEN_SYSTARTMMDREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_SYEN */ +#define RAC_SYEN_SYSTARTMMDREG_no_fast_startup (_RAC_SYEN_SYSTARTMMDREG_no_fast_startup << 14) /**< Shifted mode no_fast_startup for RAC_SYEN */ +#define RAC_SYEN_SYSTARTMMDREG_fast_startup (_RAC_SYEN_SYSTARTMMDREG_fast_startup << 14) /**< Shifted mode fast_startup for RAC_SYEN */ + +/* Bit fields for RAC SYLOEN */ +#define _RAC_SYLOEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SYLOEN */ +#define _RAC_SYLOEN_MASK 0x00001F1EUL /**< Mask for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVEN (0x1UL << 1) /**< SYLODIVEN */ +#define _RAC_SYLOEN_SYLODIVEN_SHIFT 1 /**< Shift value for RAC_SYLODIVEN */ +#define _RAC_SYLOEN_SYLODIVEN_MASK 0x2UL /**< Bit mask for RAC_SYLODIVEN */ +#define _RAC_SYLOEN_SYLODIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVEN_DEFAULT (_RAC_SYLOEN_SYLODIVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVEN_disable (_RAC_SYLOEN_SYLODIVEN_disable << 1) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVEN_enable (_RAC_SYLOEN_SYLODIVEN_enable << 1) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOBIASEN (0x1UL << 2) /**< SYLODIVLDOBIASEN */ +#define _RAC_SYLOEN_SYLODIVLDOBIASEN_SHIFT 2 /**< Shift value for RAC_SYLODIVLDOBIASEN */ +#define _RAC_SYLOEN_SYLODIVLDOBIASEN_MASK 0x4UL /**< Bit mask for RAC_SYLODIVLDOBIASEN */ +#define _RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVLDOBIASEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVLDOBIASEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT (_RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOBIASEN_disable (_RAC_SYLOEN_SYLODIVLDOBIASEN_disable << 2) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOBIASEN_enable (_RAC_SYLOEN_SYLODIVLDOBIASEN_enable << 2) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOEN (0x1UL << 3) /**< SYLODIVLDOEN */ +#define _RAC_SYLOEN_SYLODIVLDOEN_SHIFT 3 /**< Shift value for RAC_SYLODIVLDOEN */ +#define _RAC_SYLOEN_SYLODIVLDOEN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVLDOEN */ +#define _RAC_SYLOEN_SYLODIVLDOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVLDOEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVLDOEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOEN_DEFAULT (_RAC_SYLOEN_SYLODIVLDOEN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOEN_disable (_RAC_SYLOEN_SYLODIVLDOEN_disable << 3) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVLDOEN_enable (_RAC_SYLOEN_SYLODIVLDOEN_enable << 3) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN (0x1UL << 4) /**< SYLODIVRLOADCCLK2G4EN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_SHIFT 4 /**< Shift value for RAC_SYLODIVRLOADCCLK2G4EN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_MASK 0x10UL /**< Bit mask for RAC_SYLODIVRLOADCCLK2G4EN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable << 4) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable << 4) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN (0x1UL << 8) /**< SYLODIVTLO0DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_SHIFT 8 /**< Shift value for RAC_SYLODIVTLO0DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_MASK 0x100UL /**< Bit mask for RAC_SYLODIVTLO0DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable << 8) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable << 8) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN (0x1UL << 9) /**< SYLODIVTLO0DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_SHIFT 9 /**< Shift value for RAC_SYLODIVTLO0DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_MASK 0x200UL /**< Bit mask for RAC_SYLODIVTLO0DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable << 9) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable << 9) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN (0x1UL << 10) /**< SYLODIVTLO20DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_SHIFT 10 /**< Shift value for RAC_SYLODIVTLO20DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_MASK 0x400UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4AUXEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable << 10) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable << 10) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN (0x1UL << 11) /**< SYLODIVTLO20DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_SHIFT 11 /**< Shift value for RAC_SYLODIVTLO20DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_MASK 0x800UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4EN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable << 11) /**< Shifted mode disable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable << 11) /**< Shifted mode enable for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL (0x1UL << 12) /**< SYLODIVRLOADCCLKSEL */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_SHIFT 12 /**< Shift value for RAC_SYLODIVRLOADCCLKSEL */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_MASK 0x1000UL /**< Bit mask for RAC_SYLODIVRLOADCCLKSEL */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 0x00000000UL /**< Mode adc_clk_div8 for RAC_SYLOEN */ +#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 0x00000001UL /**< Mode adc_clk_div16 for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 << 12) /**< Shifted mode adc_clk_div8 for RAC_SYLOEN */ +#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 << 12) /**< Shifted mode adc_clk_div16 for RAC_SYLOEN */ + +/* Bit fields for RAC SYMMDCTRL */ +#define _RAC_SYMMDCTRL_RESETVALUE 0x00000048UL /**< Default value for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_MASK 0x000001FFUL /**< Mask for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_SHIFT 0 /**< Shift value for RAC_SYMMDDIVRSDIG */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_MASK 0x3UL /**< Bit mask for RAC_SYMMDDIVRSDIG */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 0x00000000UL /**< Mode Divideby1 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 0x00000001UL /**< Mode Divideby2 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 0x00000002UL /**< Mode Divideby4 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 0x00000003UL /**< Mode Divideby8 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 << 0) /**< Shifted mode Divideby1 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 << 0) /**< Shifted mode Divideby2 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 << 0) /**< Shifted mode Divideby4 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 << 0) /**< Shifted mode Divideby8 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_SHIFT 2 /**< Shift value for RAC_SYMMDMODERX */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_MASK 0x1CUL /**< Bit mask for RAC_SYMMDMODERX */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl 0x00000000UL /**< Mode rx_w_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl 0x00000001UL /**< Mode rx_wo_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 0x00000002UL /**< Mode qnc_dsm2 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 0x00000003UL /**< Mode qnc_dsm3 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl 0x00000004UL /**< Mode rxlp_wo_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 0x00000005UL /**< Mode notuse_5 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 0x00000006UL /**< Mode notuse_6 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 0x00000007UL /**< Mode notuse_7 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT (_RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl << 2) /**< Shifted mode rx_w_swctrl for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl << 2) /**< Shifted mode rx_wo_swctrl for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 (_RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 << 2) /**< Shifted mode qnc_dsm2 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 (_RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 << 2) /**< Shifted mode qnc_dsm3 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl << 2) /**< Shifted mode rxlp_wo_swctrl for RAC_SYMMDCTRL*/ +#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 << 2) /**< Shifted mode notuse_5 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 << 2) /**< Shifted mode notuse_6 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 << 2) /**< Shifted mode notuse_7 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_SHIFT 5 /**< Shift value for RAC_SYMMDMODETX */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_MASK 0xE0UL /**< Bit mask for RAC_SYMMDMODETX */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl 0x00000000UL /**< Mode rx_w_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl 0x00000001UL /**< Mode rx_wo_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 0x00000002UL /**< Mode qnc_dsm2 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 0x00000003UL /**< Mode qnc_dsm3 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl 0x00000004UL /**< Mode rxlp_wo_swctrl for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 0x00000005UL /**< Mode notuse_5 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 0x00000006UL /**< Mode notuse_6 for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 0x00000007UL /**< Mode notuse_7 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT (_RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl << 5) /**< Shifted mode rx_w_swctrl for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl << 5) /**< Shifted mode rx_wo_swctrl for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 (_RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 << 5) /**< Shifted mode qnc_dsm2 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 (_RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 << 5) /**< Shifted mode qnc_dsm3 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl << 5) /**< Shifted mode rxlp_wo_swctrl for RAC_SYMMDCTRL*/ +#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 << 5) /**< Shifted mode notuse_5 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 << 5) /**< Shifted mode notuse_6 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 << 5) /**< Shifted mode notuse_7 for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDENRSDIG (0x1UL << 8) /**< SYMMDENRSDIG */ +#define _RAC_SYMMDCTRL_SYMMDENRSDIG_SHIFT 8 /**< Shift value for RAC_SYMMDENRSDIG */ +#define _RAC_SYMMDCTRL_SYMMDENRSDIG_MASK 0x100UL /**< Bit mask for RAC_SYMMDENRSDIG */ +#define _RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDENRSDIG_disable 0x00000000UL /**< Mode disable for RAC_SYMMDCTRL */ +#define _RAC_SYMMDCTRL_SYMMDENRSDIG_enable 0x00000001UL /**< Mode enable for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT (_RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDENRSDIG_disable (_RAC_SYMMDCTRL_SYMMDENRSDIG_disable << 8) /**< Shifted mode disable for RAC_SYMMDCTRL */ +#define RAC_SYMMDCTRL_SYMMDENRSDIG_enable (_RAC_SYMMDCTRL_SYMMDENRSDIG_enable << 8) /**< Shifted mode enable for RAC_SYMMDCTRL */ + +/* Bit fields for RAC DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_MASK 0x00000777UL /**< Mask for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME (0x1UL << 0) /**< DIGCLKRETIMEENRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_SHIFT 0 /**< Shift value for RAC_DIGCLKRETIMEENRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_MASK 0x1UL /**< Bit mask for RAC_DIGCLKRETIMEENRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable 0x00000000UL /**< Mode disable for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable 0x00000001UL /**< Mode enable for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable << 0) /**< Shifted mode disable for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable << 0) /**< Shifted mode enable for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME (0x1UL << 1) /**< DIGCLKRETIMEDISRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_SHIFT 1 /**< Shift value for RAC_DIGCLKRETIMEDISRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_MASK 0x2UL /**< Bit mask for RAC_DIGCLKRETIMEDISRETIME */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime 0x00000000UL /**< Mode enable_retime for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime 0x00000001UL /**< Mode disable_retime for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime << 1) /**< Shifted mode enable_retime for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime << 1) /**< Shifted mode disable_retime for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN (0x1UL << 2) /**< DIGCLKRETIMERESETN */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_SHIFT 2 /**< Shift value for RAC_DIGCLKRETIMERESETN */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_MASK 0x4UL /**< Bit mask for RAC_DIGCLKRETIMERESETN */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset 0x00000000UL /**< Mode reset for RAC_DIGCLKRETIMECTRL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate 0x00000001UL /**< Mode operate for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset << 2) /**< Shifted mode reset for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate << 2) /**< Shifted mode operate for RAC_DIGCLKRETIMECTRL*/ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_SHIFT 4 /**< Shift value for RAC_DIGCLKRETIMELIMITH */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_MASK 0x70UL /**< Bit mask for RAC_DIGCLKRETIMELIMITH */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_SHIFT 8 /**< Shift value for RAC_DIGCLKRETIMELIMITL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_MASK 0x700UL /**< Bit mask for RAC_DIGCLKRETIMELIMITL */ +#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */ +#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/ + +/* Bit fields for RAC DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_MASK 0x00000003UL /**< Mask for RAC_DIGCLKRETIMESTATUS */ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL (0x1UL << 0) /**< DIGCLKRETIMECLKSEL */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_SHIFT 0 /**< Shift value for RAC_DIGCLKRETIMECLKSEL */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_MASK 0x1UL /**< Bit mask for RAC_DIGCLKRETIMECLKSEL */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk 0x00000000UL /**< Mode use_raw_clk for RAC_DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk 0x00000001UL /**< Mode use_retimed_clk for RAC_DIGCLKRETIMESTATUS*/ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMESTATUS*/ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk << 0) /**< Shifted mode use_raw_clk for RAC_DIGCLKRETIMESTATUS*/ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk << 0) /**< Shifted mode use_retimed_clk for RAC_DIGCLKRETIMESTATUS*/ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO (0x1UL << 1) /**< DIGCLKRETIMERESETNLO */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_SHIFT 1 /**< Shift value for RAC_DIGCLKRETIMERESETNLO */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_MASK 0x2UL /**< Bit mask for RAC_DIGCLKRETIMERESETNLO */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo 0x00000000UL /**< Mode lo for RAC_DIGCLKRETIMESTATUS */ +#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi 0x00000001UL /**< Mode hi for RAC_DIGCLKRETIMESTATUS */ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMESTATUS*/ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo << 1) /**< Shifted mode lo for RAC_DIGCLKRETIMESTATUS */ +#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi << 1) /**< Shifted mode hi for RAC_DIGCLKRETIMESTATUS */ + +/* Bit fields for RAC XORETIMECTRL */ +#define _RAC_XORETIMECTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_MASK 0x00000777UL /**< Mask for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEENRETIME (0x1UL << 0) /**< XORETIMEENRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEENRETIME_SHIFT 0 /**< Shift value for RAC_XORETIMEENRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEENRETIME_MASK 0x1UL /**< Bit mask for RAC_XORETIMEENRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMEENRETIME_disable 0x00000000UL /**< Mode disable for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMEENRETIME_enable 0x00000001UL /**< Mode enable for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT (_RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEENRETIME_disable (_RAC_XORETIMECTRL_XORETIMEENRETIME_disable << 0) /**< Shifted mode disable for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEENRETIME_enable (_RAC_XORETIMECTRL_XORETIMEENRETIME_enable << 0) /**< Shifted mode enable for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEDISRETIME (0x1UL << 1) /**< XORETIMEDISRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_SHIFT 1 /**< Shift value for RAC_XORETIMEDISRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_MASK 0x2UL /**< Bit mask for RAC_XORETIMEDISRETIME */ +#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime 0x00000000UL /**< Mode enable_retime for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime 0x00000001UL /**< Mode disable_retime for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT (_RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime (_RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime << 1) /**< Shifted mode enable_retime for RAC_XORETIMECTRL*/ +#define RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime (_RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime << 1) /**< Shifted mode disable_retime for RAC_XORETIMECTRL*/ +#define RAC_XORETIMECTRL_XORETIMERESETN (0x1UL << 2) /**< XORETIMERESETN */ +#define _RAC_XORETIMECTRL_XORETIMERESETN_SHIFT 2 /**< Shift value for RAC_XORETIMERESETN */ +#define _RAC_XORETIMECTRL_XORETIMERESETN_MASK 0x4UL /**< Bit mask for RAC_XORETIMERESETN */ +#define _RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMERESETN_reset 0x00000000UL /**< Mode reset for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMERESETN_operate 0x00000001UL /**< Mode operate for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT (_RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMERESETN_reset (_RAC_XORETIMECTRL_XORETIMERESETN_reset << 2) /**< Shifted mode reset for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMERESETN_operate (_RAC_XORETIMECTRL_XORETIMERESETN_operate << 2) /**< Shifted mode operate for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMELIMITH_SHIFT 4 /**< Shift value for RAC_XORETIMELIMITH */ +#define _RAC_XORETIMECTRL_XORETIMELIMITH_MASK 0x70UL /**< Bit mask for RAC_XORETIMELIMITH */ +#define _RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT (_RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */ +#define _RAC_XORETIMECTRL_XORETIMELIMITL_SHIFT 8 /**< Shift value for RAC_XORETIMELIMITL */ +#define _RAC_XORETIMECTRL_XORETIMELIMITL_MASK 0x700UL /**< Bit mask for RAC_XORETIMELIMITL */ +#define _RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */ +#define RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT (_RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */ + +/* Bit fields for RAC XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_MASK 0x00000003UL /**< Mask for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMECLKSEL (0x1UL << 0) /**< XORETIMECLKSEL */ +#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_SHIFT 0 /**< Shift value for RAC_XORETIMECLKSEL */ +#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_MASK 0x1UL /**< Bit mask for RAC_XORETIMECLKSEL */ +#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk 0x00000000UL /**< Mode use_raw_clk for RAC_XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk 0x00000001UL /**< Mode use_retimed_clk for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT (_RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk (_RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk << 0) /**< Shifted mode use_raw_clk for RAC_XORETIMESTATUS*/ +#define RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk (_RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk << 0) /**< Shifted mode use_retimed_clk for RAC_XORETIMESTATUS*/ +#define RAC_XORETIMESTATUS_XORETIMERESETNLO (0x1UL << 1) /**< XORETIMERESETNLO */ +#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_SHIFT 1 /**< Shift value for RAC_XORETIMERESETNLO */ +#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_MASK 0x2UL /**< Bit mask for RAC_XORETIMERESETNLO */ +#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_lo 0x00000000UL /**< Mode lo for RAC_XORETIMESTATUS */ +#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_hi 0x00000001UL /**< Mode hi for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT (_RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMERESETNLO_lo (_RAC_XORETIMESTATUS_XORETIMERESETNLO_lo << 1) /**< Shifted mode lo for RAC_XORETIMESTATUS */ +#define RAC_XORETIMESTATUS_XORETIMERESETNLO_hi (_RAC_XORETIMESTATUS_XORETIMERESETNLO_hi << 1) /**< Shifted mode hi for RAC_XORETIMESTATUS */ + +/* Bit fields for RAC AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_MASK 0x03F0FFFFUL /**< Mask for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT (0x1UL << 0) /**< Enable RAC Overwite PN */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_SHIFT 0 /**< Shift value for RAC_ENMANLNAMIXRFATT */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_MASK 0x1UL /**< Bit mask for RAC_ENMANLNAMIXRFATT */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT (_RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE (0x1UL << 1) /**< Enable RAC Overwite LNA */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_SHIFT 1 /**< Shift value for RAC_ENMANLNAMIXSLICE */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_MASK 0x2UL /**< Bit mask for RAC_ENMANLNAMIXSLICE */ +#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT (_RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANPGAGAIN (0x1UL << 2) /**< Enable RAC Overwite PGA */ +#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_SHIFT 2 /**< Shift value for RAC_ENMANPGAGAIN */ +#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_MASK 0x4UL /**< Bit mask for RAC_ENMANPGAGAIN */ +#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT (_RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANIFADCSCALE (0x1UL << 3) /**< Enable RAC Overwite PN */ +#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_SHIFT 3 /**< Shift value for RAC_ENMANIFADCSCALE */ +#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_MASK 0x8UL /**< Bit mask for RAC_ENMANIFADCSCALE */ +#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT (_RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_SHIFT 4 /**< Shift value for RAC_MANLNAMIXSLICE0 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_MASK 0x3F0UL /**< Bit mask for RAC_MANLNAMIXSLICE0 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT (_RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_SHIFT 10 /**< Shift value for RAC_MANLNAMIXSLICE1 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_MASK 0xFC00UL /**< Bit mask for RAC_MANLNAMIXSLICE1 */ +#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT (_RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_MANPGAGAIN_SHIFT 20 /**< Shift value for RAC_MANPGAGAIN */ +#define _RAC_AGCOVERWRITE0_MANPGAGAIN_MASK 0xF00000UL /**< Bit mask for RAC_MANPGAGAIN */ +#define _RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT (_RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_SHIFT 24 /**< Shift value for RAC_MANIFADCSCALE */ +#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_MASK 0x3000000UL /**< Bit mask for RAC_MANIFADCSCALE */ +#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */ +#define RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT (_RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */ + +/* Bit fields for RAC AGCOVERWRITE1 */ +#define _RAC_AGCOVERWRITE1_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE1 */ +#define _RAC_AGCOVERWRITE1_MASK 0x3FFF3FFFUL /**< Mask for RAC_AGCOVERWRITE1 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_SHIFT 0 /**< Shift value for RAC_MANLNAMIXRFATT0 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_MASK 0x3FFFUL /**< Bit mask for RAC_MANLNAMIXRFATT0 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE1 */ +#define RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT (_RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE1 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_SHIFT 16 /**< Shift value for RAC_MANLNAMIXRFATT1 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_MASK 0x3FFF0000UL /**< Bit mask for RAC_MANLNAMIXRFATT1 */ +#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE1 */ +#define RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT (_RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE1 */ + +/* Bit fields for RAC AGCOVERWRITE2 */ +#define _RAC_AGCOVERWRITE2_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE2 */ +#define _RAC_AGCOVERWRITE2_MASK 0x0000FFFFUL /**< Mask for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_ENMANFENOTCH (0x1UL << 0) /**< Enable RAC Overwrite FENOTCH */ +#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_SHIFT 0 /**< Shift value for RAC_ENMANFENOTCH */ +#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_MASK 0x1UL /**< Bit mask for RAC_ENMANFENOTCH */ +#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT (_RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHEN (0x1UL << 1) /**< RAC Overwrite fenotchen */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_SHIFT 1 /**< Shift value for RAC_MANFENOTCHEN */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_MASK 0x2UL /**< Bit mask for RAC_MANFENOTCHEN */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_SHIFT 2 /**< Shift value for RAC_MANFENOTCHATTNSEL */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_MASK 0x3CUL /**< Bit mask for RAC_MANFENOTCHATTNSEL */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0 (0x1UL << 6) /**< RAC Overwrite fenotchrattnenrf0 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_SHIFT 6 /**< Shift value for RAC_MANFENOTCHRATTNENRF0 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_MASK 0x40UL /**< Bit mask for RAC_MANFENOTCHRATTNENRF0 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1 (0x1UL << 7) /**< RAC Overwrite fenotchrattnenrf1 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_SHIFT 7 /**< Shift value for RAC_MANFENOTCHRATTNENRF1 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_MASK 0x80UL /**< Bit mask for RAC_MANFENOTCHRATTNENRF1 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_SHIFT 8 /**< Shift value for RAC_MANFENOTCHCAPCRSE */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_MASK 0xF00UL /**< Bit mask for RAC_MANFENOTCHCAPCRSE */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_SHIFT 12 /**< Shift value for RAC_MANFENOTCHCAPFINE */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_MASK 0xF000UL /**< Bit mask for RAC_MANFENOTCHCAPFINE */ +#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */ +#define RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */ + +/* Bit fields for RAC PACTRL */ +#define _RAC_PACTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_PACTRL */ +#define _RAC_PACTRL_MASK 0x0001FFFFUL /**< Mask for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMLATCHBYPASS (0x1UL << 0) /**< TX0DBMLATCHBYPASS */ +#define _RAC_PACTRL_TX0DBMLATCHBYPASS_SHIFT 0 /**< Shift value for RAC_TX0DBMLATCHBYPASS */ +#define _RAC_PACTRL_TX0DBMLATCHBYPASS_MASK 0x1UL /**< Bit mask for RAC_TX0DBMLATCHBYPASS */ +#define _RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TX0DBMLATCHBYPASS_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */ +#define _RAC_PACTRL_TX0DBMLATCHBYPASS_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT (_RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMLATCHBYPASS_disable (_RAC_PACTRL_TX0DBMLATCHBYPASS_disable << 0) /**< Shifted mode disable for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMLATCHBYPASS_enable (_RAC_PACTRL_TX0DBMLATCHBYPASS_enable << 0) /**< Shifted mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMSLICERESET (0x1UL << 1) /**< TX0DBMSLICERESET */ +#define _RAC_PACTRL_TX0DBMSLICERESET_SHIFT 1 /**< Shift value for RAC_TX0DBMSLICERESET */ +#define _RAC_PACTRL_TX0DBMSLICERESET_MASK 0x2UL /**< Bit mask for RAC_TX0DBMSLICERESET */ +#define _RAC_PACTRL_TX0DBMSLICERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TX0DBMSLICERESET_active 0x00000000UL /**< Mode active for RAC_PACTRL */ +#define _RAC_PACTRL_TX0DBMSLICERESET_reset 0x00000001UL /**< Mode reset for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMSLICERESET_DEFAULT (_RAC_PACTRL_TX0DBMSLICERESET_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMSLICERESET_active (_RAC_PACTRL_TX0DBMSLICERESET_active << 1) /**< Shifted mode active for RAC_PACTRL */ +#define RAC_PACTRL_TX0DBMSLICERESET_reset (_RAC_PACTRL_TX0DBMSLICERESET_reset << 1) /**< Shifted mode reset for RAC_PACTRL */ +#define RAC_PACTRL_TXPABYPASSPREDRVREG (0x1UL << 2) /**< TXPABYPASSPREDRVREG */ +#define _RAC_PACTRL_TXPABYPASSPREDRVREG_SHIFT 2 /**< Shift value for RAC_TXPABYPASSPREDRVREG */ +#define _RAC_PACTRL_TXPABYPASSPREDRVREG_MASK 0x4UL /**< Bit mask for RAC_TXPABYPASSPREDRVREG */ +#define _RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass 0x00000000UL /**< Mode not_bypass for RAC_PACTRL */ +#define _RAC_PACTRL_TXPABYPASSPREDRVREG_bypass 0x00000001UL /**< Mode bypass for RAC_PACTRL */ +#define RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT (_RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass (_RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass << 2) /**< Shifted mode not_bypass for RAC_PACTRL */ +#define RAC_PACTRL_TXPABYPASSPREDRVREG_bypass (_RAC_PACTRL_TXPABYPASSPREDRVREG_bypass << 2) /**< Shifted mode bypass for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPULLDOWNVDDPA (0x1UL << 3) /**< TXPAPULLDOWNVDDPA */ +#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_SHIFT 3 /**< Shift value for RAC_TXPAPULLDOWNVDDPA */ +#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_MASK 0x8UL /**< Bit mask for RAC_TXPAPULLDOWNVDDPA */ +#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down 0x00000000UL /**< Mode not_pull_down for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa 0x00000001UL /**< Mode pull_down_vddpa for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT (_RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down (_RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down << 3) /**< Shifted mode not_pull_down for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa (_RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa << 3) /**< Shifted mode pull_down_vddpa for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_SHIFT 4 /**< Shift value for RAC_TXPAPOWER */ +#define _RAC_PACTRL_TXPAPOWER_MASK 0xF0UL /**< Bit mask for RAC_TXPAPOWER */ +#define _RAC_PACTRL_TXPAPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t0stripeon 0x00000000UL /**< Mode t0stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t1stripeon 0x00000001UL /**< Mode t1stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t2stripeon 0x00000002UL /**< Mode t2stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t3stripeon 0x00000003UL /**< Mode t3stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t4stripeon 0x00000004UL /**< Mode t4stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t5stripeon 0x00000005UL /**< Mode t5stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t6stripeon 0x00000006UL /**< Mode t6stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t7stripeon 0x00000007UL /**< Mode t7stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t8stripeon 0x00000008UL /**< Mode t8stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t9stripeon 0x00000009UL /**< Mode t9stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t10stripeon 0x0000000AUL /**< Mode t10stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t11stripeon 0x0000000BUL /**< Mode t11stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t12stripeon 0x0000000CUL /**< Mode t12stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t13stripeon 0x0000000DUL /**< Mode t13stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t14stripeon 0x0000000EUL /**< Mode t14stripeon for RAC_PACTRL */ +#define _RAC_PACTRL_TXPAPOWER_t15stripeon 0x0000000FUL /**< Mode t15stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_DEFAULT (_RAC_PACTRL_TXPAPOWER_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t0stripeon (_RAC_PACTRL_TXPAPOWER_t0stripeon << 4) /**< Shifted mode t0stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t1stripeon (_RAC_PACTRL_TXPAPOWER_t1stripeon << 4) /**< Shifted mode t1stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t2stripeon (_RAC_PACTRL_TXPAPOWER_t2stripeon << 4) /**< Shifted mode t2stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t3stripeon (_RAC_PACTRL_TXPAPOWER_t3stripeon << 4) /**< Shifted mode t3stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t4stripeon (_RAC_PACTRL_TXPAPOWER_t4stripeon << 4) /**< Shifted mode t4stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t5stripeon (_RAC_PACTRL_TXPAPOWER_t5stripeon << 4) /**< Shifted mode t5stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t6stripeon (_RAC_PACTRL_TXPAPOWER_t6stripeon << 4) /**< Shifted mode t6stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t7stripeon (_RAC_PACTRL_TXPAPOWER_t7stripeon << 4) /**< Shifted mode t7stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t8stripeon (_RAC_PACTRL_TXPAPOWER_t8stripeon << 4) /**< Shifted mode t8stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t9stripeon (_RAC_PACTRL_TXPAPOWER_t9stripeon << 4) /**< Shifted mode t9stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t10stripeon (_RAC_PACTRL_TXPAPOWER_t10stripeon << 4) /**< Shifted mode t10stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t11stripeon (_RAC_PACTRL_TXPAPOWER_t11stripeon << 4) /**< Shifted mode t11stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t12stripeon (_RAC_PACTRL_TXPAPOWER_t12stripeon << 4) /**< Shifted mode t12stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t13stripeon (_RAC_PACTRL_TXPAPOWER_t13stripeon << 4) /**< Shifted mode t13stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t14stripeon (_RAC_PACTRL_TXPAPOWER_t14stripeon << 4) /**< Shifted mode t14stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPAPOWER_t15stripeon (_RAC_PACTRL_TXPAPOWER_t15stripeon << 4) /**< Shifted mode t15stripeon for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS10DBM (0x1UL << 8) /**< TXPALATCHBYPASS10DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_SHIFT 8 /**< Shift value for RAC_TXPALATCHBYPASS10DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_MASK 0x100UL /**< Bit mask for RAC_TXPALATCHBYPASS10DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */ +#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT (_RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS10DBM_disable (_RAC_PACTRL_TXPALATCHBYPASS10DBM_disable << 8) /**< Shifted mode disable for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS10DBM_enable (_RAC_PACTRL_TXPALATCHBYPASS10DBM_enable << 8) /**< Shifted mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS20DBM (0x1UL << 9) /**< TXPALATCHBYPASS20DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_SHIFT 9 /**< Shift value for RAC_TXPALATCHBYPASS20DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_MASK 0x200UL /**< Bit mask for RAC_TXPALATCHBYPASS20DBM */ +#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */ +#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT (_RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS20DBM_disable (_RAC_PACTRL_TXPALATCHBYPASS20DBM_disable << 9) /**< Shifted mode disable for RAC_PACTRL */ +#define RAC_PACTRL_TXPALATCHBYPASS20DBM_enable (_RAC_PACTRL_TXPALATCHBYPASS20DBM_enable << 9) /**< Shifted mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDPA (0x1UL << 10) /**< TXPASELPREDRVREGVDDPA */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_SHIFT 10 /**< Shift value for RAC_TXPASELPREDRVREGVDDPA */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_MASK 0x400UL /**< Bit mask for RAC_TXPASELPREDRVREGVDDPA */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected 0x00000000UL /**< Mode not_selected for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected 0x00000001UL /**< Mode selected for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected << 10) /**< Shifted mode not_selected for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected << 10) /**< Shifted mode selected for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDRF (0x1UL << 11) /**< TXPASELPREDRVREGVDDRF */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_SHIFT 11 /**< Shift value for RAC_TXPASELPREDRVREGVDDRF */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_MASK 0x800UL /**< Bit mask for RAC_TXPASELPREDRVREGVDDRF */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected 0x00000000UL /**< Mode not_selected for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected 0x00000001UL /**< Mode selected for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected << 11) /**< Shifted mode not_selected for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected << 11) /**< Shifted mode selected for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASELSLICE_SHIFT 12 /**< Shift value for RAC_TXPASELSLICE */ +#define _RAC_PACTRL_TXPASELSLICE_MASK 0xF000UL /**< Bit mask for RAC_TXPASELSLICE */ +#define _RAC_PACTRL_TXPASELSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPASELSLICE_DEFAULT (_RAC_PACTRL_TXPASELSLICE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPASLICERST (0x1UL << 16) /**< TXPASLICERST */ +#define _RAC_PACTRL_TXPASLICERST_SHIFT 16 /**< Shift value for RAC_TXPASLICERST */ +#define _RAC_PACTRL_TXPASLICERST_MASK 0x10000UL /**< Bit mask for RAC_TXPASLICERST */ +#define _RAC_PACTRL_TXPASLICERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASLICERST_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */ +#define _RAC_PACTRL_TXPASLICERST_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */ +#define RAC_PACTRL_TXPASLICERST_DEFAULT (_RAC_PACTRL_TXPASLICERST_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PACTRL */ +#define RAC_PACTRL_TXPASLICERST_disable (_RAC_PACTRL_TXPASLICERST_disable << 16) /**< Shifted mode disable for RAC_PACTRL */ +#define RAC_PACTRL_TXPASLICERST_enable (_RAC_PACTRL_TXPASLICERST_enable << 16) /**< Shifted mode enable for RAC_PACTRL */ + +/* Bit fields for RAC FENOTCH0 */ +#define _RAC_FENOTCH0_RESETVALUE 0x00004000UL /**< Default value for RAC_FENOTCH0 */ +#define _RAC_FENOTCH0_MASK 0x00007000UL /**< Mask for RAC_FENOTCH0 */ +#define _RAC_FENOTCH0_FENOTCHVBIAS_SHIFT 12 /**< Shift value for RAC_FENOTCHVBIAS */ +#define _RAC_FENOTCH0_FENOTCHVBIAS_MASK 0x7000UL /**< Bit mask for RAC_FENOTCHVBIAS */ +#define _RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_FENOTCH0 */ +#define RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT (_RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_FENOTCH0 */ + +/* Bit fields for RAC FENOTCH1 */ +#define _RAC_FENOTCH1_RESETVALUE 0x00000000UL /**< Default value for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_MASK 0x001FFF05UL /**< Mask for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHENVDDSW (0x1UL << 0) /**< FENOTCHENVDDSW */ +#define _RAC_FENOTCH1_FENOTCHENVDDSW_SHIFT 0 /**< Shift value for RAC_FENOTCHENVDDSW */ +#define _RAC_FENOTCH1_FENOTCHENVDDSW_MASK 0x1UL /**< Bit mask for RAC_FENOTCHENVDDSW */ +#define _RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHENVDDSW_disable 0x00000000UL /**< Mode disable for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHENVDDSW_enable 0x00000001UL /**< Mode enable for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT (_RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHENVDDSW_disable (_RAC_FENOTCH1_FENOTCHENVDDSW_disable << 0) /**< Shifted mode disable for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHENVDDSW_enable (_RAC_FENOTCH1_FENOTCHENVDDSW_enable << 0) /**< Shifted mode enable for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALEN (0x1UL << 2) /**< FENOTCHRCCALEN */ +#define _RAC_FENOTCH1_FENOTCHRCCALEN_SHIFT 2 /**< Shift value for RAC_FENOTCHRCCALEN */ +#define _RAC_FENOTCH1_FENOTCHRCCALEN_MASK 0x4UL /**< Bit mask for RAC_FENOTCHRCCALEN */ +#define _RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHRCCALEN_disable 0x00000000UL /**< Mode disable for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHRCCALEN_enable 0x00000001UL /**< Mode enable for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALEN_disable (_RAC_FENOTCH1_FENOTCHRCCALEN_disable << 2) /**< Shifted mode disable for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALEN_enable (_RAC_FENOTCH1_FENOTCHRCCALEN_enable << 2) /**< Shifted mode enable for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_SHIFT 8 /**< Shift value for RAC_FENOTCHRCCALCOUNTER */ +#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_MASK 0xFF00UL /**< Bit mask for RAC_FENOTCHRCCALCOUNTER */ +#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */ +#define _RAC_FENOTCH1_FENOTCHRCCALOSC_SHIFT 16 /**< Shift value for RAC_FENOTCHRCCALOSC */ +#define _RAC_FENOTCH1_FENOTCHRCCALOSC_MASK 0xF0000UL /**< Bit mask for RAC_FENOTCHRCCALOSC */ +#define _RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALOUT (0x1UL << 20) /**< FENOTCHRCCALOUT */ +#define _RAC_FENOTCH1_FENOTCHRCCALOUT_SHIFT 20 /**< Shift value for RAC_FENOTCHRCCALOUT */ +#define _RAC_FENOTCH1_FENOTCHRCCALOUT_MASK 0x100000UL /**< Bit mask for RAC_FENOTCHRCCALOUT */ +#define _RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */ +#define RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */ + +/* Bit fields for RAC SCRATCH0 */ +#define _RAC_SCRATCH0_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH0 */ +#define _RAC_SCRATCH0_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH0 */ +#define _RAC_SCRATCH0_SCRATCH0_SHIFT 0 /**< Shift value for RAC_SCRATCH0 */ +#define _RAC_SCRATCH0_SCRATCH0_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH0 */ +#define _RAC_SCRATCH0_SCRATCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH0 */ +#define RAC_SCRATCH0_SCRATCH0_DEFAULT (_RAC_SCRATCH0_SCRATCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH0 */ + +/* Bit fields for RAC SCRATCH1 */ +#define _RAC_SCRATCH1_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH1 */ +#define _RAC_SCRATCH1_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH1 */ +#define _RAC_SCRATCH1_SCRATCH1_SHIFT 0 /**< Shift value for RAC_SCRATCH1 */ +#define _RAC_SCRATCH1_SCRATCH1_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH1 */ +#define _RAC_SCRATCH1_SCRATCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH1 */ +#define RAC_SCRATCH1_SCRATCH1_DEFAULT (_RAC_SCRATCH1_SCRATCH1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH1 */ + +/* Bit fields for RAC SCRATCH2 */ +#define _RAC_SCRATCH2_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH2 */ +#define _RAC_SCRATCH2_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH2 */ +#define _RAC_SCRATCH2_SCRATCH2_SHIFT 0 /**< Shift value for RAC_SCRATCH2 */ +#define _RAC_SCRATCH2_SCRATCH2_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH2 */ +#define _RAC_SCRATCH2_SCRATCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH2 */ +#define RAC_SCRATCH2_SCRATCH2_DEFAULT (_RAC_SCRATCH2_SCRATCH2_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH2 */ + +/* Bit fields for RAC SCRATCH3 */ +#define _RAC_SCRATCH3_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH3 */ +#define _RAC_SCRATCH3_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH3 */ +#define _RAC_SCRATCH3_SCRATCH3_SHIFT 0 /**< Shift value for RAC_SCRATCH3 */ +#define _RAC_SCRATCH3_SCRATCH3_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH3 */ +#define _RAC_SCRATCH3_SCRATCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH3 */ +#define RAC_SCRATCH3_SCRATCH3_DEFAULT (_RAC_SCRATCH3_SCRATCH3_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH3 */ + +/* Bit fields for RAC SCRATCH4 */ +#define _RAC_SCRATCH4_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH4 */ +#define _RAC_SCRATCH4_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH4 */ +#define _RAC_SCRATCH4_SCRATCH4_SHIFT 0 /**< Shift value for RAC_SCRATCH4 */ +#define _RAC_SCRATCH4_SCRATCH4_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH4 */ +#define _RAC_SCRATCH4_SCRATCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH4 */ +#define RAC_SCRATCH4_SCRATCH4_DEFAULT (_RAC_SCRATCH4_SCRATCH4_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH4 */ + +/* Bit fields for RAC SCRATCH5 */ +#define _RAC_SCRATCH5_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH5 */ +#define _RAC_SCRATCH5_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH5 */ +#define _RAC_SCRATCH5_SCRATCH5_SHIFT 0 /**< Shift value for RAC_SCRATCH5 */ +#define _RAC_SCRATCH5_SCRATCH5_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH5 */ +#define _RAC_SCRATCH5_SCRATCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH5 */ +#define RAC_SCRATCH5_SCRATCH5_DEFAULT (_RAC_SCRATCH5_SCRATCH5_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH5 */ + +/* Bit fields for RAC SCRATCH6 */ +#define _RAC_SCRATCH6_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH6 */ +#define _RAC_SCRATCH6_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH6 */ +#define _RAC_SCRATCH6_SCRATCH6_SHIFT 0 /**< Shift value for RAC_SCRATCH6 */ +#define _RAC_SCRATCH6_SCRATCH6_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH6 */ +#define _RAC_SCRATCH6_SCRATCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH6 */ +#define RAC_SCRATCH6_SCRATCH6_DEFAULT (_RAC_SCRATCH6_SCRATCH6_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH6 */ + +/* Bit fields for RAC SCRATCH7 */ +#define _RAC_SCRATCH7_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH7 */ +#define _RAC_SCRATCH7_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH7 */ +#define _RAC_SCRATCH7_SCRATCH7_SHIFT 0 /**< Shift value for RAC_SCRATCH7 */ +#define _RAC_SCRATCH7_SCRATCH7_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH7 */ +#define _RAC_SCRATCH7_SCRATCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH7 */ +#define RAC_SCRATCH7_SCRATCH7_DEFAULT (_RAC_SCRATCH7_SCRATCH7_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH7 */ + +/* Bit fields for RAC THMSW */ +#define _RAC_THMSW_RESETVALUE 0x00000000UL /**< Default value for RAC_THMSW */ +#define _RAC_THMSW_MASK 0x00000003UL /**< Mask for RAC_THMSW */ +#define RAC_THMSW_EN (0x1UL << 0) /**< Enable Switch */ +#define _RAC_THMSW_EN_SHIFT 0 /**< Shift value for RAC_EN */ +#define _RAC_THMSW_EN_MASK 0x1UL /**< Bit mask for RAC_EN */ +#define _RAC_THMSW_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_THMSW */ +#define _RAC_THMSW_EN_Disabled 0x00000000UL /**< Mode Disabled for RAC_THMSW */ +#define _RAC_THMSW_EN_Enabled 0x00000001UL /**< Mode Enabled for RAC_THMSW */ +#define RAC_THMSW_EN_DEFAULT (_RAC_THMSW_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_THMSW */ +#define RAC_THMSW_EN_Disabled (_RAC_THMSW_EN_Disabled << 0) /**< Shifted mode Disabled for RAC_THMSW */ +#define RAC_THMSW_EN_Enabled (_RAC_THMSW_EN_Enabled << 0) /**< Shifted mode Enabled for RAC_THMSW */ +#define RAC_THMSW_HALFSWITCH (0x1UL << 1) /**< Halfswitch Mode enable */ +#define _RAC_THMSW_HALFSWITCH_SHIFT 1 /**< Shift value for RAC_HALFSWITCH */ +#define _RAC_THMSW_HALFSWITCH_MASK 0x2UL /**< Bit mask for RAC_HALFSWITCH */ +#define _RAC_THMSW_HALFSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_THMSW */ +#define _RAC_THMSW_HALFSWITCH_Disabled 0x00000000UL /**< Mode Disabled for RAC_THMSW */ +#define _RAC_THMSW_HALFSWITCH_Enabled 0x00000001UL /**< Mode Enabled for RAC_THMSW */ +#define RAC_THMSW_HALFSWITCH_DEFAULT (_RAC_THMSW_HALFSWITCH_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_THMSW */ +#define RAC_THMSW_HALFSWITCH_Disabled (_RAC_THMSW_HALFSWITCH_Disabled << 1) /**< Shifted mode Disabled for RAC_THMSW */ +#define RAC_THMSW_HALFSWITCH_Enabled (_RAC_THMSW_HALFSWITCH_Enabled << 1) /**< Shifted mode Enabled for RAC_THMSW */ + +/** @} End of group EFR32MG24_RAC_BitFields */ +/** @} End of group EFR32MG24_RAC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_RAC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_rfcrc.h b/EFR32MG24/Device/Include/efr32mg24_rfcrc.h new file mode 100644 index 0000000..4ce9e7a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_rfcrc.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 RFCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_RFCRC_H +#define EFR32MG24_RFCRC_H +#define RFCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_RFCRC RFCRC + * @{ + * @brief EFR32MG24 RFCRC Register Declaration. + *****************************************************************************/ + +/** RFCRC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INPUTDATA; /**< Input Data Register */ + __IOM uint32_t INIT; /**< CRC Initialization Value */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INPUTDATA_SET; /**< Input Data Register */ + __IOM uint32_t INIT_SET; /**< CRC Initialization Value */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INPUTDATA_CLR; /**< Input Data Register */ + __IOM uint32_t INIT_CLR; /**< CRC Initialization Value */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INPUTDATA_TGL; /**< Input Data Register */ + __IOM uint32_t INIT_TGL; /**< CRC Initialization Value */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ +} RFCRC_TypeDef; +/** @} End of group EFR32MG24_RFCRC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_RFCRC + * @{ + * @defgroup EFR32MG24_RFCRC_BitFields RFCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for RFCRC IPVERSION */ +#define _RFCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for RFCRC_IPVERSION */ +#define _RFCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_IPVERSION */ +#define _RFCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RFCRC_IPVERSION */ +#define _RFCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_IPVERSION */ +#define _RFCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_IPVERSION */ +#define RFCRC_IPVERSION_IPVERSION_DEFAULT (_RFCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_IPVERSION */ + +/* Bit fields for RFCRC EN */ +#define _RFCRC_EN_RESETVALUE 0x00000000UL /**< Default value for RFCRC_EN */ +#define _RFCRC_EN_MASK 0x00000001UL /**< Mask for RFCRC_EN */ +#define RFCRC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _RFCRC_EN_EN_SHIFT 0 /**< Shift value for RFCRC_EN */ +#define _RFCRC_EN_EN_MASK 0x1UL /**< Bit mask for RFCRC_EN */ +#define _RFCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_EN */ +#define RFCRC_EN_EN_DEFAULT (_RFCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_EN */ + +/* Bit fields for RFCRC CTRL */ +#define _RFCRC_CTRL_RESETVALUE 0x00000704UL /**< Default value for RFCRC_CTRL */ +#define _RFCRC_CTRL_MASK 0x00001FEFUL /**< Mask for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTINV (0x1UL << 0) /**< Input Invert */ +#define _RFCRC_CTRL_INPUTINV_SHIFT 0 /**< Shift value for RFCRC_INPUTINV */ +#define _RFCRC_CTRL_INPUTINV_MASK 0x1UL /**< Bit mask for RFCRC_INPUTINV */ +#define _RFCRC_CTRL_INPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTINV_DEFAULT (_RFCRC_CTRL_INPUTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_OUTPUTINV (0x1UL << 1) /**< Output Invert */ +#define _RFCRC_CTRL_OUTPUTINV_SHIFT 1 /**< Shift value for RFCRC_OUTPUTINV */ +#define _RFCRC_CTRL_OUTPUTINV_MASK 0x2UL /**< Bit mask for RFCRC_OUTPUTINV */ +#define _RFCRC_CTRL_OUTPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_OUTPUTINV_DEFAULT (_RFCRC_CTRL_OUTPUTINV_DEFAULT << 1) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_CRCWIDTH_SHIFT 2 /**< Shift value for RFCRC_CRCWIDTH */ +#define _RFCRC_CTRL_CRCWIDTH_MASK 0xCUL /**< Bit mask for RFCRC_CRCWIDTH */ +#define _RFCRC_CTRL_CRCWIDTH_DEFAULT 0x00000001UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 0x00000000UL /**< Mode CRCWIDTH8 for RFCRC_CTRL */ +#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 0x00000001UL /**< Mode CRCWIDTH16 for RFCRC_CTRL */ +#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 0x00000002UL /**< Mode CRCWIDTH24 for RFCRC_CTRL */ +#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 0x00000003UL /**< Mode CRCWIDTH32 for RFCRC_CTRL */ +#define RFCRC_CTRL_CRCWIDTH_DEFAULT (_RFCRC_CTRL_CRCWIDTH_DEFAULT << 2) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 << 2) /**< Shifted mode CRCWIDTH8 for RFCRC_CTRL */ +#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 << 2) /**< Shifted mode CRCWIDTH16 for RFCRC_CTRL */ +#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 << 2) /**< Shifted mode CRCWIDTH24 for RFCRC_CTRL */ +#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 << 2) /**< Shifted mode CRCWIDTH32 for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTBITORDER (0x1UL << 5) /**< CRC input bit ordering setting */ +#define _RFCRC_CTRL_INPUTBITORDER_SHIFT 5 /**< Shift value for RFCRC_INPUTBITORDER */ +#define _RFCRC_CTRL_INPUTBITORDER_MASK 0x20UL /**< Bit mask for RFCRC_INPUTBITORDER */ +#define _RFCRC_CTRL_INPUTBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_INPUTBITORDER_LSBFIRST 0x00000000UL /**< Mode LSBFIRST for RFCRC_CTRL */ +#define _RFCRC_CTRL_INPUTBITORDER_MSBFIRST 0x00000001UL /**< Mode MSBFIRST for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTBITORDER_DEFAULT (_RFCRC_CTRL_INPUTBITORDER_DEFAULT << 5) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTBITORDER_LSBFIRST (_RFCRC_CTRL_INPUTBITORDER_LSBFIRST << 5) /**< Shifted mode LSBFIRST for RFCRC_CTRL */ +#define RFCRC_CTRL_INPUTBITORDER_MSBFIRST (_RFCRC_CTRL_INPUTBITORDER_MSBFIRST << 5) /**< Shifted mode MSBFIRST for RFCRC_CTRL */ +#define RFCRC_CTRL_BYTEREVERSE (0x1UL << 6) /**< Reverse CRC byte ordering over air */ +#define _RFCRC_CTRL_BYTEREVERSE_SHIFT 6 /**< Shift value for RFCRC_BYTEREVERSE */ +#define _RFCRC_CTRL_BYTEREVERSE_MASK 0x40UL /**< Bit mask for RFCRC_BYTEREVERSE */ +#define _RFCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */ +#define _RFCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */ +#define RFCRC_CTRL_BYTEREVERSE_DEFAULT (_RFCRC_CTRL_BYTEREVERSE_DEFAULT << 6) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_BYTEREVERSE_NORMAL (_RFCRC_CTRL_BYTEREVERSE_NORMAL << 6) /**< Shifted mode NORMAL for RFCRC_CTRL */ +#define RFCRC_CTRL_BYTEREVERSE_REVERSED (_RFCRC_CTRL_BYTEREVERSE_REVERSED << 6) /**< Shifted mode REVERSED for RFCRC_CTRL */ +#define RFCRC_CTRL_BITREVERSE (0x1UL << 7) /**< Reverse CRC bit ordering over air */ +#define _RFCRC_CTRL_BITREVERSE_SHIFT 7 /**< Shift value for RFCRC_BITREVERSE */ +#define _RFCRC_CTRL_BITREVERSE_MASK 0x80UL /**< Bit mask for RFCRC_BITREVERSE */ +#define _RFCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */ +#define _RFCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */ +#define RFCRC_CTRL_BITREVERSE_DEFAULT (_RFCRC_CTRL_BITREVERSE_DEFAULT << 7) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_BITREVERSE_NORMAL (_RFCRC_CTRL_BITREVERSE_NORMAL << 7) /**< Shifted mode NORMAL for RFCRC_CTRL */ +#define RFCRC_CTRL_BITREVERSE_REVERSED (_RFCRC_CTRL_BITREVERSE_REVERSED << 7) /**< Shifted mode REVERSED for RFCRC_CTRL */ +#define _RFCRC_CTRL_BITSPERWORD_SHIFT 8 /**< Shift value for RFCRC_BITSPERWORD */ +#define _RFCRC_CTRL_BITSPERWORD_MASK 0xF00UL /**< Bit mask for RFCRC_BITSPERWORD */ +#define _RFCRC_CTRL_BITSPERWORD_DEFAULT 0x00000007UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_BITSPERWORD_DEFAULT (_RFCRC_CTRL_BITSPERWORD_DEFAULT << 8) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_PADCRCINPUT (0x1UL << 12) /**< Pad CRC input data */ +#define _RFCRC_CTRL_PADCRCINPUT_SHIFT 12 /**< Shift value for RFCRC_PADCRCINPUT */ +#define _RFCRC_CTRL_PADCRCINPUT_MASK 0x1000UL /**< Bit mask for RFCRC_PADCRCINPUT */ +#define _RFCRC_CTRL_PADCRCINPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ +#define _RFCRC_CTRL_PADCRCINPUT_X0 0x00000000UL /**< Mode X0 for RFCRC_CTRL */ +#define _RFCRC_CTRL_PADCRCINPUT_X1 0x00000001UL /**< Mode X1 for RFCRC_CTRL */ +#define RFCRC_CTRL_PADCRCINPUT_DEFAULT (_RFCRC_CTRL_PADCRCINPUT_DEFAULT << 12) /**< Shifted mode DEFAULT for RFCRC_CTRL */ +#define RFCRC_CTRL_PADCRCINPUT_X0 (_RFCRC_CTRL_PADCRCINPUT_X0 << 12) /**< Shifted mode X0 for RFCRC_CTRL */ +#define RFCRC_CTRL_PADCRCINPUT_X1 (_RFCRC_CTRL_PADCRCINPUT_X1 << 12) /**< Shifted mode X1 for RFCRC_CTRL */ + +/* Bit fields for RFCRC STATUS */ +#define _RFCRC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RFCRC_STATUS */ +#define _RFCRC_STATUS_MASK 0x00000001UL /**< Mask for RFCRC_STATUS */ +#define RFCRC_STATUS_BUSY (0x1UL << 0) /**< CRC Running */ +#define _RFCRC_STATUS_BUSY_SHIFT 0 /**< Shift value for RFCRC_BUSY */ +#define _RFCRC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for RFCRC_BUSY */ +#define _RFCRC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_STATUS */ +#define RFCRC_STATUS_BUSY_DEFAULT (_RFCRC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_STATUS */ + +/* Bit fields for RFCRC CMD */ +#define _RFCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for RFCRC_CMD */ +#define _RFCRC_CMD_MASK 0x00000001UL /**< Mask for RFCRC_CMD */ +#define RFCRC_CMD_INITIALIZE (0x1UL << 0) /**< Initialize CRC */ +#define _RFCRC_CMD_INITIALIZE_SHIFT 0 /**< Shift value for RFCRC_INITIALIZE */ +#define _RFCRC_CMD_INITIALIZE_MASK 0x1UL /**< Bit mask for RFCRC_INITIALIZE */ +#define _RFCRC_CMD_INITIALIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CMD */ +#define RFCRC_CMD_INITIALIZE_DEFAULT (_RFCRC_CMD_INITIALIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CMD */ + +/* Bit fields for RFCRC INPUTDATA */ +#define _RFCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INPUTDATA */ +#define _RFCRC_INPUTDATA_MASK 0x0000FFFFUL /**< Mask for RFCRC_INPUTDATA */ +#define _RFCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for RFCRC_INPUTDATA */ +#define _RFCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFUL /**< Bit mask for RFCRC_INPUTDATA */ +#define _RFCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INPUTDATA */ +#define RFCRC_INPUTDATA_INPUTDATA_DEFAULT (_RFCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INPUTDATA */ + +/* Bit fields for RFCRC INIT */ +#define _RFCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INIT */ +#define _RFCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_INIT */ +#define _RFCRC_INIT_INIT_SHIFT 0 /**< Shift value for RFCRC_INIT */ +#define _RFCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_INIT */ +#define _RFCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INIT */ +#define RFCRC_INIT_INIT_DEFAULT (_RFCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INIT */ + +/* Bit fields for RFCRC DATA */ +#define _RFCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_DATA */ +#define _RFCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_DATA */ +#define _RFCRC_DATA_DATA_SHIFT 0 /**< Shift value for RFCRC_DATA */ +#define _RFCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_DATA */ +#define _RFCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_DATA */ +#define RFCRC_DATA_DATA_DEFAULT (_RFCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_DATA */ + +/* Bit fields for RFCRC POLY */ +#define _RFCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for RFCRC_POLY */ +#define _RFCRC_POLY_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_POLY */ +#define _RFCRC_POLY_POLY_SHIFT 0 /**< Shift value for RFCRC_POLY */ +#define _RFCRC_POLY_POLY_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_POLY */ +#define _RFCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_POLY */ +#define RFCRC_POLY_POLY_DEFAULT (_RFCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_POLY */ + +/** @} End of group EFR32MG24_RFCRC_BitFields */ +/** @} End of group EFR32MG24_RFCRC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_RFCRC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_scratchpad.h b/EFR32MG24/Device/Include/efr32mg24_scratchpad.h new file mode 100644 index 0000000..d3008dc --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_scratchpad.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SCRATCHPAD register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SCRATCHPAD_H +#define EFR32MG24_SCRATCHPAD_H +#define SCRATCHPAD_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SCRATCHPAD SCRATCHPAD + * @{ + * @brief EFR32MG24 SCRATCHPAD Register Declaration. + *****************************************************************************/ + +/** SCRATCHPAD Register Declaration. */ +typedef struct { + __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ + uint32_t RESERVED0[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ + uint32_t RESERVED1[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ + uint32_t RESERVED2[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ +} SCRATCHPAD_TypeDef; +/** @} End of group EFR32MG24_SCRATCHPAD */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SCRATCHPAD + * @{ + * @defgroup EFR32MG24_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SCRATCHPAD SREG0 */ +#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ +#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ + +/* Bit fields for SCRATCHPAD SREG1 */ +#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ +#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ + +/** @} End of group EFR32MG24_SCRATCHPAD_BitFields */ +/** @} End of group EFR32MG24_SCRATCHPAD */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SCRATCHPAD_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_semailbox.h b/EFR32MG24/Device/Include/efr32mg24_semailbox.h new file mode 100644 index 0000000..cc82c6a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_semailbox.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SEMAILBOX_H +#define EFR32MG24_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief EFR32MG24 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct { + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group EFR32MG24_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SEMAILBOX_HOST + * @{ + * @defgroup EFR32MG24_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group EFR32MG24_SEMAILBOX_HOST_BitFields */ +/** @} End of group EFR32MG24_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup EFR32MG24_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief EFR32MG24 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct { + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SEMAILBOX_APBSE + * @{ + * @defgroup EFR32MG24_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group EFR32MG24_SEMAILBOX_APBSE_BitFields */ +/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SEMAILBOX_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_smu.h b/EFR32MG24/Device/Include/efr32mg24_smu.h new file mode 100644 index 0000000..b416099 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_smu.h @@ -0,0 +1,1483 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SMU_H +#define EFR32MG24_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SMU SMU + * @{ + * @brief EFR32MG24 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +} SMU_TypeDef; +/** @} End of group EFR32MG24_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SMU + * @{ + * @defgroup EFR32MG24_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSRTC_DEFAULT (_SMU_PPUPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ +#define _SMU_PPUPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1_DEFAULT (_SMU_PPUPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ +#define _SMU_PPUPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP_DEFAULT (_SMU_PPUPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSRTC_DEFAULT (_SMU_PPUSATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 1) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 3) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 6) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Secure Access */ +#define _SMU_PPUSATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1_DEFAULT (_SMU_PPUSATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 12) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 15) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP (0x1UL << 20) /**< MVP Secure Access */ +#define _SMU_PPUSATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP_DEFAULT (_SMU_PPUSATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32MG24_SMU_BitFields */ +/** @} End of group EFR32MG24_SMU */ +/**************************************************************************//** + * @defgroup EFR32MG24_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32MG24 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32MG24_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SMU_CFGNS + * @{ + * @defgroup EFR32MG24_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD0_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSRTC_DEFAULT (_SMU_PPUNSPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1_DEFAULT (_SMU_PPUNSPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ +#define _SMU_PPUNSPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUNSPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUNSPATD1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_MVP_DEFAULT (_SMU_PPUNSPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32MG24_SMU_CFGNS_BitFields */ +/** @} End of group EFR32MG24_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SMU_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_synth.h b/EFR32MG24/Device/Include/efr32mg24_synth.h new file mode 100644 index 0000000..3fead39 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_synth.h @@ -0,0 +1,1124 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SYNTH register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2021 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SYNTH_H +#define EFR32MG24_SYNTH_H +#define SYNTH_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SYNTH SYNTH + * @{ + * @brief EFR32MG24 SYNTH Register Declaration. + *****************************************************************************/ + +/** SYNTH Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS; /**< Frequency Synthesizer Status */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CTRL; /**< Frequency Synthesizer Control register */ + uint32_t RESERVED0[6U]; /**< Reserved for future use */ + __IOM uint32_t VCDACCTRL; /**< VCDAC Control register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t FREQ; /**< Frequency Word */ + __IOM uint32_t IFFREQ; /**< IF frequency */ + __IOM uint32_t DIVCTRL; /**< Frequency division control */ + __IOM uint32_t CHCTRL; /**< Frequency Synthesizer Channel Control */ + __IOM uint32_t CHSP; /**< Channel spacing */ + __IOM uint32_t CALOFFSET; /**< Calibration offset */ + __IOM uint32_t VCOTUNING; /**< VCO Frequency tuning */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t VCOGAIN; /**< Calibration values for VCO gain */ + uint32_t RESERVED3[7U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCNTCTRL; /**< LO Counter Control Register */ + __IM uint32_t LOCNTSTATUS; /**< LO Counter Status Register */ + __IM uint32_t LOCNTTARGET; /**< LO Counter Target Value */ + __IOM uint32_t MMDDENOMINIT; /**< Initial Values for MMD Denom */ + __IOM uint32_t CHPDACINIT; /**< Initial Value for CHP DAC */ + __IOM uint32_t LPFCTRL1CAL; /**< LPF control register 1 for CAL mode */ + __IOM uint32_t LPFCTRL1RX; /**< LPF control register 1 for RX mode */ + __IOM uint32_t LPFCTRL1TX; /**< LPF control register 1 for TX mode */ + __IOM uint32_t LPFCTRL2RX; /**< LPF control register 2 for RX mode */ + __IOM uint32_t LPFCTRL2TX; /**< LPF control register 2 for TX mode */ + __IOM uint32_t DSMCTRLRX; /**< DSM Control register for RX mode */ + __IOM uint32_t DSMCTRLTX; /**< DSM Control register for TX mode */ + __IOM uint32_t SEQIF; /**< SEQ Interrupt Flag Register */ + __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED5[976U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_SET; /**< Frequency Synthesizer Status */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t CTRL_SET; /**< Frequency Synthesizer Control register */ + uint32_t RESERVED6[6U]; /**< Reserved for future use */ + __IOM uint32_t VCDACCTRL_SET; /**< VCDAC Control register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t FREQ_SET; /**< Frequency Word */ + __IOM uint32_t IFFREQ_SET; /**< IF frequency */ + __IOM uint32_t DIVCTRL_SET; /**< Frequency division control */ + __IOM uint32_t CHCTRL_SET; /**< Frequency Synthesizer Channel Control */ + __IOM uint32_t CHSP_SET; /**< Channel spacing */ + __IOM uint32_t CALOFFSET_SET; /**< Calibration offset */ + __IOM uint32_t VCOTUNING_SET; /**< VCO Frequency tuning */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t VCOGAIN_SET; /**< Calibration values for VCO gain */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCNTCTRL_SET; /**< LO Counter Control Register */ + __IM uint32_t LOCNTSTATUS_SET; /**< LO Counter Status Register */ + __IM uint32_t LOCNTTARGET_SET; /**< LO Counter Target Value */ + __IOM uint32_t MMDDENOMINIT_SET; /**< Initial Values for MMD Denom */ + __IOM uint32_t CHPDACINIT_SET; /**< Initial Value for CHP DAC */ + __IOM uint32_t LPFCTRL1CAL_SET; /**< LPF control register 1 for CAL mode */ + __IOM uint32_t LPFCTRL1RX_SET; /**< LPF control register 1 for RX mode */ + __IOM uint32_t LPFCTRL1TX_SET; /**< LPF control register 1 for TX mode */ + __IOM uint32_t LPFCTRL2RX_SET; /**< LPF control register 2 for RX mode */ + __IOM uint32_t LPFCTRL2TX_SET; /**< LPF control register 2 for TX mode */ + __IOM uint32_t DSMCTRLRX_SET; /**< DSM Control register for RX mode */ + __IOM uint32_t DSMCTRLTX_SET; /**< DSM Control register for TX mode */ + __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flag Register */ + __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED11[976U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_CLR; /**< Frequency Synthesizer Status */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t CTRL_CLR; /**< Frequency Synthesizer Control register */ + uint32_t RESERVED12[6U]; /**< Reserved for future use */ + __IOM uint32_t VCDACCTRL_CLR; /**< VCDAC Control register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t FREQ_CLR; /**< Frequency Word */ + __IOM uint32_t IFFREQ_CLR; /**< IF frequency */ + __IOM uint32_t DIVCTRL_CLR; /**< Frequency division control */ + __IOM uint32_t CHCTRL_CLR; /**< Frequency Synthesizer Channel Control */ + __IOM uint32_t CHSP_CLR; /**< Channel spacing */ + __IOM uint32_t CALOFFSET_CLR; /**< Calibration offset */ + __IOM uint32_t VCOTUNING_CLR; /**< VCO Frequency tuning */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t VCOGAIN_CLR; /**< Calibration values for VCO gain */ + uint32_t RESERVED15[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCNTCTRL_CLR; /**< LO Counter Control Register */ + __IM uint32_t LOCNTSTATUS_CLR; /**< LO Counter Status Register */ + __IM uint32_t LOCNTTARGET_CLR; /**< LO Counter Target Value */ + __IOM uint32_t MMDDENOMINIT_CLR; /**< Initial Values for MMD Denom */ + __IOM uint32_t CHPDACINIT_CLR; /**< Initial Value for CHP DAC */ + __IOM uint32_t LPFCTRL1CAL_CLR; /**< LPF control register 1 for CAL mode */ + __IOM uint32_t LPFCTRL1RX_CLR; /**< LPF control register 1 for RX mode */ + __IOM uint32_t LPFCTRL1TX_CLR; /**< LPF control register 1 for TX mode */ + __IOM uint32_t LPFCTRL2RX_CLR; /**< LPF control register 2 for RX mode */ + __IOM uint32_t LPFCTRL2TX_CLR; /**< LPF control register 2 for TX mode */ + __IOM uint32_t DSMCTRLRX_CLR; /**< DSM Control register for RX mode */ + __IOM uint32_t DSMCTRLTX_CLR; /**< DSM Control register for TX mode */ + __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flag Register */ + __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */ + uint32_t RESERVED17[976U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ + __IM uint32_t STATUS_TGL; /**< Frequency Synthesizer Status */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t CTRL_TGL; /**< Frequency Synthesizer Control register */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IOM uint32_t VCDACCTRL_TGL; /**< VCDAC Control register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t FREQ_TGL; /**< Frequency Word */ + __IOM uint32_t IFFREQ_TGL; /**< IF frequency */ + __IOM uint32_t DIVCTRL_TGL; /**< Frequency division control */ + __IOM uint32_t CHCTRL_TGL; /**< Frequency Synthesizer Channel Control */ + __IOM uint32_t CHSP_TGL; /**< Channel spacing */ + __IOM uint32_t CALOFFSET_TGL; /**< Calibration offset */ + __IOM uint32_t VCOTUNING_TGL; /**< VCO Frequency tuning */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t VCOGAIN_TGL; /**< Calibration values for VCO gain */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCNTCTRL_TGL; /**< LO Counter Control Register */ + __IM uint32_t LOCNTSTATUS_TGL; /**< LO Counter Status Register */ + __IM uint32_t LOCNTTARGET_TGL; /**< LO Counter Target Value */ + __IOM uint32_t MMDDENOMINIT_TGL; /**< Initial Values for MMD Denom */ + __IOM uint32_t CHPDACINIT_TGL; /**< Initial Value for CHP DAC */ + __IOM uint32_t LPFCTRL1CAL_TGL; /**< LPF control register 1 for CAL mode */ + __IOM uint32_t LPFCTRL1RX_TGL; /**< LPF control register 1 for RX mode */ + __IOM uint32_t LPFCTRL1TX_TGL; /**< LPF control register 1 for TX mode */ + __IOM uint32_t LPFCTRL2RX_TGL; /**< LPF control register 2 for RX mode */ + __IOM uint32_t LPFCTRL2TX_TGL; /**< LPF control register 2 for TX mode */ + __IOM uint32_t DSMCTRLRX_TGL; /**< DSM Control register for RX mode */ + __IOM uint32_t DSMCTRLTX_TGL; /**< DSM Control register for TX mode */ + __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flag Register */ + __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */ +} SYNTH_TypeDef; +/** @} End of group EFR32MG24_SYNTH */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYNTH + * @{ + * @defgroup EFR32MG24_SYNTH_BitFields SYNTH Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYNTH IPVERSION */ +#define _SYNTH_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SYNTH_IPVERSION */ +#define _SYNTH_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYNTH_IPVERSION */ +#define _SYNTH_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYNTH_IPVERSION */ +#define _SYNTH_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYNTH_IPVERSION */ +#define _SYNTH_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYNTH_IPVERSION */ +#define SYNTH_IPVERSION_IPVERSION_DEFAULT (_SYNTH_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IPVERSION */ + +/* Bit fields for SYNTH EN */ +#define _SYNTH_EN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_EN */ +#define _SYNTH_EN_MASK 0x00000001UL /**< Mask for SYNTH_EN */ +#define SYNTH_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ +#define _SYNTH_EN_EN_SHIFT 0 /**< Shift value for SYNTH_EN */ +#define _SYNTH_EN_EN_MASK 0x1UL /**< Bit mask for SYNTH_EN */ +#define _SYNTH_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_EN */ +#define SYNTH_EN_EN_DEFAULT (_SYNTH_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_EN */ + +/* Bit fields for SYNTH STATUS */ +#define _SYNTH_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYNTH_STATUS */ +#define _SYNTH_STATUS_MASK 0x04014707UL /**< Mask for SYNTH_STATUS */ +#define SYNTH_STATUS_INLOCK (0x1UL << 0) /**< RF Synthesizer in Lock */ +#define _SYNTH_STATUS_INLOCK_SHIFT 0 /**< Shift value for SYNTH_INLOCK */ +#define _SYNTH_STATUS_INLOCK_MASK 0x1UL /**< Bit mask for SYNTH_INLOCK */ +#define _SYNTH_STATUS_INLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_STATUS */ +#define SYNTH_STATUS_INLOCK_DEFAULT (_SYNTH_STATUS_INLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_STATUS */ +#define SYNTH_STATUS_IFFREQEN (0x1UL << 1) /**< Synthesizer IF frequency enable status */ +#define _SYNTH_STATUS_IFFREQEN_SHIFT 1 /**< Shift value for SYNTH_IFFREQEN */ +#define _SYNTH_STATUS_IFFREQEN_MASK 0x2UL /**< Bit mask for SYNTH_IFFREQEN */ +#define _SYNTH_STATUS_IFFREQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_STATUS */ +#define SYNTH_STATUS_IFFREQEN_DEFAULT (_SYNTH_STATUS_IFFREQEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_STATUS */ + +/* Bit fields for SYNTH CMD */ +#define _SYNTH_CMD_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CMD */ +#define _SYNTH_CMD_MASK 0x0000061FUL /**< Mask for SYNTH_CMD */ +#define SYNTH_CMD_SYNTHSTART (0x1UL << 0) /**< Starts the RF synthesizer */ +#define _SYNTH_CMD_SYNTHSTART_SHIFT 0 /**< Shift value for SYNTH_SYNTHSTART */ +#define _SYNTH_CMD_SYNTHSTART_MASK 0x1UL /**< Bit mask for SYNTH_SYNTHSTART */ +#define _SYNTH_CMD_SYNTHSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_SYNTHSTART_DEFAULT (_SYNTH_CMD_SYNTHSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_SYNTHSTOP (0x1UL << 1) /**< Stops the RF synthesizer */ +#define _SYNTH_CMD_SYNTHSTOP_SHIFT 1 /**< Shift value for SYNTH_SYNTHSTOP */ +#define _SYNTH_CMD_SYNTHSTOP_MASK 0x2UL /**< Bit mask for SYNTH_SYNTHSTOP */ +#define _SYNTH_CMD_SYNTHSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_SYNTHSTOP_DEFAULT (_SYNTH_CMD_SYNTHSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_ENABLEIF (0x1UL << 2) /**< Enable the synthesizer IF frequency */ +#define _SYNTH_CMD_ENABLEIF_SHIFT 2 /**< Shift value for SYNTH_ENABLEIF */ +#define _SYNTH_CMD_ENABLEIF_MASK 0x4UL /**< Bit mask for SYNTH_ENABLEIF */ +#define _SYNTH_CMD_ENABLEIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_ENABLEIF_DEFAULT (_SYNTH_CMD_ENABLEIF_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_DISABLEIF (0x1UL << 3) /**< Disable the synthesizer IF frequency */ +#define _SYNTH_CMD_DISABLEIF_SHIFT 3 /**< Shift value for SYNTH_DISABLEIF */ +#define _SYNTH_CMD_DISABLEIF_MASK 0x8UL /**< Bit mask for SYNTH_DISABLEIF */ +#define _SYNTH_CMD_DISABLEIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_DISABLEIF_DEFAULT (_SYNTH_CMD_DISABLEIF_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_CAPCALSTART (0x1UL << 4) /**< Start VCO capacitor array calibration */ +#define _SYNTH_CMD_CAPCALSTART_SHIFT 4 /**< Shift value for SYNTH_CAPCALSTART */ +#define _SYNTH_CMD_CAPCALSTART_MASK 0x10UL /**< Bit mask for SYNTH_CAPCALSTART */ +#define _SYNTH_CMD_CAPCALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */ +#define SYNTH_CMD_CAPCALSTART_DEFAULT (_SYNTH_CMD_CAPCALSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_CMD */ + +/* Bit fields for SYNTH CTRL */ +#define _SYNTH_CTRL_RESETVALUE 0x00000003UL /**< Default value for SYNTH_CTRL */ +#define _SYNTH_CTRL_MASK 0xD9F70007UL /**< Mask for SYNTH_CTRL */ +#define _SYNTH_CTRL_LOCKTHRESHOLD_SHIFT 0 /**< Shift value for SYNTH_LOCKTHRESHOLD */ +#define _SYNTH_CTRL_LOCKTHRESHOLD_MASK 0x7UL /**< Bit mask for SYNTH_LOCKTHRESHOLD */ +#define _SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT (_SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_SHIFT 16 /**< Shift value for SYNTH_PRSMUX0 */ +#define _SYNTH_CTRL_PRSMUX0_MASK 0x70000UL /**< Bit mask for SYNTH_PRSMUX0 */ +#define _SYNTH_CTRL_PRSMUX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_INLOCK 0x00000001UL /**< Mode INLOCK for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_LOCK_WINDOW 0x00000002UL /**< Mode LOCK_WINDOW for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_FPLL 0x00000003UL /**< Mode FPLL for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_VCCMP_HI 0x00000004UL /**< Mode VCCMP_HI for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK 0x00000005UL /**< Mode VCO_AMPLITUDE_OK for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D 0x00000006UL /**< Mode VCO_DET_OUT_D for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_DEFAULT (_SYNTH_CTRL_PRSMUX0_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_DISABLED (_SYNTH_CTRL_PRSMUX0_DISABLED << 16) /**< Shifted mode DISABLED for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_INLOCK (_SYNTH_CTRL_PRSMUX0_INLOCK << 16) /**< Shifted mode INLOCK for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_LOCK_WINDOW (_SYNTH_CTRL_PRSMUX0_LOCK_WINDOW << 16) /**< Shifted mode LOCK_WINDOW for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_FPLL (_SYNTH_CTRL_PRSMUX0_FPLL << 16) /**< Shifted mode FPLL for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_VCCMP_HI (_SYNTH_CTRL_PRSMUX0_VCCMP_HI << 16) /**< Shifted mode VCCMP_HI for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK (_SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK << 16) /**< Shifted mode VCO_AMPLITUDE_OK for SYNTH_CTRL*/ +#define SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D (_SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D << 16) /**< Shifted mode VCO_DET_OUT_D for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_SHIFT 20 /**< Shift value for SYNTH_PRSMUX1 */ +#define _SYNTH_CTRL_PRSMUX1_MASK 0x700000UL /**< Bit mask for SYNTH_PRSMUX1 */ +#define _SYNTH_CTRL_PRSMUX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_AUXINLOCK 0x00000001UL /**< Mode AUXINLOCK for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_REF_IS_LEADING 0x00000002UL /**< Mode REF_IS_LEADING for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_FPLL 0x00000003UL /**< Mode FPLL for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_VCCMP_LOW 0x00000004UL /**< Mode VCCMP_LOW for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N 0x00000005UL /**< Mode MMD_PRESCALER_RESET_N for SYNTH_CTRL */ +#define _SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 0x00000006UL /**< Mode CLK_SYNTH_DIV2 for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_DEFAULT (_SYNTH_CTRL_PRSMUX1_DEFAULT << 20) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_DISABLED (_SYNTH_CTRL_PRSMUX1_DISABLED << 20) /**< Shifted mode DISABLED for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_AUXINLOCK (_SYNTH_CTRL_PRSMUX1_AUXINLOCK << 20) /**< Shifted mode AUXINLOCK for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_REF_IS_LEADING (_SYNTH_CTRL_PRSMUX1_REF_IS_LEADING << 20) /**< Shifted mode REF_IS_LEADING for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_FPLL (_SYNTH_CTRL_PRSMUX1_FPLL << 20) /**< Shifted mode FPLL for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_VCCMP_LOW (_SYNTH_CTRL_PRSMUX1_VCCMP_LOW << 20) /**< Shifted mode VCCMP_LOW for SYNTH_CTRL */ +#define SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N (_SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N << 20) /**< Shifted mode MMD_PRESCALER_RESET_N for SYNTH_CTRL*/ +#define SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 (_SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 << 20) /**< Shifted mode CLK_SYNTH_DIV2 for SYNTH_CTRL */ +#define SYNTH_CTRL_DISCLKSYNTH (0x1UL << 23) /**< Disable clk_synth */ +#define _SYNTH_CTRL_DISCLKSYNTH_SHIFT 23 /**< Shift value for SYNTH_DISCLKSYNTH */ +#define _SYNTH_CTRL_DISCLKSYNTH_MASK 0x800000UL /**< Bit mask for SYNTH_DISCLKSYNTH */ +#define _SYNTH_CTRL_DISCLKSYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_DISCLKSYNTH_ENABLE 0x00000000UL /**< Mode ENABLE for SYNTH_CTRL */ +#define _SYNTH_CTRL_DISCLKSYNTH_DISABLE 0x00000001UL /**< Mode DISABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_DISCLKSYNTH_DEFAULT (_SYNTH_CTRL_DISCLKSYNTH_DEFAULT << 23) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_DISCLKSYNTH_ENABLE (_SYNTH_CTRL_DISCLKSYNTH_ENABLE << 23) /**< Shifted mode ENABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_DISCLKSYNTH_DISABLE (_SYNTH_CTRL_DISCLKSYNTH_DISABLE << 23) /**< Shifted mode DISABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_INVCLKSYNTH (0x1UL << 24) /**< Invert clk_synth */ +#define _SYNTH_CTRL_INVCLKSYNTH_SHIFT 24 /**< Shift value for SYNTH_INVCLKSYNTH */ +#define _SYNTH_CTRL_INVCLKSYNTH_MASK 0x1000000UL /**< Bit mask for SYNTH_INVCLKSYNTH */ +#define _SYNTH_CTRL_INVCLKSYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_INVCLKSYNTH_NO 0x00000000UL /**< Mode NO for SYNTH_CTRL */ +#define _SYNTH_CTRL_INVCLKSYNTH_YES 0x00000001UL /**< Mode YES for SYNTH_CTRL */ +#define SYNTH_CTRL_INVCLKSYNTH_DEFAULT (_SYNTH_CTRL_INVCLKSYNTH_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_INVCLKSYNTH_NO (_SYNTH_CTRL_INVCLKSYNTH_NO << 24) /**< Shifted mode NO for SYNTH_CTRL */ +#define SYNTH_CTRL_INVCLKSYNTH_YES (_SYNTH_CTRL_INVCLKSYNTH_YES << 24) /**< Shifted mode YES for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDRSTNOVERRIDEEN (0x1UL << 30) /**< Enable MMD reset override */ +#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_SHIFT 30 /**< Shift value for SYNTH_MMDRSTNOVERRIDEEN */ +#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_MASK 0x40000000UL /**< Bit mask for SYNTH_MMDRSTNOVERRIDEEN */ +#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_CTRL */ +#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT << 30) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE << 30) /**< Shifted mode DISABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE << 30) /**< Shifted mode ENABLE for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDMANRSTN (0x1UL << 31) /**< Manual MMD reset */ +#define _SYNTH_CTRL_MMDMANRSTN_SHIFT 31 /**< Shift value for SYNTH_MMDMANRSTN */ +#define _SYNTH_CTRL_MMDMANRSTN_MASK 0x80000000UL /**< Bit mask for SYNTH_MMDMANRSTN */ +#define _SYNTH_CTRL_MMDMANRSTN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */ +#define _SYNTH_CTRL_MMDMANRSTN_RESET 0x00000000UL /**< Mode RESET for SYNTH_CTRL */ +#define _SYNTH_CTRL_MMDMANRSTN_NORESET 0x00000001UL /**< Mode NORESET for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDMANRSTN_DEFAULT (_SYNTH_CTRL_MMDMANRSTN_DEFAULT << 31) /**< Shifted mode DEFAULT for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDMANRSTN_RESET (_SYNTH_CTRL_MMDMANRSTN_RESET << 31) /**< Shifted mode RESET for SYNTH_CTRL */ +#define SYNTH_CTRL_MMDMANRSTN_NORESET (_SYNTH_CTRL_MMDMANRSTN_NORESET << 31) /**< Shifted mode NORESET for SYNTH_CTRL */ + +/* Bit fields for SYNTH VCDACCTRL */ +#define _SYNTH_VCDACCTRL_RESETVALUE 0x00000020UL /**< Default value for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_MASK 0x000001FFUL /**< Mask for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_VCDACVAL_SHIFT 0 /**< Shift value for SYNTH_VCDACVAL */ +#define _SYNTH_VCDACCTRL_VCDACVAL_MASK 0x3FUL /**< Bit mask for SYNTH_VCDACVAL */ +#define _SYNTH_VCDACCTRL_VCDACVAL_DEFAULT 0x00000020UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_VCDACVAL_DEFAULT (_SYNTH_VCDACCTRL_VCDACVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_VCDACEN (0x1UL << 6) /**< Enable VCDAC */ +#define _SYNTH_VCDACCTRL_VCDACEN_SHIFT 6 /**< Shift value for SYNTH_VCDACEN */ +#define _SYNTH_VCDACCTRL_VCDACEN_MASK 0x40UL /**< Bit mask for SYNTH_VCDACEN */ +#define _SYNTH_VCDACCTRL_VCDACEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_VCDACEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_VCDACEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_VCDACEN_DEFAULT (_SYNTH_VCDACCTRL_VCDACEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_VCDACEN_DISABLE (_SYNTH_VCDACCTRL_VCDACEN_DISABLE << 6) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_VCDACEN_ENABLE (_SYNTH_VCDACCTRL_VCDACEN_ENABLE << 6) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFEN (0x1UL << 7) /**< LPF Enable Control */ +#define _SYNTH_VCDACCTRL_LPFEN_SHIFT 7 /**< Shift value for SYNTH_LPFEN */ +#define _SYNTH_VCDACCTRL_LPFEN_MASK 0x80UL /**< Bit mask for SYNTH_LPFEN */ +#define _SYNTH_VCDACCTRL_LPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_LPFEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_LPFEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFEN_DEFAULT (_SYNTH_VCDACCTRL_LPFEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFEN_DISABLE (_SYNTH_VCDACCTRL_LPFEN_DISABLE << 7) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFEN_ENABLE (_SYNTH_VCDACCTRL_LPFEN_ENABLE << 7) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFQSEN (0x1UL << 8) /**< LPF Quickstart Control */ +#define _SYNTH_VCDACCTRL_LPFQSEN_SHIFT 8 /**< Shift value for SYNTH_LPFQSEN */ +#define _SYNTH_VCDACCTRL_LPFQSEN_MASK 0x100UL /**< Bit mask for SYNTH_LPFQSEN */ +#define _SYNTH_VCDACCTRL_LPFQSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_LPFQSEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */ +#define _SYNTH_VCDACCTRL_LPFQSEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFQSEN_DEFAULT (_SYNTH_VCDACCTRL_LPFQSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFQSEN_DISABLE (_SYNTH_VCDACCTRL_LPFQSEN_DISABLE << 8) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */ +#define SYNTH_VCDACCTRL_LPFQSEN_ENABLE (_SYNTH_VCDACCTRL_LPFQSEN_ENABLE << 8) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */ + +/* Bit fields for SYNTH FREQ */ +#define _SYNTH_FREQ_RESETVALUE 0x00000000UL /**< Default value for SYNTH_FREQ */ +#define _SYNTH_FREQ_MASK 0x0FFFFFFFUL /**< Mask for SYNTH_FREQ */ +#define _SYNTH_FREQ_FREQ_SHIFT 0 /**< Shift value for SYNTH_FREQ */ +#define _SYNTH_FREQ_FREQ_MASK 0xFFFFFFFUL /**< Bit mask for SYNTH_FREQ */ +#define _SYNTH_FREQ_FREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_FREQ */ +#define SYNTH_FREQ_FREQ_DEFAULT (_SYNTH_FREQ_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_FREQ */ + +/* Bit fields for SYNTH IFFREQ */ +#define _SYNTH_IFFREQ_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_MASK 0x001FFFFFUL /**< Mask for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_IFFREQ_SHIFT 0 /**< Shift value for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_IFFREQ_MASK 0xFFFFFUL /**< Bit mask for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_IFFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IFFREQ */ +#define SYNTH_IFFREQ_IFFREQ_DEFAULT (_SYNTH_IFFREQ_IFFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IFFREQ */ +#define SYNTH_IFFREQ_LOSIDE (0x1UL << 20) /**< Configure LO in receive */ +#define _SYNTH_IFFREQ_LOSIDE_SHIFT 20 /**< Shift value for SYNTH_LOSIDE */ +#define _SYNTH_IFFREQ_LOSIDE_MASK 0x100000UL /**< Bit mask for SYNTH_LOSIDE */ +#define _SYNTH_IFFREQ_LOSIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_LOSIDE_LOW 0x00000000UL /**< Mode LOW for SYNTH_IFFREQ */ +#define _SYNTH_IFFREQ_LOSIDE_HIGH 0x00000001UL /**< Mode HIGH for SYNTH_IFFREQ */ +#define SYNTH_IFFREQ_LOSIDE_DEFAULT (_SYNTH_IFFREQ_LOSIDE_DEFAULT << 20) /**< Shifted mode DEFAULT for SYNTH_IFFREQ */ +#define SYNTH_IFFREQ_LOSIDE_LOW (_SYNTH_IFFREQ_LOSIDE_LOW << 20) /**< Shifted mode LOW for SYNTH_IFFREQ */ +#define SYNTH_IFFREQ_LOSIDE_HIGH (_SYNTH_IFFREQ_LOSIDE_HIGH << 20) /**< Shifted mode HIGH for SYNTH_IFFREQ */ + +/* Bit fields for SYNTH DIVCTRL */ +#define _SYNTH_DIVCTRL_RESETVALUE 0x00000001UL /**< Default value for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_MASK 0x000001FFUL /**< Mask for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_SHIFT 0 /**< Shift value for SYNTH_LODIVFREQCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_MASK 0x1FFUL /**< Bit mask for SYNTH_LODIVFREQCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 0x00000001UL /**< Mode LODIV1 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 0x00000002UL /**< Mode LODIV2 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 0x00000003UL /**< Mode LODIV3 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 0x00000004UL /**< Mode LODIV4 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 0x00000005UL /**< Mode LODIV5 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 0x00000007UL /**< Mode LODIV7 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 0x00000013UL /**< Mode LODIV6 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 0x00000014UL /**< Mode LODIV8 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 0x00000015UL /**< Mode LODIV10 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 0x00000017UL /**< Mode LODIV14 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 0x0000001BUL /**< Mode LODIV9 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 0x0000001CUL /**< Mode LODIV12 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 0x0000001DUL /**< Mode LODIV15 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 0x00000024UL /**< Mode LODIV16 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 0x00000025UL /**< Mode LODIV20 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 0x0000009BUL /**< Mode LODIV18 for SYNTH_DIVCTRL */ +#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 0x0000009CUL /**< Mode LODIV24 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT (_SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 << 0) /**< Shifted mode LODIV1 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 << 0) /**< Shifted mode LODIV2 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 << 0) /**< Shifted mode LODIV3 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 << 0) /**< Shifted mode LODIV4 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 << 0) /**< Shifted mode LODIV5 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 << 0) /**< Shifted mode LODIV7 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 << 0) /**< Shifted mode LODIV6 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 << 0) /**< Shifted mode LODIV8 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 << 0) /**< Shifted mode LODIV10 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 << 0) /**< Shifted mode LODIV14 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 << 0) /**< Shifted mode LODIV9 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 << 0) /**< Shifted mode LODIV12 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 << 0) /**< Shifted mode LODIV15 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 << 0) /**< Shifted mode LODIV16 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 << 0) /**< Shifted mode LODIV20 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 << 0) /**< Shifted mode LODIV18 for SYNTH_DIVCTRL */ +#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 << 0) /**< Shifted mode LODIV24 for SYNTH_DIVCTRL */ + +/* Bit fields for SYNTH CHCTRL */ +#define _SYNTH_CHCTRL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHCTRL */ +#define _SYNTH_CHCTRL_MASK 0x0000003FUL /**< Mask for SYNTH_CHCTRL */ +#define _SYNTH_CHCTRL_CHNO_SHIFT 0 /**< Shift value for SYNTH_CHNO */ +#define _SYNTH_CHCTRL_CHNO_MASK 0x3FUL /**< Bit mask for SYNTH_CHNO */ +#define _SYNTH_CHCTRL_CHNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHCTRL */ +#define SYNTH_CHCTRL_CHNO_DEFAULT (_SYNTH_CHCTRL_CHNO_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHCTRL */ + +/* Bit fields for SYNTH CHSP */ +#define _SYNTH_CHSP_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHSP */ +#define _SYNTH_CHSP_MASK 0x0003FFFFUL /**< Mask for SYNTH_CHSP */ +#define _SYNTH_CHSP_CHSP_SHIFT 0 /**< Shift value for SYNTH_CHSP */ +#define _SYNTH_CHSP_CHSP_MASK 0x3FFFFUL /**< Bit mask for SYNTH_CHSP */ +#define _SYNTH_CHSP_CHSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHSP */ +#define SYNTH_CHSP_CHSP_DEFAULT (_SYNTH_CHSP_CHSP_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHSP */ + +/* Bit fields for SYNTH CALOFFSET */ +#define _SYNTH_CALOFFSET_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CALOFFSET */ +#define _SYNTH_CALOFFSET_MASK 0x00007FFFUL /**< Mask for SYNTH_CALOFFSET */ +#define _SYNTH_CALOFFSET_CALOFFSET_SHIFT 0 /**< Shift value for SYNTH_CALOFFSET */ +#define _SYNTH_CALOFFSET_CALOFFSET_MASK 0x7FFFUL /**< Bit mask for SYNTH_CALOFFSET */ +#define _SYNTH_CALOFFSET_CALOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CALOFFSET */ +#define SYNTH_CALOFFSET_CALOFFSET_DEFAULT (_SYNTH_CALOFFSET_CALOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CALOFFSET */ + +/* Bit fields for SYNTH VCOTUNING */ +#define _SYNTH_VCOTUNING_RESETVALUE 0x00008400UL /**< Default value for SYNTH_VCOTUNING */ +#define _SYNTH_VCOTUNING_MASK 0x0000FFFFUL /**< Mask for SYNTH_VCOTUNING */ +#define _SYNTH_VCOTUNING_VCOTUNING_SHIFT 0 /**< Shift value for SYNTH_VCOTUNING */ +#define _SYNTH_VCOTUNING_VCOTUNING_MASK 0x7FFUL /**< Bit mask for SYNTH_VCOTUNING */ +#define _SYNTH_VCOTUNING_VCOTUNING_DEFAULT 0x00000400UL /**< Mode DEFAULT for SYNTH_VCOTUNING */ +#define SYNTH_VCOTUNING_VCOTUNING_DEFAULT (_SYNTH_VCOTUNING_VCOTUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCOTUNING */ +#define _SYNTH_VCOTUNING_VCAPSEL_SHIFT 11 /**< Shift value for SYNTH_VCAPSEL */ +#define _SYNTH_VCOTUNING_VCAPSEL_MASK 0xF800UL /**< Bit mask for SYNTH_VCAPSEL */ +#define _SYNTH_VCOTUNING_VCAPSEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for SYNTH_VCOTUNING */ +#define SYNTH_VCOTUNING_VCAPSEL_DEFAULT (_SYNTH_VCOTUNING_VCAPSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_VCOTUNING */ + +/* Bit fields for SYNTH VCOGAIN */ +#define _SYNTH_VCOGAIN_RESETVALUE 0x00000077UL /**< Default value for SYNTH_VCOGAIN */ +#define _SYNTH_VCOGAIN_MASK 0x000000FFUL /**< Mask for SYNTH_VCOGAIN */ +#define _SYNTH_VCOGAIN_VCOKVCOARSE_SHIFT 0 /**< Shift value for SYNTH_VCOKVCOARSE */ +#define _SYNTH_VCOGAIN_VCOKVCOARSE_MASK 0xFUL /**< Bit mask for SYNTH_VCOKVCOARSE */ +#define _SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT 0x00000007UL /**< Mode DEFAULT for SYNTH_VCOGAIN */ +#define SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT (_SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCOGAIN */ +#define _SYNTH_VCOGAIN_VCOKVFINE_SHIFT 4 /**< Shift value for SYNTH_VCOKVFINE */ +#define _SYNTH_VCOGAIN_VCOKVFINE_MASK 0xF0UL /**< Bit mask for SYNTH_VCOKVFINE */ +#define _SYNTH_VCOGAIN_VCOKVFINE_DEFAULT 0x00000007UL /**< Mode DEFAULT for SYNTH_VCOGAIN */ +#define SYNTH_VCOGAIN_VCOKVFINE_DEFAULT (_SYNTH_VCOGAIN_VCOKVFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_VCOGAIN */ + +/* Bit fields for SYNTH IF */ +#define _SYNTH_IF_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IF */ +#define _SYNTH_IF_MASK 0x00000237UL /**< Mask for SYNTH_IF */ +#define SYNTH_IF_LOCKED (0x1UL << 0) /**< Synthesizer locked Interrupt Flag */ +#define _SYNTH_IF_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */ +#define _SYNTH_IF_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */ +#define _SYNTH_IF_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_LOCKED_DEFAULT (_SYNTH_IF_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_UNLOCKED (0x1UL << 1) /**< Synthesizer unlocked Interrupt Flag */ +#define _SYNTH_IF_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */ +#define _SYNTH_IF_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */ +#define _SYNTH_IF_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_UNLOCKED_DEFAULT (_SYNTH_IF_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_SYRDY (0x1UL << 2) /**< Synthesizer ready Interrupt Flag */ +#define _SYNTH_IF_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */ +#define _SYNTH_IF_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */ +#define _SYNTH_IF_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_SYRDY_DEFAULT (_SYNTH_IF_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_VCOHIGH (0x1UL << 4) /**< VCO high voltage Interrupt Flag */ +#define _SYNTH_IF_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */ +#define _SYNTH_IF_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */ +#define _SYNTH_IF_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_VCOHIGH_DEFAULT (_SYNTH_IF_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_VCOLOW (0x1UL << 5) /**< VCO low voltage Interrupt Flag */ +#define _SYNTH_IF_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */ +#define _SYNTH_IF_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */ +#define _SYNTH_IF_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_VCOLOW_DEFAULT (_SYNTH_IF_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_LOCNTDONE (0x1UL << 9) /**< LOCNT measurement done Interrupt Flag */ +#define _SYNTH_IF_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */ +#define _SYNTH_IF_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */ +#define _SYNTH_IF_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */ +#define SYNTH_IF_LOCNTDONE_DEFAULT (_SYNTH_IF_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_IF */ + +/* Bit fields for SYNTH IEN */ +#define _SYNTH_IEN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IEN */ +#define _SYNTH_IEN_MASK 0x00000237UL /**< Mask for SYNTH_IEN */ +#define SYNTH_IEN_LOCKED (0x1UL << 0) /**< LOCKED Interrupt Enable */ +#define _SYNTH_IEN_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */ +#define _SYNTH_IEN_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */ +#define _SYNTH_IEN_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_LOCKED_DEFAULT (_SYNTH_IEN_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_UNLOCKED (0x1UL << 1) /**< UNLOCKED Interrupt Enable */ +#define _SYNTH_IEN_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */ +#define _SYNTH_IEN_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */ +#define _SYNTH_IEN_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_UNLOCKED_DEFAULT (_SYNTH_IEN_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_SYRDY (0x1UL << 2) /**< CAPCALDONE Interrupt Enable */ +#define _SYNTH_IEN_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */ +#define _SYNTH_IEN_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */ +#define _SYNTH_IEN_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_SYRDY_DEFAULT (_SYNTH_IEN_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_VCOHIGH (0x1UL << 4) /**< VCOHIGH Interrupt Enable */ +#define _SYNTH_IEN_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */ +#define _SYNTH_IEN_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */ +#define _SYNTH_IEN_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_VCOHIGH_DEFAULT (_SYNTH_IEN_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_VCOLOW (0x1UL << 5) /**< VCOLOW Interrupt Enable */ +#define _SYNTH_IEN_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */ +#define _SYNTH_IEN_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */ +#define _SYNTH_IEN_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_VCOLOW_DEFAULT (_SYNTH_IEN_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_LOCNTDONE (0x1UL << 9) /**< LOCNTDONE Interrupt Enable */ +#define _SYNTH_IEN_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */ +#define _SYNTH_IEN_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */ +#define _SYNTH_IEN_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */ +#define SYNTH_IEN_LOCNTDONE_DEFAULT (_SYNTH_IEN_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_IEN */ + +/* Bit fields for SYNTH LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_MASK 0x00000FFFUL /**< Mask for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_ENABLE (0x1UL << 0) /**< Enable LO Counter */ +#define _SYNTH_LOCNTCTRL_ENABLE_SHIFT 0 /**< Shift value for SYNTH_ENABLE */ +#define _SYNTH_LOCNTCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SYNTH_ENABLE */ +#define _SYNTH_LOCNTCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_ENABLE_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_ENABLE_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_ENABLE_DEFAULT (_SYNTH_LOCNTCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_ENABLE_OFF (_SYNTH_LOCNTCTRL_ENABLE_OFF << 0) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_ENABLE_ON (_SYNTH_LOCNTCTRL_ENABLE_ON << 0) /**< Shifted mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_CLEAR (0x1UL << 1) /**< Clear LO Counter */ +#define _SYNTH_LOCNTCTRL_CLEAR_SHIFT 1 /**< Shift value for SYNTH_CLEAR */ +#define _SYNTH_LOCNTCTRL_CLEAR_MASK 0x2UL /**< Bit mask for SYNTH_CLEAR */ +#define _SYNTH_LOCNTCTRL_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_CLEAR_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_CLEAR_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_CLEAR_DEFAULT (_SYNTH_LOCNTCTRL_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_CLEAR_OFF (_SYNTH_LOCNTCTRL_CLEAR_OFF << 1) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_CLEAR_ON (_SYNTH_LOCNTCTRL_CLEAR_ON << 1) /**< Shifted mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_RUN (0x1UL << 2) /**< Run LO Counter */ +#define _SYNTH_LOCNTCTRL_RUN_SHIFT 2 /**< Shift value for SYNTH_RUN */ +#define _SYNTH_LOCNTCTRL_RUN_MASK 0x4UL /**< Bit mask for SYNTH_RUN */ +#define _SYNTH_LOCNTCTRL_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_RUN_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_RUN_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_RUN_DEFAULT (_SYNTH_LOCNTCTRL_RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_RUN_OFF (_SYNTH_LOCNTCTRL_RUN_OFF << 2) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_RUN_ON (_SYNTH_LOCNTCTRL_RUN_ON << 2) /**< Shifted mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_READ (0x1UL << 3) /**< Read LO Counter */ +#define _SYNTH_LOCNTCTRL_READ_SHIFT 3 /**< Shift value for SYNTH_READ */ +#define _SYNTH_LOCNTCTRL_READ_MASK 0x8UL /**< Bit mask for SYNTH_READ */ +#define _SYNTH_LOCNTCTRL_READ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_READ_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_READ_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_READ_DEFAULT (_SYNTH_LOCNTCTRL_READ_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_READ_OFF (_SYNTH_LOCNTCTRL_READ_OFF << 3) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_READ_ON (_SYNTH_LOCNTCTRL_READ_ON << 3) /**< Shifted mode ON for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_SHIFT 4 /**< Shift value for SYNTH_NUMCYCLE */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_MASK 0xF0UL /**< Bit mask for SYNTH_NUMCYCLE */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 0x00000000UL /**< Mode CNT_2 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 0x00000001UL /**< Mode CNT_4 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 0x00000002UL /**< Mode CNT_8 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 0x00000003UL /**< Mode CNT_16 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 0x00000004UL /**< Mode CNT_32 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 0x00000005UL /**< Mode CNT_64 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 0x00000006UL /**< Mode CNT_128 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 0x00000007UL /**< Mode CNT_256 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 0x00000008UL /**< Mode CNT_512 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 0x00000009UL /**< Mode CNT_1024 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 0x0000000AUL /**< Mode CNT_2048 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 0x0000000BUL /**< Mode CNT_4096 for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 0x0000000CUL /**< Mode CNT_8192 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT (_SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 << 4) /**< Shifted mode CNT_2 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 << 4) /**< Shifted mode CNT_4 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 << 4) /**< Shifted mode CNT_8 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 << 4) /**< Shifted mode CNT_16 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 << 4) /**< Shifted mode CNT_32 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 << 4) /**< Shifted mode CNT_64 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 << 4) /**< Shifted mode CNT_128 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 << 4) /**< Shifted mode CNT_256 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 << 4) /**< Shifted mode CNT_512 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 << 4) /**< Shifted mode CNT_1024 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 << 4) /**< Shifted mode CNT_2048 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 << 4) /**< Shifted mode CNT_4096 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 << 4) /**< Shifted mode CNT_8192 for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN (0x1UL << 8) /**< Enable manual override of CLEAR and RUN */ +#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_SHIFT 8 /**< Shift value for SYNTH_LOCNTOVERRIDEEN */ +#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_MASK 0x100UL /**< Bit mask for SYNTH_LOCNTOVERRIDEEN */ +#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE << 8) /**< Shifted mode DISABLE for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE << 8) /**< Shifted mode ENABLE for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR (0x1UL << 9) /**< Manual Control of LO counter CLEAR */ +#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_SHIFT 9 /**< Shift value for SYNTH_LOCNTMANCLEAR */ +#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTMANCLEAR */ +#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR 0x00000000UL /**< Mode NOCLEAR for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR 0x00000001UL /**< Mode CLEAR for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR << 9) /**< Shifted mode NOCLEAR for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR << 9) /**< Shifted mode CLEAR for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANRUN (0x1UL << 10) /**< Manual Control of the LO counter RUN */ +#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_SHIFT 10 /**< Shift value for SYNTH_LOCNTMANRUN */ +#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_MASK 0x400UL /**< Bit mask for SYNTH_LOCNTMANRUN */ +#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN 0x00000000UL /**< Mode NORUN for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN 0x00000001UL /**< Mode RUN for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN (_SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN << 10) /**< Shifted mode NORUN for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN (_SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN << 10) /**< Shifted mode RUN for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_FCALRUNCLKEN (0x1UL << 11) /**< Enable FCAL run pulse counter clock */ +#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_SHIFT 11 /**< Shift value for SYNTH_FCALRUNCLKEN */ +#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_MASK 0x800UL /**< Bit mask for SYNTH_FCALRUNCLKEN */ +#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LOCNTCTRL */ +#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE << 11) /**< Shifted mode DISABLE for SYNTH_LOCNTCTRL */ +#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE << 11) /**< Shifted mode ENABLE for SYNTH_LOCNTCTRL */ + +/* Bit fields for SYNTH LOCNTSTATUS */ +#define _SYNTH_LOCNTSTATUS_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTSTATUS */ +#define _SYNTH_LOCNTSTATUS_MASK 0x000FFFFFUL /**< Mask for SYNTH_LOCNTSTATUS */ +#define _SYNTH_LOCNTSTATUS_LOCOUNT_SHIFT 0 /**< Shift value for SYNTH_LOCOUNT */ +#define _SYNTH_LOCNTSTATUS_LOCOUNT_MASK 0x7FFFFUL /**< Bit mask for SYNTH_LOCOUNT */ +#define _SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTSTATUS */ +#define SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT (_SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTSTATUS */ +#define SYNTH_LOCNTSTATUS_BUSY (0x1UL << 19) /**< LO Counter is Busy */ +#define _SYNTH_LOCNTSTATUS_BUSY_SHIFT 19 /**< Shift value for SYNTH_BUSY */ +#define _SYNTH_LOCNTSTATUS_BUSY_MASK 0x80000UL /**< Bit mask for SYNTH_BUSY */ +#define _SYNTH_LOCNTSTATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTSTATUS */ +#define SYNTH_LOCNTSTATUS_BUSY_DEFAULT (_SYNTH_LOCNTSTATUS_BUSY_DEFAULT << 19) /**< Shifted mode DEFAULT for SYNTH_LOCNTSTATUS */ + +/* Bit fields for SYNTH LOCNTTARGET */ +#define _SYNTH_LOCNTTARGET_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTTARGET */ +#define _SYNTH_LOCNTTARGET_MASK 0x0007FFFFUL /**< Mask for SYNTH_LOCNTTARGET */ +#define _SYNTH_LOCNTTARGET_TARGET_SHIFT 0 /**< Shift value for SYNTH_TARGET */ +#define _SYNTH_LOCNTTARGET_TARGET_MASK 0x7FFFFUL /**< Bit mask for SYNTH_TARGET */ +#define _SYNTH_LOCNTTARGET_TARGET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTTARGET */ +#define SYNTH_LOCNTTARGET_TARGET_DEFAULT (_SYNTH_LOCNTTARGET_TARGET_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTTARGET */ + +/* Bit fields for SYNTH MMDDENOMINIT */ +#define _SYNTH_MMDDENOMINIT_RESETVALUE 0x00000000UL /**< Default value for SYNTH_MMDDENOMINIT */ +#define _SYNTH_MMDDENOMINIT_MASK 0x07FFFFFFUL /**< Mask for SYNTH_MMDDENOMINIT */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT0_SHIFT 0 /**< Shift value for SYNTH_DENOMINIT0 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT0_MASK 0x1FFUL /**< Bit mask for SYNTH_DENOMINIT0 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */ +#define SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT1_SHIFT 9 /**< Shift value for SYNTH_DENOMINIT1 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT1_MASK 0x3FE00UL /**< Bit mask for SYNTH_DENOMINIT1 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */ +#define SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT2_SHIFT 18 /**< Shift value for SYNTH_DENOMINIT2 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT2_MASK 0x7FC0000UL /**< Bit mask for SYNTH_DENOMINIT2 */ +#define _SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */ +#define SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT << 18) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */ + +/* Bit fields for SYNTH CHPDACINIT */ +#define _SYNTH_CHPDACINIT_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHPDACINIT */ +#define _SYNTH_CHPDACINIT_MASK 0x00000FFFUL /**< Mask for SYNTH_CHPDACINIT */ +#define _SYNTH_CHPDACINIT_DACINIT_SHIFT 0 /**< Shift value for SYNTH_DACINIT */ +#define _SYNTH_CHPDACINIT_DACINIT_MASK 0xFFFUL /**< Bit mask for SYNTH_DACINIT */ +#define _SYNTH_CHPDACINIT_DACINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHPDACINIT */ +#define SYNTH_CHPDACINIT_DACINIT_DEFAULT (_SYNTH_CHPDACINIT_DACINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHPDACINIT */ + +/* Bit fields for SYNTH LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_SHIFT 0 /**< Shift value for SYNTH_OP1BWCAL */ +#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWCAL */ +#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_SHIFT 4 /**< Shift value for SYNTH_OP1COMPCAL */ +#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPCAL */ +#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_SHIFT 8 /**< Shift value for SYNTH_RFBVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_RPVALCAL_SHIFT 11 /**< Shift value for SYNTH_RPVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RPVALCAL_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define _SYNTH_LPFCTRL1CAL_RZVALCAL_SHIFT 14 /**< Shift value for SYNTH_RZVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RZVALCAL_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALCAL */ +#define _SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */ +#define SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */ + +/* Bit fields for SYNTH LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_OP1BWRX_SHIFT 0 /**< Shift value for SYNTH_OP1BWRX */ +#define _SYNTH_LPFCTRL1RX_OP1BWRX_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWRX */ +#define _SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT (_SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_OP1COMPRX_SHIFT 4 /**< Shift value for SYNTH_OP1COMPRX */ +#define _SYNTH_LPFCTRL1RX_OP1COMPRX_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPRX */ +#define _SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT (_SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_RFBVALRX_SHIFT 8 /**< Shift value for SYNTH_RFBVALRX */ +#define _SYNTH_LPFCTRL1RX_RFBVALRX_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALRX */ +#define _SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_RPVALRX_SHIFT 11 /**< Shift value for SYNTH_RPVALRX */ +#define _SYNTH_LPFCTRL1RX_RPVALRX_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALRX */ +#define _SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define _SYNTH_LPFCTRL1RX_RZVALRX_SHIFT 14 /**< Shift value for SYNTH_RZVALRX */ +#define _SYNTH_LPFCTRL1RX_RZVALRX_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALRX */ +#define _SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */ +#define SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */ + +/* Bit fields for SYNTH LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_OP1BWTX_SHIFT 0 /**< Shift value for SYNTH_OP1BWTX */ +#define _SYNTH_LPFCTRL1TX_OP1BWTX_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWTX */ +#define _SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT (_SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_OP1COMPTX_SHIFT 4 /**< Shift value for SYNTH_OP1COMPTX */ +#define _SYNTH_LPFCTRL1TX_OP1COMPTX_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPTX */ +#define _SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT (_SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_RFBVALTX_SHIFT 8 /**< Shift value for SYNTH_RFBVALTX */ +#define _SYNTH_LPFCTRL1TX_RFBVALTX_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALTX */ +#define _SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_RPVALTX_SHIFT 11 /**< Shift value for SYNTH_RPVALTX */ +#define _SYNTH_LPFCTRL1TX_RPVALTX_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALTX */ +#define _SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define _SYNTH_LPFCTRL1TX_RZVALTX_SHIFT 14 /**< Shift value for SYNTH_RZVALTX */ +#define _SYNTH_LPFCTRL1TX_RZVALTX_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALTX */ +#define _SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */ +#define SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */ + +/* Bit fields for SYNTH LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_MASK 0x1FFFFFFFUL /**< Mask for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFSWENRX (0x1UL << 0) /**< LPF Switching Enable in RX Mode */ +#define _SYNTH_LPFCTRL2RX_LPFSWENRX_SHIFT 0 /**< Shift value for SYNTH_LPFSWENRX */ +#define _SYNTH_LPFCTRL2RX_LPFSWENRX_MASK 0x1UL /**< Bit mask for SYNTH_LPFSWENRX */ +#define _SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE (_SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE << 0) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE (_SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE << 0) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_SHIFT 1 /**< Shift value for SYNTH_LPFINCAPRX */ +#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_MASK 0x6UL /**< Bit mask for SYNTH_LPFINCAPRX */ +#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX (0x1UL << 3) /**< LPF Gnd Switch Enable in RX Mode */ +#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_SHIFT 3 /**< Shift value for SYNTH_LPFGNDSWENRX */ +#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_MASK 0x8UL /**< Bit mask for SYNTH_LPFGNDSWENRX */ +#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE << 3) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE << 3) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CALCRX_SHIFT 4 /**< Shift value for SYNTH_CALCRX */ +#define _SYNTH_LPFCTRL2RX_CALCRX_MASK 0x1F0UL /**< Bit mask for SYNTH_CALCRX */ +#define _SYNTH_LPFCTRL2RX_CALCRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CALCRX_DEFAULT (_SYNTH_LPFCTRL2RX_CALCRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CASELRX (0x1UL << 9) /**< LPF Ca Select in RX Mode */ +#define _SYNTH_LPFCTRL2RX_CASELRX_SHIFT 9 /**< Shift value for SYNTH_CASELRX */ +#define _SYNTH_LPFCTRL2RX_CASELRX_MASK 0x200UL /**< Bit mask for SYNTH_CASELRX */ +#define _SYNTH_LPFCTRL2RX_CASELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CASELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CASELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CASELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CASELRX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CASELRX_DISABLE (_SYNTH_LPFCTRL2RX_CASELRX_DISABLE << 9) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CASELRX_ENABLE (_SYNTH_LPFCTRL2RX_CASELRX_ENABLE << 9) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CAVALRX_SHIFT 10 /**< Shift value for SYNTH_CAVALRX */ +#define _SYNTH_LPFCTRL2RX_CAVALRX_MASK 0x7C00UL /**< Bit mask for SYNTH_CAVALRX */ +#define _SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT (_SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CFBSELRX (0x1UL << 15) /**< LPF Cfb Select in RX Mode */ +#define _SYNTH_LPFCTRL2RX_CFBSELRX_SHIFT 15 /**< Shift value for SYNTH_CFBSELRX */ +#define _SYNTH_LPFCTRL2RX_CFBSELRX_MASK 0x8000UL /**< Bit mask for SYNTH_CFBSELRX */ +#define _SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT << 15) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE (_SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE << 15) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE (_SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE << 15) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CZSELRX (0x1UL << 16) /**< LPF Cz Select in RX Mode */ +#define _SYNTH_LPFCTRL2RX_CZSELRX_SHIFT 16 /**< Shift value for SYNTH_CZSELRX */ +#define _SYNTH_LPFCTRL2RX_CZSELRX_MASK 0x10000UL /**< Bit mask for SYNTH_CZSELRX */ +#define _SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CZSELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CZSELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CZSELRX_DISABLE (_SYNTH_LPFCTRL2RX_CZSELRX_DISABLE << 16) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CZSELRX_ENABLE (_SYNTH_LPFCTRL2RX_CZSELRX_ENABLE << 16) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_CZVALRX_SHIFT 17 /**< Shift value for SYNTH_CZVALRX */ +#define _SYNTH_LPFCTRL2RX_CZVALRX_MASK 0x1FE0000UL /**< Bit mask for SYNTH_CZVALRX */ +#define _SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT (_SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT << 17) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_MODESELRX (0x1UL << 25) /**< LPF Filter Mode Select in RX Mode */ +#define _SYNTH_LPFCTRL2RX_MODESELRX_SHIFT 25 /**< Shift value for SYNTH_MODESELRX */ +#define _SYNTH_LPFCTRL2RX_MODESELRX_MASK 0x2000000UL /**< Bit mask for SYNTH_MODESELRX */ +#define _SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_MODESELRX_ONEOP 0x00000000UL /**< Mode ONEOP for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_MODESELRX_TWOOP 0x00000001UL /**< Mode TWOOP for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT (_SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_MODESELRX_ONEOP (_SYNTH_LPFCTRL2RX_MODESELRX_ONEOP << 25) /**< Shifted mode ONEOP for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_MODESELRX_TWOOP (_SYNTH_LPFCTRL2RX_MODESELRX_TWOOP << 25) /**< Shifted mode TWOOP for SYNTH_LPFCTRL2RX */ +#define _SYNTH_LPFCTRL2RX_VCMLVLRX_SHIFT 26 /**< Shift value for SYNTH_VCMLVLRX */ +#define _SYNTH_LPFCTRL2RX_VCMLVLRX_MASK 0x1C000000UL /**< Bit mask for SYNTH_VCMLVLRX */ +#define _SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */ +#define SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT (_SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */ + +/* Bit fields for SYNTH LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_MASK 0x1FFFFFFFUL /**< Mask for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFSWENTX (0x1UL << 0) /**< LPF Switching Enable in TX Mode */ +#define _SYNTH_LPFCTRL2TX_LPFSWENTX_SHIFT 0 /**< Shift value for SYNTH_LPFSWENTX */ +#define _SYNTH_LPFCTRL2TX_LPFSWENTX_MASK 0x1UL /**< Bit mask for SYNTH_LPFSWENTX */ +#define _SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE (_SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE << 0) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE (_SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE << 0) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_SHIFT 1 /**< Shift value for SYNTH_LPFINCAPTX */ +#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_MASK 0x6UL /**< Bit mask for SYNTH_LPFINCAPTX */ +#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX (0x1UL << 3) /**< LPF Gnd Switch Enable in TX Mode */ +#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_SHIFT 3 /**< Shift value for SYNTH_LPFGNDSWENTX */ +#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_MASK 0x8UL /**< Bit mask for SYNTH_LPFGNDSWENTX */ +#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE << 3) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE << 3) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CALCTX_SHIFT 4 /**< Shift value for SYNTH_CALCTX */ +#define _SYNTH_LPFCTRL2TX_CALCTX_MASK 0x1F0UL /**< Bit mask for SYNTH_CALCTX */ +#define _SYNTH_LPFCTRL2TX_CALCTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CALCTX_DEFAULT (_SYNTH_LPFCTRL2TX_CALCTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CASELTX (0x1UL << 9) /**< LPF Ca Select in TX Mode */ +#define _SYNTH_LPFCTRL2TX_CASELTX_SHIFT 9 /**< Shift value for SYNTH_CASELTX */ +#define _SYNTH_LPFCTRL2TX_CASELTX_MASK 0x200UL /**< Bit mask for SYNTH_CASELTX */ +#define _SYNTH_LPFCTRL2TX_CASELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CASELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CASELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CASELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CASELTX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CASELTX_DISABLE (_SYNTH_LPFCTRL2TX_CASELTX_DISABLE << 9) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CASELTX_ENABLE (_SYNTH_LPFCTRL2TX_CASELTX_ENABLE << 9) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CAVALTX_SHIFT 10 /**< Shift value for SYNTH_CAVALTX */ +#define _SYNTH_LPFCTRL2TX_CAVALTX_MASK 0x7C00UL /**< Bit mask for SYNTH_CAVALTX */ +#define _SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT (_SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CFBSELTX (0x1UL << 15) /**< LPF Cfb Select in TX Mode */ +#define _SYNTH_LPFCTRL2TX_CFBSELTX_SHIFT 15 /**< Shift value for SYNTH_CFBSELTX */ +#define _SYNTH_LPFCTRL2TX_CFBSELTX_MASK 0x8000UL /**< Bit mask for SYNTH_CFBSELTX */ +#define _SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT << 15) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE (_SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE << 15) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE (_SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE << 15) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CZSELTX (0x1UL << 16) /**< LPF Cz Select in TX Mode */ +#define _SYNTH_LPFCTRL2TX_CZSELTX_SHIFT 16 /**< Shift value for SYNTH_CZSELTX */ +#define _SYNTH_LPFCTRL2TX_CZSELTX_MASK 0x10000UL /**< Bit mask for SYNTH_CZSELTX */ +#define _SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CZSELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CZSELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CZSELTX_DISABLE (_SYNTH_LPFCTRL2TX_CZSELTX_DISABLE << 16) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CZSELTX_ENABLE (_SYNTH_LPFCTRL2TX_CZSELTX_ENABLE << 16) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_CZVALTX_SHIFT 17 /**< Shift value for SYNTH_CZVALTX */ +#define _SYNTH_LPFCTRL2TX_CZVALTX_MASK 0x1FE0000UL /**< Bit mask for SYNTH_CZVALTX */ +#define _SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT (_SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT << 17) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_MODESELTX (0x1UL << 25) /**< LPF Filter Mode Select in TX Mode */ +#define _SYNTH_LPFCTRL2TX_MODESELTX_SHIFT 25 /**< Shift value for SYNTH_MODESELTX */ +#define _SYNTH_LPFCTRL2TX_MODESELTX_MASK 0x2000000UL /**< Bit mask for SYNTH_MODESELTX */ +#define _SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_MODESELTX_ONEOP 0x00000000UL /**< Mode ONEOP for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_MODESELTX_TWOOP 0x00000001UL /**< Mode TWOOP for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT (_SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_MODESELTX_ONEOP (_SYNTH_LPFCTRL2TX_MODESELTX_ONEOP << 25) /**< Shifted mode ONEOP for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_MODESELTX_TWOOP (_SYNTH_LPFCTRL2TX_MODESELTX_TWOOP << 25) /**< Shifted mode TWOOP for SYNTH_LPFCTRL2TX */ +#define _SYNTH_LPFCTRL2TX_VCMLVLTX_SHIFT 26 /**< Shift value for SYNTH_VCMLVLTX */ +#define _SYNTH_LPFCTRL2TX_VCMLVLTX_MASK 0x1C000000UL /**< Bit mask for SYNTH_VCMLVLTX */ +#define _SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */ +#define SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT (_SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */ + +/* Bit fields for SYNTH DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_RESETVALUE 0x00000013UL /**< Default value for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_MASK 0x070003FFUL /**< Mask for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DITHERDSMINPUTRX (0x1UL << 0) /**< Dithering of DSM input for RX mode */ +#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_SHIFT 0 /**< Shift value for SYNTH_DITHERDSMINPUTRX */ +#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_MASK 0x1UL /**< Bit mask for SYNTH_DITHERDSMINPUTRX */ +#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_SHIFT 1 /**< Shift value for SYNTH_DITHERDSMOUTPUTRX */ +#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_MASK 0xEUL /**< Bit mask for SYNTH_DITHERDSMOUTPUTRX */ +#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DITHERDACRX_SHIFT 4 /**< Shift value for SYNTH_DITHERDACRX */ +#define _SYNTH_DSMCTRLRX_DITHERDACRX_MASK 0xF0UL /**< Bit mask for SYNTH_DITHERDACRX */ +#define _SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DSMMODERX (0x1UL << 8) /**< Delta-sigma topology for RX mode */ +#define _SYNTH_DSMCTRLRX_DSMMODERX_SHIFT 8 /**< Shift value for SYNTH_DSMMODERX */ +#define _SYNTH_DSMCTRLRX_DSMMODERX_MASK 0x100UL /**< Bit mask for SYNTH_DSMMODERX */ +#define _SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD 0x00000000UL /**< Mode FEEDFORWARD for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DSMMODERX_MASH 0x00000001UL /**< Mode MASH for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT (_SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD (_SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD << 8) /**< Shifted mode FEEDFORWARD for SYNTH_DSMCTRLRX*/ +#define SYNTH_DSMCTRLRX_DSMMODERX_MASH (_SYNTH_DSMCTRLRX_DSMMODERX_MASH << 8) /**< Shifted mode MASH for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_LSBFORCERX (0x1UL << 9) /**< Delta-sigma input force LSB for RX mode */ +#define _SYNTH_DSMCTRLRX_LSBFORCERX_SHIFT 9 /**< Shift value for SYNTH_LSBFORCERX */ +#define _SYNTH_DSMCTRLRX_LSBFORCERX_MASK 0x200UL /**< Bit mask for SYNTH_LSBFORCERX */ +#define _SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT (_SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DEMMODERX (0x1UL << 24) /**< DEM Mode for RX mode */ +#define _SYNTH_DSMCTRLRX_DEMMODERX_SHIFT 24 /**< Shift value for SYNTH_DEMMODERX */ +#define _SYNTH_DSMCTRLRX_DEMMODERX_MASK 0x1000000UL /**< Bit mask for SYNTH_DEMMODERX */ +#define _SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DEMMODERX_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_DEMMODERX_ENABLED 0x00000001UL /**< Mode ENABLED for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT (_SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DEMMODERX_DISABLED (_SYNTH_DSMCTRLRX_DEMMODERX_DISABLED << 24) /**< Shifted mode DISABLED for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_DEMMODERX_ENABLED (_SYNTH_DSMCTRLRX_DEMMODERX_ENABLED << 24) /**< Shifted mode ENABLED for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_MASHORDERRX (0x1UL << 25) /**< MASH order for RX mode */ +#define _SYNTH_DSMCTRLRX_MASHORDERRX_SHIFT 25 /**< Shift value for SYNTH_MASHORDERRX */ +#define _SYNTH_DSMCTRLRX_MASHORDERRX_MASK 0x2000000UL /**< Bit mask for SYNTH_MASHORDERRX */ +#define _SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_MASHORDERRX_SECOND 0x00000000UL /**< Mode SECOND for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_MASHORDERRX_THIRD 0x00000001UL /**< Mode THIRD for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT (_SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_MASHORDERRX_SECOND (_SYNTH_DSMCTRLRX_MASHORDERRX_SECOND << 25) /**< Shifted mode SECOND for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_MASHORDERRX_THIRD (_SYNTH_DSMCTRLRX_MASHORDERRX_THIRD << 25) /**< Shifted mode THIRD for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_REQORDERRX (0x1UL << 26) /**< ReQuant order for RX mode */ +#define _SYNTH_DSMCTRLRX_REQORDERRX_SHIFT 26 /**< Shift value for SYNTH_REQORDERRX */ +#define _SYNTH_DSMCTRLRX_REQORDERRX_MASK 0x4000000UL /**< Bit mask for SYNTH_REQORDERRX */ +#define _SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_REQORDERRX_FIRST 0x00000000UL /**< Mode FIRST for SYNTH_DSMCTRLRX */ +#define _SYNTH_DSMCTRLRX_REQORDERRX_SECOND 0x00000001UL /**< Mode SECOND for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT (_SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_REQORDERRX_FIRST (_SYNTH_DSMCTRLRX_REQORDERRX_FIRST << 26) /**< Shifted mode FIRST for SYNTH_DSMCTRLRX */ +#define SYNTH_DSMCTRLRX_REQORDERRX_SECOND (_SYNTH_DSMCTRLRX_REQORDERRX_SECOND << 26) /**< Shifted mode SECOND for SYNTH_DSMCTRLRX */ + +/* Bit fields for SYNTH DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_RESETVALUE 0x00000013UL /**< Default value for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_MASK 0x070003FFUL /**< Mask for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DITHERDSMINPUTTX (0x1UL << 0) /**< Dithering of DSM input for TX mode */ +#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_SHIFT 0 /**< Shift value for SYNTH_DITHERDSMINPUTTX */ +#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_MASK 0x1UL /**< Bit mask for SYNTH_DITHERDSMINPUTTX */ +#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_SHIFT 1 /**< Shift value for SYNTH_DITHERDSMOUTPUTTX */ +#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_MASK 0xEUL /**< Bit mask for SYNTH_DITHERDSMOUTPUTTX */ +#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DITHERDACTX_SHIFT 4 /**< Shift value for SYNTH_DITHERDACTX */ +#define _SYNTH_DSMCTRLTX_DITHERDACTX_MASK 0xF0UL /**< Bit mask for SYNTH_DITHERDACTX */ +#define _SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DSMMODETX (0x1UL << 8) /**< Delta-sigma topology for TX mode */ +#define _SYNTH_DSMCTRLTX_DSMMODETX_SHIFT 8 /**< Shift value for SYNTH_DSMMODETX */ +#define _SYNTH_DSMCTRLTX_DSMMODETX_MASK 0x100UL /**< Bit mask for SYNTH_DSMMODETX */ +#define _SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD 0x00000000UL /**< Mode FEEDFORWARD for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DSMMODETX_MASH 0x00000001UL /**< Mode MASH for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT (_SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD (_SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD << 8) /**< Shifted mode FEEDFORWARD for SYNTH_DSMCTRLTX*/ +#define SYNTH_DSMCTRLTX_DSMMODETX_MASH (_SYNTH_DSMCTRLTX_DSMMODETX_MASH << 8) /**< Shifted mode MASH for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_LSBFORCETX (0x1UL << 9) /**< Delta-sigma input force LSB for TX mode */ +#define _SYNTH_DSMCTRLTX_LSBFORCETX_SHIFT 9 /**< Shift value for SYNTH_LSBFORCETX */ +#define _SYNTH_DSMCTRLTX_LSBFORCETX_MASK 0x200UL /**< Bit mask for SYNTH_LSBFORCETX */ +#define _SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT (_SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DEMMODETX (0x1UL << 24) /**< DEM Mode for TX mode */ +#define _SYNTH_DSMCTRLTX_DEMMODETX_SHIFT 24 /**< Shift value for SYNTH_DEMMODETX */ +#define _SYNTH_DSMCTRLTX_DEMMODETX_MASK 0x1000000UL /**< Bit mask for SYNTH_DEMMODETX */ +#define _SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DEMMODETX_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_DEMMODETX_ENABLED 0x00000001UL /**< Mode ENABLED for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT (_SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DEMMODETX_DISABLED (_SYNTH_DSMCTRLTX_DEMMODETX_DISABLED << 24) /**< Shifted mode DISABLED for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_DEMMODETX_ENABLED (_SYNTH_DSMCTRLTX_DEMMODETX_ENABLED << 24) /**< Shifted mode ENABLED for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_MASHORDERTX (0x1UL << 25) /**< MASH order for TX mode */ +#define _SYNTH_DSMCTRLTX_MASHORDERTX_SHIFT 25 /**< Shift value for SYNTH_MASHORDERTX */ +#define _SYNTH_DSMCTRLTX_MASHORDERTX_MASK 0x2000000UL /**< Bit mask for SYNTH_MASHORDERTX */ +#define _SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_MASHORDERTX_SECOND 0x00000000UL /**< Mode SECOND for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_MASHORDERTX_THIRD 0x00000001UL /**< Mode THIRD for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT (_SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_MASHORDERTX_SECOND (_SYNTH_DSMCTRLTX_MASHORDERTX_SECOND << 25) /**< Shifted mode SECOND for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_MASHORDERTX_THIRD (_SYNTH_DSMCTRLTX_MASHORDERTX_THIRD << 25) /**< Shifted mode THIRD for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_REQORDERTX (0x1UL << 26) /**< ReQuant order for TX mode */ +#define _SYNTH_DSMCTRLTX_REQORDERTX_SHIFT 26 /**< Shift value for SYNTH_REQORDERTX */ +#define _SYNTH_DSMCTRLTX_REQORDERTX_MASK 0x4000000UL /**< Bit mask for SYNTH_REQORDERTX */ +#define _SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_REQORDERTX_FIRST 0x00000000UL /**< Mode FIRST for SYNTH_DSMCTRLTX */ +#define _SYNTH_DSMCTRLTX_REQORDERTX_SECOND 0x00000001UL /**< Mode SECOND for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT (_SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_REQORDERTX_FIRST (_SYNTH_DSMCTRLTX_REQORDERTX_FIRST << 26) /**< Shifted mode FIRST for SYNTH_DSMCTRLTX */ +#define SYNTH_DSMCTRLTX_REQORDERTX_SECOND (_SYNTH_DSMCTRLTX_REQORDERTX_SECOND << 26) /**< Shifted mode SECOND for SYNTH_DSMCTRLTX */ + +/* Bit fields for SYNTH SEQIF */ +#define _SYNTH_SEQIF_RESETVALUE 0x00000000UL /**< Default value for SYNTH_SEQIF */ +#define _SYNTH_SEQIF_MASK 0x00000237UL /**< Mask for SYNTH_SEQIF */ +#define SYNTH_SEQIF_LOCKED (0x1UL << 0) /**< Synthesizer locked Interrupt Flag */ +#define _SYNTH_SEQIF_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */ +#define _SYNTH_SEQIF_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */ +#define _SYNTH_SEQIF_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_LOCKED_DEFAULT (_SYNTH_SEQIF_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_UNLOCKED (0x1UL << 1) /**< Synthesizer unlocked Interrupt Flag */ +#define _SYNTH_SEQIF_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */ +#define _SYNTH_SEQIF_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */ +#define _SYNTH_SEQIF_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_UNLOCKED_DEFAULT (_SYNTH_SEQIF_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_SYRDY (0x1UL << 2) /**< Synthesizer ready Interrupt Flag */ +#define _SYNTH_SEQIF_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */ +#define _SYNTH_SEQIF_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */ +#define _SYNTH_SEQIF_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_SYRDY_DEFAULT (_SYNTH_SEQIF_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_VCOHIGH (0x1UL << 4) /**< VCO high voltage Interrupt Flag */ +#define _SYNTH_SEQIF_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */ +#define _SYNTH_SEQIF_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */ +#define _SYNTH_SEQIF_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_VCOHIGH_DEFAULT (_SYNTH_SEQIF_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_VCOLOW (0x1UL << 5) /**< VCO low voltage Interrupt Flag */ +#define _SYNTH_SEQIF_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */ +#define _SYNTH_SEQIF_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */ +#define _SYNTH_SEQIF_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_VCOLOW_DEFAULT (_SYNTH_SEQIF_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_LOCNTDONE (0x1UL << 9) /**< LOCNT measurement done Interrupt Flag */ +#define _SYNTH_SEQIF_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */ +#define _SYNTH_SEQIF_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */ +#define _SYNTH_SEQIF_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */ +#define SYNTH_SEQIF_LOCNTDONE_DEFAULT (_SYNTH_SEQIF_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_SEQIF */ + +/* Bit fields for SYNTH SEQIEN */ +#define _SYNTH_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_SEQIEN */ +#define _SYNTH_SEQIEN_MASK 0x00000237UL /**< Mask for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_LOCKED (0x1UL << 0) /**< LOCKED Interrupt Enable */ +#define _SYNTH_SEQIEN_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */ +#define _SYNTH_SEQIEN_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */ +#define _SYNTH_SEQIEN_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_LOCKED_DEFAULT (_SYNTH_SEQIEN_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_UNLOCKED (0x1UL << 1) /**< UNLOCKED Interrupt Enable */ +#define _SYNTH_SEQIEN_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */ +#define _SYNTH_SEQIEN_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */ +#define _SYNTH_SEQIEN_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_UNLOCKED_DEFAULT (_SYNTH_SEQIEN_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_SYRDY (0x1UL << 2) /**< CAPCALDONE Interrupt Enable */ +#define _SYNTH_SEQIEN_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */ +#define _SYNTH_SEQIEN_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */ +#define _SYNTH_SEQIEN_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_SYRDY_DEFAULT (_SYNTH_SEQIEN_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_VCOHIGH (0x1UL << 4) /**< VCOHIGH Interrupt Enable */ +#define _SYNTH_SEQIEN_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */ +#define _SYNTH_SEQIEN_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */ +#define _SYNTH_SEQIEN_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_VCOHIGH_DEFAULT (_SYNTH_SEQIEN_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_VCOLOW (0x1UL << 5) /**< VCOLOW Interrupt Enable */ +#define _SYNTH_SEQIEN_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */ +#define _SYNTH_SEQIEN_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */ +#define _SYNTH_SEQIEN_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_VCOLOW_DEFAULT (_SYNTH_SEQIEN_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_LOCNTDONE (0x1UL << 9) /**< LOCNTDONE Interrupt Enable */ +#define _SYNTH_SEQIEN_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */ +#define _SYNTH_SEQIEN_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */ +#define _SYNTH_SEQIEN_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */ +#define SYNTH_SEQIEN_LOCNTDONE_DEFAULT (_SYNTH_SEQIEN_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */ + +/** @} End of group EFR32MG24_SYNTH_BitFields */ +/** @} End of group EFR32MG24_SYNTH */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SYNTH_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_syscfg.h b/EFR32MG24/Device/Include/efr32mg24_syscfg.h new file mode 100644 index 0000000..5d2cc86 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_syscfg.h @@ -0,0 +1,772 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SYSCFG_H +#define EFR32MG24_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSCFG SYSCFG + * @{ + * @brief EFR32MG24 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED7[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED8[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED11[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[635U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED17[54U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED21[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED22[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED25[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[635U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED31[54U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED35[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED36[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED39[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[635U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED45[54U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED49[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED50[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED53[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group EFR32MG24_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSCFG + * @{ + * @defgroup EFR32MG24_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000C01UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000030UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group EFR32MG24_SYSCFG_BitFields */ +/** @} End of group EFR32MG24_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32MG24 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32MG24_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSCFG_CFGNS + * @{ + * @defgroup EFR32MG24_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32MG24_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32MG24_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SYSCFG_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_sysrtc.h b/EFR32MG24/Device/Include/efr32mg24_sysrtc.h new file mode 100644 index 0000000..797abf8 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_sysrtc.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 SYSRTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SYSRTC_H +#define EFR32MG24_SYSRTC_H +#define SYSRTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSRTC SYSRTC + * @{ + * @brief EFR32MG24 SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} SYSRTC_TypeDef; +/** @} End of group EFR32MG24_SYSRTC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSRTC + * @{ + * @defgroup EFR32MG24_SYSRTC_BitFields SYSRTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSRTC IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ + +/* Bit fields for SYSRTC EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ + +/* Bit fields for SYSRTC SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ + +/* Bit fields for SYSRTC CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ + +/* Bit fields for SYSRTC CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ + +/* Bit fields for SYSRTC STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ + +/* Bit fields for SYSRTC CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ + +/* Bit fields for SYSRTC SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ + +/* Bit fields for SYSRTC LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ + +/* Bit fields for SYSRTC GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ + +/* Bit fields for SYSRTC GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ + +/* Bit fields for SYSRTC GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ + +/* Bit fields for SYSRTC GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ + +/* Bit fields for SYSRTC GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ + +/** @} End of group EFR32MG24_SYSRTC_BitFields */ +/** @} End of group EFR32MG24_SYSRTC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_SYSRTC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_timer.h b/EFR32MG24/Device/Include/efr32mg24_timer.h new file mode 100644 index 0000000..1a1974a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_timer.h @@ -0,0 +1,1020 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_TIMER_H +#define EFR32MG24_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_TIMER TIMER + * @{ + * @brief EFR32MG24 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32MG24_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_TIMER + * @{ + * @defgroup EFR32MG24_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32MG24_TIMER_BitFields */ +/** @} End of group EFR32MG24_TIMER */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_TIMER_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_ulfrco.h b/EFR32MG24/Device/Include/efr32mg24_ulfrco.h new file mode 100644 index 0000000..f621de4 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_ulfrco.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ULFRCO_H +#define EFR32MG24_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ULFRCO ULFRCO + * @{ + * @brief EFR32MG24 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32MG24_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ULFRCO + * @{ + * @defgroup EFR32MG24_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32MG24_ULFRCO_BitFields */ +/** @} End of group EFR32MG24_ULFRCO */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_ULFRCO_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_usart.h b/EFR32MG24/Device/Include/efr32mg24_usart.h new file mode 100644 index 0000000..2d086ab --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_usart.h @@ -0,0 +1,1431 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_USART_H +#define EFR32MG24_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_USART USART + * @{ + * @brief EFR32MG24 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32MG24_USART */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_USART + * @{ + * @defgroup EFR32MG24_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32MG24_USART_BitFields */ +/** @} End of group EFR32MG24_USART */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_USART_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_vdac.h b/EFR32MG24/Device/Include/efr32mg24_vdac.h new file mode 100644 index 0000000..f8b8537 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_vdac.h @@ -0,0 +1,757 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 VDAC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_VDAC_H +#define EFR32MG24_VDAC_H +#define VDAC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_VDAC VDAC + * @{ + * @brief EFR32MG24 VDAC Register Declaration. + *****************************************************************************/ + +/** VDAC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ +} VDAC_TypeDef; +/** @} End of group EFR32MG24_VDAC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_VDAC + * @{ + * @defgroup EFR32MG24_VDAC_BitFields VDAC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ + +/* Bit fields for VDAC EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ + +/* Bit fields for VDAC SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ + +/* Bit fields for VDAC CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ + +/* Bit fields for VDAC CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ + +/* Bit fields for VDAC CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ + +/* Bit fields for VDAC OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ + +/* Bit fields for VDAC OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ + +/** @} End of group EFR32MG24_VDAC_BitFields */ +/** @} End of group EFR32MG24_VDAC */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_VDAC_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24_wdog.h b/EFR32MG24/Device/Include/efr32mg24_wdog.h new file mode 100644 index 0000000..60f9144 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24_wdog.h @@ -0,0 +1,375 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG24 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_WDOG_H +#define EFR32MG24_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_WDOG WDOG + * @{ + * @brief EFR32MG24 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32MG24_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_WDOG + * @{ + * @defgroup EFR32MG24_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32MG24_WDOG_BitFields */ +/** @} End of group EFR32MG24_WDOG */ +/** @} End of group Parts */ + +#endif /* EFR32MG24_WDOG_H */ diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1024im40.h b/EFR32MG24/Device/Include/efr32mg24a010f1024im40.h new file mode 100644 index 0000000..146589b --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1024im40.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1024IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1024IM40_H +#define EFR32MG24A010F1024IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40 EFR32MG24A010F1024IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40_Core EFR32MG24A010F1024IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1024IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1024IM40_Part EFR32MG24A010F1024IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1024IM40) +#define EFR32MG24A010F1024IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1024IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1024IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1024IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40_Peripheral_TypeDefs EFR32MG24A010F1024IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1024IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40_Peripheral_Base EFR32MG24A010F1024IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40_Peripheral_Declaration EFR32MG24A010F1024IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM40_Peripheral_Parameters EFR32MG24A010F1024IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1024IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1024im48.h b/EFR32MG24/Device/Include/efr32mg24a010f1024im48.h new file mode 100644 index 0000000..54cdafd --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1024im48.h @@ -0,0 +1,1521 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1024IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1024IM48_H +#define EFR32MG24A010F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48 EFR32MG24A010F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48_Core EFR32MG24A010F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1024IM48_Part EFR32MG24A010F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1024IM48) +#define EFR32MG24A010F1024IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1024IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1024IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48_Peripheral_TypeDefs EFR32MG24A010F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48_Peripheral_Base EFR32MG24A010F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48_Peripheral_Declaration EFR32MG24A010F1024IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1024IM48_Peripheral_Parameters EFR32MG24A010F1024IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1024IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1536gm40.h b/EFR32MG24/Device/Include/efr32mg24a010f1536gm40.h new file mode 100644 index 0000000..cb7ad67 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1536gm40.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1536GM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1536GM40_H +#define EFR32MG24A010F1536GM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40 EFR32MG24A010F1536GM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40_Core EFR32MG24A010F1536GM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1536GM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1536GM40_Part EFR32MG24A010F1536GM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1536GM40) +#define EFR32MG24A010F1536GM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1536GM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1536GM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1536GM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40_Peripheral_TypeDefs EFR32MG24A010F1536GM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1536GM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40_Peripheral_Base EFR32MG24A010F1536GM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40_Peripheral_Declaration EFR32MG24A010F1536GM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM40_Peripheral_Parameters EFR32MG24A010F1536GM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1536GM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a010f1536gm48.h new file mode 100644 index 0000000..8dea3b3 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1536gm48.h @@ -0,0 +1,1521 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1536GM48_H +#define EFR32MG24A010F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48 EFR32MG24A010F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48_Core EFR32MG24A010F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1536GM48_Part EFR32MG24A010F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1536GM48) +#define EFR32MG24A010F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48_Peripheral_TypeDefs EFR32MG24A010F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48_Peripheral_Base EFR32MG24A010F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48_Peripheral_Declaration EFR32MG24A010F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536GM48_Peripheral_Parameters EFR32MG24A010F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a010f1536im40.h new file mode 100644 index 0000000..6faa214 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1536im40.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1536IM40_H +#define EFR32MG24A010F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40 EFR32MG24A010F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40_Core EFR32MG24A010F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1536IM40_Part EFR32MG24A010F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1536IM40) +#define EFR32MG24A010F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40_Peripheral_TypeDefs EFR32MG24A010F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40_Peripheral_Base EFR32MG24A010F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40_Peripheral_Declaration EFR32MG24A010F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM40_Peripheral_Parameters EFR32MG24A010F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a010f1536im48.h b/EFR32MG24/Device/Include/efr32mg24a010f1536im48.h new file mode 100644 index 0000000..8f61fea --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a010f1536im48.h @@ -0,0 +1,1521 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A010F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A010F1536IM48_H +#define EFR32MG24A010F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48 EFR32MG24A010F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48_Core EFR32MG24A010F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A010F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A010F1536IM48_Part EFR32MG24A010F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A010F1536IM48) +#define EFR32MG24A010F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A010F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A010F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A010F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48_Peripheral_TypeDefs EFR32MG24A010F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A010F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48_Peripheral_Base EFR32MG24A010F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48_Peripheral_Declaration EFR32MG24A010F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A010F1536IM48_Peripheral_Parameters EFR32MG24A010F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A010F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1024im40.h b/EFR32MG24/Device/Include/efr32mg24a020f1024im40.h new file mode 100644 index 0000000..c1a3cf7 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1024im40.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1024IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1024IM40_H +#define EFR32MG24A020F1024IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40 EFR32MG24A020F1024IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40_Core EFR32MG24A020F1024IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1024IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1024IM40_Part EFR32MG24A020F1024IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1024IM40) +#define EFR32MG24A020F1024IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1024IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1024IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1024IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40_Peripheral_TypeDefs EFR32MG24A020F1024IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1024IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40_Peripheral_Base EFR32MG24A020F1024IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40_Peripheral_Declaration EFR32MG24A020F1024IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM40_Peripheral_Parameters EFR32MG24A020F1024IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1024IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1024im48.h b/EFR32MG24/Device/Include/efr32mg24a020f1024im48.h new file mode 100644 index 0000000..e87b6ae --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1024im48.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1024IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1024IM48_H +#define EFR32MG24A020F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48 EFR32MG24A020F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48_Core EFR32MG24A020F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1024IM48_Part EFR32MG24A020F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1024IM48) +#define EFR32MG24A020F1024IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1024IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1024IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48_Peripheral_TypeDefs EFR32MG24A020F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48_Peripheral_Base EFR32MG24A020F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48_Peripheral_Declaration EFR32MG24A020F1024IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1024IM48_Peripheral_Parameters EFR32MG24A020F1024IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1024IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1536gm40.h b/EFR32MG24/Device/Include/efr32mg24a020f1536gm40.h new file mode 100644 index 0000000..5900eb0 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1536gm40.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1536GM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1536GM40_H +#define EFR32MG24A020F1536GM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40 EFR32MG24A020F1536GM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40_Core EFR32MG24A020F1536GM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1536GM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1536GM40_Part EFR32MG24A020F1536GM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1536GM40) +#define EFR32MG24A020F1536GM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1536GM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1536GM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1536GM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40_Peripheral_TypeDefs EFR32MG24A020F1536GM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1536GM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40_Peripheral_Base EFR32MG24A020F1536GM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40_Peripheral_Declaration EFR32MG24A020F1536GM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM40_Peripheral_Parameters EFR32MG24A020F1536GM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1536GM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a020f1536gm48.h new file mode 100644 index 0000000..d7f9c3d --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1536gm48.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1536GM48_H +#define EFR32MG24A020F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48 EFR32MG24A020F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48_Core EFR32MG24A020F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1536GM48_Part EFR32MG24A020F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1536GM48) +#define EFR32MG24A020F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48_Peripheral_TypeDefs EFR32MG24A020F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48_Peripheral_Base EFR32MG24A020F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48_Peripheral_Declaration EFR32MG24A020F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536GM48_Peripheral_Parameters EFR32MG24A020F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a020f1536im40.h new file mode 100644 index 0000000..86357bb --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1536im40.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1536IM40_H +#define EFR32MG24A020F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40 EFR32MG24A020F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40_Core EFR32MG24A020F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1536IM40_Part EFR32MG24A020F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1536IM40) +#define EFR32MG24A020F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40_Peripheral_TypeDefs EFR32MG24A020F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40_Peripheral_Base EFR32MG24A020F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40_Peripheral_Declaration EFR32MG24A020F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM40_Peripheral_Parameters EFR32MG24A020F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a020f1536im48.h b/EFR32MG24/Device/Include/efr32mg24a020f1536im48.h new file mode 100644 index 0000000..5e6944d --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a020f1536im48.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A020F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A020F1536IM48_H +#define EFR32MG24A020F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48 EFR32MG24A020F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48_Core EFR32MG24A020F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A020F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A020F1536IM48_Part EFR32MG24A020F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A020F1536IM48) +#define EFR32MG24A020F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A020F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A020F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A020F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48_Peripheral_TypeDefs EFR32MG24A020F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A020F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48_Peripheral_Base EFR32MG24A020F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48_Peripheral_Declaration EFR32MG24A020F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A020F1536IM48_Peripheral_Parameters EFR32MG24A020F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A020F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a021f1024im40.h b/EFR32MG24/Device/Include/efr32mg24a021f1024im40.h new file mode 100644 index 0000000..461cca3 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a021f1024im40.h @@ -0,0 +1,1514 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A021F1024IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A021F1024IM40_H +#define EFR32MG24A021F1024IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40 EFR32MG24A021F1024IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40_Core EFR32MG24A021F1024IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A021F1024IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A021F1024IM40_Part EFR32MG24A021F1024IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A021F1024IM40) +#define EFR32MG24A021F1024IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A021F1024IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A021F1024IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 6U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 6U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A021F1024IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40_Peripheral_TypeDefs EFR32MG24A021F1024IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A021F1024IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40_Peripheral_Base EFR32MG24A021F1024IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40_Peripheral_Declaration EFR32MG24A021F1024IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A021F1024IM40_Peripheral_Parameters EFR32MG24A021F1024IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A021F1024IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a110f1024im48.h b/EFR32MG24/Device/Include/efr32mg24a110f1024im48.h new file mode 100644 index 0000000..b893aad --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a110f1024im48.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A110F1024IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A110F1024IM48_H +#define EFR32MG24A110F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48 EFR32MG24A110F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48_Core EFR32MG24A110F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A110F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A110F1024IM48_Part EFR32MG24A110F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A110F1024IM48) +#define EFR32MG24A110F1024IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A110F1024IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A110F1024IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A110F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48_Peripheral_TypeDefs EFR32MG24A110F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A110F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48_Peripheral_Base EFR32MG24A110F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48_Peripheral_Declaration EFR32MG24A110F1024IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1024IM48_Peripheral_Parameters EFR32MG24A110F1024IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A110F1024IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a110f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a110f1536gm48.h new file mode 100644 index 0000000..5cb271c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a110f1536gm48.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A110F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A110F1536GM48_H +#define EFR32MG24A110F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48 EFR32MG24A110F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48_Core EFR32MG24A110F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A110F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A110F1536GM48_Part EFR32MG24A110F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A110F1536GM48) +#define EFR32MG24A110F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A110F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A110F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A110F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48_Peripheral_TypeDefs EFR32MG24A110F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A110F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48_Peripheral_Base EFR32MG24A110F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48_Peripheral_Declaration EFR32MG24A110F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A110F1536GM48_Peripheral_Parameters EFR32MG24A110F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A110F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a111f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a111f1536gm48.h new file mode 100644 index 0000000..a72495c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a111f1536gm48.h @@ -0,0 +1,1516 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A111F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A111F1536GM48_H +#define EFR32MG24A111F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48 EFR32MG24A111F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48_Core EFR32MG24A111F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A111F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A111F1536GM48_Part EFR32MG24A111F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A111F1536GM48) +#define EFR32MG24A111F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A111F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A111F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 9U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x02FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A111F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48_Peripheral_TypeDefs EFR32MG24A111F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A111F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48_Peripheral_Base EFR32MG24A111F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48_Peripheral_Declaration EFR32MG24A111F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A111F1536GM48_Peripheral_Parameters EFR32MG24A111F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A111F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a120f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a120f1536gm48.h new file mode 100644 index 0000000..ec39f88 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a120f1536gm48.h @@ -0,0 +1,1515 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A120F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A120F1536GM48_H +#define EFR32MG24A120F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48 EFR32MG24A120F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48_Core EFR32MG24A120F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A120F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A120F1536GM48_Part EFR32MG24A120F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A120F1536GM48) +#define EFR32MG24A120F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A120F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A120F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A120F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48_Peripheral_TypeDefs EFR32MG24A120F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A120F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48_Peripheral_Base EFR32MG24A120F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48_Peripheral_Declaration EFR32MG24A120F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A120F1536GM48_Peripheral_Parameters EFR32MG24A120F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A120F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a121f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24a121f1536gm48.h new file mode 100644 index 0000000..42f0fa0 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a121f1536gm48.h @@ -0,0 +1,1514 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A121F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A121F1536GM48_H +#define EFR32MG24A121F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48 EFR32MG24A121F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48_Core EFR32MG24A121F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A121F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A121F1536GM48_Part EFR32MG24A121F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A121F1536GM48) +#define EFR32MG24A121F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A121F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A121F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 9U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x02FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A121F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48_Peripheral_TypeDefs EFR32MG24A121F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A121F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48_Peripheral_Base EFR32MG24A121F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48_Peripheral_Declaration EFR32MG24A121F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A121F1536GM48_Peripheral_Parameters EFR32MG24A121F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A121F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a410f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a410f1536im40.h new file mode 100644 index 0000000..5499a9f --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a410f1536im40.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A410F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A410F1536IM40_H +#define EFR32MG24A410F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40 EFR32MG24A410F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40_Core EFR32MG24A410F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A410F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A410F1536IM40_Part EFR32MG24A410F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A410F1536IM40) +#define EFR32MG24A410F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A410F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A410F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A410F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40_Peripheral_TypeDefs EFR32MG24A410F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A410F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40_Peripheral_Base EFR32MG24A410F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40_Peripheral_Declaration EFR32MG24A410F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM40_Peripheral_Parameters EFR32MG24A410F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A410F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a410f1536im48.h b/EFR32MG24/Device/Include/efr32mg24a410f1536im48.h new file mode 100644 index 0000000..e6cff4c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a410f1536im48.h @@ -0,0 +1,1521 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A410F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A410F1536IM48_H +#define EFR32MG24A410F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48 EFR32MG24A410F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48_Core EFR32MG24A410F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A410F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A410F1536IM48_Part EFR32MG24A410F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A410F1536IM48) +#define EFR32MG24A410F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A410F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A410F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A410F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48_Peripheral_TypeDefs EFR32MG24A410F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A410F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48_Peripheral_Base EFR32MG24A410F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48_Peripheral_Declaration EFR32MG24A410F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A410F1536IM48_Peripheral_Parameters EFR32MG24A410F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A410F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a420f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a420f1536im40.h new file mode 100644 index 0000000..cc93414 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a420f1536im40.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A420F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A420F1536IM40_H +#define EFR32MG24A420F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40 EFR32MG24A420F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40_Core EFR32MG24A420F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A420F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A420F1536IM40_Part EFR32MG24A420F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A420F1536IM40) +#define EFR32MG24A420F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A420F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A420F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A420F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40_Peripheral_TypeDefs EFR32MG24A420F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A420F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40_Peripheral_Base EFR32MG24A420F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40_Peripheral_Declaration EFR32MG24A420F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM40_Peripheral_Parameters EFR32MG24A420F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A420F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a420f1536im48.h b/EFR32MG24/Device/Include/efr32mg24a420f1536im48.h new file mode 100644 index 0000000..dea8b8a --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a420f1536im48.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A420F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A420F1536IM48_H +#define EFR32MG24A420F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48 EFR32MG24A420F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48_Core EFR32MG24A420F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A420F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A420F1536IM48_Part EFR32MG24A420F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A420F1536IM48) +#define EFR32MG24A420F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A420F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A420F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A420F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48_Peripheral_TypeDefs EFR32MG24A420F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A420F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48_Peripheral_Base EFR32MG24A420F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48_Peripheral_Declaration EFR32MG24A420F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A420F1536IM48_Peripheral_Parameters EFR32MG24A420F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A420F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a610f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a610f1536im40.h new file mode 100644 index 0000000..de6494f --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a610f1536im40.h @@ -0,0 +1,1519 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A610F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A610F1536IM40_H +#define EFR32MG24A610F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40 EFR32MG24A610F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40_Core EFR32MG24A610F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A610F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A610F1536IM40_Part EFR32MG24A610F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A610F1536IM40) +#define EFR32MG24A610F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A610F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A610F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A610F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40_Peripheral_TypeDefs EFR32MG24A610F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A610F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40_Peripheral_Base EFR32MG24A610F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40_Peripheral_Declaration EFR32MG24A610F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A610F1536IM40_Peripheral_Parameters EFR32MG24A610F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A610F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24a620f1536im40.h b/EFR32MG24/Device/Include/efr32mg24a620f1536im40.h new file mode 100644 index 0000000..3551342 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24a620f1536im40.h @@ -0,0 +1,1517 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24A620F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24A620F1536IM40_H +#define EFR32MG24A620F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40 EFR32MG24A620F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40_Core EFR32MG24A620F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24A620F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24A620F1536IM40_Part EFR32MG24A620F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24A620F1536IM40) +#define EFR32MG24A620F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24A620F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24A620F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24A620F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40_Peripheral_TypeDefs EFR32MG24A620F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24A620F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40_Peripheral_Base EFR32MG24A620F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40_Peripheral_Declaration EFR32MG24A620F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24A620F1536IM40_Peripheral_Parameters EFR32MG24A620F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24A620F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b010f1024im48.h b/EFR32MG24/Device/Include/efr32mg24b010f1024im48.h new file mode 100644 index 0000000..d907c34 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b010f1024im48.h @@ -0,0 +1,1522 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B010F1024IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B010F1024IM48_H +#define EFR32MG24B010F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48 EFR32MG24B010F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48_Core EFR32MG24B010F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B010F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B010F1024IM48_Part EFR32MG24B010F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B010F1024IM48) +#define EFR32MG24B010F1024IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B010F1024IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B010F1024IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B010F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48_Peripheral_TypeDefs EFR32MG24B010F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B010F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48_Peripheral_Base EFR32MG24B010F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48_Peripheral_Declaration EFR32MG24B010F1024IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1024IM48_Peripheral_Parameters EFR32MG24B010F1024IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B010F1024IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b010f1536im40.h b/EFR32MG24/Device/Include/efr32mg24b010f1536im40.h new file mode 100644 index 0000000..d9b724e --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b010f1536im40.h @@ -0,0 +1,1520 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B010F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B010F1536IM40_H +#define EFR32MG24B010F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40 EFR32MG24B010F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40_Core EFR32MG24B010F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B010F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B010F1536IM40_Part EFR32MG24B010F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B010F1536IM40) +#define EFR32MG24B010F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B010F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B010F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B010F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40_Peripheral_TypeDefs EFR32MG24B010F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B010F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40_Peripheral_Base EFR32MG24B010F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40_Peripheral_Declaration EFR32MG24B010F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM40_Peripheral_Parameters EFR32MG24B010F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B010F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b010f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b010f1536im48.h new file mode 100644 index 0000000..a446b9e --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b010f1536im48.h @@ -0,0 +1,1522 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B010F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B010F1536IM48_H +#define EFR32MG24B010F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48 EFR32MG24B010F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48_Core EFR32MG24B010F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B010F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B010F1536IM48_Part EFR32MG24B010F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B010F1536IM48) +#define EFR32MG24B010F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B010F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B010F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B010F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48_Peripheral_TypeDefs EFR32MG24B010F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B010F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48_Peripheral_Base EFR32MG24B010F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48_Peripheral_Declaration EFR32MG24B010F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B010F1536IM48_Peripheral_Parameters EFR32MG24B010F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B010F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b020f1024im48.h b/EFR32MG24/Device/Include/efr32mg24b020f1024im48.h new file mode 100644 index 0000000..977b592 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b020f1024im48.h @@ -0,0 +1,1520 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B020F1024IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B020F1024IM48_H +#define EFR32MG24B020F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48 EFR32MG24B020F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48_Core EFR32MG24B020F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B020F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B020F1024IM48_Part EFR32MG24B020F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B020F1024IM48) +#define EFR32MG24B020F1024IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B020F1024IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B020F1024IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B020F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48_Peripheral_TypeDefs EFR32MG24B020F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B020F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48_Peripheral_Base EFR32MG24B020F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48_Peripheral_Declaration EFR32MG24B020F1024IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1024IM48_Peripheral_Parameters EFR32MG24B020F1024IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B020F1024IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b020f1536im40.h b/EFR32MG24/Device/Include/efr32mg24b020f1536im40.h new file mode 100644 index 0000000..6bbcf03 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b020f1536im40.h @@ -0,0 +1,1518 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B020F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B020F1536IM40_H +#define EFR32MG24B020F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40 EFR32MG24B020F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40_Core EFR32MG24B020F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B020F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B020F1536IM40_Part EFR32MG24B020F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B020F1536IM40) +#define EFR32MG24B020F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B020F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B020F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B020F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40_Peripheral_TypeDefs EFR32MG24B020F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B020F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40_Peripheral_Base EFR32MG24B020F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40_Peripheral_Declaration EFR32MG24B020F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM40_Peripheral_Parameters EFR32MG24B020F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B020F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b020f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b020f1536im48.h new file mode 100644 index 0000000..0b78f79 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b020f1536im48.h @@ -0,0 +1,1520 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B020F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B020F1536IM48_H +#define EFR32MG24B020F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48 EFR32MG24B020F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48_Core EFR32MG24B020F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B020F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B020F1536IM48_Part EFR32MG24B020F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B020F1536IM48) +#define EFR32MG24B020F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B020F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B020F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B020F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48_Peripheral_TypeDefs EFR32MG24B020F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B020F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48_Peripheral_Base EFR32MG24B020F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48_Peripheral_Declaration EFR32MG24B020F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B020F1536IM48_Peripheral_Parameters EFR32MG24B020F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B020F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b110f1536gm48.h b/EFR32MG24/Device/Include/efr32mg24b110f1536gm48.h new file mode 100644 index 0000000..61ef698 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b110f1536gm48.h @@ -0,0 +1,1518 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B110F1536GM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B110F1536GM48_H +#define EFR32MG24B110F1536GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48 EFR32MG24B110F1536GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48_Core EFR32MG24B110F1536GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B110F1536GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B110F1536GM48_Part EFR32MG24B110F1536GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B110F1536GM48) +#define EFR32MG24B110F1536GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B110F1536GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B110F1536GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B110F1536GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48_Peripheral_TypeDefs EFR32MG24B110F1536GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B110F1536GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48_Peripheral_Base EFR32MG24B110F1536GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48_Peripheral_Declaration EFR32MG24B110F1536GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536GM48_Peripheral_Parameters EFR32MG24B110F1536GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B110F1536GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b110f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b110f1536im48.h new file mode 100644 index 0000000..96c7868 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b110f1536im48.h @@ -0,0 +1,1518 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B110F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B110F1536IM48_H +#define EFR32MG24B110F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48 EFR32MG24B110F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48_Core EFR32MG24B110F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B110F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B110F1536IM48_Part EFR32MG24B110F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B110F1536IM48) +#define EFR32MG24B110F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B110F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B110F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B110F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48_Peripheral_TypeDefs EFR32MG24B110F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B110F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48_Peripheral_Base EFR32MG24B110F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48_Peripheral_Declaration EFR32MG24B110F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B110F1536IM48_Peripheral_Parameters EFR32MG24B110F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B110F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b120f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b120f1536im48.h new file mode 100644 index 0000000..caeed53 --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b120f1536im48.h @@ -0,0 +1,1516 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B120F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B120F1536IM48_H +#define EFR32MG24B120F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48 EFR32MG24B120F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48_Core EFR32MG24B120F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B120F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B120F1536IM48_Part EFR32MG24B120F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B120F1536IM48) +#define EFR32MG24B120F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B120F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B120F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B120F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48_Peripheral_TypeDefs EFR32MG24B120F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B120F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48_Peripheral_Base EFR32MG24B120F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48_Peripheral_Declaration EFR32MG24B120F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B120F1536IM48_Peripheral_Parameters EFR32MG24B120F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B120F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b210f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b210f1536im48.h new file mode 100644 index 0000000..92813cd --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b210f1536im48.h @@ -0,0 +1,1536 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B210F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B210F1536IM48_H +#define EFR32MG24B210F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48 EFR32MG24B210F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48_Core EFR32MG24B210F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B210F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B210F1536IM48_Part EFR32MG24B210F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B210F1536IM48) +#define EFR32MG24B210F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B210F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B210F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B210F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48_Peripheral_TypeDefs EFR32MG24B210F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_mvp.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B210F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48_Peripheral_Base EFR32MG24B210F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48_Peripheral_Declaration EFR32MG24B210F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B210F1536IM48_Peripheral_Parameters EFR32MG24B210F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B210F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b220f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b220f1536im48.h new file mode 100644 index 0000000..0a2fd6c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b220f1536im48.h @@ -0,0 +1,1534 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B220F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B220F1536IM48_H +#define EFR32MG24B220F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48 EFR32MG24B220F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Core EFR32MG24B220F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B220F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B220F1536IM48_Part EFR32MG24B220F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B220F1536IM48) +#define EFR32MG24B220F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B220F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B220F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B220F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_TypeDefs EFR32MG24B220F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_mvp.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Base EFR32MG24B220F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Declaration EFR32MG24B220F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Parameters EFR32MG24B220F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B220F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b310f1536im48.h b/EFR32MG24/Device/Include/efr32mg24b310f1536im48.h new file mode 100644 index 0000000..266b2bc --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b310f1536im48.h @@ -0,0 +1,1533 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B310F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B310F1536IM48_H +#define EFR32MG24B310F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48 EFR32MG24B310F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48_Core EFR32MG24B310F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B310F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B310F1536IM48_Part EFR32MG24B310F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B310F1536IM48) +#define EFR32MG24B310F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B310F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B310F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B310F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48_Peripheral_TypeDefs EFR32MG24B310F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_mvp.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B310F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48_Peripheral_Base EFR32MG24B310F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48_Peripheral_Declaration EFR32MG24B310F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B310F1536IM48_Peripheral_Parameters EFR32MG24B310F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B310F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/efr32mg24b610f1536im40.h b/EFR32MG24/Device/Include/efr32mg24b610f1536im40.h new file mode 100644 index 0000000..1f9f60c --- /dev/null +++ b/EFR32MG24/Device/Include/efr32mg24b610f1536im40.h @@ -0,0 +1,1520 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B610F1536IM40 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B610F1536IM40_H +#define EFR32MG24B610F1536IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40 EFR32MG24B610F1536IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40_Core EFR32MG24B610F1536IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B610F1536IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B610F1536IM40_Part EFR32MG24B610F1536IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B610F1536IM40) +#define EFR32MG24B610F1536IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B610F1536IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B610F1536IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00028000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ +#define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B610F1536IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40_Peripheral_TypeDefs EFR32MG24B610F1536IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_amuxcp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B610F1536IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40_Peripheral_Base EFR32MG24B610F1536IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40_Peripheral_Declaration EFR32MG24B610F1536IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B610F1536IM40_Peripheral_Parameters EFR32MG24B610F1536IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B610F1536IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/EFR32MG24/Device/Include/em_device.h b/EFR32MG24/Device/Include/em_device.h new file mode 100644 index 0000000..87e5c35 --- /dev/null +++ b/EFR32MG24/Device/Include/em_device.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32MG24A010F1024IM40) +#include "efr32mg24a010f1024im40.h" + +#elif defined(EFR32MG24A010F1024IM48) +#include "efr32mg24a010f1024im48.h" + +#elif defined(EFR32MG24A010F1536GM40) +#include "efr32mg24a010f1536gm40.h" + +#elif defined(EFR32MG24A010F1536GM48) +#include "efr32mg24a010f1536gm48.h" + +#elif defined(EFR32MG24A010F1536IM40) +#include "efr32mg24a010f1536im40.h" + +#elif defined(EFR32MG24A010F1536IM48) +#include "efr32mg24a010f1536im48.h" + +#elif defined(EFR32MG24A020F1024IM40) +#include "efr32mg24a020f1024im40.h" + +#elif defined(EFR32MG24A020F1024IM48) +#include "efr32mg24a020f1024im48.h" + +#elif defined(EFR32MG24A020F1536GM40) +#include "efr32mg24a020f1536gm40.h" + +#elif defined(EFR32MG24A020F1536GM48) +#include "efr32mg24a020f1536gm48.h" + +#elif defined(EFR32MG24A020F1536IM40) +#include "efr32mg24a020f1536im40.h" + +#elif defined(EFR32MG24A020F1536IM48) +#include "efr32mg24a020f1536im48.h" + +#elif defined(EFR32MG24A021F1024IM40) +#include "efr32mg24a021f1024im40.h" + +#elif defined(EFR32MG24A110F1024IM48) +#include "efr32mg24a110f1024im48.h" + +#elif defined(EFR32MG24A110F1536GM48) +#include "efr32mg24a110f1536gm48.h" + +#elif defined(EFR32MG24A111F1536GM48) +#include "efr32mg24a111f1536gm48.h" + +#elif defined(EFR32MG24A120F1536GM48) +#include "efr32mg24a120f1536gm48.h" + +#elif defined(EFR32MG24A121F1536GM48) +#include "efr32mg24a121f1536gm48.h" + +#elif defined(EFR32MG24A410F1536IM40) +#include "efr32mg24a410f1536im40.h" + +#elif defined(EFR32MG24A410F1536IM48) +#include "efr32mg24a410f1536im48.h" + +#elif defined(EFR32MG24A420F1536IM40) +#include "efr32mg24a420f1536im40.h" + +#elif defined(EFR32MG24A420F1536IM48) +#include "efr32mg24a420f1536im48.h" + +#elif defined(EFR32MG24A610F1536IM40) +#include "efr32mg24a610f1536im40.h" + +#elif defined(EFR32MG24A620F1536IM40) +#include "efr32mg24a620f1536im40.h" + +#elif defined(EFR32MG24B010F1024IM48) +#include "efr32mg24b010f1024im48.h" + +#elif defined(EFR32MG24B010F1536IM40) +#include "efr32mg24b010f1536im40.h" + +#elif defined(EFR32MG24B010F1536IM48) +#include "efr32mg24b010f1536im48.h" + +#elif defined(EFR32MG24B020F1024IM48) +#include "efr32mg24b020f1024im48.h" + +#elif defined(EFR32MG24B020F1536IM40) +#include "efr32mg24b020f1536im40.h" + +#elif defined(EFR32MG24B020F1536IM48) +#include "efr32mg24b020f1536im48.h" + +#elif defined(EFR32MG24B110F1536GM48) +#include "efr32mg24b110f1536gm48.h" + +#elif defined(EFR32MG24B110F1536IM48) +#include "efr32mg24b110f1536im48.h" + +#elif defined(EFR32MG24B120F1536IM48) +#include "efr32mg24b120f1536im48.h" + +#elif defined(EFR32MG24B210F1536IM48) +#include "efr32mg24b210f1536im48.h" + +#elif defined(EFR32MG24B220F1536IM48) +#include "efr32mg24b220f1536im48.h" + +#elif defined(EFR32MG24B310F1536IM48) +#include "efr32mg24b310f1536im48.h" + +#elif defined(EFR32MG24B610F1536IM40) +#include "efr32mg24b610f1536im40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/EFR32MG24/Device/Include/system_efr32mg24.h b/EFR32MG24/Device/Include/system_efr32mg24.h new file mode 100644 index 0000000..136e009 --- /dev/null +++ b/EFR32MG24/Device/Include/system_efr32mg24.h @@ -0,0 +1,245 @@ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32MG24 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32MG24_H +#define SYSTEM_EFR32MG24_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32MG24 EFR32MG24 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */ + +/*Re-direction of IRQHandler.*/ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ +void MVP_IRQHandler(void); /**< MVP IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */ +void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */ +void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */ +void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */ +void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ +void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ +void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */ +void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */ +void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +uint32_t SystemSYSCLKGet(void); +uint32_t SystemMaxCoreClockGet(void); +uint32_t SystemFSRCOClockGet(void); +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +uint32_t SystemCLKIN0Get(void); +uint32_t SystemHFRCOEM23ClockGet(void); +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32MG24_H */ diff --git a/EFR32MG24/Device/Source/system_efr32mg24.c b/EFR32MG24/Device/Source/system_efr32mg24.c new file mode 100644 index 0000000..7b3d6e5 --- /dev/null +++ b/EFR32MG24/Device/Source/system_efr32mg24.c @@ -0,0 +1,656 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices. + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective nFXO_FREQ */ +/* values according to board design. By defining the nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#if !defined(FSRCO_FREQ) +/* FSRCO frequency */ +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +/* HFXO frequency */ +#define HFXO_FREQ (39000000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +/* HFRCODPLL startup frequency */ +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +/* Maximum HFRCODPLL frequency */ +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +/* CLKIN0 input */ +#if !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +/* LFRCO frequency, tuned to below frequency during manufacturing. */ +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +/* ULFRCO frequency */ +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +/* LFXO frequency */ +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +/* NOTE: Gecko bootloaders can't have static variable allocation. */ +/* System HFXO clock frequency */ +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +/* System LFXO clock frequency */ +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +/* System HFRCODPLL clock frequency */ +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; +#endif + + /* config SMU to Secure and other peripherals to Non-Secure. */ + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + /* SAU treats all accesses as non-secure */ +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif /* __ARM_FEATURE_CMSE */ + +/* Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. */ + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif /*SL_TRUSTZONE_SECURE */ +} + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + + /* Get oscillator frequency band */ + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; /* Unused parameter */ +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + /* Find clock source */ + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + /* Unknown clock source. */ + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* The external crystal oscillator is not present if HFXO_FREQ==0 */ +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + /* This function will update the global variable */ + SystemHCLKGet(); + } +#else + (void) freq; /* Unused parameter */ +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get current HFRCOEM23 frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCOEM23 frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCOEM23ClockGet(void) +{ + uint32_t ret = 0UL; + + /* Get oscillator frequency band */ + switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 40000000UL; + break; + + default: + break; + } + return ret; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal present? */ +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; /* Unused parameter */ +#endif +} diff --git a/EFR32MG24/Scripts/EFR32MG24_Target.js b/EFR32MG24/Scripts/EFR32MG24_Target.js new file mode 100644 index 0000000..a5baeee --- /dev/null +++ b/EFR32MG24/Scripts/EFR32MG24_Target.js @@ -0,0 +1,44 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2022 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + diff --git a/EFR32MG24/Source/EFR32MG24_Startup.s b/EFR32MG24/Source/EFR32MG24_Startup.s new file mode 100644 index 0000000..1d9ec93 --- /dev/null +++ b/EFR32MG24/Source/EFR32MG24_Startup.s @@ -0,0 +1,288 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2022 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : EFR32MG24_Startup.s +Purpose : Startup and exception handlers for EFR32MG24 devices. + +Additional information: + Preprocessor Definitions + __NO_SYSTEM_INIT + If defined, + SystemInit is not called. + If not defined, + SystemInit is called. + SystemInit is usually supplied by the CMSIS files. + This file declares a weak implementation as fallback. + + __NO_SYSTEM_CLK_UPDATE + If defined, + SystemCoreClockUpdate is not automatically called. + Should be defined if SystemCoreClockUpdate must not be called before main(). + If not defined, + SystemCoreClockUpdate is called before the application entry point. + + __MEMORY_INIT + If defined, + MemoryInit is called after SystemInit. + void MemoryInit(void) can be implemented to enable external + memory controllers. + + __VECTORS_IN_RAM + If defined, + the vector table will be copied from Flash to RAM, + and the vector table offset register is adjusted. + + __VTOR_CONFIG + If defined, + the vector table offset register is set to point to the + application's vector table. + + __NO_FPU_ENABLE + If defined, the FPU is explicitly not enabled, + even if the compiler could use floating point operations. + + __SOFTFP__ + Defined by the build system. + If not defined, the FPU is enabled for floating point operations. +*/ + + .syntax unified + + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* Reset_Handler +* +* Function description +* Exception handler for reset. +* Generic bringup of a Cortex-M system. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + // + // Call SystemInit + // + bl SystemInit +#endif +#ifdef __MEMORY_INIT + // + // Call MemoryInit + // + bl MemoryInit +#endif +#ifdef __VECTORS_IN_RAM + // + // Copy vector table (from Flash) to RAM + // + ldr R0, =__vectors_start__ + ldr R1, =__vectors_end__ + ldr R2, =__vectors_ram_start__ +1: + cmp R0, R1 + beq 2f + ldr R3, [R0] + str R3, [R2] + adds R0, R0, #4 + adds R2, R2, #4 + b 1b +2: +#endif + +#if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM) + // + // Configure vector table offset register + // +#ifdef __ARM_ARCH_6M__ + ldr R0, =0xE000ED08 // VTOR_REG +#else + movw R0, 0xED08 // VTOR_REG + movt R0, 0xE000 +#endif +#ifdef __VECTORS_IN_RAM + ldr R1, =_vectors_ram +#else + ldr R1, =_vectors +#endif + str R1, [R0] +#endif +#if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE) + // + // Enable CP11 and CP10 with CPACR |= (0xf<<20) + // + movw R0, 0xED88 // CPACR + movt R0, 0xE000 + ldr R1, [R0] + orrs R1, R1, #(0xf << 20) + str R1, [R0] +#endif + // + // Call runtime initialization, which calls main(). + // + bl _start + + // + // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, + // when there is no strong definition of SystemInit. + // + .weak SystemInit + // + // Place SystemCoreClockUpdate in .init_array + // to be called after runtime initialization + // +#if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE) + .section .init_array, "aw" + .balign 4 + .word SystemCoreClockUpdate +#endif + +/********************************************************************* +* +* HardFault_Handler +* +* Function description +* Simple exception handler for HardFault. +* In case of a HardFault caused by BKPT instruction without +* debugger attached, return execution, otherwise stay in loop. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + +#undef L +#define L(label) .LHardFault_Handler_##label + + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + // + // Check if HardFault is caused by BKPT instruction + // + ldr R1, =0xE000ED2C // Load NVIC_HFSR + ldr R2, [R1] + cmp R2, #0 // Check NVIC_HFSR[31] + +L(hfLoop): + bmi L(hfLoop) // Not set? Stay in HardFault Handler. + // + // Continue execution after BKPT instruction + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R0, #4 + mov R1, LR + tst R0, R1 // Check EXC_RETURN in Link register bit 2. + bne L(Uses_PSP) + mrs R0, MSP // Stacking was using MSP. + b L(Pass_StackPtr) +L(Uses_PSP): + mrs R0, PSP // Stacking was using PSP. +L(Pass_StackPtr): +#else + tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack + ite eq + mrseq R0, MSP // Frame stored on MSP + mrsne R0, PSP // Frame stored on PSP +#endif + // + // Reset HardFault Status + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] +#else + orr R2, R2, #0x80000000 + str R2, [R1] +#endif + // + // Adjust return address + // + ldr R1, [R0, #24] // Get stored PC from stack + adds R1, #2 // Adjust PC by 2 to skip current BKPT + str R1, [R0, #24] // Write back adjusted PC to stack + // + bx LR // Return + +/********************************************************************* +* +* SystemCoreClockUpdate +* +* Function description +* Set the SystemCoreClock variable. +* +* Additional information +* This is a weak implementation, as it is missing in the CMSIS files. +* It is recommended to supply your own implementation. +*/ + .weak SystemCoreClockUpdate + .section .init.SystemCoreClockUpdate, "ax" + .balign 2 + .thumb_func +SystemCoreClockUpdate: + push {LR} + sub SP, SP, #4 + bl SystemHCLKGet + add SP, SP, #4 + pop {PC} + +/*************************** End of file ****************************/ diff --git a/EFR32MG24/Source/efr32mg24_Vectors.s b/EFR32MG24/Source/efr32mg24_Vectors.s new file mode 100644 index 0000000..6c5627f --- /dev/null +++ b/EFR32MG24/Source/efr32mg24_Vectors.s @@ -0,0 +1,301 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2022 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : efr32mg24_Vectors.s +Purpose : Exception and interrupt vectors for efr32mg24 devices. + +Additional information: + Preprocessor Definitions + __NO_EXTERNAL_INTERRUPTS + If defined, + the vector table will contain only the internal exceptions + and interrupts. + __VECTORS_IN_RAM + If defined, + an area of RAM, large enough to store the vector table, + will be reserved. + + __OPTIMIZATION_SMALL + If defined, + all weak definitions of interrupt handlers will share the + same implementation. + If not defined, + all weak definitions of interrupt handlers will be defined + with their own implementation. +*/ + .syntax unified + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ + +// +// Directly place a vector (word) in the vector table +// +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// +// Declare an exception handler with a weak definition +// +.macro EXC_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// +// Declare an interrupt handler with a weak definition +// +.macro ISR_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern __stack_end__ + .extern Reset_Handler + .extern HardFault_Handler + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* Setup of the vector table and weak definition of interrupt handlers +* +*/ + .section .vectors, "ax" + .code 16 + .balign 512 + .global _vectors + .global __Vectors +_vectors: +__Vectors: + // + // Internal exceptions and interrupts + // + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + VECTOR HardFault_Handler + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER SVC_Handler + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + // + // External interrupts + // +#ifndef __NO_EXTERNAL_INTERRUPTS + ISR_HANDLER SMU_SECURE_IRQHandler + ISR_HANDLER SMU_S_PRIVILEGED_IRQHandler + ISR_HANDLER SMU_NS_PRIVILEGED_IRQHandler + ISR_HANDLER EMU_IRQHandler + ISR_HANDLER TIMER0_IRQHandler + ISR_HANDLER TIMER1_IRQHandler + ISR_HANDLER TIMER2_IRQHandler + ISR_HANDLER TIMER3_IRQHandler + ISR_HANDLER TIMER4_IRQHandler + ISR_HANDLER USART0_RX_IRQHandler + ISR_HANDLER USART0_TX_IRQHandler + ISR_HANDLER EUSART0_RX_IRQHandler + ISR_HANDLER EUSART0_TX_IRQHandler + ISR_HANDLER EUSART1_RX_IRQHandler + ISR_HANDLER EUSART1_TX_IRQHandler + ISR_HANDLER MVP_IRQHandler + ISR_HANDLER ICACHE0_IRQHandler + ISR_HANDLER BURTC_IRQHandler + ISR_HANDLER LETIMER0_IRQHandler + ISR_HANDLER SYSCFG_IRQHandler + ISR_HANDLER MPAHBRAM_IRQHandler + ISR_HANDLER LDMA_IRQHandler + ISR_HANDLER LFXO_IRQHandler + ISR_HANDLER LFRCO_IRQHandler + ISR_HANDLER ULFRCO_IRQHandler + ISR_HANDLER GPIO_ODD_IRQHandler + ISR_HANDLER GPIO_EVEN_IRQHandler + ISR_HANDLER I2C0_IRQHandler + ISR_HANDLER I2C1_IRQHandler + ISR_HANDLER EMUDG_IRQHandler + ISR_HANDLER AGC_IRQHandler + ISR_HANDLER BUFC_IRQHandler + ISR_HANDLER FRC_PRI_IRQHandler + ISR_HANDLER FRC_IRQHandler + ISR_HANDLER MODEM_IRQHandler + ISR_HANDLER PROTIMER_IRQHandler + ISR_HANDLER RAC_RSM_IRQHandler + ISR_HANDLER RAC_SEQ_IRQHandler + ISR_HANDLER HOSTMAILBOX_IRQHandler + ISR_HANDLER SYNTH_IRQHandler + ISR_HANDLER ACMP0_IRQHandler + ISR_HANDLER ACMP1_IRQHandler + ISR_HANDLER WDOG0_IRQHandler + ISR_HANDLER WDOG1_IRQHandler + ISR_HANDLER HFXO0_IRQHandler + ISR_HANDLER HFRCO0_IRQHandler + ISR_HANDLER HFRCOEM23_IRQHandler + ISR_HANDLER CMU_IRQHandler + ISR_HANDLER AES_IRQHandler + ISR_HANDLER IADC_IRQHandler + ISR_HANDLER MSC_IRQHandler + ISR_HANDLER DPLL0_IRQHandler + ISR_HANDLER EMUEFP_IRQHandler + ISR_HANDLER DCDC_IRQHandler + ISR_HANDLER PCNT0_IRQHandler + ISR_HANDLER SW0_IRQHandler + ISR_HANDLER SW1_IRQHandler + ISR_HANDLER SW2_IRQHandler + ISR_HANDLER SW3_IRQHandler + ISR_HANDLER KERNEL0_IRQHandler + ISR_HANDLER KERNEL1_IRQHandler + ISR_HANDLER M33CTI0_IRQHandler + ISR_HANDLER M33CTI1_IRQHandler + ISR_HANDLER FPUEXH_IRQHandler + ISR_HANDLER SETAMPERHOST_IRQHandler + ISR_HANDLER SEMBRX_IRQHandler + ISR_HANDLER SEMBTX_IRQHandler + ISR_HANDLER SYSRTC_APP_IRQHandler + ISR_HANDLER SYSRTC_SEQ_IRQHandler + ISR_HANDLER KEYSCAN_IRQHandler + ISR_HANDLER RFECA0_IRQHandler + ISR_HANDLER RFECA1_IRQHandler + ISR_HANDLER VDAC0_IRQHandler + ISR_HANDLER VDAC1_IRQHandler + ISR_HANDLER AHB2AHB0_IRQHandler + ISR_HANDLER AHB2AHB1_IRQHandler +#endif + // + .section .vectors, "ax" +_vectors_end: + +#ifdef __VECTORS_IN_RAM + // + // Reserve space with the size of the vector table + // in the designated RAM section. + // + .section .vectors_ram, "ax" + .balign 512 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop + + +/*************************** End of file ****************************/ diff --git a/EFR32MG24B310F1536IM48_MemoryMap.xml b/EFR32MG24B310F1536IM48_MemoryMap.xml new file mode 100644 index 0000000..00b41bb --- /dev/null +++ b/EFR32MG24B310F1536IM48_MemoryMap.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/EFR32MG24B310F1536IM48_Registers.xml b/EFR32MG24B310F1536IM48_Registers.xml new file mode 100644 index 0000000..3fcf678 --- /dev/null +++ b/EFR32MG24B310F1536IM48_Registers.xml @@ -0,0 +1,28828 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EFR32MG24_Flash.icf b/EFR32MG24_Flash.icf new file mode 100644 index 0000000..db9dadc --- /dev/null +++ b/EFR32MG24_Flash.icf @@ -0,0 +1,138 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2022 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +-------------------------- END-OF-HEADER ----------------------------- + +File : EFR32MG24_Flash.icf +Purpose : EFR32MG24 linker script for application placement in Flash, + for use with the SEGGER Linker. +Maps : EFR32MG24A010F1024IM40, EFR32MG24A010F1024IM48, EFR32MG24A010F1536GM40, + EFR32MG24A010F1536GM48, EFR32MG24A010F1536IM40, EFR32MG24A010F1536IM48, + EFR32MG24A020F1024IM40, EFR32MG24A020F1024IM48, EFR32MG24A020F1536GM40, + EFR32MG24A020F1536GM48, EFR32MG24A020F1536IM40, EFR32MG24A020F1536IM48, + EFR32MG24A021F1024IM40, EFR32MG24A110F1024IM48, EFR32MG24A110F1536GM48, + EFR32MG24A111F1536GM48, EFR32MG24A120F1536GM48, EFR32MG24A121F1536GM48, + EFR32MG24A410F1536IM40, EFR32MG24A410F1536IM48, EFR32MG24A420F1536IM40, + EFR32MG24A420F1536IM48, EFR32MG24A610F1536IM40, EFR32MG24A620F1536IM40, + EFR32MG24B010F1024IM48, EFR32MG24B010F1536IM40, EFR32MG24B010F1536IM48, + EFR32MG24B020F1024IM48, EFR32MG24B020F1536IM40, EFR32MG24B020F1536IM48, + EFR32MG24B110F1536GM48, EFR32MG24B110F1536IM48, EFR32MG24B120F1536IM48, + EFR32MG24B210F1536IM48, EFR32MG24B220F1536IM48, EFR32MG24B310F1536IM48, + EFR32MG24B610F1536IM40 +Literature: + [1] SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html) + [2] SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files) +*/ + +define memory with size = 4G; + +// +// Combined regions per memory type +// +define region FLASH = FLASH1; +define region RAM = RAM1; + +// +// Block definitions +// +define block vectors { section .vectors }; // Vector table section +define block vectors_ram { section .vectors_ram }; // Vector table section +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with auto size = __HEAPSIZE__, alignment = 8, readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, readwrite access { }; + +// +// Explicit initialization settings for sections +// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits +// +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { block vectors_ram }; +initialize by copy with packing=auto { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +#define USES_ALLOC_FUNC \ + linked symbol malloc || linked symbol aligned_alloc || \ + linked symbol calloc || linked symbol realloc + +initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap }; // Init the heap if one is required +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +//assert with warning "free() linked into application but there are no calls to an allocation function!" { +// linked symbol free => USES_ALLOC_FUNC +//}; + +assert with error "heap is too small!" { USES_ALLOC_FUNC => size of block heap >= 48 }; +assert with error "heap size not a multiple of 8!" { USES_ALLOC_FUNC => size of block heap % 8 == 0 }; +assert with error "heap not correctly aligned!" { USES_ALLOC_FUNC => start of block heap % 8 == 0 }; + +// +// Explicit placement in FLASHn +// +place in FLASH1 { section .FLASH1, section .FLASH1.* }; +// +// FLASH Placement +// +place at start of FLASH { block vectors }; // Vector table section +place in FLASH with minimum size order { block tdata_load, // Thread-local-storage load image + block exidx, // ARM exception unwinding block + block ctors, // Constructors block + block dtors, // Destructors block + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// Explicit placement in RAMn +// +place in RAM1 { section .RAM1, section .RAM1.* }; +// +// RAM Placement +// +place at start of RAM { block vectors_ram }; +place in RAM { section .fast, section .fast.* }; // "ramfunc" section +place in RAM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack }; // Stack reserved block at the end diff --git a/Firmware_Debug.jlink b/Firmware_Debug.jlink new file mode 100644 index 0000000..27f7fc6 --- /dev/null +++ b/Firmware_Debug.jlink @@ -0,0 +1,48 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x20000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 diff --git a/Libs/CMSIS/Core/Include/cmsis_compiler.h b/Libs/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Libs/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Libs/CMSIS/Core/Include/cmsis_gcc.h b/Libs/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/Libs/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Libs/CMSIS/Core/Include/cmsis_version.h b/Libs/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..2f048e4 --- /dev/null +++ b/Libs/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Libs/CMSIS/Core/Include/core_cm33.h b/Libs/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..f9cf6ab --- /dev/null +++ b/Libs/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3265 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Libs/CMSIS/Core/Include/mpu_armv8.h b/Libs/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..3de16ef --- /dev/null +++ b/Libs/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Libs/CMSIS/Core/Include/tz_context.h b/Libs/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Libs/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Libs/CMSIS/RTOS2/Include/cmsis_os2.h b/Libs/CMSIS/RTOS2/Include/cmsis_os2.h new file mode 100644 index 0000000..5050964 --- /dev/null +++ b/Libs/CMSIS/RTOS2/Include/cmsis_os2.h @@ -0,0 +1,759 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 12. June 2020 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +// Minimum number of priorities required by CMSIS-RTOS2 +#define osMinNumPriority 56 + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Libs/CMSIS/RTOS2/Include/os_tick.h b/Libs/CMSIS/RTOS2/Include/os_tick.h new file mode 100644 index 0000000..3cfd895 --- /dev/null +++ b/Libs/CMSIS/RTOS2/Include/os_tick.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.2 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#ifdef __cplusplus +} +#endif + +#endif /* OS_TICK_H */ diff --git a/Libs/CMSIS/RTOS2/Source/os_systick.c b/Libs/CMSIS/RTOS2/Source/os_systick.c new file mode 100644 index 0000000..3cce53c --- /dev/null +++ b/Libs/CMSIS/RTOS2/Source/os_systick.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.3 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST __attribute__((section(".bss.os"))); + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos); +} + +#endif // SysTick diff --git a/Libs/FreeRTOS/cmsis/Include/freertos_mpool.h b/Libs/FreeRTOS/cmsis/Include/freertos_mpool.h new file mode 100644 index 0000000..cea5017 --- /dev/null +++ b/Libs/FreeRTOS/cmsis/Include/freertos_mpool.h @@ -0,0 +1,63 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_mpool.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_MPOOL_H_ +#define FREERTOS_MPOOL_H_ + +#include +#include "FreeRTOS.h" +#include "semphr.h" + +/* Memory Pool implementation definitions */ +#define MPOOL_STATUS 0x5EED0000U + +/* Memory Block header */ +typedef struct { + void *next; /* Pointer to next block */ +} MemPoolBlock_t; + +/* Memory Pool control block */ +typedef struct MemPoolDef_t { + MemPoolBlock_t *head; /* Pointer to head block */ + SemaphoreHandle_t sem; /* Pool semaphore handle */ + uint8_t *mem_arr; /* Pool memory array */ + uint32_t mem_sz; /* Pool memory array size */ + const char *name; /* Pointer to name string */ + uint32_t bl_sz; /* Size of a single block */ + uint32_t bl_cnt; /* Number of blocks */ + uint32_t n; /* Block allocation index */ + volatile uint32_t status; /* Object status flags */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mem_sem; /* Semaphore object memory */ +#endif +} MemPool_t; + +/* No need to hide static object type, just align to coding style */ +#define StaticMemPool_t MemPool_t + +/* Define memory pool control block size */ +#define MEMPOOL_CB_SIZE (sizeof(StaticMemPool_t)) + +/* Define size of the byte array required to create count of blocks of given size */ +#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count)) + +#endif /* FREERTOS_MPOOL_H_ */ diff --git a/Libs/FreeRTOS/cmsis/Include/freertos_os2.h b/Libs/FreeRTOS/cmsis/Include/freertos_os2.h new file mode 100644 index 0000000..5d6f88d --- /dev/null +++ b/Libs/FreeRTOS/cmsis/Include/freertos_os2.h @@ -0,0 +1,336 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_OS2_H_ +#define FREERTOS_OS2_H_ + +#include +#include + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core + +#if defined(_RTE_) +#include "RTE_Components.h" // Component selection +#include CMSIS_device_header + +/* Configuration and component setup check */ +#if defined(RTE_Compiler_EventRecorder) + #if !defined(EVR_FREERTOS_DISABLE) + #define USE_TRACE_EVENT_RECORDER + /* + FreeRTOS provides functions and hooks to support execution tracing. This + functionality is only enabled if configUSE_TRACE_FACILITY == 1. + Set #define configUSE_TRACE_FACILITY 1 in FreeRTOSConfig.h to enable trace events. + */ + #if (configUSE_TRACE_FACILITY == 0) + #error "Definition configUSE_TRACE_FACILITY must equal 1 to enable FreeRTOS trace events." + #endif + #endif +#endif + +#if defined(RTE_RTOS_FreeRTOS_HEAP_1) + #define USE_FreeRTOS_HEAP_1 +#endif + +#if defined(RTE_RTOS_FreeRTOS_HEAP_5) + #define USE_FreeRTOS_HEAP_5 +#endif +#endif /* _RTE_ */ + +/* + CMSIS-RTOS2 FreeRTOS image size optimization definitions. + + Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when + certain functionality is not required when using CMSIS-RTOS2 API. + In general optimization decisions are left to the tool chain but in cases + when coding style prevents it to optimize the code following optional + definitions can be used. +*/ + +/* + Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from + the application image. +*/ +#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image. +*/ +#ifndef configUSE_OS2_THREAD_ENUMERATE +#define configUSE_OS2_THREAD_ENUMERATE 1 +#endif + +/* + Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear + operation from ISR. +*/ +#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image. +*/ +#ifndef configUSE_OS2_THREAD_FLAGS +#define configUSE_OS2_THREAD_FLAGS configUSE_TASK_NOTIFICATIONS +#endif + +/* + Option to exclude CMSIS-RTOS2 Timer API functions from the application image. +*/ +#ifndef configUSE_OS2_TIMER +#define configUSE_OS2_TIMER configUSE_TIMERS +#endif + +/* + Option to exclude CMSIS-RTOS2 Mutex API functions from the application image. +*/ +#ifndef configUSE_OS2_MUTEX +#define configUSE_OS2_MUTEX configUSE_MUTEXES +#endif + + +/* + CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h). + + Note: CMSIS-RTOS API requires functions included by using following definitions. + In case if certain API function is not used compiler will optimize it away. +*/ +#if (INCLUDE_xSemaphoreGetMutexHolder == 0) + /* + CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if + osMutexGetOwner is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error. + */ + #error "Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API." +#endif +#if (INCLUDE_vTaskDelay == 0) + /* + CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if + osDelay is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelay 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelayUntil == 0) + /* + CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if + osDelayUntil is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelayUntil 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelete == 0) + /* + CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function + vTaskDelete. In case if they are not used in the application image, compiler + will optimize them away. + Set #define INCLUDE_vTaskDelete 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetCurrentTaskHandle == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement + functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these + functions are not used in the application image, compiler will optimize them away. + Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetSchedulerState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel + tick handling and therefore it is vital that xTaskGetSchedulerState is included into + the application image. + Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API." +#endif +#if (INCLUDE_uxTaskGetStackHighWaterMark == 0) + /* + CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark. + In case if osThreadGetStackSpace is not used in the application image, compiler will + optimize it away. + Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_uxTaskPriorityGet == 0) + /* + CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if + osThreadGetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskPrioritySet == 0) + /* + CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if + osThreadSetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskPrioritySet 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_eTaskGetState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState + and osThreadTerminate. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define INCLUDE_eTaskGetState 1 to fix this error. + */ + #error "Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskSuspend == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement + functions osThreadSuspend and osThreadResume. In case if these functions are not + used in the application image, compiler will optimize them away. + Set #define INCLUDE_vTaskSuspend 1 to fix this error. + + Alternatively, if the application does not use osThreadSuspend and + osThreadResume they can be excluded from the image code by setting: + #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) + #error "Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API." + #endif +#endif +#if (INCLUDE_xTimerPendFunctionCall == 0) + /* + CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from + the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and + xEventGroupClearBitsFromISR which are only enabled if timers are operational and + xTimerPendFunctionCall in enabled. + Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1 + to fix this error. + + Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear + from the ISR their operation from ISR can be restricted by setting: + #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1) + #error "Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API." + #endif +#endif + +#if (configUSE_TIMERS == 0) + /* + CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement + timer management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TIMERS 1 to fix this error. + + Alternatively, if the application does not use timer functions they can be + excluded from the image code by setting: + #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_TIMER == 1) + #error "Definition configUSE_TIMERS must equal 1 to implement Timer Management API." + #endif +#endif + +#if (configUSE_MUTEXES == 0) + /* + CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement + mutex management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_MUTEXES 1 to fix this error. + + Alternatively, if the application does not use mutex functions they can be + excluded from the image code by setting: + #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_MUTEX == 1) + #error "Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API." + #endif +#endif + +#if (configUSE_COUNTING_SEMAPHORES == 0) + /* + CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting + to implement memory pools. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error. + */ + #error "Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API." +#endif +#if (configUSE_TASK_NOTIFICATIONS == 0) + /* + CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement + thread flag management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error. + + Alternatively, if the application does not use thread flags functions they can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_FLAGS == 1) + #error "Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API." + #endif +#endif + +#if (configUSE_TRACE_FACILITY == 0) + /* + CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState + which is only enabled if configUSE_TRACE_FACILITY == 1. + Set #define configUSE_TRACE_FACILITY 1 to fix this error. + + Alternatively, if the application does not use osThreadEnumerate it can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_ENUMERATE == 1) + #error "Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate." + #endif +#endif + +#if (configUSE_16_BIT_TICKS == 1) + /* + CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on + a 32-bit CPU architectures. + Set #define configUSE_16_BIT_TICKS 0 to fix this error. + */ + #error "Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API." +#endif + +#if (configMAX_PRIORITIES != 56) + /* + CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2 + implementation should implement the same number of priorities. + Set #define configMAX_PRIORITIES 56 to fix this error. + */ + #error "Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API." +#endif +#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0) + /* + CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port + optimised selection for Cortex core only handles 32 different priorities. + Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error. + */ + #error "Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API." +#endif + +#endif /* FREERTOS_OS2_H_ */ diff --git a/Libs/FreeRTOS/cmsis/Source/cmsis_os2.c b/Libs/FreeRTOS/cmsis/Source/cmsis_os2.c new file mode 100644 index 0000000..719e81f --- /dev/null +++ b/Libs/FreeRTOS/cmsis/Source/cmsis_os2.c @@ -0,0 +1,2459 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.c + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#include + +#include "cmsis_os2.h" // ::CMSIS:RTOS2 +#include "cmsis_compiler.h" // Compiler agnostic definitions +#include "os_tick.h" // OS Tick API + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core +#include "task.h" // ARM.FreeRTOS::RTOS:Core +#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups +#include "semphr.h" // ARM.FreeRTOS::RTOS:Core + +#include "freertos_mpool.h" // osMemoryPool definitions +#include "freertos_os2.h" // Configuration check and setup + +/*---------------------------------------------------------------------------*/ +#ifndef __ARM_ARCH_6M__ + #define __ARM_ARCH_6M__ 0 +#endif +#ifndef __ARM_ARCH_7M__ + #define __ARM_ARCH_7M__ 0 +#endif +#ifndef __ARM_ARCH_7EM__ + #define __ARM_ARCH_7EM__ 0 +#endif +#ifndef __ARM_ARCH_8M_MAIN__ + #define __ARM_ARCH_8M_MAIN__ 0 +#endif +#ifndef __ARM_ARCH_7A__ + #define __ARM_ARCH_7A__ 0 +#endif + +#if ((__ARM_ARCH_7M__ == 1U) || \ + (__ARM_ARCH_7EM__ == 1U) || \ + (__ARM_ARCH_8M_MAIN__ == 1U)) +#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) +#elif (__ARM_ARCH_6M__ == 1U) +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#elif (__ARM_ARCH_7A__ == 1U) +/* CPSR mask bits */ +#define CPSR_MASKBIT_I 0x80U + +#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U) +#else +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#endif + +#if (__ARM_ARCH_7A__ == 1U) +/* CPSR mode bitmasks */ +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) +#else +#define IS_IRQ_MODE() (__get_IPSR() != 0U) +#endif + +#define IS_IRQ() (IS_IRQ_MODE() || (IS_IRQ_MASKED() && (KernelState == osKernelRunning))) + +/* Limits */ +#define MAX_BITS_TASK_NOTIFY 31U +#define MAX_BITS_EVENT_GROUPS 24U + +#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U)) +#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U)) + +/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */ +#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \ + ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \ + ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL)) + +#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +/* Timer callback information structure definition */ +typedef struct { + osTimerFunc_t func; + void *arg; +} TimerCallback_t; + +/* Kernel initialization state */ +static osKernelState_t KernelState = osKernelInactive; + +/* + Heap region definition used by heap_5 variant + + Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if + heap regions are already defined and vPortDefineHeapRegions is called in application. + + Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using + definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS + is possible by defining it globally or in FreeRTOSConfig.h. +*/ +#if defined(USE_FreeRTOS_HEAP_5) +#if (configAPPLICATION_ALLOCATED_HEAP == 0) + /* + FreeRTOS heap is not defined by the application. + Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h) + is provided by default. Define configHEAP_5_REGIONS to provide custom + HeapRegion_t array. + */ + #define HEAP_5_REGION_SETUP 1 + + #ifndef configHEAP_5_REGIONS + #define configHEAP_5_REGIONS xHeapRegions + + static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + + static HeapRegion_t xHeapRegions[] = { + { ucHeap, configTOTAL_HEAP_SIZE }, + { NULL, 0 } + }; + #else + /* Global definition is provided to override default heap array */ + extern HeapRegion_t configHEAP_5_REGIONS[]; + #endif +#else + /* + The application already defined the array used for the FreeRTOS heap and + called vPortDefineHeapRegions to initialize heap. + */ + #define HEAP_5_REGION_SETUP 0 +#endif /* configAPPLICATION_ALLOCATED_HEAP */ +#endif /* USE_FreeRTOS_HEAP_5 */ + +#if defined(SysTick) +#undef SysTick_Handler + +/* CMSIS SysTick interrupt handler prototype */ +extern void SysTick_Handler (void) PRIVILEGED_FUNCTION; +/* FreeRTOS tick timer interrupt handler prototype */ +extern void xPortSysTickHandler (void) PRIVILEGED_FUNCTION; + +/* + SysTick handler implementation that also clears overflow flag. +*/ +void SysTick_Handler (void) { + /* Clear overflow flag */ + SysTick->CTRL; + + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + /* Call tick handler */ + xPortSysTickHandler(); + } +} +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +PRIVILEGED_FUNCTION __STATIC_INLINE void SVC_Setup (void) { +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + NVIC_SetPriority (SVCall_IRQn, 0U); +#endif +} + +/* + Function macro used to retrieve semaphore count from ISR +*/ +#ifndef uxSemaphoreGetCountFromISR +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) +#endif + +/*---------------------------------------------------------------------------*/ + +PRIVILEGED_FUNCTION osStatus_t osKernelInitialize (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelInactive) { + #if defined(USE_TRACE_EVENT_RECORDER) + EvrFreeRTOSSetup(0U); + #endif + #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); + #endif + KernelState = osKernelReady; + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + + if (version != NULL) { + /* Version encoding is major.minor.rev: mmnnnrrrr dec */ + version->api = KERNEL_VERSION; + version->kernel = KERNEL_VERSION; + } + + if ((id_buf != NULL) && (id_size != 0U)) { + if (id_size > sizeof(KERNEL_ID)) { + id_size = sizeof(KERNEL_ID); + } + memcpy(id_buf, KERNEL_ID, id_size); + } + + return (osOK); +} + +PRIVILEGED_FUNCTION osKernelState_t osKernelGetState (void) { + osKernelState_t state; + + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_RUNNING: + state = osKernelRunning; + break; + + case taskSCHEDULER_SUSPENDED: + state = osKernelLocked; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + if (KernelState == osKernelReady) { + state = osKernelReady; + } else { + state = osKernelInactive; + } + break; + } + + return (state); +} + +PRIVILEGED_FUNCTION osStatus_t osKernelStart (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelReady) { + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + /* Start the kernel scheduler */ + vTaskStartScheduler(); + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION int32_t osKernelLock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + break; + + case taskSCHEDULER_RUNNING: + vTaskSuspendAll(); + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +PRIVILEGED_FUNCTION int32_t osKernelUnlock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) { + lock = (int32_t)osError; + } + } + break; + + case taskSCHEDULER_RUNNING: + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +PRIVILEGED_FUNCTION int32_t osKernelRestoreLock (int32_t lock) { + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + case taskSCHEDULER_RUNNING: + if (lock == 1) { + vTaskSuspendAll(); + } + else { + if (lock != 0) { + lock = (int32_t)osError; + } + else { + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { + lock = (int32_t)osError; + } + } + } + } + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +PRIVILEGED_FUNCTION uint32_t osKernelGetTickCount (void) { + TickType_t ticks; + + if (IS_IRQ()) { + ticks = xTaskGetTickCountFromISR(); + } else { + ticks = xTaskGetTickCount(); + } + + return (ticks); +} + +PRIVILEGED_FUNCTION uint32_t osKernelGetTickFreq (void) { + return (configTICK_RATE_HZ); +} + +PRIVILEGED_FUNCTION uint32_t osKernelGetSysTimerCount (void) { + uint32_t irqmask = IS_IRQ_MASKED(); + TickType_t ticks; + uint32_t val; + + __disable_irq(); + + ticks = xTaskGetTickCount(); + val = OS_Tick_GetCount(); + + if (OS_Tick_GetOverflow() != 0U) { + val = OS_Tick_GetCount(); + ticks++; + } + val += ticks * OS_Tick_GetInterval(); + + if (irqmask == 0U) { + __enable_irq(); + } + + return (val); +} + +PRIVILEGED_FUNCTION uint32_t osKernelGetSysTimerFreq (void) { + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +PRIVILEGED_FUNCTION osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + const char *name; + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + + if (!IS_IRQ() && (func != NULL)) { + stack = configMINIMAL_STACK_SIZE; + prio = (UBaseType_t)osPriorityNormal; + + name = NULL; + mem = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + if (attr->priority != osPriorityNone) { + prio = (UBaseType_t)attr->priority; + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + return (NULL); + } + + if (attr->stack_size > 0U) { + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + (StaticTask_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + hTask = NULL; + } + #endif + } + } + } + + return ((osThreadId_t)hTask); +} + +PRIVILEGED_FUNCTION const char *osThreadGetName (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + const char *name; + + if (IS_IRQ() || (hTask == NULL)) { + name = NULL; + } else { + name = pcTaskGetName (hTask); + } + + return (name); +} + +PRIVILEGED_FUNCTION osThreadId_t osThreadGetId (void) { + osThreadId_t id; + + id = (osThreadId_t)xTaskGetCurrentTaskHandle(); + + return (id); +} + +PRIVILEGED_FUNCTION osThreadState_t osThreadGetState (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osThreadState_t state; + + if (IS_IRQ() || (hTask == NULL)) { + state = osThreadError; + } + else { + switch (eTaskGetState (hTask)) { + case eRunning: state = osThreadRunning; break; + case eReady: state = osThreadReady; break; + case eBlocked: + case eSuspended: state = osThreadBlocked; break; + case eDeleted: state = osThreadTerminated; break; + case eInvalid: + default: state = osThreadError; break; + } + } + + return (state); +} + +PRIVILEGED_FUNCTION uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t sz; + + if (IS_IRQ() || (hTask == NULL)) { + sz = 0U; + } else { + sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t)); + } + + return (sz); +} + +PRIVILEGED_FUNCTION osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskPrioritySet (hTask, (UBaseType_t)priority); + } + + return (stat); +} + +PRIVILEGED_FUNCTION osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osPriority_t prio; + + if (IS_IRQ() || (hTask == NULL)) { + prio = osPriorityError; + } else { + prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask)); + } + + return (prio); +} + +PRIVILEGED_FUNCTION osStatus_t osThreadYield (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else { + stat = osOK; + taskYIELD(); + } + + return (stat); +} + +#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) +PRIVILEGED_FUNCTION osStatus_t osThreadSuspend (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskSuspend (hTask); + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osThreadResume (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskResume (hTask); + } + + return (stat); +} +#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */ + +PRIVILEGED_FUNCTION __NO_RETURN void osThreadExit (void) { +#ifndef USE_FreeRTOS_HEAP_1 + vTaskDelete (NULL); +#endif + for (;;); +} + +PRIVILEGED_FUNCTION osStatus_t osThreadTerminate (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + eTaskState tstate; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + tstate = eTaskGetState (hTask); + + if (tstate != eDeleted) { + stat = osOK; + vTaskDelete (hTask); + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} + +PRIVILEGED_FUNCTION uint32_t osThreadGetCount (void) { + uint32_t count; + + if (IS_IRQ()) { + count = 0U; + } else { + count = uxTaskGetNumberOfTasks(); + } + + return (count); +} + +#if (configUSE_OS2_THREAD_ENUMERATE == 1) +PRIVILEGED_FUNCTION uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + uint32_t i, count; + TaskStatus_t *task; + + if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) { + count = 0U; + } else { + vTaskSuspendAll(); + + count = uxTaskGetNumberOfTasks(); + task = pvPortMalloc (count * sizeof(TaskStatus_t)); + + if (task != NULL) { + count = uxTaskGetSystemState (task, count, NULL); + + for (i = 0U; (i < count) && (i < array_items); i++) { + thread_array[i] = (osThreadId_t)task[i].xHandle; + } + count = i; + } + (void)xTaskResumeAll(); + + vPortFree (task); + } + + return (count); +} +#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */ + +#if (configUSE_OS2_THREAD_FLAGS == 1) +PRIVILEGED_FUNCTION uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t rflags; + BaseType_t yield; + + if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else { + rflags = (uint32_t)osError; + + if (IS_IRQ()) { + yield = pdFALSE; + + (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); + (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); + + portYIELD_FROM_ISR (yield); + } + else { + (void)xTaskNotify (hTask, flags, eSetBits); + (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); + } + } + /* Return flags after setting */ + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osThreadFlagsClear (uint32_t flags) { + TaskHandle_t hTask; + uint32_t rflags, cflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) { + rflags = cflags; + cflags &= ~flags; + + if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) { + rflags = (uint32_t)osError; + } + } + else { + rflags = (uint32_t)osError; + } + } + + /* Return flags before clearing */ + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osThreadFlagsGet (void) { + TaskHandle_t hTask; + uint32_t rflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) { + rflags = (uint32_t)osError; + } + } + + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t rflags, nval; + uint32_t clear; + TickType_t t0, td, tout; + BaseType_t rval; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + if ((options & osFlagsNoClear) == osFlagsNoClear) { + clear = 0U; + } else { + clear = flags; + } + + rflags = 0U; + tout = timeout; + + t0 = xTaskGetTickCount(); + do { + rval = xTaskNotifyWait (0, clear, &nval, tout); + + if (rval == pdPASS) { + rflags &= flags; + rflags |= nval; + + if ((options & osFlagsWaitAll) == osFlagsWaitAll) { + if ((flags & rflags) == flags) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + else { + if ((flags & rflags) != 0) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + + /* Update timeout */ + td = xTaskGetTickCount() - t0; + + if (td > tout) { + tout = 0; + } else { + tout -= td; + } + } + else { + if (timeout == 0) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = (uint32_t)osErrorTimeout; + } + } + } + while (rval != pdFAIL); + } + + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +PRIVILEGED_FUNCTION osStatus_t osDelay (uint32_t ticks) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + + if (ticks != 0U) { + vTaskDelay(ticks); + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osDelayUntil (uint32_t ticks) { + TickType_t tcnt, delay; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + tcnt = xTaskGetTickCount(); + + /* Determine remaining number of ticks to delay */ + delay = (TickType_t)ticks - tcnt; + + /* Check if target tick has not expired */ + if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) { + vTaskDelayUntil (&tcnt, delay); + } + else + { + /* No delay or already expired */ + stat = osErrorParameter; + } + } + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_TIMER == 1) + +PRIVILEGED_FUNCTION static void TimerCallback (TimerHandle_t hTimer) { + TimerCallback_t *callb; + + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (callb != NULL) { + callb->func (callb->arg); + } +} + +PRIVILEGED_FUNCTION osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + const char *name; + TimerHandle_t hTimer; + TimerCallback_t *callb; + UBaseType_t reload; + int32_t mem; + + hTimer = NULL; + + if (!IS_IRQ() && (func != NULL)) { + /* Allocate memory to store callback function and argument */ + callb = pvPortMalloc (sizeof(TimerCallback_t)); + + if (callb != NULL) { + callb->func = func; + callb->arg = argument; + + if (type == osTimerOnce) { + reload = pdFALSE; + } else { + reload = pdTRUE; + } + + mem = -1; + name = NULL; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); + #endif + } + } + + if ((hTimer == NULL) && (callb != NULL)) { + vPortFree (callb); + } + } + } + + return ((osTimerId_t)hTimer); +} + +PRIVILEGED_FUNCTION const char *osTimerGetName (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + const char *p; + + if (IS_IRQ() || (hTimer == NULL)) { + p = NULL; + } else { + p = pcTimerGetName (hTimer); + } + + return (p); +} + +PRIVILEGED_FUNCTION osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { + stat = osOK; + } else { + stat = osErrorResource; + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osTimerStop (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerIsTimerActive (hTimer) == pdFALSE) { + stat = osErrorResource; + } + else { + if (xTimerStop (hTimer, 0) == pdPASS) { + stat = osOK; + } else { + stat = osError; + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION uint32_t osTimerIsRunning (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + uint32_t running; + + if (IS_IRQ() || (hTimer == NULL)) { + running = 0U; + } else { + running = (uint32_t)xTimerIsTimerActive (hTimer); + } + + return (running); +} + +PRIVILEGED_FUNCTION osStatus_t osTimerDelete (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + TimerCallback_t *callb; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (xTimerDelete (hTimer, 0) == pdPASS) { + vPortFree (callb); + stat = osOK; + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_TIMER == 1) */ + +/*---------------------------------------------------------------------------*/ + +PRIVILEGED_FUNCTION osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + EventGroupHandle_t hEventGroup; + int32_t mem; + + hEventGroup = NULL; + + if (!IS_IRQ()) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreateStatic (attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreate(); + #endif + } + } + } + + return ((osEventFlagsId_t)hEventGroup); +} + +PRIVILEGED_FUNCTION uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + BaseType_t yield; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + (void)yield; + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + yield = pdFALSE; + + if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = flags; + portYIELD_FROM_ISR (yield); + } + #endif + } + else { + rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + rflags = xEventGroupGetBitsFromISR (hEventGroup); + + if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } + #endif + } + else { + rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if (ef_id == NULL) { + rflags = 0U; + } + else if (IS_IRQ()) { + rflags = xEventGroupGetBitsFromISR (hEventGroup); + } + else { + rflags = xEventGroupGetBits (hEventGroup); + } + + return (rflags); +} + +PRIVILEGED_FUNCTION uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + BaseType_t wait_all; + BaseType_t exit_clr; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + if (options & osFlagsWaitAll) { + wait_all = pdTRUE; + } else { + wait_all = pdFAIL; + } + + if (options & osFlagsNoClear) { + exit_clr = pdFAIL; + } else { + exit_clr = pdTRUE; + } + + rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout); + + if (options & osFlagsWaitAll) { + if ((flags & rflags) != flags) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + else { + if ((flags & rflags) == 0U) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + } + + return (rflags); +} + +PRIVILEGED_FUNCTION osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hEventGroup == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vEventGroupDelete (hEventGroup); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_MUTEX == 1) + +PRIVILEGED_FUNCTION osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + SemaphoreHandle_t hMutex; + uint32_t type; + uint32_t rmtx; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hMutex = NULL; + + if (!IS_IRQ()) { + if (attr != NULL) { + type = attr->attr_bits; + } else { + type = 0U; + } + + if ((type & osMutexRecursive) == osMutexRecursive) { + rmtx = 1U; + } else { + rmtx = 0U; + } + + if ((type & osMutexRobust) != osMutexRobust) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); + #endif + } + else { + hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); + } + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutex (); + #endif + } else { + hMutex = xSemaphoreCreateMutex (); + } + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hMutex != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hMutex, name); + } + #endif + + if ((hMutex != NULL) && (rmtx != 0U)) { + hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); + } + } + } + + return ((osMutexId_t)hMutex); +} + +PRIVILEGED_FUNCTION osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + #endif + } + else { + if (xSemaphoreTake (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osMutexRelease (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { + stat = osErrorResource; + } + #endif + } + else { + if (xSemaphoreGive (hMutex) != pdPASS) { + stat = osErrorResource; + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osThreadId_t owner; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (hMutex == NULL) { + owner = NULL; + } else if (IS_IRQ()) { + owner = (osThreadId_t)xSemaphoreGetMutexHolderFromISR (hMutex); + } else { + owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex); + } + + return (owner); +} + +PRIVILEGED_FUNCTION osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + SemaphoreHandle_t hMutex; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hMutex); + #endif + stat = osOK; + vSemaphoreDelete (hMutex); + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_MUTEX == 1) */ + +/*---------------------------------------------------------------------------*/ + +PRIVILEGED_FUNCTION osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + SemaphoreHandle_t hSemaphore; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hSemaphore = NULL; + + if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem != -1) { + if (max_count == 1U) { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinary(); + #endif + } + + if ((hSemaphore != NULL) && (initial_count != 0U)) { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + vSemaphoreDelete (hSemaphore); + hSemaphore = NULL; + } + } + } + else { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hSemaphore != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hSemaphore, name); + } + #endif + } + } + + return ((osSemaphoreId_t)hSemaphore); +} + +PRIVILEGED_FUNCTION osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + if (timeout != 0U) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + yield = pdFALSE; + + if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + else { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + stat = osErrorResource; + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + uint32_t count; + + if (hSemaphore == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hSemaphore); + } else { + count = (uint32_t)uxSemaphoreGetCount (hSemaphore); + } + + return (count); +} + +PRIVILEGED_FUNCTION osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hSemaphore); + #endif + + stat = osOK; + vSemaphoreDelete (hSemaphore); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ + +PRIVILEGED_FUNCTION osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + QueueHandle_t hQueue; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hQueue = NULL; + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hQueue, name); + } + #endif + + } + + return ((osMessageQueueId_t)hQueue); +} + +PRIVILEGED_FUNCTION osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t capacity; + + if (mq == NULL) { + capacity = 0U; + } else { + /* capacity = pxQueue->uxLength */ + capacity = mq->uxDummy4[1]; + } + + return (capacity); +} + +PRIVILEGED_FUNCTION uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t size; + + if (mq == NULL) { + size = 0U; + } else { + /* size = pxQueue->uxItemSize */ + size = mq->uxDummy4[2]; + } + + return (size); +} + +PRIVILEGED_FUNCTION uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hQueue); + } + else { + count = uxQueueMessagesWaiting (hQueue); + } + + return ((uint32_t)count); +} + +PRIVILEGED_FUNCTION uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } + else if (IS_IRQ()) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + else { + space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq); + } + + return (space); +} + +PRIVILEGED_FUNCTION osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + (void)xQueueReset (hQueue); + } + + return (stat); +} + +PRIVILEGED_FUNCTION osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hQueue); + #endif + + stat = osOK; + vQueueDelete (hQueue); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#ifdef FREERTOS_MPOOL_H_ + +/* Static memory pool functions */ +static void FreeBlock (MemPool_t *mp, void *block); +static void *AllocBlock (MemPool_t *mp); +static void *CreateBlock (MemPool_t *mp); + +PRIVILEGED_FUNCTION osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + MemPool_t *mp; + const char *name; + int32_t mem_cb, mem_mp; + uint32_t sz; + + if (IS_IRQ()) { + mp = NULL; + } + else if ((block_count == 0U) || (block_size == 0U)) { + mp = NULL; + } + else { + mp = NULL; + sz = MEMPOOL_ARR_SIZE (block_count, block_size); + + name = NULL; + mem_cb = -1; + mem_mp = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) { + /* Static control block is provided */ + mem_cb = 1; + } + else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + /* Allocate control block memory on heap */ + mem_cb = 0; + } + + if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) { + /* Allocate memory array on heap */ + mem_mp = 0; + } + else { + if (attr->mp_mem != NULL) { + /* Check if array is 4-byte aligned */ + if (((uint32_t)attr->mp_mem & 3U) == 0U) { + /* Check if array big enough */ + if (attr->mp_size >= sz) { + /* Static memory pool array is provided */ + mem_mp = 1; + } + } + } + } + } + else { + /* Attributes not provided, allocate memory on heap */ + mem_cb = 0; + mem_mp = 0; + } + + if (mem_cb == 0) { + mp = pvPortMalloc (sizeof(MemPool_t)); + } else { + mp = attr->cb_mem; + } + + if (mp != NULL) { + /* Create a semaphore (max count == initial count == block_count) */ + #if (configSUPPORT_STATIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem); + #elif (configSUPPORT_DYNAMIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCounting (block_count, block_count); + #else + mp->sem == NULL; + #endif + + if (mp->sem != NULL) { + /* Setup memory array */ + if (mem_mp == 0) { + mp->mem_arr = pvPortMalloc (sz); + } else { + mp->mem_arr = attr->mp_mem; + } + } + } + + if ((mp != NULL) && (mp->mem_arr != NULL)) { + /* Memory pool can be created */ + mp->head = NULL; + mp->mem_sz = sz; + mp->name = name; + mp->bl_sz = block_size; + mp->bl_cnt = block_count; + mp->n = 0U; + + /* Set heap allocated memory flags */ + mp->status = MPOOL_STATUS; + + if (mem_cb == 0) { + /* Control block on heap */ + mp->status |= 1U; + } + if (mem_mp == 0) { + /* Memory array on heap */ + mp->status |= 2U; + } + } + else { + /* Memory pool cannot be created, release allocated resources */ + if ((mem_cb == 0) && (mp != NULL)) { + /* Free control block memory */ + vPortFree (mp); + } + mp = NULL; + } + } + + return (mp); +} + +PRIVILEGED_FUNCTION const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { + MemPool_t *mp = (osMemoryPoolId_t)mp_id; + const char *p; + + if (IS_IRQ()) { + p = NULL; + } + else if (mp_id == NULL) { + p = NULL; + } + else { + p = mp->name; + } + + return (p); +} + +PRIVILEGED_FUNCTION void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + MemPool_t *mp; + void *block; + uint32_t isrm; + + if (mp_id == NULL) { + /* Invalid input parameters */ + block = NULL; + } + else { + block = NULL; + + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + if (IS_IRQ()) { + if (timeout == 0U) { + if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + } + } + } + else { + if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + taskENTER_CRITICAL(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL(); + } + } + } + } + } + + return (block); +} + +PRIVILEGED_FUNCTION osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + MemPool_t *mp; + osStatus_t stat; + uint32_t isrm; + BaseType_t yield; + + if ((mp_id == NULL) || (block == NULL)) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + stat = osErrorResource; + } + else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) { + /* Block pointer outside of memory array area */ + stat = osErrorParameter; + } + else { + stat = osOK; + + if (IS_IRQ()) { + if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL_FROM_ISR(isrm); + + yield = pdFALSE; + xSemaphoreGiveFromISR (mp->sem, &yield); + portYIELD_FROM_ISR (yield); + } + } + else { + if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + taskENTER_CRITICAL(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL(); + + xSemaphoreGive (mp->sem); + } + } + } + } + + return (stat); +} + +PRIVILEGED_FUNCTION uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + n = mp->bl_cnt; + } + } + + /* Return maximum number of memory blocks */ + return (n); +} + +PRIVILEGED_FUNCTION uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t sz; + + if (mp_id == NULL) { + /* Invalid input parameters */ + sz = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + sz = 0U; + } + else { + sz = mp->bl_sz; + } + } + + /* Return memory block size in bytes */ + return (sz); +} + +PRIVILEGED_FUNCTION uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + + n = mp->bl_cnt - n; + } + } + + /* Return number of memory blocks used */ + return (n); +} + +PRIVILEGED_FUNCTION uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + } + } + + /* Return number of memory blocks available */ + return (n); +} + +PRIVILEGED_FUNCTION osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + osStatus_t stat; + + if (mp_id == NULL) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else if (IS_IRQ()) { + stat = osErrorISR; + } + else { + mp = (MemPool_t *)mp_id; + + taskENTER_CRITICAL(); + + /* Invalidate control block status */ + mp->status = mp->status & 3U; + + /* Wake-up tasks waiting for pool semaphore */ + while (xSemaphoreGive (mp->sem) == pdTRUE); + + mp->head = NULL; + mp->bl_sz = 0U; + mp->bl_cnt = 0U; + + if ((mp->status & 2U) != 0U) { + /* Memory pool array allocated on heap */ + vPortFree (mp->mem_arr); + } + if ((mp->status & 1U) != 0U) { + /* Memory pool control block allocated on heap */ + vPortFree (mp); + } + + taskEXIT_CRITICAL(); + + stat = osOK; + } + + return (stat); +} + +/* + Create new block given according to the current block index. +*/ +PRIVILEGED_FUNCTION static void *CreateBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->n < mp->bl_cnt) { + /* Unallocated blocks exist, set pointer to new block */ + p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n)); + + /* Increment block index */ + mp->n += 1U; + } + + return (p); +} + +/* + Allocate a block by reading the list of free blocks. +*/ +PRIVILEGED_FUNCTION static void *AllocBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->head != NULL) { + /* List of free block exists, get head block */ + p = mp->head; + + /* Head block is now next on the list */ + mp->head = p->next; + } + + return (p); +} + +/* + Free block by putting it to the list of free blocks. +*/ +PRIVILEGED_FUNCTION static void FreeBlock (MemPool_t *mp, void *block) { + MemPoolBlock_t *p = block; + + /* Store current head into block memory space */ + p->next = mp->head; + + /* Store current block as new head */ + mp->head = p; +} +#endif /* FREERTOS_MPOOL_H_ */ +/*---------------------------------------------------------------------------*/ + +/* Callback function prototypes */ +extern void vApplicationIdleHook (void) PRIVILEGED_FUNCTION; +extern void vApplicationTickHook (void) PRIVILEGED_FUNCTION; +extern void vApplicationMallocFailedHook (void) PRIVILEGED_FUNCTION; +extern void vApplicationDaemonTaskStartupHook (void) PRIVILEGED_FUNCTION; +extern void vApplicationStackOverflowHook (TaskHandle_t xTask, char *pcTaskName) PRIVILEGED_FUNCTION; + +/** + Dummy implementation of the callback function vApplicationIdleHook(). +*/ +#if (configUSE_IDLE_HOOK == 1) +__WEAK void vApplicationIdleHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationTickHook(). +*/ +#if (configUSE_TICK_HOOK == 1) + __WEAK void vApplicationTickHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationMallocFailedHook(). +*/ +#if (configUSE_MALLOC_FAILED_HOOK == 1) +__WEAK void vApplicationMallocFailedHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationDaemonTaskStartupHook(). +*/ +#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1) +__WEAK void vApplicationDaemonTaskStartupHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationStackOverflowHook(). +*/ +#if (configCHECK_FOR_STACK_OVERFLOW > 0) +__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, char *pcTaskName) { + (void)xTask; + (void)pcTaskName; + configASSERT(0); +} +#endif + +/*---------------------------------------------------------------------------*/ +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* External Idle and Timer task static memory allocation functions */ +extern void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) PRIVILEGED_FUNCTION; +extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) PRIVILEGED_FUNCTION; + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; +} + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; +} +#endif diff --git a/Libs/FreeRTOS/kernel/croutine.c b/Libs/FreeRTOS/kernel/croutine.c new file mode 100644 index 0000000..500641d --- /dev/null +++ b/Libs/FreeRTOS/kernel/croutine.c @@ -0,0 +1,374 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if ( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ + #ifdef portREMOVE_STATIC_QUALIFIER + #define static + #endif + + +/* Lists for ready and blocked co-routines. --------------------*/ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ + CRCB_t * pxCurrentCoRoutine = NULL; + static UBaseType_t uxTopCoRoutineReadyPriority = 0; + static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ + #define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ + #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ + { \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ + } + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ + static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ + static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ + static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ) + { + BaseType_t xReturn; + CRCB_t * pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + * be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + * This is so we can get back to the containing CRCB from a generic item + * in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + * list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ) + { + TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + * not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + * ourselves to the blocked list as the same list item is used for + * both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + * overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + * current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + * function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckPendingReadyList( void ) + { + /* Are there any co-routines waiting to get moved to the ready list? These + * are co-routines that have been readied by an ISR. The ISR cannot access + * the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t * pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckDelayedList( void ) + { + CRCB_t * pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + * any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineSchedule( void ) + { + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been + * called. prvInitialiseCoRoutineLists() is called automatically when a + * co-routine is created. */ + if( pxDelayedCoRoutineList != NULL ) + { + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + * of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + } + } +/*-----------------------------------------------------------*/ + + static void prvInitialiseCoRoutineLists( void ) + { + UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + * pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; + } +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ) + { + CRCB_t * pxUnblockedCRCB; + BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + * event lists and the pending ready list. This function assumes that a + * check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES == 0 */ diff --git a/Libs/FreeRTOS/kernel/event_groups.c b/Libs/FreeRTOS/kernel/event_groups.c new file mode 100644 index 0000000..1242686 --- /dev/null +++ b/Libs/FreeRTOS/kernel/event_groups.c @@ -0,0 +1,784 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list + * item value. It is important they don't clash with the + * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) + { + EventGroup_t * pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticEventGroup_t equals the size of the real + * event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + * this event group was created statically in case the event group + * is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + * pxEventGroupBuffer pointing to a pre-allocated (compile time + * allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t * pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + * follows: pvPortMalloc() always ensures returned memory blocks are + * aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the EventGroup_t structure - which (if you + * follow it through) is the alignment requirements of the TickType_t type + * (EventBits_t being of TickType_t itself). Therefore, whenever the + * stack alignment requirements are greater than or equal to the + * TickType_t alignment requirements the cast is safe. In other cases, + * where the natural word size of the architecture is less than + * sizeof( TickType_t ), the TickType_t variables will be accessed in two + * or more reads operations, and the alignment requirements is only that + * of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + * event group was allocated statically in case the event group is + * later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) +{ + EventBits_t uxOriginalBitValue, uxReturn; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + * already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + * the task unblocks, but some compilers mistakenly generate a + * warning about uxReturn being returned without being set if the + * assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + * specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + * bits it was waiting for were set, it is possible that since it + * unblocked another task has set the bits. If this is the case + * then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + * returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn, uxControlBits = 0; + BaseType_t xWaitConditionMet, xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + * itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + * block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + * specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + * set. uxControlBits are used to remember the specified behaviour of + * this call to xEventGroupWaitBits() - for use when the event bits + * unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + * some compilers mistakenly generate a warning about the variable + * being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + * task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + * cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ + UBaseType_t uxSavedInterruptStatus; + EventGroup_t const * const pxEventBits = xEventGroup; + EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) +{ + ListItem_t * pxListItem, * pxNext; + ListItem_t const * pxListEnd; + List_t const * pxList; + EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + * item before removing the task from the event list. The + * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + * that is was unblocked due to its required bits matching, rather + * than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + * used here as the list item may have been removed from the event list + * and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + * bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ + EventGroup_t * pxEventBits = xEventGroup; + const List_t * pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + * and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + * it again. */ + vPortFree( pxEventBits ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + * dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from + * an interrupt. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from + * an interrupt. */ +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) +{ + BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + * set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + * Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/Libs/FreeRTOS/kernel/include/FreeRTOS.h b/Libs/FreeRTOS/kernel/include/FreeRTOS.h new file mode 100644 index 0000000..277186a --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/FreeRTOS.h @@ -0,0 +1,1358 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + #if ( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * know. The StaticStreamBuffer_t structure below is provided for this purpose. + * Its size and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/Libs/FreeRTOS/kernel/include/StackMacros.h b/Libs/FreeRTOS/kernel/include/StackMacros.h new file mode 100644 index 0000000..03731b7 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/StackMacros.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +#include "stack_macros.h" diff --git a/Libs/FreeRTOS/kernel/include/atomic.h b/Libs/FreeRTOS/kernel/include/atomic.h new file mode 100644 index 0000000..f6629b4 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/atomic.h @@ -0,0 +1,432 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + + + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + +/* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + +/* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ + uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ + void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ + uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ATOMIC_H */ diff --git a/Libs/FreeRTOS/kernel/include/croutine.h b/Libs/FreeRTOS/kernel/include/croutine.h new file mode 100644 index 0000000..1af45c8 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/croutine.h @@ -0,0 +1,764 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Used to hide the implementation of the co-routine control block. The + * control block structure however has to be included in the header due to + * the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t, + UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + * 
+ * BaseType_t xCoRoutineCreate(
+ *                               crCOROUTINE_CODE pxCoRoutineCode,
+ *                               UBaseType_t uxPriority,
+ *                               UBaseType_t uxIndex
+ *                             ); 
+ *
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * static const char cLedToFlash[ 2 ] = { 5, 6 };
+ * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // This co-routine just delays for a fixed period, then toggles
+ *       // an LED.  Two co-routines are created using this function, so
+ *       // the uxIndex parameter is used to tell the co-routine which
+ *       // LED to flash and how int32_t to delay.  This assumes xQueue has
+ *       // already been created.
+ *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * // Function that creates two co-routines.
+ * void vOtherFunction( void )
+ * {
+ * uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle;
+ *
+ *   // Create two co-routines at priority 0.  The first is given index 0
+ *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
+ *   // is given index 1 so toggles LED 6 every 400 ticks.
+ *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ *   {
+ *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ *   }
+ * }
+ *
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ); + + +/** + * croutine. h + * 
+ * void vCoRoutineSchedule( void );
+ *
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + * 
+ * // This idle task hook will schedule a co-routine each time it is called.
+ * // The rest of the idle task will execute between co-routine calls.
+ * void vApplicationIdleHook( void )
+ * {
+ *  vCoRoutineSchedule();
+ * }
+ *
+ * // Alternatively, if you do not require any other part of the idle task to
+ * // execute, the idle task hook can call vCoRoutineSchedule() within an
+ * // infinite loop.
+ * void vApplicationIdleHook( void )
+ * {
+ *  for( ;; )
+ *  {
+ *      vCoRoutineSchedule();
+ *  }
+ * }
+ *
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ * crSTART( CoRoutineHandle_t xHandle );
+ *
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) \ + switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \ + case 0: + +/** + * croutine. h + * 
+ * crEND();
+ *
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \ + case ( __LINE__ * 2 ): +#define crSET_STATE1( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \ + case ( ( __LINE__ * 2 ) + 1 ): + +/** + * croutine. h + * 
+ * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ *
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * // We are to delay for 200ms.
+ * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *      // Delay for 200ms.
+ *      crDELAY( xHandle, xDelayTime );
+ *
+ *      // Do something here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ * crQUEUE_SEND(
+ *                CoRoutineHandle_t xHandle,
+ *                QueueHandle_t pxQueue,
+ *                void *pvItemToQueue,
+ *                TickType_t xTicksToWait,
+ *                BaseType_t *pxResult
+ *           )
+ *
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + * 
+ * // Co-routine function that blocks for a fixed period then posts a number onto
+ * // a queue.
+ * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xNumberToPost = 0;
+ * static BaseType_t xResult;
+ *
+ *  // Co-routines must begin with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // This assumes the queue has already been created.
+ *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+ *
+ *      if( xResult != pdPASS )
+ *      {
+ *          // The message was not posted!
+ *      }
+ *
+ *      // Increment the number to be posted onto the queue.
+ *      xNumberToPost++;
+ *
+ *      // Delay for 100 ticks.
+ *      crDELAY( xHandle, 100 );
+ *  }
+ *
+ *  // Co-routines must end with a call to crEND().
+ *  crEND();
+ * }
+ *
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ + } + +/** + * croutine. h + * 
+ * crQUEUE_RECEIVE(
+ *                   CoRoutineHandle_t xHandle,
+ *                   QueueHandle_t pxQueue,
+ *                   void *pvBuffer,
+ *                   TickType_t xTicksToWait,
+ *                   BaseType_t *pxResult
+ *               )
+ *
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + * 
+ * // A co-routine receives the number of an LED to flash from a queue.  It
+ * // blocks on the queue until the number is received.
+ * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xResult;
+ * static UBaseType_t uxLEDToFlash;
+ *
+ *  // All co-routines must start with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // Wait for data to become available on the queue.
+ *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // We received the LED to flash - flash it!
+ *          vParTestToggleLED( uxLEDToFlash );
+ *      }
+ *  }
+ *
+ *  crEND();
+ * }
+ *
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ + } + +/** + * croutine. h + * 
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvItemToQueue,
+ *                          BaseType_t xCoRoutinePreviouslyWoken
+ *                     )
+ *
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + * 
+ * // A co-routine that blocks on a queue waiting for characters to be received.
+ * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * char cRxedChar;
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Wait for data to become available on the queue.  This assumes the
+ *       // queue xCommsRxQueue has already been created!
+ *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *       // Was a character received?
+ *       if( xResult == pdPASS )
+ *       {
+ *           // Process the character here.
+ *       }
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to send characters received on a serial port to
+ * // a co-routine.
+ * void vUART_ISR( void )
+ * {
+ * char cRxedChar;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   // We loop around reading characters until there are none left in the UART.
+ *   while( UART_RX_REG_NOT_EMPTY() )
+ *   {
+ *       // Obtain the character from the UART.
+ *       cRxedChar = UART_RX_REG;
+ *
+ *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+ *       // the first time around the loop.  If the post causes a co-routine
+ *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ *       // In this manner we can ensure that if more than one co-routine is
+ *       // blocked on the queue only one is woken by this ISR no matter how
+ *       // many characters are posted to the queue.
+ *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ *   }
+ * }
+ *
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \ + xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvBuffer,
+ *                          BaseType_t * pxCoRoutineWoken
+ *                     )
+ *
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + * 
+ * // A co-routine that posts a character to a queue then blocks for a fixed
+ * // period.  The character is incremented each time.
+ * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // cChar holds its value while this co-routine is blocked and must therefore
+ * // be declared static.
+ * static char cCharToTx = 'a';
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Send the next character to the queue.
+ *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+ *
+ *       if( xResult == pdPASS )
+ *       {
+ *           // The character was successfully posted to the queue.
+ *       }
+ *       else
+ *       {
+ *          // Could not post the character to the queue.
+ *       }
+ *
+ *       // Enable the UART Tx interrupt to cause an interrupt in this
+ *       // hypothetical UART.  The interrupt will obtain the character
+ *       // from the queue and send it.
+ *       ENABLE_RX_INTERRUPT();
+ *
+ *       // Increment to the next character then block for a fixed period.
+ *       // cCharToTx will maintain its value across the delay as it is
+ *       // declared static.
+ *       cCharToTx++;
+ *       if( cCharToTx > 'x' )
+ *       {
+ *          cCharToTx = 'a';
+ *       }
+ *       crDELAY( 100 );
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to receive characters to send on a UART.
+ * void vUART_ISR( void )
+ * {
+ * char cCharToTx;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   while( UART_TX_REG_EMPTY() )
+ *   {
+ *       // Are there any characters in the queue waiting to be sent?
+ *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ *       // is woken by the post - ensuring that only a single co-routine is
+ *       // woken no matter how many times we go around this loop.
+ *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ *       {
+ *           SEND_CHARACTER( cCharToTx );
+ *       }
+ *   }
+ * }
+ *
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \ + xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* CO_ROUTINE_H */ diff --git a/Libs/FreeRTOS/kernel/include/deprecated_definitions.h b/Libs/FreeRTOS/kernel/include/deprecated_definitions.h new file mode 100644 index 0000000..cb9edca --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/deprecated_definitions.h @@ -0,0 +1,292 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. The + * definitions below remain in the code for backward compatibility only. New + * projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ diff --git a/Libs/FreeRTOS/kernel/include/event_groups.h b/Libs/FreeRTOS/kernel/include/event_groups.h new file mode 100644 index 0000000..fc2aa47 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/event_groups.h @@ -0,0 +1,788 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + * 
+ * EventGroupHandle_t xEventGroupCreate( void );
+ *
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * 
+ *  // Declare a variable to hold the created event group.
+ *  EventGroupHandle_t xCreatedEventGroup;
+ *
+ *  // Attempt to create the event group.
+ *  xCreatedEventGroup = xEventGroupCreate();
+ *
+ *  // Was the event group created successfully?
+ *  if( xCreatedEventGroup == NULL )
+ *  {
+ *      // The event group was not created because there was insufficient
+ *      // FreeRTOS heap available.
+ *  }
+ *  else
+ *  {
+ *      // The event group was created.
+ *  }
+ *
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * 
+ * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ *
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * 
+ *  // StaticEventGroup_t is a publicly accessible structure that has the same
+ *  // size and alignment requirements as the real event group structure.  It is
+ *  // provided as a mechanism for applications to know the size of the event
+ *  // group (which is dependent on the architecture and configuration file
+ *  // settings) without breaking the strict data hiding policy by exposing the
+ *  // real event group internals.  This StaticEventGroup_t variable is passed
+ *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
+ *  // the event group's data structures
+ *  StaticEventGroup_t xEventGroupBuffer;
+ *
+ *  // Create the event group without dynamically allocating any memory.
+ *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ *
+ */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
+ *                                      const EventBits_t uxBitsToWaitFor,
+ *                                      const BaseType_t xClearOnExit,
+ *                                      const BaseType_t xWaitForAllBits,
+ *                                      const TickType_t xTicksToWait );
+ *
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ *      // the event group.  Clear the bits before exiting.
+ *      uxBits = xEventGroupWaitBits(
+ *                  xEventGroup,    // The event group being tested.
+ *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
+ *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
+ *                  pdFALSE,        // Don't wait for both bits, either bit will do.
+ *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // xEventGroupWaitBits() returned because both bits were set.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_0 was set.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_4 was set.
+ *      }
+ *      else
+ *      {
+ *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ *          // without either BIT_0 or BIT_4 becoming set.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ *
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupClearBits(
+ *                              xEventGroup,    // The event group being updated.
+ *                              BIT_0 | BIT_4 );// The bits being cleared.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ *          // called.  Both will now be clear (not set).
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 were set in the first place.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ *
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupClearBitsFromISR(
+ *                          xEventGroup,     // The event group being updated.
+ *                          BIT_0 | BIT_4 ); // The bits being set.
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // The message was posted successfully.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \ + xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ *
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupSetBits(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4 );// The bits being set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 remained set when the function returned.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 remained set when the function returned, but bit 4 was
+ *          // cleared.  It might be that bit 4 was cleared automatically as a
+ *          // task that was waiting for bit 4 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 remained set when the function returned, but bit 0 was
+ *          // cleared.  It might be that bit 0 was cleared automatically as a
+ *          // task that was waiting for bit 0 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
+ *          // was waiting for both of the bits to be set, and the bits were
+ *          // cleared as the task left the Blocked state.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken, xResult;
+ *
+ *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupSetBitsFromISR(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4   // The bits being set.
+ *                          &xHigherPriorityTaskWoken );
+ *
+ *      // Was the message posted successfully?
+ *      if( xResult == pdPASS )
+ *      {
+ *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *          // switch should be requested.  The macro used is port specific and
+ *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *          // refer to the documentation page for the port being used.
+ *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \ + xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
+ *                                  const EventBits_t uxBitsToSet,
+ *                                  const EventBits_t uxBitsToWaitFor,
+ *                                  TickType_t xTicksToWait );
+ *
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * 
+ * // Bits used by the three tasks.
+ #define TASK_0_BIT     ( 1 << 0 )
+ #define TASK_1_BIT     ( 1 << 1 )
+ #define TASK_2_BIT     ( 1 << 2 )
+ *
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+ *
+ * // Use an event group to synchronise three tasks.  It is assumed this event
+ * // group has already been created elsewhere.
+ * EventGroupHandle_t xEventBits;
+ *
+ * void vTask0( void *pvParameters )
+ * {
+ * EventBits_t uxReturn;
+ * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 0 in the event flag to note this task has reached the
+ *      // sync point.  The other two tasks will set the other two bits defined
+ *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+ *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+ *      // for this to happen.
+ *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+ *
+ *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ *      {
+ *          // All three tasks reached the synchronisation point before the call
+ *          // to xEventGroupSync() timed out.
+ *      }
+ *  }
+ * }
+ *
+ * void vTask1( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 1 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *   }
+ * }
+ *
+ * void vTask2( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 2 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *  }
+ * }
+ *
+ *
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ *
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ *
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ *
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* EVENT_GROUPS_H */ diff --git a/Libs/FreeRTOS/kernel/include/list.h b/Libs/FreeRTOS/kernel/include/list.h new file mode 100644 index 0000000..f956c15 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/list.h @@ -0,0 +1,430 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +#ifndef INC_FREERTOS_H + #error "FreeRTOS.h must be included before list.h" +#endif + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/Libs/FreeRTOS/kernel/include/message_buffer.h b/Libs/FreeRTOS/kernel/include/message_buffer.h new file mode 100644 index 0000000..ba64ec6 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/message_buffer.h @@ -0,0 +1,834 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * + * 
+ * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+ *
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: + * 
+ *
+ * void vAFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ * const size_t xMessageBufferSizeBytes = 100;
+ *
+ *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the message buffer structure and the messages themselves is allocated
+ *  // dynamically.  Each message added to the buffer consumes an additional 4
+ *  // bytes which are used to hold the lengh of the message.
+ *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+ *
+ *  if( xMessageBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // message buffer.
+ *  }
+ *  else
+ *  {
+ *      // The message buffer was created successfully and can now be used.
+ *  }
+ *
+ *
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * + * 
+ * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                uint8_t *pucMessageBufferStorageArea,
+ *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ *
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: + * 
+ *
+ * // Used to dimension the array used to hold the messages.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the messages within the message
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the message buffer structure.
+ * StaticMessageBuffer_t xMessageBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                               ucBufferStorage,
+ *                                               &xMessageBufferStruct );
+ *
+ *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ *  // reference the created message buffer in other message buffer API calls.
+ *
+ *  // Other code that uses the message buffer can go here.
+ * }
+ *
+ *
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ *                         const void *pvTxData,
+ *                         size_t xDataLengthBytes,
+ *                         TickType_t xTicksToWait );
+ *
+ * + * Sends a discrete message to the message buffer. The message can be any + * length that fits within the buffer's free space, and is copied into the + * buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param xTicksToWait The maximum amount of time the calling task should remain + * in the Blocked state to wait for enough space to become available in the + * message buffer, should the message buffer have insufficient space when + * xMessageBufferSend() is called. The calling task will never block if + * xTicksToWait is zero. The block time is specified in tick periods, so the + * absolute time it represents is dependent on the tick frequency. The macro + * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into + * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause + * the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The number of bytes written to the message buffer. If the call to + * xMessageBufferSend() times out before there was enough space to write the + * message into the message buffer then zero is returned. If the call did not + * time out then xDataLengthBytes is returned. + * + * Example use: + * 
+ * void vAFunction( MessageBufferHandle_t xMessageBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the message buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the message buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xMessageBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written.
+ *  }
+ *
+ *  // Send the string to the message buffer.  Return immediately if there is
+ *  // not enough space in the buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ * }
+ *
+ * \defgroup xMessageBufferSend xMessageBufferSend + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \ + xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                const void *pvTxData,
+ *                                size_t xDataLengthBytes,
+ *                                BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * Interrupt safe version of the API function that sends a discrete message to + * the message buffer. The message can be any length that fits within the + * buffer's free space, and is copied into the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for data. Calling + * xMessageBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xMessageBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the code example below for an example. + * + * @return The number of bytes actually written to the message buffer. If the + * message buffer didn't have enough free space for the message to be stored + * then 0 is returned, otherwise xDataLengthBytes is returned. + * + * Example use: + * 
+ * // A message buffer that has already been created.
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the message buffer.
+ *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ *                                          ( void * ) pcStringToSend,
+ *                                          strlen( pcStringToSend ),
+ *                                          &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ *                            void *pvRxData,
+ *                            size_t xBufferLengthBytes,
+ *                            TickType_t xTicksToWait );
+ *
+ * + * Receives a discrete message from a message buffer. Messages can be of + * variable length and are copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for a message, should the message buffer be empty. + * xMessageBufferReceive() will return immediately if xTicksToWait is zero and + * the message buffer is empty. The block time is specified in tick periods, so + * the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. If xMessageBufferReceive() times out before a message became available + * then zero is returned. If the length of the message is greater than + * xBufferLengthBytes then the message will be left in the message buffer and + * zero is returned. + * + * Example use: + * 
+ * void vAFunction( MessageBuffer_t xMessageBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive the next message from the message buffer.  Wait in the Blocked
+ *  // state (so not using any CPU processing time) for a maximum of 100ms for
+ *  // a message to become available.
+ *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ *                                          ( void * ) ucRxData,
+ *                                          sizeof( ucRxData ),
+ *                                          xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ * }
+ *
+ * \defgroup xMessageBufferReceive xMessageBufferReceive + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \ + xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) + + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                   void *pvRxData,
+ *                                   size_t xBufferLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * An interrupt safe version of the API function that receives a discrete + * message from a message buffer. Messages can be of variable length and are + * copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for space to become available. Calling + * xMessageBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. + * + * Example use: + * 
+ * // A message buffer that has already been created.
+ * MessageBuffer_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next message from the message buffer.
+ *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+ *
+ * + * Deletes a message buffer that was previously created using a call to + * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message + * buffer was created using dynamic memory (that is, by xMessageBufferCreate()), + * then the allocated memory is freed. + * + * A message buffer handle must not be used after the message buffer has been + * deleted. + * + * @param xMessageBuffer The handle of the message buffer to be deleted. + * + */ +#define vMessageBufferDelete( xMessageBuffer ) \ + vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * + * Tests to see if a message buffer is full. A message buffer is full if it + * cannot accept any more messages, of any size, until space is made available + * by a message being removed from the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is full then + * pdTRUE is returned. Otherwise pdFALSE is returned. + */ +#define xMessageBufferIsFull( xMessageBuffer ) \ + xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * + * Tests to see if a message buffer is empty (does not contain any messages). + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is empty then + * pdTRUE is returned. Otherwise pdFALSE is returned. + * + */ +#define xMessageBufferIsEmpty( xMessageBuffer ) \ + xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+ *
+ * + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferReset xMessageBufferReset + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReset( xMessageBuffer ) \ + xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer ) + + +/** + * message_buffer.h + * 
+ * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * Returns the number of bytes of free space in the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The number of bytes that can be written to the message buffer before + * the message buffer would be full. When a message is written to the message + * buffer an additional sizeof( size_t ) bytes are also written to store the + * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size + * of the largest message that can be written to the message buffer is 6 bytes. + * + * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSpaceAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + * 
+ * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) \ + xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * + * 
+ * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferSendCompletedFromISR(). If calling + * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferReceiveCompletedFromISR(). If calling + * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } /* extern "C" */ +#endif +/* *INDENT-ON* */ + +#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */ diff --git a/Libs/FreeRTOS/kernel/include/mpu_prototypes.h b/Libs/FreeRTOS/kernel/include/mpu_prototypes.h new file mode 100644 index 0000000..126cde9 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/mpu_prototypes.h @@ -0,0 +1,270 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +/* MPU versions of tasks.h API functions. */ +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint16_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of timers.h API functions. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of event_group.h API functions. */ +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; + + + +#endif /* MPU_PROTOTYPES_H */ diff --git a/Libs/FreeRTOS/kernel/include/mpu_wrappers.h b/Libs/FreeRTOS/kernel/include/mpu_wrappers.h new file mode 100644 index 0000000..b6e63ef --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/mpu_wrappers.h @@ -0,0 +1,200 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#ifdef portUSING_MPU_WRAPPERS + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard tasks.h API functions to the MPU equivalents. */ + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskGetHandle MPU_xTaskGetHandle + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueGenericReset MPU_xQueueGenericReset + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + #define xTimerGenericCommand MPU_xTimerGenericCommand + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + #define vEventGroupDelete MPU_vEventGroupDelete + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferReset MPU_xStreamBufferReset + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + + +/* Remove the privileged function macro, but keep the PRIVILEGED_DATA + * macro so applications can place data in privileged access sections + * (useful when using statically allocated objects). */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +/* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #include "sl_code_classification.h" + + #define PRIVILEGED_FUNCTION SL_CODE_CLASSIFY(SL_CODE_COMPONENT_FREERTOS_KERNEL, SL_CODE_CLASS_TIME_CRITICAL) + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + #define portUSING_MPU_WRAPPERS 0 + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/Libs/FreeRTOS/kernel/include/portable.h b/Libs/FreeRTOS/kernel/include/portable.h new file mode 100644 index 0000000..0c7d9cd --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/portable.h @@ -0,0 +1,229 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#endif + +#if portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#endif + +#if portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#endif + +#ifndef portBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/Libs/FreeRTOS/kernel/include/projdefs.h b/Libs/FreeRTOS/kernel/include/projdefs.h new file mode 100644 index 0000000..8e60f31 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/projdefs.h @@ -0,0 +1,133 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/Libs/FreeRTOS/kernel/include/queue.h b/Libs/FreeRTOS/kernel/include/queue.h new file mode 100644 index 0000000..ee5d352 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/queue.h @@ -0,0 +1,1729 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "task.h" + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * 
+ * QueueHandle_t xQueueCreate(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize
+ *                        );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *  if( xQueue1 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue2 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * 
+ * QueueHandle_t xQueueCreateStatic(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize,
+ *                            uint8_t *pucQueueStorageBuffer,
+ *                            StaticQueue_t *pxQueueBuffer
+ *                        );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorageBuffer If uxItemSize is not zero then + * pucQueueStorageBuffer must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorageBuffer can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+ *
+ * // xQueueBuffer will hold the queue structure.
+ * StaticQueue_t xQueueBuffer;
+ *
+ * // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ * // [(queue length) * ( queue item size)] bytes long.
+ * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+ *                          ITEM_SIZE     // The size of each item in the queue
+ *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+ *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
+ *
+ *  // The queue is guaranteed to be created successfully as no dynamic memory
+ *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToToFront(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ *
+ * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToBack(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSend(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            TickType_t xTicksToWait
+ *                       );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueOverwrite(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue
+ *                       );
+ *
+ * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + * 
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwrite() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ *
+ *  // Write the value 10 to the queue using xQueueOverwrite().
+ *  ulVarToSend = 10;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // Peeking the queue should now return 10, but leave the value 10 in
+ *  // the queue.  A block time of zero is used as it is known that the
+ *  // queue holds a value.
+ *  ulValReceived = 0;
+ *  xQueuePeek( xQueue, &ulValReceived, 0 );
+ *
+ *  if( ulValReceived != 10 )
+ *  {
+ *      // Error unless the item was removed by a different task.
+ *  }
+ *
+ *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
+ *  // value held in the queue with 100.
+ *  ulVarToSend = 100;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // This time read from the queue, leaving the queue empty once more.
+ *  // A block time of 0 is used again.
+ *  xQueueReceive( xQueue, &ulValReceived, 0 );
+ *
+ *  // The value read should be the last value written, even though the
+ *  // queue was already full when the value was written.
+ *  if( ulValReceived != 100 )
+ *  {
+ *      // Error!
+ *  }
+ *
+ *  // ...
+ * }
+ *
+ * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * 
+ * BaseType_t xQueueGenericSend(
+ *                                  QueueHandle_t xQueue,
+ *                                  const void * pvItemToQueue,
+ *                                  TickType_t xTicksToWait
+ *                                  BaseType_t xCopyPosition
+ *                              );
+ *
+ * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueuePeek(
+ *                           QueueHandle_t xQueue,
+ *                           void * const pvBuffer,
+ *                           TickType_t xTicksToWait
+ *                       );
+ *
+ * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to peek the data from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Peek a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask, but the item still remains on the queue.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueuePeekFromISR(
+ *                                  QueueHandle_t xQueue,
+ *                                  void *pvBuffer,
+ *                              );
+ *
+ * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueReceive(
+ *                               QueueHandle_t xQueue,
+ *                               void *pvBuffer,
+ *                               TickType_t xTicksToWait
+ *                          );
+ *
+ * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to receive from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Receive a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ *
+ * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ *
+ * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * void vQueueDelete( QueueHandle_t xQueue );
+ *
+ * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToFrontFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPrioritTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToBackFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueOverwriteFromISR(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            BaseType_t *pxHigherPriorityTaskWoken
+ *                       );
+ *
+ * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + * 
+ *
+ * QueueHandle_t xQueue;
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ * }
+ *
+ * void vAnInterruptHandler( void )
+ * {
+ * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ *  ulVarToSend = 10;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ *  // pass because the value held in the queue will be overwritten with the
+ *  // new value.
+ *  ulVarToSend = 100;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // Reading from the queue will now return 100.
+ *
+ *  // ...
+ *
+ *  if( xHigherPrioritytaskWoken == pdTRUE )
+ *  {
+ *      // Writing to the queue caused a task to unblock and the unblocked task
+ *      // has a priority higher than or equal to the priority of the currently
+ *      // executing task (the task this interrupt interrupted).  Perform a context
+ *      // switch so this interrupt returns directly to the unblocked task.
+ *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ *  }
+ * }
+ *
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSendFromISR(
+ *                                   QueueHandle_t xQueue,
+ *                                   const void *pvItemToQueue,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken
+ *                              );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      // Actual macro used here is port specific.
+ *      portYIELD_FROM_ISR ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueGenericSendFromISR(
+ *                                         QueueHandle_t    xQueue,
+ *                                         const    void    *pvItemToQueue,
+ *                                         BaseType_t  *pxHigherPriorityTaskWoken,
+ *                                         BaseType_t  xCopyPosition
+ *                                     );
+ *
+ * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWokenByPost;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWokenByPost = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post each byte.
+ *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.  Note that the
+ *  // name of the yield function required is port specific.
+ *  if( xHigherPriorityTaskWokenByPost )
+ *  {
+ *      portYIELD_FROM_ISR();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueReceiveFromISR(
+ *                                     QueueHandle_t    xQueue,
+ *                                     void             *pvBuffer,
+ *                                     BaseType_t       *pxTaskWoken
+ *                                 );
+ *
+ * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Function to create a queue and post some values.
+ * void vAFunction( void *pvParameters )
+ * {
+ * char cValueToPost;
+ * const TickType_t xTicksToWait = ( TickType_t )0xff;
+ *
+ *  // Create a queue capable of containing 10 characters.
+ *  xQueue = xQueueCreate( 10, sizeof( char ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Post some characters that will be used within an ISR.  If the queue
+ *  // is full then this task will block for xTicksToWait ticks.
+ *  cValueToPost = 'a';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *  cValueToPost = 'b';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *
+ *  // ... keep posting characters ... this task may block when the queue
+ *  // becomes full.
+ *
+ *  cValueToPost = 'c';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ * }
+ *
+ * // ISR that outputs all the characters received on the queue.
+ * void vISR_Routine( void )
+ * {
+ * BaseType_t xTaskWokenByReceive = pdFALSE;
+ * char cRxedChar;
+ *
+ *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ *  {
+ *      // A character was received.  Output the character now.
+ *      vOutputCharacter( cRxedChar );
+ *
+ *      // If removing the character from the queue woke the task that was
+ *      // posting onto the queue cTaskWokenByReceive will have been set to
+ *      // pdTRUE.  No matter how many times this loop iterates only one
+ *      // task will be woken.
+ *  }
+ *
+ *  if( cTaskWokenByPost != ( char ) pdFALSE;
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from witin an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not effect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* QUEUE_H */ diff --git a/Libs/FreeRTOS/kernel/include/semphr.h b/Libs/FreeRTOS/kernel/include/semphr.h new file mode 100644 index 0000000..727c1f4 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/semphr.h @@ -0,0 +1,1186 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * 
+ * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
+ *
+ * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ *  // This is a macro so pass the variable in directly.
+ *  vSemaphoreCreateBinary( xSemaphore );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateBinary( void );
+ *
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
+ *
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
+ *  // variable, the address of which is passed into the function.  The
+ *  // function's parameter is not NULL, so the function will not attempt any
+ *  // dynamic memory allocation, and therefore the function will not return
+ *  // return NULL.
+ *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+ *
+ *  // Rest of task code goes here.
+ * }
+ *
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               );
+ *
+ * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // A task that creates a semaphore.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ * }
+ *
+ * // A task that uses the semaphore.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // See if we can obtain the semaphore.  If the semaphore is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the semaphore and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource.  Release the
+ *          // semaphore.
+ *          xSemaphoreGive( xSemaphore );
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the semaphore and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * 
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        );
+ *
+ * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + * 
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, but instead buried in a more complex
+ *          // call structure.  This is just for illustrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * 
+ * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
+ *
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = vSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *      {
+ *          // We would expect this call to fail because we cannot give
+ *          // a semaphore without first "taking" it!
+ *      }
+ *
+ *      // Obtain the semaphore - don't block if the semaphore is not
+ *      // immediately available.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ *      {
+ *          // We now have the semaphore and can access the shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource so can free the
+ *          // semaphore.
+ *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *          {
+ *              // We would not expect this call to fail because we must have
+ *              // obtained the semaphore to get here.
+ *          }
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
+ * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
+ *
+ * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + * 
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, it would be more likely that the calls
+ *          // to xSemaphoreGiveRecursive() would be called as a call stack
+ *          // unwound.  This is just for demonstrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * 
+ * xSemaphoreGiveFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ *
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // Repetitive task.
+ * void vATask( void * pvParameters )
+ * {
+ *  for( ;; )
+ *  {
+ *      // We want this task to run every 10 ticks of a timer.  The semaphore
+ *      // was created before this task was started.
+ *
+ *      // Block waiting for the semaphore to become available.
+ *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ *      {
+ *          // It is time to execute.
+ *
+ *          // ...
+ *
+ *          // We have finished our task.  Return to the top of the loop where
+ *          // we will block on the semaphore until it is time to execute
+ *          // again.  Note when using the semaphore for synchronisation with an
+ *          // ISR in this manner there is no need to 'give' the semaphore back.
+ *      }
+ *  }
+ * }
+ *
+ * // Timer ISR
+ * void vTimerISR( void * pvParameters )
+ * {
+ * static uint8_t ucLocalTickCount = 0;
+ * static BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // A timer tick has occurred.
+ *
+ *  // ... Do other time functions.
+ *
+ *  // Is it time for vATask () to run?
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *  ucLocalTickCount++;
+ *  if( ucLocalTickCount >= TICKS_TO_WAIT )
+ *  {
+ *      // Unblock the task by releasing the semaphore.
+ *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+ *
+ *      // Reset the count so we release the semaphore again in 10 ticks time.
+ *      ucLocalTickCount = 0;
+ *  }
+ *
+ *  if( xHigherPriorityTaskWoken != pdFALSE )
+ *  {
+ *      // We can force a context switch here.  Context switching from an
+ *      // ISR uses port specific syntax.  Check the demo task for your port
+ *      // to find the syntax required.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ * xSemaphoreTakeFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ *
+ * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateMutex( void );
+ *
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ *
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A mutex cannot be used before it has been created.  xMutexBuffer is
+ *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ *
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
+ *
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ *
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A recursive semaphore cannot be used before it is created.  Here a
+ *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+ *  // The address of xMutexBuffer is passed into the function, and will hold
+ *  // the mutexes data structures - so no dynamic memory allocation will be
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ *
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
+ *
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ *  // The max value to which the semaphore can count should be 10, and the
+ *  // initial value assigned to the count should be 0.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
+ *
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Counting semaphore cannot be used before they have been created.  Create
+ *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+ *  // value to which the semaphore can count is 10, and the initial value
+ *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+ *  // passed in and will be used to hold the semaphore structure, so no dynamic
+ *  // memory allocation will be used.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+ *
+ *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+ *  // is no need to check its value.
+ * }
+ *
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ *
+ * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ *
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
+ *
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
+ *
+ * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ diff --git a/Libs/FreeRTOS/kernel/include/stack_macros.h b/Libs/FreeRTOS/kernel/include/stack_macros.h new file mode 100644 index 0000000..a9ff496 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/stack_macros.h @@ -0,0 +1,140 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ diff --git a/Libs/FreeRTOS/kernel/include/stream_buffer.h b/Libs/FreeRTOS/kernel/include/stream_buffer.h new file mode 100644 index 0000000..2c2dba7 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/stream_buffer.h @@ -0,0 +1,880 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Stream buffers are used to send a continuous stream of data from one task or + * interrupt to another. Their implementation is light weight, making them + * particularly suited for interrupt to task and core to core communication + * scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section section and set the + * receive block time to 0. + * + */ + +#ifndef STREAM_BUFFER_H +#define STREAM_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; + + +/** + * message_buffer.h + * + * 
+ * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ *
+ * + * Creates a new stream buffer using dynamically allocated memory. See + * xStreamBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes the stream buffer will be + * able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @return If NULL is returned, then the stream buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream buffer data structures and storage area. A non-NULL value being + * returned indicates that the stream buffer has been created successfully - + * the returned value should be stored as the handle to the created stream + * buffer. + * + * Example use: + * 
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the stream buffer structure and the data in the stream buffer is
+ *  // allocated dynamically.
+ *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream buffer was created successfully and can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferCreate xStreamBufferCreate + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE ) + +/** + * stream_buffer.h + * + * 
+ * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                              size_t xTriggerLevelBytes,
+ *                                              uint8_t *pucStreamBufferStorageArea,
+ *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ *
+ * Creates a new stream buffer using statically allocated memory. See + * xStreamBufferCreate() for a version that uses dynamically allocated memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBufferCreateStatic() to be available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which streams are + * copied when they are written to the stream buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream buffer's data + * structure. + * + * @return If the stream buffer is created successfully then a handle to the + * created stream buffer is returned. If either pucStreamBufferStorageArea or + * pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * 
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                             xTriggerLevel,
+ *                                             ucBufferStorage,
+ *                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ *  // reference the created stream buffer in other stream buffer API calls.
+ *
+ *  // Other code that uses the stream buffer can go here.
+ * }
+ *
+ *
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer ) + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ *                        const void *pvTxData,
+ *                        size_t xDataLengthBytes,
+ *                        TickType_t xTicksToWait );
+ *
+ * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * 
+ * void vAFunction( StreamBufferHandle_t xStreamBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the stream buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xStreamBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written, but it did
+ *      // successfully write xBytesSent bytes.
+ *  }
+ *
+ *  // Send the string to the stream buffer.  Return immediately if there is not
+ *  // enough space in the buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The entire string could not be added to the stream buffer because
+ *      // there was not enough free space in the buffer, but xBytesSent bytes
+ *      // were sent.  Could try again to send the remaining bytes.
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferSend xStreamBufferSend + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                               const void *pvTxData,
+ *                               size_t xDataLengthBytes,
+ *                               BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * 
+ * // A stream buffer that has already been created.
+ * StreamBufferHandle_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the stream buffer.
+ *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ *                                         ( void * ) pcStringToSend,
+ *                                         strlen( pcStringToSend ),
+ *                                         &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // There was not enough free space in the stream buffer for the entire
+ *      // string to be written, ut xBytesSent bytes were written.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ *                           void *pvRxData,
+ *                           size_t xBufferLengthBytes,
+ *                           TickType_t xTicksToWait );
+ *
+ * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * 
+ * void vAFunction( StreamBuffer_t xStreamBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ *  // Wait in the Blocked state (so not using any CPU processing time) for a
+ *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ *  // available.
+ *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ *                                         ( void * ) ucRxData,
+ *                                         sizeof( ucRxData ),
+ *                                         xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains another xRecievedBytes bytes of data, which can
+ *      // be processed here....
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferReceive xStreamBufferReceive + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                                  void *pvRxData,
+ *                                  size_t xBufferLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * 
+ * // A stream buffer that has already been created.
+ * StreamBuffer_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next stream from the stream buffer.
+ *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // ucRxData contains xReceivedBytes read from the stream buffer.
+ *      // Process the stream here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \defgroup vStreamBufferDelete vStreamBufferDelete + * \ingroup StreamBufferManagement + */ +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsFull xStreamBufferIsFull + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferReset xStreamBufferReset + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+ *
+ * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* Functions below here are not part of the public API. */ +StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION; + +StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION; + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } +#endif +/* *INDENT-ON* */ + +#endif /* !defined( STREAM_BUFFER_H ) */ diff --git a/Libs/FreeRTOS/kernel/include/task.h b/Libs/FreeRTOS/kernel/include/task.h new file mode 100644 index 0000000..e10fd82 --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/task.h @@ -0,0 +1,3066 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +#define tskKERNEL_VERSION_NUMBER "V10.4.3" +#define tskKERNEL_VERSION_MAJOR 10 +#define tskKERNEL_VERSION_MINOR 4 +#define tskKERNEL_VERSION_BUILD 3 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) + +/* The direct to task notification feature used to have only a single notification + * per task. Now there is an array of notifications per task that is dimensioned by + * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the + * original direct to task notification defaults to using the first index in the + * array. */ +#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 ) + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock * TaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (* TaskHookFunction_t)( void * ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a read or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ + eInvalid /* Used as an 'invalid state' value. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void * pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + configSTACK_DEPTH_TYPE usStackDepth; + void * pvParameters; + UBaseType_t uxPriority; + StackType_t * puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; + #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + StaticTask_t * const pxTaskBuffer; + #endif +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + UBaseType_t xTaskNumber; /* A number unique to the task. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */ + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ +} eSleepModeStatus; + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is + * 0 to generate more optimal code when configASSERT() is defined as the constant + * is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + + +/*----------------------------------------------------------- +* TASK CREATION API +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * BaseType_t xTaskCreate(
+ *                            TaskFunction_t pvTaskCode,
+ *                            const char * const pcName,
+ *                            configSTACK_DEPTH_TYPE usStackDepth,
+ *                            void *pvParameters,
+ *                            UBaseType_t uxPriority,
+ *                            TaskHandle_t *pvCreatedTask
+ *                        );
+ *
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * See xTaskCreateStatic() for a version that does not use any dynamic memory + * allocation. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pvCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Task to be created.
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *   }
+ * }
+ *
+ * // Function that creates a task.
+ * void vOtherFunction( void )
+ * {
+ * static uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle = NULL;
+ *
+ *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+ *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+ *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ *   // the new task attempts to access it.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ *   configASSERT( xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   if( xHandle != NULL )
+ *   {
+ *      vTaskDelete( xHandle );
+ *   }
+ * }
+ *
+ * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+ *                               const char * const pcName,
+ *                               uint32_t ulStackDepth,
+ *                               void *pvParameters,
+ *                               UBaseType_t uxPriority,
+ *                               StackType_t *pxStackBuffer,
+ *                               StaticTask_t *pxTaskBuffer );
+ *
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. The maximum length of the string is defined by + * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h. + * + * @param ulStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task will run. + * + * @param pxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes - the array will then be used as the task's stack, + * removing the need for the stack to be allocated dynamically. + * + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, removing the need for the + * memory to be allocated dynamically. + * + * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will + * be created and a handle to the created task is returned. If either + * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. + * + * Example usage: + * 
+ *
+ *  // Dimensions the buffer that the task being created will use as its stack.
+ *  // NOTE:  This is the number of words the stack will hold, not the number of
+ *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+ *  // then 400 bytes (100 * 32-bits) will be allocated.
+ #define STACK_SIZE 200
+ *
+ *  // Structure that will hold the TCB of the task being created.
+ *  StaticTask_t xTaskBuffer;
+ *
+ *  // Buffer that the task being created will use as its stack.  Note this is
+ *  // an array of StackType_t variables.  The size of StackType_t is dependent on
+ *  // the RTOS port.
+ *  StackType_t xStack[ STACK_SIZE ];
+ *
+ *  // Function that implements the task being created.
+ *  void vTaskCode( void * pvParameters )
+ *  {
+ *      // The parameter value is expected to be 1 as 1 is passed in the
+ *      // pvParameters value in the call to xTaskCreateStatic().
+ *      configASSERT( ( uint32_t ) pvParameters == 1UL );
+ *
+ *      for( ;; )
+ *      {
+ *          // Task code goes here.
+ *      }
+ *  }
+ *
+ *  // Function that creates a task.
+ *  void vOtherFunction( void )
+ *  {
+ *      TaskHandle_t xHandle = NULL;
+ *
+ *      // Create the task without using any dynamic memory allocation.
+ *      xHandle = xTaskCreateStatic(
+ *                    vTaskCode,       // Function that implements the task.
+ *                    "NAME",          // Text name for the task.
+ *                    STACK_SIZE,      // Stack size in words, not bytes.
+ *                    ( void * ) 1,    // Parameter passed into the task.
+ *                    tskIDLE_PRIORITY,// Priority at which the task is created.
+ *                    xStack,          // Array to use as the task's stack.
+ *                    &xTaskBuffer );  // Variable to hold the task's data structure.
+ *
+ *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+ *      // been created, and xHandle will be the task's handle.  Use the handle
+ *      // to suspend the task.
+ *      vTaskSuspend( xHandle );
+ *  }
+ *
+ * \defgroup xTaskCreateStatic xTaskCreateStatic + * \ingroup Tasks + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * task. h + * 
+ * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ *
+ * + * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1. + * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * See xTaskCreateRestrictedStatic() for a version that does not use any + * dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ *
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ *
+ * + * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1. + * + * xTaskCreateRestrictedStatic() should only be used in systems that include an + * MPU implementation. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreateRestricted() then the stack is provided by the application writer, + * and the memory used to hold the task's data structure is automatically + * dynamically allocated inside the xTaskCreateRestricted() function. If a task + * is created using xTaskCreateRestrictedStatic() then the application writer + * must provide the memory used to hold the task's data structures too. + * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be + * created without using any dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure + * contains an additional member, which is used to point to a variable of type + * StaticTask_t - which is then used to hold the task's data structure. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * // The StaticTask_t variable is only included in the structure when
+ * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+ * // be used to force the variable into the RTOS kernel's privileged data area.
+ * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ *
+ *  &xTaskBuffer; // Holds the task's data structure.
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ *
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ *
+ * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param xRegions A pointer to an MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * 
+ * // Define an array of MemoryRegion_t structures that configures an MPU region
+ * // allowing read/write access for 1024 bytes starting at the beginning of the
+ * // ucOneKByte array.  The other two of the maximum 3 definable regions are
+ * // unused so set to zero.
+ * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+ * {
+ *  // Base address     Length      Parameters
+ *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
+ *  { 0,                0,          0 },
+ *  { 0,                0,          0 }
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ *  // This task was created such that it has access to certain regions of
+ *  // memory as defined by the MPU configuration.  At some point it is
+ *  // desired that these MPU regions are replaced with that defined in the
+ *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+ *  // for this purpose.  NULL is used as the task handle to indicate that this
+ *  // function should modify the MPU regions of the calling task.
+ *  vTaskAllocateMPURegions( NULL, xAltRegions );
+ *
+ *  // Now the task can continue its function, but from this point on can only
+ *  // access its stack and the ucOneKByte array (unless any other statically
+ *  // defined or shared regions have been declared elsewhere).
+ * }
+ *
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +void vTaskAllocateMPURegions( TaskHandle_t xTask, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskDelete( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTask The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * 
+ * void vOtherFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create the task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   vTaskDelete( xHandle );
+ * }
+ *
+ * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK CONTROL API +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * void vTaskDelay( const TickType_t xTicksToDelay );
+ *
+ * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will effect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ *
+ * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. + * + * Example usage: + * 
+ * // Perform an action every 10 ticks.
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * TickType_t xLastWakeTime;
+ * const TickType_t xFrequency = 10;
+ * BaseType_t xWasDelayed;
+ *
+ *     // Initialise the xLastWakeTime variable with the current time.
+ *     xLastWakeTime = xTaskGetTickCount ();
+ *     for( ;; )
+ *     {
+ *         // Wait for the next cycle.
+ *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
+ *
+ *         // Perform action here. xWasDelayed value can be used to determine
+ *         // whether a deadline was missed if the code here took too long.
+ *     }
+ * }
+ *
+ * \defgroup xTaskDelayUntil xTaskDelayUntil + * \ingroup TaskCtrl + */ +BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/* + * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not + * return a value. + */ +#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \ +{ \ + ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \ +} + + +/** + * task. h + * 
+ * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \defgroup xTaskAbortDelay xTaskAbortDelay + * \ingroup TaskCtrl + */ +BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
+ *
+ * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to obtain the priority of the created task.
+ *   // It was created with tskIDLE_PRIORITY, but may have changed
+ *   // it itself.
+ *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ *   {
+ *       // The task has changed it's priority.
+ *   }
+ *
+ *   // ...
+ *
+ *   // Is our priority higher than the created task?
+ *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ *   {
+ *       // Our priority (obtained using NULL handle) is higher.
+ *   }
+ * }
+ *
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
+ *
+ * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * eTaskState eTaskGetState( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+ *
+ * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * TaskStatus_t xTaskDetails;
+ *
+ *  // Obtain the handle of a task from its name.
+ *  xHandle = xTaskGetHandle( "Task_Name" );
+ *
+ *  // Check the handle is not NULL.
+ *  configASSERT( xHandle );
+ *
+ *  // Use the handle to obtain further information about the task.
+ *  vTaskGetInfo( xHandle,
+ *                &xTaskDetails,
+ *                pdTRUE, // Include the high water mark in xTaskDetails.
+ *                eInvalid ); // Include the task state in xTaskDetails.
+ * }
+ *
+ * \defgroup vTaskGetInfo vTaskGetInfo + * \ingroup TaskCtrl + */ +void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ *
+ * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to raise the priority of the created task.
+ *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+ *
+ *   // ...
+ *
+ *   // Use a NULL handle to raise our priority to the same value.
+ *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ * }
+ *
+ * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ *
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Suspend ourselves.
+ *   vTaskSuspend( NULL );
+ *
+ *   // We cannot get here unless another task calls vTaskResume
+ *   // with our handle as the parameter.
+ * }
+ *
+ * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskResume( TaskHandle_t xTaskToResume );
+ *
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Resume the suspended task ourselves.
+ *   vTaskResume( xHandle );
+ *
+ *   // The created task will once again get microcontroller processing
+ *   // time in accordance with its priority within the system.
+ * }
+ *
+ * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ *
+ * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* SCHEDULER CONTROL +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * void vTaskStartScheduler( void );
+ *
+ * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will not get here unless a task calls vTaskEndScheduler ()
+ * }
+ *
+ * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskEndScheduler( void );
+ *
+ * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * 
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // At some point we want to end the real time kernel processing
+ *       // so call ...
+ *       vTaskEndScheduler ();
+ *   }
+ * }
+ *
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will only get here when the vTaskCode () task has called
+ *   // vTaskEndScheduler ().  When we get here we are back to single task
+ *   // execution.
+ * }
+ *
+ * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskSuspendAll( void );
+ *
+ * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * 
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the kernel
+ *       // tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.
+ *       xTaskResumeAll ();
+ *   }
+ * }
+ *
+ * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * BaseType_t xTaskResumeAll( void );
+ *
+ * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * 
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the real
+ *       // time kernel tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.  We want to force
+ *       // a context switch - but there is no point if resuming the scheduler
+ *       // caused a context switch already.
+ *       if( !xTaskResumeAll () )
+ *       {
+ *            taskYIELD ();
+ *       }
+ *   }
+ * }
+ *
+ * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK UTILITIES +*----------------------------------------------------------*/ + +/** + * task. h + * 
TickType_t xTaskGetTickCount( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
TickType_t xTaskGetTickCountFromISR( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
uint16_t uxTaskGetNumberOfTasks( void );
+ * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );
+ * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \defgroup pcTaskGetName pcTaskGetName + * \ingroup TaskUtils + */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
+ * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \defgroup pcTaskGetHandle pcTaskGetHandle + * \ingroup TaskUtils + */ +TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task.h + * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* When using trace macros it is sometimes necessary to include task.h before + * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, + * so the following two prototypes will cause a compilation error. This can be + * fixed by simply guarding against the inclusion of these two prototypes unless + * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration + * constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + +/** + * task.h + * 
+ * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ *
+ * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ *
+ * + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
+ *
+ * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + +/* Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + + /** + * task.h + * 
void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName);
+ * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ + void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ); + +#endif + +#if ( configUSE_TICK_HOOK > 0 ) + /** + * task.h + * 
void vApplicationTickHook( void );
+ * + * This hook function is called in the system tick handler after any OS work is completed. + */ + void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + /** + * task.h + * 
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+ * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ +#endif + +/** + * task.h + * 
+ * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ *
+ * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task. It is not valid to call + * xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * 
+ *  // This example demonstrates how a human readable table of run time stats
+ *  // information is generated from raw data provided by uxTaskGetSystemState().
+ *  // The human readable table is written to pcWriteBuffer
+ *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ *  {
+ *  TaskStatus_t *pxTaskStatusArray;
+ *  volatile UBaseType_t uxArraySize, x;
+ *  uint32_t ulTotalRunTime, ulStatsAsPercentage;
+ *
+ *      // Make sure the write buffer does not contain a string.
+ * pcWriteBuffer = 0x00;
+ *
+ *      // Take a snapshot of the number of tasks in case it changes while this
+ *      // function is executing.
+ *      uxArraySize = uxTaskGetNumberOfTasks();
+ *
+ *      // Allocate a TaskStatus_t structure for each task.  An array could be
+ *      // allocated statically at compile time.
+ *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+ *
+ *      if( pxTaskStatusArray != NULL )
+ *      {
+ *          // Generate raw status information about each task.
+ *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+ *
+ *          // For percentage calculations.
+ *          ulTotalRunTime /= 100UL;
+ *
+ *          // Avoid divide by zero errors.
+ *          if( ulTotalRunTime > 0 )
+ *          {
+ *              // For each populated position in the pxTaskStatusArray array,
+ *              // format the raw data as human readable ASCII data
+ *              for( x = 0; x < uxArraySize; x++ )
+ *              {
+ *                  // What percentage of the total run time has the task used?
+ *                  // This will always be rounded down to the nearest integer.
+ *                  // ulTotalRunTimeDiv100 has already been divided by 100.
+ *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+ *
+ *                  if( ulStatsAsPercentage > 0UL )
+ *                  {
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ *                  }
+ *                  else
+ *                  {
+ *                      // If the percentage is zero here then the task has
+ *                      // consumed less than 1% of the total run time.
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ *                  }
+ *
+ *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ *              }
+ *          }
+ *
+ *          // The array is no longer needed, free the memory it consumes.
+ *          vPortFree( pxTaskStatusArray );
+ *      }
+ *  }
+ *
+ */ +UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskList( char *pcWriteBuffer );
+ * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task + * names, states and stack usage. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );
+ * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
uint32_t ulTaskGetIdleRunTimeCounter( void );
+ * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task. + * + * @return The total run time of the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + * \ingroup TaskUtils + */ +uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNofifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * pulPreviousNotificationValue - + * Can be used to pass out the subject task's notification value before any + * bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL ) +#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL ) + +/** + * task. h + * 
BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * 
BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexed() performs the same operation as + * xTaskNotifyIndexed() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than when the function returns) in the additional + * pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the + * addition that it also returns the subject task's prior notification value + * (the notification value as it was at the time the function is called, rather + * than when the function returns) in the additional pulPreviousNotifyValue + * parameter. + * + * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) +#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNofify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as + * xTaskNotifyIndexedFromISR() with the addition that it also returns the + * subject task's prior notification value (the notification value at the time + * the function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQueryFromISR() performs the same operation as + * xTaskNotifyFromISR() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * 
+ * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) +#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
+ * + * Sends a direct to task notification to a particular index in the target + * task's notification array in a manner similar to giving a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * macros to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * xTaskNotifyGiveIndexed() is a helper macro intended for use when task + * notifications are used as light weight and faster binary or counting + * semaphore equivalents. Actual FreeRTOS semaphores are given using the + * xSemaphoreGive() API function, the equivalent action that instead uses a task + * notification is xTaskNotifyGiveIndexed(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyGive() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyGive() is equivalent to calling + * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyGive() + * does not have this parameter and always sends notifications to index 0. + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL ) +#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL ) + +/** + * task. h + * 
void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR + * \ingroup TaskNotifications + */ +void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) ); +#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) ); + +/** + * task. h + * 
+ * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * the task's notification value to be non-zero. The task does not consume any + * CPU time while it is in the Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) ) +#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) ) + +/** + * task. h + * 
+ * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
+ *
+ * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+ *
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; +#define xTaskNotifyStateClear( xTask ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) ) +#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) ) + +/** + * task. h + * 
+ * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
+ *
+ * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
+ *
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) ) +#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) ) + +/** + * task.h + * 
+ * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+ *
+ * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+ *
+ * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTIcksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * 
+ *  // Driver library function used to receive uxWantedBytes from an Rx buffer
+ *  // that is filled by a UART interrupt. If there are not enough bytes in the
+ *  // Rx buffer then the task enters the Blocked state until it is notified that
+ *  // more data has been placed into the buffer. If there is still not enough
+ *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+ *  // is used to re-calculate the Block time to ensure the total amount of time
+ *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+ *  // continues until either the buffer contains at least uxWantedBytes bytes,
+ *  // or the total amount of time spent in the Blocked state reaches
+ *  // MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+ *  // available up to a maximum of uxWantedBytes.
+ *
+ *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+ *  {
+ *  size_t uxReceived = 0;
+ *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+ *  TimeOut_t xTimeOut;
+ *
+ *      // Initialize xTimeOut.  This records the time at which this function
+ *      // was entered.
+ *      vTaskSetTimeOutState( &xTimeOut );
+ *
+ *      // Loop until the buffer contains the wanted number of bytes, or a
+ *      // timeout occurs.
+ *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+ *      {
+ *          // The buffer didn't contain enough data so this task is going to
+ *          // enter the Blocked state. Adjusting xTicksToWait to account for
+ *          // any time that has been spent in the Blocked state within this
+ *          // function so far to ensure the total amount of time spent in the
+ *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
+ *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+ *          {
+ *              //Timed out before the wanted number of bytes were available,
+ *              // exit the loop.
+ *              break;
+ *          }
+ *
+ *          // Wait for a maximum of xTicksToWait ticks to be notified that the
+ *          // receive interrupt has placed more data into the buffer.
+ *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
+ *      }
+ *
+ *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+ *      // The actual number of bytes read (which might be less than
+ *      // uxWantedBytes) is returned.
+ *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+ *                                                  pucBuffer,
+ *                                                  uxWantedBytes );
+ *
+ *      return uxReceived;
+ *  }
+ *
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
+ *
+ * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks + * \ingroup TaskCtrl + */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + + +/*----------------------------------------------------------- +* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES +*----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + */ +BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning tasks priority) to insert the list item into the event list is task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks,the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the calling task. + */ +TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION; + +/* + * Get the uxTCBNumber assigned to the task referenced by the xTask parameter. + */ +UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* INC_TASK_H */ diff --git a/Libs/FreeRTOS/kernel/include/timers.h b/Libs/FreeRTOS/kernel/include/timers.h new file mode 100644 index 0000000..970e27b --- /dev/null +++ b/Libs/FreeRTOS/kernel/include/timers.h @@ -0,0 +1,1364 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef TIMERS_H +#define TIMERS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include timers.h" +#endif + +/*lint -save -e537 This headers are only multiply included if the application code + * happens to also be including task.h. */ +#include "task.h" +/*lint -restore */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* IDs for commands that can be sent/received on the timer queue. These are to + * be used solely through the macros that make up the public software timer API, + * as defined below. The commands that are sent from interrupts must use the + * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task + * or interrupt version of the queue send function should be used. */ +#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) +#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) +#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 ) +#define tmrCOMMAND_START ( ( BaseType_t ) 1 ) +#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 ) +#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 ) +#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 ) +#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 ) + +#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 ) +#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 ) +#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 ) + + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; + +/* + * Defines the prototype to which timer callback functions must conform. + */ +typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); + +/* + * Defines the prototype to which functions used with the + * xTimerPendFunctionCallFromISR() function must conform. + */ +typedef void (* PendedFunction_t)( void *, + uint32_t ); + +/** + * TimerHandle_t xTimerCreate( const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * x ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +#endif + +/** + * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction, + * StaticTimer_t *pxTimerBuffer ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * void *pvTimerGetTimerID( TimerHandle_t xTimer ); + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStart() starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerStart() has equivalent functionality + * to the xTimerReset() API function. + * + * Starting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerStart() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerStart() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerStart() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() + * to be available. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the start command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStart( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStop() stops a timer that was previously started using either of the + * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), + * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. + * + * Stopping a timer ensures the timer is not in the active state. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() + * to be available. + * + * @param xTimer The handle of the timer being stopped. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the stop command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStop( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerChangePeriod() changes the period of a timer that was previously + * created using the xTimerCreate() API function. + * + * xTimerChangePeriod() can be called to change the period of an active or + * dormant state timer. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerChangePeriod() to be available. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the change period command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerChangePeriod() was called. xTicksToWait is ignored if + * xTimerChangePeriod() is called before the scheduler is started. + * + * @return pdFAIL will be returned if the change period command could not be + * sent to the timer command queue even after xTicksToWait ticks had passed. + * pdPASS will be returned if the command was successfully sent to the timer + * command queue. When the command is actually processed will depend on the + * priority of the timer service/daemon task relative to other tasks in the + * system. The timer service/daemon task priority is set by the + * configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. If the timer + * // referenced by xTimer is already active when it is called, then the timer + * // is deleted. If the timer referenced by xTimer is not active when it is + * // called, then the period of the timer is set to 500ms and the timer is + * // started. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is already active - delete it. + * xTimerDelete( xTimer ); + * } + * else + * { + * // xTimer is not active, change its period to 500ms. This will also + * // cause the timer to start. Block for a maximum of 100 ticks if the + * // change period command cannot immediately be sent to the timer + * // command queue. + * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS ) + * { + * // The command was successfully sent. + * } + * else + * { + * // The command could not be sent, even after waiting for 100 ticks + * // to pass. Take appropriate action here. + * } + * } + * } + * @endverbatim + */ +#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerDelete() deletes a timer that was previously created using the + * xTimerCreate() API function. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerDelete() to be available. + * + * @param xTimer The handle of the timer being deleted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the delete command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete() + * is called before the scheduler is started. + * + * @return pdFAIL will be returned if the delete command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerChangePeriod() API function example usage scenario. + */ +#define xTimerDelete( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerReset() re-starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerReset() will cause the timer to + * re-evaluate its expiry time so that it is relative to when xTimerReset() was + * called. If the timer was in the dormant state then xTimerReset() has + * equivalent functionality to the xTimerStart() API function. + * + * Resetting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerReset() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerReset() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerReset() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() + * to be available. + * + * @param xTimer The handle of the timer being reset/started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the reset command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer. + * + * TimerHandle_t xBacklightTimer = NULL; + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press event handler. + * void vKeyPressEventHandler( char cKey ) + * { + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. Wait 10 ticks for the command to be successfully sent + * // if it cannot be sent immediately. + * vSetBacklightState( BACKLIGHT_ON ); + * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start the one-shot timer that is responsible for turning + * // the back-light off if no keys are pressed within a 5 second period. + * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. + * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks. + * pdFALSE, // The timer is a one-shot timer. + * 0, // The id is not used by the callback so can take any value. + * vBacklightTimerCallback // The callback function that switches the LCD back-light off. + * ); + * + * if( xBacklightTimer == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timer running as it has already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#define xTimerReset( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStart() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStartFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStartFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStartFromISR() function. If + * xTimerStartFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerStartFromISR() is actually called. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then restart the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The start command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStop() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being stopped. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStopFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStopFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStopFromISR() function. If + * xTimerStopFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the timer should be simply stopped. + * + * // The interrupt service routine that stops the timer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - simply stop the timer. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The stop command was not executed successfully. Take appropriate + * // action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerChangePeriod() that can be called from an interrupt + * service routine. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerChangePeriodFromISR() writes a message to the + * timer command queue, so has the potential to transition the timer service/ + * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() + * causes the timer service/daemon task to leave the Blocked state, and the + * timer service/daemon task has a priority equal to or greater than the + * currently executing task (the task that was interrupted), then + * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the + * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets + * this value to pdTRUE then a context switch should be performed before the + * interrupt exits. + * + * @return pdFAIL will be returned if the command to change the timers period + * could not be sent to the timer command queue. pdPASS will be returned if the + * command was successfully sent to the timer command queue. When the command + * is actually processed will depend on the priority of the timer service/daemon + * task relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the period of xTimer should be changed to 500ms. + * + * // The interrupt service routine that changes the period of xTimer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - change the period of xTimer to 500ms. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The command to change the timers period was not executed + * // successfully. Take appropriate action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerReset() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer that is to be started, reset, or + * restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerResetFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerResetFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerResetFromISR() function. If + * xTimerResetFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerResetFromISR() is actually called. The timer service/daemon + * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + + +/** + * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * TickType_t xTicksToWait ); + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * const char * const pcTimerGetName( TimerHandle_t xTimer ); + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION; + +/** + * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + /** + * task.h + * 
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task + * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ); + +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* TIMERS_H */ diff --git a/Libs/FreeRTOS/kernel/list.c b/Libs/FreeRTOS/kernel/list.c new file mode 100644 index 0000000..8db46a5 --- /dev/null +++ b/Libs/FreeRTOS/kernel/list.c @@ -0,0 +1,223 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "list.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be + * defined for the header files above, but not in this file, in order to + * generate the correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ +/* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems )--; + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 0000000..099a33a --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -0,0 +1,1205 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the + * same a the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + +/** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +/** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + +/** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + +/** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be un-suspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation + * contains its own wait for interrupt or wait for event + * instruction, and so wfi should not be executed again. However, + * the original expected idle time variable must remain unmodified, + * so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will + * increase any slippage between the time maintained by the RTOS and + * calendar time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. + * Again, the time the SysTick is stopped for is accounted for as + * best it can be, but using the tickless mode will inevitably + * result in some tiny drift of the time maintained by the kernel + * with respect to calendar time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is + * yet to count to zero (in which case an interrupt other than the + * SysTick must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is + * stepped forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* configENABLE_MPU */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != NULL ); + SecureContext_LoadContext( xSecureContext ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + /* R0 contains the secure context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* configENABLE_MPU */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ +/* *INDENT-OFF* */ +#if ( configENABLE_MPU == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +/* *INDENT-ON* */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if ( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr1 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c new file mode 100644 index 0000000..cda3617 --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -0,0 +1,333 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + " ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " msr control, r2 \n"/* Set this task's CONTROL value. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n"/* Finally, branch to EXC_RETURN. */ + #else /* configENABLE_MPU */ + " ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n"/* Set this task's PSPLIM value. */ + " movs r1, #2 \n"/* r1 = 2. */ + " msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n"/* Discard everything up to r0. */ + " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n"/* Finally, branch to EXC_RETURN. */ + #endif /* configENABLE_MPU */ + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst2: .word 0xe000ed94 \n" + "xMAIR0Const2: .word 0xe000edc0 \n" + "xRNRConst2: .word 0xe000ed98 \n" + "xRBARConst2: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n"/* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " mrs r0, control \n"/* Read the CONTROL register. */ + " bic r0, #1 \n"/* Clear the bit 0. */ + " msr control, r0 \n"/* Write back the new CONTROL value. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n"/* r0 = CONTROL. */ + " orr r0, #1 \n"/* r0 = r0 | 1. */ + " msr control, r0 \n"/* CONTROL = r0. */ + " bx lr \n"/* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n"/* Set the MSP back to the start of the stack. */ + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n"/* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + "xVTORConst: .word 0xe000ed08 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " msr basepri, r0 \n"/* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n"/* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n"/* Read PSP in r0. */ + #if ( configENABLE_FPU == 1 ) + " tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n"/* Store the FPU registers which are not saved automatically. */ + #endif /* configENABLE_FPU */ + #if ( configENABLE_MPU == 1 ) + " mrs r1, psplim \n"/* r1 = PSPLIM. */ + " mrs r2, control \n"/* r2 = CONTROL. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ + #else /* configENABLE_MPU */ + " mrs r2, psplim \n"/* r2 = PSPLIM. */ + " mov r3, lr \n"/* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + #endif /* configENABLE_MPU */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " str r0, [r1] \n"/* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n"/* r0 = 0. */ + " msr basepri, r0 \n"/* Enable interrupts. */ + " \n" + " ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n"/* Read pxCurrentTCB. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " dmb \n"/* Complete outstanding transfers before disabling MPU. */ + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + " str r4, [r2] \n"/* Disable MPU. */ + " \n" + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + " ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */ + " ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r3, [r2] \n"/* Program MAIR0. */ + " ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */ + " movs r3, #4 \n"/* r3 = 4. */ + " str r3, [r2] \n"/* Program RNR = 4. */ + " adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + " ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */ + " ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + " ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */ + " orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + " str r4, [r2] \n"/* Enable MPU. */ + " dsb \n"/* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ + #else /* configENABLE_MPU */ + " ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + #endif /* configENABLE_MPU */ + " \n" + #if ( configENABLE_FPU == 1 ) + " tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n"/* Restore the FPU registers which are not restored automatically. */ + #endif /* configENABLE_FPU */ + " \n" + #if ( configENABLE_MPU == 1 ) + " msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */ + " msr control, r2 \n"/* Restore the CONTROL register value for the task. */ + #else /* configENABLE_MPU */ + " msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */ + #endif /* configENABLE_MPU */ + " msr psp, r0 \n"/* Remember the new top of stack for the task. */ + " bx r3 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + #if ( configENABLE_MPU == 1 ) + "xMPUCTRLConst: .word 0xe000ed94 \n" + "xMAIR0Const: .word 0xe000edc0 \n" + "xRNRConst: .word 0xe000ed98 \n" + "xRBARConst: .word 0xe000ed9c \n" + #endif /* configENABLE_MPU */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, svchandler_address_const \n" + " bx r1 \n" + " \n" + " .align 4 \n" + "svchandler_address_const: .word vPortSVCHandler_C \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..50bd258 --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..1d24286 --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h @@ -0,0 +1,325 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" { + #endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + + #ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. + #endif /* configENABLE_FPU */ + + #ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. + #endif /* configENABLE_MPU */ + + #ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. + #endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ + #define portARCH_NAME "Cortex-M33" + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portNOP() + #define portINLINE __inline + #ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) + #endif + #define portHAS_STACK_OVERFLOW_CHECKING 1 + #define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ + extern BaseType_t xPortIsInsideInterrupt( void ); + + extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + + extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; + extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + + extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + + #if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ + #if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) + #else + #define portPRIVILEGE_BIT ( 0x0UL ) + #endif /* configENABLE_MPU */ + + +/* MPU regions. */ + #define portPRIVILEGED_FLASH_REGION ( 0UL ) + #define portUNPRIVILEGED_FLASH_REGION ( 1UL ) + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) + #define portPRIVILEGED_RAM_REGION ( 3UL ) + #define portSTACK_REGION ( 4UL ) + #define portFIRST_CONFIGURABLE_REGION ( 5UL ) + #define portLAST_CONFIGURABLE_REGION ( 7UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ + #define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) + #define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) + #define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) + #define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + } xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ + #define portSVC_ALLOCATE_SECURE_CONTEXT 0 + #define portSVC_FREE_SECURE_CONTEXT 1 + #define portSVC_START_SCHEDULER 2 + #define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ + #define portYIELD() vPortYield() + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) + #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) + #define portDISABLE_INTERRUPTS() ulSetInterruptMask() + #define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) + #else + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) + #define portCLEAN_UP_TCB( pxTCB ) + #endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + #else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + #endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus + } + #endif + +#endif /* PORTMACRO_H */ diff --git a/Libs/FreeRTOS/kernel/portable/MemMang/heap_3.c b/Libs/FreeRTOS/kernel/portable/MemMang/heap_3.c new file mode 100644 index 0000000..08cfff8 --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/MemMang/heap_3.c @@ -0,0 +1,107 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + traceFREE( pv, 0 ); + } + ( void ) xTaskResumeAll(); + } +} diff --git a/Libs/FreeRTOS/kernel/portable/SiliconLabs/tick_power_manager.c b/Libs/FreeRTOS/kernel/portable/SiliconLabs/tick_power_manager.c new file mode 100644 index 0000000..6b82aca --- /dev/null +++ b/Libs/FreeRTOS/kernel/portable/SiliconLabs/tick_power_manager.c @@ -0,0 +1,232 @@ +/***************************************************************************//** + * @file + * @brief FreeRTOS Tick and Sleep port. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +/* Compiler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" +#include "sl_sleeptimer.h" +#include "sl_atomic.h" +#include "sl_power_manager.h" + +#if configUSE_TICKLESS_IDLE == 0 +#error "This port requires configUSE_TICKLESS_IDLE to be enabled." +#endif + +/* Local variables */ +/* Number of lf ticks per OS ticks. */ +static uint32_t lfticks_per_os_ticks = 0; + +/* Tick count (in lf ticks) last time the tick count was updated in FreeRTOS. */ +static uint32_t last_update_lftick = 0; + +/* Indicates if system is sleeping. */ +static bool is_sleeping = false; + +/* Maximum number of os ticks the system can sleep per call. */ +static TickType_t max_sleep_os_ticks = 0; + +/* Expected sleep ticks */ +static TickType_t expected_sleep_ticks = 0; + +/* Total ticks slept */ +static TickType_t total_slept_os_ticks = 0; + +/* Handle to schedule wakeup timer. */ +static sl_sleeptimer_timer_handle_t schedule_wakeup_timer_handle; + +/* Local functions */ +static void sli_schedule_wakeup_timer_expire_handler(sl_sleeptimer_timer_handle_t *handle, + void *data); + +static void sli_os_schedule_wakeup(TickType_t os_ticks); + +/***************************************************************************//** + * Sets up sleeptimer timer for constant ticking. + ******************************************************************************/ +void vPortSetupTimerInterrupt( void ) +{ + uint32_t sleeptimer_freq; + + /* FreeRTOS requires a high SVC priority when starting the scheduler */ + NVIC_SetPriority(SVCall_IRQn, 0); + + sleeptimer_freq = sl_sleeptimer_get_timer_frequency(); + configASSERT( configTICK_RATE_HZ <= sleeptimer_freq ); + + lfticks_per_os_ticks = (sleeptimer_freq + (configTICK_RATE_HZ - 1)) / configTICK_RATE_HZ; + max_sleep_os_ticks = (0xFFFFFFFF / lfticks_per_os_ticks) - 10; + + last_update_lftick = sl_sleeptimer_get_tick_count(); + + /* Schedule a wakeup in one tick. */ + sli_os_schedule_wakeup(1); +} + +/***************************************************************************//** + * Stop constant ticking and wake the system up after specified idle time. + * + * @param xExpectedIdleTime Time in os ticks that the system is expected to + * sleep. + ******************************************************************************/ +SL_WEAK void sli_iot_power_set_expected_idle(TickType_t expected_idle) +{ + (void)expected_idle; + return; +} + +void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) +{ + sl_atomic_store(is_sleeping, true); + + /* Schedule a wakeup for expected idle end time. */ + sl_sleeptimer_stop_timer(&schedule_wakeup_timer_handle); + sli_os_schedule_wakeup(xExpectedIdleTime); + + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + sli_iot_power_set_expected_idle(xExpectedIdleTime); + + expected_sleep_ticks = xExpectedIdleTime; + total_slept_os_ticks = 0; + + sl_power_manager_sleep(); + + configPOST_SLEEP_PROCESSING( total_slept_os_ticks ); + + sl_atomic_store(is_sleeping, false); + + /* Schedule a wakeup in one tick. */ + sl_sleeptimer_stop_timer(&schedule_wakeup_timer_handle); + sli_os_schedule_wakeup(1); +} + +/***************************************************************************//** + * Function called when schedule wakeup timer expires. + ******************************************************************************/ +static void sli_schedule_wakeup_timer_expire_handler(sl_sleeptimer_timer_handle_t *handle, void *data) +{ + uint32_t current_tick_count = sl_sleeptimer_get_tick_count(); + + (void)handle; + (void)data; + + uint32_t originalMask = portSET_INTERRUPT_MASK_FROM_ISR(); + /* If system was not sleeping, update lfticks counter. */ + if (!is_sleeping) { + bool sched = false; + + /* Increment the RTOS tick. */ + while ((current_tick_count - last_update_lftick) >= lfticks_per_os_ticks) { + sched |= xTaskIncrementTick(); + last_update_lftick += lfticks_per_os_ticks; + } + + if ( sched != pdFALSE ) { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portYIELD(); + } + + sli_os_schedule_wakeup(1); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR(originalMask); +} + +/***************************************************************************//** + * (Re)-start schedule wakeup timer with delay specified. + * + * @param os_ticks Delay, in os ticks, before next wakeup/tick. + ******************************************************************************/ +static void sli_os_schedule_wakeup(TickType_t os_ticks) +{ + sl_status_t status; + uint32_t lf_ticks_to_sleep; + TickType_t os_ticks_to_sleep; + uint32_t current_tick_count = sl_sleeptimer_get_tick_count(); + + /* Compute number of lfticks to sleep. */ + os_ticks_to_sleep = (os_ticks <= max_sleep_os_ticks) ? os_ticks : max_sleep_os_ticks; + + /* This function implements a correction mechanism that corrects any drift that can */ + /* occur between the sleep timer time and the tick count in FreeRTOS. */ + lf_ticks_to_sleep = os_ticks_to_sleep * lfticks_per_os_ticks; + if (lf_ticks_to_sleep <= (current_tick_count - last_update_lftick)) { + lf_ticks_to_sleep = 1; + } else { + lf_ticks_to_sleep -= (current_tick_count - last_update_lftick); + } + + status = sl_sleeptimer_start_timer(&schedule_wakeup_timer_handle, + lf_ticks_to_sleep, + sli_schedule_wakeup_timer_expire_handler, + 0, + 0, + 0); + configASSERT( status == SL_STATUS_OK ); + +#if (configASSERT_DEFINED == 0) + (void)status; +#endif +} + +/***************************************************************************//** + * Function called by power manager to ensure that system is ok to sleep. + ******************************************************************************/ +SL_WEAK bool sli_iot_power_ok_to_sleep(void) +{ + return true; +} + +bool sl_power_manager_is_ok_to_sleep(void) +{ + return sli_iot_power_ok_to_sleep() && (eTaskConfirmSleepModeStatus() != eAbortSleep); +} + +/***************************************************************************//** + * Function called by power manager to determine if system can go back to sleep + * after a wakeup. + * + * @note Function is called in critical section + ******************************************************************************/ +bool sl_power_manager_sleep_on_isr_exit(void) +{ + uint32_t slept_lf_ticks; + uint32_t slept_os_ticks; + + /* Determine how long we slept. */ + slept_lf_ticks = sl_sleeptimer_get_tick_count() - last_update_lftick; + slept_os_ticks = slept_lf_ticks / lfticks_per_os_ticks; + last_update_lftick += slept_os_ticks * lfticks_per_os_ticks; + + /* Notify FreeRTOS of how long we slept. */ + if ((total_slept_os_ticks + slept_os_ticks) < expected_sleep_ticks) { + vTaskStepTick(slept_os_ticks); + total_slept_os_ticks += slept_os_ticks; + } else { + vTaskStepTick(expected_sleep_ticks - total_slept_os_ticks); + total_slept_os_ticks = expected_sleep_ticks; + } + + /* Have we slept enough ? */ + if (total_slept_os_ticks >= expected_sleep_ticks) { + return false; + } + + /* Check if we can sleep again */ + return (eTaskConfirmSleepModeStatus() != eAbortSleep); +} diff --git a/Libs/FreeRTOS/kernel/queue.c b/Libs/FreeRTOS/kernel/queue.c new file mode 100644 index 0000000..05e5ece --- /dev/null +++ b/Libs/FreeRTOS/kernel/queue.c @@ -0,0 +1,3029 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#if ( configUSE_CO_ROUTINES == 1 ) + #include "croutine.h" +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( int8_t ) -1 ) +#define queueLOCKED_UNMODIFIED ( ( int8_t ) 0 ) +#define queueINT8_MAX ( ( int8_t ) 127 ) + +/* When the Queue_t structure is used to represent a base queue its pcHead and + * pcTail members are used as pointers into the queue storage area. When the + * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are + * not necessary, and the pcHead pointer is set to NULL to indicate that the + * structure instead holds a pointer to the mutex holder (if any). Map alternative + * names to the pcHead and structure member to ensure the readability of the code + * is maintained. The QueuePointers_t and SemaphoreData_t types are used to form + * a union as their usage is mutually exclusive dependent on what the queue is + * being used for. */ +#define uxQueueType pcHead +#define queueQUEUE_IS_MUTEX NULL + +typedef struct QueuePointers +{ + int8_t * pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + +/* Semaphores do not actually store or copy data, so have an item size of + * zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define queueYIELD_IF_USING_PREEMPTION() +#else + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. See the following link for the + * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + */ +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + int8_t * pcHead; /*< Points to the beginning of the queue storage area. */ + int8_t * pcWriteTo; /*< Points to the free next place in the storage area. */ + + union + { + QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */ + } u; + + List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */ + UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */ + + volatile int8_t cRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + volatile int8_t cTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + struct QueueDefinition * pxQueueSetContainer; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueNumber; + uint8_t ucQueueType; + #endif +} xQUEUE; + +/* The old xQUEUE name is maintained above then typedefed to the new Queue_t + * name below to enable the use of older kernel aware debuggers. */ +typedef xQUEUE Queue_t; + +/*-----------------------------------------------------------*/ + +/* + * The queue registry is just a means for kernel aware debuggers to locate + * queue structures. It has no other purpose so is an optional component. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +/* The type stored within the queue registry array. This allows a name + * to be assigned to each queue making kernel aware debugging a little + * more user friendly. */ + typedef struct QUEUE_REGISTRY_ITEM + { + const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + QueueHandle_t xHandle; + } xQueueRegistryItem; + +/* The old xQueueRegistryItem name is maintained above then typedefed to the + * new xQueueRegistryItem name below to enable the use of older kernel aware + * debuggers. */ + typedef xQueueRegistryItem QueueRegistryItem_t; + +/* The queue registry is simply an array of QueueRegistryItem_t structures. + * The pcQueueName member of a structure being NULL is indicative of the + * array position being vacant. */ + PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; + +#endif /* configQUEUE_REGISTRY_SIZE */ + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) PRIVILEGED_FUNCTION; + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_QUEUE_SETS == 1 ) + +/* + * Checks to see if a queue is a member of a queue set, and if so, notifies + * the queue set that the queue contains data. + */ + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Called after a Queue_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; + +/* + * Mutexes are a special type of queue. When a mutex is created, first the + * queue is created, then prvInitialiseMutex() is called to configure the queue + * as a mutex. + */ +#if ( configUSE_MUTEXES == 1 ) + static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MUTEXES == 1 ) + +/* + * If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. This function returns + * that priority. + */ + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ + taskENTER_CRITICAL(); \ + { \ + if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \ + } \ + if( ( pxQueue )->cTxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ + } \ + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + pxQueue->pcWriteTo = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->cRxLock = queueUNLOCKED; + pxQueue->cTxLock = queueUNLOCKED; + + if( xNewQueue == pdFALSE ) + { + /* If there are tasks blocked waiting to read from the queue, then + * the tasks will remain blocked as after this function exits the queue + * will still be empty. If there are tasks blocked waiting to write to + * the queue, then one should be unblocked as after this function exits + * it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + } + } + taskEXIT_CRITICAL(); + + /* A value is returned for calling semantic consistency with previous + * versions. */ + return pdPASS; +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + + /* The StaticQueue_t structure and the queue storage area must be + * supplied. */ + configASSERT( pxStaticQueue != NULL ); + + /* A queue storage area should be provided if the item size is not 0, and + * should not be provided if the item size is 0. */ + configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); + configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticQueue_t or StaticSemaphore_t equals the size of + * the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + configASSERT( xSize == sizeof( Queue_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + * The address of a statically allocated storage area was also passed in + * but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + + if( pxNewQueue != NULL ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + * note this queue was allocated statically in case the queue is + * later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue; + size_t xQueueSizeInBytes; + uint8_t * pucQueueStorage; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Check for multiplication overflow. */ + configASSERT( ( uxItemSize == 0 ) || ( uxQueueLength == ( xQueueSizeInBytes / uxItemSize ) ) ); + + /* Check for addition overflow. */ + configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) > xQueueSizeInBytes ); + + /* Allocate the queue and storage area. Justification for MISRA + * deviation as follows: pvPortMalloc() always ensures returned memory + * blocks are aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the Queue_t structure - which in this case + * is an int8_t *. Therefore, whenever the stack alignment requirements + * are greater than or equal to the pointer to char requirements the cast + * is safe. In other cases alignment requirements are not strict (one or + * two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + + if( pxNewQueue != NULL ) + { + /* Jump past the queue structure to find the location of the queue + * storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + * note this task was created dynamically in case it is later + * deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) +{ + /* Remove compiler warnings about unused parameters should + * configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + { + /* No RAM was allocated for the queue storage area, but PC head cannot + * be set to NULL because NULL is used as a key to say the queue is used as + * a mutex. Therefore just set pcHead to point to the queue as a benign + * value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + } + + /* Initialise the queue members as described where the queue type is + * defined. */ + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + } + #endif /* configUSE_TRACE_FACILITY */ + + #if ( configUSE_QUEUE_SETS == 1 ) + { + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t * pxNewQueue ) + { + if( pxNewQueue != NULL ) + { + /* The queue create function will set all the queue structure members + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + /* Prevent compiler warnings about unused parameters if + * configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + + /* This function is called by xSemaphoreGetMutexHolder(), and should not + * be called directly. Note: This is a good way of determining if the + * calling task is the mutex holder, but not a good way of determining the + * identity of the mutex holder, as the holder may change between the + * following critical section exiting and the function returning. */ + taskENTER_CRITICAL(); + { + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + } + taskEXIT_CRITICAL(); + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + + configASSERT( xSemaphore ); + + /* Mutexes cannot be used in interrupt service routines, so the mutex + * holder should not change in an ISR, and therefore a critical section is + * not required here. */ + if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* If this is the task that holds the mutex then xMutexHolder will not + * change outside of this task. If this task does not hold the mutex then + * pxMutexHolder can never coincidentally equal the tasks handle, and as + * this is the only condition we are interested in it does not matter if + * pxMutexHolder is accessed simultaneously by another task. Therefore no + * mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + traceGIVE_MUTEX_RECURSIVE( pxMutex ); + + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to + * the task handle, therefore no underflow check is required. Also, + * uxRecursiveCallCount is only modified by the mutex holder, and as + * there can only be one, no mutual exclusion is required to modify the + * uxRecursiveCallCount member. */ + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; + + /* Has the recursive call count unwound to 0? */ + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + { + /* Return the mutex. This will automatically unblock any other + * task that might be waiting to access the mutex. */ + ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + /* The mutex cannot be given because the calling task is not the + * holder. */ + xReturn = pdFAIL; + + traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* Comments regarding mutual exclusion as per those within + * xQueueGiveMutexRecursive(). */ + + traceTAKE_MUTEX_RECURSIVE( pxMutex ); + + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + xReturn = pdPASS; + } + else + { + xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); + + /* pdPASS will only be returned if the mutex was successfully + * obtained. The calling task may have entered the Blocked state + * before reaching here. */ + if( xReturn != pdFAIL ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + } + else + { + traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + configASSERT( uxInitialCount <= uxMaxCount ); + + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) + { + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + configASSERT( uxInitialCount <= uxMaxCount ); + + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) +{ + BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Is there room on the queue now? The running task must be the + * highest priority task wanting to access the queue. If the head item + * in the queue is to be overwritten then it does not matter if the + * queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + traceQUEUE_SEND( pxQueue ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to + * do this from within the critical section - the + * kernel takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes + * and the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to do + * this from within the critical section - the kernel + * takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes and + * the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was full and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + /* Return to the original privilege level before exiting + * the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was full and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Unlocking the queue means queue events can effect the + * event list. It is possible that interrupts occurring now + * remove this task from the event list again - but as the + * scheduler is suspended the task will go onto the pending + * ready last instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler will move tasks from the pending + * ready list into the ready list - so it is feasible that this + * task is already in a ready list before it yields - in which + * case the yield will not cause a context switch unless there + * is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* Similar to xQueueGenericSend, except without blocking if there is no room + * in the queue. Also don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the + * item size is 0. Don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + + configASSERT( pxQueue ); + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + * if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Normally a mutex would not be given from an interrupt, especially if + * there is a mutex holder, as priority inheritance makes no sense for an + * interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* When the queue is used to implement a semaphore no data is ever + * moved through the queue but it is still valid to see if the queue 'has + * space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + { + const int8_t cTxLock = pxQueue->cTxLock; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* A task can only have an inherited priority if it is a mutex + * holder - and if there is a mutex holder then the mutex cannot be + * given from an ISR. As this is the ISR version of the function it + * can be assumed there is no mutex holder and no need to determine if + * priority disinheritance is needed. Simply increase the count of + * messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The semaphore is a member of a queue set, and + * posting to the queue set caused a higher priority + * task to unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer). */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* There is now space in the queue, were any tasks waiting to + * post to the queue? If so, unblock the highest priority waiting + * task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* The timeout has not expired. If the queue is still empty place + * the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The queue contains data again. Loop back to try and read the + * data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + * back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + #if ( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + #endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* Check this really is a semaphore, in which case the item size will be + * 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + * statements within the function itself. This is done in the interest + * of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Semaphores are queues with an item size of 0, and where the + * number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + * messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + * priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + * semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* For inheritance to have occurred there must have been an + * initial timeout, and an adjusted timeout cannot become 0, as + * if it were 0 the function would have exited. */ + #if ( configUSE_MUTEXES == 1 ) + { + configASSERT( xInheritanceOccurred == pdFALSE ); + } + #endif /* configUSE_MUTEXES */ + + /* The semaphore count was 0 and no block time is specified + * (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The semaphore count was 0 and a block time was specified + * so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can give to and take from the semaphore + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* A block time is specified and not expired. If the semaphore + * count is 0 then enter the Blocked state to wait for a semaphore to + * become available. As semaphores are implemented with queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + taskENTER_CRITICAL(); + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There was no timeout and the semaphore count was not 0, so + * attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + /* If the semaphore count is 0 exit now as the timeout has + * expired. Otherwise return to attempt to take the semaphore that is + * known to be available. As semaphores are implemented by queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + * test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + { + taskENTER_CRITICAL(); + { + UBaseType_t uxHighestWaitingPriority; + + /* This task blocking on the mutex caused another + * task to inherit this task's priority. Now this task + * has timed out the priority should be disinherited + * again, but only as low as the next highest priority + * task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + } + taskEXIT_CRITICAL(); + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Remember the read position so it can be reset after the data + * is read from the queue as this function is only peeking the + * data, not removing it. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_PEEK( pxQueue ); + + /* The data is not being removed, so reset the read pointer. */ + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so see if there are + * any other tasks waiting for the data. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than this task. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure ready to enter the blocked + * state. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Timeout has not expired yet, check to see if there is data in the + * queue now, and if not enter the Blocked state to wait for data. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There is data in the queue now, so don't enter the blocked + * state, instead return to try and obtain the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. If there is still no data in the queue + * exit, otherwise go back and try to read the data again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + const int8_t cRxLock = pxQueue->cRxLock; + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* If the queue is locked the event list will not be modified. + * Instead update the lock count so the task that unlocks the queue + * will know that an ISR has removed data while the queue was + * locked. */ + if( cRxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + * force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was removed while it was locked. */ + configASSERT( cRxLock != queueINT8_MAX ); + + pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */ + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Cannot block in an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + traceQUEUE_PEEK_FROM_ISR( pxQueue ); + + /* Remember the read position so it can be reset as nothing is + * actually being removed from the queue. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + + configASSERT( xQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The queue can only have been allocated dynamically - free it + * again. */ + vPortFree( pxQueue ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + * check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxQueue ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + { + /* The queue must have been statically allocated, so is not going to be + * deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) + { + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->ucQueueType; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + UBaseType_t uxHighestPriorityOfWaitingTasks; + + /* If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. For this purpose, + * return the priority of the highest priority task that is waiting for the + * mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + } + + return uxHighestPriorityOfWaitingTasks; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) +{ + BaseType_t xReturn = pdFALSE; + UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* An item is not being added but overwritten, so subtract + * one from the recorded number of items in the queue so when + * one is added again below the number of recorded items remains + * correct. */ + --uxMessagesWaiting; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) +{ + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + * removed from the queue while the queue was locked. When a queue is + * locked items can be added or removed, but the event lists cannot be + * updated. */ + taskENTER_CRITICAL(); + { + int8_t cTxLock = pxQueue->cTxLock; + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + { + /* Data was posted while the queue was locked. Are any tasks + * blocked waiting for data to become available? */ + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting to + * the queue set caused a higher priority task to unblock. + * A context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Tasks that are removed from the event list will get + * added to the pending ready list as the scheduler is still + * suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + * the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that + * a context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + int8_t cRxLock = pxQueue->cRxLock; + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + } + else + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already full we may have to block. A critical section + * is required to prevent an interrupt removing something from the queue + * between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + /* The queue is full - do we want to block or just leave without + * posting? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + * return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + * that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already empty we may have to block. A critical section + * is required to prevent an interrupt adding something to the queue + * between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + * leave with nothing? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + * indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ) + { + Queue_t * const pxQueue = xQueue; + + /* Cannot block within an ISR so if there is no space on the queue then + * exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + * co-routine has not already been woken. */ + if( xCoRoutinePreviouslyWoken == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCoRoutinePreviouslyWoken; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxCoRoutineWoken ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* We cannot block from an ISR, so check there is data available. If + * not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( ( *pxCoRoutineWoken ) == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + + /* See if there is an empty space in the registry. A NULL name denotes + * a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].pcQueueName == NULL ) + { + /* Store the information on this queue. */ + xQueueRegistry[ ux ].pcQueueName = pcQueueName; + xQueueRegistry[ ux ].xHandle = xQueue; + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + /* Note there is nothing here to protect against another task adding or + * removing entries from the registry while it is being searched. */ + + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + pcReturn = xQueueRegistry[ ux ].pcQueueName; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return pcReturn; + } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + UBaseType_t ux; + + /* See if the handle of the queue being unregistered in actually in the + * registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + + /* Set the handle to NULL to ensure the same queue handle cannot + * appear in the registry twice if it is added, removed, then + * added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + Queue_t * const pxQueue = xQueue; + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements. + * It can result in vListInsert() being called on a list that can only + * possibly ever have one item in it, so the list will be fast, but even + * so it should be called with the scheduler locked and not from a critical + * section. */ + + /* Only do anything if there are no messages in the queue. This function + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvUnlockQueue( pxQueue ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) + { + QueueSetHandle_t pxQueue; + + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + + return pxQueue; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) + { + /* Cannot add a queue/semaphore to more than one queue set. */ + xReturn = pdFAIL; + } + else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* Cannot add a queue/semaphore to a queue set if there are already + * items in the queue/semaphore. */ + xReturn = pdFAIL; + } + else + { + ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet; + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) + { + /* The queue was not a member of the set. */ + xReturn = pdFAIL; + } + else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* It is dangerous to remove a queue from a set when the queue is + * not empty because the queue set will still hold pending events for + * the queue. */ + xReturn = pdFAIL; + } + else + { + taskENTER_CRITICAL(); + { + /* The queue is no longer contained in the set. */ + pxQueueOrSemaphore->pxQueueSetContainer = NULL; + } + taskEXIT_CRITICAL(); + xReturn = pdPASS; + } + + return xReturn; + } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */ + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t const xTicksToWait ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) + { + Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; + BaseType_t xReturn = pdFALSE; + + /* This function must be called form a critical section. */ + + configASSERT( pxQueueSetContainer ); + configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); + + if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ) + { + const int8_t cTxLock = pxQueueSetContainer->cTxLock; + + traceQUEUE_SET_SEND( pxQueueSetContainer ); + + /* The data copied is the handle of the queue that contains data. */ + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); + + if( cTxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( cTxLock != queueINT8_MAX ); + + pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ diff --git a/Libs/FreeRTOS/kernel/stream_buffer.c b/Libs/FreeRTOS/kernel/stream_buffer.c new file mode 100644 index 0000000..7d0971d --- /dev/null +++ b/Libs/FreeRTOS/kernel/stream_buffer.c @@ -0,0 +1,1327 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +#if ( configUSE_TASK_NOTIFICATIONS != 1 ) + #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c +#endif + +/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* If the user has not provided application specific Rx notification macros, + * or #defined the notification macros away, them provide default implementations + * that uses task notifications. */ +/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */ +#ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbRECEIVE_COMPLETED */ + +#ifndef sbRECEIVE_COMPLETED_FROM_ISR + #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbRECEIVE_COMPLETED_FROM_ISR */ + +/* If the user has not provided an application specific Tx notification macro, + * or #defined the notification macro away, them provide a default implementation + * that uses task notifications. */ +#ifndef sbSEND_COMPLETED + #define sbSEND_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbSEND_COMPLETED */ + +#ifndef sbSEND_COMPLETE_FROM_ISR + #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbSEND_COMPLETE_FROM_ISR */ +/*lint -restore (9026) */ + +/* The number of bytes used to hold the length of a message in the buffer. */ +#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Bits stored in the ucFlags field of the stream buffer. */ +#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ +#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */ + +/*-----------------------------------------------------------*/ + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ + #endif +} StreamBuffer_t; + +/* + * The number of bytes available to be read from the buffer. + */ +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION; + +/* + * Add xCount bytes from pucData into the pxStreamBuffer message buffer. + * Returns the number of bytes written, which will either equal xCount in the + * success case, or 0 if there was not enough space in the buffer (in which case + * no data is written into the buffer). + */ +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then reads an entire + * message out of the buffer. If the stream buffer is being used as a stream + * buffer then read as many bytes as possible from the buffer. + * prvReadBytesFromBuffer() is called to actually extract the bytes from the + * buffer's data storage area. + */ +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable, + size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then writes an entire + * message to the buffer. If the stream buffer is being used as a stream + * buffer then write as many bytes as possible to the buffer. + * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's + * data storage area. + */ +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) PRIVILEGED_FUNCTION; + +/* + * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them + * to pucData. + */ +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xMaxCount, + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; + +/* + * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to + * initialise the members of the newly created stream buffer structure. + */ +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) + { + uint8_t * pucAllocatedMemory; + uint8_t ucFlags; + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xIsMessageBuffer == pdTRUE ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } + + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* A stream buffer requires a StreamBuffer_t structure and a buffer. + * Both are allocated in a single call to pvPortMalloc(). The + * StreamBuffer_t structure is placed at the start of the allocated memory + * and the buffer follows immediately after. The requested size is + * incremented so the free space is returned as the user would expect - + * this is a quirk of the implementation that means otherwise the free + * space would be reported as one byte smaller than would be logically + * expected. */ + if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) ) + { + xBufferSizeBytes++; + pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */ + } + else + { + pucAllocatedMemory = NULL; + } + + + if( pucAllocatedMemory != NULL ) + { + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */ + pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer ); + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); + } + + return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) + { + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ + StreamBufferHandle_t xReturn; + uint8_t ucFlags; + + configASSERT( pucStreamBufferStorageArea ); + configASSERT( pxStaticStreamBuffer ); + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + if( xIsMessageBuffer != pdFALSE ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; + } + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticStreamBuffer_t equals the size of the real + * message buffer structure. */ + volatile size_t xSize = sizeof( StaticStreamBuffer_t ); + configASSERT( xSize == sizeof( StreamBuffer_t ) ); + } /*lint !e529 xSize is referenced is configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pucStreamBufferStorageArea, + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + /* Remember this was statically allocated in case it is ever deleted + * again. */ + pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED; + + traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ); + + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */ + } + else + { + xReturn = NULL; + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); + } + + return xReturn; + } + +#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + traceSTREAM_BUFFER_DELETE( xStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both the structure and the buffer were allocated using a single call + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ + } + #else + { + /* Should not be possible to get here, ucFlags must be corrupt. + * Force an assert. */ + configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 ); + } + #endif + } + else + { + /* The structure and buffer were not allocated dynamically and cannot be + * freed - just scrub the structure so future use will assert. */ + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + taskENTER_CRITICAL(); + { + if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) + { + if( pxStreamBuffer->xTaskWaitingToSend == NULL ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags ); + xReturn = pdPASS; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET( xStreamBuffer ); + } + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + + configASSERT( pxStreamBuffer ); + + /* It is not valid for the trigger level to be 0. */ + if( xTriggerLevel == ( size_t ) 0 ) + { + xTriggerLevel = ( size_t ) 1; + } + + /* The trigger level is the number of bytes that must be in the stream + * buffer before a task that is waiting for data is unblocked. */ + if( xTriggerLevel <= pxStreamBuffer->xLength ) + { + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel; + xReturn = pdPASS; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xSpace; + + configASSERT( pxStreamBuffer ); + + xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; + xSpace -= pxStreamBuffer->xHead; + xSpace -= ( size_t ) 1; + + if( xSpace >= pxStreamBuffer->xLength ) + { + xSpace -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xSpace; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn; + + configASSERT( pxStreamBuffer ); + + xReturn = prvBytesInBuffer( pxStreamBuffer ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace = 0; + size_t xRequiredSpace = xDataLengthBytes; + TimeOut_t xTimeOut; + + /* The maximum amount of space a stream buffer will ever report is its length + * minus 1. */ + const size_t xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + + /* If this is a message buffer then it must be possible to write the + * whole message. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + /* The message would not fit even if the entire buffer was empty, + * so don't wait for space. */ + xTicksToWait = ( TickType_t ) 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If this is a stream buffer then it is acceptable to write only part + * of the message to the buffer. Cap the length to the total length of + * the buffer. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + xRequiredSpace = xMaxReportedSpace; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* Wait until the required number of bytes are free in the message + * buffer. */ + taskENTER_CRITICAL(); + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + + if( xSpace < xRequiredSpace ) + { + /* Clear notification state as going to wait for space. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one writer. */ + configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); + pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); + } + else + { + taskEXIT_CRITICAL(); + break; + } + } + taskEXIT_CRITICAL(); + + traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToSend = NULL; + } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xSpace == ( size_t ) 0 ) + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); + + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace; + size_t xRequiredSpace = xDataLengthBytes; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) +{ + BaseType_t xShouldWrite; + size_t xReturn; + + if( xSpace == ( size_t ) 0 ) + { + /* Doesn't matter if this is a stream buffer or a message buffer, there + * is no space to write. */ + xShouldWrite = pdFALSE; + } + else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) + { + /* This is a stream buffer, as opposed to a message buffer, so writing a + * stream of bytes rather than discrete messages. Write as many bytes as + * possible. */ + xShouldWrite = pdTRUE; + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); + } + else if( xSpace >= xRequiredSpace ) + { + /* This is a message buffer, as opposed to a stream buffer, and there + * is enough space to write both the message length and the message itself + * into the buffer. Start by writing the length of the data, the data + * itself will be written later in this function. */ + xShouldWrite = pdTRUE; + ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* There is space available, but not enough space. */ + xShouldWrite = pdFALSE; + } + + if( xShouldWrite != pdFALSE ) + { + /* Writes the data itself. */ + xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */ + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. */ + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Clear notification state as going to wait for data. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one reader. */ + configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL ); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ); + sbRECEIVE_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ); + mtCOVERAGE_TEST_MARKER(); + } + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xBytesAvailable, xOriginalTail; + configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + * required to hold the length of the next message, so another message + * is available. Return its length without removing the length bytes + * from the buffer. A copy of the tail is stored so the buffer can be + * returned to its prior state as the message is not actually being + * removed from the buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable ); + xReturn = ( size_t ) xTempReturn; + pxStreamBuffer->xTail = xOriginalTail; + } + else + { + /* The minimum amount of bytes in a message buffer is + * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + * value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable, + size_t xBytesToStoreMessageLength ) +{ + size_t xOriginalTail, xReceivedLength, xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + + if( xBytesToStoreMessageLength != ( size_t ) 0 ) + { + /* A discrete message is being received. First receive the length + * of the message. A copy of the tail is stored so the buffer can be + * returned to its prior state if the length of the message is too + * large for the provided buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= xBytesToStoreMessageLength; + + /* Check there is enough space in the buffer provided by the + * user. */ + if( xNextMessageLength > xBufferLengthBytes ) + { + /* The user has provided insufficient space to read the message + * so return the buffer to its previous state (so the length of + * the message is in the buffer again). */ + pxStreamBuffer->xTail = xOriginalTail; + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Read the actual data. */ + xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + size_t xTail; + + configASSERT( pxStreamBuffer ); + + /* True if no bytes are available. */ + xTail = pxStreamBuffer->xTail; + + if( pxStreamBuffer->xHead == xTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) +{ + BaseType_t xReturn; + size_t xBytesToStoreMessageLength; + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + /* This generic version of the receive function is used by both message + * buffers, which store discrete messages, and stream buffers, which store a + * continuous stream of bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + /* True if the available space equals zero. */ + if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount ) +{ + size_t xNextHead, xFirstLength; + + configASSERT( xCount > ( size_t ) 0 ); + + xNextHead = pxStreamBuffer->xHead; + + /* Calculate the number of bytes that can be added in the first write - + * which may be less than the total number of bytes that need to be added if + * the buffer will wrap back to the beginning. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); + + /* Write as many bytes as can be written in the first write. */ + configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the number of bytes written was less than the number that could be + * written in the first write... */ + if( xCount > xFirstLength ) + { + /* ...then write the remaining bytes to the start of the buffer. */ + configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xNextHead += xCount; + + if( xNextHead >= pxStreamBuffer->xLength ) + { + xNextHead -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxStreamBuffer->xHead = xNextHead; + + return xCount; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xMaxCount, + size_t xBytesAvailable ) +{ + size_t xCount, xFirstLength, xNextTail; + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN( xBytesAvailable, xMaxCount ); + + if( xCount > ( size_t ) 0 ) + { + xNextTail = pxStreamBuffer->xTail; + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT( xFirstLength <= xMaxCount ); + configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if( xCount > xFirstLength ) + { + /*...then read the remaining bytes from the start of the buffer. */ + configASSERT( xCount <= xMaxCount ); + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from + * the buffer. */ + xNextTail += xCount; + + if( xNextTail >= pxStreamBuffer->xLength ) + { + xNextTail -= pxStreamBuffer->xLength; + } + + pxStreamBuffer->xTail = xNextTail; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) +{ +/* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + + if( xCount >= pxStreamBuffer->xLength ) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) +{ + /* Assert here is deliberately writing to the entire buffer to ensure it can + * be written to without generating exceptions, and is setting the buffer to a + * known value to assist in development/debugging. */ + #if ( configASSERT_DEFINED == 1 ) + { + /* The value written just has to be identifiable when looking at the + * memory. Don't use 0xA5 as that is the stack fill value and could + * result in confusion as to what is actually being observed. */ + const BaseType_t xWriteValue = 0x55; + configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); + } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ + #endif + + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + pxStreamBuffer->pucBuffer = pucBuffer; + pxStreamBuffer->xLength = xBufferSizeBytes; + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; + pxStreamBuffer->ucFlags = ucFlags; +} + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) + { + return xStreamBuffer->uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) + { + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) + { + return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/Libs/FreeRTOS/kernel/tasks.c b/Libs/FreeRTOS/kernel/tasks.c new file mode 100644 index 0000000..4a170e1 --- /dev/null +++ b/Libs/FreeRTOS/kernel/tasks.c @@ -0,0 +1,5408 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "stack_macros.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting + * functions but without including stdio.h here. */ +#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) + +/* At the bottom of this file are two optional functions that can be used + * to generate human readable text from the raw data generated by the + * uxTaskGetSystemState() function. Note the formatting functions are provided + * for convenience only, and are NOT considered part of the kernel. */ + #include +#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */ + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define taskYIELD_IF_USING_PREEMPTION() +#else + #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* Values that can be assigned to the ucNotifyState member of the TCB. */ +#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ +#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 ) +#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 ) + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5U ) + +/* Bits used to recored how a task's stack and TCB were allocated. */ +#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) +#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) +#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) + +/* If any of the following are set then task stacks are filled with a known + * value so the high water mark can be determined. If none of the following are + * set then don't fill the stack so there is no unnecessary dependency on memset. */ +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 +#else + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 +#endif + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskRUNNING_CHAR ( 'X' ) +#define tskBLOCKED_CHAR ( 'B' ) +#define tskREADY_CHAR ( 'R' ) +#define tskDELETED_CHAR ( 'D' ) +#define tskSUSPENDED_CHAR ( 'S' ) + +/* + * Some kernel aware debuggers require the data the debugger needs access to be + * global, rather than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + +/* The name allocated to the Idle task. This can be overridden by defining + * configIDLE_TASK_NAME in FreeRTOSConfig.h. */ +#ifndef configIDLE_TASK_NAME + #define configIDLE_TASK_NAME "IDLE" +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is + * performed in a generic way that is not optimised to any particular + * microcontroller architecture. */ + +/* uxTopReadyPriority holds the priority of the highest priority ready + * state task. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) \ + { \ + if( ( uxPriority ) > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = ( uxPriority ); \ + } \ + } /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority = uxTopReadyPriority; \ + \ + /* Find the highest priority queue that contains ready tasks. */ \ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \ + { \ + configASSERT( uxTopPriority ); \ + --uxTopPriority; \ + } \ + \ + /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \ + * the same priority get an equal share of the processor time. */ \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + uxTopReadyPriority = uxTopPriority; \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK */ + +/*-----------------------------------------------------------*/ + +/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as + * they are only required when a port optimised method of task selection is + * being used. */ + #define taskRESET_READY_PRIORITY( uxPriority ) + #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is + * performed in a way that is tailored to the particular microcontroller + * architecture being used. */ + +/* A port optimised version is provided. Call the port defined macros. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority; \ + \ + /* Find the highest priority list that contains ready tasks. */ \ + portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \ + configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK() */ + +/*-----------------------------------------------------------*/ + +/* A port optimised version is provided, call it only if the TCB being reset + * is being referenced from a ready list. If it is referenced from a delayed + * or suspended list then it won't be in a ready list. */ + #define taskRESET_READY_PRIORITY( uxPriority ) \ + { \ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \ + { \ + portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \ + } \ + } + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick + * count overflows. */ +#define taskSWITCH_DELAYED_LISTS() \ + { \ + List_t * pxTemp; \ + \ + /* The delayed tasks list should be empty when the lists are switched. */ \ + configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \ + \ + pxTemp = pxDelayedTaskList; \ + pxDelayedTaskList = pxOverflowDelayedTaskList; \ + pxOverflowDelayedTaskList = pxTemp; \ + xNumOfOverflows++; \ + prvResetNextTaskUnblockTime(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Place the task represented by pxTCB into the appropriate ready list for + * the task. It is inserted at the end of the list. + */ +#define prvAddTaskToReadyList( pxTCB ) \ + traceMOVED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +/*-----------------------------------------------------------*/ + +/* + * Several functions take an TaskHandle_t parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) + +/* The item value of the event list item is normally used to hold the priority + * of the task to which it belongs (coded to allow it to be held in reverse + * priority order). However, it is occasionally borrowed for other purposes. It + * is important its value is not updated due to a task priority change while it is + * being used for another purpose. The following bit definition is used to inform + * the scheduler that the value should not be changed - in which case it is the + * responsibility of whichever module is using the value to ensure it gets set back + * to its original value when it is released. */ +#if ( configUSE_16_BIT_TICKS == 1 ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U +#else + #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL +#endif + +/* + * Task control block. A task control block (TCB) is allocated for each task, + * and stores task state information, including a pointer to the task's context + * (the task's run time environment, including register values) + */ +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + + /* Allocate a Newlib reent structure that is specific to this task. + * Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. + * + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + struct _reent xNewLib_reent; + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + + /* See the comments in FreeRTOS.h with the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif +} tskTCB; + +/* The old tskTCB name is maintained above then typedefed to the new TCB_t name + * below to enable the use of older kernel aware debuggers. */ +typedef tskTCB TCB_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ +PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. -------------------- + * xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but + * doing so breaks some kernel aware debuggers and debuggers that rely on removing + * the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ + PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* Global POSIX errno. Its value is changed upon context switching to match + * the errno of the currently running task. */ +#if ( configUSE_POSIX_ERRNO == 1 ) + int FreeRTOS_errno = 0; +#endif + +/* Other file private variables. --------------------------------*/ +PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; +PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; +PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; +PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ + +/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. + * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority + * to determine the number of priority lists to read back from the remote target. */ +const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; + +/* Context switches are held pending while the scheduler is suspended. Also, + * interrupts must not manipulate the xStateListItem of a TCB, or any of the + * lists the xStateListItem can be referenced from, if the scheduler is suspended. + * If an interrupt needs to unblock a task while the scheduler is suspended then it + * moves the task's event list item into the xPendingReadyList, ready for the + * kernel to move the task from the pending ready list into the real ready list + * when the scheduler is unsuspended. The pending ready list itself can only be + * accessed from a critical section. */ +PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE; + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +/* Do not move these variables to function scope as doing so prevents the + * code working with debuggers that need to remove the static qualifier. */ + PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ + PRIVILEGED_DATA static volatile uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ + +#endif + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* File private functions. --------------------------------*/ + +/** + * Utility task that simply returns pdTRUE if the task referenced by xTask is + * currently in the Suspended state, or pdFALSE if the task referenced by xTask + * is in any other state. + */ +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +#endif /* INCLUDE_vTaskSuspend */ + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; + +/* + * The currently executing task is entering the Blocked state. Add the task to + * either the current or the overflow delayed task list. + */ +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * Fills an TaskStatus_t structure with information on each task that is + * referenced from the pxList list (which may be a ready list, a delayed list, + * a suspended list, etc.). + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Searches pxList for a task with name pcNameToQuery - returning a handle to + * the task if it is found, or NULL if the task is not found. + */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Return the amount of time, in ticks, that will pass before the kernel will + * next move a task from the Blocked state to the Running state. + * + * This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user + * defined low power mode implementations require configUSE_TICKLESS_IDLE to be + * set to a value other than 1. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Set xNextTaskUnblockTime to the time at which the next Blocked state task + * will exit the Blocked state. + */ +static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION; + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + +/* + * Helper function used to pad task names with spaces when printing out + * human readable tables of task information. + */ + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Called after a Task_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; + +/* + * Called after a new task has been created and initialised to place the task + * under the control of the scheduler. + */ +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; + +/* + * freertos_tasks_c_additions_init() should only be called if the user definable + * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro + * called by the function. + */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + + static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION; + +#endif + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + TCB_t * pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + configASSERT( pxTaskBuffer != NULL ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + } + #endif /* configASSERT_DEFINED */ + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + xReturn = NULL; + } + + return xReturn; + } + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + + return xReturn; + } + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + } + + return xReturn; + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ + #if ( portSTACK_GROWTH > 0 ) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + } + } + #else /* portSTACK_GROWTH */ + { + StackType_t * pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + + if( pxStack != NULL ) + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + + if( pxNewTCB != NULL ) + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + } + else + { + /* The stack cannot be used as the TCB was not created. Free + * it again. */ + vPortFree( pxStack ); + } + } + else + { + pxNewTCB = NULL; + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + { + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + StackType_t * pxTopOfStack; + UBaseType_t x; + + #if ( portUSING_MPU_WRAPPERS == 1 ) + /* Should the task be created in privileged mode? */ + BaseType_t xRunPrivileged; + + if( ( uxPriority & portPRIVILEGE_BIT ) != 0U ) + { + xRunPrivileged = pdTRUE; + } + else + { + xRunPrivileged = pdFALSE; + } + uxPriority &= ~portPRIVILEGE_BIT; + #endif /* portUSING_MPU_WRAPPERS == 1 */ + + /* Avoid dependency on memset() if it is not required. */ + #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + } + #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */ + + /* Calculate the top of stack address. This depends on whether the stack + * grows from high memory to low (as per the 80x86) or vice versa. + * portSTACK_GROWTH is used to make the result positive or negative as required + * by the port. */ + #if ( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + #if ( configRECORD_STACK_HIGH_ADDRESS == 1 ) + { + /* Also record the stack's high address, which may assist + * debugging. */ + pxNewTCB->pxEndOfStack = pxTopOfStack; + } + #endif /* configRECORD_STACK_HIGH_ADDRESS */ + } + #else /* portSTACK_GROWTH */ + { + pxTopOfStack = pxNewTCB->pxStack; + + /* Check the alignment of the stack buffer is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + /* The other extreme of the stack space is required if stack checking is + * performed. */ + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure the name string is terminated in the case that the string length + * was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + * terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + } + + /* This is used as an array index so must ensure it's not too large. First + * remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + pxNewTCB->uxMutexesHeld = 0; + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + * back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + { + pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U; + } + #endif /* portCRITICAL_NESTING_IN_TCB */ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + { + pxNewTCB->pxTaskTag = NULL; + } + #endif /* configUSE_APPLICATION_TASK_TAG */ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxNewTCB->ulRunTimeCounter = 0UL; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth ); + } + #else + { + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) xRegions; + } + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + { + memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) ); + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + memset( ( void * ) &( pxNewTCB->ulNotifiedValue[ 0 ] ), 0x00, sizeof( pxNewTCB->ulNotifiedValue ) ); + memset( ( void * ) &( pxNewTCB->ucNotifyState[ 0 ] ), 0x00, sizeof( pxNewTCB->ucNotifyState ) ); + } + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Initialise this task's Newlib reent structure. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); + } + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + pxNewTCB->ucDelayAborted = pdFALSE; + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + * but had been interrupted by the scheduler. The return address is set + * to the start of the task function. Once the stack has been initialised + * the top of stack variable is updated. */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #else /* portUSING_MPU_WRAPPERS */ + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + { + /* Pass the handle out in an anonymous way. The handle can be used to + * change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) +{ + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + + if( pxCurrentTCB == NULL ) + { + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( TaskHandle_t xTaskToDelete ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the calling task that is + * being deleted. */ + pxTCB = prvGetTCBFromHandle( xTaskToDelete ); + + /* Remove task from the ready/delayed list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Increment the uxTaskNumber also so kernel aware debuggers can + * detect that the task lists need re-generating. This is done before + * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will + * not return. */ + uxTaskNumber++; + + if( pxTCB == pxCurrentTCB ) + { + /* A task is deleting itself. This cannot complete within the + * task itself, as a context switch to another task is required. + * Place the task in the termination list. The idle task will + * check the termination list and free up any memory allocated by + * the scheduler for the TCB and stack of the deleted task. */ + vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + * there is a task that has been deleted and that it should therefore + * check the xTasksWaitingTermination list. */ + ++uxDeletedTasksWaitingCleanUp; + + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + + /* The pre-delete hook is primarily for the Windows simulator, + * in which Windows specific clean up operations are performed, + * after which it is not possible to yield away from this task - + * hence xYieldPending is used to latch that a context switch is + * required. */ + portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending ); + } + else + { + --uxCurrentNumberOfTasks; + traceTASK_DELETE( pxTCB ); + prvDeleteTCB( pxTCB ); + + /* Reset the next expected unblock time in case it referred to + * the task that has just been deleted. */ + prvResetNextTaskUnblockTime(); + } + } + taskEXIT_CRITICAL(); + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + if( xSchedulerRunning != pdFALSE ) + { + if( pxTCB == pxCurrentTCB ) + { + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) + { + TickType_t xTimeToWake; + BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + + configASSERT( pxPreviousWakeTime ); + configASSERT( ( xTimeIncrement > 0U ) ); + configASSERT( uxSchedulerSuspended == 0 ); + + vTaskSuspendAll(); + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount; + + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xConstTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + * lasted called. In this case the only time we should ever + * actually delay is if the wake time has also overflowed, + * and the wake time is greater than the tick time. When this + * is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The tick time has not overflowed. In this case we will + * delay if either the wake time has overflowed, and/or the + * tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay != pdFALSE ) + { + traceTASK_DELAY_UNTIL( xTimeToWake ); + + /* prvAddCurrentTaskToDelayedList() needs the block time, not + * the time to wake, so subtract the current tick count. */ + prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xShouldDelay; + } + +#endif /* INCLUDE_xTaskDelayUntil */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + BaseType_t xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + { + configASSERT( uxSchedulerSuspended == 0 ); + vTaskSuspendAll(); + { + traceTASK_DELAY(); + + /* A task that is removed from the event list while the + * scheduler is suspended will not get placed in the ready + * list or removed from the blocked list until the scheduler + * is resumed. + * + * This task cannot be in an event list as it is the currently + * executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + } + xAlreadyYielded = xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskDelay */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + + eTaskState eTaskGetState( TaskHandle_t xTask ) + { + eTaskState eReturn; + List_t const * pxStateList, * pxDelayedList, * pxOverflowedDelayedList; + const TCB_t * const pxTCB = xTask; + + configASSERT( pxTCB ); + + if( pxTCB == pxCurrentTCB ) + { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } + else + { + taskENTER_CRITICAL(); + { + pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; + } + taskEXIT_CRITICAL(); + + if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) ) + { + /* The task being queried is referenced from one of the Blocked + * lists. */ + eReturn = eBlocked; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( pxStateList == &xSuspendedTaskList ) + { + /* The task being queried is referenced from the suspended + * list. Is it genuinely suspended or is it blocked + * indefinitely? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ) + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + eReturn = eSuspended; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + eReturn = eBlocked; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + eReturn = eSuspended; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + else + { + eReturn = eBlocked; + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + + #if ( INCLUDE_vTaskDelete == 1 ) + else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) ) + { + /* The task being queried is referenced from the deleted + * tasks list, or it is not referenced from any lists at + * all. */ + eReturn = eDeleted; + } + #endif + + else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */ + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + + return eReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_eTaskGetState */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the task + * that called uxTaskPriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn, uxSavedInterruptState; + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + uxReturn = pxTCB->uxPriority; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) + { + TCB_t * pxTCB; + UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + + configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) ); + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being changed. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + traceTASK_PRIORITY_SET( pxTCB, uxNewPriority ); + + #if ( configUSE_MUTEXES == 1 ) + { + uxCurrentBasePriority = pxTCB->uxBasePriority; + } + #else + { + uxCurrentBasePriority = pxTCB->uxPriority; + } + #endif + + if( uxCurrentBasePriority != uxNewPriority ) + { + /* The priority change may have readied a task of higher + * priority than the calling task. */ + if( uxNewPriority > uxCurrentBasePriority ) + { + if( pxTCB != pxCurrentTCB ) + { + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if( uxNewPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ + } + } + else if( pxTCB == pxCurrentTCB ) + { + /* Setting the priority of the running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + xYieldRequired = pdTRUE; + } + else + { + /* Setting the priority of any other task down does not + * require a yield as the running task must be above the + * new priority of the task being modified. */ + } + + /* Remember the ready list the task might be referenced from + * before its uxPriority member is changed so the + * taskRESET_READY_PRIORITY() macro can function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + #if ( configUSE_MUTEXES == 1 ) + { + /* Only change the priority being used if the task is not + * currently using an inherited priority. */ + if( pxTCB->uxBasePriority == pxTCB->uxPriority ) + { + pxTCB->uxPriority = uxNewPriority; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxTCB->uxPriority = uxNewPriority; + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to it's new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + ( void ) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); + } + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( TaskHandle_t xTaskToSuspend ) + { + TCB_t * pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the running task that is + * being suspended. */ + pxTCB = prvGetTCBFromHandle( xTaskToSuspend ); + + traceTASK_SUSPEND( pxTCB ); + + /* Remove task from the ready/delayed list and place in the + * suspended list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ); + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + /* The task was blocked to wait for a notification, but is + * now suspended, so no notification was received. */ + pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION; + } + } + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( pxTCB == pxCurrentTCB ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */ + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } + else + { + vTaskSwitchContext(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) + { + BaseType_t xReturn = pdFALSE; + const TCB_t * const pxTCB = xTask; + + /* Accesses xPendingReadyList so must be called from a critical + * section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT( xTask ); + + /* Is the task being resumed actually in the suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) + { + /* Is it in the suspended list because it is in the Suspended + * state, or because is is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */ + { + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( TaskHandle_t xTaskToResume ) + { + TCB_t * const pxTCB = xTaskToResume; + + /* It does not make sense to resume the calling task. */ + configASSERT( xTaskToResume ); + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + { + taskENTER_CRITICAL(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME( pxTCB ); + + /* The ready list can be accessed even if the scheduler is + * suspended because this is inside a critical section. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* A higher priority task may have just been resumed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* INCLUDE_vTaskSuspend */ + +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) + { + BaseType_t xYieldRequired = pdFALSE; + TCB_t * const pxTCB = xTaskToResume; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToResume ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME_FROM_ISR( pxTCB ); + + /* Check the ready lists can be accessed. */ + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using portYIELD_FROM_ISR. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed or ready lists cannot be accessed so the task + * is held in the pending ready list until the scheduler is + * unsuspended. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xYieldRequired; + } + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxIdleTaskTCBBuffer = NULL; + StackType_t * pxIdleTaskStackBuffer = NULL; + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); + xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, + configIDLE_TASK_NAME, + ulIdleTaskStackSize, + ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if( xIdleTaskHandle != NULL ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( prvIdleTask, + configIDLE_TASK_NAME, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + { + xReturn = xTimerCreateTimerTask(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + { + /* freertos_tasks_c_additions_init() should only be called if the user + * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is + * the only macro called by the function. */ + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + { + freertos_tasks_c_additions_init(); + } + #endif + + /* Interrupts are turned off here, to ensure a tick does not occur + * before or during the call to xPortStartScheduler(). The stacks of + * the created tasks contain a status word with interrupts switched on + * so interrupts will automatically get re-enabled when the first task + * starts to run. */ + portDISABLE_INTERRUPTS(); + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to the task that will run first. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + xSchedulerRunning = pdTRUE; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + + /* If configGENERATE_RUN_TIME_STATS is defined then the following + * macro must be defined to configure the timer/counter used to generate + * the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS + * is set to 0 and the following line fails to build then ensure you do not + * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your + * FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + * portable interface. */ + if( xPortStartScheduler() != pdFALSE ) + { + /* Should not reach here as if the scheduler is running the + * function will not return. */ + } + else + { + /* Should only reach here if a task calls xTaskEndScheduler(). */ + } + } + else + { + /* This line will only be reached if the kernel could not be started, + * because there was not enough FreeRTOS heap to create the idle task + * or the timer task. */ + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + * meaning xIdleTaskHandle is not used anywhere else. */ + ( void ) xIdleTaskHandle; + + /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority + * from getting optimized out as it is no longer used by the kernel. */ + ( void ) uxTopUsedPriority; +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + /* Stop the scheduler interrupts and call the portable scheduler end + * routine so the original ISRs can be restored if necessary. The port + * layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + /* A critical section is not required as the variable is of type + * BaseType_t. Please read Richard Barry's reply in the following link to a + * post in the FreeRTOS support forum before reporting this as a bug! - + * https://goo.gl/wu4acr */ + + /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); +} +/*----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) + { + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + + /* uxHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + { + xReturn = 0; + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + { + /* There are other idle priority tasks in the ready state. If + * time slicing is used then the very next tick interrupt must be + * processed. */ + xReturn = 0; + } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } + else + { + xReturn = xNextTaskUnblockTime - xTickCount; + } + + return xReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + TCB_t * pxTCB = NULL; + BaseType_t xAlreadyYielded = pdFALSE; + + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + { + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* If the moved task has a priority higher than the current + * task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); + } + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if( xPendedCounts > ( TickType_t ) 0U ) + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + { + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); + + xPendedTicks = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + { + #if ( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xAlreadyYielded; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR( void ) +{ + TickType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = xTickCount; + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxTaskGetNumberOfTasks( void ) +{ + /* A critical section is not required because the variables are of type + * BaseType_t. */ + return uxCurrentNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +{ + TCB_t * pxTCB; + + /* If null is passed in here then the name of the calling task is being + * queried. */ + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB ); + return &( pxTCB->pcTaskName[ 0 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + cNextChar = pxNextTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxNextTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } + } + + if( pxReturn != NULL ) + { + /* The handle has been found. */ + break; + } + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t uxQueue = configMAX_PRIORITIES; + TCB_t * pxTCB; + + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ + configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); + + vTaskSuspendAll(); + { + /* Search the ready lists. */ + do + { + uxQueue--; + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery ); + + if( pxTCB != NULL ) + { + /* Found the handle. */ + break; + } + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Search the delayed lists. */ + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery ); + } + + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery ); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the suspended list. */ + pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery ); + } + } + #endif + + #if ( INCLUDE_vTaskDelete == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the deleted list. */ + pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery ); + } + } + #endif + } + ( void ) xTaskResumeAll(); + + return pxTCB; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t * const pulTotalRunTime ) + { + UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + + vTaskSuspendAll(); + { + /* Is there a space in the array for each task in the system? */ + if( uxArraySize >= uxCurrentNumberOfTasks ) + { + /* Fill in an TaskStatus_t structure with information on each + * task in the Ready state. */ + do + { + uxQueue--; + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ); + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Fill in an TaskStatus_t structure with information on each + * task in the Blocked state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ); + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task that has been deleted but not yet cleaned up. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task in the Suspended state. */ + uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ); + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + if( pulTotalRunTime != NULL ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) ); + #else + *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + } + } + #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + { + if( pulTotalRunTime != NULL ) + { + *pulTotalRunTime = 0; + } + } + #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandle will be NULL. */ + configASSERT( ( xIdleTaskHandle != NULL ) ); + return xIdleTaskHandle; + } + +#endif /* INCLUDE_xTaskGetIdleTaskHandle */ +/*----------------------------------------------------------*/ + +/* This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure vTaskStepTick() is available when user defined low power mode + * implementations require configUSE_TICKLESS_IDLE to be set to a value other than + * 1. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + void vTaskStepTick( const TickType_t xTicksToJump ) + { + /* Correct the tick count value after a period during which the tick + * was suppressed. Note this does *not* call the tick hook function for + * each stepped tick. */ + configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + xTickCount += xTicksToJump; + traceINCREASE_TICK_COUNT( xTicksToJump ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) +{ + BaseType_t xYieldOccurred; + + /* Must not be called with the scheduler suspended as the implementation + * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT( uxSchedulerSuspended == 0 ); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + xPendedTicks += xTicksToCatchUp; + xYieldOccurred = xTaskResumeAll(); + + return xYieldOccurred; +} +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) + { + TCB_t * pxTCB = xTask; + BaseType_t xReturn; + + configASSERT( pxTCB ); + + vTaskSuspendAll(); + { + /* A task can only be prematurely removed from the Blocked state if + * it is actually in the Blocked state. */ + if( eTaskGetState( xTask ) == eBlocked ) + { + xReturn = pdPASS; + + /* Remove the reference to the task from the blocked list. An + * interrupt won't touch the xStateListItem because the + * scheduler is suspended. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove it from + * the event list too. Interrupts can touch the event list item, + * even though the scheduler is suspended, so a critical section + * is used. */ + taskENTER_CRITICAL(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + * blocked state so it should not re-evaluate its block time and + * then block again. */ + pxTCB->ucDelayAborted = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* Place the unblocked task into the appropriate ready list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate context + * switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * equal to or higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + xReturn = pdFAIL; + } + } + ( void ) xTaskResumeAll(); + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + TCB_t * pxTCB; + TickType_t xItemValue; + BaseType_t xSwitchRequired = pdFALSE; + + /* Called by the portable layer each time a tick interrupt occurs. + * Increments the tick then checks to see if the new tick value will cause any + * tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + + /* Increment the RTOS tick, switching the delayed and overflowed + * delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + { + taskSWITCH_DELAYED_LISTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* See if this tick has made a timeout expire. Tasks are stored in + * the queue in the order of their wake time - meaning once one task + * has been found whose block time has not expired there is no need to + * look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + { + for( ; ; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The delayed list is empty. Set xNextTaskUnblockTime + * to the maximum possible value so it is extremely + * unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass + * next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + break; + } + else + { + /* The delayed list is not empty, get the value of the + * item at the head of the delayed list. This is the time + * at which the task at the head of the delayed list must + * be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + + if( xConstTickCount < xItemValue ) + { + /* It is not time to unblock this item yet, but the + * item value is the time at which the task at the head + * of the blocked list must be removed from the Blocked + * state - so record the item value in + * xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove + * it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + * list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate + * context switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should + * only be performed if the unblocked task has a + * priority that is equal to or higher than the + * currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + } + } + + /* Tasks of equal priority to the currently running task will share + * processing time (time slice) if preemption is on, and the application + * writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + + #if ( configUSE_TICK_HOOK == 1 ) + { + /* Guard against the tick hook being called when the pended tick + * count is being unwound (when the scheduler is being unlocked). */ + if( xPendedTicks == ( TickType_t ) 0 ) + { + vApplicationTickHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + ++xPendedTicks; + + /* The tick hook gets called at regular intervals, even if the + * scheduler is locked. */ + #if ( configUSE_TICK_HOOK == 1 ) + { + vApplicationTickHook(); + } + #endif + } + + return xSwitchRequired; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) + { + TCB_t * xTCB; + + /* If xTask is NULL then it is the task hook of the calling task that is + * getting set. */ + if( xTask == NULL ) + { + xTCB = ( TCB_t * ) pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xTCB->pxTaskTag = pxHookFunction; + } + taskEXIT_CRITICAL(); + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) + { + TCB_t * xTCB; + BaseType_t xReturn; + + /* If xTask is NULL then we are calling our own task hook. */ + if( xTask == NULL ) + { + xTCB = pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + if( xTCB->pxTaskTag != NULL ) + { + xReturn = xTCB->pxTaskTag( pvParameter ); + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPending = pdTRUE; + } + else + { + xYieldPending = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); + #else + ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime > ulTaskSwitchedInTime ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime = ulTotalRunTime; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + traceTASK_SWITCHED_IN(); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to this task. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE + * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ + + /* Place the event list item of the TCB in the appropriate event list. + * This is placed in the list in priority order so the highest priority task + * is the first to be woken by the event. The queue that contains the event + * list is locked, preventing simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) +{ + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + configASSERT( uxSchedulerSuspended != 0 ); + + /* Store the item value in the event list item. It is safe to access the + * event list item here as interrupts won't access the event list item of a + * task that is not in the Blocked state. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Place the event list item of the TCB at the end of the appropriate event + * list. It is safe to access the event list here because it is part of an + * event group implementation - and interrupts don't access event groups + * directly (instead they access them indirectly by pending function calls to + * the task level). */ + vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + configASSERT( pxEventList ); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements - + * it should be called with the scheduler suspended. */ + + + /* Place the event list item of the TCB in the appropriate event list. + * In this case it is assume that this is the only task that is going to + * be waiting on this event list, so the faster vListInsertEnd() function + * can be used in place of vListInsert. */ + vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + /* If the task should block indefinitely then set the block time to a + * value that will be recognised as an indefinite delay inside the + * prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + { + xTicksToWait = portMAX_DELAY; + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + TCB_t * pxUnblockedTCB; + BaseType_t xReturn; + + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be + * called from a critical section within an ISR. */ + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) +{ + TCB_t * pxUnblockedTCB; + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event flags implementation. */ + configASSERT( uxSchedulerSuspended != pdFALSE ); + + /* Store the new item value in the event list. */ + listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Remove the event list form the event flag. Interrupts do not access + * event flags. */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT( pxUnblockedTCB ); + ( void ) uxListRemove( pxEventListItem ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + /* Remove the task from the delayed list and add it to the ready list. The + * scheduler is suspended so interrupts will not be accessing the ready + * lists. */ + ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPending = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + configASSERT( pxTimeOut ); + taskENTER_CRITICAL(); + { + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) +{ + BaseType_t xReturn; + + configASSERT( pxTimeOut ); + configASSERT( pxTicksToWait ); + + taskENTER_CRITICAL(); + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + { + /* The delay was aborted, which is not the same as a time out, + * but has the same result. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + xReturn = pdTRUE; + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + * specified is the maximum block time then the task should block + * indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + { + /* The tick count is greater than the time at which + * vTaskSetTimeout() was called, but has also overflowed since + * vTaskSetTimeOut() was called. It must have wrapped all the way + * around and gone past again. This passed since vTaskSetTimeout() + * was called. */ + xReturn = pdTRUE; + *pxTicksToWait = ( TickType_t ) 0; + } + else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + vTaskInternalSetTimeOutState( pxTimeOut ); + xReturn = pdFALSE; + } + else + { + *pxTicksToWait = ( TickType_t ) 0; + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + xYieldPending = pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) + { + UBaseType_t uxReturn; + TCB_t const * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + uxReturn = pxTCB->uxTaskNumber; + } + else + { + uxReturn = 0U; + } + + return uxReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) + { + TCB_t * pxTCB; + + if( xTask != NULL ) + { + pxTCB = xTask; + pxTCB->uxTaskNumber = uxHandle; + } + } + +#endif /* configUSE_TRACE_FACILITY */ + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE + * SCHEDULER IS STARTED. **/ + + /* In case a task that has a secure context deletes itself, in which case + * the idle task is responsible for deleting the task's secure context, if + * any. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + for( ; ; ) + { + /* See if any tasks have deleted themselves - if so then the idle task + * is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains more than one task + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_IDLE_HOOK == 1 ) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } + #endif /* configUSE_IDLE_HOOK */ + + /* This conditional compilation should use inequality to 0, not equality + * to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when + * user defined low power mode implementations require + * configUSE_TICKLESS_IDLE to be set to a value other than 1. */ + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + TickType_t xExpectedIdleTime; + + /* It is not desirable to suspend then resume the scheduler on + * each iteration of the idle task. Therefore, a preliminary + * test of the expected idle time is performed without the + * scheduler suspended. The result here is not necessarily + * valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + vTaskSuspendAll(); + { + /* Now the scheduler is suspended, the expected idle + * time can be sampled again, and this time its value can + * be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + xExpectedIdleTime = prvGetExpectedIdleTime(); + + /* Define the following macro to set xExpectedIdleTime to 0 + * if the application does not want + * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + traceLOW_POWER_IDLE_END(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICKLESS_IDLE */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = 1; + eSleepModeStatus eReturn = eStandardSleep; + + /* This function must be called from a critical section. */ + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xYieldPending != pdFALSE ) + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xPendedTicks != 0 ) + { + /* A tick interrupt has already occurred but was held pending + * because the scheduler is suspended. */ + eReturn = eAbortSleep; + } + else + { + /* If all the tasks are in the suspended list (which might mean they + * have an infinite block time rather than actually being suspended) + * then it is safe to turn all clocks off and just wait for external + * interrupts. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + { + eReturn = eNoTasksWaitingTimeout; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return eReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) + { + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); + pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; + } + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) + { + void * pvReturn = NULL; + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; + } + else + { + pvReturn = NULL; + } + + return pvReturn; + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) + { + TCB_t * pxTCB; + + /* If null is passed in here then we are modifying the MPU settings of + * the calling task. */ + pxTCB = prvGetTCBFromHandle( xTaskToModify ); + + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( &xDelayedTaskList1 ); + vListInitialise( &xDelayedTaskList2 ); + vListInitialise( &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + * using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/ + + #if ( INCLUDE_vTaskDelete == 1 ) + { + TCB_t * pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + * being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + taskENTER_CRITICAL(); + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + taskEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + } + #endif /* INCLUDE_vTaskDelete */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) + { + TCB_t * pxTCB; + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB; + pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); + pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; + pxTaskStatus->pxStackBase = pxTCB->pxStack; + pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + + #if ( configUSE_MUTEXES == 1 ) + { + pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; + } + #else + { + pxTaskStatus->uxBasePriority = 0; + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter; + } + #else + { + pxTaskStatus->ulRunTimeCounter = 0; + } + #endif + + /* Obtaining the task state is a little fiddly, so is only done if the + * value of eState passed into this function is eInvalid - otherwise the + * state is just set to whatever is passed in. */ + if( eState != eInvalid ) + { + if( pxTCB == pxCurrentTCB ) + { + pxTaskStatus->eCurrentState = eRunning; + } + else + { + pxTaskStatus->eCurrentState = eState; + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* If the task is in the suspended list then there is a + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ + if( eState == eSuspended ) + { + vTaskSuspendAll(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + pxTaskStatus->eCurrentState = eBlocked; + } + } + ( void ) xTaskResumeAll(); + } + } + #endif /* INCLUDE_vTaskSuspend */ + } + } + else + { + pxTaskStatus->eCurrentState = eTaskGetState( pxTCB ); + } + + /* Obtaining the stack space takes some time, so the xGetFreeStackSpace + * parameter is provided to allow it to be skipped. */ + if( xGetFreeStackSpace != pdFALSE ) + { + #if ( portSTACK_GROWTH > 0 ) + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack ); + } + #else + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack ); + } + #endif + } + else + { + pxTaskStatus->usStackHighWaterMark = 0; + } + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) + { + configLIST_VOLATILE TCB_t * pxNextTCB, * pxFirstTCB; + UBaseType_t uxTask = 0; + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Populate an TaskStatus_t structure within the + * pxTaskStatusArray array for each task that is referenced from + * pxList. See the definition of TaskStatus_t in task.h for the + * meaning of each TaskStatus_t structure member. */ + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); + uxTask++; + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) + { + uint32_t ulCount = 0U; + + while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + ulCount++; + } + + ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */ + + return ( configSTACK_DEPTH_TYPE ) ulCount; + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + +/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + * the same except for their return type. Using configSTACK_DEPTH_TYPE + * allows the user to determine the return type. It gets around the + * problem of the value overflowing on 8-bit types without breaking + * backward compatibility for applications that expect an 8-bit return + * type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + UBaseType_t uxReturn; + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) + { + /* This call is required specifically for the TriCore port. It must be + * above the vPortFree() calls. The call is also used by ports/demos that + * want to allocate and clean RAM statically. */ + portCLEAN_UP_TCB( pxTCB ); + + /* Free up the memory allocated by the scheduler for the task. It is up + * to the task to free any memory allocated at the application level. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + { + _reclaim_reent( &( pxTCB->xNewLib_reent ) ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + { + /* The task can only have been allocated dynamically - free both + * the stack and TCB. */ + vPortFree( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + * check what was statically allocated before trying to free the + * memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + { + /* Both the stack and TCB were allocated dynamically, so both + * must be freed. */ + vPortFree( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + { + /* Only the stack was statically allocated, so the TCB is the + * only memory that must be freed. */ + vPortFree( pxTCB ); + } + else + { + /* Neither the stack nor the TCB were allocated dynamically, so + * nothing needs to be freed. */ + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + * the maximum possible value so it is extremely unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass until + * there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + } + else + { + /* The new current delayed list is not empty, get the value of + * the item at the head of the delayed list. This is the time at + * which the task at the head of the delayed list should be removed + * from the Blocked state. */ + xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + BaseType_t xReturn; + + if( xSchedulerRunning == pdFALSE ) + { + xReturn = taskSCHEDULER_NOT_STARTED; + } + else + { + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + /* If the mutex was given back by an interrupt while the queue was + * locked then the mutex holder might now be NULL. _RB_ Is this still + * needed as interrupts can no longer use mutexes? */ + if( pxMutexHolder != NULL ) + { + /* If the holder of the mutex has a priority below the priority of + * the task attempting to obtain the mutex then it will temporarily + * inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + { + /* Adjust the mutex holder state to account for its new + * priority. Only reset the event list item value if the value is + * not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + * to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + prvAddTaskToReadyList( pxMutexHolderTCB ); + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + { + /* The base priority of the mutex holder is lower than the + * priority of the task attempting to take the mutex, but the + * current priority of the mutex holder is not lower than the + * priority of the task attempting to take the mutex. + * Therefore the mutex holder must have already inherited a + * priority, but inheritance would have occurred if that had + * not been the case. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + if( pxMutexHolder != NULL ) + { + /* A task can only have an inherited priority if it holds the mutex. + * If the mutex is held by a task then it cannot be given from an + * interrupt, and if a mutex is given by the holding task then it must + * be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + configASSERT( pxTCB->uxMutexesHeld ); + ( pxTCB->uxMutexesHeld )--; + + /* Has the holder of the mutex inherited the priority of another + * task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + { + /* A task can only have an inherited priority if it holds + * the mutex. If the mutex is held by a task then it cannot be + * given from an interrupt, and if a mutex is given by the + * holding task then it must be the running state task. Remove + * the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Disinherit the priority before adding the task into the + * new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + + /* Reset the event list item value. It cannot be in use for + * any other purpose if this task is running, and it must be + * running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + prvAddTaskToReadyList( pxTCB ); + + /* Return true to indicate that a context switch is required. + * This is only actually required in the corner case whereby + * multiple mutexes were held and the mutexes were given back + * in an order different to that in which they were taken. + * If a context switch did not occur when the first mutex was + * returned, even if a task was waiting on it, then a context + * switch should occur when the last mutex is returned whether + * a task is waiting on it or not. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) + { + TCB_t * const pxTCB = pxMutexHolder; + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + + if( pxMutexHolder != NULL ) + { + /* If pxMutexHolder is not NULL then the holder must hold at least + * one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + + /* Determine the priority to which the priority of the task that + * holds the mutex should be set. This will be the greater of the + * holding task's base priority and the priority of the highest + * priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + { + /* Only disinherit if no other mutexes are held. This is a + * simplification in the priority inheritance implementation. If + * the task that holds the mutex is also holding other mutexes then + * the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + { + /* If a task has timed out because it already holds the + * mutex it was trying to obtain then it cannot of inherited + * its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + + /* Disinherit the priority, remembering the previous + * priority to facilitate determining the subject task's + * state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + pxTCB->uxPriority = uxPriorityToUse; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the running task is not the task that holds the mutex + * then the task that holds the mutex could be in either the + * Ready, Blocked or Suspended states. Only remove the task + * from its current state list if it is in the Ready state as + * the task's priority is going to change and there is one + * Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1 ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( portCRITICAL_NESTING_IN_TCB == 1 ) + + void vTaskExitCritical( void ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) + { + size_t x; + + /* Start by copying the entire string. */ + strcpy( pcBuffer, pcTaskName ); + + /* Pad the end of the string with spaces to ensure columns line up when + * printed out. */ + for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ ) + { + pcBuffer[ x ] = ' '; + } + + /* Terminate. */ + pcBuffer[ x ] = ( char ) 0x00; + + /* Return the new end of string. */ + return &( pcBuffer[ x ] ); + } + +#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + void vTaskList( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + char cStatus; + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that + * displays task names, states and stack usage. + * + * vTaskList() has a dependency on the sprintf() C library function that + * might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, + * and limited functionality implementation of sprintf() is provided in + * many of the FreeRTOS/Demo sub-directories in a file called + * printf-stdarg.c (note printf-stdarg.c does not provide a full + * snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskList(). + */ + + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! if + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL ); + + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + switch( pxTaskStatusArray[ x ].eCurrentState ) + { + case eRunning: + cStatus = tskRUNNING_CHAR; + break; + + case eReady: + cStatus = tskREADY_CHAR; + break; + + case eBlocked: + cStatus = tskBLOCKED_CHAR; + break; + + case eSuspended: + cStatus = tskSUSPENDED_CHAR; + break; + + case eDeleted: + cStatus = tskDELETED_CHAR; + break; + + case eInvalid: /* Fall through. */ + default: /* Should not get here, but it is included + * to prevent static checking errors. */ + cStatus = ( char ) 0x00; + break; + } + + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + /* Write the rest of the string. */ + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + void vTaskGetRunTimeStats( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + uint32_t ulTotalTime, ulStatsAsPercentage; + + #if ( configUSE_TRACE_FACILITY != 1 ) + { + #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats(). + } + #endif + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part + * of the uxTaskGetSystemState() output into a human readable table that + * displays the amount of time each task has spent in the Running state + * in both absolute and percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library + * function that might bloat the code size, use a lot of stack, and + * provide different results on different platforms. An alternative, + * tiny, third party, and limited functionality implementation of + * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * a file called printf-stdarg.c (note printf-stdarg.c does not provide + * a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskGetRunTimeStats(). + */ + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! If + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); + + /* For percentage calculations. */ + ulTotalTime /= 100UL; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > 0UL ) + { + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + /* What percentage of the total run time has the task used? + * This will always be rounded down to the nearest integer. + * ulTotalRunTimeDiv100 has already been divided by 100. */ + ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; + + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + if( ulStatsAsPercentage > 0UL ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +TickType_t uxTaskResetEventItemValue( void ) +{ + TickType_t uxReturn; + + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) ); + + /* Reset the event list item to its normal value - so it can be used with + * queues and semaphores. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + /* If xSemaphoreCreateMutex() is called before any tasks have been created + * then pxCurrentTCB will be NULL. */ + if( pxCurrentTCB != NULL ) + { + ( pxCurrentTCB->uxMutexesHeld )++; + } + + return pxCurrentTCB; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) + { + uint32_t ulReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if the notification count is not already non-zero. */ + if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL ) + { + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_TAKE( uxIndexToWait ); + ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + + if( ulReturn != 0UL ) + { + if( xClearCountOnExit != pdFALSE ) + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL; + } + else + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + + configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + taskENTER_CRITICAL(); + { + /* Only block if a notification is not already pending. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used to + * clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION; + + if( xTicksToWait > ( TickType_t ) 0 ) + { + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_WAIT( uxIndexToWait ); + + if( pulNotificationValue != NULL ) + { + /* Output the current notification value, which may or may not + * have changed. */ + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ]; + } + + /* If ucNotifyValue is set then either the task never entered the + * blocked state (because a notification was already pending) or the + * task unblocked because of a notification. Otherwise the task + * unblocked because of a timeout. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED ) + { + /* A notification was not received. */ + xReturn = pdFALSE; + } + else + { + /* A notification was already pending or a notification was + * received while the task was waiting. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit; + xReturn = pdTRUE; + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) + { + TCB_t * pxTCB; + BaseType_t xReturn = pdPASS; + uint8_t ucOriginalNotifyState; + + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + configASSERT( xTaskToNotify ); + pxTCB = xTaskToNotify; + + taskENTER_CRITICAL(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + + break; + } + + traceTASK_NOTIFY( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + taskYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + BaseType_t xReturn = pdPASS; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + break; + } + + traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + /* 'Giving' is equivalent to incrementing a count in a counting + * semaphore. */ + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + + traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + { + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) + { + TCB_t * pxTCB; + BaseType_t xReturn; + + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED ) + { + pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION; + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) + { + TCB_t * pxTCB; + uint32_t ulReturn; + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + * then clear the bit mask. */ + ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ]; + pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + uint32_t ulTaskGetIdleRunTimeCounter( void ) + { + return xIdleTaskHandle->ulRunTimeCounter; + } + +#endif +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) +{ + TickType_t xTimeToWake; + const TickType_t xConstTickCount = xTickCount; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + * reset to pdFALSE so it can be detected as having been set to pdTRUE + * when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + * as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* The current task must be in a ready list, so there is no need to + * check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + { + /* Add the task to the suspended task list instead of a delayed task + * list to ensure it is not woken by a timing event. It will block + * indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the + * kernel will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow + * list. */ + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list + * is used. */ + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the + * head of the list of blocked tasks then xNextTaskUnblockTime + * needs to be updated too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } + #else /* INCLUDE_vTaskSuspend */ + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the kernel + * will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list is used. */ + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the head of the + * list of blocked tasks then xNextTaskUnblockTime needs to be updated + * too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + +/* Code below here allows additional code to be inserted into this source file, + * especially where access to file scope functions and data is needed (for example + * when performing module tests). */ + +#ifdef FREERTOS_MODULE_TEST + #include "tasks_test_access_functions.h" +#endif + + +#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) + + #include "freertos_tasks_c_additions.h" + + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { + FREERTOS_TASKS_C_ADDITIONS_INIT(); + } + #endif + +#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ diff --git a/Libs/FreeRTOS/kernel/timers.c b/Libs/FreeRTOS/kernel/timers.c new file mode 100644 index 0000000..ab09c2c --- /dev/null +++ b/Libs/FreeRTOS/kernel/timers.c @@ -0,0 +1,1157 @@ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 ) + #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ + + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. This #if is closed at the very bottom + * of this file. If you want to include software timer functionality then ensure + * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_TIMERS == 1 ) + +/* Misc definitions. */ + #define tmrNO_DELAY ( TickType_t ) 0U + +/* The name assigned to the timer service task. This can be overridden by + * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_NAME + #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" + #endif + +/* Bit definitions used in the ucStatus member of a timer structure. */ + #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) + #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + +/* The definition of the timers themselves. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + const char * pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /*<< How quickly and often the timer expires. */ + void * pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */ + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */ + #endif + uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + } xTIMER; + +/* The old xTIMER name is maintained above then typedefed to the new Timer_t + * name below to enable the use of older kernel aware debuggers. */ + typedef xTIMER Timer_t; + +/* The definition of messages that can be sent and received on the timer queue. + * Two types of message can be queued - messages that manipulate a software timer, + * and messages that request the execution of a non-timer related callback. The + * two message types are defined in two separate structures, xTimerParametersType + * and xCallbackParametersType respectively. */ + typedef struct tmrTimerParameters + { + TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ + } TimerParameter_t; + + + typedef struct tmrCallbackParameters + { + PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ + void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ + uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ + } CallbackParameters_t; + +/* The structure that contains the two message types, along with an identifier + * that is used to determine which message type is valid. */ + typedef struct tmrTimerQueueMessage + { + BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ + union + { + TimerParameter_t xTimerParameters; + + /* Don't include xCallbackParameters if it is not going to be used as + * it makes the structure (and therefore the timer queue) larger. */ + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + CallbackParameters_t xCallbackParameters; + #endif /* INCLUDE_xTimerPendFunctionCall */ + } u; + } DaemonTaskMessage_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ + +/* The list in which active timers are stored. Timers are referenced in expire + * time order, with the nearest expiry time at the front of the list. Only the + * timer service task is allowed to access these lists. + * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that + * breaks some kernel aware debuggers, and debuggers that reply on removing the + * static qualifier. */ + PRIVILEGED_DATA static List_t xActiveTimerList1; + PRIVILEGED_DATA static List_t xActiveTimerList2; + PRIVILEGED_DATA static List_t * pxCurrentTimerList; + PRIVILEGED_DATA static List_t * pxOverflowTimerList; + +/* A queue that is used to send commands to the timer service task. */ + PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; + PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* + * Initialise the infrastructure used by the timer service task if it has not + * been initialised already. + */ + static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; + +/* + * The timer service task (daemon). Timer functionality is controlled by this + * task. Other tasks communicate with the timer service task using the + * xTimerQueue queue. + */ + static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Called by the timer service task to interpret and process a command it + * received on the timer queue. + */ + static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; + +/* + * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, + * depending on if the expire time causes a timer counter overflow. + */ + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; + +/* + * An active timer has reached its expire time. Reload the timer if it is an + * auto-reload timer, then call its callback. + */ + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * The tick count has overflowed. Switch the timer lists after ensuring the + * current timer list does not still reference some timers. + */ + static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; + +/* + * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE + * if a tick count overflow occurred since prvSampleTimeNow() was last called. + */ + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; + +/* + * If the timer list contains any active timers then return the expire time of + * the timer that will expire first and set *pxListWasEmpty to false. If the + * timer list does not contain any timers then return 0 and set *pxListWasEmpty + * to pdTRUE. + */ + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * If a timer has expired, process it. Otherwise, block the timer service task + * until either a timer does expire or a command is received. + */ + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * Called after a Timer_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + + BaseType_t xTimerCreateTimerTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* This function is called when the scheduler is started if + * configUSE_TIMERS is set to 1. Check that the infrastructure used by the + * timer service task has been created/initialised. If timers have already + * been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + + if( xTimerQueue != NULL ) + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + Timer_t * pxNewTimer; + + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + + if( pxNewTimer != NULL ) + { + /* Status is thus far zero as the timer is not created statically + * and has not been started. The auto-reload bit may get set in + * prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) + { + Timer_t * pxNewTimer; + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTimer_t equals the size of the real timer + * structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + + if( pxNewTimer != NULL ) + { + /* Timers can be created statically or dynamically so note this + * timer was created statically in case it is later deleted. The + * auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) + { + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + + if( pxNewTimer != NULL ) + { + /* Ensure the infrastructure used by the timer service task has been + * created/initialised. */ + prvCheckForValidListAndQueue(); + + /* Initialise the timer structure members using the function + * parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + pxNewTimer->pvTimerID = pvTimerID; + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + + if( uxAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + + traceTIMER_CREATE( pxNewTimer ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( xTimerQueue != NULL ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) + { + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been + * started, then xTimerTaskHandle will be NULL. */ + configASSERT( ( xTimerTaskHandle != NULL ) ); + return xTimerTaskHandle; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->xTimerPeriodInTicks; + } +/*-----------------------------------------------------------*/ + + void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( uxAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD; + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + UBaseType_t uxReturn; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + { + /* Not an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + TickType_t xReturn; + + configASSERT( xTimer ); + xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->pcTimerName; + } +/*-----------------------------------------------------------*/ + + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) + { + BaseType_t xResult; + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Remove the timer from the list of active timers. A check has already + * been performed to ensure the list is not empty. */ + + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + traceTIMER_EXPIRED( pxTimer ); + + /* If the timer is an auto-reload timer then calculate the next + * expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + /* The timer is inserted into a list using a time relative to anything + * other than the current time. It will therefore be inserted into the + * correct list relative to the time this task thinks it is now. */ + if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) + { + /* The timer expired before it was added to the active timer + * list. Reload it now. */ + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + mtCOVERAGE_TEST_MARKER(); + } + + /* Call the timer callback. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } +/*-----------------------------------------------------------*/ + + static portTASK_FUNCTION( prvTimerTask, pvParameters ) + { + TickType_t xNextExpireTime; + BaseType_t xListWasEmpty; + + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 ) + { + extern void vApplicationDaemonTaskStartupHook( void ); + + /* Allow the application writer to execute some code in the context of + * this task at the point the task starts executing. This is useful if the + * application includes initialisation code that would benefit from + * executing after the scheduler has been started. */ + vApplicationDaemonTaskStartupHook(); + } + #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ + + for( ; ; ) + { + /* Query the timers list to see if it contains any timers, and if so, + * obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + + /* If a timer has expired, process it. Otherwise, block this task + * until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) + { + TickType_t xTimeNow; + BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + { + /* Obtain the time now to make an assessment as to whether the timer + * has expired or not. If obtaining the time causes the lists to switch + * then don't process this timer as any timers that remained in the list + * when the lists were switched will have been processed within the + * prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + if( xTimerListsWereSwitched == pdFALSE ) + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + { + ( void ) xTaskResumeAll(); + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + } + else + { + /* The tick count has not overflowed, and the next expire + * time has not been reached yet. This task should therefore + * block to wait for the next expire time or a command to be + * received - whichever comes first. The following line cannot + * be reached unless xNextExpireTime > xTimeNow, except in the + * case when the current timer list is empty. */ + if( xListWasEmpty != pdFALSE ) + { + /* The current timer list is empty - is the overflow list + * also empty? */ + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + } + + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + + if( xTaskResumeAll() == pdFALSE ) + { + /* Yield to wait for either a command to arrive, or the + * block time to expire. If a command arrived between the + * critical section being exited and this yield then the yield + * will not cause the task to block. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + ( void ) xTaskResumeAll(); + } + } + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) + { + TickType_t xNextExpireTime; + + /* Timers are listed in expiry time order, with the head of the list + * referencing the task that will expire first. Obtain the time at which + * the timer with the nearest expiry time will expire. If there are no + * active timers then just set the next expire time to 0. That will cause + * this task to unblock when the tick count overflows, at which point the + * timer lists will be switched and the next expiry time can be + * re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + + if( *pxListWasEmpty == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + } + + return xNextExpireTime; + } +/*-----------------------------------------------------------*/ + + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) + { + TickType_t xTimeNow; + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + + if( xTimeNow < xLastTime ) + { + prvSwitchTimerLists(); + *pxTimerListsWereSwitched = pdTRUE; + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + } + + xLastTime = xTimeNow; + + return xTimeNow; + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) + { + BaseType_t xProcessTimerNow = pdFALSE; + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + + if( xNextExpiryTime <= xTimeNow ) + { + /* Has the expiry time elapsed between the command to start/reset a + * timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + { + /* The time between a command being issued and the command being + * processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + { + /* If, since the command was issued, the tick count has overflowed + * but the expiry time has not, then the timer must have already passed + * its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + } + + return xProcessTimerNow; + } +/*-----------------------------------------------------------*/ + + static void prvProcessReceivedCommands( void ) + { + DaemonTaskMessage_t xMessage; + Timer_t * pxTimer; + BaseType_t xTimerListsWereSwitched, xResult; + TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + * commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + + /* The timer uses the xCallbackParameters member to request a + * callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + * function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + { + /* The messages uses the xTimerParameters member to work on a + * software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); + + /* In this case the xTimerListsWereSwitched parameter is not used, but + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + switch( xMessage.xMessageID ) + { + case tmrCOMMAND_START: + case tmrCOMMAND_START_FROM_ISR: + case tmrCOMMAND_RESET: + case tmrCOMMAND_RESET_FROM_ISR: + case tmrCOMMAND_START_DONT_TRACE: + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + { + /* The timer expired before it was added to the active + * timer list. Process it now. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + traceTIMER_EXPIRED( pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + break; + + case tmrCOMMAND_STOP: + case tmrCOMMAND_STOP_FROM_ISR: + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + break; + + case tmrCOMMAND_CHANGE_PERIOD: + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + + /* The new period does not really have a reference, and can + * be longer or shorter than the old one. The command time is + * therefore set to the current time, and as the period cannot + * be zero the next expiry time can only be in the future, + * meaning (unlike for the xTimerStart() case above) there is + * no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + break; + + case tmrCOMMAND_DELETE: + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + * just free up the memory if the memory was dynamically + * allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + { + vPortFree( pxTimer ); + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + } + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + { + /* If dynamic allocation is not enabled, the memory + * could not have been dynamically allocated. So there is + * no need to free the memory - just mark the timer as + * "not active". */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + + default: + /* Don't expect to get here. */ + break; + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSwitchTimerLists( void ) + { + TickType_t xNextExpireTime, xReloadTime; + List_t * pxTemp; + Timer_t * pxTimer; + BaseType_t xResult; + + /* The tick count has overflowed. The timer lists must be switched. + * If there are any timers still referenced from the current timer list + * then they must have expired and should be processed before the lists + * are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Remove the timer from the list. */ + pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + traceTIMER_EXPIRED( pxTimer ); + + /* Execute its callback, then send a command to restart the timer if + * it is an auto-reload timer. It cannot be restarted here as the lists + * have not yet been switched. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + /* Calculate the reload value, and if the reload value results in + * the timer going into the same timer list then it has already expired + * and the timer should be re-inserted into the current list so it is + * processed again within this loop. Otherwise a command should be sent + * to restart the timer to ensure it is only inserted into a list after + * the lists have been swapped. */ + xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); + + if( xReloadTime > xNextExpireTime ) + { + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + else + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxTemp = pxCurrentTimerList; + pxCurrentTimerList = pxOverflowTimerList; + pxOverflowTimerList = pxTemp; + } +/*-----------------------------------------------------------*/ + + static void prvCheckForValidListAndQueue( void ) + { + /* Check that the list from which active timers are referenced, and the + * queue used to communicate with the timer service, have been + * initialised. */ + taskENTER_CRITICAL(); + { + if( xTimerQueue == NULL ) + { + vListInitialise( &xActiveTimerList1 ); + vListInitialise( &xActiveTimerList2 ); + pxCurrentTimerList = &xActiveTimerList1; + pxOverflowTimerList = &xActiveTimerList2; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The timer queue is allocated statically in case + * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + } + #else + { + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configQUEUE_REGISTRY_SIZE */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + + /* Is the timer in the list of active timers? */ + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } /*lint !e818 Can't be pointer to const due to the typedef. */ +/*-----------------------------------------------------------*/ + + void * pvTimerGetTimerID( const TimerHandle_t xTimer ) + { + Timer_t * const pxTimer = xTimer; + void * pvReturn; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pvReturn = pxTimer->pvTimerID; + } + taskEXIT_CRITICAL(); + + return pvReturn; + } +/*-----------------------------------------------------------*/ + + void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) + { + Timer_t * const pxTimer = xTimer; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pxTimer->pvTimerID = pvNewID; + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + + tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* This function can only be called after a timer has been created or + * after the scheduler has been started because, until then, the timer + * queue does not exist. */ + configASSERT( xTimerQueue ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + + tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) + { + return ( ( Timer_t * ) xTimer )->uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) + { + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. If you want to include software timer + * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_TIMERS == 1 */ diff --git a/Libs/platform/common/inc/sl_assert.h b/Libs/platform/common/inc/sl_assert.h new file mode 100644 index 0000000..6747fc7 --- /dev/null +++ b/Libs/platform/common/inc/sl_assert.h @@ -0,0 +1,99 @@ +/***************************************************************************//** + * @file + * @brief API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_ASSERT_H +#define SL_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DOXY_DOC_ONLY) +/** Included for documentation purposes only. This define is not present by default. + * DEBUG_EFM should be defined from the compiler to enable the default internal + * assert handler. */ +#define DEBUG_EFM +#endif + +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) +/***************************************************************************//** + * @addtogroup assert ASSERT - Assert + * @brief Assert/error checking module + * @details + * By default, library assert usage is not included to reduce + * footprint and processing overhead. Further, assert usage is decoupled + * from ISO C assert handling (NDEBUG usage) to allow using ISO C + * assert without including assert statements. + * + * Below are available defines for controlling assert inclusion. The defines + * are typically for a project to be used by the preprocessor. + * + * @li If DEBUG_EFM is defined, the internal library assert handling will + * be used. This is implemented as a simple while(true) loop. DEBUG_EFM is not + * defined by default. + * + * @li If DEBUG_EFM_USER is defined, the user must provide custom + * implementation of the assertEFM() function. + * + * @li If both DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() + * statements are not operational. + * + * @note + * The internal assert is documented because DEBUG_EFM is defined in + * the doxygen configuration. + * @{ + ******************************************************************************/ +/* Due to footprint considerations, we only pass file name and line number, */ +/* not the assert expression (nor function name (C99)) */ +/***************************************************************************//** + * @brief + * Assert function for EFM. + * @param[in] file - path and file name of the assert. + * + * @param[in] line - line number, in the file. + ******************************************************************************/ +void assertEFM(const char *file, int line); +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) + +#else + +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((void)(expr)) + +#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ + +/** @} (end addtogroup assert) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_ASSERT_H */ diff --git a/Libs/platform/common/inc/sl_atomic.h b/Libs/platform/common/inc/sl_atomic.h new file mode 100644 index 0000000..d3a51ec --- /dev/null +++ b/Libs/platform/common/inc/sl_atomic.h @@ -0,0 +1,80 @@ +/******************************************************************************* + * @file + * @brief Implementation of atomic operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ATOMIC_H +#define SL_ATOMIC_H + +/******************************************************************************* + * @addtogroup atomic Atomic Operations + * @brief Atomic operations provide RAM store and read functionalities. + * @n @section atomic_usage Atomic Operations Usage + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Perform an atomic load. Use when a variable must be read from + * RAM. + * + * @param dest Variable where to copy the loaded value. + * + * @param source Variable from where to load the value. + * + * @note Does only support native types <= 32 bits. + * + * @note Load operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the load operation from 'source' is guaranteed to be + * performed atomically. If writing to 'dest' implies a store, + * the load and store operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_load(dest, source) ((dest) = (source)) + +/******************************************************************************* + * @brief Perform an atomic store. Use when a value must be stored in + * RAM. + * + * @param dest Variable where to store the value. + * + * @param source Variable that contains the value to store in 'dest'. + * + * @note Does only support native types <= 32 bits. + * + * @note Store operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the store operation to 'dest' is guaranteed to be + * performed atomically. If reading from 'source' implies a load, + * the store and load operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_store(dest, source) ((dest) = (source)) + +/** @} (end addtogroup atomic) */ + +#endif /* SL_ATOMIC_H */ diff --git a/Libs/platform/common/inc/sl_bit.h b/Libs/platform/common/inc/sl_bit.h new file mode 100644 index 0000000..ff15ae1 --- /dev/null +++ b/Libs/platform/common/inc/sl_bit.h @@ -0,0 +1,189 @@ +/***************************************************************************//** + * @file + * @brief Implementation of bit operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BIT_H +#define SL_BIT_H + +/***************************************************************************//** + * @addtogroup bit Bit Manipulation + * @brief Bitwise operations + * @{ + ******************************************************************************/ + +/****************************************************************************************************//** + * SL_DEF_BIT() + * + * @brief Create bit mask with single, specified bit set. + * + * @param bit Bit number of bit to set. + * + * @return Bit mask with single, specified bit set. + * + * @note (1) 'bit' SHOULD be a non-negative integer. + * + * @note (2) 'bit' values that overflow the target CPU &/or compiler environment (e.g. negative + * or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors. + *******************************************************************************************************/ + +#define SL_DEF_BIT(bit) (1u << (bit)) + +/****************************************************************************************************//** + * SL_SET_BIT() + * + * @brief Set specified bit(s) in a value. + * + * @param val Value to modify by setting specified bit(s). + * + * @param mask Mask of bits to set. + * + * @return Modified value with specified bit(s) set. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + *******************************************************************************************************/ + +#define SL_SET_BIT(val, mask) ((val) = ((val) | (mask))) + +/****************************************************************************************************//** + * SL_CLEAR_BIT() + * + * @brief Clear specified bit(s) in a value. + * + * @param val Value to modify by clearing specified bit(s). + * + * @param mask Mask of bits to clear. + * + * @return Modified value with specified bit(s) clear. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note 'mask' SHOULD be cast with the same data type than 'val'. + *******************************************************************************************************/ + +#define SL_CLEAR_BIT(val, mask) ((val) = ((val) & (~(mask)))) + +/****************************************************************************************************//** + * SL_IS_BIT_SET() + * + * @brief Determine whether the specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set. + * + * @return true, if ALL specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_BIT_SET(val, mask) (((((val) & (mask)) == (mask)) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_BIT_CLEAR() + * + * @brief Determine whether the specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear. + * + * @return true, if ALL specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ +#define SL_IS_BIT_CLEAR(val, mask) (((((val) & (mask)) == 0u) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_SET() + * + * @brief Determine whether any specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set (see Note #2). + * + * @return true, if ANY specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_SET(val, mask) ((((val) & (mask)) == 0u) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_CLEAR() + * + * @brief Determine whether any specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear (see Note #2). + * + * @return true, if ANY specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_CLEAR(val, mask) ((((val) & (mask)) == (mask)) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_MATH_IS_PWR2() + * + * @brief Determine if a value is a power of 2. + * + * @param val Value. + * + * @return true, 'val' is a power of 2. + * false, 'val' is not a power of 2. + *******************************************************************************************************/ + +#define SL_MATH_IS_PWR2(val) ((((val) != 0u) && (((val) & ((val) - 1u)) == 0u)) ? true : false) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @} (end addtogroup bit) */ + +#endif /* SL_BIT_H */ diff --git a/Libs/platform/common/inc/sl_cmsis_os2_common.h b/Libs/platform/common/inc/sl_cmsis_os2_common.h new file mode 100644 index 0000000..781c8af --- /dev/null +++ b/Libs/platform/common/inc/sl_cmsis_os2_common.h @@ -0,0 +1,200 @@ +/***************************************************************************//** + * @file sl_cmsis_os2_common.h + * @brief OS-agnostic header to provide CMSIS OS-Specific APIs like typedefs. + * @version x.y.z + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CMSIS_OS2_COMMON_H +#define SL_CMSIS_OS2_COMMON_H + +#include +#include "cmsis_os2.h" +#include "sl_status.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +// Validate the chosen RTOS +#if !defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && !defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) +#error "The extended CMSIS RTOS2 API currently only supports FreeRTOS or MicriumOS" +#endif + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) +#include "FreeRTOS.h" +#elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) +#include "os.h" +#endif + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + +#define osEventFlagsCbSize sizeof(StaticEventGroup_t) +#define osThreadCbSize sizeof(StaticTask_t) +#define osTimerCbSize sizeof(StaticTimer_t) +#define osMutexCbSize sizeof(StaticSemaphore_t) +#define osSemaphoreCbSize sizeof(StaticSemaphore_t) +#define osMessageQueueCbSize sizeof(StaticQueue_t) +#define osAlignment (portBYTE_ALIGNMENT) + +typedef StaticEventGroup_t osEventFlags_t; +typedef StaticTask_t osThread_t; +typedef StaticTimer_t osTimer_t; +typedef StaticSemaphore_t osMutex_t; +typedef StaticSemaphore_t osSemaphore_t; +typedef StaticQueue_t osMessageQueue_t; + +#elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) + +typedef struct { + OS_TCB tcb; // This must be the first element, used by OSTCBCurPtr +#if (OS_CFG_FLAG_EN == DEF_ENABLED) + OS_FLAG_GRP flag_grp; +#endif +#if (OS_CFG_MUTEX_EN == DEF_ENABLED) + OS_MUTEX join_mutex; +#endif + uint8_t obj_dyn_alloc; + uint8_t stack_dyn_alloc; + uint32_t attr_bits; +} osThread_t; + +#if (CMSIS_RTOS2_TIMER_TASK_EN == DEF_ENABLED) +typedef struct { + sl_sleeptimer_timer_handle_t handle; + osTimerFunc_t callback; + void *callback_data; + osTimerType_t type; + const char *name; + uint8_t dyn_alloc; +} osTimer_t; +#endif + +#if (OS_CFG_FLAG_EN == DEF_ENABLED) +typedef struct { + OS_FLAG_GRP flag_grp; + uint8_t dyn_alloc; + uint32_t flags; +} osEventFlags_t; +#endif + +#if (OS_CFG_MUTEX_EN == DEF_ENABLED) +typedef struct { + OS_MUTEX mutex; + uint8_t dyn_alloc; + uint8_t recursive; +} osMutex_t; +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +typedef struct { + OS_SEM sem; + uint8_t dyn_alloc; + uint32_t max_ctr; +} osSemaphore_t; +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +typedef struct { + OS_SEM sem_put; + OS_SEM sem_get; + uint8_t *buf; + uint8_t obj_dyn_alloc; + uint8_t buf_dyn_alloc; + uint32_t msg_count; + uint32_t msg_size; + uint32_t msg_queued; + uint32_t msg_head; + uint32_t msg_tail; +} osMessageQueue_t; +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +typedef struct { + OS_SEM sem; + uint8_t *buf; + uint8_t obj_dyn_alloc; + uint8_t buf_dyn_alloc; + uint32_t block_count; + uint32_t block_size; + uint32_t free_count; + uint32_t free_head; +} osMemoryPool_t; +#endif + +#if (OS_CFG_FLAG_EN == DEF_ENABLED) +#define osEventFlagsCbSize sizeof(osEventFlags_t) +#endif + +#define osThreadCbSize sizeof(osThread_t) + +#if (OS_CFG_TMR_EN == DEF_ENABLED) +#define osTimerCbSize sizeof(osTimer_t) +#endif + +#if (OS_CFG_MUTEX_EN == DEF_ENABLED) +#define osMutexCbSize sizeof(osMutex_t) +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +#define osSemaphoreCbSize sizeof(osSemaphore_t) +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +#define osMessageQueueCbSize sizeof(osMessageQueue_t) +#endif + +#if (OS_CFG_SEM_EN == DEF_ENABLED) +#define osMemoryPoolCbSize sizeof(osMemoryPool_t) +#endif + +#define osAlignment sizeof(CPU_ALIGN) +#endif // SL_CATALOG_MICRIUMOS_KERNEL_PRESENT + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * sl_cmsis_os_convert_status() + * + * @brief Convert OsStatus from CMSIS-RTOS2 to sl_status type. + * + * @param os_status The OS status code returned by CMSIS-RTOS2 API. + * + * @return Status code converted to sl_status. + *******************************************************************************************************/ +sl_status_t sl_cmsis_os_convert_status(osStatus_t os_status); + +#ifdef __cplusplus +} +#endif + +#endif // SL_CMSIS_OS2_COMMON_H diff --git a/Libs/platform/common/inc/sl_code_classification.h b/Libs/platform/common/inc/sl_code_classification.h new file mode 100644 index 0000000..04e9d21 --- /dev/null +++ b/Libs/platform/common/inc/sl_code_classification.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief Code Classification API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_CODE_CLASSIFICATION_H_ +#define _SL_CODE_CLASSIFICATION_H_ + +#include "sli_code_classification.h" + +// NOTE: This API is for use by applications only. + +/**************************************************************************//** + * @addtogroup code_placement + * @brief Code Classification API + * @{ + *****************************************************************************/ + +/******************************************************************************/ +/* Macro API */ +/******************************************************************************/ +#if defined(__GNUC__) && !defined(__llvm__) + +// With GCC, __attribute__ can be used to specify the input section of +// functions. + +/// Prepend a function definition with this macro to place it in RAM. +#define SL_CODE_RAM \ + __attribute__((section("text_application_ram"))) + +#elif defined(__ICCARM__) + +// With IAR, _Pragma can be used to specify the input section of +// functions. + +/// Prepend a function definition with this macro to place it in RAM. +#define SL_CODE_RAM \ + _Pragma("location =\"text_application_ram\"") + +#elif defined(__llvm__) + +#define SL_CODE_RAM + +#else + #error "(sl_code_classification.h): Code classification does not support \ + the chosen compiler." +#endif // __GNUC__ + +/** @} (end addtogroup code_placement) */ +#endif // _SL_CODE_CLASSIFICATION_H_ diff --git a/Libs/platform/common/inc/sl_common.h b/Libs/platform/common/inc/sl_common.h new file mode 100644 index 0000000..ff3a624 --- /dev/null +++ b/Libs/platform/common/inc/sl_common.h @@ -0,0 +1,420 @@ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COMMON_H +#define SL_COMMON_H + +#include +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__STATIC_INLINE) +#if !defined(__unix__) && defined(__arm__) +/* Compiler agnostic definitions */ +#include "cmsis_compiler.h" +#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#define __STATIC_INLINE static inline +#else +#warning Please provide a macro for your compiler and architecture +#define __STATIC_INLINE static +#endif +#endif + +/***************************************************************************//** + * @addtogroup common COMMON - Common Utilities + * @brief General purpose utilities and cross-compiler support + * @details + * This SDK supports the following compilers/IDEs: + * @li Simplicity Studio + * @li IAR Embedded Workbench + * @li Keil uVision IDE + * @li Plain armgcc + * + * Certain compiler features such as alignment is implemented differently in the tools. + * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent + * code. + * + * @note RAM code macros are implemented in [RAMFUNC](/gecko-platform//emlib-efm32g/). + * Cross-compiler RAM code support needs extended documentation and it is therefore + * implemented as a separate module. + * + * @{ + ******************************************************************************/ + +/** @brief Macros to concatenate. */ +#define _CONCAT_2(first, second) first ## second +#define SL_CONCAT_PASTER_2(first, second) _CONCAT_2(first, second) ///< sl concat paster 2. +#define _CONCAT_3(first, second, third) first ## second ## third +#define SL_CONCAT_PASTER_3(first, second, third) _CONCAT_3(first, second, third) ///< sl concat paster 3. +#define _CONCAT_4(first, second, third, fourth) first ## second ## third ## fourth +#define SL_CONCAT_PASTER_4(first, second, third, fourth) _CONCAT_4(first, second, third, fourth) ///< sl concat paster 4. + +/** @brief Round n up to closest interval of i. */ +#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) + +/** @brief Round n down to closest interval of i. */ +#define SL_FLOOR(n, i) ((n / i) * i) + +/** @brief Stringify X */ +#define STRINGIZE(X) #X + +#if !defined(__GNUC__) +/* Not GCC compilers */ + +/** @brief Macros for giving the compiler hints about the likelihood of a branch. */ +#define SL_BRANCH_LIKELY(x) (x) +#define SL_BRANCH_UNLIKELY(x) (x) + +/** @brief Macro for getting minimum value. */ +#define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) + +/** @brief Macro for getting maximum value. */ +#define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) + +/** @brief Macros for handling packed structures. */ +#define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) +#define SL_PACK_END() _Pragma("pack()") +#define SL_ATTRIBUTE_PACKED + +#if defined(__CC_ARM) +/** @brief MDK-ARM compiler: Macros for handling aligned structures. */ +#define SL_ALIGN(X) __align(X) + +/** MDK-ARM compiler: Macro for handling weak symbols. */ +#define SL_WEAK __attribute__ ((weak)) + +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** MDK-ARM compiler: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) +#endif + +#if defined(__ICCARM__) + +#if (__VER__ >= 8000000) +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_BEGIN +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_END +#endif + +/** @brief IAR Embedded Workbench: Macros for handling aligned structures. */ +#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) + +/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ +#define SL_WEAK __weak + +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + +/* *INDENT-OFF* */ +/** IAR Embedded Workbench: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) @ X +#endif +/* *INDENT-ON* */ + +#define SL_ATTRIBUTE_ALIGN(X) + +/** @brief Macro for notifying the compiler of an intended + * switch case fallthrough. */ +#define SL_FALLTHROUGH + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#define SL_IGNORE_TYPE_LIMIT_BEGIN +#define SL_IGNORE_TYPE_LIMIT_END + +#else // !defined(__GNUC__) +/* GCC compilers */ + +/** @brief Macros for giving the compiler hints about the likelihood of a branch. */ +#define SL_BRANCH_LIKELY(x) __builtin_expect(!!(x), 1) +#define SL_BRANCH_UNLIKELY(x) __builtin_expect(!!(x), 0) + +/** @brief A macro for getting the minimum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) + +/** @brief A macro for getting the maximum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) + +/** @brief A GCC style macro for handling packed structures. */ +#define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) + +/** @brief A macro for handling packed structures. + * @n Use this macro before the structure definition. + * @n X denotes the maximum alignment of structure members. X is not supported with + * GCC. GCC always uses 1 byte maximum alignment. + */ +#define SL_PACK_START(x) + +/** @brief A macro for handling packed structures. + * @n Use this macro after the structure definition. + * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure + * definition. + */ +#define SL_PACK_END() + +/** @brief GCC style macro for aligning a variable. */ +#define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) + +/** @brief A macro for aligning a variable. + * @n Use this macro before the variable definition. + * @n X denotes the storage alignment value in bytes. + * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal + * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. + */ +#define SL_ALIGN(X) + +/** @brief A macro for defining a weak symbol. */ +#define SL_WEAK __attribute__ ((weak)) + +/** @brief A macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** A macro for placing a variable in a section. + * @n Use this macro after the variable definition, before the equal sign or a semicolon. + * @n X denotes the section to place the variable in. + */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) + +/** @brief A macro for notifying the compiler of an intended + * switch case fallthrough. */ +#if __GNUC__ >= 7 + #define SL_FALLTHROUGH __attribute__ ((fallthrough)); +#else + #define SL_FALLTHROUGH +#endif + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) + #define SL_IGNORE_TYPE_LIMIT_BEGIN \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wtype-limits\"") + #define SL_IGNORE_TYPE_LIMIT_END \ + _Pragma("GCC diagnostic pop") +#else + #define SL_IGNORE_TYPE_LIMIT_BEGIN + #define SL_IGNORE_TYPE_LIMIT_END ///< A MACRO to notify the compiler, limit END. +#endif + +#endif // !defined(__GNUC__) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** @brief + * Macro for marking deprecated functions + * + * @details + * SL_DEPRECATED_API_SDK_ is used to mark functions that are + * deprecated and should not be used from a given version of the SDK. + * The accompanying SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_ + * define can be set to suppress warnings generated when using + * deprecated APIs. + */ +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_0 +#define SL_DEPRECATED_API_SDK_3_0 +#else +#define SL_DEPRECATED_API_SDK_3_0 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_2 +#define SL_DEPRECATED_API_SDK_3_2 +#else +#define SL_DEPRECATED_API_SDK_3_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_3 +#define SL_DEPRECATED_API_SDK_3_3 +#else +#define SL_DEPRECATED_API_SDK_3_3 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_1 +#define SL_DEPRECATED_API_SDK_4_1 +#else +#define SL_DEPRECATED_API_SDK_4_1 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_2 +#define SL_DEPRECATED_API_SDK_4_2 +#else +#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4 +#define SL_DEPRECATED_API_SDK_4_4 +#else +#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2024_6 +#define SL_DEPRECATED_API_SDK_2024_6 +#else +#define SL_DEPRECATED_API_SDK_2024_6 __attribute__ ((deprecated)) +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Count trailing number of zeros. Use CLZ instruction if available. + * + * @param[in] value + * Data value to check for number of trailing zero bits. + * + * @return + * A number of trailing zeros in value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_CTZ(uint32_t value) +{ +#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) + return __CLZ(__RBIT(value)); + +#else + uint32_t zeros; + for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { + ; + } + return zeros; +#endif +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated function. New code should use @ref SL_CTZ. */ +__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) +{ + return SL_CTZ(value); +} +/** @endcond */ + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * Data value to reverse. + * + * @return + * A reversed value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_RBIT(uint32_t value) +{ + uint32_t result; + +#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) + result = __RBIT(value); +#else + int32_t s = 4 * 8 - 1; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; +#endif + return result; +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 16-bit data value to reverse. + * + * @return + * A 16-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) +{ + return (uint16_t)(SL_RBIT(value) >> 16); +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 8-bit data value to reverse. + * + * @return + * A 8-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint8_t SL_RBIT8(uint8_t value) +{ + return (uint8_t)(SL_RBIT(value) >> 24); +} + +/***************************************************************************//** + * @brief + * Convert logarithm of 2 to division factor. + * + * @param[in] log2 + * Logarithm of 2. + * + * @return + * Dividend. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) +{ + EFM_ASSERT(log2 < 32U); + return 1UL << log2; +} + +/***************************************************************************//** + * @brief + * Count the number of bits that are set to 1 in a 32-bit bitfield. + * + * @param[in] bitfield + * 32-bit bitfield. + * + * @return + * The number of bits that are set to 1 in the bitfield. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_POPCOUNT32(uint32_t bitfield) +{ + bitfield = bitfield - ((bitfield >> 1) & 0x55555555); + bitfield = (bitfield & 0x33333333) + ((bitfield >> 2) & 0x33333333); + bitfield = (bitfield + (bitfield >> 4)) & 0x0F0F0F0F; + return (bitfield * 0x01010101) >> 24; +} + +/** @} (end addtogroup common) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_COMMON_H */ diff --git a/Libs/platform/common/inc/sl_compiler.h b/Libs/platform/common/inc/sl_compiler.h new file mode 100644 index 0000000..74f2e87 --- /dev/null +++ b/Libs/platform/common/inc/sl_compiler.h @@ -0,0 +1,210 @@ +/***************************************************************************//** + * @file + * @brief Silabs Compiler definitions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COMPILER_H +#define SL_COMPILER_H + +/***************************************************************************//** + * @addtogroup compiler Compiler definitions + * @brief Compiler definitions + * @{ + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__GNUC__) + +// Fallback for __has_builtin. + #ifndef __has_builtin + #define __has_builtin(x) (0) + #endif + +// Compiler specific defines. + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + +#elif defined(__IAR_SYSTEMS_ICC__) + + #pragma system_include + + #if (__VER__ >= 8000000) + #define __ICCARM_V8 1 + #else + #define __ICCARM_V8 0 + #endif + + #ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #endif + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif + #endif + + #ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED __packed + #endif + #endif + + #ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif + #endif + + #ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif + #endif + + #ifndef __RESTRICT + #define __RESTRICT restrict + #endif + + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") + #endif + + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE + #endif + + #ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif + #endif + + #ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif + #endif + +#else + #error "Unknown compiler." +#endif + +// IO definitions (access restrictions to peripheral registers). +#ifdef __cplusplus + #define __I volatile ///< Defines 'read only' permissions +#else + #define __I volatile const ///< Defines 'read only' permissions +#endif +#define __O volatile ///< Defines 'write only' permissions +#define __IO volatile ///< Defines 'read / write' permissions + +// The following defines should be used for structure members. +#define __IM volatile const ///< Defines 'read only' structure member permissions +#define __OM volatile ///< Defines 'write only' structure member permissions +#define __IOM volatile ///< Defines 'read / write' structure member permissions + +#ifdef __cplusplus +} +#endif + +/** @} (end group compiler) */ + +#endif // SL_COMPILER_H diff --git a/Libs/platform/common/inc/sl_core.h b/Libs/platform/common/inc/sl_core.h new file mode 100644 index 0000000..a52562e --- /dev/null +++ b/Libs/platform/common/inc/sl_core.h @@ -0,0 +1,499 @@ +/***************************************************************************//** + * @file + * @brief Core API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CORE_H +#define SL_CORE_H + +#include +#include +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup sl_core Core + * + * @section sl_core_intro Introduction + * + * The core abstraction API provides high-level, device agnostic, control of + * core peripherals, most notably the ability to execute code in sections with + * varying levels of interrupt masking. + * + * This module provides support for two types of critical sections, each + * with different interrupt masking capabilities. + * + * @li CRITICAL section: Inside a critical section, all interrupts are + * masked (except for core exception handlers). + * @li ATOMIC section: Inside an atomic section, interrupts with a + * priority less than the configurable @ref SL_CORE_BASE_PRIORITY_LEVEL + * value will be masked. + * + * @section sl_core_conf Compile-time Configuration + * + * The following #define is used to configure sl_core: + * @code{.c} + * // Enables debug methods to measure the time spent in critical sections. + * #define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0 + * @endcode + * + * @section sl_core_macro_api Macro API + * + * The core abstraction API has macros to facilitate executing code in + * ATOMIC and CRITICAL sections. + * + * @ref CORE_DECLARE_IRQ_STATE, @ref CORE_ENTER_ATOMIC() and + * @ref CORE_EXIT_ATOMIC() can be used together to implement an ATOMIC section. + * @code{.c} + * { + * CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to + * // atomic section entry. + * + * CORE_ENTER_ATOMIC(); // Enter atomic section. + * + * ... + * ... your code goes here ... + * ... + * + * CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. + * } + * @endcode + * + * @ref CORE_ATOMIC_SECTION(yourcode) is aconcatenation of all three of the + * macros above. + * @code{.c} + * { + * CORE_ATOMIC_SECTION( + * ... + * ... your code goes here ... + * ... + * ) + * } + * @endcode + * + * The following macros implement CRITICAL sections in a similar fashion as + * described above for ATOMIC sections: + *
  • @ref CORE_DECLARE_IRQ_STATE
    • + *
  • @ref CORE_ENTER_CRITICAL()
    • + *
  • @ref CORE_EXIT_CRITICAL()
    • + *
  • @ref CORE_CRITICAL_SECTION(yourcode)
    • + * + * @section sl_core_reimplementation API Reimplementation + * + * Most of the functions in the API are implemented as weak functions. This means + * that it is easy to reimplement when special needs arise. Shown below is a + * reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: + * @code{.c} + * CORE_irqState_t CORE_EnterCritical(void) + * { + * vPortEnterCritical(); + * return 0; + * } + * + * void CORE_ExitCritical(CORE_irqState_t irqState) + * { + * (void)irqState; + * vPortExitCritical(); + * } + * @endcode + * Also note that CORE_Enter/ExitCritical() are not implemented as inline + * functions. As a result, reimplementations will be possible even when original + * implementations are inside a linked library. + * + * Some RTOSes must be notified on interrupt handler entry and exit. Macros + * @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable + * placeholders for inserting such code. Insert these macros in all your + * interrupt handlers and then override the default macro implementations. + * This is an example if uC/OS is used: + * @code{.c} + * // In emlib_config.h: + * + * #define CORE_INTERRUPT_ENTRY() OSIntEnter() + * #define CORE_INTERRUPT_EXIT() OSIntExit() + * @endcode + * + * @section sl_core_max_timing Maximum Interrupt Disabled Time + * + * The maximum time spent (in cycles) in critical and atomic sections can be + * measured for performance and interrupt latency analysis. + * To enable the timings, use the SL_CORE_ENABLE_INTERRUPT_DISABLED_TIMING + * configuration option. When enabled, the functions + * @ref CORE_get_max_time_critical_section() and + * @ref CORE_get_max_time_atomic_section() + * can be used to get the max timings since startup. + * + * @section sl_core_porting Porting from em_int + * + * Existing code using INT_Enable() and INT_Disable() must be ported to the + * sl_core API. While em_int used, a global counter to store the interrupt state, + * sl_core uses a local variable. Any usage of INT_Disable(), therefore, needs to + * be replaced with a declaration of the interrupt state variable before entering + * the critical section. + * + * Since the state variable is in local scope, the critical section exit + * needs to occur within the scope of the variable. If multiple nested critical + * sections are used, each needs to have its own state variable in its own scope. + * + * In many cases, completely disabling all interrupts using CRITICAL sections + * might be more heavy-handed than needed. When porting, consider whether + * an ATOMIC section can be used to only disable a subset of the interrupts. + * + * Replacing em_int calls with sl_core function calls: + * @code{.c} + * void func(void) + * { + * // INT_Disable(); + * CORE_DECLARE_IRQ_STATE; + * CORE_ENTER_ATOMIC(); + * . + * . + * . + * // INT_Enable(); + * CORE_EXIT_ATOMIC(); + * } + * @endcode + * @{ + ******************************************************************************/ + +/******************************************************************************* + ***************************** DEFINES ************************************* + ******************************************************************************/ + +#if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) +/** The interrupt priority level disabled within ATOMIC regions. Interrupts + * with priority level equal to or lower than this definition will be disabled + * within ATOMIC regions. */ +#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 +#else +#ifndef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2024_6 +#warning "The CORE_ATOMIC_BASE_PRIORITY_LEVEL configuration is DEPRECATED. In \ + later releases, the base priority of atomic sections will be hardcoded to 3 \ + and will no longer be configurable. Please consider updating the priorities \ + of interrupts in your application to account for this new hardcoded value." +#endif +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +/// Allocate storage for PRIMASK or BASEPRI value for use by +/// CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. +#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState + +/// CRITICAL style interrupt disable. +#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() + +/// CRITICAL style interrupt enable. +#define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() + +/// Convenience macro for implementing a CRITICAL section. +#define CORE_CRITICAL_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_CRITICAL(); \ + { \ + yourcode \ + } \ + CORE_EXIT_CRITICAL(); \ + } + +/// Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in +/// scope. +#define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() + +/// Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in +/// scope. +#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) + +/// CRITICAL style yield. +#define CORE_YIELD_CRITICAL() CORE_YieldCritical() + +/// ATOMIC style interrupt disable. +#define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() + +/// ATOMIC style interrupt enable. +#define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() + +/// Convenience macro for implementing an ATOMIC section. +#define CORE_ATOMIC_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_ATOMIC(); \ + { \ + yourcode \ + } \ + CORE_EXIT_ATOMIC(); \ + } + +/// Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in +/// scope. +#define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() + +/// Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in +/// scope. +#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) + +/// ATOMIC style yield. +#define CORE_YIELD_ATOMIC() CORE_YieldAtomic() + +/// Check if IRQ is disabled. +#define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() + +/// Check if inside an IRQ handler. +#define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() + +// Reset System. +#define CORE_RESET_SYSTEM() CORE_ResetSystem() + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/// Storage for PRIMASK or BASEPRI value. +typedef uint32_t CORE_irqState_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable all interrupts by setting PRIMASK. + * (Fault exception handlers will still be enabled). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_CriticalDisableIrq(void); + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by clearing PRIMASK. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_CriticalEnableIrq(void); + +/***************************************************************************//** + * @brief + * Exit a CRITICAL section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to PRIMASK when exiting + * the CRITICAL section. This value is usually the one returned by a prior + * call to @ref CORE_EnterCritical(). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_ExitCritical(CORE_irqState_t irqState); + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usually used within a CRITICAL section. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_YieldCritical(void); + +/***************************************************************************//** + * @brief + * Enter a CRITICAL section. + * + * When a CRITICAL section is entered, all interrupts (except fault handlers) + * are disabled. + * + * @return + * The value of PRIMASK register prior to the CRITICAL section entry. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +CORE_irqState_t CORE_EnterCritical(void); + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable interrupts with a priority lower or equal to + * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register + * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalDisableIrq(). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_AtomicDisableIrq(void); + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by setting core BASEPRI register to 0. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK + * is set (CPU is inside a CRITICAL section), interrupts will still be + * disabled after calling this function. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalEnableIrq(). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_AtomicEnableIrq(void); + +/***************************************************************************//** + * @brief + * Exit an ATOMIC section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to BASEPRI when exiting + * the ATOMIC section. This value is usually the one returned by a prior + * call to @ref CORE_EnterAtomic(). + * + * @note + * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_ExitCritical(). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_ExitAtomic(CORE_irqState_t irqState); + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usually used within an ATOMIC section. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_YieldCritical(). + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_YieldAtomic(void); + +/***************************************************************************//** + * @brief + * Enter an ATOMIC section. + * + * When an ATOMIC section is entered, interrupts with priority lower or equal + * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_EnterCritical(). + * + * @return + * The value of BASEPRI register prior to ATOMIC section entry. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +CORE_irqState_t CORE_EnterAtomic(void); + +/***************************************************************************//** + * @brief + * Check whether the current CPU operation mode is handler mode. + * + * @return + * True if the CPU is in handler mode (currently executing an interrupt handler). + * @n False if the CPU is in thread mode. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +bool CORE_InIrqContext(void); + +/***************************************************************************//** + * @brief + * Check if interrupts are disabled. + * + * @return + * True if interrupts are disabled. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +bool CORE_IrqIsDisabled(void); + +/***************************************************************************//** + * @brief + * Returns the max time spent in critical section. + * + * @return + * The max time spent in critical section. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t CORE_get_max_time_critical_section(void); + +/***************************************************************************//** + * @brief + * Returns the max time spent in atomic section. + * + * @return + * The max time spent in atomic section. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t CORE_get_max_time_atomic_section(void); + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_clear_max_time_critical_section(void); + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) +void CORE_clear_max_time_atomic_section(void); + +/***************************************************************************//** + * @brief + * Reset chip routine. + ******************************************************************************/ +void CORE_ResetSystem(void); + +/** @} (end addtogroup sl_core) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_CORE_H */ diff --git a/Libs/platform/common/inc/sl_enum.h b/Libs/platform/common/inc/sl_enum.h new file mode 100644 index 0000000..e7e33bb --- /dev/null +++ b/Libs/platform/common/inc/sl_enum.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * @file + * @brief SL_ENUM Implementation + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ENUM_H +#define SL_ENUM_H + +/******************************************************************************* + * @addtogroup enum Enumerations + * @brief Enumerations with stable binary representation + * @details + * Silicon Labs libraries do not use enumerations because the ARM EABI leaves + * their size ambiguous, which causes problems if the application is built + * with different flags than the library. Instead, uint8_t typedefs + * are used in compiled code for all enumerations. For documentation purposes, + * this is converted to an actual enumeration in documentation. + * @{ + ******************************************************************************/ + +#ifdef DOXYGEN +/// Enumeration mapped to uint8_t +#define SL_ENUM(name) enum name +/// Enumeration mapped to arbitrary type +#define SL_ENUM_GENERIC(name, type) enum name +#else +// NOTE: The following macros might cause MISRA warnings because +// Macro parameters need to be enclosed in parentheses. +// However, it is not possible in C to enclose declaration +// identifiers in parentheses. For example: +// typedef uint8_t (some_identifier); +// is not syntactically correct in the C language (C99). +#define SL_ENUM(name) typedef uint8_t name; enum name##_enum +#define SL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum + +// For debugging, use the following define to turn this back into a proper enumeration +// #define SL_ENUM(name) typedef enum name##_enum name; enum name##_enum +#endif + +/** @} end enum */ + +#endif // SL_ENUM_H diff --git a/Libs/platform/common/inc/sl_slist.h b/Libs/platform/common/inc/sl_slist.h new file mode 100644 index 0000000..bcbd301 --- /dev/null +++ b/Libs/platform/common/inc/sl_slist.h @@ -0,0 +1,173 @@ +/******************************************************************************* + * @file + * @brief Single Link List. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SLIST_H +#define SL_SLIST_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * @addtogroup slist Singly-Linked List + * @brief Singly-linked List module provides APIs to handle singly-linked list + * operations such as insert, push, pop, push back, sort and remove. + * + * @note The pop operation follows FIFO method. + * @n @section slist_usage Singly-Linked List module Usage + * @{ + ******************************************************************************/ + +/// List node type +typedef struct sl_slist_node sl_slist_node_t; + +/// List node +struct sl_slist_node { + sl_slist_node_t *node; ///< List node +}; + +#ifndef DOXYGEN +#define container_of(ptr, type, member) (type *)((uintptr_t)(ptr) - ((uintptr_t)(&((type *)0)->member))) + +#define SL_SLIST_ENTRY container_of + +#define SL_SLIST_FOR_EACH(list_head, iterator) for ((iterator) = (list_head); (iterator) != NULL; (iterator) = (iterator)->node) + +#define SL_SLIST_FOR_EACH_ENTRY(list_head, entry, type, member) for ( (entry) = SL_SLIST_ENTRY(list_head, type, member); \ + (type *)(entry) != SL_SLIST_ENTRY(NULL, type, member); \ + (entry) = SL_SLIST_ENTRY((entry)->member.node, type, member)) +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/******************************************************************************* + * Initialize a singly-linked list. + * + * @param head Pointer to pointer of head element of list. + ******************************************************************************/ +void sl_slist_init(sl_slist_node_t **head); + +/******************************************************************************* + * Add given item at beginning of the list. + * + * @param head Pointer to pointer of head element of the list. + * + * @param item Pointer to an item to add. + ******************************************************************************/ +void sl_slist_push(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Add item at the end of the list. + * + * @param head Pointer to the pointer of a head element of the list. + * + * @param item Pointer to the item to add. + ******************************************************************************/ +void sl_slist_push_back(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Remove and return the first element of the list. + * + * @param head Pointer to he pointer of the head element of the list. + * + * @return Pointer to item that was at top of the list. + ******************************************************************************/ +sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head); + +/******************************************************************************* + * Insert an item after the given item. + * + * @param item Pointer to an item to add. + * + * @param pos Pointer to an item after which the item to add will be inserted. + ******************************************************************************/ +void sl_slist_insert(sl_slist_node_t *item, + sl_slist_node_t *pos); + +/******************************************************************************* + * Join two lists together. + * + * @param head_list_1 Pointer to the pointer of a head element of the list. + * + * @param head_list_2 Pointer to the pointer of a head element of the list + * to be appended. After the call, this pointer will be + * invalidated (set to NULL). + ******************************************************************************/ +void sl_slist_join(sl_slist_node_t **head_list_1, + sl_slist_node_t **head_list_2); + +/******************************************************************************* + * Remove an item from the list. + * + * @param head Pointer to pointer of the head element of list. + * + * @param item Pointer to the item to remove. + ******************************************************************************/ +void sl_slist_remove(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Sort list items. + * + * @param head Pointer to the pointer of the head element of the list. + * + * @param cmp_fnct Pointer to function to use for sorting the list. + * item_l Pointer to left item. + * item_r Pointer to right item. + * Returns whether the two items are ordered (true) or not (false). + ******************************************************************************/ +void sl_slist_sort(sl_slist_node_t **head, + bool (*cmp_fnct)(sl_slist_node_t *item_l, + sl_slist_node_t *item_r)); + +/******************************************************************************* + * Checks if the list is empty. + * + * @param head Pointer to the head element of the list. + ******************************************************************************/ +static inline bool sl_slist_is_empty(sl_slist_node_t *head) +{ + return head == NULL; +} + +/** @} (end addtogroup slist) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SLIST_H */ diff --git a/Libs/platform/common/inc/sl_status.h b/Libs/platform/common/inc/sl_status.h new file mode 100644 index 0000000..f89704d --- /dev/null +++ b/Libs/platform/common/inc/sl_status.h @@ -0,0 +1,526 @@ +/******************************************************************************* + * @file + * @brief SL Status Codes. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_STATUS_H +#define SL_STATUS_H + +#include + +/******************************************************************************* + * @addtogroup status Status Codes + * @details Status Codes contains error and status code definitions used by + * Simplicity SDK software components and stacks. This module also + * provides routines to read the string linked with the error and + * status codes. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Space Defines + +#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask. + +#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space. + +#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space. +#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space. +#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space. + +#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space. +#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space. +#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space. +#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space. +#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space. +#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space. +#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space. +#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space. +#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space. +#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space. + +#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space. +#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space. + +#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space. +#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space. +#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space. +#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space. + +#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space. + +#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space. + +// ----------------------------------------------------------------------------- +// Status Defines + +// ----------------------------------------------------------------------------- +// Generic Errors + +#define SL_STATUS_OK ((sl_status_t)0x0000) ///< No error. +#define SL_STATUS_FAIL ((sl_status_t)0x0001) ///< Generic error. + +// State Errors +#define SL_STATUS_INVALID_STATE ((sl_status_t)0x0002) ///< Generic invalid state error. +#define SL_STATUS_NOT_READY ((sl_status_t)0x0003) ///< Module is not ready for requested operation. +#define SL_STATUS_BUSY ((sl_status_t)0x0004) ///< Module is busy and cannot carry out requested operation. +#define SL_STATUS_IN_PROGRESS ((sl_status_t)0x0005) ///< Operation is in progress and not yet complete (pass or fail). +#define SL_STATUS_ABORT ((sl_status_t)0x0006) ///< Operation aborted. +#define SL_STATUS_TIMEOUT ((sl_status_t)0x0007) ///< Operation timed out. +#define SL_STATUS_PERMISSION ((sl_status_t)0x0008) ///< Operation not allowed per permissions. +#define SL_STATUS_WOULD_BLOCK ((sl_status_t)0x0009) ///< Non-blocking operation would block. +#define SL_STATUS_IDLE ((sl_status_t)0x000A) ///< Operation/module is Idle, cannot carry requested operation. +#define SL_STATUS_IS_WAITING ((sl_status_t)0x000B) ///< Operation cannot be done while construct is waiting. +#define SL_STATUS_NONE_WAITING ((sl_status_t)0x000C) ///< No task/construct waiting/pending for that action/event. +#define SL_STATUS_SUSPENDED ((sl_status_t)0x000D) ///< Operation cannot be done while construct is suspended. +#define SL_STATUS_NOT_AVAILABLE ((sl_status_t)0x000E) ///< Feature not available due to software configuration. +#define SL_STATUS_NOT_SUPPORTED ((sl_status_t)0x000F) ///< Feature not supported. +#define SL_STATUS_INITIALIZATION ((sl_status_t)0x0010) ///< Initialization failed. +#define SL_STATUS_NOT_INITIALIZED ((sl_status_t)0x0011) ///< Module has not been initialized. +#define SL_STATUS_ALREADY_INITIALIZED ((sl_status_t)0x0012) ///< Module has already been initialized. +#define SL_STATUS_DELETED ((sl_status_t)0x0013) ///< Object/construct has been deleted. +#define SL_STATUS_ISR ((sl_status_t)0x0014) ///< Illegal call from ISR. +#define SL_STATUS_NETWORK_UP ((sl_status_t)0x0015) ///< Illegal call because network is up. +#define SL_STATUS_NETWORK_DOWN ((sl_status_t)0x0016) ///< Illegal call because network is down. +#define SL_STATUS_NOT_JOINED ((sl_status_t)0x0017) ///< Failure due to not being joined in a network. +#define SL_STATUS_NO_BEACONS ((sl_status_t)0x0018) ///< Invalid operation as there are no beacons. + +// Allocation/ownership Errors +#define SL_STATUS_ALLOCATION_FAILED ((sl_status_t)0x0019) ///< Generic allocation error. +#define SL_STATUS_NO_MORE_RESOURCE ((sl_status_t)0x001A) ///< No more resource available to perform the operation. +#define SL_STATUS_EMPTY ((sl_status_t)0x001B) ///< Item/list/queue is empty. +#define SL_STATUS_FULL ((sl_status_t)0x001C) ///< Item/list/queue is full. +#define SL_STATUS_WOULD_OVERFLOW ((sl_status_t)0x001D) ///< Item would overflow. +#define SL_STATUS_HAS_OVERFLOWED ((sl_status_t)0x001E) ///< Item/list/queue has been overflowed. +#define SL_STATUS_OWNERSHIP ((sl_status_t)0x001F) ///< Generic ownership error. +#define SL_STATUS_IS_OWNER ((sl_status_t)0x0020) ///< Already/still owning resource. + +// Invalid Parameters Errors +#define SL_STATUS_INVALID_PARAMETER ((sl_status_t)0x0021) ///< Generic invalid argument or consequence of invalid argument. +#define SL_STATUS_NULL_POINTER ((sl_status_t)0x0022) ///< Invalid null pointer received as argument. +#define SL_STATUS_INVALID_CONFIGURATION ((sl_status_t)0x0023) ///< Invalid configuration provided. +#define SL_STATUS_INVALID_MODE ((sl_status_t)0x0024) ///< Invalid mode. +#define SL_STATUS_INVALID_HANDLE ((sl_status_t)0x0025) ///< Invalid handle. +#define SL_STATUS_INVALID_TYPE ((sl_status_t)0x0026) ///< Invalid type for operation. +#define SL_STATUS_INVALID_INDEX ((sl_status_t)0x0027) ///< Invalid index. +#define SL_STATUS_INVALID_RANGE ((sl_status_t)0x0028) ///< Invalid range. +#define SL_STATUS_INVALID_KEY ((sl_status_t)0x0029) ///< Invalid key. +#define SL_STATUS_INVALID_CREDENTIALS ((sl_status_t)0x002A) ///< Invalid credentials. +#define SL_STATUS_INVALID_COUNT ((sl_status_t)0x002B) ///< Invalid count. +#define SL_STATUS_INVALID_SIGNATURE ((sl_status_t)0x002C) ///< Invalid signature / verification failed. +#define SL_STATUS_NOT_FOUND ((sl_status_t)0x002D) ///< Item could not be found. +#define SL_STATUS_ALREADY_EXISTS ((sl_status_t)0x002E) ///< Item already exists. + +// IO/Communication Errors +#define SL_STATUS_IO ((sl_status_t)0x002F) ///< Generic I/O failure. +#define SL_STATUS_IO_TIMEOUT ((sl_status_t)0x0030) ///< I/O failure due to timeout. +#define SL_STATUS_TRANSMIT ((sl_status_t)0x0031) ///< Generic transmission error. +#define SL_STATUS_TRANSMIT_UNDERFLOW ((sl_status_t)0x0032) ///< Transmit underflowed. +#define SL_STATUS_TRANSMIT_INCOMPLETE ((sl_status_t)0x0033) ///< Transmit is incomplete. +#define SL_STATUS_TRANSMIT_BUSY ((sl_status_t)0x0034) ///< Transmit is busy. +#define SL_STATUS_RECEIVE ((sl_status_t)0x0035) ///< Generic reception error. +#define SL_STATUS_OBJECT_READ ((sl_status_t)0x0036) ///< Failed to read on/via given object. +#define SL_STATUS_OBJECT_WRITE ((sl_status_t)0x0037) ///< Failed to write on/via given object. +#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long. + +// EEPROM/Flash Errors +#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch. +#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch. +#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited. +#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed. +#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed. +#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed. + +// MAC Errors +#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data. +#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received. +#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout. +#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type. +#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type. +#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure. + +// CLI_STORAGE Errors +#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM + +// Security status codes +#define SL_STATUS_SECURITY_IMAGE_CHECKSUM_ERROR ((sl_status_t)0x0046) ///< Image checksum is not valid. +#define SL_STATUS_SECURITY_DECRYPT_ERROR ((sl_status_t)0x0047) ///< Decryption failed + +// Command status codes +#define SL_STATUS_COMMAND_IS_INVALID ((sl_status_t)0x0048) ///< Command was not recognized +#define SL_STATUS_COMMAND_TOO_LONG ((sl_status_t)0x0049) ///< Command or parameter maximum length exceeded +#define SL_STATUS_COMMAND_INCOMPLETE ((sl_status_t)0x004A) ///< Data received does not form a complete command + +// Misc Errors +#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address + +// Unified MAC Errors +#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure. + +// Scan errors +#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning. +#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type. +#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask. +#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration. + +// MAC transmit related status +#define SL_STATUS_MAC_TRANSMIT_QUEUE_FULL ((sl_status_t)0x0053) ///< The MAC transmit queue is full +#define SL_STATUS_TRANSMIT_SCHEDULER_FAIL ((sl_status_t)0x0054) ///< The transmit attempt failed because the radio scheduler could not find a slot to transmit this packet in or a higher priority event interrupted it +#define SL_STATUS_TRANSMIT_INVALID_CHANNEL ((sl_status_t)0x0055) ///< An unsupported channel setting was specified +#define SL_STATUS_TRANSMIT_INVALID_POWER ((sl_status_t)0x0056) ///< An unsupported power setting was specified +#define SL_STATUS_TRANSMIT_ACK_RECEIVED ((sl_status_t)0x0057) ///< The expected ACK was received after the last transmission +#define SL_STATUS_TRANSMIT_BLOCKED ((sl_status_t)0x0058) ///< The transmit attempt was blocked from going over the air. Typically this is due to the Radio Hold Off (RHO) or Coexistence plugins as they can prevent transmits based on external signals. + +// NVM3 specific errors +#define SL_STATUS_NVM3_ALIGNMENT_INVALID ((sl_status_t)0x0059) ///< The initialization was aborted as the NVM3 instance is not aligned properly in memory +#define SL_STATUS_NVM3_SIZE_TOO_SMALL ((sl_status_t)0x005A) ///< The initialization was aborted as the size of the NVM3 instance is too small +#define SL_STATUS_NVM3_PAGE_SIZE_NOT_SUPPORTED ((sl_status_t)0x005B) ///< The initialization was aborted as the NVM3 page size is not supported +#define SL_STATUS_NVM3_TOKEN_INIT_FAILED ((sl_status_t)0x005C) ///< The application that there was an error initializing some of the tokens +#define SL_STATUS_NVM3_OPENED_WITH_OTHER_PARAMETERS ((sl_status_t)0x005D) ///< The initialization was aborted as the NVM3 instance was already opened with other parameters +#define SL_STATUS_NVM3_NO_VALID_PAGES ((sl_status_t)0x005E) ///< Initialization aborted, no valid page found +#define SL_STATUS_NVM3_OBJECT_SIZE_NOT_SUPPORTED ((sl_status_t)0x005F) ///< The object size is not supported +#define SL_STATUS_NVM3_OBJECT_IS_NOT_DATA ((sl_status_t)0x0060) ///< Trying to access a data object which is currently a counter object +#define SL_STATUS_NVM3_OBJECT_IS_NOT_A_COUNTER ((sl_status_t)0x0061) ///< Trying to access a counter object which is currently a data object +#define SL_STATUS_NVM3_WRITE_DATA_SIZE ((sl_status_t)0x0062) ///< The object is too large +#define SL_STATUS_NVM3_READ_DATA_SIZE ((sl_status_t)0x0063) ///< Trying to read with a length different from actual object size +#define SL_STATUS_NVM3_INIT_WITH_FULL_NVM ((sl_status_t)0x0064) ///< The module was opened with a full NVM +#define SL_STATUS_NVM3_RESIZE_PARAMETER ((sl_status_t)0x0065) ///< Illegal parameter +#define SL_STATUS_NVM3_RESIZE_NOT_ENOUGH_SPACE ((sl_status_t)0x0066) ///< Not enough NVM to complete resize +#define SL_STATUS_NVM3_ERASE_COUNT_ERROR ((sl_status_t)0x0067) ///< Erase counts are not valid +#define SL_STATUS_NVM3_NVM_ACCESS ((sl_status_t)0x0068) ///< A NVM function call was failing +#define SL_STATUS_NVM3_CRYPTO_INIT_FAILED ((sl_status_t)0x0069) ///< Crypto initialization failed +#define SL_STATUS_NVM3_ENCRYPTION_KEY_ERROR ((sl_status_t)0x006A) ///< Error in obtaining encryption key +#define SL_STATUS_NVM3_RANDOM_NUM_GENERATION_FAILED ((sl_status_t)0x006B) ///< Error in obtaining random number +#define SL_STATUS_NVM3_ENCRYPTION_FAILED ((sl_status_t)0x006C) ///< Encryption failed +#define SL_STATUS_NVM3_WRITE_TO_NOT_ERASED ((sl_status_t)0x006D) ///< Write to memory that is not erased +#define SL_STATUS_NVM3_INVALID_ADDR ((sl_status_t)0x006E) ///< Invalid NVM address +#define SL_STATUS_NVM3_KEY_MISMATCH ((sl_status_t)0x006F) ///< Key validation failure +#define SL_STATUS_NVM3_SIZE_ERROR ((sl_status_t)0x0070) ///< Size mismatch error +#define SL_STATUS_NVM3_EMULATOR ((sl_status_t)0x0071) ///< Emulator error +#define SL_STATUS_NVM3_SECURITY_INIT_FAILED ((sl_status_t)0x0072) ///< Security init failed +#define SL_STATUS_NVM3_GET_REGION_LOCATION_FAILED ((sl_status_t)0x0073) ///< Get data region location failed + +// Bluetooth status codes +#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. +#define SL_STATUS_BT_UNSPECIFIED ((sl_status_t)0x0403) ///< Unspecified error +#define SL_STATUS_BT_HARDWARE ((sl_status_t)0x0404) ///< Hardware failure +#define SL_STATUS_BT_NO_BONDING ((sl_status_t)0x0406) ///< The bonding does not exist. +#define SL_STATUS_BT_CRYPTO ((sl_status_t)0x0407) ///< Error using crypto functions +#define SL_STATUS_BT_DATA_CORRUPTED ((sl_status_t)0x0408) ///< Data was corrupted. +#define SL_STATUS_BT_INVALID_SYNC_HANDLE ((sl_status_t)0x040A) ///< Invalid periodic advertising sync handle +#define SL_STATUS_BT_INVALID_MODULE_ACTION ((sl_status_t)0x040B) ///< Bluetooth cannot be used on this hardware +#define SL_STATUS_BT_RADIO ((sl_status_t)0x040C) ///< Error received from radio +#define SL_STATUS_BT_L2CAP_REMOTE_DISCONNECTED ((sl_status_t)0x040D) ///< Returned when remote disconnects the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_LOCAL_DISCONNECTED ((sl_status_t)0x040E) ///< Returned when local host disconnect the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_CID_NOT_EXIST ((sl_status_t)0x040F) ///< Returned when local host did not find a connection-oriented channel with given destination CID. +#define SL_STATUS_BT_L2CAP_LE_DISCONNECTED ((sl_status_t)0x0410) ///< Returned when connection-oriented channel disconnected due to LE connection is dropped. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_VIOLATED ((sl_status_t)0x0412) ///< Returned when connection-oriented channel disconnected due to remote end send data even without credit. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_CREDIT_OVERFLOWED ((sl_status_t)0x0413) ///< Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. +#define SL_STATUS_BT_L2CAP_NO_FLOW_CONTROL_CREDIT ((sl_status_t)0x0414) ///< Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. +#define SL_STATUS_BT_L2CAP_CONNECTION_REQUEST_TIMEOUT ((sl_status_t)0x0415) ///< Returned when connection-oriented channel has not received connection response message within maximum timeout. +#define SL_STATUS_BT_L2CAP_INVALID_CID ((sl_status_t)0x0416) ///< Returned when local host received a connection-oriented channel connection response with an invalid destination CID. +#define SL_STATUS_BT_L2CAP_WRONG_STATE ((sl_status_t)0x0417) ///< Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. +#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full +#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found +#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level +#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed. + +// Bluetooth controller status codes +#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled. +#define SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE ((sl_status_t)0x1005) ///< Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key +#define SL_STATUS_BT_CTRL_PIN_OR_KEY_MISSING ((sl_status_t)0x1006) ///< Pairing failed because of missing PIN, or authentication failed because of missing Key +#define SL_STATUS_BT_CTRL_MEMORY_CAPACITY_EXCEEDED ((sl_status_t)0x1007) ///< Controller is out of memory. +#define SL_STATUS_BT_CTRL_CONNECTION_TIMEOUT ((sl_status_t)0x1008) ///< Link supervision timeout has expired. +#define SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x1009) ///< Controller is at limit of connections it can support. +#define SL_STATUS_BT_CTRL_SYNCHRONOUS_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x100A) ///< The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. +#define SL_STATUS_BT_CTRL_ACL_CONNECTION_ALREADY_EXISTS ((sl_status_t)0x100B) ///< The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. +#define SL_STATUS_BT_CTRL_COMMAND_DISALLOWED ((sl_status_t)0x100C) ///< Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES ((sl_status_t)0x100D) ///< The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS ((sl_status_t)0x100E) ///< The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR ((sl_status_t)0x100F) ///< The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. +#define SL_STATUS_BT_CTRL_CONNECTION_ACCEPT_TIMEOUT_EXCEEDED ((sl_status_t)0x1010) ///< The Connection Accept Timeout has been exceeded for this connection attempt. +#define SL_STATUS_BT_CTRL_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE ((sl_status_t)0x1011) ///< A feature or parameter value in the HCI command is not supported. +#define SL_STATUS_BT_CTRL_INVALID_COMMAND_PARAMETERS ((sl_status_t)0x1012) ///< Command contained invalid parameters. +#define SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED ((sl_status_t)0x1013) ///< User on the remote device terminated the connection. +#define SL_STATUS_BT_CTRL_REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES ((sl_status_t)0x1014) ///< The remote device terminated the connection because of low resources +#define SL_STATUS_BT_CTRL_REMOTE_POWERING_OFF ((sl_status_t)0x1015) ///< Remote Device Terminated Connection due to Power Off +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST ((sl_status_t)0x1016) ///< Local device terminated the connection. +#define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. +#define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing +#define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. +#define SL_STATUS_BT_CTRL_INVALID_LL_PARAMETERS ((sl_status_t)0x101E) ///< Indicates that some LMP PDU / LL Control PDU parameters were invalid +#define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. +#define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. +#define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. +#define SL_STATUS_BT_CTRL_ENCRYPTION_MODE_NOT_ACCEPTABLE ((sl_status_t)0x1025) ///< The requested encryption mode is not acceptable at this time. +#define SL_STATUS_BT_CTRL_LINK_KEY_CANNOT_BE_CHANGED ((sl_status_t)0x1026) ///< Link key cannot be changed because a fixed unit key is being used. +#define SL_STATUS_BT_CTRL_INSTANT_PASSED ((sl_status_t)0x1028) ///< LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. +#define SL_STATUS_BT_CTRL_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED ((sl_status_t)0x1029) ///< It was not possible to pair as a unit key was requested and it is not supported. +#define SL_STATUS_BT_CTRL_DIFFERENT_TRANSACTION_COLLISION ((sl_status_t)0x102A) ///< LMP transaction was started that collides with an ongoing transaction. +#define SL_STATUS_BT_CTRL_CHANNEL_ASSESSMENT_NOT_SUPPORTED ((sl_status_t)0x102E) ///< The Controller cannot perform channel assessment because it is not supported. +#define SL_STATUS_BT_CTRL_INSUFFICIENT_SECURITY ((sl_status_t)0x102F) ///< The HCI command or LMP PDU sent is only possible on an encrypted link. +#define SL_STATUS_BT_CTRL_PARAMETER_OUT_OF_MANDATORY_RANGE ((sl_status_t)0x1030) ///< A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. +#define SL_STATUS_BT_CTRL_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST ((sl_status_t)0x1037) ///< The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. +#define SL_STATUS_BT_CTRL_HOST_BUSY_PAIRING ((sl_status_t)0x1038) ///< The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation. +#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request. +#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval. +#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. +#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. +#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. +#define SL_STATUS_BT_CTRL_COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING ((sl_status_t)0x1040) ///< The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. +#define SL_STATUS_BT_CTRL_UNKNOWN_ADVERTISING_IDENTIFIER ((sl_status_t)0x1042) ///< A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. +#define SL_STATUS_BT_CTRL_LIMIT_REACHED ((sl_status_t)0x1043) ///< Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). +#define SL_STATUS_BT_CTRL_OPERATION_CANCELLED_BY_HOST ((sl_status_t)0x1044) ///< A request to the Controller issued by the Host and still pending was successfully canceled. +#define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. +#define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. +#define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. +#define SL_STATUS_BT_CTRL_INSUFFICIENT_CHANNELS ((sl_status_t)0x1048) ///< Indicates that the result of the requested operation would yield too few physical channels. + +// Bluetooth attribute status codes +#define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server +#define SL_STATUS_BT_ATT_READ_NOT_PERMITTED ((sl_status_t)0x1102) ///< The attribute cannot be read +#define SL_STATUS_BT_ATT_WRITE_NOT_PERMITTED ((sl_status_t)0x1103) ///< The attribute cannot be written +#define SL_STATUS_BT_ATT_INVALID_PDU ((sl_status_t)0x1104) ///< The attribute PDU was invalid +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHENTICATION ((sl_status_t)0x1105) ///< The attribute requires authentication before it can be read or written. +#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client. +#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written. +#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued +#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range. +#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient. +#define SL_STATUS_BT_ATT_INVALID_ATT_LENGTH ((sl_status_t)0x110D) ///< The attribute value length is invalid for the operation +#define SL_STATUS_BT_ATT_UNLIKELY_ERROR ((sl_status_t)0x110E) ///< The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENCRYPTION ((sl_status_t)0x110F) ///< The attribute requires encryption before it can be read or written. +#define SL_STATUS_BT_ATT_UNSUPPORTED_GROUP_TYPE ((sl_status_t)0x1110) ///< The attribute type is not a supported grouping attribute as defined by a higher layer specification. +#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request +#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database. +#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed. +#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. +#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions. +#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service. +#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress. +#define SL_STATUS_BT_ATT_OUT_OF_RANGE ((sl_status_t)0x11FF) ///< The attribute value is out of range as defined by a profile or service specification. + +// Bluetooth Security Manager Protocol status codes +#define SL_STATUS_BT_SMP_PASSKEY_ENTRY_FAILED ((sl_status_t)0x1201) ///< The user input of passkey failed, for example, the user cancelled the operation +#define SL_STATUS_BT_SMP_OOB_NOT_AVAILABLE ((sl_status_t)0x1202) ///< Out of Band data is not available for authentication +#define SL_STATUS_BT_SMP_AUTHENTICATION_REQUIREMENTS ((sl_status_t)0x1203) ///< The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices +#define SL_STATUS_BT_SMP_CONFIRM_VALUE_FAILED ((sl_status_t)0x1204) ///< The confirm value does not match the calculated compare value +#define SL_STATUS_BT_SMP_PAIRING_NOT_SUPPORTED ((sl_status_t)0x1205) ///< Pairing is not supported by the device +#define SL_STATUS_BT_SMP_ENCRYPTION_KEY_SIZE ((sl_status_t)0x1206) ///< The resultant encryption key size is insufficient for the security requirements of this device +#define SL_STATUS_BT_SMP_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1207) ///< The SMP command received is not supported on this device +#define SL_STATUS_BT_SMP_UNSPECIFIED_REASON ((sl_status_t)0x1208) ///< Pairing failed due to an unspecified reason +#define SL_STATUS_BT_SMP_REPEATED_ATTEMPTS ((sl_status_t)0x1209) ///< Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request +#define SL_STATUS_BT_SMP_INVALID_PARAMETERS ((sl_status_t)0x120A) ///< The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. +#define SL_STATUS_BT_SMP_DHKEY_CHECK_FAILED ((sl_status_t)0x120B) ///< Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. +#define SL_STATUS_BT_SMP_NUMERIC_COMPARISON_FAILED ((sl_status_t)0x120C) ///< Indicates that the confirm values in the numeric comparison protocol do not match. +#define SL_STATUS_BT_SMP_BREDR_PAIRING_IN_PROGRESS ((sl_status_t)0x120D) ///< Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. +#define SL_STATUS_BT_SMP_CROSS_TRANSPORT_KEY_DERIVATION_GENERATION_NOT_ALLOWED ((sl_status_t)0x120E) ///< Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. +#define SL_STATUS_BT_SMP_KEY_REJECTED ((sl_status_t)0x120F) ///< Indicates that the device chose not to accept a distributed key. + +// Bluetooth Mesh status codes +#define SL_STATUS_BT_MESH_ALREADY_EXISTS ((sl_status_t)0x0501) ///< Returned when trying to add a key or some other unique resource with an ID which already exists +#define SL_STATUS_BT_MESH_DOES_NOT_EXIST ((sl_status_t)0x0502) ///< Returned when trying to manipulate a key or some other resource with an ID which does not exist +#define SL_STATUS_BT_MESH_LIMIT_REACHED ((sl_status_t)0x0503) ///< Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached +#define SL_STATUS_BT_MESH_INVALID_ADDRESS ((sl_status_t)0x0504) ///< Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device +#define SL_STATUS_BT_MESH_MALFORMED_DATA ((sl_status_t)0x0505) ///< In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data +#define SL_STATUS_BT_MESH_ALREADY_INITIALIZED ((sl_status_t)0x0506) ///< An attempt was made to initialize a subsystem that was already initialized. +#define SL_STATUS_BT_MESH_NOT_INITIALIZED ((sl_status_t)0x0507) ///< An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. +#define SL_STATUS_BT_MESH_NO_FRIEND_OFFER ((sl_status_t)0x0508) ///< Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. +#define SL_STATUS_BT_MESH_PROV_LINK_CLOSED ((sl_status_t)0x0509) ///< Provisioning link was unexpectedly closed before provisioning was complete. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU ((sl_status_t)0x050A) ///< An unrecognized provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU_FORMAT ((sl_status_t)0x050B) ///< A provisioning PDU with wrong length or containing field values that are out of bounds was received. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_PDU ((sl_status_t)0x050C) ///< An unexpected (out of sequence) provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_CONFIRMATION_FAILED ((sl_status_t)0x050D) ///< The computed confirmation value did not match the expected value. +#define SL_STATUS_BT_MESH_PROV_OUT_OF_RESOURCES ((sl_status_t)0x050E) ///< Provisioning could not be continued due to insufficient resources. +#define SL_STATUS_BT_MESH_PROV_DECRYPTION_FAILED ((sl_status_t)0x050F) ///< The provisioning data block could not be decrypted. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_ERROR ((sl_status_t)0x0510) ///< An unexpected error happened during provisioning. +#define SL_STATUS_BT_MESH_PROV_CANNOT_ASSIGN_ADDR ((sl_status_t)0x0511) ///< Device could not assign unicast addresses to all of its elements. +#define SL_STATUS_BT_MESH_ADDRESS_TEMPORARILY_UNAVAILABLE ((sl_status_t)0x0512) ///< Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. +#define SL_STATUS_BT_MESH_ADDRESS_ALREADY_USED ((sl_status_t)0x0513) ///< Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. +#define SL_STATUS_BT_MESH_PUBLISH_NOT_CONFIGURED ((sl_status_t)0x0514) ///< Application key or publish address are not set +#define SL_STATUS_BT_MESH_APP_KEY_NOT_BOUND ((sl_status_t)0x0515) ///< Application key is not bound to a model + +// Bluetooth Mesh foundation status codes +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_ADDRESS ((sl_status_t)0x1301) ///< Returned when address in request was not valid +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_MODEL ((sl_status_t)0x1302) ///< Returned when model identified is not found for a given element +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_APP_KEY ((sl_status_t)0x1303) ///< Returned when the key identified by AppKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_NET_KEY ((sl_status_t)0x1304) ///< Returned when the key identified by NetKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INSUFFICIENT_RESOURCES ((sl_status_t)0x1305) ///< Returned when The node cannot serve the request due to insufficient resources +#define SL_STATUS_BT_MESH_FOUNDATION_KEY_INDEX_EXISTS ((sl_status_t)0x1306) ///< Returned when the key identified is already stored in the node and the new NetKey value is different +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_PUBLISH_PARAMS ((sl_status_t)0x1307) ///< Returned when the model does not support the publish mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUBSCRIBE_MODEL ((sl_status_t)0x1308) ///< Returned when the model does not support the subscribe mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_STORAGE_FAILURE ((sl_status_t)0x1309) ///< Returned when storing of the requested parameters failed +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUPPORTED ((sl_status_t)0x130A) ///< Returned when requested setting is not supported +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_UPDATE ((sl_status_t)0x130B) ///< Returned when the requested update operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_REMOVE ((sl_status_t)0x130C) ///< Returned when the requested delete operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_BIND ((sl_status_t)0x130D) ///< Returned when the requested bind operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_TEMPORARILY_UNABLE ((sl_status_t)0x130E) ///< Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_SET ((sl_status_t)0x130F) ///< Returned when the requested state cannot be set +#define SL_STATUS_BT_MESH_FOUNDATION_UNSPECIFIED ((sl_status_t)0x1310) ///< Returned when an unspecified error took place +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_BINDING ((sl_status_t)0x1311) ///< Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update + +// ----------------------------------------------------------------------------- +// Wi-Fi Errors + +#define SL_STATUS_WIFI_INVALID_KEY ((sl_status_t)0x0B01) ///< Invalid firmware keyset +#define SL_STATUS_WIFI_FIRMWARE_DOWNLOAD_TIMEOUT ((sl_status_t)0x0B02) ///< The firmware download took too long +#define SL_STATUS_WIFI_UNSUPPORTED_MESSAGE_ID ((sl_status_t)0x0B03) ///< Unknown request ID or wrong interface ID used +#define SL_STATUS_WIFI_WARNING ((sl_status_t)0x0B04) ///< The request is successful but some parameters have been ignored +#define SL_STATUS_WIFI_NO_PACKET_TO_RECEIVE ((sl_status_t)0x0B05) ///< No Packets waiting to be received +#define SL_STATUS_WIFI_SLEEP_GRANTED ((sl_status_t)0x0B08) ///< The sleep mode is granted +#define SL_STATUS_WIFI_SLEEP_NOT_GRANTED ((sl_status_t)0x0B09) ///< The WFx does not go back to sleep +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ERROR ((sl_status_t)0x0B10) ///< The SecureLink MAC key was not found +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ALREADY_BURNED ((sl_status_t)0x0B11) ///< The SecureLink MAC key is already installed in OTP +#define SL_STATUS_WIFI_SECURE_LINK_RAM_MODE_NOT_ALLOWED ((sl_status_t)0x0B12) ///< The SecureLink MAC key cannot be installed in RAM +#define SL_STATUS_WIFI_SECURE_LINK_FAILED_UNKNOWN_MODE ((sl_status_t)0x0B13) ///< The SecureLink MAC key installation failed +#define SL_STATUS_WIFI_SECURE_LINK_EXCHANGE_FAILED ((sl_status_t)0x0B14) ///< SecureLink key (re)negotiation failed +#define SL_STATUS_WIFI_WRONG_STATE ((sl_status_t)0x0B18) ///< The device is in an inappropriate state to perform the request +#define SL_STATUS_WIFI_CHANNEL_NOT_ALLOWED ((sl_status_t)0x0B19) ///< The request failed due to regulatory limitations +#define SL_STATUS_WIFI_NO_MATCHING_AP ((sl_status_t)0x0B1A) ///< The connection request failed because no suitable AP was found +#define SL_STATUS_WIFI_CONNECTION_ABORTED ((sl_status_t)0x0B1B) ///< The connection request was aborted by host +#define SL_STATUS_WIFI_CONNECTION_TIMEOUT ((sl_status_t)0x0B1C) ///< The connection request failed because of a timeout +#define SL_STATUS_WIFI_CONNECTION_REJECTED_BY_AP ((sl_status_t)0x0B1D) ///< The connection request failed because the AP rejected the device +#define SL_STATUS_WIFI_CONNECTION_AUTH_FAILURE ((sl_status_t)0x0B1E) ///< The connection request failed because the WPA handshake did not complete successfully +#define SL_STATUS_WIFI_RETRY_EXCEEDED ((sl_status_t)0x0B1F) ///< The request failed because the retry limit was exceeded +#define SL_STATUS_WIFI_TX_LIFETIME_EXCEEDED ((sl_status_t)0x0B20) ///< The request failed because the MSDU life time was exceeded + +// ----------------------------------------------------------------------------- + +// MVP Driver and MVP Math status codes +#define SL_STATUS_COMPUTE_DRIVER_FAULT ((sl_status_t)0x1501) ///< Critical fault +#define SL_STATUS_COMPUTE_DRIVER_ALU_NAN ((sl_status_t)0x1502) ///< ALU operation output NaN +#define SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW ((sl_status_t)0x1503) ///< ALU numeric overflow +#define SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW ((sl_status_t)0x1504) ///< ALU numeric underflow +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW ((sl_status_t)0x1505) ///< Overflow during array store +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW ((sl_status_t)0x1506) ///< Underflow during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion + +#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered +#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered +#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow +#define SL_STATUS_COMPUTE_MATH_UNDERFLOW ((sl_status_t)0x1515) ///< MATH numeric underflow + +// Zigbee status codes + +#define SL_STATUS_ZIGBEE_PACKET_HANDOFF_DROPPED ((sl_status_t)0x0C01) ///< Packet is dropped by packet-handoff callbacks +#define SL_STATUS_ZIGBEE_DELIVERY_FAILED ((sl_status_t)0x0C02) ///< The APS layer attempted to send or deliver a message and failed +#define SL_STATUS_ZIGBEE_MAX_MESSAGE_LIMIT_REACHED ((sl_status_t)0x0C03) ///< The maximum number of in-flight messages ::EMBER_APS_UNICAST_MESSAGE_COUNT has been reached +#define SL_STATUS_ZIGBEE_BINDING_IS_ACTIVE ((sl_status_t)0x0C04) ///< The application is trying to delete or overwrite a binding that is in use +#define SL_STATUS_ZIGBEE_ADDRESS_TABLE_ENTRY_IS_ACTIVE ((sl_status_t)0x0C05) ///< The application is trying to overwrite an address table entry that is in use +#define SL_STATUS_ZIGBEE_MOVE_FAILED ((sl_status_t)0x0C06) ///< After moving, a mobile node's attempt to re-establish contact with the network failed +#define SL_STATUS_ZIGBEE_NODE_ID_CHANGED ((sl_status_t)0x0C07) ///< The local node ID has changed. The application can get the new node ID by calling ::sl_zigbee_get_node_id() +#define SL_STATUS_ZIGBEE_INVALID_SECURITY_LEVEL ((sl_status_t)0x0C08) ///< The chosen security level is not supported by the stack +#define SL_STATUS_ZIGBEE_IEEE_ADDRESS_DISCOVERY_IN_PROGRESS ((sl_status_t)0x0C09) ///< An error occurred when trying to encrypt at the APS Level +#define SL_STATUS_ZIGBEE_APS_ENCRYPTION_ERROR ((sl_status_t)0x0C0A) ///< An error occurred when trying to encrypt at the APS Level +#define SL_STATUS_ZIGBEE_SECURITY_STATE_NOT_SET ((sl_status_t)0x0C0B) ///< There was an attempt to form or join a network with security without calling ::sl_zigbee_set_initial_security_state() first +#define SL_STATUS_ZIGBEE_TOO_SOON_FOR_SWITCH_KEY ((sl_status_t)0x0C0C) ///< There was an attempt to broadcast a key switch too quickly after broadcasting the next network key. The Trust Center must wait at least a period equal to the broadcast timeout so that all routers have a chance to receive the broadcast of the new network key +#define SL_STATUS_ZIGBEE_SIGNATURE_VERIFY_FAILURE ((sl_status_t)0x0C0D) ///< The received signature corresponding to the message that was passed to the CBKE Library failed verification and is not valid +#define SL_STATUS_ZIGBEE_KEY_NOT_AUTHORIZED ((sl_status_t)0x0C0E) ///< The message could not be sent because the link key corresponding to the destination is not authorized for use in APS data messages +#define SL_STATUS_ZIGBEE_BINDING_HAS_CHANGED ((sl_status_t)0x0C0F) ///< The application tried to use a binding that has been remotely modified and the change has not yet been reported to the application +#define SL_STATUS_ZIGBEE_TRUST_CENTER_SWAP_EUI_HAS_CHANGED ((sl_status_t)0x0C10) ///< The EUI of the Trust center has changed due to a successful rejoin after TC Swapout +#define SL_STATUS_ZIGBEE_TRUST_CENTER_SWAP_EUI_HAS_NOT_CHANGED ((sl_status_t)0x0C11) ///< A Trust Center Swapout Rejoin has occurred without the EUI of the TC changing +#define SL_STATUS_ZIGBEE_INSUFFICIENT_RANDOM_DATA ((sl_status_t)0x0C12) ///< An attempt to generate random bytes failed because of insufficient random data from the radio +#define SL_STATUS_ZIGBEE_SOURCE_ROUTE_FAILURE ((sl_status_t)0x0C13) ///< A Zigbee route error command frame was received indicating that a source routed message from this node failed en route +#define SL_STATUS_ZIGBEE_MANY_TO_ONE_ROUTE_FAILURE ((sl_status_t)0x0C14) ///< A Zigbee route error command frame was received indicating that a message sent to this node along a many-to-one route failed en route +#define SL_STATUS_ZIGBEE_STACK_AND_HARDWARE_MISMATCH ((sl_status_t)0x0C15) ///< A critical and fatal error indicating that the version of the stack trying to run does not match with the chip it's running on +#define SL_STATUS_ZIGBEE_PAN_ID_CHANGED ((sl_status_t)0x0C16) ///< The local PAN ID has changed. The application can get the new PAN ID by calling ::emberGetPanId() +#define SL_STATUS_ZIGBEE_CHANNEL_CHANGED ((sl_status_t)0x0C17) ///< The channel has changed. +#define SL_STATUS_ZIGBEE_NETWORK_OPENED ((sl_status_t)0x0C18) ///< The network has been opened for joining. +#define SL_STATUS_ZIGBEE_NETWORK_CLOSED ((sl_status_t)0x0C19) ///< The network has been closed for joining. +#define SL_STATUS_ZIGBEE_RECEIVED_KEY_IN_THE_CLEAR ((sl_status_t)0x0C1A) ///< An attempt was made to join a Secured Network using a pre-configured key, but the Trust Center sent back a Network Key in-the-clear when an encrypted Network Key was required. (::EMBER_REQUIRE_ENCRYPTED_KEY) +#define SL_STATUS_ZIGBEE_NO_NETWORK_KEY_RECEIVED ((sl_status_t)0x0C1B) ///< An attempt was made to join a Secured Network, but the device did not receive a Network Key. +#define SL_STATUS_ZIGBEE_NO_LINK_KEY_RECEIVED ((sl_status_t)0x0C1C) ///< After a device joined a Secured Network, a Link Key was requested (::EMBER_GET_LINK_KEY_WHEN_JOINING) but no response was ever received. +#define SL_STATUS_ZIGBEE_PRECONFIGURED_KEY_REQUIRED ((sl_status_t)0x0C1D) ///< An attempt was made to join a Secured Network without a pre-configured key, but the Trust Center sent encrypted data using a pre-configured key. +#define SL_STATUS_ZIGBEE_EZSP_ERROR ((sl_status_t)0x0C1E) ///< A Zigbee EZSP error has occured. Track the origin and corresponding EzspStatus for more info. + +// ----------------------------------------------------------------------------- +// Data Types +/** @brief define global status variable. */ +typedef uint32_t sl_status_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * sl_status_get_string_n() + * + * @brief Get a copy of the status string associated to the status code passed, up to + * 'buffer_length' length, if the string associated to the status code is enabled. If not, + * the error code number, in hex, prefixed by "SL_STATUS_" will be copied in the buffer + * instead. + * For example, the buffer would either contain "SL_STATUS_FAIL" if that status string is + * enabled, or "SL_STATUS_0x0001" if the string is disabled, as SL_STATUS_FAIL's + * value is 0x0001. + * + * @param status The status code from which to obtain the status string. + * + * @param buffer Pointer to a buffer in which the status string will be copied. A terminating + * null-character will be appended after the copied status string. + * + * @param buffer_length Maximum number of characters that can be written in the buffer, including the + * terminating null-character. If the status string would be longer than the + * available length, it will be truncated and a null-terminating character will + * be the last character contained in the buffer. + * + * @return The number of characters that would have been written if the buffer_length had been + * sufficiently large, not counting the terminating null character. + * If the status code is invalid, 0 or a negative number is returned. + * Notice that only when this returned value is strictly positive and less than + * buffer_length, the status string has been completely written in the buffer. + *******************************************************************************************************/ +int32_t sl_status_get_string_n(sl_status_t status, char *buffer, uint32_t buffer_length); + +/******************************************************************************************************** + * sl_status_print() + * + * @brief Print, through printf, the string associated to the passed status code. If the string + * associated to the status code is enabled, the status string will be printed, for example + * "SL_STATUS_OK". If the string associated to the status code is disabled, the status number, + * in hex, prefixed by "SL_STATUS_" will be printed instead, for example "SL_STATUS_0x0000", + * as SL_STATUS_OK's value is 0x0000. + * + * @param status The status code of which to print the status string. + *******************************************************************************************************/ +void sl_status_print(sl_status_t status); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup status) */ + +#endif /* SL_STATUS_H */ diff --git a/Libs/platform/common/inc/sli_cmsis_os2_ext_task_register.h b/Libs/platform/common/inc/sli_cmsis_os2_ext_task_register.h new file mode 100644 index 0000000..b998628 --- /dev/null +++ b/Libs/platform/common/inc/sli_cmsis_os2_ext_task_register.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file sli_cmsis_os2_ext_task_register.h + * @brief Abstraction for Task Registers (Thread Local Variables) + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_CMSIS_OS2_EXT_TASK_REGISTER_H +#define SLI_CMSIS_OS2_EXT_TASK_REGISTER_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +// Validate the chosen RTOS +#if !defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && !defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) +#error "The task register API currently only supports FreeRTOS or MicriumOS" +#endif + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) +#include "FreeRTOS.h" +#include "task.h" +// Validate maximum of task registers +#if configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS > 255 +#error "The task register API currently only supports a maximum of 255 registers" +#endif +// Check if the user has overwritten the configNUM_THREAD_LOCAL_STORAGE_POINTERS config +#if configNUM_THREAD_LOCAL_STORAGE_POINTERS < (configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS \ + + configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS) +#error "Please use the configUSER_NUM_THREAD_LOCAL_STORAGE_POINTERS to configure the local storage pointers" +#endif +#elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) +#include "os.h" +#endif + +#include "sl_status.h" +#include "cmsis_os2.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) +typedef uint8_t sli_task_register_id_t; +#elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) +typedef OS_REG_ID sli_task_register_id_t; +#endif + +/***************************************************************************//** + * Get the task register ID. + * + * @param[out] reg_id The task register id + * @return sl_status_t The status result + ******************************************************************************/ +sl_status_t sli_osTaskRegisterNew(sli_task_register_id_t *reg_id); + +/***************************************************************************//** + * Get the task register value. + * + * @param thread_id CMSIS-RTOS2 thread identification + * @param reg_id Task register ID + * @param[out] value Value of the task register requested + * @return sl_status_t The status result + ******************************************************************************/ +sl_status_t sli_osTaskRegisterGetValue(const osThreadId_t thread_id, + const sli_task_register_id_t reg_id, + uint32_t *value); + +/***************************************************************************//** + * Set the task register to the provided value. + * + * @param thread_id CMSIS-RTOS2 thread identification + * @param reg_id Task register ID + * @param[out] value Value of the task register to set + * @return sl_status_t The status result + ******************************************************************************/ +sl_status_t sli_osTaskRegisterSetValue(const osThreadId_t thread_id, + const sli_task_register_id_t reg_id, + const uint32_t value); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CMSIS_OS2_EXT_TASK_REGISTER_H diff --git a/Libs/platform/common/inc/sli_code_classification.h b/Libs/platform/common/inc/sli_code_classification.h new file mode 100644 index 0000000..f4729c6 --- /dev/null +++ b/Libs/platform/common/inc/sli_code_classification.h @@ -0,0 +1,131 @@ +/***************************************************************************//** + * @file + * @brief Code Classification API (Internal) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SLI_CODE_CLASSIFICATION_H_ +#define _SLI_CODE_CLASSIFICATION_H_ + +// Standard Code Classes +#define SL_CODE_CLASS_TIME_CRITICAL timecritical + +/******************************************************************************/ +/* Helper Macros */ +/******************************************************************************/ + +// Stringize tokens +#define _SL_CC_STRINGIZE(X) #X +#define _SL_CC_XSTRINGIZE(X) _SL_CC_STRINGIZE(X) +#define _SL_CC_CONCAT3(A, B, C) A B C +#define _SL_CC_CONCAT4(A, B, C, D) A B C D + +/******************************************************************************/ +/* Compiler Specific Macros */ +/******************************************************************************/ + +// The directive that is built is dependent on the compiler. Section names are +// appended with an identifier generated from __COUNTER__ and __LINE__ so that +// functions are more likely to be separated into unique sections. Doing this +// allows the linker to discard unused functions with more granularity. +#if defined(__GNUC__) && !(defined(__llvm__) || defined(SLI_CODE_CLASSIFICATION_DISABLE)) + +// With GCC, __attribute__ can be used to specify the input section of +// functions. +#define _SL_CC_SECTION(section_name, count, line) \ + __attribute__((section(_SL_CC_CONCAT3(_SL_CC_XSTRINGIZE(section_name), _SL_CC_XSTRINGIZE(count), _SL_CC_XSTRINGIZE(line))))) + +#elif defined(__ICCARM__) && !defined(SLI_CODE_CLASSIFICATION_DISABLE) + +// With IAR, _Pragma can be used to specify the input section of +// functions. +#define _SL_CC_SECTION(section_name, count, line) \ + _Pragma(_SL_CC_XSTRINGIZE(_SL_CC_CONCAT4(location =, _SL_CC_XSTRINGIZE(section_name), _SL_CC_XSTRINGIZE(count), _SL_CC_XSTRINGIZE(line)))) + +#elif defined(__llvm__) && !defined(SLI_CODE_CLASSIFICATION_DISABLE) + +// With llvm, __attribute__ can be used to specify the input section of +// functions. + +// However the syntax of the string within the section directive is +// dependent on the specifics of the target backend (e.g. osx) +#if defined(__MACH__) && defined(SLI_CODE_CLASSIFICATION_OSX_ENABLE) +// code classifcation is not supported on OSX and can have weird +// interactions for executable code so it is disabled by default +// since it can be useful for code analysis allow it as an opt-in feature +#define _SL_CC_SECTION(section_name, count, line) \ + __attribute__((section("sl_cc,code_class" _SL_CC_XSTRINGIZE(count) _SL_CC_XSTRINGIZE(line)))) +#else +#define _SL_CC_SECTION(section_name, count, line) +#endif // defined(__MACH__) + +#elif defined(SLI_CODE_CLASSIFICATION_DISABLE) + +#define _SL_CC_SECTION(section_name, count, line) + +#else + #error "(sli_code_classification.h): Code classification does not support \ + the chosen compiler." +#endif // __GNUC__ + +/******************************************************************************/ +/* Compiler Generic Macros */ +/******************************************************************************/ + +// Build the linker section name based on the name of the component and the +// code classes. +#define _SL_CODE_CLASS_SECTION_CONCAT1(component, p1) \ + text_ ## component ## _ ## p1 +#define _SL_CODE_CLASS_SECTION_CONCAT2(component, p1, p2) \ + text_ ## component ## _ ## p1 ## _ ## p2 + +// Build the compiler specific directives +#define _SL_CODE_CLASS1(component, c1) \ + _SL_CC_SECTION(_SL_CODE_CLASS_SECTION_CONCAT1(component, c1), __COUNTER__, __LINE__) +#define _SL_CODE_CLASS2(component, c1, c2) \ + _SL_CC_SECTION(_SL_CODE_CLASS_SECTION_CONCAT2(component, c1, c2), __COUNTER__, __LINE__) + +// Utilities to dispatch a macro with the correct number of parameters. +// Update COUNT_N and COUNT macros if the upper limit of code class +// combinations increases. +#define _SL_CC_COUNT_N(_1, _2, N, ...) N +#define _SL_CC_COUNT(...) _SL_CC_COUNT_N(__VA_ARGS__, 2, 1) +#define _SL_CC_IDENTITY(N) N +#define _SL_CC_APPLY(macro, ...) _SL_CC_IDENTITY(macro(__VA_ARGS__)) + +// Dispatch _SL_CODE_CLASSX with the correct number of parameters. +#define _SL_CC_DISPATCH(N) _SL_CODE_CLASS ## N + +/******************************************************************************/ +/* Macro API (Internal) */ +/******************************************************************************/ + +// Variadic macro to specify the code class membership of a function. +#define SL_CODE_CLASSIFY(component, ...) \ + _SL_CC_IDENTITY(_SL_CC_APPLY(_SL_CC_DISPATCH, _SL_CC_COUNT(__VA_ARGS__)))(component, __VA_ARGS__) + +#endif // _SLI_CODE_CLASSIFICATION_H_ diff --git a/Libs/platform/common/src/sl_assert.c b/Libs/platform/common/src/sl_assert.c new file mode 100644 index 0000000..5fbc325 --- /dev/null +++ b/Libs/platform/common/src/sl_assert.c @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Assert API + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include + +/***************************************************************************//** + * @addtogroup assert + * @details + * This module contains functions to control the ASSERT peripheral of Silicon + * Labs 32-bit MCUs and SoCs. + * @{ + ******************************************************************************/ + +#if defined(DEBUG_EFM) && !defined(DEBUG_EFM_USER) +/***************************************************************************//** + * @brief + * EFM internal assert handling. + * + * This function is invoked through EFM_ASSERT() macro usage only and should + * not be used explicitly. + * + * This implementation enters an indefinite loop, allowing + * the use of a debugger to determine a cause of failure. By defining + * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version + * of this function must be defined and will be invoked instead, possibly + * providing output of assertion location. + * + * @note + * This function is not used unless DEBUG_EFM is defined + * during preprocessing of EFM_ASSERT() usage. + * + * @param[in] file + * Name of the source file where assertion failed. + * + * @param[in] line + * A line number in the source file where assertion failed. + ******************************************************************************/ +void assertEFM(const char *file, int line) +{ + (void)file; /* Unused parameter */ + (void)line; /* Unused parameter */ + + while (true) { + } +} +#endif /* DEBUG_EFM && !DEBUG_EFM_USER */ + +/** @} (end addtogroup assert) */ diff --git a/Libs/platform/common/src/sl_cmsis_os2_common.c b/Libs/platform/common/src/sl_cmsis_os2_common.c new file mode 100644 index 0000000..0a8af02 --- /dev/null +++ b/Libs/platform/common/src/sl_cmsis_os2_common.c @@ -0,0 +1,61 @@ +/***************************************************************************//** + * @file + * @brief CMSIS OS2 Common + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_assert.h" +#include "sl_status.h" +#include "cmsis_os2.h" + +/***************************************************************************//** + * Convert OsStatus from CMSIS-RTOS2 to sl_status type. + ******************************************************************************/ +sl_status_t sl_cmsis_os_convert_status(osStatus_t os_status) +{ + switch (os_status) { + case osOK: + return SL_STATUS_OK; + case osError: + return SL_STATUS_FAIL; + case osErrorTimeout: + return SL_STATUS_TIMEOUT; + case osErrorResource: + return SL_STATUS_NOT_AVAILABLE; + case osErrorParameter: + return SL_STATUS_INVALID_PARAMETER; + case osErrorNoMemory: + return SL_STATUS_NO_MORE_RESOURCE; + case osErrorISR: + return SL_STATUS_ISR; + case osStatusReserved: + default: + EFM_ASSERT(0); + return SL_STATUS_FAIL; + } +} diff --git a/Libs/platform/common/src/sl_core_cortexm.c b/Libs/platform/common/src/sl_core_cortexm.c new file mode 100644 index 0000000..3b8b56e --- /dev/null +++ b/Libs/platform/common/src/sl_core_cortexm.c @@ -0,0 +1,395 @@ +/***************************************************************************//** + * @file + * @brief Core API implemented for CortexM + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_core.h" +#include "sl_core_config.h" +#include "sl_common.h" +#include "em_device.h" + +/**************************************************************************//** + * @addtogroup sl_core + * @{ + *****************************************************************************/ + +/******************************************************************************* + ************************** STRUCTS **************************************** + ******************************************************************************/ +/// A Cycle Counter Instance. +typedef struct { + uint32_t start; /*!< Cycle counter at start of recording. */ + uint32_t cycles; /*!< Cycles elapsed in last recording. */ + uint32_t max; /*!< Max recorded cycles since last reset or init. */ +} dwt_cycle_counter_handle_t; + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +// cycle counter to record atomic sections +dwt_cycle_counter_handle_t atomic_cycle_counter = { 0 }; +// cycle counter to record critical sections +dwt_cycle_counter_handle_t critical_cycle_counter = { 0 }; +#endif + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle); +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable interrupts. + ******************************************************************************/ +SL_WEAK void CORE_CriticalDisableIrq(void) +{ + __disable_irq(); +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. + ******************************************************************************/ +SL_WEAK void CORE_CriticalEnableIrq(void) +{ + __enable_irq(); + __ISB(); +} + +/***************************************************************************//** + * @brief + * Enter a CRITICAL section. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterCritical(void) +{ + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + if (irqState == 0U) { + cycle_counter_start(&critical_cycle_counter); + } +#endif + return irqState; +} + +/***************************************************************************//** + * @brief + * Exit a CRITICAL section. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. + ******************************************************************************/ +SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) +{ + if (irqState == 0U) { +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + cycle_counter_stop(&critical_cycle_counter); +#endif + __enable_irq(); + __ISB(); + } +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + ******************************************************************************/ +SL_WEAK void CORE_YieldCritical(void) +{ + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +} + +/***************************************************************************//** + * @brief + * Disable interrupts. + ******************************************************************************/ +SL_WEAK void CORE_AtomicDisableIrq(void) +{ +#ifndef __CM0PLUS_REV + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8UL - __NVIC_PRIO_BITS)); +#else + __disable_irq(); +#endif +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. + ******************************************************************************/ +SL_WEAK void CORE_AtomicEnableIrq(void) +{ +#ifndef __CM0PLUS_REV + __set_BASEPRI(0); +#else + __enable_irq(); +#endif + __ISB(); +} + +/***************************************************************************//** + * @brief + * Enter an ATOMIC section. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) +{ +#ifndef __CM0PLUS_REV + CORE_irqState_t irqState = __get_BASEPRI(); + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS)); +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { + cycle_counter_start(&atomic_cycle_counter); + } +#endif + return irqState; +#else + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + if (irqState == 0U) { + cycle_counter_start(&critical_cycle_counter); + } +#endif + return irqState; +#endif +} + +/***************************************************************************//** + * @brief + * Exit an ATOMIC section. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. + ******************************************************************************/ +SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) +{ +#ifndef __CM0PLUS_REV +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { + cycle_counter_stop(&atomic_cycle_counter); + } +#endif + __set_BASEPRI(irqState); + __ISB(); +#else + if (irqState == 0U) { +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + cycle_counter_stop(&critical_cycle_counter); +#endif + __enable_irq(); + __ISB(); + } +#endif +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + ******************************************************************************/ +SL_WEAK void CORE_YieldAtomic(void) +{ +#ifndef __CM0PLUS_REV + CORE_irqState_t basepri = __get_BASEPRI(); + if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { + __set_BASEPRI(0); + __ISB(); + __set_BASEPRI(basepri); + } +#else + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +#endif +} + +/***************************************************************************//** + * @brief + * Check whether the current CPU operation mode is handler mode. + ******************************************************************************/ +SL_WEAK bool CORE_InIrqContext(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; +} + +/***************************************************************************//** + * @brief + * Check if interrupts are disabled. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsDisabled(void) +{ +#ifndef __CM0PLUS_REV + return ((__get_PRIMASK() & 1U) == 1U) + || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL + << (8U - __NVIC_PRIO_BITS))); +#else + return (__get_PRIMASK() & 1U == 1U); +#endif +} + +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +/***************************************************************************//** + * @brief + * Start a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle) +{ + handle->start = DWT->CYCCNT; +} +#endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + +#if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +/***************************************************************************//** + * @brief + * Stop a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle) +{ + handle->cycles = DWT->CYCCNT - handle->start; + + if (handle->cycles > handle->max) { + handle->max = handle->cycles; + } +} +#endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + +/***************************************************************************//** + * @brief + * Returns the max time spent in critical section. + ******************************************************************************/ +uint32_t CORE_get_max_time_critical_section(void) +{ + #if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + return critical_cycle_counter.max; + #else + return 0U; + #endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +} + +/***************************************************************************//** + * @brief + * Returns the max time spent in atomic section. + ******************************************************************************/ +uint32_t CORE_get_max_time_atomic_section(void) +{ + #if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + return atomic_cycle_counter.max; + #else + return 0U; + #endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + ******************************************************************************/ +void CORE_clear_max_time_critical_section(void) +{ + #if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + critical_cycle_counter.max = 0; + #endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + ******************************************************************************/ +void CORE_clear_max_time_atomic_section(void) +{ + #if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) + atomic_cycle_counter.max = 0; + #endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) +} + +/***************************************************************************//** + * @brief + * Reset chip routine. + ******************************************************************************/ +void CORE_ResetSystem(void) +{ + // Ensure all outstanding memory accesses including buffered writes are + // completed before reset + __DSB(); + + // Keep priority group unchanged + SCB->AIRCR = (0x5FAUL << SCB_AIRCR_VECTKEY_Pos) + | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) + | SCB_AIRCR_SYSRESETREQ_Msk; + + // Ensure completion of memory access + __DSB(); + + // Wait until reset + for (;; ) { + __NOP(); + } +} + +/** @} (end addtogroup sl_core) */ diff --git a/Libs/platform/common/src/sl_slist.c b/Libs/platform/common/src/sl_slist.c new file mode 100644 index 0000000..8e9d117 --- /dev/null +++ b/Libs/platform/common/src/sl_slist.c @@ -0,0 +1,190 @@ +/***************************************************************************//** + * @file + * @brief Single Link List + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include "sl_slist.h" +#include +#include +#include + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes a singly-linked list. + ******************************************************************************/ +void sl_slist_init(sl_slist_node_t **head) +{ + *head = 0; +} + +/***************************************************************************//** + * Add given item at beginning of list. + ******************************************************************************/ +void sl_slist_push(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + EFM_ASSERT((item != NULL) && (head != NULL)); + + item->node = *head; + *head = item; +} + +/***************************************************************************//** + * Add item at end of list. + ******************************************************************************/ +void sl_slist_push_back(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + sl_slist_node_t **node_ptr = head; + + EFM_ASSERT((item != NULL) && (head != NULL)); + + while (*node_ptr != NULL) { + node_ptr = &((*node_ptr)->node); + } + + item->node = NULL; + *node_ptr = item; +} + +/***************************************************************************//** + * Removes and returns first element of list. + ******************************************************************************/ +sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head) +{ + sl_slist_node_t *item; + + EFM_ASSERT(head != NULL); + + item = *head; + if (item == NULL) { + return (NULL); + } + + *head = item->node; + + item->node = NULL; + + return (item); +} + +/***************************************************************************//** + * Insert item after given item. + ******************************************************************************/ +void sl_slist_insert(sl_slist_node_t *item, + sl_slist_node_t *pos) +{ + EFM_ASSERT((item != NULL) && (pos != NULL)); + + item->node = pos->node; + pos->node = item; +} + +/***************************************************************************//** + * Add item at end of list. + ******************************************************************************/ +void sl_slist_join(sl_slist_node_t **head_list_1, + sl_slist_node_t **head_list_2) +{ + sl_slist_node_t **node_ptr = head_list_1; + + EFM_ASSERT((head_list_2 != NULL) + && (head_list_1 != NULL)); + + while (*node_ptr != NULL) { + node_ptr = &((*node_ptr)->node); + } + + *node_ptr = *head_list_2; + *head_list_2 = NULL; +} + +/***************************************************************************//** + * Remove item from list. + ******************************************************************************/ +void sl_slist_remove(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + sl_slist_node_t **node_ptr; + + EFM_ASSERT((item != NULL) && (head != NULL)); + + for (node_ptr = head; *node_ptr != NULL; node_ptr = &((*node_ptr)->node)) { + if (*node_ptr == item) { + *node_ptr = item->node; + item->node = NULL; + return; + } + } +} + +/***************************************************************************//** + * Sorts list items. + ******************************************************************************/ +void sl_slist_sort(sl_slist_node_t **head, + bool (*cmp_fnct)(sl_slist_node_t *item_l, + sl_slist_node_t *item_r)) +{ + bool swapped; + sl_slist_node_t **pp_item_l; + + EFM_ASSERT((head != NULL) && (cmp_fnct != NULL)); + + do { + swapped = false; + + pp_item_l = head; + // Loop until end of list is found. + while ((*pp_item_l != NULL) && ((*pp_item_l)->node != NULL)) { + sl_slist_node_t *p_item_r = (*pp_item_l)->node; + bool ordered; + + // Call provided compare fnct. + ordered = cmp_fnct(*pp_item_l, p_item_r); + if (ordered == false) { + // If order is not correct, swap items. + sl_slist_node_t *p_tmp = p_item_r->node; + + // Swap the two items. + p_item_r->node = *pp_item_l; + (*pp_item_l)->node = p_tmp; + *pp_item_l = p_item_r; + pp_item_l = &(p_item_r->node); + // Indicate a swap has been done. + swapped = true; + } else { + pp_item_l = &((*pp_item_l)->node); + } + } + // Re-loop until no items have been swapped. + } while (swapped == true); +} diff --git a/Libs/platform/common/src/sl_syscalls.c b/Libs/platform/common/src/sl_syscalls.c new file mode 100644 index 0000000..826ad05 --- /dev/null +++ b/Libs/platform/common/src/sl_syscalls.c @@ -0,0 +1,115 @@ +/***************************************************************************//** + * @file + * @brief SystemCall API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup systemcalls + * @details + * This module reimplements the syscalls that don't have the definition in the + * bare metal project. + * This prevents linker warnings. + * @{ + ******************************************************************************/ +#include "sl_compiler.h" + +struct stat; +struct timeval; +struct timezone; + +__WEAK int _close(int file) +{ + (void)file; + return -1; +} + +__WEAK void _exit(int status) +{ + (void)status; + + /* Convince GCC that this function never returns. */ + for (;; ) { + ; + } +} + +__WEAK int _fstat(int file, struct stat *st) +{ + (void)file; + (void)(void *)st; + return 0; +} + +__WEAK int _getpid(void) +{ + return 1; +} + +__WEAK int _isatty(int file) +{ + (void)file; + return 1; +} + +__WEAK int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + return -1; +} + +__WEAK int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +__WEAK int _read(int file, char *ptr, int len) +{ + (void)file; + (void)(void *)ptr; + (void)len; + return 0; +} + +__WEAK int _write(int file, const char *ptr, int len) +{ + (void)file; + (void)(const void *)ptr; + (void)len; + return 0; +} + +__WEAK int _gettimeofday(struct timeval *tv, struct timezone *tz) +{ + (void)(void *)tv; + (void)(void *)tz; + return 0; +} diff --git a/Libs/platform/common/src/sli_cmsis_os2_ext_task_register.c b/Libs/platform/common/src/sli_cmsis_os2_ext_task_register.c new file mode 100644 index 0000000..7983c68 --- /dev/null +++ b/Libs/platform/common/src/sli_cmsis_os2_ext_task_register.c @@ -0,0 +1,143 @@ +/***************************************************************************//** + * @file sli_cmsis_os2_ext_task_register.c + * @brief Abstraction for Task Registers (Thread Local Variables) + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include "sli_cmsis_os2_ext_task_register.h" +#include "sl_cmsis_os2_common.h" + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Get a task register ID + ******************************************************************************/ +sl_status_t sli_osTaskRegisterNew(sli_task_register_id_t *reg_id) +{ + sl_status_t status = SL_STATUS_FAIL; + + if (reg_id == NULL) { + return SL_STATUS_FAIL; + } + +#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) + RTOS_ERR err; + + *reg_id = OSTaskRegGetID(&err); + if (RTOS_ERR_CODE_GET(err) == RTOS_ERR_NONE) { + status = SL_STATUS_OK; + } + +#elif defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + static uint8_t register_count = 0; + if (register_count > (configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS - 1)) { + return SL_STATUS_FAIL; + } + + *reg_id = register_count + configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS; + ++register_count; + status = SL_STATUS_OK; +#else +#error "Task registers abstraction only supports MicriumOS or FreeRTOS" +#endif + return status; +} + +/***************************************************************************//** + * Get the task register + ******************************************************************************/ +sl_status_t sli_osTaskRegisterGetValue(const osThreadId_t thread_id, + const sli_task_register_id_t reg_id, + uint32_t *value) +{ + sl_status_t status = SL_STATUS_FAIL; +#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) + RTOS_ERR err; + osThread_t *thread; + + if (value == NULL) { + return SL_STATUS_FAIL; + } + + if (thread_id != NULL) { + thread = (osThread_t *)thread_id; + *value = OSTaskRegGet(&thread->tcb, reg_id, &err); + } else { + *value = OSTaskRegGet(NULL, reg_id, &err); + } + + if (RTOS_ERR_CODE_GET(err) == RTOS_ERR_NONE) { + status = SL_STATUS_OK; + } +#elif defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + *value = (uint32_t)pvTaskGetThreadLocalStoragePointer(thread_id, reg_id); + status = SL_STATUS_OK; +#else +#error "Task registers abstraction only supports MicriumOS or FreeRTOS" +#endif + + return status; +} + +/***************************************************************************//** + * Set the task register + ******************************************************************************/ +sl_status_t sli_osTaskRegisterSetValue(const osThreadId_t thread_id, + const sli_task_register_id_t reg_id, + const uint32_t value) +{ + sl_status_t status = SL_STATUS_FAIL; +#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) + RTOS_ERR err; + osThread_t *thread; + + if (thread_id != NULL) { + thread = (osThread_t *)thread_id; + OSTaskRegSet(&thread->tcb, reg_id, (OS_REG)value, &err); + } else { + OSTaskRegSet(NULL, reg_id, (OS_REG)value, &err); + } + + if (RTOS_ERR_CODE_GET(err) == RTOS_ERR_NONE) { + status = SL_STATUS_OK; + } +#elif defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + vTaskSetThreadLocalStoragePointer(thread_id, reg_id, (void *)value); + status = SL_STATUS_OK; +#else +#error "Task registers abstraction only supports MicriumOS or FreeRTOS" +#endif + + return status; +} diff --git a/Libs/platform/common/toolchain/inc/sl_gcc_preinclude.h b/Libs/platform/common/toolchain/inc/sl_gcc_preinclude.h new file mode 100644 index 0000000..9745eba --- /dev/null +++ b/Libs/platform/common/toolchain/inc/sl_gcc_preinclude.h @@ -0,0 +1,40 @@ +/***************************************************************************//** + * @file + * @brief GCC startup file + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* The startup files contain a stack and heap symbol in addition + * to the vector table. The size of these internal stack and heap + * objects depend on the build system providing two macros on the + * commandline called __STACK_SIZE and __HEAP_SIZE. + * + * We provide alternative stack and heap symbols in the sl_memory_region.c + * file which can be configured in a separate config file. Go to + * sl_memory_manager_config.h to configure the stack and heap size. */ +#define __STACK_SIZE 0x0 +#define __HEAP_SIZE 0x0 diff --git a/Libs/platform/common/toolchain/inc/sl_memory.h b/Libs/platform/common/toolchain/inc/sl_memory.h new file mode 100644 index 0000000..d88df2e --- /dev/null +++ b/Libs/platform/common/toolchain/inc/sl_memory.h @@ -0,0 +1,39 @@ +/***************************************************************************//** + * @file + * @brief Heap and stack memory + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MEMORY_H +#define SL_MEMORY_H + +#include "sl_memory_manager_region.h" + +#ifndef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2024_6 +#warning "This file is deprecated as of Simplicity SDK 2024.6. Content was moved to sl_memory_manager.h." +#endif + +#endif // SL_MEMORY_H diff --git a/Libs/platform/common/toolchain/inc/sl_memory_region.h b/Libs/platform/common/toolchain/inc/sl_memory_region.h new file mode 100644 index 0000000..85f2a82 --- /dev/null +++ b/Libs/platform/common/toolchain/inc/sl_memory_region.h @@ -0,0 +1,39 @@ +/***************************************************************************//** + * @file + * @brief Memory region types + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_REGION_H +#define SL_REGION_H + +#include "sl_memory_manager_region.h" + +#ifndef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2024_6 +#warning "This file is deprecated as of Simplicity SDK 2024.6. Content was moved to sl_memory_manager.h." +#endif + +#endif diff --git a/Libs/platform/driver/button/inc/sl_button.h b/Libs/platform/driver/button/inc/sl_button.h new file mode 100644 index 0000000..19935b8 --- /dev/null +++ b/Libs/platform/driver/button/inc/sl_button.h @@ -0,0 +1,191 @@ +/***************************************************************************//** + * @file + * @brief Button Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BUTTON_H +#define SL_BUTTON_H + +#include "sl_common.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup button Button API + * @brief Generic Button API + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#define BUTTON_ERROR 0xFFFF ///< Error when trying to return state + +/******************************************************************************* + ***************************** DATA TYPES ********************************* + ******************************************************************************/ + +typedef uint8_t sl_button_mode_t; ///< BUTTON mode +typedef uint8_t sl_button_state_t; ///< BUTTON state +typedef struct sl_button sl_button_t; ///< BUTTON Instance structure + +/// A BUTTON instance +typedef struct sl_button { + void *context; ///< The context for this BUTTON instance + sl_status_t (*init)(const sl_button_t *handle); ///< Member function to initialize BUTTON instance + void (*poll)(const sl_button_t *handle); ///< Member function to poll BUTTON + void (*enable)(const sl_button_t *handle); ///< Member function to enable BUTTON + void (*disable)(const sl_button_t *handle); ///< Member function to disable BUTTON + sl_button_state_t (*get_state)(const sl_button_t *handle); ///< Member function to retrieve BUTTON state +} sl_button; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Button driver init. This function should be called before calling any other + * button function. Sets up the GPIO. Sets the mode of operation. Sets up the + * interrupts based on the mode of operation. + * + * @param[in] handle Pointer to button instance + * + * @return Status Code: + * - SL_STATUS_OK + ******************************************************************************/ +sl_status_t sl_button_init(const sl_button_t *handle); + +/***************************************************************************//** + * Get button state. + * + * @param[in] handle Pointer to button instance + * + * @return Button state Current state of the button + ******************************************************************************/ +sl_button_state_t sl_button_get_state(const sl_button_t *handle); + +/***************************************************************************//** + * Enable the button. + * + * @param[in] handle Pointer to button instance + * + ******************************************************************************/ +void sl_button_enable(const sl_button_t *handle); + +/***************************************************************************//** + * Disable the button. + * + * @param[in] handle Pointer to button instance + * + ******************************************************************************/ +void sl_button_disable(const sl_button_t *handle); + +/***************************************************************************//** + * Poll the button. + * + * @param[in] handle Pointer to button instance + ******************************************************************************/ +void sl_button_poll_step(const sl_button_t *handle); + +/***************************************************************************//** + * A callback called in interrupt context whenever a button changes its state. + * + * @remark Can be implemented by the application if required. This function + * can contain the functionality to be executed in response to changes of state + * in each of the buttons, or callbacks to appropriate functionality. + * + * @note The button state should not be updated in this function, it is updated + * by specific button driver prior to arriving here + * + @param[out] handle Pointer to button instance + ******************************************************************************/ +void sl_button_on_change(const sl_button_t *handle); + +/** @} (end addtogroup button) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup button Button API +/// @{ +/// +/// @details +/// +/// @n @section buttondrv_intro Introduction +/// +/// The button driver is a platfom level software module that manages the initialization +/// and reading of various types of buttons. There is currently one type of button +/// supported by the button driver: +/// +/// @li @ref simple_button +/// +/// All button functions are called through the generic driver, which then references +/// functions in the simple button and other potential future button drivers. +/// +/// @n @section buttondrv_config Configuration +/// +/// All button instances are configured with an @ref sl_button_t struct and a type specific +/// context struct. These structs are automatically generated after a button is set up +/// using Simplicity Studio's wizard, along with a function definition for initializing all +/// LEDs of that type. Specific setup for the simple button is in the following section. +/// +/// - [Simple Button Configuration](/gecko-platform//platform-driver/simple-button#simple-button-configuration) +/// +/// @n @section buttondrv_usage Usage +/// +/// Once the button structs are defined, the common button functions can be called being +/// passed an instance of sl_button_t, which will be redirected to calling the type specific +/// version of that function. The common functions include the following: +/// +/// @li @ref sl_button_init +/// @li @ref sl_button_get_state +/// @li @ref sl_button_poll_step +/// @li @ref sl_button_on_change +/// +/// @ref sl_button_init must be called before attempting to read the state of the button. +/// +/// The button driver can either be used with interrupt mode, polling or polling with debounce. +/// In the case of using interrupt mode, @ref sl_button_on_change can be implemented by the +/// application if required. This function can contain functionality to be executed in response +/// to button event or callbacks to appropriate functionality. +/// In the case of polling and polling with debounce mode, @ref sl_button_poll_step is used to +/// update the state, and needs to be called from a tick function or similar by the user. +/// These mode can be configured per button instance in the instance specific config file. +/// +/// Both the interrupt and polling methods obtain the button state for the user by calling +/// @ref sl_button_get_state. +/// +/// @} end group button ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif // SL_BUTTON_H diff --git a/Libs/platform/driver/button/inc/sl_simple_button.h b/Libs/platform/driver/button/inc/sl_simple_button.h new file mode 100644 index 0000000..09bdbfc --- /dev/null +++ b/Libs/platform/driver/button/inc/sl_simple_button.h @@ -0,0 +1,225 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_H +#define SL_SIMPLE_BUTTON_H + +#include "sl_button.h" +#include "sl_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup button + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup simple_button Simple Button Driver + * @details Simple Button Driver module provides APIs to initalize and read + * simple buttons. Subsequent sections provide more insight into button + * driver configuration and usage. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#define SL_SIMPLE_BUTTON_MODE_POLL 0U ///< BUTTON input capture using polling +#define SL_SIMPLE_BUTTON_MODE_POLL_AND_DEBOUNCE 1U ///< BUTTON input capture using polling and debouncing +#define SL_SIMPLE_BUTTON_MODE_INTERRUPT 2U ///< BUTTON input capture using interrupt + +#define SL_SIMPLE_BUTTON_DISABLED 2U ///< BUTTON state is disabled +#define SL_SIMPLE_BUTTON_PRESSED 1U ///< BUTTON state is pressed +#define SL_SIMPLE_BUTTON_RELEASED 0U ///< BUTTON state is released + +#define SL_SIMPLE_BUTTON_GET_STATE(context) (((sl_simple_button_context_t *)(context))->state) ///< BUTTON member function to get state +#define SL_SIMPLE_BUTTON_GET_PORT(context) (((sl_simple_button_context_t *)(context))->port) ///< BUTTON member function to get port +#define SL_SIMPLE_BUTTON_GET_PIN(context) (((sl_simple_button_context_t *)(context))->pin) ///< BUTTON member function to get pin +#define SL_SIMPLE_BUTTON_GET_MODE(context) (((sl_simple_button_context_t *)(context))->mode) ///< BUTTON member function to get mode + +/******************************************************************************* + ***************************** DATA TYPES ********************************* + ******************************************************************************/ + +/// A Simple BUTTON instance +typedef struct { + sl_button_state_t state; ///< Current button state + uint16_t history; ///< History of button states + sl_gpio_port_t port; ///< Button port + uint8_t pin; ///< Button pin + sl_button_mode_t mode; ///< Mode of operation +} sl_simple_button_context_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize the simple button driver. + * + * @param[in] handle Pointer to button handle: + * - sl_button_t + * + * @return Status Code: + * - SL_STATUS_OK + ******************************************************************************/ +sl_status_t sl_simple_button_init(const sl_button_t *handle); + +/***************************************************************************//** + * Get the current state of the simple button. + * + * @param[in] handle Pointer to button handle: + * - sl_button_t + * + * @return Button State: Current state of the button + * - SL_SIMPLE_BUTTON_PRESSED + * - SL_SIMPLE_BUTTON_RELEASED + ******************************************************************************/ +sl_button_state_t sl_simple_button_get_state(const sl_button_t *handle); + +/***************************************************************************//** + * Poll the simple button. (button mode - poll / poll and debonuce) + * + * @param[in] handle Pointer to button handle: + * - sl_button_t + ******************************************************************************/ +void sl_simple_button_poll_step(const sl_button_t *handle); + +/***************************************************************************//** + * Enable the simple button. + * + * @param[in] handle Pointer to button handle: + * - sl_button_t + ******************************************************************************/ +void sl_simple_button_enable(const sl_button_t *handle); + +/***************************************************************************//** + * Disable the simple button. + * + * @param[in] handle Pointer to button handle: + * - sl_button_t + ******************************************************************************/ +void sl_simple_button_disable(const sl_button_t *handle); + +/** @} (end addtogroup simple_button) */ +/** @} (end addtogroup button) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup simple_button Simple Button Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section simple_button_intro Introduction +/// +/// The Simple Button driver is a module of the button driver that provides the functionality +/// to initialize and read simple buttons. +/// +/// @n @section simple_button_config Simple Button Configuration +/// +/// Simple buttons use the @ref sl_button_t struct and their @ref sl_simple_button_context_t +/// struct. These are automatically generated into the following files, as well as +/// instance specific headers with macro definitions in them. The samples below +/// are for a single instance called "inst0". +/// +/// @code{.c} +///// sl_simple_button_instances.c +/// +///#include "sl_simple_button.h" +///#include "sl_simple_button_inst0_config.h" +/// +///sl_simple_button_context_t simple_inst0_context = { +/// .state = 0, +/// .history = 0, +/// .port = SL_SIMPLE_BUTTON_INST0_PORT, +/// .pin = SL_SIMPLE_BUTTON_INST0_PIN, +/// .mode = SL_SIMPLE_BUTTON_INST0_MODE, +///}; +/// +///const sl_button_t sl_button_inst0 = { +/// .context = &simple_inst0_context, +/// .init = sl_simple_button_init, +/// .get_state = sl_simple_button_get_state, +/// .poll = sl_simple_button_poll_step, +///}; +/// +///const sl_button_t *sl_simple_button_array[] = {&sl_button_inst0}; +///const uint8_t simple_button_count = 1; +/// +///void sl_simple_button_init_instances(void) +///{ +/// sl_button_init(&sl_button_inst0); +///} +/// +///void sl_simple_button_poll_instances(void) +///{ +/// sl_button_poll_step(&sl_button_inst0); +///} +/// @endcode +/// +/// @note The sl_simple_button_instances.c file is shown with only one instance, but if more +/// were in use they would all appear in this .c file. +/// +/// @code{.c} +///// sl_simple_button_instances.h +/// +///#ifndef SL_SIMPLE_BUTTON_INSTANCES_H +///#define SL_SIMPLE_BUTTON_INSTANCES_H +/// +///#include "sl_simple_button.h" +/// +///extern const sl_button_t sl_button_inst0; +/// +///void sl_simple_button_init_instances(void); +///void sl_simple_button_poll_instances(void); +/// +///#endif // SL_SIMPLE_BUTTON_INSTANCES_H +/// @endcode +/// +/// @note The sl_simple_button_instances.h file is shown with only one instance, but if more +/// were in use they would all appear in this .h file. +/// +/// @n @section simple_button_usage Simple Button Usage +/// +/// The simple button driver has no differences in its usage from the common button driver. +/// See @ref buttondrv_usage. +/// +/// @} end group simple_button ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif // SL_SIMPLE_BUTTON_H diff --git a/Libs/platform/driver/button/src/sl_button.c b/Libs/platform/driver/button/src/sl_button.c new file mode 100644 index 0000000..7eed692 --- /dev/null +++ b/Libs/platform/driver/button/src/sl_button.c @@ -0,0 +1,76 @@ +/***************************************************************************//** + * @file + * @brief Button Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_button.h" +#include + +sl_status_t sl_button_init(const sl_button_t *handle) +{ + if (handle->init != NULL) { + return handle->init(handle); + } else { + return SL_STATUS_NULL_POINTER; + } +} + +sl_button_state_t sl_button_get_state(const sl_button_t *handle) +{ + if (handle->get_state != NULL) { + return handle->get_state(handle); + } else { + return (sl_button_state_t)BUTTON_ERROR; + } +} + +void sl_button_poll_step(const sl_button_t *handle) +{ + if (handle->poll != NULL) { + handle->poll(handle); + } +} + +void sl_button_enable(const sl_button_t *handle) +{ + if (handle->enable != NULL) { + handle->enable(handle); + } +} + +void sl_button_disable(const sl_button_t *handle) +{ + if (handle->disable != NULL) { + handle->disable(handle); + } +} + +SL_WEAK void sl_button_on_change(const sl_button_t *handle) +{ + (void)handle; +} diff --git a/Libs/platform/driver/button/src/sl_simple_button.c b/Libs/platform/driver/button/src/sl_simple_button.c new file mode 100644 index 0000000..1f70720 --- /dev/null +++ b/Libs/platform/driver/button/src/sl_simple_button.c @@ -0,0 +1,205 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_simple_button.h" +#include "sl_simple_button_config.h" +#include "sl_clock_manager.h" + +#if (SL_SIMPLE_BUTTON_DEBOUNCE_BITS < 1U) +#undef SL_SIMPLE_BUTTON_DEBOUNCE_BITS +#define SL_SIMPLE_BUTTON_DEBOUNCE_BITS 1U +#endif +#if (SL_SIMPLE_BUTTON_DEBOUNCE_BITS > 15U) +#undef SL_SIMPLE_BUTTON_DEBOUNCE_BITS +#define SL_SIMPLE_BUTTON_DEBOUNCE_BITS 15U +#endif + +static const uint16_t check_press = (uint16_t)(0xffff << SL_SIMPLE_BUTTON_DEBOUNCE_BITS); +static const uint16_t check_release = (uint16_t)(~(0x1 << SL_SIMPLE_BUTTON_DEBOUNCE_BITS)); +static const uint16_t debounce_window = (uint16_t)(0xffff << (SL_SIMPLE_BUTTON_DEBOUNCE_BITS + 1)); + +/***************************************************************************//** + * An internal callback called in interrupt context whenever a button changes + * its state. (mode - SL_SIMPLE_BUTTON_MODE_INTERRUPT) + * + * @note The button state is updated by this function. The application callback + * should not update it again. + * + * @param[in] interrupt_no Interrupt number (pin number) + * @param[in] ctx Pointer to button handle + ******************************************************************************/ +static void sli_simple_button_on_change(uint8_t interrupt_no, void *ctx) +{ + (void)interrupt_no; + sl_button_t *button = (sl_button_t *)ctx; + sl_simple_button_context_t *simple_button = button->context; + sl_gpio_t gpio = { + .port = simple_button->port, + .pin = simple_button->pin + }; + bool pin_value; + + if (simple_button->state != SL_SIMPLE_BUTTON_DISABLED) { + sl_gpio_get_pin_input(&gpio, &pin_value); + simple_button->state = ((bool)pin_value == SL_SIMPLE_BUTTON_POLARITY); + + sl_button_on_change(button); + } +} + +sl_status_t sl_simple_button_init(const sl_button_t *handle) +{ + int32_t interrupt_em4, interrupt_ext; + sl_status_t status; + sl_button_t *button = (sl_button_t *)handle; + sl_simple_button_context_t *simple_button = button->context; + sl_gpio_t gpio = { + .port = simple_button->port, + .pin = simple_button->pin + }; + bool pin_value; + + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + + sl_gpio_set_pin_mode(&gpio, SL_SIMPLE_BUTTON_GPIO_MODE, SL_SIMPLE_BUTTON_GPIO_DOUT); + sl_gpio_get_pin_input(&gpio, &pin_value); + simple_button->state = ((bool)pin_value == SL_SIMPLE_BUTTON_POLARITY); + + if (simple_button->mode == SL_SIMPLE_BUTTON_MODE_INTERRUPT) { + interrupt_em4 = SL_GPIO_INTERRUPT_UNAVAILABLE; + interrupt_ext = SL_GPIO_INTERRUPT_UNAVAILABLE; + // Try to register an EM4WU interrupt for the given pin + status = sl_gpio_configure_wakeup_em4_interrupt(&gpio, + &interrupt_em4, + SL_SIMPLE_BUTTON_POLARITY, + (sl_gpio_irq_callback_t)sli_simple_button_on_change, + button); + if (interrupt_em4 == SL_GPIO_INTERRUPT_UNAVAILABLE) { + // if the pin not EM4WU-compatible, instead register a regualr interrupt + status = sl_gpio_configure_external_interrupt(&gpio, + &interrupt_ext, + SL_GPIO_INTERRUPT_RISING_FALLING_EDGE, + (sl_gpio_irq_callback_t)sli_simple_button_on_change, + button); + EFM_ASSERT(status == SL_STATUS_OK); + } else { + // If the pin is EM4WU-compatible, setup the pin as an EM4WU pin + // Since EM4WU interrupts are level-sensitive and not edge-sensitive, also register a regular edge-sensitive interrupt to capture the other edge + uint8_t flags; + if (SL_SIMPLE_BUTTON_POLARITY == 0) { + flags = SL_GPIO_INTERRUPT_RISING_EDGE; + } else if (SL_SIMPLE_BUTTON_POLARITY == 1) { + flags = SL_GPIO_INTERRUPT_FALLING_EDGE; + } + status = sl_gpio_configure_external_interrupt(&gpio, + &interrupt_ext, + flags, + (sl_gpio_irq_callback_t)sli_simple_button_on_change, + button); + EFM_ASSERT(status == SL_STATUS_OK); + } + } + + return SL_STATUS_OK; +} + +sl_button_state_t sl_simple_button_get_state(const sl_button_t *handle) +{ + sl_button_t *button = (sl_button_t *)handle; + sl_simple_button_context_t *simple_button = button->context; + + return simple_button->state; +} + +void sl_simple_button_poll_step(const sl_button_t *handle) +{ + sl_button_t *button = (sl_button_t *)handle; + sl_simple_button_context_t *simple_button = button->context; + bool button_press, pin_value; + sl_gpio_t gpio = { + .port = simple_button->port, + .pin = simple_button->pin + }; + + if (simple_button->state == SL_SIMPLE_BUTTON_DISABLED) { + return; + } + + sl_gpio_get_pin_input(&gpio, &pin_value); + button_press = (bool)pin_value; + + if (simple_button->mode == SL_SIMPLE_BUTTON_MODE_POLL_AND_DEBOUNCE) { + uint16_t history = simple_button->history; + history = (history << 1) | (button_press ^ SL_SIMPLE_BUTTON_POLARITY) | (debounce_window); + + if (history == check_press) { + simple_button->state = SL_SIMPLE_BUTTON_PRESSED; + } + if (history == check_release) { + simple_button->state = SL_SIMPLE_BUTTON_RELEASED; + } + + simple_button->history = history; + } else if (simple_button->mode == SL_SIMPLE_BUTTON_MODE_POLL) { + simple_button->state = (button_press == SL_SIMPLE_BUTTON_POLARITY); + } +} + +void sl_simple_button_enable(const sl_button_t *handle) +{ + sl_button_t *button = (sl_button_t *)handle; + sl_simple_button_context_t *simple_button = button->context; + + // Return if the button is not disabled + if (simple_button->state != SL_SIMPLE_BUTTON_DISABLED) { + return; + } + + // Clear history + simple_button->history = 0; + // Reinit button + sl_simple_button_init(handle); +} + +void sl_simple_button_disable(const sl_button_t *handle) +{ + sl_button_t *button = (sl_button_t *)handle; + sl_simple_button_context_t *simple_button = button->context; + + // Return if the button is disabled + if (simple_button->state == SL_SIMPLE_BUTTON_DISABLED) { + return; + } + if (simple_button->mode == SL_SIMPLE_BUTTON_MODE_INTERRUPT) { + sl_gpio_deconfigure_external_interrupt(simple_button->pin); + } + // Disable the button + simple_button->state = SL_SIMPLE_BUTTON_DISABLED; +} diff --git a/Libs/platform/driver/gpio/inc/sl_gpio.h b/Libs/platform/driver/gpio/inc/sl_gpio.h new file mode 100644 index 0000000..758a476 --- /dev/null +++ b/Libs/platform/driver/gpio/inc/sl_gpio.h @@ -0,0 +1,521 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) driver API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_GPIO_H +#define SL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_status.h" +#include "sl_device_gpio.h" + +#ifndef EM_GPIO_H +#define gpioPortA 0 +#define gpioPortB 1 +#define gpioPortC 2 +#define gpioPortD 3 +#define gpioPortE 4 +#define gpioPortF 5 +#define gpioPortG 6 +#define gpioPortH 7 +#define gpioPortI 8 +#define gpioPortJ 9 +#define gpioPortK 10 +#endif + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup gpio GPIO - General Purpose Input Output +/// @brief General Purpose Input Output driver +/// +/// @li @ref gpio_intro +/// +///@n @section gpio_intro Introduction +/// This module contains functions to control the GPIO peripheral of Silicon Labs 32-bit MCUs and SoCs. +/// The GPIO driver is used for external and EM4 interrupt configuration, port and pin configuration. +/// as well as manages the interrupt handler. +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// GPIO Pin directions. +SL_ENUM(sl_gpio_pin_direction_t) { + /// Input direction. + SL_GPIO_PIN_DIRECTION_IN = 0, + /// Output direction. + SL_GPIO_PIN_DIRECTION_OUT +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Structure for GPIO port and pin configuration. + ******************************************************************************/ +typedef struct { + sl_gpio_mode_t mode; + sl_gpio_pin_direction_t direction; +} sl_gpio_pin_config_t; + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * GPIO interrupt callback function pointer. + * + * @param int_no The pin interrupt number to which the callback function is invoked for. + * @param context Pointer to callback context. + ******************************************************************************/ +typedef void (*sl_gpio_irq_callback_t)(uint8_t int_no, void *context); + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialization of GPIO driver module. + * + * @return SL_STATUS_OK if initialization is successful. + ******************************************************************************/ +sl_status_t sl_gpio_init(void); + +/***************************************************************************//** + * Sets the pin direction of GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] pin_dir Pin direction of GPIO pin. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin, direction parameters are invalid. + * SL_STATUS_INVALID_STATE if GPIO configuration is in lock state. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_direction(const sl_gpio_t *gpio, + sl_gpio_pin_direction_t pin_dir); + +/***************************************************************************//** + * Set the pin mode and set/clear the pin for GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] mode The desired pin mode. + * @param[in] output_value Value to set/clear for pin output on the port. + * Determines the pull-up/pull-down direction of the pin for + * some input mode configurations. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin, mode parameters are invalid. + * SL_STATUS_INVALID_STATE if GPIO configuration is in locked state. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value); + +/***************************************************************************//** + * Gets the current configuration selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_config Pointer to pin configuration such as mode and direction. + * Pointer acts as an output and returns the configuration of + * selected pin on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_config is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_config(const sl_gpio_t *gpio, + sl_gpio_pin_config_t *pin_config); + +/***************************************************************************//** + * Sets the selected pin of the selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Clears the selected pin of the selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_clear_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Toggles the state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Gets the output state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_value Pointer to return output state of selected pin on selected port + * when configured to output mode. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_output(const sl_gpio_t *gpio, + bool *pin_value); + +/***************************************************************************//** + * Gets the input state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_value Pointer to return input state of selected pin on selected port + * when configured to input mode. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_input(const sl_gpio_t *gpio, + bool *pin_value); + +/***************************************************************************//** + * Sets the selected pin(s) of selected port. + * + * @param[in] port The GPIO port to access. + * @param[in] pins Bit mask for pins to set. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_port(sl_gpio_port_t port, + uint32_t pins); + +/***************************************************************************//** + * Clears the selected pin(s) of selected port. + * + * @param[in] port The GPIO Port to access. + * @param[in] pins Bit mask for bits to clear. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins); + +/***************************************************************************//** + * Gets the output state of pins of selected port. + * + * @param[in] gpio The GPIO Port to access. + * @param[out] port_value Pointer to return output state of pins on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if port_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_output(sl_gpio_port_t port, + uint32_t *port_value); + +/***************************************************************************//** + * Gets the input state of pins of selected port. + * + * @param[in] gpio The GPIO Port to access. + * @param[out] port_value Pointer to return output state of pins on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if port_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_input(sl_gpio_port_t port, + uint32_t *port_value); + +/***************************************************************************//** + * Configures the GPIO pin interrupt. + * + * @details By default, this function can be used to register a callback which shall be called upon + * interrupt generated for a given pin interrupt number and enables interrupt. + * This function configures and enables the external interrupt and performs + * callback registration. + * It is recommended to use sl_gpio_deconfigure_external_interrupt() + * to disable the interrupt and unregister the callback. + * see @ref sl_gpio_deconfigure_external_interrupt for more information. + * If a valid interrupt number is provided, operation will proceed accordingly. + * Otherwise, a valid interrupt number will be generated based on provided port and + * pin and used for subsequent operations. + * + * @note If the user has a valid interrupt number to provide as input, it can be used. + * If the user does not have an interrupt number, they can pass -1 (SL_GPIO_INTERRUPT_UNAVAILABLE) + * as value to variable int_no. + * The int_no parameter serves even as an output, a pointer to convey the interrupt number + * for cases where user lacks an interrupt number. + * @note the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (int_no / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in/out] int_no Pointer to interrupt number to trigger. + * Pointer that serves as both an input and an output to return int_no + * when the user lacks an int_no. + * @param[in] flags Interrupt flags for interrupt configuration. + * Determines the interrupt to get trigger based on rising/falling edge. + * @param[in] gpio_callback A pointer to gpio callback function. + * @param[in] context A pointer to the callback context. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin, flag parameters are invalid. + * SL_STATUS_NULL_POINTER if the int_no is passed as NULL. + * SL_STATUS_NOT_FOUND if there's no available interrupt number. + ******************************************************************************/ +sl_status_t sl_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t *int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + void *context); + +/***************************************************************************//** + * Deconfigures the GPIO external pin interrupt. + * + * @details This function can be used to deconfigure the external GPIO interrupt. + * This function performs callback unregistration, clears and disables the + * given interrupt. + * + * @note the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (int_no / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] int_no Interrupt number to unregister and disable. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if int_no is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_external_interrupt(int32_t int_no); + +/***************************************************************************//** + * Enables one or more GPIO Interrupts. + * + * @param[in] int_mask Mask for GPIO Interrupt sources to enable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_enable_interrupts(uint32_t int_mask); + +/***************************************************************************//** + * Disables one or more GPIO Interrupts. + * + * @param[in] int_mask Mask for GPIO Interrupt sources to disable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_disable_interrupts(uint32_t int_mask); + +/***************************************************************************//** + * Configuration EM4WU pins as external level-sensitive interrupts. + * + * @details By default, this function performs callback registration, enables GPIO pin wake-up from EM4, + * sets the wake-up polarity, enables GPIO pin retention and enables the EM4 wake-up interrupt. + * It is recommended to use sl_gpio_deconfigure_wakeup_em4_interrupt() + * to unregister the callback and disable the em4 interrupt as well as GPIO pin wake-up from EM4. + * It is recommended to use sl_gpio_set_pin_em4_retention() to enable/disable the GPIO pin retention. + * see @ref sl_gpio_deconfigure_wakeup_em4_interrupt() and @ref sl_gpio_set_pin_em4_retention(). + * If a valid EM4 wake-up interrupt number is provided, operation will proceed accordingly. + * Otherwise, a valid EM4 interrupt number will be generated based on provided EM4 configured + * port and pin and used for subsequent operations. + * + * @note If the user has a valid em4 interrupt number to provide as input, it can be used. + * If the user does not have an interrupt number, they can pass -1 (SL_GPIO_INTERRUPT_UNAVAILABLE) + * as value to variable em4_int_no. + * The em4_int_no parameter serves even as an output, a pointer to convey the em4 interrupt number + * for cases where user lacks an em4 interrupt number. + * @note There are specific ports and pins mapped to an existent EM4WU interrupt + * Each EM4WU signal is connected to a fixed pin and port. + * Based on chip, EM4 wake up interrupts configured port and pin might vary. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in/out] em4_int_no Pointer to interrupt number to trigger. + * Pointer that serves as both an input and an output to return em4_int_no + * when the user lacks an em4_int_no. + * @param[in] polarity Determines the wakeup polarity. + * true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * @param[in] gpio_callback A pointer to callback. + * @param[in] context A pointer to callback context. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if the int_no is passed as NULL. + * SL_STATUS_NOT_FOUND if there's no available interrupt number. + ******************************************************************************/ +sl_status_t sl_gpio_configure_wakeup_em4_interrupt(const sl_gpio_t *gpio, + int32_t *em4_int_no, + bool polarity, + sl_gpio_irq_callback_t gpio_callback, + void *context); + +/***************************************************************************//** + * Utilize this function to deconfigure the EM4 GPIO pin interrupt. + * It serves to unregister a callback, disable/clear interrupt and clear em4 wakeup source. + * + * @details This function performs callback unregistration, clears and disables given em4 + * interrupt and disables GPIO pin wake-up from EM4. + * + * @param[in] em4_int_no EM4 wakeup interrupt number. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if em4_int_no is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_wakeup_em4_interrupt(int32_t em4_int_no); + +/***************************************************************************//** + * Enable EM4 GPIO pin Wake-up bit. + * Sets the wakeup and polarity of the EM4 wakeup. + * + * @param[in] em4_int_mask Mask for setting desired EM4 wake up interrupt to enable. + * Mask contains the bitwise logic OR of which EM4 wake up interrupt to + * enable. + * @param[in] em4_polarity_mask Mask for setting the wake up polarity for the EM4 wake up interrupt. + * Mask contains the bitwise logic OR of EM4 wake-up interrupt polarity. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_enable_pin_em4_wakeup(uint32_t em4_int_mask, + uint32_t em4_polarity_mask); + +/***************************************************************************//** + * Disabled the GPIO wake up from EM4. + * + * @param[in] pinmask Mask for clearing desired EM4 wake up interrupt to disable. + * Mask contains the bitwise logic OR of which EM4 wake up interrupt to + * disable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_disable_pin_em4_wakeup(uint32_t em4_int_mask); + +/***************************************************************************//** + * Enable/Disable GPIO pin retention of output enable, output value, pull enable, and pull direction in EM4. + * + * @param[in] enable true - enables EM4 pin retention. + * false - disables EM4 pin retention. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_em4_retention(bool enable); + +/***************************************************************************//** + * Sets slewrate for selected port. + * + * @param[in] port The GPIO port to configure. + * @param[in] slewrate The slewrate to configure the GPIO port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate); + +/***************************************************************************//** + * Gets slewrate for selected port. + * + * @param[in] port The GPIO port to get slewrate. + * @param[out] slewrate Pointer to store the slewrate of selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if slewrate is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, + uint8_t *slewrate); + +/***************************************************************************//** + * Locks the GPIO Configuration. + * + * @note This API locks the functionalities such as sl_gpio_set_pin_mode(), + * sl_gpio_configure_external_interrupt() and sl_gpio_configure_wakeup_em4_interrupt(). + * After locking the GPIO configuration, use sl_gpio_unlock API to unlock + * the GPIO configuration to use mentioned functionalities. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_lock(void); + +/***************************************************************************//** + * Unlocks the GPIO Configuration. + * + * @note After locking the GPIO configuration it is recommended to unlock the GPIO configuration + * using sl_gpio_unlock(). You can determine if the GPIO configuration is locked or unlocked + * by using the sl_gpio_is_locked() function. + * Before using certain functions like sl_gpio_set_pin_mode(), + * sl_gpio_configure_external_interrupt(), and sl_gpio_configure_wakeup_em4_interrupt(), + * it's important to check if the GPIO configuration lock is unlocked. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_unlock(void); + +/***************************************************************************//** + * Gets current GPIO Lock status. + * + * @note This function helps check the current status of GPIO configuration. + * + * @param[out] state Pointer to current state of GPIO configuration (lock/unlock). + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_NULL_POINTER if state is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_is_locked(bool *state); + +/** @} (end addtogroup gpio driver) */ +#ifdef __cplusplus +} +#endif + +#endif /* SL_GPIO_H */ diff --git a/Libs/platform/driver/gpio/src/sl_gpio.c b/Libs/platform/driver/gpio/src/sl_gpio.c new file mode 100644 index 0000000..07e58ef --- /dev/null +++ b/Libs/platform/driver/gpio/src/sl_gpio.c @@ -0,0 +1,824 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) driver API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_core.h" +#include "sl_common.h" +#include "sl_interrupt_manager.h" +#include "sl_clock_manager.h" +#include "sl_hal_gpio.h" +#include "sl_gpio.h" + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/// Define for supporting gpiointerrupt porting +#define SL_GPIO_PORT_INTERRUPT (0xFF) + +/// Pin direction validation. +#define SL_GPIO_DIRECTION_IS_VALID(direction) (direction <= SL_GPIO_PIN_DIRECTION_OUT) + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +typedef struct { + // Pin interrupt number in range 0 to 15. + uint32_t int_no; + // Pointer to callback function. + void *callback; + // Pointer to callback context. + void *context; +} sl_gpio_callback_desc_t; + +typedef struct { + // An array of user callbacks for external interrupts. + // We have external interrupts configured from 0 to 15 bits. + sl_gpio_callback_desc_t callback_ext[SL_HAL_GPIO_INTERRUPT_MAX]; + // An array of user callbacks for EM4 interrupts. + // We have EM4 interrupts configured from 16 to 31 bits. + sl_gpio_callback_desc_t callback_em4[SL_HAL_GPIO_INTERRUPT_MAX]; +} sl_gpio_callbacks_t; + +/******************************************************************************* + ******************************** GLOBALS ********************************** + ******************************************************************************/ + +// Variable to manage and organize the callback functions for External and EM4 interrupts. +static sl_gpio_callbacks_t gpio_interrupts = { 0 }; + +/******************************************************************************* + ****************************** LOCAL FUCTIONS ***************************** + ******************************************************************************/ +static void sl_gpio_dispatch_interrupt(uint32_t iflags); + +/***************************************************************************//** + * Driver GPIO Initialization. + ******************************************************************************/ +sl_status_t sl_gpio_init() +{ + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + + if (sl_interrupt_manager_is_irq_disabled(GPIO_ODD_IRQn)) { + sl_interrupt_manager_clear_irq_pending(GPIO_ODD_IRQn); + sl_interrupt_manager_enable_irq(GPIO_ODD_IRQn); + } + if (sl_interrupt_manager_is_irq_disabled(GPIO_EVEN_IRQn)) { + sl_interrupt_manager_clear_irq_pending(GPIO_EVEN_IRQn); + sl_interrupt_manager_enable_irq(GPIO_EVEN_IRQn); + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the pin direction for GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_direction(const sl_gpio_t *gpio, + sl_gpio_pin_direction_t pin_direction) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) || !SL_GPIO_DIRECTION_IS_VALID(pin_direction)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (sl_hal_gpio_get_lock_status() != 0) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_STATE; + } + + CORE_ENTER_ATOMIC(); + + if (pin_direction == SL_GPIO_PIN_DIRECTION_OUT) { + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_PUSH_PULL, 1); + } else if (pin_direction == SL_GPIO_PIN_DIRECTION_IN) { + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_INPUT, 0); + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the mode for GPIO pin and pin direction. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_MODE_IS_VALID(mode) || !SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (sl_hal_gpio_get_lock_status() != 0) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_STATE; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin_mode(gpio, mode, output_value); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the current configuration selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_config(const sl_gpio_t *gpio, + sl_gpio_pin_config_t *pin_config) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_config == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + pin_config->mode = sl_hal_gpio_get_pin_mode(gpio); + switch (pin_config->mode) { + case SL_GPIO_MODE_INPUT: + case SL_GPIO_MODE_INPUT_PULL: + case SL_GPIO_MODE_INPUT_PULL_FILTER: + pin_config->direction = SL_GPIO_PIN_DIRECTION_IN; + break; + + case SL_GPIO_MODE_DISABLED: + case SL_GPIO_MODE_PUSH_PULL: + case SL_GPIO_MODE_PUSH_PULL_ALTERNATE: + case SL_GPIO_MODE_WIRED_OR: + case SL_GPIO_MODE_WIRED_OR_PULL_DOWN: + case SL_GPIO_MODE_WIRED_AND: + case SL_GPIO_MODE_WIRED_AND_FILTER: + case SL_GPIO_MODE_WIRED_AND_PULLUP: + case SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER: + pin_config->direction = SL_GPIO_PIN_DIRECTION_OUT; + break; + + default: + CORE_EXIT_ATOMIC(); + EFM_ASSERT(false); + return SL_STATUS_INVALID_MODE; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_clear_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_clear_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Toggles the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_toggle_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the output state of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_output(const sl_gpio_t *gpio, + bool *pin_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *pin_value = sl_hal_gpio_get_pin_output(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the input state of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_input(const sl_gpio_t *gpio, + bool *pin_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *pin_value = sl_hal_gpio_get_pin_input(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the selected pin(s) on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_port(sl_gpio_port_t port, + uint32_t pins) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_port(port, pins); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears the selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_clear_port(port, pins); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the output state of pins of selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_output(sl_gpio_port_t port, + uint32_t *port_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (port_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *port_value = sl_hal_gpio_get_port_output(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the input state of pins of selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_input(sl_gpio_port_t port, + uint32_t *port_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (port_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *port_value = sl_hal_gpio_get_port_input(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configuring the GPIO external pin interrupt. + * This API can be used to configure interrupt and to register the callback. + ******************************************************************************/ +sl_status_t sl_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t *int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + void *context) +{ + uint32_t enabled_interrupts; + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || int_no == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) && (gpio->port != SL_GPIO_PORT_INTERRUPT)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (!SL_GPIO_FLAG_IS_VALID(flags)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + *int_no = sl_hal_gpio_configure_external_interrupt(gpio, *int_no, flags); + } + + if (*int_no == SL_GPIO_INTERRUPT_UNAVAILABLE && gpio->port == SL_GPIO_PORT_INTERRUPT) { + enabled_interrupts = sl_hal_gpio_get_enabled_interrupts(); + *int_no = sl_hal_gpio_get_external_interrupt_number(gpio->pin, enabled_interrupts); + } + + if (*int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + // Callback registration. + gpio_interrupts.callback_ext[*int_no].callback = (void *)gpio_callback; + gpio_interrupts.callback_ext[*int_no].context = context; + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + sl_hal_gpio_enable_interrupts(1 << *int_no); + } + } else { + CORE_EXIT_ATOMIC(); + return SL_STATUS_NOT_FOUND; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deconfigures the GPIO external pin interrupt. + * This API can be used to deconfigure the interrupt and to unregister the callback. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_external_interrupt(int32_t int_no) +{ + CORE_DECLARE_IRQ_STATE; + + if (!((int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) && (int_no <= SL_HAL_GPIO_INTERRUPT_MAX) && (int_no >= 0))) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + // Clear pending interrupt. + sl_hal_gpio_clear_interrupts(1 << int_no); + sl_hal_gpio_disable_interrupts(1 << int_no); + + // Callback deregistration. + gpio_interrupts.callback_ext[int_no].callback = NULL; + gpio_interrupts.callback_ext[int_no].context = NULL; + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Enables one or more GPIO interrupts. + ******************************************************************************/ +sl_status_t sl_gpio_enable_interrupts(uint32_t flags) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_enable_interrupts(flags); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Disables one or more GPIO interrupts. + ******************************************************************************/ +sl_status_t sl_gpio_disable_interrupts(uint32_t flags) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_disable_interrupts(flags); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configures the EM4WU pin as external level interrupts for waking up from EM mode. + * Registering/unregistering the callbacks and Configuring the EM4 interrupts to enable/disable + ******************************************************************************/ +sl_status_t sl_gpio_configure_wakeup_em4_interrupt(const sl_gpio_t *gpio, + int32_t *em4_int_no, + bool polarity, + sl_gpio_irq_callback_t gpio_callback, + void *context) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || em4_int_no == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) && (gpio->port != SL_GPIO_PORT_INTERRUPT)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + *em4_int_no = sl_hal_gpio_configure_wakeup_em4_external_interrupt(gpio, *em4_int_no, polarity); + } + + if (*em4_int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + // Callback registration. + gpio_interrupts.callback_em4[*em4_int_no].callback = (void *)gpio_callback; + gpio_interrupts.callback_em4[*em4_int_no].context = context; + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + sl_hal_gpio_enable_interrupts(1 << (*em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + } + } else { + CORE_EXIT_ATOMIC(); + return SL_STATUS_NOT_FOUND; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deconfigures the EM4 GPIO pin interrupt. + * Unregisters a callback, disable/clear interrupt and clear em4 wakeup source + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_wakeup_em4_interrupt(int32_t em4_int_no) +{ + CORE_DECLARE_IRQ_STATE; + + if (!((em4_int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) && (em4_int_no <= SL_HAL_GPIO_INTERRUPT_MAX) && (em4_int_no >= 0))) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + // Clear any pending interrupt. + sl_hal_gpio_clear_interrupts(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + sl_hal_gpio_disable_pin_em4_wakeup(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + sl_hal_gpio_disable_interrupts(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + + /* Callback deregistration */ + gpio_interrupts.callback_em4[em4_int_no].callback = NULL; + gpio_interrupts.callback_em4[em4_int_no].context = NULL; + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets GPIO EM4 Wake up interrupt to Enable and EM4 Wake up interrupt polarity + ******************************************************************************/ +sl_status_t sl_gpio_enable_pin_em4_wakeup(uint32_t em4_int_mask, + uint32_t em4_polarity_mask) +{ + uint32_t int_mask = 0; + uint32_t polarity_mask = 0; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Enable EM4WU function and set polarity. + int_mask |= (em4_int_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + polarity_mask |= (em4_polarity_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + sl_hal_gpio_enable_pin_em4_wakeup(int_mask, polarity_mask); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears GPIO EM4 Wake up enable + ******************************************************************************/ +sl_status_t sl_gpio_disable_pin_em4_wakeup(uint32_t em4_int_mask) +{ + uint32_t int_mask = 0; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Disable EM4WU function. + int_mask |= (em4_int_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + sl_hal_gpio_disable_pin_em4_wakeup(int_mask); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Enable GPIO pin retention of output enable, output value, pull direction, pull enable in EM4 + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_em4_retention(bool enable) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin_em4_retention(enable); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets slewrate for selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_slew_rate(port, slewrate); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets slewrate for selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, + uint8_t *slewrate) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (slewrate == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *slewrate = sl_hal_gpio_get_slew_rate(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Locks the GPIO Configuration + ******************************************************************************/ +sl_status_t sl_gpio_lock(void) +{ + sl_hal_gpio_lock(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Unlocks the GPIO Configuration + ******************************************************************************/ +sl_status_t sl_gpio_unlock(void) +{ + sl_hal_gpio_unlock(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the GPIO State + ******************************************************************************/ +sl_status_t sl_gpio_is_locked(bool *state) +{ + uint32_t status; + CORE_DECLARE_IRQ_STATE; + + if (state == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + status = sl_hal_gpio_get_lock_status(); + if (status) { + // true - GPIO configuration registers are locked. + *state = true; + } else { + // false - GPIO configuration registers are unlocked. + *state = false; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Function calls users callback for registered pin interrupts. + * + * @details This function is called when GPIO interrupts are handled by the IRQHandlers. + * Function gets even or odd interrupt flags and calls user callback + * registered for that pin. Function iterates on flags starting from MSB. + * + * @param iflags Interrupt flags which shall be handled by the dispatcher. + ******************************************************************************/ +static void sl_gpio_dispatch_interrupt(uint32_t iflags) +{ + uint32_t irq_idx; + sl_gpio_callback_desc_t *callback; + sl_gpio_irq_callback_t func; + + // Check for flags set in IF register. + while (iflags != 0) { + irq_idx = SL_CTZ(iflags); + iflags &= ~(1UL << irq_idx); + + if (irq_idx <= SL_HAL_GPIO_INTERRUPT_MAX) { + callback = &gpio_interrupts.callback_ext[irq_idx]; + } else { + callback = &gpio_interrupts.callback_em4[irq_idx - SL_HAL_GPIO_EM4WUEN_SHIFT]; + irq_idx = irq_idx - SL_HAL_GPIO_EM4WUEN_SHIFT; + } + // Call user callback. + if (callback->callback) { + func = (sl_gpio_irq_callback_t)(callback->callback); + func((uint8_t)irq_idx, callback->context); + } + } +} + +/***************************************************************************//** + * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and + * call the dispatcher passing the flags which triggered the interrupt. + ******************************************************************************/ +void GPIO_EVEN_IRQHandler(void) +{ + uint32_t even_flags; + + // Gets all enabled and pending even interrupts. + even_flags = sl_hal_gpio_get_enabled_pending_interrupts() & SL_HAL_GPIO_INT_IF_EVEN_MASK; + // Clears only even interrupts. + sl_hal_gpio_clear_interrupts(even_flags); + + sl_gpio_dispatch_interrupt(even_flags); +} + +/***************************************************************************//** + * @brief + * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and + * call the dispatcher passing the flags which triggered the interrupt. + ******************************************************************************/ +void GPIO_ODD_IRQHandler(void) +{ + uint32_t odd_flags; + + // Gets all enabled and pending odd interrupts. + odd_flags = sl_hal_gpio_get_enabled_pending_interrupts() & SL_HAL_GPIO_INT_IF_ODD_MASK; + // Clears only odd interrupts. + sl_hal_gpio_clear_interrupts(odd_flags); + + sl_gpio_dispatch_interrupt(odd_flags); +} diff --git a/Libs/platform/driver/leddrv/inc/sl_led.h b/Libs/platform/driver/leddrv/inc/sl_led.h new file mode 100644 index 0000000..7491bb0 --- /dev/null +++ b/Libs/platform/driver/leddrv/inc/sl_led.h @@ -0,0 +1,183 @@ +/***************************************************************************//** + * @file + * @brief LED Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_LED_H +#define SL_LED_H + +#include +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup led LED Driver + * @brief Generic LED Driver + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#define SL_LED_CURRENT_STATE_OFF 0U ///< LED state off +#define SL_LED_CURRENT_STATE_ON 1U ///< LED state on + +/******************************************************************************* + ***************************** DATA TYPES ********************************** + ******************************************************************************/ + +typedef uint8_t sl_led_state_t; ///< LED state + +/// A LED instance +typedef struct { + void *context; ///< The context for this LED instance + sl_status_t (*init)(void *context); ///< Member function to initialize LED instance + void (*turn_on)(void *context); ///< Member function to turn on LED + void (*turn_off)(void *context); ///< Member function to turn off LED + void (*toggle)(void *context); ///< Member function to toggle LED + sl_led_state_t (*get_state)(void *context); ///< Member function to retrieve LED state +} sl_led_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize the LED driver. Call this function before any other LED + * function. Initializes the selected LED GPIO, mode, and polarity. + * + * @param[in] led_handle Pointer to instance of sl_led_t to initialize + * + * @return Status Code: + * - SL_STATUS_OK + ******************************************************************************/ +sl_status_t sl_led_init(const sl_led_t *led_handle); + +/***************************************************************************//** + * Turn on the LED. + * + * @param[in] led_handle Pointer to instance of sl_led_t to turn on + ******************************************************************************/ +void sl_led_turn_on(const sl_led_t *led_handle); + +/***************************************************************************//** + * Turn off the LED. + * + * @param[in] led_handle Pointer to instance of sl_led_t to turn off + ******************************************************************************/ +void sl_led_turn_off(const sl_led_t *led_handle); + +/***************************************************************************//** + * Toggle the LED. Turn it on if it is off, and off if it is on. + * + * @param[in] led_handle Pointer to instance of sl_led_t to toggle + ******************************************************************************/ +void sl_led_toggle(const sl_led_t *led_handle); + +/***************************************************************************//** + * Get the current state of the LED. + * + * @param[in] led_handle Pointer to instance of sl_led_t to check + * + * @return sl_led_state_t Current state of LED. 1 for on, 0 for off + ******************************************************************************/ +sl_led_state_t sl_led_get_state(const sl_led_t *led_handle); + +/** @} (end group led) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup led LED Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section leddrv_intro Introduction +/// +/// The LED driver is a platfom level software module that manages the control of +/// various types of LEDs. There are currently two types of LEDs supported by the +/// LED driver: +/// +/// @li @ref simple_led +/// @li @ref simple_rgbw_pwm_led +/// +/// The common LED functions are called through the generic LED driver, while other +/// functions specific to a certain type of LED are called directly through their own +/// driver. +/// +/// @n @section leddrv_config Configuration +/// +/// All LED instances are configured using an @ref sl_led_t struct along with a +/// type-specific context struct, and sometimes additional structs. For `sl_led_XXX` +/// functions, the `sl_led_t *led_handle` is used, while for `sl_simple_led_XXX` +/// functions, the `sl_simple_led_context_t *context` is used. +/// +/// These structs are automatically generated when an LED is set up using Simplicity +/// Studio's wizard. Specific configuration setups for the various LED types are +/// described in the following sections. +/// +/// - [Simple LED Configuration](/gecko-platform//platform-driver/simple-led#simple-led-configuration) +/// - [RGBW PWM LED Configuration](/gecko-platform//platform-driver/simple-rgb-pwm-led#rgb-pwm-led-configuration) +/// +/// @n @section leddrv_usage Usage +/// +/// Once the LED structs are defined, the common LED functions can be called being passed an instance +/// of sl_led_t, which will be redirected to calling the type specific version of that function. The +/// common functions include the following: +/// +/// @li @ref sl_led_init +/// @li @ref sl_led_turn_on +/// @li @ref sl_led_turn_off +/// @li @ref sl_led_toggle +/// @li @ref sl_led_get_state +/// +/// These functions allow for initializing the LED, turning it on and off, toggling it, and retrieving +/// its current state (on/off). Other functions specific to certain types of LEDs are called through +/// their respective APIs. The usages of the different types of LEDs are described in detail in the +/// following sections: +/// +/// @li @ref simple_led_usage +/// @li @ref rgbw_led_usage +/// +/// Ensure that the appropriate context type is used in the function calls: +/// - Use `sl_led_t *led_handle` for `sl_led_XXX` functions. +/// - Use `sl_simple_led_context_t *context` for `sl_simple_led_XXX` functions. +/// +/// These distinctions are handled by the Simplicity Studio auto-generated code. +/// +/// @} end group led ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif // SL_LED_H diff --git a/Libs/platform/driver/leddrv/inc/sl_simple_led.h b/Libs/platform/driver/leddrv/inc/sl_simple_led.h new file mode 100644 index 0000000..6e470b7 --- /dev/null +++ b/Libs/platform/driver/leddrv/inc/sl_simple_led.h @@ -0,0 +1,226 @@ +/***************************************************************************//** + * @file + * @brief Simple LED Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_H +#define SL_SIMPLE_LED_H + +#include "sl_led.h" +#include "sl_gpio.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup led + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup simple_led Simple LED Driver + * @brief Simple LED Driver can be used to execute basic LED functionalities + * such as on, off, toggle, or retrive the on/off status on Silicon Labs + * devices. Subsequent sections provide more insight into this module. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#define SL_SIMPLE_LED_POLARITY_ACTIVE_LOW 0U ///< LED Active polarity Low +#define SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH 1U ///< LED Active polarity High + +/******************************************************************************* + ***************************** DATA TYPES ********************************** + ******************************************************************************/ + +typedef uint8_t sl_led_polarity_t; ///< LED GPIO polarities (active high/low) + +/// A Simple LED instance +typedef struct { + sl_gpio_port_t port; ///< LED port + uint8_t pin; ///< LED pin + sl_led_polarity_t polarity; ///< Initial state of LED +} sl_simple_led_context_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize the simple LED driver. + * + * @param[in] led_handle Pointer to simple-led specific data: + * - sl_simple_led_context_t + * + * @return Status Code: + * - SL_STATUS_OK + ******************************************************************************/ +sl_status_t sl_simple_led_init(void *led_handle); + +/***************************************************************************//** + * Turn on a simple LED. + * + * @param[in] led_handle Pointer to simple-led specific data: + * - sl_simple_led_context_t + * + ******************************************************************************/ +void sl_simple_led_turn_on(void *led_handle); + +/***************************************************************************//** + * Turn off a simple LED. + * + * @param[in] led_handle Pointer to simple-led specific data: + * - sl_simple_led_context_t + * + ******************************************************************************/ +void sl_simple_led_turn_off(void *led_handle); + +/***************************************************************************//** + * Toggle a simple LED. + * + * @param[in] led_handle Pointer to simple-led specific data: + * - sl_simple_led_context_t + * + ******************************************************************************/ +void sl_simple_led_toggle(void *led_handle); + +/***************************************************************************//** + * Get the current state of the simple LED. + * + * @param[in] led_handle Pointer to simple-led specific data: + * - sl_simple_led_context_t + * + * @return sl_led_state_t Current state of simple LED. 1 for on, 0 for off + ******************************************************************************/ +sl_led_state_t sl_simple_led_get_state(void *led_handle); + +/** @} (end group simple_led) */ +/** @} (end group led) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup simple_led Simple LED Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section simple_led_intro Introduction +/// +/// The Simple LED driver is a module of the LED driver that provides the functionality +/// to control simple on/off LEDs. +/// +/// @n @section simple_led_config Simple LED Configuration +/// +/// Simple LEDs use the @ref sl_led_t struct and their @ref sl_simple_led_context_t +/// struct. These are automatically generated into the following files, as well as +/// instance specific headers with macro definitions in them. The samples below +/// are for a single instance called "inst0". +/// +/// @code{.c} +///// sl_simple_led_instances.c +/// +///#include "sl_simple_led.h" +///#include "sl_gpio.h" +///#include "sl_simple_led_inst0_config.h" +/// +///sl_simple_led_context_t simple_inst0_context = { +/// .port = SL_SIMPLE_LED_INST0_PORT, +/// .pin = SL_SIMPLE_LED_INST0_PIN, +/// .polarity = SL_SIMPLE_LED_INST0_POLARITY, +///}; +/// +///const sl_led_t sl_led_inst0 = { +/// .context = &simple_inst0_context, +/// .init = sl_simple_led_init, +/// .turn_on = sl_simple_led_turn_on, +/// .turn_off = sl_simple_led_turn_off, +/// .toggle = sl_simple_led_toggle, +/// .get_state = sl_simple_led_get_state, +///}; +/// +///void sl_simple_led_init_instances(void) +///{ +/// sl_led_init(&sl_led_inst0); +///} +/// @endcode +/// +/// @note The sl_simple_led_instances.c file is shown with only one instance, but if more +/// were in use they would all appear in this .c file. +/// +/// @code{.c} +///// sl_simple_led_instances.h +/// +///#ifndef SL_SIMPLE_LED_INSTANCES_H +///#define SL_SIMPLE_LED_INSTANCES_H +/// +///#include "sl_simple_led.h" +/// +///extern const sl_led_t sl_led_inst0; +/// +///void sl_simple_led_init_instances(void); +/// +///#endif // SL_SIMPLE_LED_INIT_H +/// @endcode +/// +/// @note The sl_simple_led_instances.h file is shown with only one instance, but if more +/// were in use they would all appear in this .h file. +/// +/// @n @section simple_led_usage Simple LED Usage +/// +/// The simple LED driver is for LEDs with basic on off functionality, and there +/// are no additional functions beyond those in the common driver. The LEDs can be +/// turned on and off, toggled, and their on/off state can be retrieved. The following +/// code shows how to control these LEDs. An LED should always be initialized before +/// calling any other functions with it. +/// +/// @code{.c} +///// initialize simple LED +///sl_simple_led_init(&simple_led_inst0); +/// +///// turn on simple LED, turn off simple LED, and toggle the simple LED +///sl_simple_led_turn_on(&simple_led_inst0); +///sl_simple_led_turn_off(&simple_led_inst0); +///sl_simple_led_toggle(&simple_led_inst0); +/// +///// get the state of the simple LED +///sl_led_state_t state = sl_simple_led_get_state(&simple_led_instance0); +/// @endcode +/// +/// @} end group simple_led ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif // SL_SIMPLE_LED_H diff --git a/Libs/platform/driver/leddrv/src/sl_led.c b/Libs/platform/driver/leddrv/src/sl_led.c new file mode 100644 index 0000000..104b934 --- /dev/null +++ b/Libs/platform/driver/leddrv/src/sl_led.c @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file + * @brief LED Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_led.h" + +sl_status_t sl_led_init(const sl_led_t *led_handle) +{ + return led_handle->init(led_handle->context); +} + +void sl_led_turn_on(const sl_led_t *led_handle) +{ + led_handle->turn_on(led_handle->context); +} + +void sl_led_turn_off(const sl_led_t *led_handle) +{ + led_handle->turn_off(led_handle->context); +} + +void sl_led_toggle(const sl_led_t *led_handle) +{ + led_handle->toggle(led_handle->context); +} + +sl_led_state_t sl_led_get_state(const sl_led_t *led_handle) +{ + return led_handle->get_state(led_handle->context); +} diff --git a/Libs/platform/driver/leddrv/src/sl_simple_led.c b/Libs/platform/driver/leddrv/src/sl_simple_led.c new file mode 100644 index 0000000..a7daf44 --- /dev/null +++ b/Libs/platform/driver/leddrv/src/sl_simple_led.c @@ -0,0 +1,104 @@ +/***************************************************************************//** + * @file + * @brief Simple LED Driver + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_simple_led.h" +#include "sl_gpio.h" +#include "sl_clock_manager.h" + +sl_status_t sl_simple_led_init(void *context) +{ + sl_simple_led_context_t *led = context; + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + + sl_gpio_t gpio; + gpio.port = led->port; + gpio.pin = led->pin; + sl_gpio_set_pin_mode(&gpio, + SL_GPIO_MODE_PUSH_PULL, + !led->polarity); + return SL_STATUS_OK; +} + +void sl_simple_led_turn_on(void *context) +{ + sl_simple_led_context_t *led = context; + + sl_gpio_t gpio; + gpio.port = led->port; + gpio.pin = led->pin; + if (led->polarity == SL_SIMPLE_LED_POLARITY_ACTIVE_LOW) { + sl_gpio_clear_pin(&gpio); + } else { + sl_gpio_set_pin(&gpio); + } +} + +void sl_simple_led_turn_off(void *context) +{ + sl_simple_led_context_t *led = context; + + sl_gpio_t gpio; + gpio.port = led->port; + gpio.pin = led->pin; + if (led->polarity == SL_SIMPLE_LED_POLARITY_ACTIVE_LOW) { + sl_gpio_set_pin(&gpio); + } else { + sl_gpio_clear_pin(&gpio); + } +} + +void sl_simple_led_toggle(void *context) +{ + sl_simple_led_context_t *led = context; + + sl_gpio_t gpio; + gpio.port = led->port; + gpio.pin = led->pin; + sl_gpio_toggle_pin(&gpio); +} + +sl_led_state_t sl_simple_led_get_state(void *context) +{ + sl_simple_led_context_t *led = context; + sl_led_state_t value; + + sl_gpio_t gpio; + bool pin_value; + gpio.port = led->port; + gpio.pin = led->pin; + sl_gpio_get_pin_output(&gpio, &pin_value); + value = (sl_led_state_t)pin_value; + + if (led->polarity == SL_SIMPLE_LED_POLARITY_ACTIVE_LOW) { + return !value; + } else { + return value; + } +} diff --git a/Libs/platform/emlib/inc/em_acmp.h b/Libs/platform/emlib/inc/em_acmp.h new file mode 100644 index 0000000..33e5cc4 --- /dev/null +++ b/Libs/platform/emlib/inc/em_acmp.h @@ -0,0 +1,1168 @@ +/***************************************************************************//** + * @file + * @brief Analog Comparator (ACMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_ACMP_H +#define EM_ACMP_H + +#include "em_device.h" +#include "em_gpio.h" + +#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup acmp + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Resistor values used for the internal capacitive sense resistor. See + * data sheet for your device for details on each resistor value. */ +typedef enum { +#if defined(_ACMP_INPUTCTRL_CSRESSEL_MASK) + acmpResistor0 = _ACMP_INPUTCTRL_CSRESSEL_RES0, /**< Resistor value 0 */ + acmpResistor1 = _ACMP_INPUTCTRL_CSRESSEL_RES1, /**< Resistor value 1 */ + acmpResistor2 = _ACMP_INPUTCTRL_CSRESSEL_RES2, /**< Resistor value 2 */ + acmpResistor3 = _ACMP_INPUTCTRL_CSRESSEL_RES3, /**< Resistor value 3 */ + acmpResistor4 = _ACMP_INPUTCTRL_CSRESSEL_RES4, /**< Resistor value 4 */ + acmpResistor5 = _ACMP_INPUTCTRL_CSRESSEL_RES5, /**< Resistor value 5 */ + acmpResistor6 = _ACMP_INPUTCTRL_CSRESSEL_RES6, /**< Resistor value 6 */ +#else + acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */ + acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */ + acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */ + acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3, /**< Resistor value 3 */ +#if defined(_ACMP_INPUTSEL_CSRESSEL_RES4) + acmpResistor4 = _ACMP_INPUTSEL_CSRESSEL_RES4, /**< Resistor value 4 */ + acmpResistor5 = _ACMP_INPUTSEL_CSRESSEL_RES5, /**< Resistor value 5 */ + acmpResistor6 = _ACMP_INPUTSEL_CSRESSEL_RES6, /**< Resistor value 6 */ + acmpResistor7 = _ACMP_INPUTSEL_CSRESSEL_RES7, /**< Resistor value 7 */ +#endif +#endif +} ACMP_CapsenseResistor_TypeDef; + +/** Hysteresis level. See data sheet for your device for details on each + * level. */ +typedef enum { +#if defined(_ACMP_CTRL_HYSTSEL_MASK) + acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */ + acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */ + acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */ + acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */ + acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */ + acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */ + acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */ + acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */ +#endif +#if defined(_ACMP_HYSTERESIS0_HYST_MASK) + acmpHysteresisLevel0 = _ACMP_HYSTERESIS0_HYST_HYST0, /**< Hysteresis level 0 */ + acmpHysteresisLevel1 = _ACMP_HYSTERESIS0_HYST_HYST1, /**< Hysteresis level 1 */ + acmpHysteresisLevel2 = _ACMP_HYSTERESIS0_HYST_HYST2, /**< Hysteresis level 2 */ + acmpHysteresisLevel3 = _ACMP_HYSTERESIS0_HYST_HYST3, /**< Hysteresis level 3 */ + acmpHysteresisLevel4 = _ACMP_HYSTERESIS0_HYST_HYST4, /**< Hysteresis level 4 */ + acmpHysteresisLevel5 = _ACMP_HYSTERESIS0_HYST_HYST5, /**< Hysteresis level 5 */ + acmpHysteresisLevel6 = _ACMP_HYSTERESIS0_HYST_HYST6, /**< Hysteresis level 6 */ + acmpHysteresisLevel7 = _ACMP_HYSTERESIS0_HYST_HYST7, /**< Hysteresis level 7 */ + acmpHysteresisLevel8 = _ACMP_HYSTERESIS0_HYST_HYST8, /**< Hysteresis level 8 */ + acmpHysteresisLevel9 = _ACMP_HYSTERESIS0_HYST_HYST9, /**< Hysteresis level 9 */ + acmpHysteresisLevel10 = _ACMP_HYSTERESIS0_HYST_HYST10, /**< Hysteresis level 10 */ + acmpHysteresisLevel11 = _ACMP_HYSTERESIS0_HYST_HYST11, /**< Hysteresis level 11 */ + acmpHysteresisLevel12 = _ACMP_HYSTERESIS0_HYST_HYST12, /**< Hysteresis level 12 */ + acmpHysteresisLevel13 = _ACMP_HYSTERESIS0_HYST_HYST13, /**< Hysteresis level 13 */ + acmpHysteresisLevel14 = _ACMP_HYSTERESIS0_HYST_HYST14, /**< Hysteresis level 14 */ + acmpHysteresisLevel15 = _ACMP_HYSTERESIS0_HYST_HYST15, /**< Hysteresis level 15 */ +#endif +#if defined(_ACMP_CFG_HYST_MASK) + acmpHysteresisDisabled = _ACMP_CFG_HYST_DISABLED, /**< Mode DISABLED for ACMP_CFG */ + acmpHysteresis10Sym = _ACMP_CFG_HYST_SYM10MV, /**< Mode HYST10SYM for ACMP_CFG */ + acmpHysteresis20Sym = _ACMP_CFG_HYST_SYM20MV, /**< Mode HYST20SYM for ACMP_CFG */ + acmpHysteresis30Sym = _ACMP_CFG_HYST_SYM30MV, /**< Mode HYST30SYM for ACMP_CFG */ + acmpHysteresis10Pos = _ACMP_CFG_HYST_POS10MV, /**< Mode HYST10POS for ACMP_CFG */ + acmpHysteresis20Pos = _ACMP_CFG_HYST_POS20MV, /**< Mode HYST20POS for ACMP_CFG */ + acmpHysteresis30Pos = _ACMP_CFG_HYST_POS30MV, /**< Mode HYST30POS for ACMP_CFG */ + acmpHysteresis10Neg = _ACMP_CFG_HYST_NEG10MV, /**< Mode HYST10NEG for ACMP_CFG */ + acmpHysteresis20Neg = _ACMP_CFG_HYST_NEG20MV, /**< Mode HYST20NEG for ACMP_CFG */ + acmpHysteresis30Neg = _ACMP_CFG_HYST_NEG30MV, /**< Mode HYST30NEG for ACMP_CFG */ +#endif +} ACMP_HysteresisLevel_TypeDef; + +#if defined(_ACMP_CTRL_WARMTIME_MASK) +/** ACMP warmup time. The delay is measured in HFPERCLK / HFPERCCLK cycles and should + * be at least 10 us. */ +typedef enum { + /** 4 cycles warmup */ + acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES, + /** 8 cycles warmup */ + acmpWarmTime8 = _ACMP_CTRL_WARMTIME_8CYCLES, + /** 16 cycles warmup */ + acmpWarmTime16 = _ACMP_CTRL_WARMTIME_16CYCLES, + /** 32 cycles warmup */ + acmpWarmTime32 = _ACMP_CTRL_WARMTIME_32CYCLES, + /** 64 cycles warmup */ + acmpWarmTime64 = _ACMP_CTRL_WARMTIME_64CYCLES, + /** 128 cycles warmup */ + acmpWarmTime128 = _ACMP_CTRL_WARMTIME_128CYCLES, + /** 256 cycles warmup */ + acmpWarmTime256 = _ACMP_CTRL_WARMTIME_256CYCLES, + /** 512 cycles warmup */ + acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES +} ACMP_WarmTime_TypeDef; +#endif + +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ + || defined(_ACMP_CFG_INPUTRANGE_MASK) +/** + * Adjust ACMP performance for a given input voltage range. + */ +typedef enum { +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) + acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ + acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than VDD/2. */ + acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than VDD/2. */ +#elif defined(_ACMP_CFG_INPUTRANGE_MASK) + acmpInputRangeFull = _ACMP_CFG_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ + acmpInputRangeReduced = _ACMP_CFG_INPUTRANGE_REDUCED, /**< Input can be from 0 to VDD-0.7 V. */ +#endif +} ACMP_InputRange_TypeDef; +#endif + +#if defined(_ACMP_CTRL_PWRSEL_MASK) +/** + * ACMP Power source. + */ +typedef enum { + acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power ACMP using the AVDD supply. */ +#if defined(_ACMP_CTRL_PWRSEL_DVDD) + acmpPowerSourceDvdd = _ACMP_CTRL_PWRSEL_DVDD, /**< Power ACMP using the DVDD supply. */ +#endif + acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power ACMP using the IOVDD/IOVDD0 supply. */ + acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power ACMP using the IOVDD1 supply (if the part has two I/O voltages). */ +} ACMP_PowerSource_TypeDef; +#endif + +#if defined(_ACMP_CTRL_ACCURACY_MASK) \ + || defined(_ACMP_CFG_ACCURACY_MASK) +/** + * ACMP accuracy mode. + */ +typedef enum { +#if defined(_ACMP_CTRL_ACCURACY_MASK) + acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ + acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ +#elif defined(_ACMP_CFG_ACCURACY_MASK) + acmpAccuracyLow = _ACMP_CFG_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ + acmpAccuracyHigh = _ACMP_CFG_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ +#endif +} ACMP_Accuracy_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/** ACMP input to the VA divider. This enumeration is used to select the input for + * the VA Divider. */ +typedef enum { + acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD, /**< Select VDD for the VA divider. */ + acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0, /**< Select APORT2Y CHannel 0 for the VA divider. */ + acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2, /**< Select APORT2Y CHannel 2 for the VA divider. */ + acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4, /**< Select APORT2Y CHannel 4 for the VA divider. */ + acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6, /**< Select APORT2Y CHannel 6 for the VA divider. */ + acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8, /**< Select APORT2Y CHannel 8 for the VA divider. */ + acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10, /**< Select APORT2Y CHannel 10 for the VA divider. */ + acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12, /**< Select APORT2Y CHannel 12 for the VA divider. */ + acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14, /**< Select APORT2Y CHannel 14 for the VA divider. */ + acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16, /**< Select APORT2Y CHannel 16 for the VA divider. */ + acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18, /**< Select APORT2Y CHannel 18 for the VA divider. */ + acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20, /**< Select APORT2Y CHannel 20 for the VA divider. */ + acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22, /**< Select APORT2Y CHannel 22 for the VA divider. */ + acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24, /**< Select APORT2Y CHannel 24 for the VA divider. */ + acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26, /**< Select APORT2Y CHannel 26 for the VA divider. */ + acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28, /**< Select APORT2Y CHannel 28 for the VA divider. */ + acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30, /**< Select APORT2Y CHannel 30 for the VA divider. */ + acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0, /**< Select APORT1X CHannel 0 for the VA divider. */ + acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1, /**< Select APORT1Y CHannel 1 for the VA divider. */ + acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2, /**< Select APORT1X CHannel 2 for the VA divider. */ + acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3, /**< Select APORT1Y CHannel 3 for the VA divider. */ + acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4, /**< Select APORT1X CHannel 4 for the VA divider. */ + acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5, /**< Select APORT1Y CHannel 5 for the VA divider. */ + acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6, /**< Select APORT1X CHannel 6 for the VA divider. */ + acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7, /**< Select APORT1Y CHannel 7 for the VA divider. */ + acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8, /**< Select APORT1X CHannel 8 for the VA divider. */ + acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9, /**< Select APORT1Y CHannel 9 for the VA divider. */ + acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10, /**< Select APORT1X CHannel 10 for the VA divider. */ + acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11, /**< Select APORT1Y CHannel 11 for the VA divider. */ + acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12, /**< Select APORT1X CHannel 12 for the VA divider. */ + acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13, /**< Select APORT1Y CHannel 13 for the VA divider. */ + acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14, /**< Select APORT1X CHannel 14 for the VA divider. */ + acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15, /**< Select APORT1Y CHannel 15 for the VA divider. */ + acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16, /**< Select APORT1X CHannel 16 for the VA divider. */ + acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17, /**< Select APORT1Y CHannel 17 for the VA divider. */ + acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18, /**< Select APORT1X CHannel 18 for the VA divider. */ + acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19, /**< Select APORT1Y CHannel 19 for the VA divider. */ + acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20, /**< Select APORT1X CHannel 20 for the VA divider. */ + acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21, /**< Select APORT1Y CHannel 21 for the VA divider. */ + acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22, /**< Select APORT1X CHannel 22 for the VA divider. */ + acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23, /**< Select APORT1Y CHannel 23 for the VA divider. */ + acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24, /**< Select APORT1X CHannel 24 for the VA divider. */ + acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25, /**< Select APORT1Y CHannel 25 for the VA divider. */ + acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26, /**< Select APORT1X CHannel 26 for the VA divider. */ + acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27, /**< Select APORT1Y CHannel 27 for the VA divider. */ + acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28, /**< Select APORT1X CHannel 28 for the VA divider. */ + acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29, /**< Select APORT1Y CHannel 29 for the VA divider. */ + acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30, /**< Select APORT1X CHannel 30 for the VA divider. */ + acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31 /**< Select APORT1Y CHannel 31 for the VA divider. */ +} ACMP_VAInput_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/** + * ACMP input to the VB divider. This enumeration is used to select the input for + * the VB divider. + */ +typedef enum { + acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25, /**< Mode 1V25 for ACMP_INPUTSEL */ + acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5 /**< Mode 2V5 for ACMP_INPUTSEL */ +} ACMP_VBInput_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) +/** + * ACMP Low-Power Input Selection. + */ +typedef enum { + acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV, /**< Mode VADIV for ACMP_INPUTSEL */ + acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV /**< Mode VBDIV for ACMP_INPUTSEL */ +} ACMP_VLPInput_Typedef; +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) +/** ACMP Input Selection. */ +typedef enum { + acmpInputVSS = _ACMP_INPUTCTRL_POSSEL_VSS, /**< Select VSS. */ + acmpInputVREFDIVAVDD = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD, /**< Select Divided AVDD. */ + acmpInputVREFDIVAVDDLP = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP, /**< Select Low-Power Divided AVDD. */ + acmpInputVREFDIV1V25 = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25, /**< Select Divided 1V25 reference. */ + acmpInputVREFDIV1V25LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP, /**< Select Low-power Divided 1V25 reference. */ + acmpInputVREFDIV2V5 = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5, /**< Select Divided 2V5 reference. */ + acmpInputVREFDIV2V5LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP, /**< Select Low-power Divided 2V5 reference. */ + acmpInputVSENSE01DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4, /**< Select VSENSE0 divided by 4. */ + acmpInputVSENSE01DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP, /**< Select Low-power VSENSE0 divided by 4. */ + acmpInputVSENSE11DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4, /**< VSENSE1 divided by 4. */ + acmpInputVSENSE11DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP, /**< Low-power VSENSE1 divided by 4. */ + acmpInputCAPSENSE = _ACMP_INPUTCTRL_NEGSEL_CAPSENSE, /**< Select Low-Power Divided AVDD. */ +#if defined(_ACMP_INPUTCTRL_POSSEL_VDACOUT0) + acmpInputVDACOUT0 = _ACMP_INPUTCTRL_POSSEL_VDACOUT0, /**< Select VDAC0 channel 0 output. */ + acmpInputVDACOUT1 = _ACMP_INPUTCTRL_POSSEL_VDACOUT1, /**< Select VDAC0 channel 1 output. */ +#endif +#if defined(_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1) + acmpInputVDAC0OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1, /**< Select VDAC0 channel 1 output. */ + acmpInputVDAC1OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1, /**< Select VDAC1 channel 1 output. */ +#endif +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + acmpInputEXTPA = _ACMP_INPUTCTRL_POSSEL_EXTPA, /**< Select external interface, base is PA0. */ + acmpInputEXTPB = _ACMP_INPUTCTRL_POSSEL_EXTPB, /**< Select external interface, base is PB0. */ + acmpInputEXTPC = _ACMP_INPUTCTRL_POSSEL_EXTPC, /**< Select external interface, base is PC0. */ + acmpInputEXTPD = _ACMP_INPUTCTRL_POSSEL_EXTPD, /**< Select external interface, base is PD0. */ +#endif + acmpInputPA0 = _ACMP_INPUTCTRL_POSSEL_PA0, /**< Select Port A Pin0. */ + acmpInputPA1 = _ACMP_INPUTCTRL_POSSEL_PA1, /**< Select Port A Pin1. */ + acmpInputPA2 = _ACMP_INPUTCTRL_POSSEL_PA2, /**< Select Port A Pin2. */ + acmpInputPA3 = _ACMP_INPUTCTRL_POSSEL_PA3, /**< Select Port A Pin3. */ + acmpInputPA4 = _ACMP_INPUTCTRL_POSSEL_PA4, /**< Select Port A Pin4. */ + acmpInputPA5 = _ACMP_INPUTCTRL_POSSEL_PA5, /**< Select Port A Pin5. */ + acmpInputPA6 = _ACMP_INPUTCTRL_POSSEL_PA6, /**< Select Port A Pin6. */ + acmpInputPA7 = _ACMP_INPUTCTRL_POSSEL_PA7, /**< Select Port A Pin7. */ + acmpInputPA8 = _ACMP_INPUTCTRL_POSSEL_PA8, /**< Select Port A Pin8. */ + acmpInputPA9 = _ACMP_INPUTCTRL_POSSEL_PA9, /**< Select Port A Pin9. */ + acmpInputPA10 = _ACMP_INPUTCTRL_POSSEL_PA10, /**< Select Port A Pin10. */ + acmpInputPA11 = _ACMP_INPUTCTRL_POSSEL_PA11, /**< Select Port A Pin11. */ + acmpInputPA12 = _ACMP_INPUTCTRL_POSSEL_PA12, /**< Select Port A Pin12. */ + acmpInputPA13 = _ACMP_INPUTCTRL_POSSEL_PA13, /**< Select Port A Pin13. */ + acmpInputPA14 = _ACMP_INPUTCTRL_POSSEL_PA14, /**< Select Port A Pin14. */ + acmpInputPA15 = _ACMP_INPUTCTRL_POSSEL_PA15, /**< Select Port A Pin15. */ + acmpInputPB0 = _ACMP_INPUTCTRL_POSSEL_PB0, /**< Select Port B Pin0. */ + acmpInputPB1 = _ACMP_INPUTCTRL_POSSEL_PB1, /**< Select Port B Pin1. */ + acmpInputPB2 = _ACMP_INPUTCTRL_POSSEL_PB2, /**< Select Port B Pin2. */ + acmpInputPB3 = _ACMP_INPUTCTRL_POSSEL_PB3, /**< Select Port B Pin3. */ + acmpInputPB4 = _ACMP_INPUTCTRL_POSSEL_PB4, /**< Select Port B Pin4. */ + acmpInputPB5 = _ACMP_INPUTCTRL_POSSEL_PB5, /**< Select Port B Pin5. */ + acmpInputPB6 = _ACMP_INPUTCTRL_POSSEL_PB6, /**< Select Port B Pin6. */ + acmpInputPB7 = _ACMP_INPUTCTRL_POSSEL_PB7, /**< Select Port B Pin7. */ + acmpInputPB8 = _ACMP_INPUTCTRL_POSSEL_PB8, /**< Select Port B Pin8. */ + acmpInputPB9 = _ACMP_INPUTCTRL_POSSEL_PB9, /**< Select Port B Pin9. */ + acmpInputPB10 = _ACMP_INPUTCTRL_POSSEL_PB10, /**< Select Port B Pin10. */ + acmpInputPB11 = _ACMP_INPUTCTRL_POSSEL_PB11, /**< Select Port B Pin11. */ + acmpInputPB12 = _ACMP_INPUTCTRL_POSSEL_PB12, /**< Select Port B Pin12. */ + acmpInputPB13 = _ACMP_INPUTCTRL_POSSEL_PB13, /**< Select Port B Pin13. */ + acmpInputPB14 = _ACMP_INPUTCTRL_POSSEL_PB14, /**< Select Port B Pin14. */ + acmpInputPB15 = _ACMP_INPUTCTRL_POSSEL_PB15, /**< Select Port B Pin15. */ + acmpInputPC0 = _ACMP_INPUTCTRL_POSSEL_PC0, /**< Select Port C Pin0. */ + acmpInputPC1 = _ACMP_INPUTCTRL_POSSEL_PC1, /**< Select Port C Pin1. */ + acmpInputPC2 = _ACMP_INPUTCTRL_POSSEL_PC2, /**< Select Port C Pin2. */ + acmpInputPC3 = _ACMP_INPUTCTRL_POSSEL_PC3, /**< Select Port C Pin3. */ + acmpInputPC4 = _ACMP_INPUTCTRL_POSSEL_PC4, /**< Select Port C Pin4. */ + acmpInputPC5 = _ACMP_INPUTCTRL_POSSEL_PC5, /**< Select Port C Pin5. */ + acmpInputPC6 = _ACMP_INPUTCTRL_POSSEL_PC6, /**< Select Port C Pin6. */ + acmpInputPC7 = _ACMP_INPUTCTRL_POSSEL_PC7, /**< Select Port C Pin7. */ + acmpInputPC8 = _ACMP_INPUTCTRL_POSSEL_PC8, /**< Select Port C Pin8. */ + acmpInputPC9 = _ACMP_INPUTCTRL_POSSEL_PC9, /**< Select Port C Pin9. */ + acmpInputPC10 = _ACMP_INPUTCTRL_POSSEL_PC10, /**< Select Port C Pin10. */ + acmpInputPC11 = _ACMP_INPUTCTRL_POSSEL_PC11, /**< Select Port C Pin11. */ + acmpInputPC12 = _ACMP_INPUTCTRL_POSSEL_PC12, /**< Select Port C Pin12. */ + acmpInputPC13 = _ACMP_INPUTCTRL_POSSEL_PC13, /**< Select Port C Pin13. */ + acmpInputPC14 = _ACMP_INPUTCTRL_POSSEL_PC14, /**< Select Port C Pin14. */ + acmpInputPC15 = _ACMP_INPUTCTRL_POSSEL_PC15, /**< Select Port C Pin15. */ + acmpInputPD0 = _ACMP_INPUTCTRL_POSSEL_PD0, /**< Select Port D Pin0. */ + acmpInputPD1 = _ACMP_INPUTCTRL_POSSEL_PD1, /**< Select Port D Pin1. */ + acmpInputPD2 = _ACMP_INPUTCTRL_POSSEL_PD2, /**< Select Port D Pin2. */ + acmpInputPD3 = _ACMP_INPUTCTRL_POSSEL_PD3, /**< Select Port D Pin3. */ + acmpInputPD4 = _ACMP_INPUTCTRL_POSSEL_PD4, /**< Select Port D Pin4. */ + acmpInputPD5 = _ACMP_INPUTCTRL_POSSEL_PD5, /**< Select Port D Pin5. */ + acmpInputPD6 = _ACMP_INPUTCTRL_POSSEL_PD6, /**< Select Port D Pin6. */ + acmpInputPD7 = _ACMP_INPUTCTRL_POSSEL_PD7, /**< Select Port D Pin7. */ + acmpInputPD8 = _ACMP_INPUTCTRL_POSSEL_PD8, /**< Select Port D Pin8. */ + acmpInputPD9 = _ACMP_INPUTCTRL_POSSEL_PD9, /**< Select Port D Pin9. */ + acmpInputPD10 = _ACMP_INPUTCTRL_POSSEL_PD10, /**< Select Port D Pin10. */ + acmpInputPD11 = _ACMP_INPUTCTRL_POSSEL_PD11, /**< Select Port D Pin11. */ + acmpInputPD12 = _ACMP_INPUTCTRL_POSSEL_PD12, /**< Select Port D Pin12. */ + acmpInputPD13 = _ACMP_INPUTCTRL_POSSEL_PD13, /**< Select Port D Pin13. */ + acmpInputPD14 = _ACMP_INPUTCTRL_POSSEL_PD14, /**< Select Port D Pin14. */ + acmpInputPD15 = _ACMP_INPUTCTRL_POSSEL_PD15, /**< Select Port D Pin15. */ +} ACMP_Channel_TypeDef; +#elif defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) +/** ACMP Input Selection. */ +typedef enum { + acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0, /**< Select Dedicated APORT0X CHannel 0. */ + acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1, /**< Select Dedicated APORT0X CHannel 1. */ + acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2, /**< Select Dedicated APORT0X CHannel 2. */ + acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3, /**< Select Dedicated APORT0X CHannel 3. */ + acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4, /**< Select Dedicated APORT0X CHannel 4. */ + acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5, /**< Select Dedicated APORT0X CHannel 5. */ + acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6, /**< Select Dedicated APORT0X CHannel 6. */ + acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7, /**< Select Dedicated APORT0X CHannel 7. */ + acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8, /**< Select Dedicated APORT0X CHannel 8. */ + acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9, /**< Select Dedicated APORT0X CHannel 9. */ + acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10, /**< Select Dedicated APORT0X CHannel 10. */ + acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11, /**< Select Dedicated APORT0X CHannel 11. */ + acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12, /**< Select Dedicated APORT0X CHannel 12. */ + acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13, /**< Select Dedicated APORT0X CHannel 13. */ + acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14, /**< Select Dedicated APORT0X CHannel 14. */ + acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15, /**< Select Dedicated APORT0X CHannel 15. */ + acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0, /**< Select Dedicated APORT0Y CHannel 0. */ + acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1, /**< Select Dedicated APORT0Y CHannel 1. */ + acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2, /**< Select Dedicated APORT0Y CHannel 2. */ + acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3, /**< Select Dedicated APORT0Y CHannel 3. */ + acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4, /**< Select Dedicated APORT0Y CHannel 4. */ + acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5, /**< Select Dedicated APORT0Y CHannel 5. */ + acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6, /**< Select Dedicated APORT0Y CHannel 6. */ + acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7, /**< Select Dedicated APORT0Y CHannel 7. */ + acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8, /**< Select Dedicated APORT0Y CHannel 8. */ + acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9, /**< Select Dedicated APORT0Y CHannel 9. */ + acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10, /**< Select Dedicated APORT0Y CHannel 10. */ + acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11, /**< Select Dedicated APORT0Y CHannel 11. */ + acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12, /**< Select Dedicated APORT0Y CHannel 12. */ + acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13, /**< Select Dedicated APORT0Y CHannel 13. */ + acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14, /**< Select Dedicated APORT0Y CHannel 14. */ + acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15, /**< Select Dedicated APORT0Y CHannel 15. */ + acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0, /**< Select Dedicated APORT1X CHannel 0. */ + acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1, /**< Select Dedicated APORT1Y CHannel 1. */ + acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2, /**< Select Dedicated APORT1X CHannel 2. */ + acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3, /**< Select Dedicated APORT1Y CHannel 3. */ + acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4, /**< Select Dedicated APORT1X CHannel 4. */ + acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5, /**< Select Dedicated APORT1Y CHannel 5. */ + acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6, /**< Select Dedicated APORT1X CHannel 6. */ + acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7, /**< Select Dedicated APORT1Y CHannel 7. */ + acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8, /**< Select Dedicated APORT1X CHannel 8. */ + acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9, /**< Select Dedicated APORT1Y CHannel 9. */ + acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10, /**< Select Dedicated APORT1X CHannel 10. */ + acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11, /**< Select Dedicated APORT1Y CHannel 11. */ + acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12, /**< Select Dedicated APORT1X CHannel 12. */ + acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13, /**< Select Dedicated APORT1Y CHannel 13. */ + acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14, /**< Select Dedicated APORT1X CHannel 14. */ + acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15, /**< Select Dedicated APORT1Y CHannel 15. */ + acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16, /**< Select Dedicated APORT1X CHannel 16. */ + acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17, /**< Select Dedicated APORT1Y CHannel 17. */ + acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18, /**< Select Dedicated APORT1X CHannel 18. */ + acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19, /**< Select Dedicated APORT1Y CHannel 19. */ + acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20, /**< Select Dedicated APORT1X CHannel 20. */ + acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21, /**< Select Dedicated APORT1Y CHannel 21. */ + acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22, /**< Select Dedicated APORT1X CHannel 22. */ + acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23, /**< Select Dedicated APORT1Y CHannel 23. */ + acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24, /**< Select Dedicated APORT1X CHannel 24. */ + acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25, /**< Select Dedicated APORT1Y CHannel 25. */ + acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26, /**< Select Dedicated APORT1X CHannel 26. */ + acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27, /**< Select Dedicated APORT1Y CHannel 27. */ + acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28, /**< Select Dedicated APORT1X CHannel 28. */ + acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29, /**< Select Dedicated APORT1Y CHannel 29. */ + acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30, /**< Select Dedicated APORT1X CHannel 30. */ + acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31, /**< Select Dedicated APORT1Y CHannel 31. */ + acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0, /**< Select Dedicated APORT2Y CHannel 0. */ + acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1, /**< Select Dedicated APORT2X CHannel 1. */ + acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2, /**< Select Dedicated APORT2Y CHannel 2. */ + acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3, /**< Select Dedicated APORT2X CHannel 3. */ + acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4, /**< Select Dedicated APORT2Y CHannel 4. */ + acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5, /**< Select Dedicated APORT2X CHannel 5. */ + acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6, /**< Select Dedicated APORT2Y CHannel 6. */ + acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7, /**< Select Dedicated APORT2X CHannel 7. */ + acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8, /**< Select Dedicated APORT2Y CHannel 8. */ + acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9, /**< Select Dedicated APORT2X CHannel 9. */ + acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10, /**< Select Dedicated APORT2Y CHannel 10. */ + acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11, /**< Select Dedicated APORT2X CHannel 11. */ + acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12, /**< Select Dedicated APORT2Y CHannel 12. */ + acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13, /**< Select Dedicated APORT2X CHannel 13. */ + acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14, /**< Select Dedicated APORT2Y CHannel 14. */ + acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15, /**< Select Dedicated APORT2X CHannel 15. */ + acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16, /**< Select Dedicated APORT2Y CHannel 16. */ + acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17, /**< Select Dedicated APORT2X CHannel 17. */ + acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18, /**< Select Dedicated APORT2Y CHannel 18. */ + acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19, /**< Select Dedicated APORT2X CHannel 19. */ + acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20, /**< Select Dedicated APORT2Y CHannel 20. */ + acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21, /**< Select Dedicated APORT2X CHannel 21. */ + acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22, /**< Select Dedicated APORT2Y CHannel 22. */ + acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23, /**< Select Dedicated APORT2X CHannel 23. */ + acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24, /**< Select Dedicated APORT2Y CHannel 24. */ + acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25, /**< Select Dedicated APORT2X CHannel 25. */ + acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26, /**< Select Dedicated APORT2Y CHannel 26. */ + acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27, /**< Select Dedicated APORT2X CHannel 27. */ + acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28, /**< Select Dedicated APORT2Y CHannel 28. */ + acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29, /**< Select Dedicated APORT2X CHannel 29. */ + acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30, /**< Select Dedicated APORT2Y CHannel 30. */ + acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31, /**< Select Dedicated APORT2X CHannel 31. */ + acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0, /**< Select Dedicated APORT3X CHannel 0. */ + acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1, /**< Select Dedicated APORT3Y CHannel 1. */ + acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2, /**< Select Dedicated APORT3X CHannel 2. */ + acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3, /**< Select Dedicated APORT3Y CHannel 3. */ + acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4, /**< Select Dedicated APORT3X CHannel 4. */ + acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5, /**< Select Dedicated APORT3Y CHannel 5. */ + acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6, /**< Select Dedicated APORT3X CHannel 6. */ + acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7, /**< Select Dedicated APORT3Y CHannel 7. */ + acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8, /**< Select Dedicated APORT3X CHannel 8. */ + acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9, /**< Select Dedicated APORT3Y CHannel 9. */ + acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10, /**< Select Dedicated APORT3X CHannel 10. */ + acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11, /**< Select Dedicated APORT3Y CHannel 11. */ + acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12, /**< Select Dedicated APORT3X CHannel 12. */ + acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13, /**< Select Dedicated APORT3Y CHannel 13. */ + acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14, /**< Select Dedicated APORT3X CHannel 14. */ + acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15, /**< Select Dedicated APORT3Y CHannel 15. */ + acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16, /**< Select Dedicated APORT3X CHannel 16. */ + acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17, /**< Select Dedicated APORT3Y CHannel 17. */ + acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18, /**< Select Dedicated APORT3X CHannel 18. */ + acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19, /**< Select Dedicated APORT3Y CHannel 19. */ + acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20, /**< Select Dedicated APORT3X CHannel 20. */ + acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21, /**< Select Dedicated APORT3Y CHannel 21. */ + acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22, /**< Select Dedicated APORT3X CHannel 22. */ + acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23, /**< Select Dedicated APORT3Y CHannel 23. */ + acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24, /**< Select Dedicated APORT3X CHannel 24. */ + acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25, /**< Select Dedicated APORT3Y CHannel 25. */ + acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26, /**< Select Dedicated APORT3X CHannel 26. */ + acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27, /**< Select Dedicated APORT3Y CHannel 27. */ + acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28, /**< Select Dedicated APORT3X CHannel 28. */ + acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29, /**< Select Dedicated APORT3Y CHannel 29. */ + acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30, /**< Select Dedicated APORT3X CHannel 30. */ + acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31, /**< Select Dedicated APORT3Y CHannel 31. */ + acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0, /**< Select Dedicated APORT4Y CHannel 0. */ + acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1, /**< Select Dedicated APORT4X CHannel 1. */ + acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2, /**< Select Dedicated APORT4Y CHannel 2. */ + acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3, /**< Select Dedicated APORT4X CHannel 3. */ + acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4, /**< Select Dedicated APORT4Y CHannel 4. */ + acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5, /**< Select Dedicated APORT4X CHannel 5. */ + acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6, /**< Select Dedicated APORT4Y CHannel 6. */ + acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7, /**< Select Dedicated APORT4X CHannel 7. */ + acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8, /**< Select Dedicated APORT4Y CHannel 8. */ + acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9, /**< Select Dedicated APORT4X CHannel 9. */ + acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10, /**< Select Dedicated APORT4Y CHannel 10. */ + acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11, /**< Select Dedicated APORT4X CHannel 11. */ + acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12, /**< Select Dedicated APORT4Y CHannel 12. */ + acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13, /**< Select Dedicated APORT4X CHannel 13. */ + acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16, /**< Select Dedicated APORT4Y CHannel 14. */ + acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17, /**< Select Dedicated APORT4X CHannel 15. */ + acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18, /**< Select Dedicated APORT4Y CHannel 16. */ + acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19, /**< Select Dedicated APORT4X CHannel 17. */ + acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20, /**< Select Dedicated APORT4Y CHannel 18. */ + acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21, /**< Select Dedicated APORT4X CHannel 19. */ + acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22, /**< Select Dedicated APORT4Y CHannel 20. */ + acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23, /**< Select Dedicated APORT4X CHannel 21. */ + acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24, /**< Select Dedicated APORT4Y CHannel 22. */ + acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25, /**< Select Dedicated APORT4X CHannel 23. */ + acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26, /**< Select Dedicated APORT4Y CHannel 24. */ + acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27, /**< Select Dedicated APORT4X CHannel 25. */ + acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28, /**< Select Dedicated APORT4Y CHannel 26. */ + acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29, /**< Select Dedicated APORT4X CHannel 27. */ + acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30, /**< Select Dedicated APORT4Y CHannel 28. */ + acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, /**< Select Dedicated APORT4X CHannel 29. */ + acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, /**< Select Dedicated APORT4Y CHannel 30. */ + acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, /**< Select Dedicated APORT4X CHannel 31. */ +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) + acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, /**< Select DAC Channel 0 Output. */ +#endif +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) + acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, /**< Select DAC Channel 1 Output. */ +#endif + acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, /**< Select Low-Power Sampled Voltage. */ + acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, /**< Select Divided VB Voltage. */ + acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, /**< Select Divided VA Voltage. */ + acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD, /**< ACMPVDD as selected via PWRSEL. */ + acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS, /**< Select VSS. */ +} ACMP_Channel_TypeDef; +#else +/** ACMP inputs. Note that scaled VDD and bandgap references can only be used + * as negative inputs. */ +typedef enum { + /** Channel 0 */ + acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0, + /** Channel 1 */ + acmpChannel1 = _ACMP_INPUTSEL_NEGSEL_CH1, + /** Channel 2 */ + acmpChannel2 = _ACMP_INPUTSEL_NEGSEL_CH2, + /** Channel 3 */ + acmpChannel3 = _ACMP_INPUTSEL_NEGSEL_CH3, + /** Channel 4 */ + acmpChannel4 = _ACMP_INPUTSEL_NEGSEL_CH4, + /** Channel 5 */ + acmpChannel5 = _ACMP_INPUTSEL_NEGSEL_CH5, + /** Channel 6 */ + acmpChannel6 = _ACMP_INPUTSEL_NEGSEL_CH6, + /** Channel 7 */ + acmpChannel7 = _ACMP_INPUTSEL_NEGSEL_CH7, + /** 1.25 V internal reference */ + acmpChannel1V25 = _ACMP_INPUTSEL_NEGSEL_1V25, + /** 2.5 V internal reference */ + acmpChannel2V5 = _ACMP_INPUTSEL_NEGSEL_2V5, + /** Scaled VDD reference */ + acmpChannelVDD = _ACMP_INPUTSEL_NEGSEL_VDD, + +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH0) + /** DAC0 channel 0 */ + acmpChannelDAC0Ch0 = _ACMP_INPUTSEL_NEGSEL_DAC0CH0, +#endif + +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) + /** DAC0 channel 1 */ + acmpChannelDAC0Ch1 = _ACMP_INPUTSEL_NEGSEL_DAC0CH1, +#endif + +#if defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) + /** Capacitive sense mode */ + acmpChannelCapSense = _ACMP_INPUTSEL_NEGSEL_CAPSENSE, +#endif +} ACMP_Channel_TypeDef; +#endif + +#if defined(_ACMP_EXTIFCTRL_MASK) +/** + * ACMP external input select. This type is used to select which APORT is + * used by an external module, such as LESENSE, when it's taking control over + * the ACMP input. + */ +typedef enum { + acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, /**< Select APORT0X as an external input. */ + acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, /**< Select APORT0Y as an external input. */ + acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, /**< Select APORT1X as an external input. */ + acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, /**< Select APORT1Y as an external input. */ + acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, /**< Select APORT1XY as an external input. */ + acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, /**< Select APORT2X as an external input. */ + acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, /**< Select APORT2Y as an external input. */ + acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, /**< Select APORT2YX as an external input. */ + acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, /**< Select APORT3X as an external input. */ + acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, /**< Select APORT3Y as an external input. */ + acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, /**< Select APORT3XY as an external input. */ + acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, /**< Select APORT4X as an external input. */ + acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, /**< Select APORT4Y as an external input. */ + acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, /**< Select APORT4YX as an external input. */ +} ACMP_ExternalInput_Typedef; +#endif + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** Capsense initialization structure. */ +typedef struct { +#if defined(_ACMP_CTRL_FULLBIAS_MASK) + /** Full-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool fullBias; +#endif + +#if defined(_ACMP_CTRL_HALFBIAS_MASK) + /** Half-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool halfBias; +#endif + + /** Bias current. See the ACMP chapter about bias and response time in the + * reference manual for details. */ + uint32_t biasProg; + +#if defined(_ACMP_CTRL_WARMTIME_MASK) + /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be + * about 10 us in wall clock time. */ + ACMP_WarmTime_TypeDef warmTime; +#endif + +#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ + || defined(_ACMP_CFG_HYST_MASK) + /** Hysteresis level. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel; +#else + /** Hysteresis level when ACMP output is 0. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; + + /** Hysteresis level when ACMP output is 1. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; +#endif + + /** A resistor used in the capacitive sensing circuit. For values see + * the device data sheet. */ + ACMP_CapsenseResistor_TypeDef resistor; + +#if defined(_ACMP_INPUTSEL_LPREF_MASK) + /** Low-power reference enabled. This setting, if enabled, reduces the + * power used by VDD and bandgap references. */ + bool lowPowerReferenceEnabled; +#endif + +#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) + /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). + * Valid values are in the 0-63 range. */ + uint32_t vrefDiv; +#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) + /** VDD reference value. VDD_SCALED = (VDD * VDDLEVEL) / 63. + * Valid values are in the 0-63 range. */ + uint32_t vddLevel; +#else + /** + * This value configures the upper voltage threshold of the capsense + * oscillation rail. + * + * The voltage threshold is calculated as follows: + * VDD * (vddLevelHigh + 1) / 64 + */ + uint32_t vddLevelHigh; + + /** + * This value configures the lower voltage threshold of the capsense + * oscillation rail. + * + * The voltage threshold is calculated as follows: + * VDD * (vddLevelLow + 1) / 64 + */ + uint32_t vddLevelLow; +#endif + + /** If true, ACMP is enabled after configuration. */ + bool enable; +} ACMP_CapsenseInit_TypeDef; + +/** A default configuration for capacitive sense mode initialization. */ +#if defined(_ACMP_CFG_MASK) + +// PM5507: provide default configuration that is functional +/** Analog comparator CFG with initial bias value */ +#define PM5507_ACMP_CFG_BIAS_DEFAULT 0x00000004UL +/** Analog comparator reset value */ +#define PM5507_ACMP_CFG_RESETVALUE 0x00000004UL + +/** Capacitive sense mode configuration default values. */ +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ + acmpHysteresisDisabled, /* Disable hysteresis. */ \ + acmpResistor5, /* Use internal resistor value 5. */ \ + 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ + true /* Enable after init. */ \ + } +#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* Don't use fullBias to lower power consumption. */ \ + 0x20, /* Using biasProg value of 0x20 (32). */ \ + acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0. */ \ + acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1. */ \ + acmpResistor5, /* Use internal resistor value 5. */ \ + 0x30, /* VDD level high. */ \ + 0x10, /* VDD level low. */ \ + true /* Enable after initialization. */ \ + } +#elif defined(_ACMP_CTRL_WARMTIME_MASK) +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + acmpWarmTime512, /* 512 cycle warmup to be safe */ \ + acmpHysteresisLevel5, \ + acmpResistor3, \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#else +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + acmpHysteresisLevel5, \ + acmpResistor3, \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#endif + +/** ACMP initialization structure. */ +typedef struct { +#if defined(_ACMP_CTRL_FULLBIAS_MASK) + /** Full-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool fullBias; +#endif + +#if defined(_ACMP_CTRL_HALFBIAS_MASK) + /** Half-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool halfBias; +#endif + + /** Bias current. See the ACMP chapter about bias and response time in the + * reference manual for details. Valid values are in the range 0-7. */ + uint32_t biasProg; + +#if defined(_ACMP_CTRL_IFALL_SHIFT) + /** Enable setting the interrupt flag on the falling edge. */ + bool interruptOnFallingEdge; +#endif +#if defined(_ACMP_CTRL_IRISE_SHIFT) + /** Enable setting the interrupt flag on the rising edge. */ + bool interruptOnRisingEdge; +#endif + +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ + || defined(_ACMP_CFG_INPUTRANGE_MASK) + /** Input range. Adjust this setting to optimize the performance for a + * given input voltage range. */ + ACMP_InputRange_TypeDef inputRange; +#endif + +#if defined(_ACMP_CTRL_ACCURACY_MASK) \ + || defined(_ACMP_CFG_ACCURACY_MASK) + /** ACMP accuracy mode. Select the accuracy mode that matches the + * required current usage and accuracy requirement. Low accuracy + * consumes less current while high accuracy consumes more current. */ + ACMP_Accuracy_TypeDef accuracy; +#endif + +#if defined(_ACMP_CTRL_PWRSEL_MASK) + /** Select the power source for the ACMP. */ + ACMP_PowerSource_TypeDef powerSource; +#endif + +#if defined(_ACMP_CTRL_WARMTIME_MASK) + /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be + * about 10 us in wall clock time. */ + ACMP_WarmTime_TypeDef warmTime; +#endif + +#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ + || defined(_ACMP_CFG_HYST_MASK) + /** Hysteresis level. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel; +#else + /** Hysteresis when ACMP output is 0. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; + + /** Hysteresis when ACMP output is 1. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; +#endif + +#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) + /** VLP Input source. Select between using VADIV or VBDIV as the VLP + * source. */ + ACMP_VLPInput_Typedef vlpInput; +#endif + + /** Inactive value emitted by ACMP during warmup. */ + bool inactiveValue; + +#if defined(_ACMP_INPUTSEL_LPREF_MASK) + /** Low power reference enabled. This setting, if enabled, reduces the + * power used by the VDD and bandgap references. */ + bool lowPowerReferenceEnabled; +#endif + +#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) + /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). + * Valid values are in the 0-63 range. */ + uint32_t vrefDiv; +#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) + /** VDD reference value. VDD_SCALED = VDD * VDDLEVEL * 50 mV/3.8 V. + * Valid values are in the 0-63 range. */ + uint32_t vddLevel; +#endif + + /** If true, ACMP is enabled after configuration. */ + bool enable; +} ACMP_Init_TypeDef; + +/** Default configuration for ACMP regular initialization. */ +#if defined(_ACMP_CFG_MASK) +#define ACMP_INIT_DEFAULT \ + { \ + PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ + acmpInputRangeFull, /* Input range from 0 to Vdd. */ \ + acmpAccuracyLow, /* Low accuracy, less current usage. */ \ + acmpHysteresisDisabled, /* Disable hysteresis. */ \ + false, /* Output 0 when ACMP is inactive. */ \ + 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ + true /* Enable after init. */ \ + } +#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) +#define ACMP_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + 0x7, /* biasProg */ \ + false, /* No interrupt on falling edge. */ \ + false, /* No interrupt on rising edge. */ \ + acmpInputRangeFull, /* Input range from 0 to VDD. */ \ + acmpAccuracyLow, /* Low accuracy, less current usage. */ \ + acmpPowerSourceAvdd, /* Use the AVDD supply. */ \ + acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \ + acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \ + acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \ + false, /* Output 0 when ACMP is inactive. */ \ + true /* Enable after init. */ \ + } +#else +#define ACMP_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + false, /* No interrupt on falling edge. */ \ + false, /* No interrupt on rising edge. */ \ + acmpWarmTime512, /* 512 cycle warmup to be safe */ \ + acmpHysteresisLevel5, \ + false, /* Disabled emitting inactive value during warmup. */ \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#endif + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/** VA Configuration structure. This structure is used to configure the + * VA voltage input source and its dividers. */ +typedef struct { + ACMP_VAInput_TypeDef input; /**< VA voltage input source */ + + /** + * A divider for VA voltage input source when ACMP output is 0. This value is + * used to divide the VA voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VA divided = VA input * (div0 + 1) / 64 + */ + uint32_t div0; + + /** + * A divider for VA voltage input source when ACMP output is 1. This value is + * used to divide the VA voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VA divided = VA input * (div1 + 1) / 64 + */ + uint32_t div1; +} ACMP_VAConfig_TypeDef; + +/** VA default configuration. */ +#define ACMP_VACONFIG_DEFAULT \ + { \ + acmpVAInputVDD, /* Use VDD as VA voltage input source. */ \ + 63, /* No division of the VA source when ACMP output is 0. */ \ + 63, /* No division of the VA source when ACMP output is 1. */ \ + } +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/** VB Configuration structure. This structure is used to configure the + * VB voltage input source and its dividers. */ +typedef struct { + ACMP_VBInput_TypeDef input; /**< VB Voltage input source */ + + /** + * A divider for VB voltage input source when ACMP output is 0. This value is + * used to divide the VB voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VB divided = VB input * (div0 + 1) / 64 + */ + uint32_t div0; + + /** + * A divider for VB voltage input source when ACMP output is 1. This value is + * used to divide the VB voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VB divided = VB input * (div1 + 1) / 64 + */ + uint32_t div1; +} ACMP_VBConfig_TypeDef; + +/** VB default configuration. */ +#define ACMP_VBCONFIG_DEFAULT \ + { \ + acmpVBInput1V25, /* Use 1.25 V as VB voltage input source. */ \ + 63, /* No division of the VB source when ACMP output is 0. */ \ + 63, /* No division of the VB source when ACMP output is 1. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init); +void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); +void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); +void ACMP_Disable(ACMP_TypeDef *acmp); +void ACMP_Enable(ACMP_TypeDef *acmp); +#if defined(_ACMP_EXTIFCTRL_MASK) +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); +#endif +#if defined(_GPIO_ACMP_ROUTEEN_MASK) +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, unsigned int pin, bool enable, bool invert); +#else +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); +#endif +void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); +void ACMP_Reset(ACMP_TypeDef *acmp); +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig); +#endif +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig); +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending ACMP interrupts. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * Pending ACMP interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IFC_EDGE or ACMP_IFC_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IF_CLR = flags; +#else + acmp->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more ACMP interrupts. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags) +{ + BUS_RegMaskedClear(&(acmp->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Enable one or more ACMP interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using ACMP_IntClear() prior to enabling + * if a pending interrupt should be ignored. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IEN_SET = flags; +#else + acmp->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending ACMP interrupt flags. + * + * @note + * This function does not clear event bits. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @return + * Pending ACMP interrupt sources. A bitwise logic OR combination of valid + * interrupt flags for the ACMP module. The pending interrupt sources can be, + * for instance, ACMP_IF_EDGE or ACMP_IF_WARMUP. + ******************************************************************************/ +__STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp) +{ + return acmp->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending ACMP interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @note + * This function does not clear interrupt flags. + * + * @return + * Pending and enabled ACMP interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in ACMPx_IEN_nnn + * register (ACMPx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the ACMP module + * (ACMPx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp) +{ + uint32_t tmp; + + /* Store ACMPx->IEN in a temporary variable to define the explicit order + * of volatile accesses. */ + tmp = acmp->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return acmp->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending ACMP interrupts from software. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to set as pending. Use a bitwise logic OR + * combination of valid interrupt flags for the ACMP module. The flags can be, + * for instance, ACMP_IFS_EDGE or ACMP_IFS_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntSet(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IF_SET = flags; +#else + acmp->IFS = flags; +#endif +} + +#if defined(_ACMP_INPUTCTRL_MASK) +/***************************************************************************//** + * @brief + * Convert GPIO port/pin to ACMP input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO pin + * + * @return + * ACMP input selection + ******************************************************************************/ +__STATIC_INLINE ACMP_Channel_TypeDef ACMP_PortPinToInput(GPIO_Port_TypeDef port, uint8_t pin) +{ + uint32_t input = (((uint32_t) port + (_ACMP_INPUTCTRL_POSSEL_PA0 >> 4)) << 4) | pin; + + return (ACMP_Channel_TypeDef) input; +} +#endif + +/***************************************************************************//** + * @brief + * Get state of ACMP output value + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @return + * State of ACMP output value + ******************************************************************************/ +__STATIC_INLINE bool ACMP_OutputGet(ACMP_TypeDef *acmp) +{ + /* Waiting for ACMP is ready*/ +#if defined(ACMP_STATUS_ACMPRDY) + while (!(acmp->STATUS & ACMP_STATUS_ACMPRDY)) ; +#elif defined(ACMP_STATUS_ACMPACT) + while (!(acmp->STATUS & ACMP_STATUS_ACMPACT)) ; +#endif + + return (acmp->STATUS & ACMP_STATUS_ACMPOUT); +} + +/** @} (end addtogroup acmp) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ +#endif /* EM_ACMP_H */ diff --git a/Libs/platform/emlib/inc/em_assert.h b/Libs/platform/emlib/inc/em_assert.h new file mode 100644 index 0000000..f3c14ac --- /dev/null +++ b/Libs/platform/emlib/inc/em_assert.h @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Emlib peripheral API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_ASSERT_H +#define EM_ASSERT_H + +#include "sl_assert.h" + +#endif /* EM_ASSERT_H */ diff --git a/Libs/platform/emlib/inc/em_burtc.h b/Libs/platform/emlib/inc/em_burtc.h new file mode 100644 index 0000000..bd2583b --- /dev/null +++ b/Libs/platform/emlib/inc/em_burtc.h @@ -0,0 +1,473 @@ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BURTC_H +#define EM_BURTC_H + +#include "em_device.h" +#if defined(BURTC_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup burtc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** BURTC clock divisors. These values are valid for the BURTC prescaler. */ +#define burtcClkDiv_1 1 /**< Divide clock by 1. */ +#define burtcClkDiv_2 2 /**< Divide clock by 2. */ +#define burtcClkDiv_4 4 /**< Divide clock by 4. */ +#define burtcClkDiv_8 8 /**< Divide clock by 8. */ +#define burtcClkDiv_16 16 /**< Divide clock by 16. */ +#define burtcClkDiv_32 32 /**< Divide clock by 32. */ +#define burtcClkDiv_64 64 /**< Divide clock by 64. */ +#define burtcClkDiv_128 128 /**< Divide clock by 128. */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC clock selection. */ +typedef enum { + /** Ultra low frequency (1 kHz) clock. */ + burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, + /** Low frequency RC oscillator. */ + burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, + /** Low frequency crystal oscillator. */ + burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO +} BURTC_ClkSel_TypeDef; + +/** BURTC mode of operation. */ +typedef enum { + /** Disable BURTC */ + burtcModeDisable = BURTC_CTRL_MODE_DISABLE, + /** Enable and start BURTC counter in EM0 to EM2. */ + burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, + /** Enable and start BURTC counter in EM0 to EM3. */ + burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, + /** Enable and start BURTC counter in EM0 to EM4. */ + burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, +} BURTC_Mode_TypeDef; + +/** BURTC low power mode. */ +typedef enum { + /** Low Power Mode is disabled. */ + burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, + /** Low Power Mode is always enabled. */ + burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, + /** Low Power Mode when system enters backup mode. */ + burtcLPBU = BURTC_LPMODE_LPMODE_BUEN +} BURTC_LP_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC initialization structure for Series 0 devices. */ +typedef struct { + bool enable; /**< Enable BURTC after initialization (starts counter). */ + + BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ + bool debugRun; /**< If true, counter will keep running under debug halt. */ + BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ + uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ + + uint32_t lowPowerComp; /**< Number of least significant clock bits to ignore in low power mode. */ + bool timeStamp; /**< Enable time stamp on entering backup power domain. */ + + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ + + BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC initialization structure. */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + burtcModeEM2, \ + false, \ + burtcClkSelULFRCO, \ + burtcClkDiv_1, \ + 0, \ + true, \ + false, \ + burtcLPDisable, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) +/** BURTC initialization structure for Series 2 devices. */ +typedef struct { + bool start; /**< Start BURTC after initialization */ + bool debugRun; /**< If true, counter will keep running under debug halt */ + uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ + bool em4comp; /**< Enable EM4 wakeup on compare match. */ + bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC init structure */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + false, \ + 1, \ + 0, \ + false, \ + false, \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Clear one or more pending BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntClear(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_CLR = flags; +#else + BURTC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntDisable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_CLR = flags; +#else + BURTC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more BURTC interrupts. + * + * @note + * Depending on use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling + * if a pending interrupt should be ignored. + * + * @param[in] flags + * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntEnable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_SET = flags; +#else + BURTC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending BURTC interrupt flags. + * + * @note + * This function does not clear the event bits. + * + * @return + * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed + * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGet(void) +{ + return BURTC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending BURTC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending BURTC interrupt sources that is also enabled. Returns a set of + * interrupt flags OR-ed together for multiple interrupt sources in the + * BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Get enabled interrupts */ + tmp = BURTC->IEN; + + /* Return set interrupts */ + return BURTC->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending BURTC interrupts from SW. + * + * @param[in] flags + * BURTC interrupt sources to set to pending. Use a set of interrupt flags + * OR-ed together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntSet(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_SET = flags; +#else + BURTC->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Status of BURTC RAM, timestamp and LP Mode + * + * @return A mask logically OR-ed status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_Status(void) +{ + return BURTC->STATUS; +} + +#if defined(BURTC_CMD_CLRSTATUS) +/***************************************************************************//** + * @brief + * Clear and reset BURTC status register + ******************************************************************************/ +__STATIC_INLINE void BURTC_StatusClear(void) +{ + BURTC->CMD = BURTC_CMD_CLRSTATUS; +} +#endif + +/***************************************************************************//** + * @brief + * Wait for the BURTC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +__STATIC_INLINE void BURTC_SyncWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (BURTC->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start BURTC counter. + * + * This function will send a start command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the start command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Start(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_START; +} + +/***************************************************************************//** + * @brief + * Stop the BURTC counter. + * + * This function will send a stop command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the stop command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Stop(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_STOP; +} +#endif + +/***************************************************************************//** + * @brief Get BURTC counter. + * + * @return + * BURTC counter value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_CounterGet(void) +{ + return BURTC->CNT; +} + +#if defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief Get BURTC timestamp for entering BU. + * + * @return + * BURTC Time Stamp value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_TimestampGet(void) +{ + return BURTC->TIMESTAMP; +} + +/***************************************************************************//** + * @brief Freeze register updates until enabled. + * @param[in] enable If true, registers are not updated until enabled again. + ******************************************************************************/ +__STATIC_INLINE void BURTC_FreezeEnable(bool enable) +{ + BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief Shut down power to retention register bank. + * @param[in] enable + * If true, shuts off power to retention registers. + * @note + * When power retention is disabled, it can't be enabled again (until + * reset). + ******************************************************************************/ +__STATIC_INLINE void BURTC_Powerdown(bool enable) +{ + BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Set a value in one of the retention registers. + * + * @param[in] num + * Register to set + * @param[in] data + * Value to put into register + ******************************************************************************/ +__STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) +{ + EFM_ASSERT(num <= 127); + + BURTC->RET[num].REG = data; +} + +/***************************************************************************//** + * @brief + * Read a value from one of the retention registers. + * + * @param[in] num + * Retention Register to read + * + * @return + * Value of the retention register + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) +{ + EFM_ASSERT(num <= 127); + + return BURTC->RET[num].REG; +} +#endif + +/***************************************************************************//** + * @brief + * Lock BURTC registers, which will protect from writing new config settings. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Lock(void) +{ + BURTC->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock BURTC registers, which will enable write access to change configuration. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Unlock(void) +{ + BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; +} + +void BURTC_Reset(void); +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); +void BURTC_Enable(bool enable); +void BURTC_CounterReset(void); +void BURTC_CompareSet(unsigned int comp, uint32_t value); +uint32_t BURTC_CompareGet(unsigned int comp); +#if defined(_BURTC_CTRL_MASK) +uint32_t BURTC_ClockFreqGet(void); +#endif + +/** @} (end addtogroup burtc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* BURTC_PRESENT */ +#endif /* EM_BURTC_H */ diff --git a/Libs/platform/emlib/inc/em_bus.h b/Libs/platform/emlib/inc/em_bus.h new file mode 100644 index 0000000..e56cf14 --- /dev/null +++ b/Libs/platform/emlib/inc/em_bus.h @@ -0,0 +1,350 @@ +/***************************************************************************//** + * @file + * @brief RAM and peripheral bit-field set and clear API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BUS_H +#define EM_BUS_H + +#include "sl_assert.h" +#include "sl_core.h" +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup bus BUS - Bitfield Read/Write + * @brief BUS register and RAM bit/field read/write API + * @details + * API to perform bit-band and field set/clear access to RAM and peripherals. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single bit write on a 32-bit word in RAM. + * See the reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. RAM bit-banding is + * performed using the memory alias region at BITBAND_RAM_BASE. + * + * @param[in] addr An ddress of a 32-bit word in RAM. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * RAM bit-banding is performed using the memory alias region + * at BITBAND_RAM_BASE. + * + * @param[in] addr RAM address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. Peripheral register + * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ + EFM_ASSERT(bit < 32U); +#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr; + if (val != 0U) { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + } else { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + } + *(volatile uint32_t *)aliasAddr = 1UL << bit; +#elif defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * Peripheral register bit-banding is performed using the memory alias + * region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked set operation on a peripheral register address. + * + * @details + * A peripheral register masked set provides a single-cycle and atomic set + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 1 in the register. All 0s in the mask are not changed in the + * register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field set. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to set. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_SET_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITSET_MEM_BASE) + uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr |= mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked clear operation on the peripheral register address. + * + * @details + * A peripheral register masked clear provides a single-cycle and atomic clear + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 0 in the register. + * All 0s in the mask are not changed in the register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field clear. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to clear. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITCLR_MEM_BASE) + uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr &= ~mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform peripheral register masked write. + * + * @details + * This function first reads the peripheral register and updates only bits + * that are set in the mask with content of val. Typically, the mask is a + * bit-field in the register and the value val is within the mask. + * + * @note + * The read-modify-write operation is executed in a critical section to + * guarantee atomicity. Note that atomicity can only be guaranteed if register + * is modified only by the core, and not by other peripherals (like DMA). + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @param[in] val A peripheral register value. The value must be shifted to the + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. The + register value is masked to prevent involuntary spillage. + ******************************************************************************/ +#if defined(__GNUC__) && __GNUC__ >= 10 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wanalyzer-null-dereference" +#endif +__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, + uint32_t mask, + uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + EFM_ASSERT(addr != 0); + *addr = (*addr & ~mask) | (val & mask); + + CORE_EXIT_CRITICAL(); +} +#if defined(__GNUC__) && __GNUC__ >= 10 +#pragma GCC diagnostic pop +#endif + +/***************************************************************************//** + * @brief + * Perform a peripheral register masked read. + * + * @details + * Read an unshifted and masked value from a peripheral register. + * + * @note + * This operation is not hardware accelerated. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @return + * An unshifted and masked register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, + uint32_t mask) +{ + return *addr & mask; +} + +/** @} (end addtogroup bus) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_BUS_H */ diff --git a/Libs/platform/emlib/inc/em_chip.h b/Libs/platform/emlib/inc/em_chip.h new file mode 100644 index 0000000..b19b744 --- /dev/null +++ b/Libs/platform/emlib/inc/em_chip.h @@ -0,0 +1,483 @@ +/***************************************************************************//** + * @file + * @brief Chip Errata Workarounds + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CHIP_H +#define EM_CHIP_H + +#include "em_device.h" +#include "sl_common.h" +#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2) +#include "em_system.h" +#endif +#include "em_bus.h" + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#include "em_gpio.h" +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240) +#include "em_cmu.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup chip CHIP - Chip Errata Workarounds + * @brief Chip errata workaround APIs + * @details + * API to apply chip errata workarounds at initialization and reset. + * @{ + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Chip initialization routine for revision errata workarounds. + * + * @note + * This function must be called immediately in main(). + * + * This initialization function configures the device to a state + * as similar to later revisions as possible to improve software compatibility + * with newer parts. See the device-specific errata for details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Init(void) +{ +#if defined(MSC_CACHECMD_INVCACHE) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#elif defined(MSC_CMD_INVCACHE) + MSC->CMD = MSC_CMD_INVCACHE; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) + uint32_t rev; + SYSTEM_ChipRevision_TypeDef chipRev; + volatile uint32_t *reg; + + rev = *(volatile uint32_t *)(0x0FE081FC); + /* Engineering Sample calibration setup. */ + if ((rev >> 24) == 0) { + reg = (volatile uint32_t *)0x400CA00C; + *reg &= ~(0x70UL); + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0xE0000000UL); + *reg |= ~(7UL << 25); + } + if ((rev >> 24) <= 3) { + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0x00001F80UL); + /* Update CMU reset values. */ + reg = (volatile uint32_t *)0x400C8040; + *reg = 0; + reg = (volatile uint32_t *)0x400C8044; + *reg = 0; + reg = (volatile uint32_t *)0x400C8058; + *reg = 0; + reg = (volatile uint32_t *)0x400C8060; + *reg = 0; + reg = (volatile uint32_t *)0x400C8078; + *reg = 0; + } + + SYSTEM_ChipRevisionGet(&chipRev); + if (chipRev.major == 0x01) { + /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ + /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ + if (chipRev.minor == 00) { + reg = (volatile uint32_t *)0x400C8040; + *reg |= 0x2; + } + + /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ + /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ + /* later chip revisions and is only needed for rev A+B. */ + if (chipRev.minor <= 0x01) { + reg = (volatile uint32_t *)0x400C8044; + *reg |= 0x1; + } + } + /* Ensure correct ADC/DAC calibration value. */ + rev = *(volatile uint32_t *)0x0FE081F0; + if (rev < 0x4C8ABA00) { + uint32_t cal; + + /* Enable ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg |= (1 << 14 | 1 << 11); + + /* Retrive calibration values. */ + cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 24; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 16; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 8; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 0; + + /* ADC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)0x40002034UL; + *reg = cal; + + /* DAC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)(0x4000402CUL); + cal = *(volatile uint32_t *)0x0FE081C8UL; + *reg = cal; + + /* Turn off ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg &= ~(1 << 14 | 1 << 11); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; + SYSTEM_ChipRevision_TypeDef chipRev; + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevisionGet(&chipRev); + + // All Giant and Leopard parts except Leopard Rev E + if ((prodRev >= 16) && (chipRev.minor >= 3) + && !((chipRev.major == 2) && (chipRev.minor == 4))) { + /* This fixes an issue with the LFXO on high temperatures. */ + *(volatile uint32_t*)0x400C80C0 = + (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); + + if (prodRev <= 129) { + /* This fixes a mistaken internal connection between PC0 and PC4. */ + /* This disables an internal pull-down on PC4. */ + *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); + /* This disables an internal LDO test signal driving PC4. */ + *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); + } +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /**************************** + * Fixes for errata GPIO_E201 (slewrate) and + * HFXO high-temperature oscillator startup robustness fix. */ + + uint32_t port; + uint32_t clkEn; + uint8_t prodRev; + const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) + | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); + const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK); + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + /* This errata is fixed in hardware from PRODREV 0x8F. */ + if (prodRev < 0x8F) { + /* Fixes for errata GPIO_E201 (slewrate). */ + + /* Save HFBUSCLK enable state and enable GPIO clock. */ + clkEn = CMU->HFBUSCLKEN0; + CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; + + /* Update slewrate. */ + for (port = 0; port <= GPIO_PORT_MAX; port++) { + GPIO->P[port].CTRL = setVal | resetVal; + } + + /* Restore HFBUSCLK enable state. */ + CMU->HFBUSCLKEN0 = clkEn; + } + + /* This errata is fixed in hardware from PRODREV 0x90. */ + if (prodRev < 0x90) { + /* HFXO high-temperature oscillator startup robustness fix. */ + CMU->HFXOSTARTUPCTRL = + (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) + | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + } + + if (chipRev.major == 0x01) { + /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ + *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; + } + + /**************************** + * Fix for errata DCDC_E206. + * Disable bypass limit enabled temporarily in SystemInit() errata + * workaround. */ + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + uint8_t prodRev = SYSTEM_GetProdRev(); + + /* EM2 current fixes for early samples. */ + if (prodRev == 0U) { + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; + } + if (prodRev < 2U) { + *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1UL << 8; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if ((chipRev.major > 1) || (chipRev.minor >= 3)) { + /* PLFRCO trim values */ + *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608; + *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250; + *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118; + *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400; + } +#endif + +/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ +#if defined(_LCD_DISPCTRL_CHGRDST_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; + CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; + *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); + CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; + CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) + /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */ + *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { + /* Change HFXO default peak detector settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) + | 0x00178500U; + /* Change HFXO low power control settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) + | 0x0000C000U; + /* Change default SQBUF bias current. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; + } + + if (chipRev.major == 0x01 && chipRev.minor == 0x0) { + /* Trigger RAM read for each RAM instance */ + volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; + for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { + // Force memory read + *dmem; + dmem += (DMEM_BANK0_SIZE / 4U); + } + } + + /* Set TRACE clock to intended reset value. */ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) +#if defined(SL_TRUSTZONE_SECURE) +#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL) +#else +#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL) +#endif +#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL) + if (SYSTEM_GetProdRev() == 1) { + bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + /* Enable HFRCO CLKOUT0. */ + *(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0; + if (hfrcoClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; + } + } +#endif + +/* PM-3503 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) + { + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; + + while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { + /* Wait for previous synchronization to finish */ + } + + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { + /* Wait for BYPASS switch enable. */ + } + + if (dcdcIsLock) { + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; + } + + if (dcdcClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + } +#endif + +/* PM-5163 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && chipRev.minor == 0x00) { + bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + + *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) + | 0x0C000000UL; + + if (hfxo0ClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; + } + } +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240) + + // Enable ICache out of reset. + CMU->CLKEN1_SET = _CMU_CLKEN1_ICACHE0_MASK; + ICACHE0->CTRL_CLR = _ICACHE_CTRL_CACHEDIS_MASK; + CMU->CLKEN1_CLR = _CMU_CLKEN1_ICACHE0_MASK; + + CMU->CLKEN0_SET = _CMU_CLKEN0_HFRCO0_MASK; + + if (((HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT) == _HFRCO_CAL_TUNING_MASK) { + CMU_HFRCODPLLBandSet(cmuHFRCODPLLFreq_19M0Hz); + } + + CMU->CLKEN0_CLR = _CMU_CLKEN0_HFRCO0_MASK; + +#endif +} + +/**************************************************************************//** + * @brief + * Chip reset routine with errata workarounds. + * + * @note + * This function should be called to reset the chip. It does not return. + * + * This function applies any errata workarounds needed to cleanly reset the + * device and then performs a system reset. See the device-specific errata for + * details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Reset(void) +{ +#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /**************************** + * Workaround for errata DCDC_E206. + * Disable radio interference minimization features when resetting */ + + // Ensure access to EMU registers + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; + + // No need to do anything if the DCDC is not powering DVDD + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + // Make sure radio cannot accidentally re-enable features + *(volatile uint32_t *)(0x40084040UL) = 0x1UL; + + // If DCDC is in use, disable features + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) + || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) { + BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); + BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); + } + } +#endif + + NVIC_SystemReset(); +} + +/** @} (end addtogroup chip) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_CHIP_H */ diff --git a/Libs/platform/emlib/inc/em_cmu.h b/Libs/platform/emlib/inc/em_cmu.h new file mode 100644 index 0000000..d413ad5 --- /dev/null +++ b/Libs/platform/emlib/inc/em_cmu.h @@ -0,0 +1,3655 @@ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CMU_H +#define EM_CMU_H + +#include "em_device.h" +#if defined(CMU_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu_compat.h" +#include "em_gpio.h" +#include "sl_common.h" +#include "sl_enum.h" +#include "sl_status.h" +#include "sli_em_cmu.h" +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup cmu + * @{ + ******************************************************************************/ + +/** Macro to set clock sources in the clock tree. */ +#define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 0U +#define CMU_EN_BIT_MASK 0x1FU + +/* Enable register ID's for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CLKEN0_EN_REG 1 +#define CMU_CLKEN1_EN_REG 2 +#if defined(_CMU_CLKEN2_MASK) +#define CMU_CLKEN2_EN_REG 3 +#endif +#define CMU_CRYPTOACCCLKCTRL_EN_REG 3 +#define CMU_EN_REG_POS 5U +#define CMU_EN_REG_MASK 0x3U + +/* Clock branch ID's internal use. */ +#define CMU_CORE_BRANCH 0 +#define CMU_SYSCLK_BRANCH 1 +#define CMU_SYSTICK_BRANCH 2 +#define CMU_HCLK_BRANCH 3 +#define CMU_EXPCLK_BRANCH 4 +#define CMU_PCLK_BRANCH 5 +#define CMU_LSPCLK_BRANCH 6 +#define CMU_TRACECLK_BRANCH 7 +#define CMU_EM01GRPACLK_BRANCH 8 +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) +#define CMU_EM01GRPBCLK_BRANCH 9 +#endif +#define CMU_EUART0CLK_BRANCH 10 +#define CMU_IADCCLK_BRANCH 11 +#define CMU_EM23GRPACLK_BRANCH 12 +#define CMU_WDOG0CLK_BRANCH 13 +#if defined(RTCC_PRESENT) +#define CMU_RTCCCLK_BRANCH 14 +#elif defined(SYSRTC_PRESENT) +#define CMU_SYSRTCCLK_BRANCH 14 +#endif +#define CMU_EM4GRPACLK_BRANCH 15 +#if defined(PDM_PRESENT) +#define CMU_PDMREF_BRANCH 16 +#endif +#define CMU_DPLLREFCLK_BRANCH 17 +#if WDOG_COUNT > 1 +#define CMU_WDOG1CLK_BRANCH 18 +#endif +#if defined(LCD_PRESENT) +#define CMU_LCD_BRANCH 19 +#endif +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_BRANCH 20 +#endif +#if defined(PCNT_PRESENT) +#define CMU_PCNT_BRANCH 21 +#endif +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHF_BRANCH 22 +#define CMU_LESENSE_BRANCH 23 +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_BRANCH 24 +#endif +#if defined(VDAC_PRESENT) && (VDAC_COUNT > 1) +#define CMU_VDAC1_BRANCH 25 +#endif +#define CMU_CLK_BRANCH_POS 7U +#define CMU_CLK_BRANCH_MASK 0x1FU +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_EMU_CMD_EM01VSCALE1_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL +#endif + +/* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 1 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Disable clocks configuration */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#endif // (_SILICON_LABS_32B_SERIES_2) + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +/** HFRCODPLL frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) { + cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ + cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ + cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ + cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ + cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ + cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */ +#endif + cmuHFRCODPLLFreq_UserDefined = 0, +}; + +#if defined(USBPLL_PRESENT) +/** HFXO reference frequency */ +SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) { + cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */ + cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (25UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */ + cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (16UL << _USBPLL_CTRL_DIVX_SHIFT) + | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */ + cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */ +}; +#endif + +/** HFRCODPLL maximum frequency */ +#define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz +/** HFRCODPLL minimum frequency */ +#define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz + +#if defined(HFRCOEM23_PRESENT) +/** HFRCOEM23 frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) { + cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ + cmuHFRCOEM23Freq_UserDefined = 0, +}; + +/** HFRCOEM23 maximum frequency */ +#define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz +/** HFRCOEM23 minimum frequency */ +#define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz +#endif // defined(HFRCOEM23_PRESENT) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Clock points in CMU clock-tree. */ +SL_ENUM(CMU_Clock_TypeDef) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK, /**< System clock. */ + cmuClock_HCLK, /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK, /**< Export clock. */ + cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ + cmuClock_IADCCLK, /**< IADC clock. */ + cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ + cmuClock_WDOG0CLK, /**< WDOG0 clock. */ + cmuClock_WDOG1CLK, /**< WDOG1 clock. */ + cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ + cmuClock_TRACECLK, /**< Debug trace clock. */ + cmuClock_RTCCCLK, /**< RTCC clock. */ + cmuClock_HFRCOEM23, + + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_CORE, /**< Cortex-M33 core clock. */ + cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ + cmuClock_ACMP0, /**< ACMP0 clock. */ + cmuClock_ACMP1, /**< ACMP1 clock. */ + cmuClock_BURTC, /**< BURTC clock. */ + cmuClock_GPCRC, /**< GPCRC clock. */ + cmuClock_GPIO, /**< GPIO clock. */ + cmuClock_I2C0, /**< I2C0 clock. */ + cmuClock_I2C1, /**< I2C1 clock. */ + cmuClock_IADC0, /**< IADC clock. */ + cmuClock_LDMA, /**< LDMA clock. */ + cmuClock_LETIMER0, /**< LETIMER clock. */ + cmuClock_PRS, /**< PRS clock. */ + cmuClock_RTCC, /**< RTCC clock. */ + cmuClock_TIMER0, /**< TIMER0 clock. */ + cmuClock_TIMER1, /**< TIMER1 clock. */ + cmuClock_TIMER2, /**< TIMER2 clock. */ + cmuClock_TIMER3, /**< TIMER3 clock. */ + cmuClock_USART0, /**< USART0 clock. */ + cmuClock_USART1, /**< USART1 clock. */ + cmuClock_USART2, /**< USART2 clock. */ + cmuClock_WDOG0, /**< WDOG0 clock. */ + cmuClock_WDOG1, /**< WDOG1 clock. */ + cmuClock_PDM /**< PDM clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/** Clock points in CMU clock-tree. */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */ + cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */ + cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */ + cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */ + cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */ + cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */ +#if defined(PDM_PRESENT) + cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */ +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */ +#endif +#if defined(EUART_PRESENT) + cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */ +#elif defined(EUSART_PRESENT) + cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */ +#endif + cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */ + cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */ + cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */ +#endif +#if defined(RTCC_PRESENT) + cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */ +#elif defined(SYSRTC_PRESENT) + cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */ +#endif + cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */ + cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */ +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */ + cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */ +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */ + cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */ +#endif + + cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */ +#if defined(PDM_PRESENT) + cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */ +#endif + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */ + cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */ +#if defined(RADIOAES_PRESENT) + cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */ +#endif + cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */ + cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */ + cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */ + cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */ + cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */ +#if defined(_CMU_CLKEN2_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN1_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN0_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN1_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN0_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN1_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN0_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN1_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN0_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER8_SHIFT) + cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER9_SHIFT) + cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 0 + cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 1 +#if defined(_CMU_CLKEN0_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#elif defined(_CMU_CLKEN2_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#endif +#endif /* defined(USART_PRESENT) && USART_COUNT > 1 */ +#if defined(USART_PRESENT) && USART_COUNT > 2 + cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */ +#endif /* defined(USART_PRESENT) && USART_COUNT > 2 */ +#if defined(IADC_PRESENT) + cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */ +#endif + cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */ +#if defined(LETIMER_PRESENT) + cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */ +#endif + cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */ +#endif +#if defined(I2C_PRESENT) + cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */ +#if I2C_COUNT > 1 + cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */ +#endif /* I2C_COUNT > 1 */ +#if I2C_COUNT > 2 + cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */ +#endif /* I2C_COUNT > 2 */ +#if I2C_COUNT > 3 + cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */ +#endif /* I2C_COUNT > 3 */ +#endif /* defined(I2C_PRESENT) */ + cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */ + cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */ + cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */ +#if defined(HFRCOEM23_PRESENT) + cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */ +#endif +#if defined(HFXO_PRESENT) + cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */ +#endif + cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */ + cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */ + cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */ + cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */ +#if defined(EUART_PRESENT) + cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */ +#endif +#if defined(PDM_PRESENT) + cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */ +#endif + cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */ + cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */ + cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */ + cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */ +#if defined(RTCC_PRESENT) + cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */ +#endif + cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */ +#if defined(SYSRTC_PRESENT) + cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#if defined(_CMU_CLKEN1_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#elif defined(_CMU_CLKEN2_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#if defined(_CMU_CLKEN1_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#elif defined(_CMU_CLKEN2_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#if defined(_CMU_CLKEN1_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#elif defined(_CMU_CLKEN2_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */ +#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) + cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */ +#endif +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */ +#endif +#if defined(SEMAILBOX_PRESENT) + cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */ +#endif + cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */ +#if defined(ICACHE_PRESENT) + cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */ +#endif +#if defined(ACMP_PRESENT) + cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */ +#if ACMP_COUNT > 1 + cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */ +#endif +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */ +#endif +#if defined(DMEM_PRESENT) + cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */ +#endif +#if defined(KEYSCAN_PRESENT) + cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */ +#endif +#if defined(MVP_PRESENT) + cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */ +#endif + cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */ +#if defined(USB_PRESENT) + cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */ +#endif +#if defined(ETAMPDET_PRESENT) + cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ + cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuOsc_HFXO, /**< High frequency crystal oscillator. */ + cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +}; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS /**< PRS input as clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */ +#endif + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_SYSCLK, /**< System clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */ +#endif + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS, /**< PRS input as clock. */ +#if defined(PCNT_PRESENT) + cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */ +#endif + cmuSelect_TEMPOSC, /**< Temperature oscillator. */ + cmuSelect_PFMOSC, /**< PFM oscillator. */ + cmuSelect_BIASOSC, /**< BIAS oscillator. */ +#if defined(USBPLL_PRESENT) + cmuSelect_USBPLL0, /**< PLL clock for USB. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** DPLL reference clock edge detect selector. */ +SL_ENUM(CMU_DPLLEdgeSel_TypeDef) { + cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ +}; + +/** LFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) { + cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ + cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ +}; + +/** LFXO start-up timeout delay. */ +SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) { + cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ + cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ + cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ + cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ + cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ + cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ + cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ + cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ +}; + +/** HFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) { + cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ +#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) + cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */ +#endif +}; + +/** HFXO core bias LSB change timeout. */ +SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) { + cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ + cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ + cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ + cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ + cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ + cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ + cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ + cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ + cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ + cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ + cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ + cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ + cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ + cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ + cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ + cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ +}; + +/** HFXO steady state timeout. */ +SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) { + cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ + cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ + cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ + cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ + cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ + cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ + cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ + cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ + cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ + cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ + cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ + cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ + cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ + cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ + cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ +#if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US) + cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ +#endif +}; + +/** HFXO core degeneration control. */ +SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) { + cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ + cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ + cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ + cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ +}; + +/** HFXO XI and XO pin fixed capacitor control. */ +SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) { + cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ + cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ + cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ + cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ +}; + +/** Oscillator precision modes. */ +SL_ENUM(CMU_Precision_TypeDef) { + cmuPrecisionDefault, /**< Default precision mode. */ + cmuPrecisionHigh, /**< High precision mode. */ +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + uint8_t gain; /**< Startup gain. */ + uint8_t capTune; /**< Internal capacitance tuning. */ + CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ + CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool highAmplitudeEn; /**< High amplitude enable. */ + bool agcEn; /**< AGC enable. */ + bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ + bool failDetEn; /**< Oscillator failure detection enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Lock register access. */ +} CMU_LFXOInit_TypeDef; + +/** Default LFXO initialization values for XTAL mode. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + 1, \ + 38, \ + cmuLfxoStartupDelay_4KCycles, \ + cmuLfxoOscMode_Crystal, \ + false, /* highAmplitudeEn */ \ + true, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external clock mode. */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_External, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external sine mode. */ +#define CMU_LFXOINIT_EXTERNAL_SINE \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_AcCoupledSine, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ + uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ + uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ + uint8_t coreBiasStartup; /**< Core bias startup current. */ + uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ + CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ + CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ + uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ + uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ + uint8_t coreBiasAna; /**< Core bias current. */ + bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ + CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool forceXo2GndAna; /**< Force XO pin to ground. */ + bool forceXi2GndAna; /**< Force XI pin to ground. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ +#if defined(HFXO_CTRL_EM23ONDEMAND) + bool em23OnDemand; /**< Enable deep sleep. */ +#endif + bool regLock; /**< Lock register access. */ +} CMU_HFXOInit_TypeDef; + +#if defined(HFXO_CTRL_EM23ONDEMAND) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// See [PM-2871] for details. +/** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) +// See [PM-5131] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG24 + * when high power PA is present and output dBm equal 20 dBm. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +// See [PM-5638] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG25 + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#else +/** + * Default configuration of fixed tuning capacitance on XO and XI. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both +#endif + +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } +#else +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_Both, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } +#endif + +#if defined(_HFXO_BUFOUTCTRL_MASK) + +/** Crystal sharing timeout start up timeout. */ +SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) { + startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */ + startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */ + startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */ + startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */ + startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */ + startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */ + startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */ + startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */ + startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */ + startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */ + startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */ + startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */ + startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */ + startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */ + startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */ + startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */ +}; + +/** Crystal sharing leader initialization structure. */ +typedef struct { + bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */ + CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */ +} CMU_BUFOUTLeaderInit_TypeDef; + +/** Default crystal sharing master initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \ + { \ + true, /* minimalStartupDelay */ \ + startupTimeout208Us, /* timeoutStartup */ \ + } +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/** PRS status select output signal. */ +SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) { + PRS_Status_select_0, /**< PRS status 0 output signal. */ + PRS_Status_select_1 /**< PRS status 1 output signal. */ +}; + +/** Crystal sharing follower initialization structure. */ +typedef struct { + CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */ + bool em23OnDemand; /**< Enable em23 on demand. */ + bool regLock; /**< Lock registers. */ +} CMU_CrystalSharingFollowerInit_TypeDef; + +/** Default crystal sharing follower initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \ + { \ + PRS_Status_select_0, /* prsStatusSelectOutput */ \ + true, /* em23OnDemand */ \ + false /* regLock */ \ + } +#endif + +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + CMU_Select_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ + bool ditherEn; /**< Enable dither functionality. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 76,800,000 Hz using HFXO as reference + * clock, M = 1919, N = 3839 + */ +#define CMU_DPLL_HFXO_TO_76_8MHZ \ + { \ + 76800000, /* Target frequency. */ \ + 3839, /* Factor N. */ \ + 1919, /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 80,000,000 Hz using HFXO as reference + * clock, M = 1919, N = 3999. + */ +#define CMU_DPLL_HFXO_TO_80MHZ \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * Default configurations for DPLL initialization. When using this macro + * you need to modify the N and M factor and the desired frequency to match + * the components placed on the board. + */ +#define CMU_DPLLINIT_DEFAULT \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +#if defined(USBPLL_PRESENT) +/** USB PLL initialization structure. */ +typedef struct { + CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */ + bool shuntRegEn; /**< Shunt regulator enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ +} CMU_USBPLL_Init_TypeDef; + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38 MHz. + */ +#define CMU_USBPLL_REFFREQ_38MHZ \ + { \ + cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38.4 MHz. + */ +#define CMU_USBPLL_REFFREQ_38_4MHZ \ + { \ + cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 39 MHz. + */ +#define CMU_USBPLL_REFFREQ_39MHZ \ + { \ + cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 40 MHz. + */ +#define CMU_USBPLL_REFFREQ_40MHZ \ + { \ + cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } +#endif + +#if defined(RFFPLL_PRESENT) +/** + * RFF PLL initialization structure. + * When using this structure you need to modify the X, Y and N factor + * and the desired host target frequency to match the components placed + * on the board (namely the RFFPLL reference clock). + * X, Y, N values for a 39MHz HFXO: + * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY + * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2) + */ +typedef struct { + uint32_t frequency; /**< Host target frequency. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ + uint8_t dividerY; /**< Divider Y for digital. */ + uint8_t dividerX; /**< Divider X for Radio. */ + uint8_t dividerN; /**< Feedback divider N. */ +} CMU_RFFPLL_Init_TypeDef; + +/** Radio frequency locked loop default initialization values. */ +#define CMU_RFFPLL_DEFAULT \ + { \ + 100000000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \ + _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \ + _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \ + } + +/** Radio frequency locked loop initialization values for 97.5MHz. */ +#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \ + { \ + 97500000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + 20U, /* Divider Y for digital. */ \ + 6U, /* Divider X for Radio. */ \ + 100U /* Feedback divider N. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, + CMU_Select_TypeDef reference); +void CMU_CalibrateConfig(uint32_t downCycles, + CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel); +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClkOutPinConfig(uint32_t clkno, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkdiv, + GPIO_Port_TypeDef port, + unsigned int pin); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, + CMU_ClkDiv_TypeDef div); +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +#endif +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, + CMU_Select_TypeDef ref); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#if defined(USBPLL_PRESENT) +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitUSBPLLLock(void); +#endif +#if defined(RFFPLL_PRESENT) +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitRFFPLLLock(void); +#endif +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); +#if defined(HFXO0_BUFOUT) +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +sl_status_t CMU_HFXOCTuneSet(uint32_t ctune); +uint32_t CMU_HFXOCTuneGet(void); +void CMU_HFXOCTuneDeltaSet(int32_t delta); +int32_t CMU_HFXOCTuneDeltaGet(void); +int32_t CMU_HFXOCTuneCurrentDeltaGet(void); +void CMU_HFXOCoreBiasCurrentCalibrate(void); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); +#if defined(PLFRCO_PRESENT) +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision); +#endif +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, + uint32_t val); +void CMU_UpdateWaitStates(uint32_t freq, int vscale); +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); + +#if defined(HFRCOEM23_PRESENT) +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +__STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + (void)clock; + (void)enable; +} +#endif + +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly + * @ref CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTART; +} + +/***************************************************************************//** + * @brief + * Stop calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTOP; +} + +/***************************************************************************//** + * @brief + * Unlock the DPLL. + * @note + * The HFRCODPLL oscillator is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { + } +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupt flags. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupt sources. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to + * enabling if such a pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupt sources. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Lock CMU register access in order to protect registers contents against + * unintended modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +__STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, + bool enable, + bool wait) +{ + (void)osc; + (void)enable; + (void)wait; +} + +/***************************************************************************//** + * @brief + * Unlock CMU register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Lock WDOG register access in order to protect registers contents against + * unintended modification. + * + * @note + * If locking the WDOG registers, they must be unlocked prior to using any + * emlib API functions modifying registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogLock(void) +{ + CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Unlock WDOG register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogUnlock(void) +{ + CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for USB PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitUSBPLLLock() +{ + while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) + != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { + /* Wait for USB PLL lock and ready */ + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for RFF PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitRFFPLLLock() +{ + while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) + != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { + /* Wait for RFF PLL lock and ready. */ + } +} +#endif + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Select register IDs for internal use. */ +#define CMU_NOSEL_REG 0 +#define CMU_HFCLKSEL_REG 1 +#define CMU_LFACLKSEL_REG 2 +#define CMU_LFBCLKSEL_REG 3 +#define CMU_LFCCLKSEL_REG 4 +#define CMU_LFECLKSEL_REG 5 +#define CMU_DBGCLKSEL_REG 6 +#define CMU_USBCCLKSEL_REG 7 +#define CMU_ADC0ASYNCSEL_REG 8 +#define CMU_ADC1ASYNCSEL_REG 9 +#define CMU_SDIOREFSEL_REG 10 +#define CMU_QSPI0REFSEL_REG 11 +#define CMU_USBRCLKSEL_REG 12 +#define CMU_PDMREFSEL_REG 13 + +#define CMU_SEL_REG_POS 0U +#define CMU_SEL_REG_MASK 0xfU + +/* Divisor/prescaler register IDs for internal use. */ +#define CMU_NODIV_REG 0 +#define CMU_NOPRESC_REG 0 +#define CMU_HFPRESC_REG 1 +#define CMU_HFCLKDIV_REG 1 +#define CMU_HFEXPPRESC_REG 2 +#define CMU_HFCLKLEPRESC_REG 3 +#define CMU_HFPERPRESC_REG 4 +#define CMU_HFPERCLKDIV_REG 4 +#define CMU_HFPERPRESCB_REG 5 +#define CMU_HFPERPRESCC_REG 6 +#define CMU_HFCOREPRESC_REG 7 +#define CMU_HFCORECLKDIV_REG 7 +#define CMU_LFAPRESC0_REG 8 +#define CMU_LFBPRESC0_REG 9 +#define CMU_LFEPRESC0_REG 10 +#define CMU_ADCASYNCDIV_REG 11 +#define CMU_HFBUSPRESC_REG 12 +#define CMU_HFCORECLKLEDIV_REG 13 + +#define CMU_PRESC_REG_POS 4U +#define CMU_DIV_REG_POS CMU_PRESC_REG_POS +#define CMU_PRESC_REG_MASK 0xfU +#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK + +/* Enable register IDs for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CTRL_EN_REG 1 +#define CMU_HFPERCLKDIV_EN_REG 1 +#define CMU_HFPERCLKEN0_EN_REG 2 +#define CMU_HFCORECLKEN0_EN_REG 3 +#define CMU_PDMREF_EN_REG 4 +#define CMU_HFBUSCLKEN0_EN_REG 5 +#define CMU_LFACLKEN0_EN_REG 6 +#define CMU_LFBCLKEN0_EN_REG 7 +#define CMU_LFCCLKEN0_EN_REG 8 +#define CMU_LFECLKEN0_EN_REG 9 +#define CMU_PCNT_EN_REG 10 +#define CMU_SDIOREF_EN_REG 11 +#define CMU_QSPI0REF_EN_REG 12 +#define CMU_QSPI1REF_EN_REG 13 +#define CMU_HFPERCLKEN1_EN_REG 14 +#define CMU_USBRCLK_EN_REG 15 + +#define CMU_EN_REG_POS 8U +#define CMU_EN_REG_MASK 0xfU + +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 12U +#define CMU_EN_BIT_MASK 0x1fU + +/* Clock branch bitfield positions, for internal use. */ +#define CMU_HF_CLK_BRANCH 0 +#define CMU_HFCORE_CLK_BRANCH 1 +#define CMU_HFPER_CLK_BRANCH 2 +#define CMU_HFPERB_CLK_BRANCH 3 +#define CMU_HFPERC_CLK_BRANCH 4 +#define CMU_HFBUS_CLK_BRANCH 5 +#define CMU_HFEXP_CLK_BRANCH 6 +#define CMU_DBG_CLK_BRANCH 7 +#define CMU_AUX_CLK_BRANCH 8 +#define CMU_RTC_CLK_BRANCH 9 +#define CMU_RTCC_CLK_BRANCH 10 +#define CMU_LETIMER0_CLK_BRANCH 11 +#define CMU_LETIMER1_CLK_BRANCH 12 +#define CMU_LEUART0_CLK_BRANCH 13 +#define CMU_LEUART1_CLK_BRANCH 14 +#define CMU_LFA_CLK_BRANCH 15 +#define CMU_LFB_CLK_BRANCH 16 +#define CMU_LFC_CLK_BRANCH 17 +#define CMU_LFE_CLK_BRANCH 18 +#define CMU_USBC_CLK_BRANCH 19 +#define CMU_USBLE_CLK_BRANCH 20 +#define CMU_LCDPRE_CLK_BRANCH 21 +#define CMU_LCD_CLK_BRANCH 22 +#define CMU_LESENSE_CLK_BRANCH 23 +#define CMU_CSEN_LF_CLK_BRANCH 24 +#define CMU_ADC0ASYNC_CLK_BRANCH 25 +#define CMU_ADC1ASYNC_CLK_BRANCH 26 +#define CMU_SDIOREF_CLK_BRANCH 27 +#define CMU_QSPI0REF_CLK_BRANCH 28 +#define CMU_USBR_CLK_BRANCH 29 +#define CMU_PDMREF_CLK_BRANCH 30 +#define CMU_HFLE_CLK_BRANCH 31 + +#define CMU_CLK_BRANCH_POS 17U +#define CMU_CLK_BRANCH_MASK 0x1fU + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL +#endif + +/* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 2 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define USBC_CLOCK_PRESENT +#endif +#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) +#define USBR_CLOCK_PRESENT +#endif +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock divisors. These values are valid for prescalers. */ +#define cmuClkDiv_1 1 /**< Divide clock by 1. */ +#define cmuClkDiv_2 2 /**< Divide clock by 2. */ +#define cmuClkDiv_4 4 /**< Divide clock by 4. */ +#define cmuClkDiv_8 8 /**< Divide clock by 8. */ +#define cmuClkDiv_16 16 /**< Divide clock by 16. */ +#define cmuClkDiv_32 32 /**< Divide clock by 32. */ +#define cmuClkDiv_64 64 /**< Divide clock by 64. */ +#define cmuClkDiv_128 128 /**< Divide clock by 128. */ +#define cmuClkDiv_256 256 /**< Divide clock by 256. */ +#define cmuClkDiv_512 512 /**< Divide clock by 512. */ +#define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ +#define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ +#define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ +#define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ +#define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ +#define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) +/** Clockprescaler configuration */ +typedef uint32_t CMU_ClkPresc_TypeDef; +#endif + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) { + cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ + cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ + cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ + cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ + cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ +#if defined(CMU_HFRCOCTRL_BAND_28MHZ) + cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ +#endif +}; +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) { + cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ + cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ + cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ + cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ + cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ +#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) + cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ +#endif +}; +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/** Universal serial high-frequency RC bands */ +SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) { + /** 24 MHz RC band. */ + cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, + /** 48 MHz RC band. */ + cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, +}; +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/** High-USHFRCO bands */ +SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) { + cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ + cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ + cmuUSHFRCOFreq_UserDefined = 0, +}; +/** USHFRCO minimum frequency */ +#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz +/** USHFRCO maximum frequency */ +#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz +#endif + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) { + cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_HFRCOCAL13_MASK) + cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL14_MASK) + cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL15_MASK) + cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL16_MASK) + cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ +#endif + cmuHFRCOFreq_UserDefined = 0, +}; + +/** HFRCO minimum frequency. */ +#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz +#if defined(_DEVINFO_HFRCOCAL16_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz +#elif defined(_DEVINFO_HFRCOCAL15_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz +#elif defined(_DEVINFO_HFRCOCAL14_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz +#elif defined(_DEVINFO_HFRCOCAL13_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz +#else +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz +#endif +#endif + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) { + cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ +#endif + cmuAUXHFRCOFreq_UserDefined = 0, +}; +/** AUXHFRCO minimum frequency. */ +#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz +#elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz +#else +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz +#endif +#endif + +/** Clock points in CMU. See CMU overview in the reference manual. */ +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* HF clock branch */ + /*******************/ + + /** High-frequency clock */ +#if defined(_CMU_CTRL_HFCLKDIV_MASK) \ + || defined(_CMU_HFPRESC_MASK) + cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Debug clock */ + cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** AUX clock */ + cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(_CMU_HFEXPPRESC_MASK) + /**********************/ + /* HF export sub-branch */ + /**********************/ + + /** Export clock */ + cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) +/**********************************/ +/* HF bus clock sub-branch */ +/**********************************/ + + /** High-frequency bus clock */ +#if defined(_CMU_HFBUSPRESC_MASK) + cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO) + /** Cryptography accelerator clock */ + cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO0) + /** Cryptography accelerator 0 clock */ + cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO1) + /** Cryptography accelerator 1 clock */ + cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_LDMA) + /** Direct-memory access controller clock */ + cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_QSPI0) + /** Quad SPI clock */ + cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPCRC) + /** General-purpose cyclic redundancy checksum clock */ + cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Low-energy clock divided down from HFCLK */ + cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFBUSCLKEN0_PRS) + /** Peripheral reflex system clock */ + cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* HF peripheral clock sub-branch */ + /**********************************/ + + /** High-frequency peripheral clock */ +#if defined(_CMU_HFPRESC_MASK) + cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCB_MASK) + /** Branch B figh-frequency peripheral clock */ + cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + /** Branch C figh-frequency peripheral clock */ + cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PDM) + /** PDM clock */ + cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF1) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART1) + /** Universal sync/async receiver/transmitter 1 clock */ + cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART2) + /** Universal sync/async receiver/transmitter 2 clock */ + cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_USART3) + /** Universal sync/async receiver/transmitter 3 clock */ + cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART4) + /** Universal sync/async receiver/transmitter 4 clock */ + cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART5) + /** Universal sync/async receiver/transmitter 5 clock */ + cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART0) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART0_MASK) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART1) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART1_MASK) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER0) + /** Timer 0 clock */ + cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER1) + /** Timer 1 clock */ + cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER2) + /** Timer 2 clock */ + cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER3) + /** Timer 3 clock */ + cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER4) + /** Timer 4 clock */ + cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER5) + /** Timer 5 clock */ + cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER6) + /** Timer 6 clock */ + cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER2) + /** Wide-timer 2 clock */ + cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER3) + /** Wide-timer 3 clock */ + cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CRYOTIMER) + /** CRYOtimer clock */ + cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP0) + /** Analog comparator 0 clock */ + cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP1) + /** Analog comparator 1 clock */ + cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP2) + /** Analog comparator 2 clock */ + cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP3) + /** Analog comparator 3 clock */ + cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PRS) + /** Peripheral-reflex system clock */ + cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_DAC0) + /** Digital-to-analog converter 0 clock */ + cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_IDAC0) + /** Current digital-to-analog converter 0 clock */ + cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VCMP) + /** Voltage comparator clock */ + cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ADC0) + /** Analog-to-digital converter 0 clock */ + cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ADC1) + /** Analog-to-digital converter 1 clock */ + cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_I2C0) + /** I2C 0 clock */ + cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C1) + /** I2C 1 clock */ + cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C2) + /** I2C 2 clock */ + cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TRNG0) + /** True random number generator clock */ + cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN0_MASK) + /** Controller Area Network 0 clock */ + cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN1_MASK) + /** Controller Area Network 1 clock. */ + cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /**********************/ + /* HF core sub-branch */ + /**********************/ + + /** Core clock */ + cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFCORECLKEN0_AES) + /** Advanced encryption standard accelerator clock */ + cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_DMA) + /** Direct memory access controller clock */ + cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_LE) + /** Low-energy clock divided down from HFCORECLK */ + cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_EBI) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_ETH_MASK) + /** Ethernet clock */ + cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) + /** SDIO clock */ + cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(USBC_CLOCK_PRESENT) + /** USB Core clock */ + cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined (USBR_CLOCK_PRESENT) + /** USB Rate clock */ + cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) + | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFBUSCLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF A branch */ + /***************/ + + /** Low-frequency A clock */ + cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFACLKEN0_RTC) + /** Real time counter clock */ + cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER0) + /** Low-energy timer 0 clock */ + cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER1) + /** Low-energy timer 1 clock */ + cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LCD) + /** Liquid crystal display, pre FDIV clock */ + cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Liquid crystal display clock. Note that FDIV prescaler + * must be set by special API. */ + cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) + | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT0CLKEN) + /** Pulse counter 0 clock */ + cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT1CLKEN) + /** Pulse counter 1 clock */ + cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT2CLKEN) + /** Pulse counter 2 clock */ + cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined(CMU_LFACLKEN0_LESENSE) + /** LESENSE clock */ + cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) + | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF B branch */ + /***************/ + + /** Low-frequency B clock */ + cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFBCLKEN0_LEUART0) + /** Low-energy universal asynchronous receiver/transmitter 0 clock */ + cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_CSEN) + /** Capacitive Sense LF clock */ + cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_LEUART1) + /** Low-energy universal asynchronous receiver/transmitter 1 clock */ + cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_SYSTICK) + /** Cortex SYSTICK LF clock */ + cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_LFCCLKEN0_MASK) + /***************/ + /* LF C branch */ + /***************/ + + /** Low-frequency C clock */ + cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFCCLKEN0_USBLE) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_LFCCLKEN0_USB) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + /***************/ + /* LF E branch */ + /***************/ + + /** Low-frequency E clock */ + cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Real-time counter and calendar clock */ +#if defined (CMU_LFECLKEN0_RTCC) + cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* Asynchronous peripheral clocks */ + /**********************************/ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + /** ADC0 asynchronous clock */ + cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + /** ADC1 asynchronous clock */ + cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) + /** SDIO reference clock */ + cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) + /** QSPI0 reference clock */ + cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) + | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) + | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) + /** PDM reference clock */ + cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +}; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Clock_TypeDef member */ +#define cmuClock_CORELE cmuClock_HFLE +/** @endcond */ + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ + cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ + cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ + cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuOsc_CLKIN0, /**< External oscillator. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +/** Oscillator modes. */ +SL_ENUM(CMU_OscMode_TypeDef) { + cmuOscMode_Crystal, /**< Crystal oscillator. */ + cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ + cmuOscMode_External, /**< External digital clock. */ +}; + +/** Selectable clock sources. */ +SL_ENUM(CMU_Select_TypeDef) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ + cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */ + cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko). */ +#if defined(CMU_STATUS_USHFRCOENS) + cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ +#endif +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ +#endif +#if defined(CMU_HFXOCTRL_HFXOX2EN) + cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuSelect_CLKIN0, /**< External clock input. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +#if defined(CMU_HFCORECLKEN0_LE) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Select_TypeDef member */ +#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE +/** @endcond */ +#endif + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/** HFXO tuning modes */ +SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) { + cmuHFXOTuningMode_Auto = 0, + cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ + cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ + | CMU_CMD_HFXOSHUNTOPTSTART, +#endif +}; +#endif + +#if defined(_CMU_CTRL_LFXOBOOST_MASK) +/** LFXO Boost values. */ +SL_ENUM(CMU_LFXOBoost_TypeDef) { + cmuLfxoBoost70 = 0x0, + cmuLfxoBoost100 = 0x2, +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + cmuLfxoBoost70Reduced = 0x1, + cmuLfxoBoost100Reduced = 0x3, +#endif +}; +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL reference clock selector. */ +SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) { + cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ + cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ + cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ +}; + +/** DPLL reference clock edge detect selector. */ +SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) { + cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ +}; +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_CMU_LFXOCTRL_MASK) + uint8_t ctune; /**< CTUNE (load capacitance) value */ + uint8_t gain; /**< Gain/max startup margin */ +#else + CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ +#endif + uint8_t timeout; /**< Startup delay */ + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_LFXOInit_TypeDef; + +#if defined(_CMU_LFXOCTRL_MASK) +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ + _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ + _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* No CTUNE value needed */ \ + 0, /* No LFXO startup gain */ \ + _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#else +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ + cmuOscMode_External, \ + } +#endif + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#elif defined(_CMU_HFXOCTRL_MASK) + bool lowPowerMode; /**< Enable low-power mode */ + bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint8_t regIshSteadyState; /**< Shunt steady-state current */ + uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t thresholdPeakDetect; /**< Peak detection threshold */ + uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#else + uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ + uint8_t timeout; /**< Startup delay */ + bool glitchDetector; /**< Enable/disable glitch detector */ +#endif + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_HFXOInit_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) +/** Default HFXO init. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_External, \ + } +#elif defined(_CMU_HFXOCTRL_MASK) +/** + * Default HFXO initialization values for Platform 2 devices, which contain a + * separate HFXOCTRL register. + */ +#if defined(_EFR_DEVICE) +#define CMU_HFXOINIT_DEFAULT \ + { \ + false, /* Low-noise mode for EFR32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default Shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state XO core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#else /* EFM32 device */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + true, /* Low-power mode for EFM32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#endif /* _EFR_DEVICE */ +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + true, /* Low-power mode */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + 0, /* Startup CTUNE=0 recommended for external clock */ \ + 0, /* Steady CTUNE=0 recommended for external clock */ \ + 0xA, /* Default shunt steady-state current */ \ + 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ + 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0x0, /* Peak-detect not recommended for external clock usage */ \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ + cmuOscMode_External, \ + } +#else /* _CMU_HFXOCTRL_MASK */ +/** + * Default HFXO initialization values for Platform 1 devices. + */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ + _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default HFXO initialization for external clock */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* Minimal HFXO boost, 50% */ \ + _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#endif /* _CMU_HFXOCTRL_MASK */ + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + uint8_t ssInterval; /**< Spread spectrum update interval. */ + uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ + CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + 0, /* No spread spectrum clocking. */ \ + 0, /* No spread spectrum clocking. */ \ + cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true /* Enable automatic lock recovery. */ \ + } +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); + +#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); +#endif + +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel); +#endif + +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); + +#if defined(_SILICON_LABS_32B_SERIES_1) +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); +#endif + +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); + +#if defined(CMU_OSCENCMD_DPLLEN) +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#endif +void CMU_FreezeEnable(bool enable); + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); + +#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); +#endif + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +uint32_t CMU_HFRCOStartupDelayGet(void); +void CMU_HFRCOStartupDelaySet(uint32_t delay); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); +uint32_t CMU_USHFRCOFreqGet(void); +#endif + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel); +#endif + +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); + +uint32_t CMU_LCDClkFDIVGet(void); +void CMU_LCDClkFDIVSet(uint32_t div); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); + +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait); +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); +bool CMU_PCNTClockExternalGet(unsigned int instance); +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); +uint32_t CMU_USHFRCOFreqGet(void); +#endif +void CMU_UpdateWaitStates(uint32_t freq, int vscale); + +#if defined(CMU_CALCTRL_CONT) +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} +#endif + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after CMU_CalibrateConfig() and possibly + * CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CMD = CMU_CMD_CALSTART; +} + +#if defined(CMU_CMD_CALSTOP) +/***************************************************************************//** + * @brief + * Stop the calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CMD = CMU_CMD_CALSTOP; +} +#endif + +/***************************************************************************//** + * @brief + * Convert divider to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] div + * An unscaled divider. + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) +{ + uint32_t log2; + + /* Fixed 2^n prescalers take argument of 32768 or less. */ + EFM_ASSERT((div > 0U) && (div <= 32768U)); + + /* Count leading zeroes and "reverse" result */ + log2 = 31UL - __CLZ(div); + + return log2; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/***************************************************************************//** + * @brief + * Unlock DPLL. + * @note + * HFRCO is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; +} +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupts. + * + * @note + * Depending on use case, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling + * if the pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupts. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * This function does not clear event bits. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IFS = flags; +} + +/***************************************************************************//** + * @brief + * Lock the CMU to protect some of its registers against unintended + * modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the CMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if !defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Convert prescaler divider to a logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] presc + * Prescaler value used to set the frequency divider. The divider is equal to + * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be + * equal to (divider - 1). + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) +{ + uint32_t log2; + + /* Integer prescalers take argument less than 32768. */ + EFM_ASSERT(presc < 32768U); + + /* Count leading zeroes and "reverse" result. Consider divider value to get + * exponent n from 2^n, so ('presc' +1). */ + log2 = 31UL - __CLZ(presc + (uint32_t) 1); + + /* Check that prescaler is a 2^n number. */ + EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); + + return log2; +} +#endif // !defined(_SILICON_LABS_32B_SERIES_0) + +/** @} (end addtogroup cmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CMU_PRESENT) */ +#endif /* EM_CMU_H */ diff --git a/Libs/platform/emlib/inc/em_cmu_compat.h b/Libs/platform/emlib/inc/em_cmu_compat.h new file mode 100644 index 0000000..1585ec8 --- /dev/null +++ b/Libs/platform/emlib/inc/em_cmu_compat.h @@ -0,0 +1,184 @@ +/***************************************************************************//** + * @file + * @brief CMU Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CMU_COMPAT_H +#define EM_CMU_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define CMU_IF_CALRDYIF CMU_IF_CALRDY +#define _CMU_IF_CALRDYIF_SHIFT _CMU_IF_CALRDY_SHIFT +#define _CMU_IF_CALRDYIF_MASK _CMU_IF_CALRDY_MASK +#define _CMU_IF_CALRDYIF_DEFAULT _CMU_IF_CALRDY_DEFAULT +#define CMU_IF_CALRDYIF_DEFAULT CMU_IF_CALRDY_DEFAULT + +#define CMU_IF_CALOFIF CMU_IF_CALOF +#define _CMU_IF_CALOFIF_SHIFT _CMU_IF_CALOF_SHIFT +#define _CMU_IF_CALOFIF_MASK _CMU_IF_CALOF_MASK +#define _CMU_IF_CALOFIF_DEFAULT _CMU_IF_CALOF_DEFAULT +#define CMU_IF_CALOFIF_DEFAULT CMU_IF_CALOF_DEFAULT + +#define CMU_IEN_CALRDYIEN CMU_IEN_CALRDY +#define _CMU_IEN_CALRDYIEN_SHIFT _CMU_IEN_CALRDY_SHIFT +#define _CMU_IEN_CALRDYIEN_MASK _CMU_IEN_CALRDY_MASK +#define _CMU_IEN_CALRDYIEN_DEFAULT _CMU_IEN_CALRDY_DEFAULT +#define CMU_IEN_CALRDYIEN_DEFAULT CMU_IEN_CALRDY_DEFAULT + +#define CMU_IEN_CALOFIEN CMU_IEN_CALOF +#define _CMU_IEN_CALOFIEN_SHIFT _CMU_IEN_CALOF_SHIFT +#define _CMU_IEN_CALOFIEN_MASK _CMU_IEN_CALOF_MASK +#define _CMU_IEN_CALOFIEN_DEFAULT _CMU_IEN_CALOF_DEFAULT +#define CMU_IEN_CALOFIEN_DEFAULT CMU_IEN_CALOF_DEFAULT + + +#define HFRCO_IF_RDYIF HFRCO_IF_RDY +#define _HFRCO_IF_RDYIF_SHIFT _HFRCO_IF_RDY_SHIFT +#define _HFRCO_IF_RDYIF_MASK _HFRCO_IF_RDY_MASK +#define _HFRCO_IF_RDYIF_DEFAULT _HFRCO_IF_RDY_DEFAULT +#define HFRCO_IF_RDYIF_DEFAULT HFRCO_IF_RDY_DEFAULT + +#define HFRCO_IEN_RDYIEN HFRCO_IEN_RDY +#define _HFRCO_IEN_RDYIEN_SHIFT _HFRCO_IEN_RDY_SHIFT +#define _HFRCO_IEN_RDYIEN_MASK _HFRCO_IEN_RDY_MASK +#define _HFRCO_IEN_RDYIEN_DEFAULT _HFRCO_IEN_RDY_DEFAULT +#define HFRCO_IEN_RDYIEN_DEFAULT HFRCO_IEN_RDY_DEFAULT + + +#define LFRCO_IF_RDYIF LFRCO_IF_RDY +#define _LFRCO_IF_RDYIF_SHIFT _LFRCO_IF_RDY_SHIFT +#define _LFRCO_IF_RDYIF_MASK _LFRCO_IF_RDY_MASK +#define _LFRCO_IF_RDYIF_DEFAULT _LFRCO_IF_RDY_DEFAULT +#define LFRCO_IF_RDYIF_DEFAULT LFRCO_IF_RDY_DEFAULT + +#define LFRCO_IF_POSEDGEIF LFRCO_IF_POSEDGE +#define _LFRCO_IF_POSEDGEIF_SHIFT _LFRCO_IF_POSEDGE_SHIFT +#define _LFRCO_IF_POSEDGEIF_MASK _LFRCO_IF_POSEDGE_MASK +#define _LFRCO_IF_POSEDGEIF_DEFAULT _LFRCO_IF_POSEDGE_DEFAULT +#define LFRCO_IF_POSEDGEIF_DEFAULT LFRCO_IF_POSEDGE_DEFAULT + +#define LFRCO_IF_NEGEDGEIF LFRCO_IF_NEGEDGE +#define _LFRCO_IF_NEGEDGEIF_SHIFT _LFRCO_IF_NEGEDGE_SHIFT +#define _LFRCO_IF_NEGEDGEIF_MASK _LFRCO_IF_NEGEDGE_MASK +#define _LFRCO_IF_NEGEDGEIF_DEFAULT _LFRCO_IF_NEGEDGE_DEFAULT +#define LFRCO_IF_NEGEDGEIF_DEFAULT LFRCO_IF_NEGEDGE_DEFAULT + +#define LFRCO_IF_TCDONEIF LFRCO_IF_TCDONE +#define _LFRCO_IF_TCDONEIF_SHIFT _LFRCO_IF_TCDONE_SHIFT +#define _LFRCO_IF_TCDONEIF_MASK _LFRCO_IF_TCDONE_MASK +#define _LFRCO_IF_TCDONEIF_DEFAULT _LFRCO_IF_TCDONE_DEFAULT +#define LFRCO_IF_TCDONEIF_DEFAULT LFRCO_IF_TCDONE_DEFAULT + +#define LFRCO_IF_CALDONEIF LFRCO_IF_CALDONE +#define _LFRCO_IF_CALDONEIF_SHIFT _LFRCO_IF_CALDONE_SHIFT +#define _LFRCO_IF_CALDONEIF_MASK _LFRCO_IF_CALDONE_MASK +#define _LFRCO_IF_CALDONEIF_DEFAULT _LFRCO_IF_CALDONE_DEFAULT +#define LFRCO_IF_CALDONEIF_DEFAULT LFRCO_IF_CALDONE_DEFAULT + +#define LFRCO_IF_TEMPCHANGEIF LFRCO_IF_TEMPCHANGE +#define _LFRCO_IF_TEMPCHANGEIF_SHIFT _LFRCO_IF_TEMPCHANGE_SHIFT +#define _LFRCO_IF_TEMPCHANGEIF_MASK _LFRCO_IF_TEMPCHANGE_MASK +#define _LFRCO_IF_TEMPCHANGEIF_DEFAULT _LFRCO_IF_TEMPCHANGE_DEFAULT +#define LFRCO_IF_TEMPCHANGEIF_DEFAULT LFRCO_IF_TEMPCHANGE_DEFAULT + +#define LFRCO_IF_SCHEDERRIF LFRCO_IF_SCHEDERR +#define _LFRCO_IF_SCHEDERRIF_SHIFT _LFRCO_IF_SCHEDERR_SHIFT +#define _LFRCO_IF_SCHEDERRIF_MASK _LFRCO_IF_SCHEDERR_MASK +#define _LFRCO_IF_SCHEDERRIF_DEFAULT _LFRCO_IF_SCHEDERR_DEFAULT +#define LFRCO_IF_SCHEDERRIF_DEFAULT LFRCO_IF_SCHEDERR_DEFAULT + +#define LFRCO_IF_TCOORIF LFRCO_IF_TCOOR +#define _LFRCO_IF_TCOORIF_SHIFT _LFRCO_IF_TCOOR_SHIFT +#define _LFRCO_IF_TCOORIF_MASK _LFRCO_IF_TCOOR_MASK +#define _LFRCO_IF_TCOORIF_DEFAULT _LFRCO_IF_TCOOR_DEFAULT +#define LFRCO_IF_TCOORIF_DEFAULT LFRCO_IF_TCOOR_DEFAULT + +#define LFRCO_IF_CALOORIF LFRCO_IF_CALOOR +#define _LFRCO_IF_CALOORIF_SHIFT _LFRCO_IF_CALOOR_SHIFT +#define _LFRCO_IF_CALOORIF_MASK _LFRCO_IF_CALOOR_MASK +#define _LFRCO_IF_CALOORIF_DEFAULT _LFRCO_IF_CALOOR_DEFAULT +#define LFRCO_IF_CALOORIF_DEFAULT LFRCO_IF_CALOOR_DEFAULT + +#define LFRCO_IEN_RDYIEN LFRCO_IEN_RDY +#define _LFRCO_IEN_RDYIEN_SHIFT _LFRCO_IEN_RDY_SHIFT +#define _LFRCO_IEN_RDYIEN_MASK _LFRCO_IEN_RDY_MASK +#define _LFRCO_IEN_RDYIEN_DEFAULT _LFRCO_IEN_RDY_DEFAULT +#define LFRCO_IEN_RDYIEN_DEFAULT LFRCO_IEN_RDY_DEFAULT + +#define LFRCO_IEN_POSEDGEIEN LFRCO_IEN_POSEDGE +#define _LFRCO_IEN_POSEDGEIEN_SHIFT _LFRCO_IEN_POSEDGE_SHIFT +#define _LFRCO_IEN_POSEDGEIEN_MASK _LFRCO_IEN_POSEDGE_MASK +#define _LFRCO_IEN_POSEDGEIEN_DEFAULT _LFRCO_IEN_POSEDGE_DEFAULT +#define LFRCO_IEN_POSEDGEIEN_DEFAULT LFRCO_IEN_POSEDGE_DEFAULT + +#define LFRCO_IEN_NEGEDGEIEN LFRCO_IEN_NEGEDGE +#define _LFRCO_IEN_NEGEDGEIEN_SHIFT _LFRCO_IEN_NEGEDGE_SHIFT +#define _LFRCO_IEN_NEGEDGEIEN_MASK _LFRCO_IEN_NEGEDGE_MASK +#define _LFRCO_IEN_NEGEDGEIEN_DEFAULT _LFRCO_IEN_NEGEDGE_DEFAULT +#define LFRCO_IEN_NEGEDGEIEN_DEFAULT LFRCO_IEN_NEGEDGE_DEFAULT + +#define LFRCO_IEN_TCDONEIEN LFRCO_IEN_TCDONE +#define _LFRCO_IEN_TCDONEIEN_SHIFT _LFRCO_IEN_TCDONE_SHIFT +#define _LFRCO_IEN_TCDONEIEN_MASK _LFRCO_IEN_TCDONE_MASK +#define _LFRCO_IEN_TCDONEIEN_DEFAULT _LFRCO_IEN_TCDONE_DEFAULT +#define LFRCO_IEN_TCDONEIEN_DEFAULT LFRCO_IEN_TCDONE_DEFAULT + +#define LFRCO_IEN_CALDONEIEN LFRCO_IEN_CALDONE +#define _LFRCO_IEN_CALDONEIEN_SHIFT _LFRCO_IEN_CALDONE_SHIFT +#define _LFRCO_IEN_CALDONEIEN_MASK _LFRCO_IEN_CALDONE_MASK +#define _LFRCO_IEN_CALDONEIEN_DEFAULT _LFRCO_IEN_CALDONE_DEFAULT +#define LFRCO_IEN_CALDONEIEN_DEFAULT LFRCO_IEN_CALDONE_DEFAULT + +#define LFRCO_IEN_TEMPCHANGEIEN LFRCO_IEN_TEMPCHANGE +#define _LFRCO_IEN_TEMPCHANGEIEN_SHIFT _LFRCO_IEN_TEMPCHANGE_SHIFT +#define _LFRCO_IEN_TEMPCHANGEIEN_MASK _LFRCO_IEN_TEMPCHANGE_MASK +#define _LFRCO_IEN_TEMPCHANGEIEN_DEFAULT _LFRCO_IEN_TEMPCHANGE_DEFAULT +#define LFRCO_IEN_TEMPCHANGEIEN_DEFAULT LFRCO_IEN_TEMPCHANGE_DEFAULT + +#define LFRCO_IEN_SCHEDERRIEN LFRCO_IEN_SCHEDERR +#define _LFRCO_IEN_SCHEDERRIEN_SHIFT _LFRCO_IEN_SCHEDERR_SHIFT +#define _LFRCO_IEN_SCHEDERRIEN_MASK _LFRCO_IEN_SCHEDERR_MASK +#define _LFRCO_IEN_SCHEDERRIEN_DEFAULT _LFRCO_IEN_SCHEDERR_DEFAULT +#define LFRCO_IEN_SCHEDERRIEN_DEFAULT LFRCO_IEN_SCHEDERR_DEFAULT + +#define LFRCO_IEN_TCOORIEN LFRCO_IEN_TCOOR +#define _LFRCO_IEN_TCOORIEN_SHIFT _LFRCO_IEN_TCOOR_SHIFT +#define _LFRCO_IEN_TCOORIEN_MASK _LFRCO_IEN_TCOOR_MASK +#define _LFRCO_IEN_TCOORIEN_DEFAULT _LFRCO_IEN_TCOOR_DEFAULT +#define LFRCO_IEN_TCOORIEN_DEFAULT LFRCO_IEN_TCOOR_DEFAULT + +#define LFRCO_IEN_CALOORIEN LFRCO_IEN_CALOOR +#define _LFRCO_IEN_CALOORIEN_SHIFT _LFRCO_IEN_CALOOR_SHIFT +#define _LFRCO_IEN_CALOORIEN_MASK _LFRCO_IEN_CALOOR_MASK +#define _LFRCO_IEN_CALOORIEN_DEFAULT _LFRCO_IEN_CALOOR_DEFAULT +#define LFRCO_IEN_CALOORIEN_DEFAULT LFRCO_IEN_CALOOR_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ + +#endif diff --git a/Libs/platform/emlib/inc/em_common.h b/Libs/platform/emlib/inc/em_common.h new file mode 100644 index 0000000..cf67370 --- /dev/null +++ b/Libs/platform/emlib/inc/em_common.h @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_COMMON_H +#define EM_COMMON_H + +#include "em_device.h" +#include "sl_common.h" + +#endif /* EM_COMMON_H */ diff --git a/Libs/platform/emlib/inc/em_core.h b/Libs/platform/emlib/inc/em_core.h new file mode 100644 index 0000000..b292952 --- /dev/null +++ b/Libs/platform/emlib/inc/em_core.h @@ -0,0 +1,174 @@ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Device Specific) + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CORE_H +#define EM_CORE_H + +#include "em_device.h" +#include "em_core_generic.h" +#include "sl_common.h" + +/***************************************************************************//** + * @addtogroup core + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Number of words in a NVIC mask set. */ +#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) + +/** Number of entries in a default interrupt vector table. */ +#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) + +/** Highest priority for core interrupt. */ +#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 + +/** Default priority for core interrupt. */ +#define CORE_INTERRUPT_DEFAULT_PRIORITY 5 + +/** Lowest priority for core interrupt. */ +#define CORE_INTERRUPT_LOWEST_PRIORITY 7 + +// Compile time sanity check. +#if (CORE_NVIC_REG_WORDS > 3) +#error "em_core: Unexpected NVIC external interrupt count." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +// +// NVIC mask section macro API. +// + +/** Allocate storage for NVIC interrupt masks for use by + * CORE_ENTER/EXIT_NVIC() macros. */ +#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState + +/** Allocate storage for NVIC interrupt masks. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x + +/** Allocate storage for and zero initialize NVIC interrupt mask. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } + +/** NVIC mask style interrupt disable. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable. */ +#define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) + +/** NVIC mask style interrupt enable. + * @param[in] mask + * Mask specifying which NVIC interrupts to enable. */ +#define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) + +/** Convenience macro for implementing a NVIC mask section. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable within the section. + * @param[in] yourcode + * The code for the section. */ +#define CORE_NVIC_SECTION(mask, yourcode) \ + { \ + CORE_DECLARE_NVIC_STATE; \ + CORE_ENTER_NVIC(mask); \ + { \ + yourcode \ + } \ + CORE_EXIT_NVIC(); \ + } + +/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. + * @param[in] disable + * Mask specifying which NVIC interrupts to disable within the section. */ +#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) + +/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. */ +#define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) + +/** NVIC maks style yield. + * @param[in] enable + * Mask specifying which NVIC interrupts to briefly enable. */ +#define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Storage for NVIC interrupt masks. */ +typedef struct { + uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ +} CORE_nvicMask_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool CORE_IrqIsBlocked(IRQn_Type irqN) SL_DEPRECATED_API_SDK_2024_6; + +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) SL_DEPRECATED_API_SDK_2024_6; +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) SL_DEPRECATED_API_SDK_2024_6; + +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable) SL_DEPRECATED_API_SDK_2024_6; +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) SL_DEPRECATED_API_SDK_2024_6; +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) SL_DEPRECATED_API_SDK_2024_6; +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) SL_DEPRECATED_API_SDK_2024_6; +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) SL_DEPRECATED_API_SDK_2024_6; +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) SL_DEPRECATED_API_SDK_2024_6; +bool CORE_NvicIRQDisabled(IRQn_Type irqN) SL_DEPRECATED_API_SDK_2024_6; + +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) SL_DEPRECATED_API_SDK_2024_6; +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) SL_DEPRECATED_API_SDK_2024_6; +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup core) */ + +#endif /* EM_CORE_H */ diff --git a/Libs/platform/emlib/inc/em_core_generic.h b/Libs/platform/emlib/inc/em_core_generic.h new file mode 100644 index 0000000..28b2a15 --- /dev/null +++ b/Libs/platform/emlib/inc/em_core_generic.h @@ -0,0 +1,36 @@ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_GENERIC_H +#define EM_CORE_GENERIC_H + +#include "sl_core.h" + +#endif /* EM_CORE_GENERIC_H */ diff --git a/Libs/platform/emlib/inc/em_dbg.h b/Libs/platform/emlib/inc/em_dbg.h new file mode 100644 index 0000000..ae8c55c --- /dev/null +++ b/Libs/platform/emlib/inc/em_dbg.h @@ -0,0 +1,130 @@ +/***************************************************************************//** + * @file + * @brief Debug (DBG) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_DBG_H +#define EM_DBG_H + +#include +#include "em_device.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dbg + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Lock modes */ +typedef enum { + dbgLockModeAllowErase = 1UL, /**< Lock debug access. */ +#if !defined(_SILICON_LABS_32B_SERIES_0) + dbgLockModePermanent = 2UL /**< Lock debug access permanently. */ +#endif +} DBG_LockMode_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWCLKPEN) \ + || defined(GPIO_ROUTEPEN_SWCLKTCKPEN) \ + || defined(GPIO_DBGROUTEPEN_SWCLKTCKPEN) +/***************************************************************************//** + * @brief + * Check if a debugger is connected (and debug session activated). + * + * @details + * Used to make run-time decisions depending on whether or not a debug session + * has been active since last reset, i.e., using a debug probe or similar. In + * some cases, special handling is required in that scenario. + * + * @return + * True if a debug session is active since last reset, otherwise false. + ******************************************************************************/ +__STATIC_INLINE bool DBG_Connected(void) +{ + return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false; +} +#endif + +#if defined(GPIO_ROUTE_SWOPEN) \ + || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +void DBG_SWOEnable(unsigned int location); +#endif + +#if defined (EMU_CTRL_EM2DBGEN) +/***************************************************************************//** + * @brief + * Enable or disable debug support while in EM2 mode. + * + * @warning + * Disabling debug support in EM2 will reduce current consumption with 1-2 uA, + * but some debuggers will have problems regaining control over a device which + * is in EM2 and has debug support disabled. + * + * To remedy this, set the WSTK switch next to the battery holder to USB + * (powers down the EFR). Execute Simplicity Commander with command line + * parameters: + * "./commander.exe device recover" + * and then immediately move the switch to the AEM position. An additional + * "./commander.exe device masserase" + * command completes the recovery procedure. + * + * @param[in] enable + * Boolean true enables EM2 debug support, false disables. + ******************************************************************************/ +__STATIC_INLINE void DBG_EM2DebugEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; + } +} +#endif + +/** @} (end addtogroup dbg) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ + +#endif /* EM_DBG_H */ diff --git a/Libs/platform/emlib/inc/em_emu.h b/Libs/platform/emlib/inc/em_emu.h new file mode 100644 index 0000000..b205c0c --- /dev/null +++ b/Libs/platform/emlib/inc/em_emu.h @@ -0,0 +1,1831 @@ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EMU_H +#define EM_EMU_H + +#include "em_device.h" +#include "sl_status.h" +#if defined(EMU_PRESENT) + +#include +#include "em_bus.h" +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) +/** Voltage scaling present */ +#define EMU_VSCALE_PRESENT +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +/** Voltage scaling for EM01 present */ +#define EMU_VSCALE_EM01_PRESENT +#endif +#endif + +#if defined(_EMU_DCDCCTRL_MASK) +/** DC-DC buck converter present */ +#define EMU_SERIES1_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC buck converter present */ +#define EMU_SERIES2_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC boost converter present */ +#define EMU_SERIES2_DCDC_BOOST_PRESENT +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_EMU_EM4CONF_OSC_MASK) +/** EM4 duty oscillator. */ +typedef enum { + /** Select ULFRCO as duty oscillator in EM4. */ + emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, + /** Select LFXO as duty oscillator in EM4. */ + emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, + /** Select LFRCO as duty oscillator in EM4. */ + emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO +} EMU_EM4Osc_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PROBE_MASK) +/** Backup Power Voltage Probe types. */ +typedef enum { + /** Disable voltage probe. */ + emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, + /** Connect probe to VDD_DREG. */ + emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, + /** Connect probe to BU_IN. */ + emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, + /** Connect probe to BU_OUT. */ + emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT +} EMU_Probe_TypeDef; +#endif + +#if defined(_EMU_PWRCONF_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, +} EMU_Resistor_TypeDef; +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain power connection. */ +typedef enum { + /** No connection between main and backup power. */ + emuPower_None = EMU_BUINACT_PWRCON_NONE, + /** Main power and backup power connected through diode, + allowing current from backup to main only. */ + emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, + /** Main power and backup power connected through diode, + allowing current from main to backup only. */ + emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, + /** Main power and backup power connected without diode. */ + emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, +} EMU_Power_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/** Backup Power Domain power connection configuration when not in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, +} EMU_BUBuInactPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/** Backup Power Domain power connection configuration in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, +} EMU_BUBuActPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, +} EMU_BUPwrRes_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/** Resistance between backup domain power supply and BU_VOUT. */ +typedef enum { + /** BU_VOUT is not connected. */ + emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, + /** Enable weak switch. */ + emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, + /** Enable medium switch. */ + emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, + /** Enable strong switch. */ + emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, +} EMU_BUVoutRes_TypeDef; +#endif + +/** BOD threshold setting selector, active or inactive mode. */ +typedef enum { + /** Configure BOD threshold for active mode. */ + emuBODMode_Active, + /** Configure BOD threshold for inactive mode. */ + emuBODMode_Inactive, +} EMU_BODMode_TypeDef; + +/** EM4 modes. */ +typedef enum { + /** EM4 Shutoff. */ + emuEM4Shutoff = 0, + /** EM4 Hibernate. */ + emuEM4Hibernate = 1, +} EMU_EM4State_TypeDef; + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/** EM4 Pin Retention Type. */ +typedef enum { + /** No Retention: Pads enter reset state when entering EM4. */ + emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, + /** Retention through EM4: Pads enter reset state when exiting EM4. */ + emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, + /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to + release pins from retention after EM4 wakeup. */ + emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, +} EMU_EM4PinRetention_TypeDef; +#endif + +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +/** HDREG Stop Gear Max Current Type. */ +typedef enum { + /** HDREG current limit is 4mA. */ + emuHdregStopGearILmt4mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA, + /** HDREG current limit is 8mA. */ + emuHdregStopGearILmt8mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA, + /** HDREG current limit is 12mA. */ + emuHdregStopGearILmt12mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA, + /** HDREG current limit is 16mA. */ + emuHdregStopGearILmt16mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA, + /** HDREG current limit is 24mA. */ + emuHdregStopGearILmt24mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA, + /** HDREG current limit is 48mA. */ + emuHdregStopGearILmt48mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA, + /** HDREG current limit is 64mA. */ + emuHdregStopGearILmt64mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA, + /** HDREG current limit is 64mA. */ + emuHdregStopGearILmtMax = _EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX, +} EMU_HdregStopGearILmt_TypeDef; +#endif + +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ +typedef enum { + /** DCDC is connected to DVDD. */ + emuPowerConfig_DcdcToDvdd, +} EMU_PowerConfig_TypeDef; + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC operating modes. */ +typedef enum { + /** DCDC regulator bypass. */ + emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, + /** DCDC low-noise mode. */ + emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, +#if defined(_EMU_DCDCLPEM01CFG_MASK) + /** DCDC low-power mode. */ + emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, +#endif +} EMU_DcdcMode_TypeDef; + +/** DCDC operating modes in EM2 or EM3. */ +typedef enum { + /** DCDC mode is low power. */ + emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER, + /** DCDC mode is according to DCDCMODE field. */ + emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW, +} EMU_DcdcModeEM23_TypeDef; + +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC conduction modes. */ +typedef enum { + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + for EFR32 when its radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + +#if defined(_EMU_PWRCTRL_MASK) +/** DCDC to DVDD mode analog peripheral power supply select. */ +typedef enum { + /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ + emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, + /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ + emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD +} EMU_DcdcAnaPeripheralPower_TypeDef; +#endif + +#if defined(_EMU_DCDCMISCCTRL_MASK) +/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ +typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; + +/** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ +#define emuDcdcLnHighEfficiency -1 + +/** Default reverse current for fast transient response mode (low noise). */ +#define emuDcdcLnFastTransient 160 +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC Low-noise RCO band select. */ +typedef enum { + /** Set RCO to 3MHz. */ + emuDcdcLnRcoBand_3MHz = 0, + /** Set RCO to 4MHz. */ + emuDcdcLnRcoBand_4MHz = 1, + /** Set RCO to 5MHz. */ + emuDcdcLnRcoBand_5MHz = 2, + /** Set RCO to 6MHz. */ + emuDcdcLnRcoBand_6MHz = 3, + /** Set RCO to 7MHz. */ + emuDcdcLnRcoBand_7MHz = 4, + /** Set RCO to 8MHz. */ + emuDcdcLnRcoBand_8MHz = 5, + /** Set RCO to 9MHz. */ + emuDcdcLnRcoBand_9MHz = 6, + /** Set RCO to 10MHz. */ + emuDcdcLnRcoBand_10MHz = 7, +} EMU_DcdcLnRcoBand_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated. */ +#define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz +#define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz +#define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz +#define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz +#define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz +#define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz +#define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz +#define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz +/** @endcond */ + +/** DCDC Low Noise Compensator Control register. */ +typedef enum { + /** DCDC capacitor is 1uF. */ + emuDcdcLnCompCtrl_1u0F, + /** DCDC capacitor is 4.7uF. */ + emuDcdcLnCompCtrl_4u7F, +} EMU_DcdcLnCompCtrl_TypeDef; +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) + +/** DCDC mode. */ +typedef enum { + emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */ + emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */ +} EMU_DcdcMode_TypeDef; +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** VREGIN comparator threshold. */ +typedef enum { + emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */ + emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */ + emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */ + emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */ +} EMU_VreginCmpThreshold_TypeDef; + +/** DCDC Buck Ton max timeout. */ +typedef enum { +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) + emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */ +#else + emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */ + emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */ + emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */ + emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */ + emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */ + emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */ + emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */ + emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */ + emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */ + emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */ + emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */ + emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */ + emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */ + emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */ + emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */ + emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */ + emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */ + emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */ + emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */ + emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */ + emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */ + emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */ + emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */ + emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */ + emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */ +#endif +} EMU_DcdcTonMaxTimeout_TypeDef; + +/** DCDC Buck drive speed. */ +typedef enum { + emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcDriveSpeed_TypeDef; + +/** DCDC Buck peak current setting. */ +typedef enum { +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA) + emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA) + emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA) + emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ +#endif + emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ + emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ + emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ + emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ + emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ + emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA) + emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA) + emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA) + emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA) + emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA) + emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ +#endif +} EMU_DcdcPeakCurrent_TypeDef; +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost drive speed. */ +typedef enum { + emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcBoostDriveSpeed_TypeDef; + +/** DCDC Boost EM01 peak current setting. */ +typedef enum { + emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ + emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ + emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ + emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ + emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ + emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ + emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ + emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ + emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ + emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ +} EMU_DcdcBoostEM01PeakCurrent_TypeDef; + +/** DCDC Boost Toff max timeout */ +typedef enum { + emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */ + emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */ + emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */ + emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */ + emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */ + emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */ + emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */ + emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */ +} EMU_DcdcBoostToffMaxTimeout_TypeDef; + +/** DCDC Boost peak current detection maximum timeout */ +typedef enum { + emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */ +} EMU_DcdcBoostTonMaxTimeout_TypeDef; + +/** DCDC Boost EM23 peak current setting. */ +typedef enum { + emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ +} EMU_DcdcBoostEM23PeakCurrent_TypeDef; + +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +/** DCDC Boost output voltage */ +typedef enum { + emuDcdcBoostOutputVoltage_1v8 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V8, /**< Output voltage is 1.8V. */ + emuDcdcBoostOutputVoltage_1v9 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V9, /**< Output voltage is 1.9V. */ + emuDcdcBoostOutputVoltage_2v0 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V, /**< Output voltage is 2.0V. */ + emuDcdcBoostOutputVoltage_2v1 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V1, /**< Output voltage is 2.1V. */ + emuDcdcBoostOutputVoltage_2v2 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V2, /**< Output voltage is 2.2V. */ + emuDcdcBoostOutputVoltage_2v3 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V3, /**< Output voltage is 2.3V. */ + emuDcdcBoostOutputVoltage_2v4 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V4, /**< Output voltage is 2.4V. */ +} EMU_DcdcBoostOutputVoltage_TypeDef; +#endif + +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ + +#if defined(EMU_STATUS_VMONRDY) +/** VMON channels. */ +typedef enum { + emuVmonChannel_AVDD, + emuVmonChannel_ALTAVDD, + emuVmonChannel_DVDD, + emuVmonChannel_IOVDD0, +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + emuVmonChannel_IOVDD1, +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + emuVmonChannel_BUVDD, +#endif +} EMU_VmonChannel_TypeDef; +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/** Bias mode configurations. */ +typedef enum { + emuBiasMode_1KHz, + emuBiasMode_4KHz, + emuBiasMode_Continuous +} EMU_BiasMode_TypeDef; +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** Supported EM0/1 Voltage Scaling Levels. */ +typedef enum { + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. HF clock must be limited + to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when core clock frequency is + changed from @ref cmu or when calling @ref EMU_EM01Init() when HF + clock is already below the limit. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + /** Minimum VSCALE level in EM0/1 is VSCALE1. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1, +#else + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +#endif +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined(EMU_VSCALE_PRESENT) +/** Supported EM2/3 Voltage Scaling Levels. */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control. */ +typedef enum { +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */ +#endif + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */ +#endif + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */ +#endif + emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */ +#endif + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */ +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2 +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + | emuPeripheralRetention_WDOG1 +#endif + | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */ +} EMU_PeripheralRetention_TypeDef; +#endif + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/** Number of samples to use for temperature averaging. */ +typedef enum { + /** 16 samples used for temperature averaging. */ + emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16, + /** 64 samples used for temperature averaging. */ + emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64, +} EMU_TempAvgNum_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance + is always enabled. */ +typedef struct { + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) + EMU_HdregStopGearILmt_TypeDef current; /**< limit HDREG max current capability. */ +#endif +} EMU_EM01Init_TypeDef; + +/** Default initialization of EM0 and 1 configuration. */ +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +#define EMU_EM01INIT_DEFAULT \ + { \ + false, /* Do not scale down in EM0/1.*/ \ + emuHdregStopGearILmt64mA /* HDREG current limit is 64mA. */ \ + } +#else +#define EMU_EM01INIT_DEFAULT \ + { \ + false /* Do not scale down in EM0/1.*/ \ + } +#endif +#endif +/** EM2 and 3 initialization structure. */ +typedef struct { + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ +#if defined(EMU_VSCALE_PRESENT) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ +#endif +} EMU_EM23Init_TypeDef; + +/** Default initialization of EM2 and 3 configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ + } +#else +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + } +#endif +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/** EM4 initialization structure. */ +typedef struct { +#if defined(_EMU_EM4CONF_MASK) + /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ + bool vreg; /**< Enable EM4 voltage regulator. */ +#elif defined(_EMU_EM4CTRL_MASK) + /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ + bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ + bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ + bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ + EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ + EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ +#endif +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ +#endif +} EMU_EM4Init_TypeDef; +#endif + +#if defined(_EMU_EM4CONF_MASK) +/** Default initialization of EM4 configuration (Series 0). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Do not lock configuration after it's been set. */ \ + false, /* No reset will be asserted due to BOD in EM4. */ \ + emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ + true, /* Wake up on EM4 BURTC interrupt. */ \ + true, /* Enable VREG. */ \ + } + +#elif defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Default initialization of EM4 configuration (Series 1 with VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ + } + +#elif defined(_EMU_EM4CTRL_MASK) +/** Default initialization of EM4 configuration (Series 1 without VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain Initialization structure. */ +typedef struct { + /* Backup Power Domain power configuration. */ + + /** Voltage probe select, selects ADC voltage. */ + EMU_Probe_TypeDef probe; + /** Enable BOD calibration mode. */ + bool bodCal; + /** Enable BU_STAT status pin for active BU mode. */ + bool statusPinEnable; + + /* Backup Power Domain connection configuration. */ + /** Power domain resistor. */ + EMU_Resistor_TypeDef resistor; + /** BU_VOUT strong enable. */ + bool voutStrong; + /** BU_VOUT medium enable. */ + bool voutMed; + /** BU_VOUT weak enable. */ + bool voutWeak; + /** Power connection, when not in Backup Mode. */ + EMU_Power_TypeDef inactivePower; + /** Power connection, when in Backup Mode. */ + EMU_Power_TypeDef activePower; + /** Enable backup power domain, and release reset, enable BU_VIN pin. */ + bool enable; +} EMU_BUPDInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUPDINIT_DEFAULT \ + { \ + emuProbe_Disable, /* Do not enable voltage probe. */ \ + false, /* Disable BOD calibration mode. */ \ + false, /* Disable BU_STAT pin for backup mode indication. */ \ + \ + emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ + false, /* Do not enable strong switch. */ \ + false, /* Do not enable medium switch. */ \ + false, /* Do not enable weak switch. */ \ + \ + emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ + emuPower_None, /* No connection between main and backup power. (active mode) */ \ + true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/** Backup Power Domain Initialization structure. */ +typedef struct { + bool disMaxComp; /**< Disable MAIN-BU Comparator. */ + EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ + EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ + EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ + EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ + bool buVinProbeEn; /**< Enable BU_VIN probing. */ + bool staEn; /**< Enable backup mode status export. */ + bool enable; /**< Enable backup power domain. */ +} EMU_BUInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUINIT_DEFAULT \ + { \ + false, /* MAIN-BU Comparator is not disabled */ \ + emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \ + emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \ + emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \ + emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \ + false, /* BU_VIN probe is disabled */ \ + false, /* Status export is disabled */ \ + true /* Enable backup mode */ \ + } +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost regulator initialization structure. */ +typedef struct { + EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ + bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + EMU_DcdcBoostOutputVoltage_TypeDef outputVoltage; /**< DCDC Boost output voltage. */ +#endif +} EMU_DCDCBoostInit_TypeDef; + +/** Default DCDC Boost initialization. */ +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +#define EMU_DCDCBOOSTINIT_DEFAULT \ + { \ + emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM23PeakCurrent_Load10mA, /**< Default peak current in EM2/3. */ \ + emuDcdcBoostOutputVoltage_1v8 /**< DCDC Boost output voltage. */ \ + } +#else +#define EMU_DCDCBOOSTINIT_DEFAULT \ + { \ + emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ + } +#endif +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** DCDC regulator initialization structure. */ +typedef struct { + EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */ + EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */ + EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + bool dcmOnlyEn; /**< DCM only mode enable. */ +#endif + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC Buck initialization. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< Enable DCM only mode. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#endif +#endif /* SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC initialization structure. */ +typedef struct { + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ + EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ + uint16_t mVout; /**< Target output voltage (mV). */ + uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). + This estimate is also used for EM1 optimization; + if EM1 current is expected to be higher than EM0, + then this parameter should hold the higher EM1 current. */ + uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). + This estimate is also used for EM3 and 4 optimization; + if EM3 or 4 current is expected to be higher than EM2, + then this parameter should hold the higher EM3 or 4 current. */ + uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). + This can be set to the maximum for the power source, + for example the maximum for a battery. */ + EMU_DcdcAnaPeripheralPower_TypeDef + anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ + EMU_DcdcLnReverseCurrentControl_TypeDef + reverseCurrentControl; /**< Low-noise reverse current control. + NOTE: this parameter uses special encoding: + >= 0 is forced CCM mode where the parameter is used as the + reverse current threshold in mA. + -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ + EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC initialization. */ +#if defined(_EFM_DEVICE) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#elif defined(WGM160PX22KGA2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif + +#else /* EFR32 device. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif +#endif +#endif + +#if defined(EMU_STATUS_VMONRDY) +/** VMON initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ + bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ +} EMU_VmonInit_TypeDef; + +/** Default VMON initialization structure. */ +#define EMU_VMONINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true, /* Enable VMON channel. */ \ + false /* Do not disable IO0 retention */ \ + } + +/** VMON Hysteresis initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int riseThreshold; /**< Rising threshold (mV). */ + int fallThreshold; /**< Falling threshold (mV). */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ +} EMU_VmonHystInit_TypeDef; + +/** Default VMON Hysteresis initialization structure. */ +#define EMU_VMONHYSTINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V rise threshold. */ \ + 3200, /* 3.2 V fall threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true /* Enable VMON channel. */ \ + } +#endif /* EMU_STATUS_VMONRDY */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); +void EMU_EM23PresleepHook(void); +void EMU_EM23PostsleepHook(void); +void EMU_EFPEM23PresleepHook(void); +void EMU_EFPEM23PostsleepHook(void); +void EMU_EnterEM2(bool restore); +void EMU_EnterEM3(bool restore); +void EMU_Save(void); +void EMU_Restore(void); +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); +#endif +void EMU_EM4PresleepHook(void); +void EMU_EFPEM4PresleepHook(void); +void EMU_EnterEM4(void); +void EMU_EnterEM4Wait(void); +#if defined(_EMU_EM4CTRL_MASK) +void EMU_EnterEM4H(void); +void EMU_EnterEM4S(void); +#endif +void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1; +void EMU_RamPowerDown(uint32_t start, uint32_t end); +void EMU_RamPowerUp(void); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif +void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1; +#if defined(EMU_VSCALE_EM01_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) +void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage); +#endif +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); +#endif +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +void EMU_BUDisMaxCompSet(bool disableMainBuComparator); +#endif +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); +#endif +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); +#endif +#if defined(_EMU_BUCTRL_PWRRES_MASK) +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); +#endif +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); +#endif +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +void EMU_BUBuVinProbeEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_STATEN_MASK) +void EMU_BUStatEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_EN_MASK) +void EMU_BUEnableSet(bool enable); +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +void EMU_DCDCUpdatedHook(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); +void EMU_BoostExternalShutdownEnable(bool enable); +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +void EMU_DCDCBoostOutputVoltageSet(const EMU_DcdcBoostOutputVoltage_TypeDef boostOutputVoltage); +#endif +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +bool EMU_DCDCPowerOff(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); +#endif +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value); +#endif +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23); +#endif +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); +bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); +#endif +#if defined(_EMU_TEMP_TEMP_MASK) +float EMU_TemperatureGet(void); +#endif +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +void EMU_EFPDirectModeEnable(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +void EMU_EFPDriveDecoupleSet(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDVDD) +void EMU_EFPDriveDvddSet(bool enable); +#endif +#if defined(_EMU_CTRL_HDREGEM2EXITCLIM_MASK) +void EMU_HDRegEM2ExitCurrentLimitEnable(bool enable); +#endif +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +void EMU_HDRegStopGearSet(EMU_HdregStopGearILmt_TypeDef current); +#endif +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Lock DCDC registers in order to protect them against unintended + * modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCLock(void) +{ + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Unlock the DCDC so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCUnlock(void) +{ + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_SYNCBUSY_MASK) +/***************************************************************************//** + * @brief + * Wait for the DCDC to complete all synchronization of register changes. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCSync(uint32_t mask) +{ + while (0UL != (DCDC->SYNCBUSY & mask)) { + /* Wait for previous synchronization to finish */ + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Check status of the internal LDO regulator. + * + * @return + * Return true if the regulator is on, false if regulator is off. + ******************************************************************************/ +__STATIC_INLINE bool EMU_LDOStatusGet(void) +{ + if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) { + return true; + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Enter energy mode 1 (EM1). + * + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + ******************************************************************************/ +__STATIC_INLINE void EMU_EnterEM1(void) +{ + /* Enter sleep mode. */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete. + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip waiting if the LDO regulator is turned off. */ + return; + } +#endif + + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Get current voltage scaling level. + * + * @return + * Current voltage scaling level. + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((uint32_t) + ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT)); +} +#endif + +#if defined(_EMU_STATUS_VMONRDY_MASK) +/***************************************************************************//** + * @brief + * Get the status of the voltage monitor (VMON). + * + * @return + * Status of the VMON. True if all the enabled channels are ready, false if + * one or more of the enabled channels are not ready. + ******************************************************************************/ +__STATIC_INLINE bool EMU_VmonStatusGet(void) +{ + return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; +} +#endif /* _EMU_STATUS_VMONRDY_MASK */ + +#if defined(_EMU_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending EMU interrupts. + * + * @param[in] flags + * Pending EMU interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntClear(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_CLR = flags; +#else + EMU->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to disable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntDisable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_CLR = flags; +#else + EMU->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more EMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * @ref EMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * EMU interrupt sources to enable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntEnable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_SET = flags; +#else + EMU->IEN |= flags; +#endif +} + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Disable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to disable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags) +{ + EMU->EFPIEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to enable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags) +{ + EMU->EFPIEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending EMU EFP interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU EFP interrupt sources pending. . + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGet(void) +{ + return EMU->EFPIF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU EFP interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU EFP interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_EFPIEN and + * - the pending interrupt flags EMU_EFPIF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->EFPIEN; + return EMU->EFPIF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU EFP interrupts. + * + * @param[in] flags + * EMU EFP interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntSet(uint32_t flags) +{ + EMU->EFPIF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending EMU EFP interrupts. + * + * @param[in] flags + * Pending EMU EFP interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU EFP module. + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntClear(uint32_t flags) +{ + EMU->EFPIF_CLR = flags; +} +#endif + +/***************************************************************************//** + * @brief + * Get pending EMU interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU interrupt sources pending. Returns one or more valid + * interrupt flags for the EMU module (EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGet(void) +{ + return EMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_IEN and + * - the pending interrupt flags EMU_IF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->IEN; + return EMU->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU module (EMU_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntSet(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_SET = flags; +#else + EMU->IFS = flags; +#endif +} +#endif /* _EMU_IF_MASK */ + +#if defined(_EMU_EM4CONF_LOCKCONF_MASK) +/***************************************************************************//** + * @brief + * Enable or disable EM4 lock configuration. + * @param[in] enable + * If true, locks down EM4 configuration. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM4Lock(bool enable) +{ + BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); +} +#endif + +#if defined(_EMU_STATUS_BURDY_MASK) +/***************************************************************************//** + * @brief + * Halts until backup power functionality is ready. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUReady(void) +{ + while (!(EMU->STATUS & EMU_STATUS_BURDY)) + ; +} +#endif + +#if defined(_EMU_ROUTE_BUVINPEN_MASK) +/***************************************************************************//** + * @brief + * Disable BU_VIN support. + * @param[in] enable + * If true, enables BU_VIN input pin support, if false disables it. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUPinEnable(bool enable) +{ + BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); +} +#endif + +/***************************************************************************//** + * @brief + * Lock EMU registers in order to protect them against unintended + * modification. + * + * @note + * If locking EMU registers, they must be unlocked prior to using any + * EMU API functions modifying EMU registers, excluding interrupt control + * and regulator control if the architecture has a EMU_PWRCTRL register. + * An exception to this is the energy mode entering API (EMU_EnterEMn()), + * which can be used when the EMU registers are locked. + ******************************************************************************/ +__STATIC_INLINE void EMU_Lock(void) +{ + EMU->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_Unlock(void) +{ + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; +} + +#if defined(_EMU_PWRLOCK_MASK) +/***************************************************************************//** + * @brief + * Lock the EMU regulator control registers in order to protect against + * unintended modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerLock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU power control registers so that writing to + * locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerUnlock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; +} +#endif + +#if defined(_EMU_CTRL_EM2BLOCK_MASK) +/***************************************************************************//** + * @brief + * Block entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2Block(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); +} + +/***************************************************************************//** + * @brief + * Unblock entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2UnBlock(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); +} +#endif + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/***************************************************************************//** + * @brief + * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained + * through EM4 entry and wakeup. The pin state is released by calling this function. + * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), + * and when initialization is done, this function can release pins and return control + * to the peripherals or GPIO. + ******************************************************************************/ +__STATIC_INLINE void EMU_UnlatchPinRetention(void) +{ + EMU->CMD = EMU_CMD_EM4UNLATCH; +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/** Zero degrees Celcius in Kelvin */ +#define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f) +/***************************************************************************//** + * @brief + * Temperature measurement ready status + * + * @return + * True if temperature measurement is ready + ******************************************************************************/ +__STATIC_INLINE bool EMU_TemperatureReady(void) +{ +#if defined(EMU_STATUS_FIRSTTEMPDONE) + return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); +#else + return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u); +#endif +} + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/***************************************************************************//** + * @brief + * Get averaged temperature in degrees Celsius. + * + * @note + * An averaged temperature measurement must first be requested by calling + * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag + * to go high. + * + * @return + * Averaged temperature + ******************************************************************************/ +__STATIC_INLINE float EMU_TemperatureAvgGet(void) +{ + uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK) + >> _EMU_TEMP_TEMPAVG_SHIFT); + return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +} + +/***************************************************************************//** + * @brief + * Request averaged temperature. + * + * @note + * EMU must be unlocked by calling @ref EMU_Unlock() before this function + * can be called. + * + * @param[in] numSamples + * Number of temperature samples to average + ******************************************************************************/ +__STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples); + EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT; +} + +#endif //defined(_EMU_TEMP_TEMPAVG_MASK) +#endif //defined(_EMU_TEMP_TEMP_MASK) + +/** @} (end addtogroup emu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( EMU_PRESENT ) */ +#endif /* EM_EMU_H */ diff --git a/Libs/platform/emlib/inc/em_eusart.h b/Libs/platform/emlib/inc/em_eusart.h new file mode 100644 index 0000000..b0c6a3b --- /dev/null +++ b/Libs/platform/emlib/inc/em_eusart.h @@ -0,0 +1,1223 @@ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_H +#define EM_EUSART_H +#include "em_device.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "sl_enum.h" +#include "em_eusart_compat.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup eusart EUSART - Extended USART +/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter +/// +/// @li @ref eusart_intro +/// @li @ref eusart_example +/// @li @ref eusart_em2 +/// +///@n @section eusart_intro Introduction +/// This module contains functions to control the Enhanced Universal Synchronous +/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon +/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, +/// therefore, be connected to an external transceiver to communicate with +/// another host using the serial link. +/// +/// It supports full duplex asynchronous UART communication as well as RS-485, +/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, +/// and IrDA devices. +/// +/// EUSART has a wide selection of operating modes, frame formats, and baud rates. +/// All features are supported through the API of this module. +/// +/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers +/// provide full support for DMA and more. +/// +///@n @section eusart_example Example +/// +/// EUSART Async TX example: +/// @code{.c} +/// { +/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); +/// CMU_ClockEnable(cmuClock_EUSART0CLK, true); +/// // Initialize the EUSART +/// EUSART_UartInitHf(EUSART0, &init); +/// EUSART_Tx(EUSART0, data); +/// } +/// +/// @endcode +/// +/// EUSART Sync SPI Transaction example: +/// @code{.c} +/// { +/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); +/// CMU_ClockEnable(cmuClock_EUSART1, true); +/// CMU_ClockEnable(cmuClock_GPIO, true); +/// +/// //Configure the SPI ports +/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0); +/// +/// // Connect EUSART to ports +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT) +/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT) +/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) +/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN; +/// +/// // Initialize the EUSART +/// EUSART_SpiInit(EUSART1, &init_master); +/// EUSART_Spi_TxRx(EUSART1, data); +/// } +/// +/// @endcode +///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances +/// +/// @note EUSART instances located in the PD1 power domain are non EM2-capable. +/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used +/// to determine whether or not a EUSART instance is EM2-Capable. +/// +/// Follow theses steps when entering in EM2: +/// -# Wait for the current transaction to complete with TXCIF interrupt +/// -# Disable TX and RX using TXDIS and RXDIS cmd +/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low +/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low +/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled +/// -# Enter EM2 +/// +/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO +/// (SCLKPEN and CSPEN) must be re-enabled. For example: +/// +/// @code{.c} +/// { +/// // Enable TX and RX +/// EUSART_Enable(EUSART0, eusartEnable); +/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN, +/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, +/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); +/// } +/// @endcode +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Define EUSART FIFO Depth information */ +#if !defined(EUSART_FIFO_DEPTH) +#if defined(EUART_PRESENT) +#define EUSART0_FIFO_DEPTH 4 +#elif defined(EUSART_PRESENT) +#define EUSART0_FIFO_DEPTH 16 +#endif /* EUART_PRESENT */ +#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH + +#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \ + : ((n) == 1) ? EUSART1_FIFO_DEPTH \ + : ((n) == 2) ? EUSART2_FIFO_DEPTH \ + : ((n) == 3) ? EUSART3_FIFO_DEPTH \ + : ((n) == 4) ? EUSART4_FIFO_DEPTH \ + : 0x0UL) +#endif /* EUSART_FIFO_DEPTH */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Enable selection. +typedef enum { + /// Disable the peripheral. + eusartDisable = 0x0, + + /// Enable receiver only, transmitter disabled. + eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS), + + /// Enable transmitter only, receiver disabled. + eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS), + + /// Enable both receiver and transmitter. + eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN) +} EUSART_Enable_TypeDef; + +/// Data bit selection. +typedef enum { + eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits. + eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits. + eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits. +#if defined(EUSART_PRESENT) + eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only. + eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only. + eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only. + eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only. + eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only. + eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only. + eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only. +#endif +} EUSART_Databits_TypeDef; + +/// Parity selection. +typedef enum { + eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity. + eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity. + eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity. +} EUSART_Parity_TypeDef; + +/// Stop bits selection. +typedef enum { + eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits. + eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits. + eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits. + eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits. +} EUSART_Stopbits_TypeDef; + +/// Oversampling selection, used for asynchronous operation. +typedef enum { + eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal). + eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling. + eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling. + eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling. + eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled. +} EUSART_OVS_TypeDef; + +/// HW flow control config. +typedef enum { + eusartHwFlowControlNone = 0, ///< No HW Flow Control. + eusartHwFlowControlCts, ///< CTS HW Flow Control. + eusartHwFlowControlRts, ///< RTS HW Flow Control. + eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control. +} EUSART_HwFlowControl_TypeDef; + +/// Loopback enable. +typedef enum { + eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback. + eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback. +} EUSART_LoopbackEnable_TypeDef; + +/// Majority vote enable. +typedef enum { + eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes. + eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes. +} EUSART_MajorityVote_TypeDef; + +/// Block reception enable. +typedef enum { + eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded. + eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO. +} EUSART_BlockRx_TypeDef; + +/// TX output tristate enable. +typedef enum { + eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output. + eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output. +} EUSART_TristateTx_TypeDef; + +/// IrDA filter enable. +typedef enum { + eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator. + eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator. +} EUSART_IrDARxFilterEnable_TypeDef; + +/// Pulse width selection for IrDA mode. +typedef enum { + /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8 + eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE, + + /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8 + eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO, + + /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8 + eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE, + + /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8 + eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR +} EUSART_IrDAPulseWidth_Typedef; + +/// PRS trigger enable. +typedef enum { + /// Disable trigger on both receiver and transmitter. + eusartPrsTriggerDisable = 0x0, + + /// Enable receive trigger only, transmit disabled. + eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN, + + /// Enable transmit trigger only, receive disabled. + eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN, + + /// Enable trigger on both receive and transmit. + eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN) +} EUSART_PrsTriggerEnable_TypeDef; + +/// PRS Channel type. +typedef uint8_t EUSART_PrsChannel_TypeDef; + +/// IO polarity selection. +typedef enum { + /// Disable inversion on both RX and TX signals. + eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE), + + /// Invert RX signal, before receiver. + eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE, + + /// Invert TX signal, after transmitter. + eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE, + + /// Enable trigger on both receive and transmit. + eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) +} EUSART_InvertIO_TypeDef; + +/// Auto TX delay transmission. +SL_ENUM(EUSART_AutoTxDelay_TypeDef) { + /// Frames are transmitted immediately. + eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE, + + /// Transmission of new frames is delayed by a single bit period. + eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE, + + /// Transmission of new frames is delayed by a two bit periods. + eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE, + + /// Transmission of new frames is delayed by a three bit periods. + eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE +}; + +/// RX FIFO Interrupt ans Status Watermark. +typedef enum { + eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME, + eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES, + eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES, + eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES, + eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES, + eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES, + eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES, + eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES, + eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES, + eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES, + eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES, + eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES, + eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES, + eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES, + eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES +#endif +} EUSART_RxFifoWatermark_TypeDef; + +/// TX FIFO Interrupt and Status Watermark. +typedef enum { + eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME, + eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES, + eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES, + eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES, + eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES, + eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES, + eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES, + eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES, + eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES, + eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES, + eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES, + eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES, + eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES, + eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES, + eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES +#endif +} EUSART_TxFifoWatermark_TypeDef; + +#if defined(EUSART_PRESENT) +/// Clock polarity/phase mode. +typedef enum { + /// Clock idle low, sample on rising edge. + eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle low, sample on falling edge. + eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING, + + /// Clock idle high, sample on falling edge. + eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle high, sample on rising edge. + eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING +} EUSART_ClockMode_TypeDef; + +/// Chip select polarity. +typedef enum { + /// Chip select active low. + eusartCsActiveLow = EUSART_CFG2_CSINV_AL, + + /// Chip select active high. + eusartCsActiveHigh = EUSART_CFG2_CSINV_AH, +} EUSART_CsPolarity_TypeDef; + +#if defined(EUSART_DALICFG_DALIEN) +/// DALI TX databits (8-32). +typedef enum { + eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliTxDatabits_TypeDef; + +/// DALI RX databits (8-32). +typedef enum { + eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliRxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliRxDatabits_TypeDef; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ +/// Advanced initialization structure. +typedef struct { + /// Hardware flow control mode. + EUSART_HwFlowControl_TypeDef hwFlowControl; + + /// Enable the collision Detection feature. + /// Internal (setting loopbackEnable) or external loopback must be done to use this feature. + bool collisionDetectEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + bool dmaWakeUpOnRx; + + /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation. + bool dmaWakeUpOnTx; + + /// Enable DMA requests blocking while framing or parity errors. + bool dmaHaltOnError; + + /// Start frame that will enable RX operation. 0x00 Disable this feature. + uint8_t startFrame; + + /// Enable automatic tristating of transmistter output when there is nothing to transmit. + bool txAutoTristate; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable Multiprocessor mode. Address and data filtering using the 9th bit. + bool multiProcessorEnable; + + /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise. + bool multiProcessorAddressBitHigh; + + /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed. + EUSART_AutoTxDelay_TypeDef autoTxDelay; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Transmit FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; +} EUSART_AdvancedInit_TypeDef; + +/// Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired baud rate. If set to 0, Auto Baud feature is enabled and + /// the EUSART will wait for (0x55) frame to detect the Baudrate. + uint32_t baudrate; + + /// Oversampling used. + EUSART_OVS_TypeDef oversampling; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Parity mode to use. + EUSART_Parity_TypeDef parity; + + /// Number of stop bits to use. + EUSART_Stopbits_TypeDef stopbits; + + /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes. + EUSART_MajorityVote_TypeDef majorityVote; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_AdvancedInit_TypeDef *advancedSettings; +} EUSART_UartInit_TypeDef; + +/// IrDA Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the IrDA low frequency mode. Only RX operation are enabled. + bool irDALowFrequencyEnable; + + /// Set to enable filter on IrDA demodulator. + EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable; + + /// Configure the pulse width generated by the IrDA modulator as a fraction + /// of the configured EUSART bit period. + EUSART_IrDAPulseWidth_Typedef irDAPulseWidth; +} EUSART_IrDAInit_TypeDef; + +/// PRS Trigger initialization structure. +typedef struct { + /// PRS to EUSART trigger mode. + EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable; + + /// PRS channel to be used to trigger auto transmission. + EUSART_PrsChannel_TypeDef prs_trigger_channel; +} EUSART_PrsTriggerInit_TypeDef; + +#if defined(EUSART_PRESENT) +/// SPI Advanced initialization structure. +typedef struct { + /// Chip select polarity + EUSART_CsPolarity_TypeDef csPolarity; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable automatic chip select. CS is managed by the peripheral. + bool autoCsEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsSetupTime; + + /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsHoldTime; + + /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoInterFrameTime; + + /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full. + /// Generates underflow interrupt if the TX FIFO is empty. + bool autoTxEnable; + + /// Default transmitted data when the TXFIFO is empty. + uint16_t defaultTxData; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + /// Only applicable to EM2 (low frequency) capable EUSART instances. + bool dmaWakeUpOnRx; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable EUSART capability to use a PRS channel as an input SPI Clock. + /// Slave mode only. + bool prsClockEnable; + + /// PRS Channel used to transmit SCLK from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsClockChannel; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Receive FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; + + /// Force load the first FIFO value. + bool forceLoad; + + /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error. + uint8_t setupWindow; +} EUSART_SpiAdvancedInit_TypeDef; + +/// SPI Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired bit rate in Hz. + /// Depending on EUSART instance clock, not all bitrates + /// are achievable as the divider is limited to 255. + uint32_t bitRate; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Select to operate in master or slave mode. + bool master; + + /// Clock polarity/phase mode. + EUSART_ClockMode_TypeDef clockMode; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_SpiAdvancedInit_TypeDef *advancedSettings; +} EUSART_SpiInit_TypeDef; +#endif /* EUSART_PRESENT */ + +/// DALI Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the DALI low frequency mode. + bool daliLowFrequencyEnable; + +#if defined(EUSART_DALICFG_DALIEN) + /// Number of TX data bits in frame. + EUSART_DaliTxDatabits_TypeDef TXdatabits; + /// Number of RX data bits in frame. + EUSART_DaliRxDatabits_TypeDef RXdatabits; +#endif +} EUSART_DaliInit_TypeDef; + +/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock. +#define EUSART_UART_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 115200, /* 115200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default start frame configuration, i.e. feature disabled. +#define EUSART_DEFAULT_START_FRAME 0x00u + +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock. +#define EUSART_UART_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_HF \ + { \ + EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \ + false, /* Disable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_LF \ + { \ + { \ + eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + }, \ + true, /* Enable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \ + } + +#if defined(EUSART_PRESENT) +/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock. +#define EUSART_SPI_ADVANCED_INIT_DEFAULT \ + { \ + eusartCsActiveLow, /* CS active low. */ \ + eusartInvertIODisable, /* RX and TX signal active High. */ \ + true, /* AutoCS enabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + 0u, /* CS setup time is 0 baud cycles */ \ + 0u, /* CS hold time is 0 baud cycles */ \ + 0u, /* Inter-frame time is 0 baud cycles */ \ + false, /* AutoTX disabled. */ \ + 0x0000, /* Default transmitted data is 0. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* Do not use PRS signal as RX signal. */ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \ + false, /* Do not use PRS signal as SCLK signal. */ \ + (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + true, /* The first byte sent by the slave won't be the default value if a byte is made available \ + after chip select is asserted. */ \ + 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock. +#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + true, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock. +#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + false, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +#if defined(EUSART_DALICFG_DALIEN) +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_DALI_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + true, /* Data is sent with the most significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_HF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_HF, \ + false, /* Disable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_LF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_LF, \ + true, /* Enable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the high frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in IrDA mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param irdaInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initialize EUSART when used in SPI mode. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initialize EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param daliInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit); + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure EUSART to its reset state. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/disable EUSART receiver and/or transmitter. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the status for the receiver and transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable); + +/***************************************************************************//** + * Receive one 8 bit frame, (or part of 9 bit frame). + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame when operating with + * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. + * Notice that possible parity/stop bits are not considered a part of the + * specified frame bit length. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received. + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Receive one 8-16 bit frame with extended information. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame and additional RX + * status information. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received and receive status. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Transmit one frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the frame length configuration, 8 (least significant) bits + * from @p data are transmitted. If the frame length is 9, 8 bits are + * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame + * with full control of all 9 bits. + * @note This function will stall if the 4 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data); + +/***************************************************************************//** + * Transmit one 8-9 bit frame with extended control. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * @note This function will stall if buffer is full until the buffer becomes + * available. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmit one 8-16 bit frame and return received data. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @return Data received and receive status. + * + * @note SPI master mode only. + * @note This function will stall if the TX buffer is full until the buffer becomes + * available. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmit one DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the TXdatabits configuration, N (least significant) bits + * from @p data are transmitted. + * @note This function will stall if the 16 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data); + +/***************************************************************************//** + * Receive one 8-32 bit DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one DALI frame (RXdatabits). + * @note This function will stall if the 16 frame FIFO is empty until new + * data is received. + * + * @return Data received. Depending on the RXdatabits configuration, N + * (least significant) bits are returned. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart); +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the baudrate (or as close as possible to a specified baudrate). + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * If set to 0, the currently configured peripheral clock is + * used. + * @param baudrate A baudrate to try to achieve. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate); + +/***************************************************************************//** + * Get the current baudrate. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return The current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/Disable reception operation until the configured start frame is + * received. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the receiver blocking status. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, + EUSART_BlockRx_TypeDef enable); + +/***************************************************************************//** + * Enable/Disable the tristating of the transmitter output. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the transmitter tristate status. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable); + +/***************************************************************************//** + * Initialize the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + * @note + * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before + * enabling the PRS trigger. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init Pointer to the initialization structure. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * Get EUSART STATUS register. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart) +{ + return eusart->STATUS; +} + +/***************************************************************************//** + * Clear one or more pending EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_CLR = flags; +} + +/***************************************************************************//** + * Disable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_CLR = flags; +} + +/***************************************************************************//** + * Enable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_SET = flags; +} + +/***************************************************************************//** + * Get pending EUSART interrupt flags. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart) +{ + return eusart->IF; +} + +/***************************************************************************//** + * Get enabled and pending EUSART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending and enabled EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart) +{ + uint32_t tmp; + + /* Store EUSARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = eusart->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return eusart->IF & tmp; +} + +/***************************************************************************//** + * Set one or more pending EUSART interrupts from SW. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_SET = flags; +} + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup eusart) */ +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ +#endif /* EM_EUSART_H */ diff --git a/Libs/platform/emlib/inc/em_eusart_compat.h b/Libs/platform/emlib/inc/em_eusart_compat.h new file mode 100644 index 0000000..50822e2 --- /dev/null +++ b/Libs/platform/emlib/inc/em_eusart_compat.h @@ -0,0 +1,218 @@ +/***************************************************************************//** + * @file + * @brief EUSART Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_COMPAT_H +#define EM_EUSART_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define EUSART_IF_TXCIF EUSART_IF_TXC +#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT +#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK +#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT +#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT + +#define EUSART_IF_TXFLIF EUSART_IF_TXFL +#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT +#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK +#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT +#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT + +#define EUSART_IF_RXFLIF EUSART_IF_RXFL +#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT +#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK +#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT +#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT + +#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL +#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT +#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK +#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT +#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT + +#define EUSART_IF_RXOFIF EUSART_IF_RXOF +#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT +#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK +#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT +#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT + +#define EUSART_IF_RXUFIF EUSART_IF_RXUF +#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT +#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK +#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT +#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT + +#define EUSART_IF_TXOFIF EUSART_IF_TXOF +#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT +#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK +#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT +#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT + +#define EUSART_IF_PERRIF EUSART_IF_PERR +#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT +#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK +#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT +#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT + +#define EUSART_IF_FERRIF EUSART_IF_FERR +#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT +#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK +#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT +#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT + +#define EUSART_IF_MPAFIF EUSART_IF_MPAF +#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT +#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK +#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT +#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT + +#define EUSART_IF_CCFIF EUSART_IF_CCF +#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT +#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK +#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT +#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT + +#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE +#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT +#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK +#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT +#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT + +#define EUSART_IF_STARTFIF EUSART_IF_STARTF +#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT +#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK +#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT +#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT + +#define EUSART_IF_SIGFIF EUSART_IF_SIGF +#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT +#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK +#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT +#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT + +#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE +#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT +#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK +#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT +#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT + +#define EUSART_IEN_TXCIEN EUSART_IEN_TXC +#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT +#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK +#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT +#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT + +#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL +#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT +#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK +#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT +#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT + +#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL +#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT +#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK +#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT +#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT + +#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL +#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT +#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK +#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT +#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT + +#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF +#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT +#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK +#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT +#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT + +#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF +#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT +#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK +#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT +#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT + +#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF +#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT +#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK +#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT +#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT + +#define EUSART_IEN_PERRIEN EUSART_IEN_PERR +#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT +#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK +#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT +#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT + +#define EUSART_IEN_FERRIEN EUSART_IEN_FERR +#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT +#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK +#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT +#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT + +#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF +#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT +#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK +#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT +#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT + +#define EUSART_IEN_CCFIEN EUSART_IEN_CCF +#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT +#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK +#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT +#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT + +#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE +#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT +#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK +#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT +#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT + +#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF +#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT +#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK +#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT +#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT + +#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF +#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT +#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK +#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT +#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT + +#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE +#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT +#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK +#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT +#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT + +#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2 + +#endif diff --git a/Libs/platform/emlib/inc/em_gpcrc.h b/Libs/platform/emlib/inc/em_gpcrc.h new file mode 100644 index 0000000..64f7d19 --- /dev/null +++ b/Libs/platform/emlib/inc/em_gpcrc.h @@ -0,0 +1,346 @@ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPCRC_H +#define EM_GPCRC_H + +#include "em_bus.h" +#include "em_device.h" +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup gpcrc GPCRC - General Purpose CRC + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API + * + * @details + * The GPCRC API functions provide full support for the GPCRC peripheral. + * + * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check + * (CRC) function. It supports a fixed 32-bit polynomial and a user + * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly + * used IEEE 802.3 polynomial 0x04C11DB7. + * + * When using a 16-bit polynomial it is up to the user to choose a polynomial + * that fits the application. Commonly used 16-bit polynomials are 0x1021 + * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). + * See this link for other polynomials: + * https://en.wikipedia.org/wiki/Cyclic_redundancy_check + * + * Before a CRC calculation can begin, call the + * @ref GPCRC_Start function. This function will reset CRC calculation + * by copying the configured initialization value over to the CRC data register. + * + * There are two ways of sending input data to the GPCRC. Either write + * the input data into the input data register using input functions + * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the + * user can configure @ref ldma to transfer data directly to one of the GPCRC + * input data registers. + * + * Examples of GPCRC usage: + * + * A CRC-32 Calculation: + * + * @include em_gpcrc_crc32.c + * + * A CRC-16 Calculation: + * + * @include em_gpcrc_crc16.c + * + * A CRC-CCITT calculation: + * + * @include em_gpcrc_ccit.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CRC initialization structure. */ +typedef struct { + /** + * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial + * or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial + * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the + * 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field. + * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 + * bits are zero. + * + * The polynomial should be written in normal bit order. For instance, + * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert + * it to hex representation and remove the highest order term + * of the polynomial. This will give 0x8005 as the value to write into + * crcPoly. + */ + uint32_t crcPoly; + + /** + * CRC initialization value. This value is assigned to the GPCRC_INIT register. + * The initValue is loaded into the data register when calling the + * @ref GPCRC_Start function or when one of the data registers are read + * while @ref autoInit is enabled. + */ + uint32_t initValue; + + /** + * Reverse byte order. This has an effect when sending a 32-bit word or + * 16-bit half word input to the CRC calculation. When set to true, the input + * bytes are reversed before entering the CRC calculation. When set to + * false, the input bytes stay in the same order. + */ + bool reverseByteOrder; + + /** + * Reverse bits within each input byte. This setting enables or disables byte + * level bit reversal. When byte-level bit reversal is enabled, then each byte + * of input data will be reversed before entering CRC calculation. + */ + bool reverseBits; + + /** + * Enable/disable byte mode. When byte mode is enabled, then all input + * is treated as single byte input even though the input is a 32-bit word + * or a 16-bit half word. Only the least significant byte of the data-word + * will be used for CRC calculation for all writes. + */ + bool enableByteMode; + + /** + * Enable automatic initialization by re-seeding the CRC result based on + * the init value after reading one of the CRC data registers. + */ + bool autoInit; + + /** Enable/disable GPCRC when initialization is completed. */ + bool enable; +} GPCRC_Init_TypeDef; + +/** Default configuration for GPCRC_Init_TypeDef structure. */ +#define GPCRC_INIT_DEFAULT \ + { \ + 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ + 0x00000000UL, /* Initialization value. */ \ + false, /* Byte order is normal. */ \ + false, /* Bit order is not reversed on output. */ \ + false, /* Disable byte mode. */ \ + false, /* Disable automatic initialization on data read. */ \ + true, /* Enable GPCRC. */ \ + } + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ + +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); +void GPCRC_Reset(GPCRC_TypeDef * gpcrc); + +/***************************************************************************//** + * @brief + * Enable/disable GPCRC. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] enable + * True to enable GPCRC, false to disable. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) +{ +#if defined(GPCRC_EN_EN) + BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Issue a command to initialize the CRC calculation. + * + * @details + * Issues the command INIT in GPCRC_CMD that initializes the + * CRC calculation by writing the initial values to the DATA register. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CMD = GPCRC_CMD_INIT; +} + +/***************************************************************************//** + * @brief + * Set the initialization value of the CRC. + * + * @param [in] initValue + * Value to use to initialize a CRC calculation. This value is moved into + * the data register when calling @ref GPCRC_Start + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) +{ + gpcrc->INIT = initValue; +} + +/***************************************************************************//** + * @brief + * Write a 32-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 32-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) +{ + gpcrc->INPUTDATA = data; +} + +/***************************************************************************//** + * @brief + * Write a 16-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 16 bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) +{ + gpcrc->INPUTDATAHWORD = data; +} + +/***************************************************************************//** + * @brief + * Write an 8-bit value to the CRC input data register. + * + * @details + * Use this function to write an 8-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) +{ + gpcrc->INPUTDATABYTE = data; +} + +/***************************************************************************//** + * @brief + * Read the CRC data register. + * + * @details + * Use this function to read the calculated CRC value. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATA; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC bit reversed. + * + * @details + * Use this function to read the calculated CRC value bit reversed. When + * using a 32-bit polynomial, bits [31:0] are reversed, when using a + * 16-bit polynomial, bits [15:0] are reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register bit reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATAREV; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC byte reversed. + * + * @details + * Use this function to read the calculated CRC value byte reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register byte reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATABYTEREV; +} + +/** @} (end addtogroup gpcrc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ +#endif /* EM_GPCRC_H */ diff --git a/Libs/platform/emlib/inc/em_gpio.h b/Libs/platform/emlib/inc/em_gpio.h new file mode 100644 index 0000000..9bca763 --- /dev/null +++ b/Libs/platform/emlib/inc/em_gpio.h @@ -0,0 +1,1380 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPIO_H +#define EM_GPIO_H + +#include "em_device.h" +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "sl_enum.h" + +#if defined(SL_CATALOG_GPIO_PRESENT) +#include "sl_device_gpio.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#ifdef gpioPortA +#undef gpioPortA +#endif + +#ifdef gpioPortB +#undef gpioPortB +#endif + +#ifdef gpioPortC +#undef gpioPortC +#endif + +#ifdef gpioPortD +#undef gpioPortD +#endif + +#ifdef gpioPortE +#undef gpioPortE +#endif + +#ifdef gpioPortF +#undef gpioPortF +#endif + +#ifdef gpioPortG +#undef gpioPortG +#endif + +#ifdef gpioPortH +#undef gpioPortH +#endif + +#ifdef gpioPortI +#undef gpioPortI +#endif + +#ifdef gpioPortJ +#undef gpioPortJ +#endif + +#ifdef gpioPortK +#undef gpioPortK +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_HAPPY_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 4 +#define _GPIO_PORT_E_PIN_COUNT 4 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x0707UL +#define _GPIO_PORT_B_PIN_MASK 0x6980UL +#define _GPIO_PORT_C_PIN_MASK 0xEF1FUL +#define _GPIO_PORT_D_PIN_MASK 0x00F0UL +#define _GPIO_PORT_E_PIN_MASK 0x3C00UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x1FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_GECKO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x03FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFC0UL +#define _GPIO_PORT_C_PIN_MASK 0x0FFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFF00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x000FUL +#define _GPIO_PORT_J_PIN_MASK 0xC000UL +#define _GPIO_PORT_K_PIN_MASK 0x0007UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 15 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x7FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 16 +#define _GPIO_PORT_H_PIN_COUNT 16 +#define _GPIO_PORT_I_PIN_COUNT 16 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_H_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_I_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_32B_SERIES_2) + +#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT +#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT +#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT +#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 0 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) +#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) +#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) +#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x0000UL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#else +#warning "Port and pin masks are not defined for this family." +#endif + +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ + : 0) + +#define _GPIO_PORT_MASK(port) ( \ + ((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ + : 0UL) + +/** Validation of port and pin. */ +#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) +#define GPIO_PORT_PIN_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) + +#if defined(_GPIO_EXTIPINSELL_MASK) +/** Validation of interrupt number and pin. */ +#define GPIO_INTNO_PIN_VALID(intNo, pin) \ + (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ + == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) +#endif + +/** Highest GPIO pin number. */ +#define GPIO_PIN_MAX 15 + +/** Highest GPIO port number. */ +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define GPIO_PORT_MAX 10 +#elif (_GPIO_PORT_J_PIN_COUNT > 0) +#define GPIO_PORT_MAX 9 +#elif (_GPIO_PORT_I_PIN_COUNT > 0) +#define GPIO_PORT_MAX 8 +#elif (_GPIO_PORT_H_PIN_COUNT > 0) +#define GPIO_PORT_MAX 7 +#elif (_GPIO_PORT_G_PIN_COUNT > 0) +#define GPIO_PORT_MAX 6 +#elif (_GPIO_PORT_F_PIN_COUNT > 0) +#define GPIO_PORT_MAX 5 +#elif (_GPIO_PORT_E_PIN_COUNT > 0) +#define GPIO_PORT_MAX 4 +#elif (_GPIO_PORT_D_PIN_COUNT > 0) +#define GPIO_PORT_MAX 3 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +/** Highest EXT GPIO interrupt number. */ +#define GPIO_EXTINTNO_MAX 15 + +/***************************************************************************//** + * @addtogroup gpio + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** GPIO ports IDs. */ +SL_ENUM(GPIO_Port_TypeDef) { +#if (_GPIO_PORT_A_PIN_COUNT > 0) + /** Port A. */ + gpioPortA = 0, +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) + /** Port B. */ + gpioPortB = 1, +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) + /** Port C. */ + gpioPortC = 2, +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) + /** Port D. */ + gpioPortD = 3, +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) + /** Port E. */ + gpioPortE = 4, +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) + /** Port F. */ + gpioPortF = 5, +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) + /** Port G. */ + gpioPortG = 6, +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) + /** Port H. */ + gpioPortH = 7, +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) + /** Port I. */ + gpioPortI = 8, +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) + /** Port J. */ + gpioPortJ = 9, +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) + /** Port K. */ + gpioPortK = 10, +#endif +}; + +/** Mapping between SL_GPIO_PORT_ enums and gpioPort values. */ +#if !defined(SL_CATALOG_GPIO_PRESENT) +#if (_GPIO_PORT_A_PIN_COUNT > 0) +#define SL_GPIO_PORT_A gpioPortA +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) +#define SL_GPIO_PORT_B gpioPortB +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) +#define SL_GPIO_PORT_C gpioPortC +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) +#define SL_GPIO_PORT_D gpioPortD +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) +#define SL_GPIO_PORT_E gpioPortE +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) +#define SL_GPIO_PORT_F gpioPortF +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) +#define SL_GPIO_PORT_G gpioPortG +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) +#define SL_GPIO_PORT_H gpioPortH +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) +#define SL_GPIO_PORT_I gpioPortI +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) +#define SL_GPIO_PORT_J gpioPortJ +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define SL_GPIO_PORT_K gpioPortK +#endif +#endif // !defined(SL_CATALOG_GPIO_PRESENT) + +#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) +/** GPIO drive mode. */ +SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { + /** Default 6mA. */ + gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, + /** 0.5 mA. */ + gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, + /** 20 mA. */ + gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, + /** 2 mA. */ + gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW +}; +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) +/** GPIO drive strength. */ +SL_ENUM_GENERIC(GPIO_DriveStrength_TypeDef, uint32_t) { + /** GPIO weak 1mA and alternate function weak 1mA. */ + gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO weak 1mA and alternate function strong 10mA. */ + gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, + + /** GPIO strong 10mA and alternate function weak 1mA. */ + gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO strong 10mA and alternate function strong 10mA. */ + gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, +}; + +/* Deprecated enums. */ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong +#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak +/** @endcond */ +#endif + +/** Pin mode. For more details on each mode, refer to the + * reference manual. */ +SL_ENUM_GENERIC(GPIO_Mode_TypeDef, uint32_t) { + /** Input disabled. Pull-up if DOUT is set. */ + gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, + /** Input enabled. Filter if DOUT is set. */ + gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, + /** Input enabled. DOUT determines pull direction. */ + gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, + /** Input enabled with filter. DOUT determines pull direction. */ + gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, + /** Push-pull output. */ + gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) + /** Push-pull output with drive-strength set by DRIVEMODE. */ + gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + /** Push-pull using alternate control. */ + gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, +#endif + /** Wired-or output. */ + gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, + /** Wired-or output with pull-down. */ + gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, + /** Open-drain output. */ + gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, + /** Open-drain output with filter. */ + gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, + /** Open-drain output with pull-up. */ + gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, + /** Open-drain output with filter and pull-up. */ + gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) + /** Open-drain output with drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, + /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, + /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, + /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + /** Open-drain output using alternate control. */ + gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, + /** Open-drain output using alternate control with filter. */ + gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, + /** Open-drain output using alternate control with pull-up. */ + gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, + /** Open-drain output using alternate control with filter and pull-up. */ + gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, +#endif +}; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void GPIO_DbgLocationSet(unsigned int location); + +/***************************************************************************//** + * @brief + * Enable/disable serial wire clock pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire clock. + * @li true - enable serial wire clock (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWCLKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWCLK pin is not defined." +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable serial wire data I/O pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire data pin. + * @li true - enable serial wire data pin (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWDIOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWDIO pin is not defined." +#endif +} + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ + || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) +/***************************************************************************//** + * @brief + * Enable/Disable serial wire output pin. + * + * @note + * Enabling this pin is not sufficient to fully enable serial wire output, + * which is also dependent on issues outside the GPIO module. Refer to + * DBG_SWOEnable(). + * + * @warning + * If debug port is locked, SWO pin is not disabled automatically. To avoid + * information leakage through SWO, disable SWO pin after locking debug port. + * + * @param[in] enable + * @li false - disable serial wire viewer pin (default after reset). + * @li true - enable serial wire viewer pin. + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); +#elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWO/SWV pin is not defined." +#endif +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Disable GPIO pin wake-up from EM4. + * + * @param[in] pinmask + * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. + * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); + + GPIO->EM4WUEN &= ~pinmask; +} +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); +#endif + +#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) +/**************************************************************************//** + * @brief + * Check which GPIO pin(s) that caused a wake-up from EM4. + * + * @return + * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the + * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) +{ +#if defined(_GPIO_EM4WUCAUSE_MASK) + return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; +#else + return GPIO->IF & _GPIO_IF_EM4WU_MASK; +#endif +} +#endif + +#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin retention of output enable, output value, pull enable, and + * pull direction in EM4. + * + * @note + * On series 0 devices EM4 gpio retention can either be turned on or off. On + * series 1 devices there are three EM4 GPIO retention modes available. These + * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the EMU_EM4Init() + * to configure the GPIO retention mode on a series 1 device. + * + * The behavior of this function depends on the configured GPIO retention mode. + * If the GPIO retention mode is configured to be "SWUNLATCH" then this + * function will not change anything. If the retention mode is anything else + * then this function will set the GPIO retention mode to "EM4EXIT" when the + * enable argument is true, and "Disabled" when false. + * + * @param[in] enable + * @li true - enable EM4 pin retention. + * @li false - disable EM4 pin retention. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) +{ +#if defined(GPIO_CTRL_EM4RET) + BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); +#else + + // Leave configuration alone when software unlatch is used. + uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; + if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { + return; + } + + if (enable) { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; + } else { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_DISABLE; + } +#endif +} +#endif + +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable); + +#if _SILICON_LABS_32B_SERIES > 0 +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable); +#endif +/***************************************************************************//** + * @brief + * Enable/disable input sensing. + * + * @details + * Disabling input sensing if not used, can save some energy consumption. + * + * @param[in] val + * Bitwise logic OR of one or more of: + * @li GPIO_INSENSE_INT - interrupt input sensing. + * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. + * + * @param[in] mask + * Mask containing bitwise logic OR of bits similar as for @p val used to + * indicate which input sense options to disable/enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) +{ +#if defined(_GPIO_INSENSE_MASK) + BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); +#else + (void) val; + (void) mask; +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending GPIO interrupts. + * + * @param[in] flags + * Bitwise logic OR of GPIO interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntClear(uint32_t flags) +{ +#if defined(GPIO_HAS_SET_CLEAR) + GPIO->IF_CLR = flags; +#else + GPIO->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more GPIO interrupts. + * + * @param[in] flags + * GPIO interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntDisable(uint32_t flags) +{ + BUS_RegMaskedClear(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Enable one or more GPIO interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * GPIO_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * GPIO interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntEnable(uint32_t flags) +{ + BUS_RegMaskedSet(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Get enabled GPIO interrupts. + * + * @return + * Enabled GPIO interrupt sources. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EnabledIntGet(void) +{ + return GPIO->IEN; +} + +/***************************************************************************//** + * @brief + * Get pending GPIO interrupts. + * + * @return + * GPIO interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGet(void) +{ + return GPIO->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending GPIO interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled GPIO interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in GPIO_IEN register + * and + * - the OR combination of valid interrupt flags in GPIO_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Store GPIO->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = GPIO->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return GPIO->IF & tmp; +} + +/**************************************************************************//** + * @brief + * Set one or more pending GPIO interrupts from SW. + * + * @param[in] flags + * GPIO interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void GPIO_IntSet(uint32_t flags) +{ +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->IF_SET = flags; +#else + GPIO->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Lock(void) +{ + GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Read the pad value for a single pin in a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to read. + * + * @return + * The pin value, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DIN, pin); +} + +#if defined (_GPIO_P_PINLOCKN_MASK) +/***************************************************************************//** + * @brief + * Lock all GPIO configuration settings for a given pin. + * The lock can only be cleared by a chip reset. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to lock. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) +{ + BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); +} +#endif + +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin); + +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out); + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out port register to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Get current setting for a pin in a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to get setting for. + * + * @return + * The DOUT setting for the requested pin, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); +} + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Toggle a single pin in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + +#if defined (_GPIO_P_DOUTTGL_MASK) + GPIO->P[port].DOUTTGL = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = 1UL << pin; +#else + GPIO->P[port].DOUT ^= 1UL << pin; +#endif +} + +/***************************************************************************//** + * @brief + * Read the pad values for GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The pad values for the GPIO port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DIN; +} + +/***************************************************************************//** + * @brief + * Set bits in DOUT register for a port to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to clear in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = pins; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current setting for a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The data out setting for the requested port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DOUT; +} + +/***************************************************************************//** + * @brief + * Set bits GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to set to 1 in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = pins; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Set GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] val + * Value to write to port data out register. + * + * @param[in] mask + * Mask indicating which bits to modify. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, + uint32_t val, + uint32_t mask) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); +} + +/***************************************************************************//** + * @brief + * Toggle pins in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask with pins to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = pins; +#else + GPIO->P[port].DOUTTGL = pins; +#endif +} + +#if defined(_GPIO_P_CTRL_SLEWRATE_MASK) +/***************************************************************************//** + * @brief + * Set slewrate for pins on a GPIO port. + * + * @param[in] port + * The GPIO port to configure. + * + * @param[in] slewrate + * The slewrate to configure for pins on this GPIO port. + * + * @param[in] slewrateAlt + * The slewrate to configure for pins using alternate modes on this GPIO port. + ******************************************************************************/ +__STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, + uint32_t slewrate, + uint32_t slewrateAlt) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK + >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); + EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK + >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK)) + | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) + | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); +} +#endif + +/***************************************************************************//** + * @brief + * Unlock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Unlock(void) +{ + GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/** @} (end addtogroup gpio) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ +#endif /* EM_GPIO_H */ diff --git a/Libs/platform/emlib/inc/em_i2c.h b/Libs/platform/emlib/inc/em_i2c.h new file mode 100644 index 0000000..74feec9 --- /dev/null +++ b/Libs/platform/emlib/inc/em_i2c.h @@ -0,0 +1,525 @@ +/***************************************************************************//** + * @file + * @brief Inter-integrated circuit (I2C) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_I2C_H +#define EM_I2C_H + +#include "em_device.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup i2c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, + * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use + * worst case value of Tlow or Thigh as base. + * + * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz + * @note + * Due to chip characteristics, max value is somewhat reduced. + */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 93000 +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_1) +// None of the chips on this platform has been characterized on this parameter. +// Use same value as on Wonder until further notice. +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_FREQ_STANDARD_MAX 100000 +#else +#error "Unknown device family." +#endif + +/** + * @brief + * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, + * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use + * worst case value of Tlow or 2xThigh as base. + * + * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz + */ +#define I2C_FREQ_FAST_MAX 392157 + +/** + * @brief + * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, + * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use + * worst case value of Tlow or (11/6)xThigh as base. + * + * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz + */ +#define I2C_FREQ_FASTPLUS_MAX 987167 + +/** + * @brief + * Indicate plain write sequence: S+ADDR(W)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(W) - address with W/R bit cleared + * @li DATA0 - Data taken from buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_WRITE 0x0001 + +/** + * @brief + * Indicate plain read sequence: S+ADDR(R)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(R) - Address with W/R bit set + * @li DATA0 - Data read into buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_READ 0x0002 + +/** + * @brief + * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. + * @details + * @li S - Start + * @li Sr - Repeated start + * @li ADDR(W) - Address with W/R bit cleared + * @li ADDR(R) - Address with W/R bit set + * @li DATAn - Data written from/read into buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_READ 0x0004 + +/** + * @brief + * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. + * @details + * @li S - Start + * @li ADDR(W) - Address with W/R bit cleared + * @li DATAn - Data written from buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_WRITE 0x0008 + +/** Use 10 bit address. */ +#define I2C_FLAG_10BIT_ADDR 0x0010 + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock low to high ratio settings. */ +typedef enum { + i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ + i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ + i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ +} I2C_ClockHLR_TypeDef; + +/** Return codes for single Controller mode transfer function. */ +typedef enum { + /* In progress code (>0) */ + i2cTransferInProgress = 1, /**< Transfer in progress. */ + + /* Complete code (=0) */ + i2cTransferDone = 0, /**< Transfer completed successfully. */ + + /* Transfer error codes (<0). */ + i2cTransferNack = -1, /**< NACK received during transfer. */ + i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ + i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ + i2cTransferUsageFault = -4, /**< Usage fault. */ + i2cTransferSwFault = -5 /**< SW fault. */ +} I2C_TransferReturn_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** I2C initialization structure. */ +typedef struct { + /** Enable I2C peripheral when initialization completed. */ + bool enable; + + /** Set to Controller (true) or Target (false) mode */ + bool master; + + /** + * I2C reference clock assumed when configuring bus frequency setup. + * Set it to 0 if currently configured reference clock will be used + * This parameter is only applicable if operating in Controller mode. + */ + uint32_t refFreq; + + /** + * (Max) I2C bus frequency to use. This parameter is only applicable + * if operating in Controller mode. + */ + uint32_t freq; + + /** Clock low/high ratio control. */ + I2C_ClockHLR_TypeDef clhr; +} I2C_Init_TypeDef; + +/** Suggested default configuration for I2C initialization structure. */ +#define I2C_INIT_DEFAULT \ + { \ + true, /* Enable when initialization done. */ \ + true, /* Set to Controller mode. */ \ + 0, /* Use currently configured reference clock. */ \ + I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ + /* within I2C specification. */ \ + i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ + } + +/** + * @brief + * Master mode transfer message structure used to define a complete + * I2C transfer sequence (from start to stop). + * @details + * The structure allows for defining the following types of sequences + * (refer to defines for sequence details): + * @li #I2C_FLAG_READ - Data read into buf[0].data + * @li #I2C_FLAG_WRITE - Data written from buf[0].data + * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read + * into buf[1].data + * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and + * buf[1].data + */ +typedef struct { + /** + * @brief + * Address to use after (repeated) start. + * @details + * Layout details, A = Address bit, X = don't care bit (set to 0): + * @li 7 bit address - Use format AAAA AAAX + * @li 10 bit address - Use format XXXX XAAX AAAA AAAA + */ + uint16_t addr; + + /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ + uint16_t flags; + + /** + * Buffers used to hold data to send from or receive into, depending + * on sequence type. + */ + struct { + /** Buffer used for data to transmit/receive, must be @p len long. */ + uint8_t *data; + + /** + * Number of bytes in @p data to send or receive. Notice that when + * receiving data to this buffer, at least 1 byte must be received. + * Setting @p len to 0 in the receive case is considered a usage fault. + * Transmitting 0 bytes is legal, in which case only the address + * is transmitted after the start condition. + */ + uint16_t len; + } buf[2]; +} I2C_TransferSeq_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode); +void I2C_Enable(I2C_TypeDef *i2c, bool enable); +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_CLR = flags; +#else + i2c->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_CLR = flags; +#else + i2c->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more I2C interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * I2C_IntClear() prior to enabling the interrupt. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_SET = flags; +#else + i2c->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending I2C interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) +{ + return i2c->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending I2C interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * Pending and enabled I2C interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in I2Cn_IEN and + * - the pending interrupt flags I2Cn_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) +{ + uint32_t ien; + + ien = i2c->IEN; + return i2c->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending I2C interrupts from SW. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_SET = flags; +#else + i2c->IFS = flags; +#endif +} + +void I2C_Reset(I2C_TypeDef *i2c); + +/***************************************************************************//** + * @brief + * Get Target address used for I2C peripheral (when operating in Target mode). + * + * @details + * For 10-bit addressing mode, the address is split in two bytes, and only + * the first byte setting is fetched, effectively only controlling the 2 most + * significant bits of the 10-bit address. Full handling of 10-bit addressing + * in Target mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address in use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDR)); +} + +/***************************************************************************//** + * @brief + * Set Target address to use for I2C peripheral (when operating in Target mode). + * + * @details + * For 10- bit addressing mode, the address is split in two bytes, and only + * the first byte is set, effectively only controlling the 2 most significant + * bits of the 10-bit address. Full handling of 10-bit addressing in Target + * mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] addr + * I2C Target address to use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always set to 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) +{ + i2c->SADDR = (uint32_t)addr & 0xfe; +} + +/***************************************************************************//** + * @brief + * Get Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is fetched, effectively only + * controlling the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address mask in use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and always + * returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDRMASK)); +} + +/***************************************************************************//** + * @brief + * Set Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is set, effectively only controlling + * the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] mask + * I2C Target address mask to use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and should + * be 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) +{ + i2c->SADDRMASK = (uint32_t)mask & 0xfe; +} + +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq); + +/** @} (end addtogroup i2c) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ +#endif /* EM_I2C_H */ diff --git a/Libs/platform/emlib/inc/em_iadc.h b/Libs/platform/emlib/inc/em_iadc.h new file mode 100644 index 0000000..2b62fa2 --- /dev/null +++ b/Libs/platform/emlib/inc/em_iadc.h @@ -0,0 +1,1407 @@ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_IADC_H +#define EM_IADC_H + +#include "em_device.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iadc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Warm-up mode. */ +typedef enum { + /** IADC shutdown after each conversion. */ + iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL, + + /** ADC is kept in standby mode between conversion. */ + iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY, + + /** ADC and reference selected for scan mode kept warmup, allowing + continuous conversion. */ + iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM +} IADC_Warmup_t; + +/** IADC result alignment. */ +typedef enum { + /** IADC results 12-bit right aligned */ + iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12, + + /** IADC results 12-bit left aligned */ + iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12, + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + /** IADC results 16-bit right aligned */ + iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16, + + /** IADC results 16-bit left aligned */ + iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16, +#endif + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + /** IADC results 20-bit right aligned */ + iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20, + + /** IADC results 20-bit left aligned */ + iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20, +#endif +} IADC_Alignment_t; + +/** IADC negative input selection. */ +typedef enum { + /** Ground */ + iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)) + | 1, + /** Ground using even mux */ + iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + +#if defined(_IADC_SCAN_PORTNEG_DAC1) + /** Direct connection to DAC_1 input pin */ + iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA1) + /** Direct connection to Pad_ana_1 input pin */ + iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA3) + /** Direct connection to Pad_ana_3 input pin */ + iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADREFNEG) + /** Negative reference pin 0 */ + iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif + /** GPIO port A pin 0 */ + iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + + /** GPIO port A pin 1 */ + iadcNegInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcNegInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcNegInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcNegInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcNegInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcNegInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcNegInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcNegInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcNegInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcNegInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcNegInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcNegInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcNegInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcNegInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcNegInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcNegInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcNegInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcNegInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcNegInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcNegInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcNegInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcNegInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcNegInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcNegInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcNegInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcNegInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcNegInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcNegInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcNegInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcNegInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcNegInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcNegInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcNegInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcNegInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcNegInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcNegInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcNegInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcNegInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcNegInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcNegInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcNegInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcNegInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcNegInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcNegInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcNegInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcNegInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcNegInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcNegInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcNegInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcNegInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcNegInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcNegInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcNegInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcNegInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcNegInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcNegInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcNegInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcNegInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcNegInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcNegInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcNegInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcNegInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcNegInputPortDPin15 +} IADC_NegInput_t; + +/** IADC positive port selection. */ +typedef enum { + /** Ground */ + iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** Avdd / 4 */ + iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 0, + + /** Vddio / 4 */ + iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 1, + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + /** Vddio1 / 4 */ + iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vddio2 / 4 */ + iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + /** Vbat /4 */ + iadcPosInputVbat = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vss */ + iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#else + /** Vss */ + iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vss */ + iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#endif + + /** Dvdd / 4 */ + iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 4, + + /** Decouple */ + iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 7, + +#if defined(_IADC_SCAN_PORTPOS_DAC0) + /** Direct connection to DAC_0 input pin */ + iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA0) + /** Direct connection to Pad_ana_0 input pin */ + iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA2) + /** Direct connection to Pad_ana_2 input pin */ + iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADREFPOS) + /** Positive reference pin 0 */ + iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif + + /** GPIO port A pin 0 */ + iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** GPIO port A pin 1 */ + iadcPosInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcPosInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcPosInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcPosInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcPosInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcPosInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcPosInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcPosInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcPosInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcPosInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcPosInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcPosInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcPosInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcPosInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcPosInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcPosInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcPosInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcPosInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcPosInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcPosInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcPosInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcPosInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcPosInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcPosInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcPosInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcPosInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcPosInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcPosInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcPosInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcPosInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcPosInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcPosInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcPosInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcPosInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcPosInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcPosInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcPosInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcPosInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcPosInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcPosInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcPosInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcPosInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcPosInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcPosInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcPosInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcPosInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcPosInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcPosInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcPosInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcPosInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcPosInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcPosInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcPosInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcPosInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcPosInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcPosInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcPosInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcPosInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcPosInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcPosInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcPosInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcPosInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcPosInputPortDPin15 +} IADC_PosInput_t; + +/** IADC Commands. */ +typedef enum { + /** Start single queue */ + iadcCmdStartSingle = IADC_CMD_SINGLESTART, + + /** Stop single queue */ + iadcCmdStopSingle = IADC_CMD_SINGLESTOP, + + /** Start scan queue */ + iadcCmdStartScan = IADC_CMD_SCANSTART, + + /** Stop scan queue */ + iadcCmdStopScan = IADC_CMD_SCANSTOP, + + /** Enable Timer */ + iadcCmdEnableTimer = IADC_CMD_TIMEREN, + + /** Disable Timer */ + iadcCmdDisableTimer = IADC_CMD_TIMERDIS +} IADC_Cmd_t; + +/** IADC Configuration. */ +typedef enum { + /** Normal mode */ + iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL, +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + /** High Speed mode */ + iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED, +#endif +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + /** High Accuracy mode */ + iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY +#endif +} IADC_CfgAdcMode_t; + +/** IADC Over sampling rate for high speed. */ +typedef enum { + /** High speed oversampling of 2x */ + iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2, + + /** High speed oversampling of 4x */ + iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4, + + /** High speed oversampling of 8x */ + iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8, + + /** High speed oversampling of 16x */ + iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16, + + /** High speed oversampling of 32x */ + iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32, + + /** High speed oversampling of 64x */ + iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64 +} IADC_CfgOsrHighSpeed_t; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** IADC Over sampling rate for high accuracy. */ +typedef enum { + /** High accuracy oversampling of 16x */ + iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16, + + /** High accuracy oversampling of 32x */ + iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32, + + /** High accuracy oversampling of 64x */ + iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64, + + /** High accuracy oversampling of 92x */ + iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92, + + /** High accuracy oversampling of 128x */ + iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128, + + /** High accuracy oversampling of 256x */ + iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256 +} IADC_CfgOsrHighAccuracy_t; +#endif + +/** IADC Analog Gain. */ +typedef enum { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + /** Analog gain of 0.25x */ + iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25, +#endif + /** Analog gain of 0.5x */ + iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5, + + /** Analog gain of 1x */ + iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1, + + /** Analog gain of 2x */ + iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2, + + /** Analog gain of 3x */ + iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3, + + /** Analog gain of 4x */ + iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4 +} IADC_CfgAnalogGain_t; + +/** IADC Reference */ +typedef enum { + /** Internal 1.2V Band Gap Reference (buffered) to ground */ + iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, + + /** External reference (unbuffered) VREFP to VREFN. + * VEVREF up to AVDD. When inputs are routed to external GPIO pins, + * the maximum pin voltage is limited to the lower + * of the IOVDD and AVDD supplies. + * The internal calibration values correspond to a 1.25V reference, + * use of other voltages may require recalibration. + * See AN1189: Incremental Analog to Digital Converter (IADC) */ + iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, + +#if defined(_IADC_CFG_REFSEL_VREF2P5) + /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ + iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, +#endif + + /** VDDX (unbuffered) to ground. */ + iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX, + + /** 0.8 * VDDX (buffered) to ground. */ + iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF, + +#if defined(_IADC_CFG_REFSEL_VREFBUF) + /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */ + iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF, +#endif + +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */ + iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF, +#endif +} IADC_CfgReference_t; + +/** IADC Two's complement results */ +typedef enum { + /** Automatic. Single ended => Unipolar, Differential => Bipolar */ + iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO, + + /** All results in unipolar format. Negative diff input gives 0 as result. */ + iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR, + + /** All results in bipolar (2's complement) format. Half range for SE. */ + iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR +} IADC_CfgTwosComp_t; + +/** IADC trigger action */ +typedef enum { + /** Start single/scan queue immediately */ + iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE, + + /** Timer starts single/scan queue */ + iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER, + + /** PRS0 from timer in same clock group starts single/scan queue */ + iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP, + + /** PRS0 positive edge starts single/scan queue */ + iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS, + + /** PRS0 negative edge starts single/scan queue */ + iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG, + +#if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE) + /** LESENSE starts scan queue */ + iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE +#endif +} IADC_TriggerSel_t; + +/** IADC trigger action */ +typedef enum { + /** Convert single/scan queue once per trigger */ + iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE, + + /** Convert single/scan queue continuously */ + iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS, +} IADC_TriggerAction_t; + +/** IADC data valid level before requesting DMA transfer */ +typedef enum { + /** Data valid level is 1 before requesting DMA transfer */ + iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1, + + /** Data valid level is 2 before requesting DMA transfer */ + iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2, + + /** Data valid level is 3 before requesting DMA transfer */ + iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3, + + /** Data valid level is 4 before requesting DMA transfer */ + iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4, + +#if !(defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 2 + /** Data valid level is 5 before requesting DMA transfer */ + iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5, + + /** Data valid level is 6 before requesting DMA transfer */ + iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6, + + /** Data valid level is 7 before requesting DMA transfer */ + iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7, +#endif + +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 3 + /** Data valid level is 8 before requesting DMA transfer */ + iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8 +#endif +#endif +} IADC_FifoCfgDvl_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +/** IADC digital averaging function. */ +typedef enum { + /** Average over 1 sample (no averaging). */ + iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1, + + /** Average over 2 samples. */ + iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2, + + /** Average over 4 samples. */ + iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4, + + /** Average over 8 samples. */ + iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8, + + /** Average over 16 samples. */ + iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16 +} IADC_DigitalAveraging_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** IADC init structure, common for single conversion and scan sequence. */ +typedef struct { + bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */ + bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */ + bool debugHalt; /**< Halt IADC during debug mode. */ + IADC_Warmup_t warmup; /**< IADC warmup mode. */ + uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us. + Used as time reference for IADC delays, e.g. warmup. + If the user sets timebase to 0, then IADC_Init() will + calculate the timebase using the currently defined CMU + clock setting for the IADC. */ + uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which + will be used if the calculated prescaler value is less. */ + uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */ + uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */ + uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */ +} IADC_Init_t; + +/** Default config for IADC init structure. */ +#define IADC_INIT_DEFAULT \ + { \ + false, /* IADC clock not disabled on PRS0*/ \ + false, /* IADC clock not disabled on PRS1 */ \ + false, /* Do not halt during debug */ \ + iadcWarmupNormal, /* IADC shutdown after each conversion. */ \ + 0, /* Calculate timebase. */ \ + 0, /* Max IADC clock rate. */ \ + _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \ + } + +/** IADC config structure */ +typedef struct { + IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */ + IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */ +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */ +#endif + IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */ + IADC_CfgReference_t reference; /**< Reference selection. */ + IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */ + uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */ + uint32_t vRef; /**< Vref magnitude expressed in millivolts. */ +#if defined(_IADC_CFG_DIGAVG_MASK) + IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */ +#endif +} IADC_Config_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#endif +#else +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#endif +#endif + +/** Structure for all IADC configs. */ +typedef struct { + /** All IADC configs. */ + IADC_Config_t configs[IADC0_CONFIGNUM]; +} IADC_AllConfigs_t; + +/** Default IADC sructure for all configs. */ +#define IADC_ALLCONFIGS_DEFAULT \ + { \ + { \ + IADC_CONFIG_DEFAULT, \ + IADC_CONFIG_DEFAULT \ + } \ + } + +/** IADC scan init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with scan table entry id. */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool start; /**< Start scan immediately. */ +} IADC_InitScan_t; + +/** Default config for IADC scan init structure. */ +#define IADC_INITSCAN_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on scan FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on scan trigger */ \ + false /* Do not start scan queue */ \ + } + +/** IADC single init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with single indicator (0x20). */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool singleTailgate; /**< If true, wait until end of SCAN queue + before single queue warmup and conversion. */ + bool start; /**< Start scan immediately. */ +} IADC_InitSingle_t; + +/** Default config for IADC single init structure. */ +#define IADC_INITSINGLE_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on single FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start single immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on single trigger */ \ + false, /* No tailgating */ \ + false /* Do not start single queue */ \ + } + +/** IADC single input selection structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ +} IADC_SingleInput_t; + +/** Default config for IADC single input structure. */ +#define IADC_SINGLEINPUT_DEFAULT \ + { \ + iadcNegInputGnd, /* Negative input GND */ \ + iadcPosInputGnd, /* Positive input GND */ \ + 0, /* Config 0 */ \ + false /* Do not compare results */ \ + } + +/** IADC scan table entry structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ + bool includeInScan; /**< Include this scan table entry in scan operation. */ +} IADC_ScanTableEntry_t; + +/** Default config for IADC scan table entry structure. */ +#define IADC_SCANTABLEENTRY_DEFAULT \ + { \ + iadcNegInputGnd,/* Negative input GND */ \ + iadcPosInputGnd,/* Positive input GND */ \ + 0, /* Config 0 */ \ + false, /* Do not compare results */ \ + false /* Do not include in scan */ \ + } + +/** Structure for IADC scan table. */ +typedef struct { + /** IADC scan table entries. */ + IADC_ScanTableEntry_t entries[IADC0_ENTRIES]; +} IADC_ScanTable_t; + +/** Default IADC structure for scan table */ +#define IADC_SCANTABLE_DEFAULT \ + { \ + { \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT \ + } \ + } + +/** Structure holding IADC result, including data and ID */ +typedef struct { + uint32_t data; /**< ADC sample data. */ + uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */ +} IADC_Result_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs); +void IADC_reset(IADC_TypeDef *iadc); +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable); +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry); +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask); +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input); +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input); +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq); +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler); +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq); +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc); +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference); + +/***************************************************************************//** + * @brief + * Pull data from single data FIFO. If showId was set when initializing + * single mode, the results will contain the ID (0x20). + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion data. If showId was set when + * initializing single mode, the data will contain the ID (0x20). Calling + * this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEDATA; +} + +/***************************************************************************//** + * @brief + * Pull data from scan data FIFO. If showId was set for the scan entry + * initialization, the data will contain the ID of the scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc) +{ + return iadc->SCANFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion data. If showId was set for the scan + * entry initialization, the data will contain the ID of the scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc) +{ + return iadc->SCANDATA; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * Pending IADC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags) +{ +#if defined (IADC_HAS_SET_CLEAR) + iadc->IEN_CLR = flags; +#else + iadc->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more IADC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using IADC_intClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending IADC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc) +{ + return iadc->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending IADC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Pending and enabled IADC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn + * register (IADCx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the IADC module + * (IADCx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc) +{ + uint32_t ien; + + /* Store IADCx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = iadc->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return iadc->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending IADC interrupts from SW. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Start/stop scan sequence, single conversion and/or timer. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] cmd + * Command to be performed. + ******************************************************************************/ +__STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd) +{ + iadc->CMD = (uint32_t)cmd; +} + +/***************************************************************************//** + * @brief + * Get the scan mask currently used in the IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Mask of scan table entries currently included in scan. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc) +{ + return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT; +} + +/***************************************************************************//** + * @brief + * Get status bits of IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc) +{ + return iadc->STATUS; +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC single FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in single FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC scan FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in scan FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC negative input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC negative input selection + ******************************************************************************/ +__STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin; + + return (IADC_NegInput_t) input; +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC positive input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC positive input selection + ******************************************************************************/ +__STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin; + + return (IADC_PosInput_t) input; +} + +/** @} (end addtogroup iadc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ +#endif /* EM_IADC_H */ diff --git a/Libs/platform/emlib/inc/em_ldma.h b/Libs/platform/emlib/inc/em_ldma.h new file mode 100644 index 0000000..7b81b75 --- /dev/null +++ b/Libs/platform/emlib/inc/em_ldma.h @@ -0,0 +1,2824 @@ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LDMA_H +#define EM_LDMA_H + +#include "em_device.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup ldma LDMA - Linked DMA + * @brief Linked Direct Memory Access (LDMA) Peripheral API + * + * @details + * LDMA API functions provide full support for the LDMA peripheral. + * + * LDMA supports these DMA transfer types: + * + * @li Memory to memory. + * @li Memory to peripheral. + * @li Peripheral to memory. + * @li Peripheral to peripheral. + * @li Constant value to memory. + * + * LDMA supports linked lists of DMA descriptors allowing: + * + * @li Circular and ping-pong buffer transfers. + * @li Scatter-gather transfers. + * @li Looped transfers. + * + * LDMA has some advanced features: + * + * @li Intra-channel synchronization (SYNC), allowing hardware events to + * pause and restart a DMA sequence. + * @li Immediate-write (WRI), allowing DMA to write a constant anywhere + * in the memory map. + * @li Complex flow control allowing if-else constructs. + * + * Basic understanding of LDMA controller is assumed. Please refer to + * the reference manual for further details. The LDMA examples described + * in the reference manual are particularly helpful in understanding LDMA + * operations. + * + * In order to use the DMA controller, the initialization function @ref + * LDMA_Init() must have been executed once (normally during system initialization). + * + * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), + * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t + * and @ref LDMA_Descriptor_t structure parameters. + * The LDMA_Descriptor_t structure parameter may be a + * pointer to an array of descriptors, descriptors in array should + * be linked together as needed. + * + * Transfer and descriptor initialization macros are provided for the most common + * transfer types. Due to the flexibility of LDMA peripheral, only a small + * subset of all possible initializer macros are provided, users should create + * new ones when needed. + * + * Examples of LDMA usage: + * + * A simple memory to memory transfer: + * + * @include em_ldma_single.c + * + * @n A linked list of three memory to memory transfers: + * + * @include em_ldma_link_memory.c + * + * @n DMA from serial port peripheral to memory: + * + * @include em_ldma_peripheral.c + * + * @n Ping-pong DMA from serial port peripheral to memory: + * + * @include em_ldma_pingpong.c + * + * @note LDMA module does not implement LDMA interrupt handler. A + * template for an LDMA IRQ handler is included here as an example. + * + * @include em_ldma_irq.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** + * Controls the number of unit data transfers per arbitration + * cycle, providing a means to balance DMA channels' load on the controller. + */ +typedef enum { + ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ + ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ + ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ + ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ + ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ + ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ + ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ + ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ +} LDMA_CtrlBlockSize_t; + +/** DMA structure type. */ +typedef enum { + ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ + ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ + ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ +} LDMA_CtrlStructType_t; + +/** DMA transfer block or cycle selector. */ +typedef enum { + ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ + ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ +} LDMA_CtrlReqMode_t; + +/** Source address increment unit size. */ +typedef enum { + ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ + ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ + ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ + ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ +} LDMA_CtrlSrcInc_t; + +/** DMA transfer unit size. */ +typedef enum { + ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ + ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ + ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ +} LDMA_CtrlSize_t; + +/** Destination address increment unit size. */ +typedef enum { + ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ + ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ + ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ + ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ +} LDMA_CtrlDstInc_t; + +/** Source addressing mode. */ +typedef enum { + ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlSrcAddrMode_t; + +/** Destination addressing mode. */ +typedef enum { + ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlDstAddrMode_t; + +/** DMA link load address mode. */ +typedef enum { + ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ + ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ +} LDMA_LinkMode_t; + +/** Insert extra arbitration slots to increase channel arbitration priority. */ +typedef enum { + ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ + ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ + ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ + ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ +} LDMA_CfgArbSlots_t; + +/** Source address increment sign. */ +typedef enum { + ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ + ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ +} LDMA_CfgSrcIncSign_t; + +/** Destination address increment sign. */ +typedef enum { + ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ + ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ +} LDMA_CfgDstIncSign_t; + +#if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK) +/** Structure fetch operation bus port. */ +typedef enum { + ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgStructBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +/** Source operation bus port. */ +typedef enum { + ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgSrcBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK) +/** Destination operation bus port. */ +typedef enum { + ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgDstBusPort_t; +#endif + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** Rules table mode (interleaving destination). */ +typedef enum { + ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */ + ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */ + ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */ +} LDMA_RulesTblMode_t; +#endif + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA + ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 + ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 + ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 + ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF + ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 + ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 + ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 + ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF + ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 + ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 + ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 + ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF + ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD + ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 + ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 + ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 + ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF + ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ) + ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ) + ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ) + ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ) + ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO. + #endif +} LDMA_PeripheralSignal_t; + +#else +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) + ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) + ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) + ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) + ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) + ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) + ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) + ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) + ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) + ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) + ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) + ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) + ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) + ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) + ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) + ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) + ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) + ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) + ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) + ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) + ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) + ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) + ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) + ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) + ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) + ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) + ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) + ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) + ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) + ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) + ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) + ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) + ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) + ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) + ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) + ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) + ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) + ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) + ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) + ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) + ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) + ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) + ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) + ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) + ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) + ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) + ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) + ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) + ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) + ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) + ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) + ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) + ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) + ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) + ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) + ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) + ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) + ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) + ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) + ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) + ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) + ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) + ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) + ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) + ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) + ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) + ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) + ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) + ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) + ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) + ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) + ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) + ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) + ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) + ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) + ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) + ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) + ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) + ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. + #endif +} LDMA_PeripheralSignal_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** + * @brief + * DMA descriptor. + * @details + * The LDMA DMA controller supports three different DMA descriptors. Each + * consists of four WORDs which map directly onto HW control registers for a + * given DMA channel. The three descriptor types are XFER, SYNC and WRI. + * Refer to the reference manual for further information. + */ +typedef union { + /** + * TRANSFER DMA descriptor, this is the only descriptor type which can be + * used to start a DMA transfer. + */ + struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } xfer; + + /** SYNCHRONIZE DMA descriptor, used for intra channel transfer + * synchronization. + */ + struct { + uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t reserved1 : 16; /**< Reserved. */ +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) + uint32_t matchEn : 8; /**< Sync trigger match enable. */ + uint32_t matchVal : 8; /**< Sync trigger match value. */ +#else + uint32_t matchVal : 8; /**< Sync trigger match value. */ + uint32_t matchEn : 8; /**< Sync trigger match enable. */ +#endif + uint32_t reserved2 : 16; /**< Reserved. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } sync; + + /** WRITE DMA descriptor, used for write immediate operations. */ + struct { + uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t immVal; /**< Data to be written at dstAddr. */ + uint32_t dstAddr; /**< DMA write destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } wri; +} LDMA_Descriptor_t; + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA extended descriptor. + * @details + * The extended descriptor adds additional fields for the extended features + * available on the MMLDMA peripheral: destination interleaving and bufferable. + * The same three different DMA descriptors supported by the LDMA DMA controller + * are available. Each consists of seven WORDs (instead of four in non-extended + * descriptors) which map directly onto HW control registers for a given DMA + * channel. The three descriptor types are XFER, SYNC and WRI. But the + * extended fields are true only for XFER. The extended fields are the following: + * + * +- +- CTRL + * | Original | SRC + * | Structure | DST + * Extended | +- LINK + * Structure | XCTRL + * | Reserved for future usage + * +- ILSRC + * + * Refer to the reference manual for further information. + */ +typedef struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t extend : 1; /**< Extend data structure. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + + uint32_t reserved1 : 4; /**< Reserved */ + uint32_t dstIlEn : 1; /**< Destination interleave. */ + uint32_t IlMode : 2; /**< Interleave mode. */ + uint32_t bufferable : 1; /**< Allow AHB buffering. */ + uint32_t reserved2 : 24; /**< Reserved */ + + uint32_t reserved3; /**< Reserved */ + uint32_t IlSrc; /**< DMA rules table base address in memory. */ +} LDMA_DescriptorExtend_t; +#endif + +/** @brief LDMA initialization configuration structure. */ +typedef struct { + uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ + uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ + uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ + uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ +} LDMA_Init_t; + +/** + * @brief + * DMA transfer configuration structure. + * @details + * This structure configures all aspects of a DMA transfer. + */ +typedef struct { + uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ + uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ + uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ + uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ + uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ + bool ldmaReqDis; /**< Mask the PRS trigger input. */ + bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ + LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */ + LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ + LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ + uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */ + LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */ + LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */ +#endif +} LDMA_TransferCfg_t; + +/******************************************************************************* + ******************************** DEFINES ********************************** + ******************************************************************************/ + +/** @brief Size in words of a non-extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4 + +/** @brief Size in words of an extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7 + +/** @brief Maximum transfer size possible per descriptor. */ +#define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +/** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */ +#define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT) + +/** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */ +#define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT) + +/******************************************************************************* + ************************** STRUCT INITIALIZERS **************************** + ******************************************************************************/ + +/** @brief Default DMA initialization structure. */ +#define LDMA_INIT_DEFAULT \ + { \ + .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ + .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ + .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ + .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ + } + +/** + * @brief + * Generic DMA transfer configuration for memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. + * @param[in] src Peripheral data source register address. + * @param[in] dest Peripheral data destination register address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * Initializer for the destination interleaving portion of the DMA extended descriptor. + * @param[in] desc Transfer-type descriptor. + * @param[in] ilmode Rules table addressing mode for interleaved data. + * @param[in] ilsrc Base address for rules table in memory. + */ +#define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \ + { \ + (desc).dstIlEn = true; \ + (desc).IlMode = (ilmode); \ + (desc).IlSrc = (uint32_t)(ilsrc); \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void LDMA_DeInit(void); +void LDMA_EnableChannelRequest(int ch, bool enable); +void LDMA_Init(const LDMA_Init_t *init); +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor); +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext); +#endif +void LDMA_StopTransfer(int ch); +bool LDMA_TransferDone(int ch); +uint32_t LDMA_TransferRemainingCount(int ch); + +#if defined(_LDMA_SWRST_MASK) +/***************************************************************************//** + * @brief + * Reset the LDMA. + ******************************************************************************/ +__STATIC_INLINE void LDMA_Reset(void) +{ + LDMA->SWRST_SET = LDMA_SWRST_SWRST; + + /* Wait for reset to complete. */ + while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) { + } +} +#endif + +/***************************************************************************//** + * @brief + * Check if a certain channel is enabled. + * + * @param[in] ch + * LDMA channel to check. + * + * @return + * return true if the LDMA channel is enabled and false if the channel is not + * enabled. + ******************************************************************************/ +__STATIC_INLINE bool LDMA_ChannelEnabled(int ch) +{ + if ((ch < 0) || (ch > 31)) { + return false; + } +#if defined(_LDMA_CHSTATUS_MASK) + return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch))); +#else + // We've already confirmed ch is between 0 and 31, + // so it's now safe to cast it to uint8_t + return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch))); +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending LDMA interrupts. + * + * @param[in] flags + * Pending LDMA interrupt sources to clear. Use one or more valid + * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntClear(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = flags; +#else + LDMA->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LDMA interrupts. + * + * @param[in] flags + * LDMA interrupt sources to disable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntDisable(uint32_t flags) +{ + LDMA->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LDMA interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LDMA_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * LDMA interrupt sources to enable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntEnable(uint32_t flags) +{ + LDMA->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LDMA interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * LDMA interrupt sources pending. Returns one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and + * one flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGet(void) +{ + return LDMA->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LDMA interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled LDMA interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in LDMA_IEN and + * - the pending interrupt flags LDMA_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) +{ + uint32_t ien; + + ien = LDMA->IEN; + return LDMA->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LDMA interrupts + * + * @param[in] flags + * LDMA interrupt sources to set to pending. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and + * one done flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntSet(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_SET = flags; +#else + LDMA->IFS = flags; +#endif +} + +/** @} (end addtogroup ldma) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ +#endif /* EM_LDMA_H */ diff --git a/Libs/platform/emlib/inc/em_letimer.h b/Libs/platform/emlib/inc/em_letimer.h new file mode 100644 index 0000000..5bbb638 --- /dev/null +++ b/Libs/platform/emlib/inc/em_letimer.h @@ -0,0 +1,334 @@ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LETIMER_H +#define EM_LETIMER_H + +#include +#include "em_device.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup letimer + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Repeat mode. */ +typedef enum { + /** Count until stopped by SW. */ + letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, + /** Count REP0 times. */ + letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, + /** + * Count REP0 times, if REP1 has been written to, it is loaded into + * REP0 when REP0 is about to be decremented to 0. + */ + letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, + /** + * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 + * are decremented when counter underflows. + */ + letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE +} LETIMER_RepeatMode_TypeDef; + +/** Underflow action on output. */ +typedef enum { + /** No output action. */ + letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, + /** Toggle output when counter underflows. */ + letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, + /** Hold output one LETIMER clock cycle when counter underflows. */ + letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, + /** Set output idle when counter underflows, and active when matching COMP1. */ + letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM +} LETIMER_UFOA_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LETIMER initialization structure. */ +typedef struct { + bool enable; /**< Start counting when initialization completes. */ + bool debugRun; /**< Counter shall keep running during debug halt. */ +#if defined(LETIMER_CTRL_RTCC0TEN) + bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ + bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ +#endif + bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ + bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ + uint8_t out0Pol; /**< Idle value for output 0. */ + uint8_t out1Pol; /**< Idle value for output 1. */ + LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ + LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ + LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ + uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ +} LETIMER_Init_TypeDef; + +/** Default configuration for LETIMER initialization structure. */ +#if defined(LETIMER_CTRL_RTCC0TEN) +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not start counting on RTC COMP0 match. */ \ + false, /* Do not start counting on RTC COMP1 match. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#else +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value); +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer); +#if !defined(_EFM32_GECKO_FAMILY) +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value); +#endif + +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); +#if defined(_LETIMER_FREEZE_MASK) +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); +#endif +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * Pending LETIMER interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_CLR = flags; +#else + letimer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LETIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LETIMER_IntClear() prior to enabling the interrupt. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LETIMER interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * LETIMER interrupt sources pending. A bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) +{ + return letimer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LETIMER interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * Pending and enabled LETIMER interrupt sources. + * Return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn + * register (LETIMER_IEN_nnn) and + * - the OR combination of valid interrupt flags of the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) +{ + uint32_t ien; + + /* Store flags in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = letimer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return letimer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LETIMER interrupts from SW. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_SET = flags; +#else + letimer->IFS = flags; +#endif +} + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Lock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @note When LETIMER registers are locked LETIMER_EN, LETIMER_SWRST, + * LETIMER_CTRL, LETIMER_CMD, LETIMER_CNT, LETIMER_COMPx, + * LETIMER_TOP, LETIMER_TOPBUFF, LETIMER_REPx, and PRSMODE registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = ~LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Unlock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Unlock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value); +void LETIMER_Reset(LETIMER_TypeDef *letimer); +void LETIMER_SyncWait(LETIMER_TypeDef *letimer); +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer); + +/** @} (end addtogroup letimer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ +#endif /* EM_LETIMER_H */ diff --git a/Libs/platform/emlib/inc/em_msc.h b/Libs/platform/emlib/inc/em_msc.h new file mode 100644 index 0000000..9b097bd --- /dev/null +++ b/Libs/platform/emlib/inc/em_msc.h @@ -0,0 +1,889 @@ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_H +#define EM_MSC_H + +#include "em_device.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include +#include +#include "em_bus.h" +#include "em_msc_compat.h" +#include "em_ramfunc.h" +#include "sl_assert.h" + +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + #include "sli_tz_ns_interface.h" + #include "sli_tz_service_msc.h" + #include "sli_tz_s_interface.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup msc MSC - Memory System Controller + * @brief Memory System Controller API + * @details + * Contains functions to control the MSC, primarily the Flash. + * Users can perform Flash memory write and erase operations, as well as + * optimization of the CPU instruction fetch interface for the application. + * Available instruction fetch features depends on the MCU or SoC family, but + * features such as instruction pre-fetch, cache, and configurable branch prediction + * are typically available. + * + * @note Flash wait-state configuration is handled by @ref cmu. + * When core clock configuration is changed by a call to functions such as + * CMU_ClockSelectSet() or CMU_HFRCOBandSet(), then Flash wait-state + * configuration is also updated. + * + * MSC resets into a safe state. To initialize the instruction interface + * to recommended settings: + * @include em_msc_init_exec.c + * + * @note The optimal configuration is highly application dependent. Performance + * benchmarking is supported by most families. See MSC_StartCacheMeasurement() + * and MSC_GetCacheMeasurement() for more details. + * + * @note + * The flash write and erase runs from RAM on the EFM32G devices. On all other + * devices the flash write and erase functions run from flash. + * + * @note + * Flash erase may add ms of delay to interrupt latency if executing from Flash. + * + * Flash write and erase operations are supported by @ref MSC_WriteWord(), + * @ref MSC_ErasePage(), and MSC_MassErase(). + * Mass erase is supported for MCU and SoC families with larger Flash sizes. + * + * @note + * @ref MSC_Init() must be called prior to any Flash write or erase operation. + * + * The following steps are necessary to perform a page erase and write: + * @include em_msc_erase_write.c + * + * @deprecated + * The configuration called EM_MSC_RUN_FROM_FLASH is deprecated. This was + * previously used for allocating the flash write functions in either flash + * or RAM. + * + * @note + * The configuration EM_MSC_RUN_FROM_RAM is used to allocate the flash + * write functions in RAM. By default, flash write + * functions are placed in RAM on EFM32G and Series 2 devices + * unless SL_RAMFUNC_DISABLE is defined. For other devices, + * flash write functions are placed in FLASH by default unless + * EM_MSC_RUN_FROM_RAM is defined and SL_RAMFUNC_DISABLE is not defined. + * + * @deprecated + * The function called MSC_WriteWordFast() is deprecated. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************* DEFINES ***************************************** + ******************************************************************************/ + +/** + * @brief + * Timeout used while waiting for Flash to become ready after a write. + * This number indicates the number of iterations to perform before + * issuing a timeout. + * + * @note + * Timeout is set very large (in the order of 100x longer than + * necessary). This is to avoid any corner case. + */ +#define MSC_PROGRAM_TIMEOUT 10000000UL + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if (defined(_EFM32_GECKO_FAMILY) \ + || defined(_SILICON_LABS_32B_SERIES_2) \ + || defined(EM_MSC_RUN_FROM_RAM)) \ + && !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +#else +#define MSC_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END +#endif +/** @endcond */ + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Return codes for writing/erasing Flash. */ +typedef enum { + mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ + mscReturnLocked = -2, /**< Flash address is locked. */ + mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ + mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ +} MSC_Status_TypeDef; + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/** Strategy for prioritized bus access. */ +typedef enum { + mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ + mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ + mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ + mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ +} MSC_BusStrategy_Typedef; +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/** AHBHOST masters that can use alternate MPAHBRAM ports. */ +typedef enum { + mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, + mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, + mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, +#if defined(_SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_MASK) + mscDmemMasterIFADCDEBUG = _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK) + mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK) + mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) + mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK) + mscDmemMasterMVPAHBDATA1 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK) + mscDmemMasterMVPAHBDATA2 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_MASK) + mscDmemMasterLDMA1 = _SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_MASK) + mscDmemMasterSRWLDMA = _SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_MASK) + mscDmemMasterUSB = _SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_MASK) + mscDmemMasterBUFC = _SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_SHIFT +#endif +} MSC_DmemMaster_TypeDef; +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/** AHB port given priority. */ +typedef enum { + mscPortPriorityNone = _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE, + mscPortPriorityPort0 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0, + mscPortPriorityPort1 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1, +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2) + mscPortPriorityPort2 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2, +#endif +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3) + mscPortPriorityPort3 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3, +#endif +} MSC_PortPriority_TypeDef; +#endif + +#if defined(MSC_READCTRL_DOUTBUFEN) || defined(MSC_RDATACTRL_DOUTBUFEN) +/** Code execution configuration */ +typedef struct { + bool doutBufEn; /**< Flash dout pipeline buffer enable */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + } + +#else +/** Code execution configuration. */ +typedef struct { + bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ + bool prefetchEn; /**< Enable MSC prefetching. */ + bool ifcDis; /**< Disable instruction cache. */ + bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ + bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ + bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization. */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + true, \ + false, \ + false, \ + false, \ + false, \ + } +#endif + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/** EFM32GG11B incorporates 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/** EFM32GG12B incorporates 3 memory banks including ECC support. */ +#define MSC_ECC_BANKS (3) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + +/** xG26 chips incorporate 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +/** Series 2 chips incorporate 1 memory bank including ECC support. */ +#define MSC_ECC_BANKS (1) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false }, \ + { 0, 1 }, \ + } + +#else +#error Device not supported. +#endif + +/** ECC configuration. */ +typedef struct { + bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable + Error Correcting Code (ECC) for + each RAM bank that supports ECC on + the device. */ + uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to + use for ECC initialization. */ +} MSC_EccConfig_TypeDef; + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated type names. */ +#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef +#define msc_Return_TypeDef MSC_Status_TypeDef +/** @endcond */ + +/******************************************************************************* + ************************* Inline Functions ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the status of the MSC register lock. + * + * @return + * Boolean true if register lock is applied, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_LockGetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_LOCKED_SID); +#elif defined(_MSC_STATUS_REGLOCK_MASK) + return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; +#else + return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to a locked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_LOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to an unlocked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetUnlocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_UNLOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the current value of the read control register (MSC_READCTRL). + * + * @return + * The 32-bit value read from the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_READCTRL_SID); +#else + return MSC->READCTRL; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the read control register (MSC_READCTRL). + * + * @param[in] value + * The 32-bit value to write to the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_READCTRL_SID, + value); +#else + MSC->READCTRL = value; +#endif +} + +#if defined(_MSC_PAGELOCK0_MASK) || defined(_MSC_INST_PAGELOCKWORD0_MASK) + +/***************************************************************************//** + * @brief + * Set the lockbit for a flash page in order to prevent page writes/erases to + * the corresponding page. + * + * @param[in] page_number + * The index of the page to apply the pagelock to. Must be in the range + * [0, (flash_size / page_size) - 1]. + ******************************************************************************/ +__STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + pagelock_registers[page_number / 32] |= (1 << (page_number % 32)); +#endif +} + +/***************************************************************************//** + * @brief + * Get the value of the lockbit for a flash page. + * + * @param[in] page_number + * The index of the page to get the lockbit value from. Must be in the range + * [0, (flash_size / page_size) - 1]. + * + * @return + * Boolean true if the page is locked, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_GET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + return pagelock_registers[page_number / 32] & (1 << (page_number % 32)); +#endif +} + +#endif // _MSC_PAGELOCK0_MASK || _MSC_INST_PAGELOCKWORD0_MASK + +#if defined(_MSC_USERDATASIZE_MASK) + +/***************************************************************************//** + * @brief + * Get the size of the user data region in flash. + * + * @return + * The size of the user data region divided by 256. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_UserDataGetSize(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_USERDATA_SIZE_SID); +#else + return MSC->USERDATASIZE; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if defined(_MSC_MISCLOCKWORD_MASK) + +/***************************************************************************//** + * @brief + * Get the current value of the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @return + * The 32-bit value read from the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_MISCLOCKWORD_SID); +#else + return MSC->MISCLOCKWORD; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @param[in] value + * The 32-bit value to write to the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_MISCLOCKWORD_SID, + value); +#else + MSC->MISCLOCKWORD = value; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + +/***************************************************************************//** + * @brief + * Clear one or more pending MSC interrupts. + * + * @param[in] flags + * Pending MSC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntClear(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_CLR = flags; +#else + MSC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more MSC interrupts. + * + * @param[in] flags + * MSC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntDisable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_CLR = flags; +#else + MSC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more MSC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * MSC_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * MSC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntEnable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_SET = flags; +#else + MSC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending MSC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * MSC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGet(void) +{ + return MSC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending MSC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled MSC interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in MSC_IEN and + * - the pending interrupt flags MSC_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGetEnabled(void) +{ + uint32_t ien; + + ien = MSC->IEN; + return MSC->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending MSC interrupts from SW. + * + * @param[in] flags + * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntSet(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_SET = flags; +#else + MSC->IFS = flags; +#endif +} + +#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) +/***************************************************************************//** + * @brief + * Start measuring the cache hit ratio. + * @details + * Starts performance counters. It is defined inline to + * minimize the impact of this code on the measurement itself. + ******************************************************************************/ +__STATIC_INLINE void MSC_StartCacheMeasurement(void) +{ + /* Clear CMOF and CHOF to catch these later. */ + MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; + + /* Start performance counters. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STARTPC; +#else + MSC->CMD = MSC_CMD_STARTPC; +#endif +} + +/***************************************************************************//** + * @brief + * Stop measuring the hit rate. + * @note + * Defined inline to minimize the impact of this + * code on the measurement itself. + * Only works for relatively short sections of code. + * To measure longer sections of code, implement an IRQ Handler for + * the CHOF and CMOF overflow interrupts. These overflows need to be + * counted and included in the total. + * Functions can then be implemented as follows: + * @verbatim + * volatile uint32_t hitOverflows + * volatile uint32_t missOverflows + * + * void MSC_IRQHandler(void) + * { + * uint32_t flags; + * flags = MSC->IF; + * if (flags & MSC_IF_CHOF) { + * MSC->IFC = MSC_IF_CHOF; + * hitOverflows++; + * } + * if (flags & MSC_IF_CMOF) { + * MSC->IFC = MSC_IF_CMOF; + * missOverflows++; + * } + * } + * + * void startPerformanceCounters(void) + * { + * hitOverflows = 0; + * missOverflows = 0; + * + * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); + * NVIC_EnableIRQ(MSC_IRQn); + * + * MSC_StartCacheMeasurement(); + * } + * @endverbatim + * @return + * Returns -1 if there has been no cache accesses. + * Returns -2 if there has been an overflow in the performance counters. + * If not, it will return the percentage of hits versus misses. + ******************************************************************************/ +__STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) +{ + int32_t total; + int32_t hits; + /* Stop counter before computing hit-rate. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STOPPC; +#else + MSC->CMD = MSC_CMD_STOPPC; +#endif + + /* Check for overflows in performance counters. */ + if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { + return -2; + } + + hits = (int32_t)MSC->CACHEHITS; + total = (int32_t)MSC->CACHEMISSES + hits; + + /* To avoid a division by zero. */ + if (total == 0) { + return -1; + } + + return (hits * 100) / total; +} + +/***************************************************************************//** + * @brief + * Flush contents of instruction cache. + ******************************************************************************/ +__STATIC_INLINE void MSC_FlushCache(void) +{ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#else + MSC->CMD = MSC_CMD_INVCACHE; +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCache(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); +} + +#if defined(MSC_READCTRL_ICCDIS) +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality in IRQs. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); +} +#endif + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache flushing when writing to flash. + * @param[in] enable + * Enable automatic cache flushing. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); +} +#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/***************************************************************************//** + * @brief + * Configure which unit should get priority on system bus. + * @param[in] mode + * Unit to prioritize bus accesses for. + ******************************************************************************/ +__STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) +{ + MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; +} +#endif + +/******************************************************************************* + ************************* PROTOTYPES ************************************** + ******************************************************************************/ + +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port); +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority); +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void); +#endif + +#if !defined(_SILICON_LABS_32B_SERIES_2) +/* Note that this function is deprecated because we no longer support + * placing msc code in ram. */ +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes); +#endif + +#if defined(MSC_WRITECMD_ERASEMAIN0) +/***************************************************************************//** + * @brief + * Erase the entire Flash in one operation. + * + * @note + * This command will erase the entire contents of the device. + * Use with care, both a debug session and all contents of the flash will be + * lost. The lock bit, MLW will prevent this operation from executing and + * might prevent a successful mass erase. + * + * @return + * Returns the status of the operation. + ******************************************************************************/ +SL_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_MassErase(void); +#endif + +#endif /* !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT */ + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes); + +#if (_SILICON_LABS_32B_SERIES > 0) +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes); +#endif + +void MSC_Init(void); +void MSC_Deinit(void); + +/** @} (end addtogroup msc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ +#endif /* EM_MSC_H */ diff --git a/Libs/platform/emlib/inc/em_msc_compat.h b/Libs/platform/emlib/inc/em_msc_compat.h new file mode 100644 index 0000000..d5044ba --- /dev/null +++ b/Libs/platform/emlib/inc/em_msc_compat.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Compatibility Header + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_COMPAT_H +#define EM_MSC_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define MSC_IF_PWROFFIF MSC_IF_PWROFF +#define _MSC_IF_PWROFFIF_SHIFT _MSC_IF_PWROFF_SHIFT +#define _MSC_IF_PWROFFIF_MASK _MSC_IF_PWROFF_MASK +#define _MSC_IF_PWROFFIF_DEFAULT _MSC_IF_PWROFF_DEFAULT +#define MSC_IF_PWROFFIF_DEFAULT MSC_IF_PWROFF_DEFAULT + +#define MSC_IEN_PWROFFIEN MSC_IEN_PWROFF +#define _MSC_IEN_PWROFFIEN_SHIFT _MSC_IEN_PWROFF_SHIFT +#define _MSC_IEN_PWROFFIEN_MASK _MSC_IEN_PWROFF_MASK +#define _MSC_IEN_PWROFFIEN_DEFAULT _MSC_IEN_PWROFF_DEFAULT +#define MSC_IEN_PWROFFIEN_DEFAULT MSC_IEN_PWROFF_DEFAULT + + +#define ICACHE_IEN_RAMERRORIEN ICACHE_IEN_RAMERROR +#define _ICACHE_IEN_RAMERRORIEN_SHIFT _ICACHE_IEN_RAMERROR_SHIFT +#define _ICACHE_IEN_RAMERRORIEN_MASK _ICACHE_IEN_RAMERROR_MASK +#define _ICACHE_IEN_RAMERRORIEN_DEFAULT _ICACHE_IEN_RAMERROR_DEFAULT +#define ICACHE_IEN_RAMERRORIEN_DEFAULT ICACHE_IEN_RAMERROR_DEFAULT + + +#define SYSCFG_IF_FRCRAMERR1BIF SYSCFG_IF_FRCRAMERR1B +#define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT _SYSCFG_IF_FRCRAMERR1B_SHIFT +#define _SYSCFG_IF_FRCRAMERR1BIF_MASK _SYSCFG_IF_FRCRAMERR1B_MASK +#define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT _SYSCFG_IF_FRCRAMERR1B_DEFAULT +#define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT SYSCFG_IF_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IF_FRCRAMERR2BIF SYSCFG_IF_FRCRAMERR2B +#define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT _SYSCFG_IF_FRCRAMERR2B_SHIFT +#define _SYSCFG_IF_FRCRAMERR2BIF_MASK _SYSCFG_IF_FRCRAMERR2B_MASK +#define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT _SYSCFG_IF_FRCRAMERR2B_DEFAULT +#define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT SYSCFG_IF_FRCRAMERR2B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR1BIEN SYSCFG_IEN_FRCRAMERR1B +#define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR1B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK _SYSCFG_IEN_FRCRAMERR1B_MASK +#define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR1B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR2BIEN SYSCFG_IEN_FRCRAMERR2B +#define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR2B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK _SYSCFG_IEN_FRCRAMERR2B_MASK +#define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR2B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR2B_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ +#endif /* EM_MSC_COMPAT_H */ diff --git a/Libs/platform/emlib/inc/em_opamp.h b/Libs/platform/emlib/inc/em_opamp.h new file mode 100644 index 0000000..26f1e8b --- /dev/null +++ b/Libs/platform/emlib/inc/em_opamp.h @@ -0,0 +1,1459 @@ +/***************************************************************************//** + * @file + * @brief Operational Amplifier (OPAMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_OPAMP_H +#define EM_OPAMP_H + +#include "em_device.h" +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(_SILICON_LABS_32B_SERIES_0) +#include "em_dac.h" +#elif defined (_SILICON_LABS_32B_SERIES_1) +#include "em_vdac.h" +#endif + +/***************************************************************************//** + * @addtogroup opamp + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of DAC OPA number for assert statements. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define DAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(VDAC_STATUS_OPA3ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA3) +#elif defined(VDAC_STATUS_OPA2ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(VDAC_STATUS_OPA1ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA1) +#else +#define VDAC_OPA_VALID(opa) ((opa) = OPA0) +#endif +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** OPAMP selector values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS) + OPA0 = 0, /**< Select OPA0. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS) + OPA1 = 1, /**< Select OPA1. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS) + OPA2 = 2, /**< Select OPA2. */ +#endif +#if defined(VDAC_STATUS_OPA3ENS) + OPA3 = 3, /**< Select OPA3. */ +#endif +} OPAMP_TypeDef; + +/** OPAMP negative terminal input selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ + opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ + opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ + opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ + opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ + opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ + opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ + opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ + opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ + opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ + opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ + opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ + opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ + opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ + opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ + opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ + opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ + opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ + opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ + opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ + opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ + opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ + opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ + opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ + opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ + opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ + opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ + opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ + opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ + opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ + opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ + opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ + opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ + opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ + opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ + opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ + opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ + opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ + opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ + opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ + opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ + opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ + opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ + opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ + opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ + opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ + opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ + opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ + opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ + opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ + opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ + opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ + opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ + opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ + opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ + opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ + opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ + opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ + opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ + opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ + opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ + opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ + opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ + opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ + opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_NegSel_TypeDef; + +/** OPAMP positive terminal input selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ + opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ + opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ + opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ + opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ + opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ + opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ + opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ + opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ + opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ + opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ + opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ + opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ + opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ + opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ + opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ + opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ + opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ + opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ + opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ + opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ + opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ + opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ + opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ + opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ + opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ + opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ + opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ + opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ + opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ + opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ + opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ + opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ + opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ + opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ + opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ + opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ + opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ + opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ + opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ + opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ + opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ + opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ + opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ + opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ + opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ + opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ + opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ + opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ + opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ + opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ + opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ + opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ + opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ + opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ + opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ + opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ + opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ + opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ + opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ + opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ + opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ + opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ + opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ + opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ + opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ + opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_PosSel_TypeDef; + +/** OPAMP output terminal selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ + opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ + opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaOutModeDisable = 0, /**< OPA output disabled. */ + opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ + opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ + opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ + opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ + opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ + opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ + opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ + opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ + opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ + opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ + opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ + opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ + opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ + opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ + opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ + opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ + opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ + opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ + opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ + opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ + opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ + opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ + opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ + opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ + opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ + opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ + opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ + opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ + opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ + opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ + opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ + opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ + opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ + opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ + opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ + opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ + opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ + opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ + opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ + opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ + opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ + opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ + opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ + opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ + opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ + opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ + opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ + opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ + opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ + opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ + opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ + opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ + opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ + opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ + opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ + opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ + opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ + opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ + opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ + opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ + opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ + opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ + opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ + opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ + opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ + opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_OutMode_TypeDef; + +/** OPAMP gain values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */ + opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ + opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_ResSel_TypeDef; + +/** OPAMP resistor ladder input selector values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ + opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ + opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. + Direct input to support common reference. */ + opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully + differential instrumentation amplifier. */ + opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_ResInMux_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) +/** OPAMP PRS Mode. */ +typedef enum { + opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP + warmup sequence. The end of the warmup sequence + is controlled by timeout settings in OPAxTIMER. */ + opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the + OPAMP warmup sequence. The end of the warmup + sequence is controlled by the edge of the pulse. */ +} OPAMP_PrsMode_TypeDef; + +/** OPAMP PRS Selection. */ +typedef enum { + opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ + opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ + opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ + opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ + opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ + opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ + opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ + opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ +#if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8) + opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ + opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ + opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ + opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ +#endif +} OPAMP_PrsSel_TypeDef; + +/** OPAMP PRS Output. */ +typedef enum { + opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ + opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ + opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ +} OPAMP_PrsOut_TypeDef; + +/** OPAMP Output Scaling. */ +typedef enum { + opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ + opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ + opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ +} OPAMP_OutScale_Typedef; + +/** OPAMP Drive Strength. */ +typedef enum { + opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ + opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive strength. */ + opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive strength. */ + opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive strength. */ + opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive strength. */ +} OPAMP_DrvStr_Typedef; +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** OPAMP init structure. */ +typedef struct { + OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */ + OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */ + OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */ + OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */ + OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ + uint32_t outPen; /**< Alternate output enable bit mask. This value + should consist one or more of the + @if DOXYDOC_P1_DEVICE + DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags + (defined in \_dac.h) OR'ed together. + @n @n + For OPA0: + @li DAC_OPA0MUX_OUTPEN_OUT0 + @li DAC_OPA0MUX_OUTPEN_OUT1 + @li DAC_OPA0MUX_OUTPEN_OUT2 + @li DAC_OPA0MUX_OUTPEN_OUT3 + @li DAC_OPA0MUX_OUTPEN_OUT4 + + For OPA1: + @li DAC_OPA1MUX_OUTPEN_OUT0 + @li DAC_OPA1MUX_OUTPEN_OUT1 + @li DAC_OPA1MUX_OUTPEN_OUT2 + @li DAC_OPA1MUX_OUTPEN_OUT3 + @li DAC_OPA1MUX_OUTPEN_OUT4 + + For OPA2: + @li DAC_OPA2MUX_OUTPEN_OUT0 + @li DAC_OPA2MUX_OUTPEN_OUT1 + + E.g: @n + init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | + DAC_OPA0MUX_OUTPEN_OUT2 | + DAC_OPA0MUX_OUTPEN_OUT4; + + @elseif DOXYDOC_P2_DEVICE + VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + (defined in \_vdac.h) OR'ed together. + @n @n + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + + E.g: @n + init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + @endif */ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t bias; /**< Set OPAMP bias current. */ + bool halfBias; /**< Divide OPAMP bias current by 2. */ + bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ + bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */ + bool nextOut; /**< Enable NEXTOUT signal source. */ + bool npEn; /**< Enable positive pad. */ + bool ppEn; /**< Enable negative pad. */ + bool shortInputs; /**< Short OPAMP input terminals. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffset; /**< Use factory calibrated opamp offset value. */ + uint32_t offset; /**< Opamp offset value when @ref defaultOffset is + false. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ + bool gain3xEn; /**< Enable 3x gain resistor ladder. */ + bool halfDrvStr; /**< Half or full output drive strength. */ + bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ + bool prsEn; /**< Enable PRS as OPAMP trigger. */ + OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ + OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ + OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ + bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ + bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ + uint32_t settleTime; /**< Number of clock cycles to drive the output. */ + uint32_t startupDly; /**< OPAx startup delay in microseconds. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffsetN; /**< Use factory calibrated opamp inverting input + offset value. */ + uint32_t offsetN; /**< Opamp inverting input offset value when + @ref defaultOffsetN is false. */ + bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting + input offset value. */ + uint32_t offsetP; /**< Opamp non-inverting input offset value when + @ref defaultOffsetP is false. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ +} OPAMP_Init_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** Configuration of OPA0/1 in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN_OPA2 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0/1 in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0/1 in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in inverting amplifier mode. */ +#define OPA_INIT_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) +/** Configuration of OPA in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA3 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA2NEXT output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA3 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in three+one opamp differential receiver mode. In this + configuration, OPA3 is a second single-ended output amplifier. */ +#define OPA_INIT_DIFF_RECEIVER_OPA3 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA2 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA0 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA1 \ + { \ + opaNegSelNegPad, /* Negative input from pad. */ \ + opaPosSelResTap, /* Input from resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#elif defined(_SILICON_LABS_32B_SERIES_1) +void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/** @} (end addtogroup opamp) */ + +#ifdef __cplusplus +} +#endif + +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ +#endif /* EM_OPAMP_H */ diff --git a/Libs/platform/emlib/inc/em_pcnt.h b/Libs/platform/emlib/inc/em_pcnt.h new file mode 100644 index 0000000..3648587 --- /dev/null +++ b/Libs/platform/emlib/inc/em_pcnt.h @@ -0,0 +1,905 @@ +/***************************************************************************//** + * @file + * @brief Pulse Counter (PCNT) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_PCNT_H +#define EM_PCNT_H + +#include "em_device.h" +#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup pcnt + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +/** PCNT0 Counter register size. */ +#if defined(_EFM32_GECKO_FAMILY) +#define PCNT0_CNT_SIZE (8) /**< PCNT0 counter is 8 bits. */ +#else +#define PCNT0_CNT_SIZE (16) /**< PCNT0 counter is 16 bits. */ +#endif + +#ifdef PCNT1 +/** PCNT1 Counter register size. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define PCNT1_CNT_SIZE (8) /**< PCNT1 counter is 8 bits. */ +#else +#define PCNT1_CNT_SIZE (16) /**< PCNT1 counter is 16 bits. */ +#endif +#endif + +#ifdef PCNT2 +/** PCNT2 Counter register size. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define PCNT2_CNT_SIZE (8) /**< PCNT2 counter is 8 bits. */ +#else +#define PCNT2_CNT_SIZE (16) /**< PCNT2 counter is 16 bits. */ +#endif +#endif + +/* Define values that can be used in case some state/mode are not defined for some devices.*/ +/** PCNT mode disable. */ +#define PCNT_MODE_DISABLE 0xFF +/** PCNT count event is none. */ +#define PCNT_CNT_EVENT_NONE 0xFF + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Mode selection. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +typedef enum { + /** Disable pulse counter. */ + pcntModeDisable = _PCNT_CTRL_MODE_DISABLE, + + /** Single input LFACLK oversampling mode (available in EM0-EM2). */ + pcntModeOvsSingle = _PCNT_CTRL_MODE_OVSSINGLE, + + /** Externally clocked single input counter mode (available in EM0-EM3). */ + pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE, + + /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ + pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD, + +#if defined(_PCNT_CTRL_MODE_OVSQUAD1X) + /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ + pcntModeOvsQuad1 = _PCNT_CTRL_MODE_OVSQUAD1X, + + /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ + pcntModeOvsQuad2 = _PCNT_CTRL_MODE_OVSQUAD2X, + + /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ + pcntModeOvsQuad4 = _PCNT_CTRL_MODE_OVSQUAD4X, +#endif +} PCNT_Mode_TypeDef; + +#else +typedef enum { + /** Disable pulse counter. */ + pcntModeDisable = PCNT_MODE_DISABLE, + + /** Single input LFACLK oversampling mode (available in EM0-EM2). */ + pcntModeOvsSingle = _PCNT_CFG_MODE_OVSSINGLE, + + /** Externally clocked single input counter mode (available in EM0-EM3). */ + pcntModeExtSingle = _PCNT_CFG_MODE_EXTCLKSINGLE, + + /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ + pcntModeExtQuad = _PCNT_CFG_MODE_EXTCLKQUAD, + + /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ + pcntModeOvsQuad1 = _PCNT_CFG_MODE_OVSQUAD1X, + + /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ + pcntModeOvsQuad2 = _PCNT_CFG_MODE_OVSQUAD2X, + + /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ + pcntModeOvsQuad4 = _PCNT_CFG_MODE_OVSQUAD4X, +} PCNT_Mode_TypeDef; +#endif + +#if defined(_PCNT_CTRL_CNTEV_MASK) +/** Counter event selection. + * Note: unshifted values are being used for enumeration because multiple + * configuration structure members use this type definition. */ +typedef enum { + /** Counts up on up-count and down on down-count events. */ + pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH, + + /** Only counts up on up-count events. */ + pcntCntEventUp = _PCNT_CTRL_CNTEV_UP, + + /** Only counts down on down-count events. */ + pcntCntEventDown = _PCNT_CTRL_CNTEV_DOWN, + + /** Never counts. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE +#else + pcntCntEventNone = PCNT_CNT_EVENT_NONE +#endif +} PCNT_CntEvent_TypeDef; +#endif + +/** PRS sources for @p s0PRS and @p s1PRS. */ +#if defined(_PCNT_INPUT_MASK) +typedef enum { + pcntPRSCh0 = 0, /**< PRS channel 0. */ + pcntPRSCh1 = 1, /**< PRS channel 1. */ + pcntPRSCh2 = 2, /**< PRS channel 2. */ + pcntPRSCh3 = 3, /**< PRS channel 3. */ +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH4) + pcntPRSCh4 = 4, /**< PRS channel 4. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH5) + pcntPRSCh5 = 5, /**< PRS channel 5. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH6) + pcntPRSCh6 = 6, /**< PRS channel 6. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH7) + pcntPRSCh7 = 7, /**< PRS channel 7. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH8) + pcntPRSCh8 = 8, /**< PRS channel 8. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH9) + pcntPRSCh9 = 9, /**< PRS channel 9. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH10) + pcntPRSCh10 = 10, /**< PRS channel 10. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11) + pcntPRSCh11 = 11, /**< PRS channel 11. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH12) + pcntPRSCh12 = 12, /**< PRS channel 12. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH13) + pcntPRSCh13 = 13, /**< PRS channel 13. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH14) + pcntPRSCh14 = 14, /**< PRS channel 14. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH15) + pcntPRSCh15 = 15, /**< PRS channel 15. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH16) + pcntPRSCh16 = 16, /**< PRS channel 16. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH17) + pcntPRSCh17 = 17, /**< PRS channel 17. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH18) + pcntPRSCh18 = 18, /**< PRS channel 18. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH19) + pcntPRSCh19 = 19, /**< PRS channel 19. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH20) + pcntPRSCh20 = 20, /**< PRS channel 20. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH21) + pcntPRSCh21 = 21, /**< PRS channel 21. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH22) + pcntPRSCh22 = 22, /**< PRS channel 22. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH23) + pcntPRSCh23 = 23, /**< PRS channel 23. */ +#endif +} PCNT_PRSSel_TypeDef; +#elif defined(_SILICON_LABS_32B_SERIES_2) +typedef unsigned int PCNT_PRSSel_TypeDef; +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +/** PRS inputs of PCNT. */ +typedef enum { + pcntPRSInputS0 = 0, /** PRS input 0. */ + pcntPRSInputS1 = 1 /** PRS input 1. */ +} PCNT_PRSInput_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Initialization structure. */ +typedef struct { + /** Mode to operate in. */ + PCNT_Mode_TypeDef mode; + + /** Initial counter value (refer to reference manual for max value allowed). + * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. + * If using #pcntModeExtSingle or #pcntModeExtQuad modes, counter + * value is reset to HW reset value. */ + uint32_t counter; + + /** Initial top value (refer to reference manual for max value allowed). + * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. + * If using #pcntModeExtSingle or #pcntModeExtQuad modes, top + * value is reset to HW reset value. */ + uint32_t top; + + /** Polarity of incoming edge. + * @li #pcntModeExtSingle mode - if false, positive edges are counted, + * otherwise negative edges. + * @li #pcntModeExtQuad mode - if true, counting direction is inverted. */ + bool negEdge; + + /** Counting direction, only applicable for #pcntModeOvsSingle and + * #pcntModeExtSingle modes. */ + bool countDown; + + /** Enable filter, only available in #pcntModeOvsSingle* mode. */ + bool filter; + +#if defined(_SILICON_LABS_32B_SERIES_2) + /** Enable/disable PCNT counting during debug halt. Only in OVSSINGLE and OVSQUAD modes. */ + bool debugHalt; +#endif + +#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) + /** Set to true to enable hysteresis. When enabled, PCNT will always + * overflow and underflow to TOP/2. */ + bool hyst; +#endif + +#if defined(PCNT_CTRL_S1CDIR) + /** Set to true to enable S1 to determine the direction of counting in + * OVSSINGLE or EXTCLKSINGLE modes. @n + * When S1 is high, the count direction is given by CNTDIR, and when S1 is + * low, the count direction is the opposite. */ + bool s1CntDir; +#endif + +#if defined(_PCNT_CTRL_CNTEV_SHIFT) + /** Selects whether the regular counter responds to up-count events, + * down-count events, both, or none. */ + PCNT_CntEvent_TypeDef cntEvent; +#endif + +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) + /** Selects whether the auxiliary counter responds to up-count events, + * down-count events, both, or none. */ + PCNT_CntEvent_TypeDef auxCntEvent; +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) + /** Select PRS channel as input to S0IN in PCNTx_INPUT register. */ + PCNT_PRSSel_TypeDef s0PRS; + + /** Select PRS channel as input to S1IN in PCNTx_INPUT register. */ + PCNT_PRSSel_TypeDef s1PRS; +#endif +} PCNT_Init_TypeDef; + +/** Default Debug. */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_DEBUG_HALT true, +#else +#define DEFAULT_DEBUG_HALT +#endif + +/** Default Mode. */ +#define DEFAULT_MODE pcntModeDisable, /**< Disabled by default. */ + +/** Default Hysteresis. */ +#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_HYST false, /**< Hysteresis disabled. */ +#else +#define DEFAULT_HYST +#endif + +/** Default counter direction*/ +#if defined(PCNT_CTRL_S1CDIR) +#define DEFAULT_CDIR true, /**< Counter direction is given by CNTDIR. */ +#else +#define DEFAULT_CDIR +#endif + +/** Default count event*/ +#if defined(_PCNT_CTRL_CNTEV_SHIFT) +#define DEFAULT_CNTEV pcntCntEventUp, /**< Regular counter counts up on upcount events. */ +#else +#define DEFAULT_CNTEV +#endif + +/** Default auxiliary count event. */ +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) +#define DEFAULT_AUXCNTEV pcntCntEventNone, /**< Auxiliary counter doesn't respond to events. */ +#else +#define DEFAULT_AUXCNTEV +#endif + +/** Default selected PRS channel as S0IN and S1IN. */ +#if defined(_PCNT_INPUT_MASK) +#define DEFAULT_PRS_CH pcntPRSCh0, /**< PRS channel 0 selected as S0IN and as S1IN. */ +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_PRS_CH 0u, +#else +#define DEFAULT_PRS_CH +#endif + +/** Default configuration for PCNT initialization structure. */ +#define PCNT_INIT_DEFAULT \ + { \ + DEFAULT_MODE /* Default mode. */ \ + _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \ + _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \ + false, /* Use positive edge. */ \ + false, /* Up-counting. */ \ + false, /* Filter disabled. */ \ + DEFAULT_DEBUG_HALT /* Debug Halt enabled. */ \ + DEFAULT_HYST /* Default Hysteresis. */ \ + DEFAULT_CDIR /* Default CNTDIR. */ \ + DEFAULT_CNTEV /* Faults CNTEV. */ \ + DEFAULT_AUXCNTEV /* Default AUXCNTEV. */ \ + DEFAULT_PRS_CH /* PRS channel 0 selected as S0IN. */ \ + DEFAULT_PRS_CH /* PRS channel 0 selected as S1IN. */ \ + } + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +/** Filter initialization structure */ +typedef struct { + /** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable filter by + * setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */ + uint8_t filtLen; + + /** When set, removes flutter from Quaddecoder inputs S0IN and S1IN. + * Available only in OVSQUAD1X-4X modes. */ + bool flutterrm; +} PCNT_Filter_TypeDef; +#endif + +/** Default configuration for PCNT initialization structure. */ +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +#define PCNT_FILTER_DEFAULT \ + { \ + 0, /* Default length is 5 LFACLK cycles. */ \ + false /* No flutter removal. */ \ + } +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) + +/** Modes for Triggered Compare and Clear module. */ +typedef enum { + /** Triggered compare and clear not enabled. */ + tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED, + + /** Compare and clear performed on each (optionally prescaled) LFA clock cycle. */ + tccModeLFA = _PCNT_CTRL_TCCMODE_LFA, + + /** Compare and clear performed on PRS edges. Polarity defined by prsPolarity. */ + tccModePRS = _PCNT_CTRL_TCCMODE_PRS +} PCNT_TCCMode_TypeDef; + +/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */ +typedef enum { + /** Compare and clear event each LFA cycle. */ + tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1, + + /** Compare and clear event every other LFA cycle. */ + tccPrescDiv2 = _PCNT_CTRL_TCCPRESC_DIV2, + + /** Compare and clear event every 4th LFA cycle. */ + tccPrescDiv4 = _PCNT_CTRL_TCCPRESC_DIV4, + + /** Compare and clear event every 8th LFA cycle. */ + tccPrescDiv8 = _PCNT_CTRL_TCCPRESC_DIV8 +} PCNT_TCCPresc_Typedef; + +/** Compare modes for TCC module. */ +typedef enum { + /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */ + tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE, + + /** Compare match if PCNT_CNT is greater than or equal to PCNT_TOP. */ + tccCompGTOE = _PCNT_CTRL_TCCCOMP_GTOE, + + /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater + * than, or equal to PCNT_TOP[7:0]. */ + tccCompRange = _PCNT_CTRL_TCCCOMP_RANGE +} PCNT_TCCComp_Typedef; + +/** TCC initialization structure. */ +typedef struct { + /** Mode to operate in. */ + PCNT_TCCMode_TypeDef mode; + + /** Prescaler value for LFACLK in LFA mode. */ + PCNT_TCCPresc_Typedef prescaler; + + /** Choose the event that will trigger a clear. */ + PCNT_TCCComp_Typedef compare; + + /** PRS input to TCC module, either for gating the PCNT clock, triggering the TCC comparison, or both. */ + PCNT_PRSSel_TypeDef tccPRS; + + /** TCC PRS input polarity. @n + * False = Rising edge for comparison trigger, and PCNT clock gated when PRS signal is high. @n + * True = Falling edge for comparison trigger, and PCNT clock gated when PRS signal is low. */ + bool prsPolarity; + + /** Enable gating PCNT input clock through TCC PRS signal. + * Polarity selection is done through prsPolarity. */ + bool prsGateEnable; +} PCNT_TCC_TypeDef; + +/** TCC Default. */ +#define PCNT_TCC_DEFAULT \ + { \ + tccModeDisabled, /* Disabled by default. */ \ + tccPrescDiv1, /* Do not prescale LFA clock in LFA mode. */ \ + tccCompLTOE, /* Clear when CNT <= TOP. */ \ + pcntPRSCh0, /* Select PRS channel 0 as input to TCC. */ \ + false, /* PRS polarity is rising edge, and gate when 1. */ \ + false /* Do not gate PCNT counter input. */ \ + } + +#endif +/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the pulse counter value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_CounterGet(PCNT_TypeDef *pcnt) +{ + return pcnt->CNT; +} + +#if defined(_PCNT_AUXCNT_MASK) +/***************************************************************************//** + * @brief + * Get the auxiliary counter value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current auxiliary counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_AuxCounterGet(PCNT_TypeDef *pcnt) +{ + return pcnt->AUXCNT; +} +#endif + +void PCNT_CounterReset(PCNT_TypeDef *pcnt); +void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top); + +/***************************************************************************//** + * @brief + * Set a counter value. + * + * @details + * Pulse counter is disabled while changing counter value and re-enabled + * (if originally enabled) when counter value has been set. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when using + * an external clock to clock the PCNT module since stall time may be + * undefined in that case. The counter should normally only be set when + * operating in (or about to enable) #pcntModeOvsSingle mode. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] count + * Value to set in counter register. + ******************************************************************************/ +__STATIC_INLINE void PCNT_CounterSet(PCNT_TypeDef *pcnt, uint32_t count) +{ + PCNT_CounterTopSet(pcnt, count, pcnt->TOP); +} + +void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode); +bool PCNT_IsEnabled(PCNT_TypeDef *pcnt); +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable); +#endif +void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init); + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable); +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, + PCNT_PRSInput_TypeDef prsInput, + bool enable); +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) +void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config); +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending PCNT interrupts. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * Pending PCNT interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntClear(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcnt->IFC = flags; +#else + pcnt->IF_CLR = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more PCNT interrupts. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(PCNT_HAS_SET_CLEAR) + pcnt->IEN_CLR = flags; +#else + pcnt->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more PCNT interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * PCNT_IntClear() prior to enabling the interrupt. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntEnable(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(PCNT_HAS_SET_CLEAR) + pcnt->IEN_SET = flags; +#else + pcnt->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending PCNT interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * PCNT interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_IntGet(PCNT_TypeDef *pcnt) +{ + return pcnt->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending PCNT interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] pcnt + * Pointer to thePCNT peripheral register block. + * + * @return + * Pending and enabled PCNT interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in PCNT_IEN_nnn + * register (PCNT_IEN_nnn) and + * - the OR combination of valid interrupt flags of the PCNT module + * (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt) +{ + uint32_t ien; + + /* Store pcnt->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = pcnt->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return pcnt->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending PCNT interrupts from SW. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntSet(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcnt->IFS = flags; +#else + pcnt->IF_SET = flags; +#endif +} + +#if defined(_PCNT_LOCK_MASK) +/***************************************************************************//** + * @brief + * Lock PCNT registers. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @note When PCNT registers are locked PCNT_CFG, PCNT_EN, PCNT_SWRST, PCNT_CMD, + * PCNT_CTRL, PCNT_OVSCTRL, PCNT_CNT, PCNT_TOP, and PCNT_TOPB registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Lock(PCNT_TypeDef *pcnt) +{ + pcnt->LOCK = ~PCNT_LOCK_PCNTLOCKKEY_UNLOCK; +} +#endif + +#if defined(_PCNT_LOCK_MASK) +/***************************************************************************//** + * @brief + * Unlock PCNT registers. + * + * @param[in] pcnt + * Pointer to thePCNT peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Unlock(PCNT_TypeDef *pcnt) +{ + pcnt->LOCK = PCNT_LOCK_PCNTLOCKKEY_UNLOCK; +} +#endif + +void PCNT_Reset(PCNT_TypeDef *pcnt); + +/***************************************************************************//** + * @brief + * Get the pulse counter top buffer value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter top buffer value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_TopBufferGet(PCNT_TypeDef *pcnt) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOPB) { + } +#endif + return pcnt->TOPB; +} + +void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val); + +/***************************************************************************//** + * @brief + * Get the pulse counter top value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter top value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_TopGet(PCNT_TypeDef *pcnt) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOP) { + } +#endif + return pcnt->TOP; +} + +void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val); + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low-frequency domain to complete. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask) +{ + /* Avoid deadlock if modifying the same register twice when freeze mode is + * activated. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE) { + return; + } +#endif + + /* Wait for any pending previous write operation to have been completed in + * low-frequency domain. */ + while (pcnt->SYNCBUSY & mask) { + } +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start the main PCNT counter. + * + * @details + * This function will send a start command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the start command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StartMainCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STARTCNT; +} + +/***************************************************************************//** + * @brief + * Stop the main PCNT counter. + * + * @details + * This function will send a stop command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the stop command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StopMainCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STOPCNT; +} + +/***************************************************************************//** + * @brief + * Start the auxiliary PCNT counter. + * + * @details + * This function will send a start command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the start command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StartAuxCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STARTAUXCNT; +} + +/***************************************************************************//** + * @brief + * Stop the auxiliary PCNT counter. + * + * @details + * This function will send a stop command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the stop command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StopAuxCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STOPAUXCNT; +} +#endif + +/** @} (end addtogroup pcnt) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ +#endif /* EM_PCNT_H */ diff --git a/Libs/platform/emlib/inc/em_prs.h b/Libs/platform/emlib/inc/em_prs.h new file mode 100644 index 0000000..0b340ff --- /dev/null +++ b/Libs/platform/emlib/inc/em_prs.h @@ -0,0 +1,1170 @@ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_PRS_H +#define EM_PRS_H + +#include "em_device.h" +#include "em_gpio.h" + +#include +#include + +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup prs + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM +#elif defined(_EFM32_GECKO_FAMILY) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT 0 +#else +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT +#endif + +#if !defined(_EFM32_GECKO_FAMILY) +/** PRS asynchronous support */ +#define PRS_ASYNC_SUPPORTED 1 +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Some devices have renamed signals so some of these signals are mapped to + common names. */ +#if defined(PRS_USART0_RXDATAV) +#define PRS_USART0_RXDATA PRS_USART0_RXDATAV +#endif +#if defined(PRS_USART1_RXDATAV) +#define PRS_USART1_RXDATA PRS_USART1_RXDATAV +#endif +#if defined(PRS_USART2_RXDATAV) +#define PRS_USART2_RXDATA PRS_USART2_RXDATAV +#endif +#if defined(PRS_BURTC_OVERFLOW) +#define PRS_BURTC_OF PRS_BURTC_OVERFLOW +#endif +#if defined(PRS_BURTC_COMP0) +#define PRS_BURTC_COMP PRS_BURTC_COMP0 +#endif +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** PRS Channel type. */ +typedef enum { + prsTypeAsync, /**< Asynchronous channel type. */ + prsTypeSync /**< Synchronous channel type.*/ +} PRS_ChType_t; + +/** Edge detection type. */ +typedef enum { + prsEdgeOff, /**< Leave signal as is. */ + prsEdgePos, /**< Generate pulses on positive edge. */ + prsEdgeNeg, /**< Generate pulses on negative edge. */ + prsEdgeBoth /**< Generate pulses on both edges. */ +} PRS_Edge_TypeDef; + +#if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) +/** Logic functions that can be used when combining two PRS channels. */ +typedef enum { + prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, /**< Logical 0. */ + prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, /**< A NOR B. */ + prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, /**< (!A) NOR B. */ + prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, /**< !A. */ + prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, /**< A AND (!B). */ + prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, /**< !B. */ + prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, /**< A XOR B. */ + prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, /**< A NAND B. */ + prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, /**< A AND B. */ + prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, /**< A XNOR B. */ + prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, /**< B. */ + prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, /**< (!A) OR B. */ + prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, /**< A. */ + prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, /**< A OR (!B). */ + prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, /**< A OR B. */ + prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, /**< Logical 1. */ +} PRS_Logic_t; +#endif + +/** PRS Signal. */ +typedef enum { +#if defined(_PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + prsSignalNone = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x0 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x1 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#else + prsSignalNone = PRS_CH_CTRL_SOURCESEL_NONE | (0x0 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_CH_CTRL_SOURCESEL_NONE | (0x1 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#endif + +#if defined(PRS_PRS_CH11) + prsSignalPRS_CH0 = PRS_PRS_CH0, /**< PRS_CH0 signal */ + prsSignalPRS_CH1 = PRS_PRS_CH1, /**< PRS_CH1 signal */ + prsSignalPRS_CH2 = PRS_PRS_CH2, /**< PRS_CH2 signal */ + prsSignalPRS_CH3 = PRS_PRS_CH3, /**< PRS_CH3 signal */ + prsSignalPRS_CH4 = PRS_PRS_CH4, /**< PRS_CH4 signal */ + prsSignalPRS_CH5 = PRS_PRS_CH5, /**< PRS_CH5 signal */ + prsSignalPRS_CH6 = PRS_PRS_CH6, /**< PRS_CH6 signal */ + prsSignalPRS_CH7 = PRS_PRS_CH7, /**< PRS_CH7 signal */ + prsSignalPRS_CH8 = PRS_PRS_CH8, /**< PRS_CH8 signal */ + prsSignalPRS_CH9 = PRS_PRS_CH9, /**< PRS_CH9 signal */ + prsSignalPRS_CH10 = PRS_PRS_CH10, /**< PRS_CH10 signal */ + prsSignalPRS_CH11 = PRS_PRS_CH11, /**< PRS_CH11 signal */ +#endif +#if defined(PRS_PRS_CH23) + prsSignalPRS_CH12 = PRS_PRS_CH12, /**< PRS_CH12 signal */ + prsSignalPRS_CH13 = PRS_PRS_CH13, /**< PRS_CH13 signal */ + prsSignalPRS_CH14 = PRS_PRS_CH14, /**< PRS_CH14 signal */ + prsSignalPRS_CH15 = PRS_PRS_CH15, /**< PRS_CH15 signal */ + prsSignalPRS_CH16 = PRS_PRS_CH16, /**< PRS_CH16 signal */ + prsSignalPRS_CH17 = PRS_PRS_CH17, /**< PRS_CH17 signal */ + prsSignalPRS_CH18 = PRS_PRS_CH18, /**< PRS_CH18 signal */ + prsSignalPRS_CH19 = PRS_PRS_CH19, /**< PRS_CH19 signal */ + prsSignalPRS_CH20 = PRS_PRS_CH20, /**< PRS_CH20 signal */ + prsSignalPRS_CH21 = PRS_PRS_CH21, /**< PRS_CH21 signal */ + prsSignalPRS_CH22 = PRS_PRS_CH22, /**< PRS_CH22 signal */ + prsSignalPRS_CH23 = PRS_PRS_CH23, /**< PRS_CH23 signal */ +#endif + +#if defined(PRS_ADC0_SINGLE) + prsSignalADC0_SINGLE = PRS_ADC0_SINGLE, /**< ADC0_SINGLE signal */ + prsSignalADC0_SCAN = PRS_ADC0_SCAN, /**< ADC0_SCAN signal */ +#endif +#if defined(PRS_ADC1_SINGLE) + prsSignalADC1_SINGLE = PRS_ADC1_SINGLE, /**< ADC1_SINGLE signal */ + prsSignalADC1_SCAN = PRS_ADC1_SCAN, /**< ADC1_SCAN signal */ +#endif + + /* Timer Signals */ +#if defined(TIMER0) + prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ + prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ + prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ + prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ + prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER1) + prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ + prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ + prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ + prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ + prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER2) + prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ + prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ + prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ + prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ + prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER3) + prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ + prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ + prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ + prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ + prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ +#if defined(PRS_TIMER1_CC3) + prsSignalTIMER1_CC3 = PRS_TIMER1_CC3, /**< TIMER3 capture/compare channel 3 Signal. */ +#endif +#endif +#if defined(TIMER4) + prsSignalTIMER4_UF = PRS_TIMER4_UF, /**< TIMER4 underflow Signal. */ + prsSignalTIMER4_OF = PRS_TIMER4_OF, /**< TIMER4 overflow Signal. */ + prsSignalTIMER4_CC0 = PRS_TIMER4_CC0, /**< TIMER4 capture/compare channel 0 Signal. */ + prsSignalTIMER4_CC1 = PRS_TIMER4_CC1, /**< TIMER4 capture/compare channel 1 Signal. */ + prsSignalTIMER4_CC2 = PRS_TIMER4_CC2, /**< TIMER4 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER5) + prsSignalTIMER5_UF = PRS_TIMER5_UF, /**< TIMER5 underflow Signal. */ + prsSignalTIMER5_OF = PRS_TIMER5_OF, /**< TIMER5 overflow Signal. */ + prsSignalTIMER5_CC0 = PRS_TIMER5_CC0, /**< TIMER5 capture/compare channel 0 Signal. */ + prsSignalTIMER5_CC1 = PRS_TIMER5_CC1, /**< TIMER5 capture/compare channel 1 Signal. */ + prsSignalTIMER5_CC2 = PRS_TIMER5_CC2, /**< TIMER5 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER6) + prsSignalTIMER6_UF = PRS_TIMER6_UF, /**< TIMER6 underflow Signal. */ + prsSignalTIMER6_OF = PRS_TIMER6_OF, /**< TIMER6 overflow Signal. */ + prsSignalTIMER6_CC0 = PRS_TIMER6_CC0, /**< TIMER6 capture/compare channel 0 Signal. */ + prsSignalTIMER6_CC1 = PRS_TIMER6_CC1, /**< TIMER6 capture/compare channel 1 Signal. */ + prsSignalTIMER6_CC2 = PRS_TIMER6_CC2, /**< TIMER6 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER7) + prsSignalTIMER7_UF = PRS_TIMER7_UF, /**< TIMER7 underflow Signal. */ + prsSignalTIMER7_OF = PRS_TIMER7_OF, /**< TIMER7 overflow Signal. */ + prsSignalTIMER7_CC0 = PRS_TIMER7_CC0, /**< TIMER7 capture/compare channel 0 Signal. */ + prsSignalTIMER7_CC1 = PRS_TIMER7_CC1, /**< TIMER7 capture/compare channel 1 Signal. */ + prsSignalTIMER7_CC2 = PRS_TIMER7_CC2, /**< TIMER7 capture/compare channel 2 Signal. */ +#endif +#if defined(PRS_LETIMER0_CH0) + prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ + prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ +#endif +#if defined(PRS_LETIMER1_CH0) + prsSignalLETIMER1_CH0 = PRS_LETIMER1_CH0, /**< LETIMER1 channel 0 Signal. */ + prsSignalLETIMER1_CH1 = PRS_LETIMER1_CH1, /**< LETIMER1 channel 1 Signal. */ +#endif +#if defined(PRS_PCNT0_TCC) + prsSignalPCNT0_TCC = PRS_PCNT0_TCC, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT0_UFOF) + prsSignalPCNT0_UFOF = PRS_PCNT0_UFOF, /**< PCNT0_TCC Signal. */ + prsSignalPCNT0_DIR = PRS_PCNT0_DIR, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT1_TCC) + prsSignalPCNT1_TCC = PRS_PCNT1_TCC, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_UFOF = PRS_PCNT1_UFOF, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_DIR = PRS_PCNT1_DIR, /**< PCNT1_TCC Signal. */ +#endif +#if defined(PRS_PCNT2_TCC) + prsSignalPCNT2_TCC = PRS_PCNT2_TCC, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_UFOF = PRS_PCNT2_UFOF, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_DIR = PRS_PCNT2_DIR, /**< PCNT2_TCC Signal. */ +#endif +#if defined(PRS_CRYOTIMER_PERIOD) + prsSignalCRYOTIMER_PERIOD = PRS_CRYOTIMER_PERIOD, /**< CRYOTIMER_PERIOD Signal. */ +#endif +#if defined(PRS_CORE_CTIOUT0) + prsSignalCORE_CTIOUT0 = PRS_CORE_CTIOUT0, /**< CORE CTIOUT0 Signal. */ + prsSignalCORE_CTIOUT1 = PRS_CORE_CTIOUT1, /**< CORE CTIOUT1 Signal. */ + prsSignalCORE_CTIOUT2 = PRS_CORE_CTIOUT2, /**< CORE CTIOUT2 Signal. */ + prsSignalCORE_CTIOUT3 = PRS_CORE_CTIOUT3, /**< CORE CTIOUT3 Signal. */ +#endif +#if defined(PRS_CMUL_CLKOUT0) + prsSignalCMUL_CLKOUT0 = PRS_CMUL_CLKOUT0, /**< CMU CLKOUT0 Signal. */ + prsSignalCMUL_CLKOUT1 = PRS_CMUL_CLKOUT1, /**< CMU CLKOUT1 Signal. */ + prsSignalCMUL_CLKOUT2 = PRS_CMUL_CLKOUT2, /**< CMU CLKOUT2 Signal. */ +#endif +#if defined(PRS_PRSL_ASYNCH0) + prsSignalPRSL_ASYNCH0 = PRS_PRSL_ASYNCH0, /**< PRS channel 0 Signal. */ + prsSignalPRSL_ASYNCH1 = PRS_PRSL_ASYNCH1, /**< PRS channel 1 Signal. */ + prsSignalPRSL_ASYNCH2 = PRS_PRSL_ASYNCH2, /**< PRS channel 2 Signal. */ + prsSignalPRSL_ASYNCH3 = PRS_PRSL_ASYNCH3, /**< PRS channel 3 Signal. */ + prsSignalPRSL_ASYNCH4 = PRS_PRSL_ASYNCH4, /**< PRS channel 4 Signal. */ + prsSignalPRSL_ASYNCH5 = PRS_PRSL_ASYNCH5, /**< PRS channel 5 Signal. */ + prsSignalPRSL_ASYNCH6 = PRS_PRSL_ASYNCH6, /**< PRS channel 6 Signal. */ + prsSignalPRSL_ASYNCH7 = PRS_PRSL_ASYNCH7, /**< PRS channel 7 Signal. */ + prsSignalPRS_ASYNCH8 = PRS_PRS_ASYNCH8, /**< PRS channel 8 Signal. */ + prsSignalPRS_ASYNCH9 = PRS_PRS_ASYNCH9, /**< PRS channel 9 Signal. */ + prsSignalPRS_ASYNCH10 = PRS_PRS_ASYNCH10, /**< PRS channel 10 Signal. */ + prsSignalPRS_ASYNCH11 = PRS_PRS_ASYNCH11, /**< PRS channel 11 Signal. */ +#if defined(PRS_PRS_ASYNCH15) + prsSignalPRS_ASYNCH12 = PRS_PRS_ASYNCH12, /**< PRS channel 12 Signal. */ + prsSignalPRS_ASYNCH13 = PRS_PRS_ASYNCH13, /**< PRS channel 13 Signal. */ + prsSignalPRS_ASYNCH14 = PRS_PRS_ASYNCH14, /**< PRS channel 14 Signal. */ + prsSignalPRS_ASYNCH15 = PRS_PRS_ASYNCH15, /**< PRS channel 15 Signal. */ +#endif +#endif + + /* RTC/RTCC/SYSRTC/BURTC Signals */ +#if defined(PRS_RTC_OF) + prsSignalRTC_OF = PRS_RTC_OF, /**< RTC_OF signal. */ + prsSignalRTC_COMP0 = PRS_RTC_COMP0, /**< RTC_COMP0 signal. */ + prsSignalRTC_COMP1 = PRS_RTC_COMP1, /**< RTC_COMP1 signal. */ +#if defined(PRS_RTC_COMP5) + prsSignalRTC_COMP2 = PRS_RTC_COMP2, /**< RTC_COMP2 signal. */ + prsSignalRTC_COMP3 = PRS_RTC_COMP3, /**< RTC_COMP3 signal. */ + prsSignalRTC_COMP4 = PRS_RTC_COMP4, /**< RTC_COMP4 signal. */ + prsSignalRTC_COMP5 = PRS_RTC_COMP5, /**< RTC_COMP5 signal. */ +#endif +#endif +#if defined(RTCC) + prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ + prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ + prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ +#endif +#if defined(BURTC) + prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ + prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ +#endif +#if defined(SYSRTC0) + prsSignalSYSRTC0_GRP0OUT0 = PRS_SYSRTC0_GRP0OUT0, /**< SYSRTC GRP0OUT0 Signal. */ + prsSignalSYSRTC0_GRP0OUT1 = PRS_SYSRTC0_GRP0OUT1, /**< SYSRTC GRP0OUT1 Signal. */ + prsSignalSYSRTC0_GRP1OUT0 = PRS_SYSRTC0_GRP1OUT0, /**< SYSRTC GRP1OUT0 Signal. */ + prsSignalSYSRTC0_GRP1OUT1 = PRS_SYSRTC0_GRP1OUT1, /**< SYSRTC GRP1OUT1 Signal. */ +#endif +#if defined(PRS_HFXO0L_STATUS) + prsSignalHFXO0L_STATUS = PRS_HFXO0L_STATUS, /**< HFXO0L_STATUS Signal. */ + prsSignalHFXO0L_STATUS1 = PRS_HFXO0L_STATUS1, /**< HFXO0L_STATUS1 Signal. */ +#endif +#if defined(PRS_HFRCO0_COREEN) + prsSignalHFRCO0_COREEN = PRS_HFRCO0_COREEN, /**< HFRCO0_COREEN Signal. */ + prsSignalHFRCO0_STATE0 = PRS_HFRCO0_STATE0, /**< HFRCO0_STATE0 Signal. */ + prsSignalHFRCO0_STATE1 = PRS_HFRCO0_STATE1, /**< HFRCO0_STATE1 Signal. */ + prsSignalHFRCO0_STATE2 = PRS_HFRCO0_STATE2, /**< HFRCO0_STATE2 Signal. */ +#endif +#if defined(PRS_HFRCOEM23_COREEN) + prsSignalHFRCOEM23_COREEN = PRS_HFRCOEM23_COREEN, /**< HFRCOEM23_COREEN Signal. */ + prsSignalHFRCOEM23_STATE0 = PRS_HFRCOEM23_STATE0, /**< HFRCOEM23_STATE0 Signal. */ + prsSignalHFRCOEM23_STATE1 = PRS_HFRCOEM23_STATE1, /**< HFRCOEM23_STATE1 Signal. */ + prsSignalHFRCOEM23_STATE2 = PRS_HFRCOEM23_STATE2, /**< HFRCOEM23_STATE2 Signal. */ +#endif + + /* ACMP Signals */ +#if defined(ACMP0) + prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ +#endif +#if defined(ACMP1) + prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ +#endif +#if defined(ACMP2) + prsSignalACMP2_OUT = PRS_ACMP2_OUT, /**< ACMP2 output Signal. */ +#endif +#if defined(ACMP3) + prsSignalACMP3_OUT = PRS_ACMP3_OUT, /**< ACMP3 output Signal. */ +#endif + + /* VDAC Signals */ +#if defined(VDAC0) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC0_CH0WARM = PRS_VDAC0L_CH0WARM, /**< VDAC0 channel 0 warmed Signal. */ + prsSignalVDAC0_CH1WARM = PRS_VDAC0L_CH1WARM, /**< VDAC0 channel 1 warmed Signal. */ + prsSignalVDAC0_CH0DONE = PRS_VDAC0L_CH0DONEASYNC, /**< VDAC0 channel 0 conversion done Signal. */ + prsSignalVDAC0_CH1DONE = PRS_VDAC0L_CH1DONEASYNC, /**< VDAC0 channel 1 conversion done Signal. */ + prsSignalVDAC0_INTERNALTIMEROF = PRS_VDAC0L_INTERNALTIMEROF, /**< VDAC0 internal timer overflow Signal. */ + prsSignalVDAC0_REFRESHTIMEROF = PRS_VDAC0L_REFRESHTIMEROF, /**< VDAC0 internal timer overflow Signal. */ +#endif +#if defined(PRS_VDAC0_OPA3) + prsSignalVDAC0_CH0 = PRS_VDAC0_CH0, /**< VDAC0_CH0 Signal. */ + prsSignalVDAC0_CH1 = PRS_VDAC0_CH1, /**< VDAC0_CH1 Signal. */ + prsSignalVDAC0_OPA0 = PRS_VDAC0_OPA0, /**< VDAC0_OPA0 Signal. */ + prsSignalVDAC0_OPA1 = PRS_VDAC0_OPA1, /**< VDAC0_OPA1 Signal. */ + prsSignalVDAC0_OPA2 = PRS_VDAC0_OPA2, /**< VDAC0_OPA2 Signal. */ + prsSignalVDAC0_OPA3 = PRS_VDAC0_OPA3, /**< VDAC0_OPA3 Signal. */ +#endif +#if defined(VDAC1) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC1_CH0WARM = PRS_VDAC1L_CH0WARM, /**< VDAC1 channel 0 warmed Signal. */ + prsSignalVDAC1_CH1WARM = PRS_VDAC1L_CH1WARM, /**< VDAC1 channel 1 warmed Signal. */ + prsSignalVDAC1_CH0DONE = PRS_VDAC1L_CH0DONEASYNC, /**< VDAC1 channel 0 conversion done Signal. */ + prsSignalVDAC1_CH1DONE = PRS_VDAC1L_CH1DONEASYNC, /**< VDAC1 channel 1 conversion done Signal. */ + prsSignalVDAC1_INTERNALTIMEROF = PRS_VDAC1L_INTERNALTIMEROF, /**< VDAC1 internal timer overflow Signal. */ + prsSignalVDAC1_REFRESHTIMEROF = PRS_VDAC1L_REFRESHTIMEROF, /**< VDAC1 internal timer overflow Signal. */ +#endif + +#if defined(PRS_LESENSE_SCANRES15) + prsSignalLESENSE_SCANRES0 = PRS_LESENSE_SCANRES0, /**< LESENSE_SCANRES0 Signal. */ + prsSignalLESENSE_SCANRES1 = PRS_LESENSE_SCANRES1, /**< LESENSE_SCANRES1 Signal. */ + prsSignalLESENSE_SCANRES2 = PRS_LESENSE_SCANRES2, /**< LESENSE_SCANRES2 Signal. */ + prsSignalLESENSE_SCANRES3 = PRS_LESENSE_SCANRES3, /**< LESENSE_SCANRES3 Signal. */ + prsSignalLESENSE_SCANRES4 = PRS_LESENSE_SCANRES4, /**< LESENSE_SCANRES4 Signal. */ + prsSignalLESENSE_SCANRES5 = PRS_LESENSE_SCANRES5, /**< LESENSE_SCANRES5 Signal. */ + prsSignalLESENSE_SCANRES6 = PRS_LESENSE_SCANRES6, /**< LESENSE_SCANRES6 Signal. */ + prsSignalLESENSE_SCANRES7 = PRS_LESENSE_SCANRES7, /**< LESENSE_SCANRES7 Signal. */ + prsSignalLESENSE_SCANRES8 = PRS_LESENSE_SCANRES8, /**< LESENSE_SCANRES8 Signal. */ + prsSignalLESENSE_SCANRES9 = PRS_LESENSE_SCANRES9, /**< LESENSE_SCANRES9 Signal. */ + prsSignalLESENSE_SCANRES10 = PRS_LESENSE_SCANRES10, /**< LESENSE_SCANRES10 Signal. */ + prsSignalLESENSE_SCANRES11 = PRS_LESENSE_SCANRES11, /**< LESENSE_SCANRES11 Signal. */ + prsSignalLESENSE_SCANRES12 = PRS_LESENSE_SCANRES12, /**< LESENSE_SCANRES12 Signal. */ + prsSignalLESENSE_SCANRES13 = PRS_LESENSE_SCANRES13, /**< LESENSE_SCANRES13 Signal. */ + prsSignalLESENSE_SCANRES14 = PRS_LESENSE_SCANRES14, /**< LESENSE_SCANRES14 Signal. */ + prsSignalLESENSE_SCANRES15 = PRS_LESENSE_SCANRES15, /**< LESENSE_SCANRES15 Signal. */ +#endif +#if defined(PRS_LESENSE_DEC2) + prsSignalLESENSE_DEC0 = PRS_LESENSE_DEC0, /**< LESENSE_DEC0 Signal. */ + prsSignalLESENSE_DEC1 = PRS_LESENSE_DEC1, /**< LESENSE_DEC1 Signal. */ + prsSignalLESENSE_DEC2 = PRS_LESENSE_DEC2, /**< LESENSE_DEC2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECOUT2) + prsSignalLESENSE_DECOUT0 = PRS_LESENSE_DECOUT0, /**< LESENSE_DECOUT0 Signal. */ + prsSignalLESENSE_DECOUT1 = PRS_LESENSE_DECOUT1, /**< LESENSE_DECOUT1 Signal. */ + prsSignalLESENSE_DECOUT2 = PRS_LESENSE_DECOUT2, /**< LESENSE_DECOUT2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECCMP) + prsSignalLESENSE_DECCMP = PRS_LESENSE_DECCMP, /**< LESENSE_DECCMP Signal. */ +#endif +#if defined(PRS_LESENSE_MEASACT) + prsSignalLESENSE_MEASACT = PRS_LESENSE_MEASACT, /**< LESENSE_MEASACT Signal. */ +#endif + + /* USART Signals */ +#if defined(USART0) + prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 TX complete Signal. */ +#if defined(PRS_USART0_RXDATA) + prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_RXDATAV) + prsSignalUSART0_RXDATAV = PRS_USART0_RXDATAV, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_IRTX) + prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR TX Signal. */ +#endif +#if defined(PRS_USART0_RTS) + prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ + prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 TX Signal. */ + prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ +#endif +#endif +#if defined(USART1) + prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 TX complete Signal. */ +#if defined(PRS_USART1_RXDATA) + prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_RXDATAV) + prsSignalUSART1_RXDATAV = PRS_USART1_RXDATAV, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_IRTX) + prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR TX Signal. */ +#endif +#if defined(PRS_USART1_RTS) + prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ + prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 TX Signal. */ + prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ +#endif +#endif +#if defined(USART2) + prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 TX complete Signal. */ +#if defined(PRS_USART2_RXDATA) + prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_RXDATAV) + prsSignalUSART2_RXDATAV = PRS_USART2_RXDATAV, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_IRTX) + prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR TX Signal. */ +#endif +#if defined(PRS_USART2_RTS) + prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ + prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 TX Signal. */ + prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ +#endif +#endif +#if defined(PRS_USART3_TXC) + prsSignalUSART3_TXC = PRS_USART3_TXC, /**< USART3 TX complete Signal. */ + prsSignalUSART3_RXDATAV = PRS_USART3_RXDATAV, /**< USART3 RX data available Signal. */ + prsSignalUSART3_RTS = PRS_USART3_RTS, /**< USART3 RTS Signal. */ + prsSignalUSART3_TX = PRS_USART3_TX, /**< USART3 TX Signal. */ + prsSignalUSART3_CS = PRS_USART3_CS, /**< USART3 chip select Signal. */ +#endif +#if defined(PRS_USART4_TXC) + prsSignalUSART4_TXC = PRS_USART4_TXC, /**< USART4 TX complete Signal. */ + prsSignalUSART4_RXDATAV = PRS_USART4_RXDATAV, /**< USART4 RX data available Signal. */ + prsSignalUSART4_RTS = PRS_USART4_RTS, /**< USART4 RTS Signal. */ + prsSignalUSART4_TX = PRS_USART4_TX, /**< USART4 TX Signal. */ + prsSignalUSART4_CS = PRS_USART4_CS, /**< USART4 chip select Signal. */ +#endif +#if defined(PRS_USART5_TXC) + prsSignalUSART5_TXC = PRS_USART5_TXC, /**< USART5 TX complete Signal. */ + prsSignalUSART5_RXDATAV = PRS_USART5_RXDATAV, /**< USART5 RX data available Signal. */ + prsSignalUSART5_RTS = PRS_USART5_RTS, /**< USART5 RTS Signal. */ + prsSignalUSART5_TX = PRS_USART5_TX, /**< USART5 TX Signal. */ + prsSignalUSART5_CS = PRS_USART5_CS, /**< USART5 chip select Signal. */ +#endif + +#if defined(UART0) + prsSignalUART0_TXC = PRS_UART0_TXC, /**< UART0 TX complete Signal. */ + prsSignalUART0_RXDATAV = PRS_UART0_RXDATAV, /**< UART0 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART0_IRTX = PRS_UART0_IRTX, /**< UART0 IR TX Signal. */ +#endif +#if defined(PRS_UART0_RTS) + prsSignalUART0_RTS = PRS_UART0_RTS, /**< UART0 RTS Signal. */ + prsSignalUART0_TX = PRS_UART0_TX, /**< UART0 TX Signal. */ + prsSignalUART0_CS = PRS_UART0_CS, /**< UART0 chip select Signal. */ +#endif +#endif + +#if defined(UART1) + prsSignalUART1_TXC = PRS_UART1_TXC, /**< UART1 TX complete Signal. */ + prsSignalUART1_RXDATAV = PRS_UART1_RXDATAV, /**< UART1 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART1_IRTX = PRS_UART1_IRTX, /**< UART1 IR RX Signal. */ +#endif +#if defined(PRS_UART1_RTS) + prsSignalUART1_RTS = PRS_UART1_RTS, /**< UART1 RTS Signal. */ + prsSignalUART1_TX = PRS_UART1_TX, /**< UART1 RX Signal. */ + prsSignalUART1_CS = PRS_UART1_CS, /**< UART1 chip select Signal. */ +#endif +#endif + +#if defined(PRS_USB_SOF) + prsSignalUSB_SOF = PRS_USB_SOF, /**< USB_SOF Signal. */ + prsSignalUSB_SOFSR = PRS_USB_SOFSR, /**< USB_SOFSR Signal. */ +#endif + +#if defined(PRS_CM4_TXEV) + prsSignalCM4_TXEV = PRS_CM4_TXEV, /**< TXEV Signal. */ +#endif +#if defined(PRS_CM4_ICACHEPCHITSOF) + prsSignalCM4_ICACHEPCHITSOF = PRS_CM4_ICACHEPCHITSOF, /**< ICACHEPCHITSOF Signal. */ + prsSignalCM4_ICACHEPCMISSESOF = PRS_CM4_ICACHEPCMISSESOF, /**< ICACHEPCMISSESOF Signal. */ +#endif + +#if defined(PRS_WTIMER0_UF) + prsSignalWTIMER0_UF = PRS_WTIMER0_UF, /**< WTIMER0_UF Signal. */ + prsSignalWTIMER0_OF = PRS_WTIMER0_OF, /**< WTIMER0_OF Signal. */ + prsSignalWTIMER0_CC0 = PRS_WTIMER0_CC0, /**< WTIMER0_CC0 Signal. */ + prsSignalWTIMER0_CC1 = PRS_WTIMER0_CC1, /**< WTIMER0_CC1 Signal. */ + prsSignalWTIMER0_CC2 = PRS_WTIMER0_CC2, /**< WTIMER0_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER1_UF) + prsSignalWTIMER1_UF = PRS_WTIMER1_UF, /**< WTIMER1_UF Signal. */ + prsSignalWTIMER1_OF = PRS_WTIMER1_OF, /**< WTIMER1_OF Signal. */ + prsSignalWTIMER1_CC0 = PRS_WTIMER1_CC0, /**< WTIMER1_CC0 Signal. */ + prsSignalWTIMER1_CC1 = PRS_WTIMER1_CC1, /**< WTIMER1_CC1 Signal. */ + prsSignalWTIMER1_CC2 = PRS_WTIMER1_CC2, /**< WTIMER1_CC2 Signal. */ + prsSignalWTIMER1_CC3 = PRS_WTIMER1_CC3, /**< WTIMER1_CC3 Signal. */ +#endif +#if defined(PRS_WTIMER2_UF) + prsSignalWTIMER2_UF = PRS_WTIMER2_UF, /**< WTIMER2_UF Signal. */ + prsSignalWTIMER2_OF = PRS_WTIMER2_OF, /**< WTIMER2_OF Signal. */ + prsSignalWTIMER2_CC0 = PRS_WTIMER2_CC0, /**< WTIMER2_CC0 Signal. */ + prsSignalWTIMER2_CC1 = PRS_WTIMER2_CC1, /**< WTIMER2_CC1 Signal. */ + prsSignalWTIMER2_CC2 = PRS_WTIMER2_CC2, /**< WTIMER2_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER3_UF) + prsSignalWTIMER3_UF = PRS_WTIMER3_UF, /**< WTIMER3_UF Signal. */ + prsSignalWTIMER3_OF = PRS_WTIMER3_OF, /**< WTIMER3_OF Signal. */ + prsSignalWTIMER3_CC0 = PRS_WTIMER3_CC0, /**< WTIMER3_CC0 Signal. */ + prsSignalWTIMER3_CC1 = PRS_WTIMER3_CC1, /**< WTIMER3_CC1 Signal. */ + prsSignalWTIMER3_CC2 = PRS_WTIMER3_CC2, /**< WTIMER3_CC2 Signal. */ +#endif + +/* EUSART Signals */ +#if defined(EUSART0) + prsSignalEUSART0_CS = PRS_EUSART0L_CS, /**< EUSART0 chip select Signal. */ + prsSignalEUSART0_IRTX = PRS_EUSART0L_IRDATX, /**< EUSART0 IR RX Signal. */ + prsSignalEUSART0_RTS = PRS_EUSART0L_RTS, /**< EUSART0 RTS Signal. */ + prsSignalEUSART0_RXDATA = PRS_EUSART0L_RXDATAV, /**< EUSART0 RX data available Signal. */ + prsSignalEUSART0_TX = PRS_EUSART0L_TX, /**< EUSART0 TX Signal. */ + prsSignalEUSART0_TXC = PRS_EUSART0L_TXC, /**< EUSART0 TX complete Signal. */ + prsSignalEUSART0_RXFL = PRS_EUSART0L_RXFL, /**< EUSART0 rxfl Signal. */ + prsSignalEUSART0_TXFL = PRS_EUSART0L_TXFL, /**< EUSART0 txfl Signal. */ +#endif +#if defined(EUSART1) + prsSignalEUSART1_CS = PRS_EUSART1L_CS, /**< EUSART1 chip select Signal. */ + prsSignalEUSART1_IRTX = PRS_EUSART1L_IRDATX, /**< EUSART1 IR TX Signal. */ + prsSignalEUSART1_RTS = PRS_EUSART1L_RTS, /**< EUSART1 RTS Signal. */ + prsSignalEUSART1_RXDATA = PRS_EUSART1L_RXDATAV, /**< EUSART1 RX data available Signal. */ + prsSignalEUSART1_TX = PRS_EUSART1L_TX, /**< EUSART1 TX Signal. */ + prsSignalEUSART1_TXC = PRS_EUSART1L_TXC, /**< EUSART1 TX complete Signal. */ + prsSignalEUSART1_RXFL = PRS_EUSART1L_RXFL, /**< EUSART1 rxfl Signal. */ + prsSignalEUSART1_TXFL = PRS_EUSART1L_TXFL, /**< EUSART1 txfl Signal. */ +#endif +#if defined(EUSART2) +#if defined(PRS_EUSART2L_CS) + prsSignalEUSART2_CS = PRS_EUSART2L_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2L_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2L_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2L_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2L_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2L_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2L_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2L_TXFL, /**< EUSART2 txfl Signal. */ +#else + prsSignalEUSART2_CS = PRS_EUSART2_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2_TXFL, /**< EUSART2 txfl Signal. */ +#endif +#endif +#if defined(EUSART3) +#if defined(PRS_EUSART3L_CS) + prsSignalEUSART3_CS = PRS_EUSART3L_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3L_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3L_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3L_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3L_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3L_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3L_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3L_TXFL, /**< EUSART3 txfl Signal. */ +#else + prsSignalEUSART3_CS = PRS_EUSART3_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3_TXFL, /**< EUSART3 txfl Signal. */ +#endif +#endif +#if defined(EUSART4) + prsSignalEUSART4_CS = PRS_EUSART4L_CS, /**< EUSART4 chip select Signal. */ + prsSignalEUSART4_IRTX = PRS_EUSART4L_IRDATX, /**< EUSART4 IR TX Signal. */ + prsSignalEUSART4_RTS = PRS_EUSART4L_RTS, /**< EUSART4 RTS Signal. */ + prsSignalEUSART4_RXDATA = PRS_EUSART4L_RXDATAV, /**< EUSART4 RX data available Signal. */ + prsSignalEUSART4_TX = PRS_EUSART4L_TX, /**< EUSART4 TX Signal. */ + prsSignalEUSART4_TXC = PRS_EUSART4L_TXC, /**< EUSART4 TX complete Signal. */ + prsSignalEUSART4_RXFL = PRS_EUSART4L_RXFL, /**< EUSART4 rxfl Signal. */ + prsSignalEUSART4_TXFL = PRS_EUSART4L_TXFL, /**< EUSART4 txfl Signal. */ +#endif + /* ADC Signals */ +#if defined(IADC0) + prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ + prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ + prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ +#endif + + /* GPIO pin Signals */ + prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ + prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ + prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ + prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ + prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ + prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ + prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ + prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ +#if defined(PRS_GPIO_PIN15) + prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ + prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ + prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ + prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ + prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ + prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ + prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ + prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ +#endif +#if defined(PRS_AGCL_CCA) + prsSignalAGCL_CCA = PRS_AGCL_CCA, /**< AGCL_CCA Signal. */ + prsSignalAGCL_CCAREQ = PRS_AGCL_CCAREQ, /**< AGCL_CCAREQ Signal. */ + prsSignalAGCL_GAINADJUST = PRS_AGCL_GAINADJUST, /**< AGCL_GAINADJUST Signal. */ + prsSignalAGCL_GAINOK = PRS_AGCL_GAINOK, /**< AGCL_GAINOK Signal. */ + prsSignalAGCL_GAINREDUCED = PRS_AGCL_GAINREDUCED, /**< AGCL_GAINREDUCED Signal. */ + prsSignalAGCL_IFPKI1 = PRS_AGCL_IFPKI1, /**< AGCL_IFPKI1 Signal. */ + prsSignalAGCL_IFPKQ2 = PRS_AGCL_IFPKQ2, /**< AGCL_IFPKQ2 Signal. */ + prsSignalAGCL_IFPKRST = PRS_AGCL_IFPKRST, /**< AGCL_IFPKRST Signal. */ +#endif +#if defined(PRS_AGC_PEAKDET) + prsSignalAGC_PEAKDET = PRS_AGC_PEAKDET, /**< AGC_PEAKDET Signal. */ + prsSignalAGC_PROPAGATED = PRS_AGC_PROPAGATED, /**< AGC_PROPAGATED Signal. */ + prsSignalAGC_RSSIDONE = PRS_AGC_RSSIDONE, /**< AGC_RSSIDONE Signal. */ +#endif +#if defined(PRS_BUFC_THR0) + prsSignalBUFC_THR0 = PRS_BUFC_THR0, /**< BUFC_THR0 Signal. */ + prsSignalBUFC_THR1 = PRS_BUFC_THR1, /**< BUFC_THR1 Signal. */ + prsSignalBUFC_THR2 = PRS_BUFC_THR2, /**< BUFC_THR2 Signal. */ + prsSignalBUFC_THR3 = PRS_BUFC_THR3, /**< BUFC_THR3 Signal. */ +#endif +#if defined(PRS_BUFC_CNT0) + prsSignalBUFC_CNT0 = PRS_BUFC_CNT0, /**< BUFC_CNT0 Signal. */ + prsSignalBUFC_CNT1 = PRS_BUFC_CNT1, /**< BUFC_CNT1 Signal. */ + prsSignalBUFC_FULL = PRS_BUFC_FULL, /**< BUFC_FULL Signal. */ +#endif +#if defined(PRS_MODEML_ADVANCE) + prsSignalMODEML_ADVANCE = PRS_MODEML_ADVANCE, /**< MODEML_ADVANCE Signal. */ + prsSignalMODEML_ANT0 = PRS_MODEML_ANT0, /**< MODEML_ANT0 Signal. */ + prsSignalMODEML_ANT1 = PRS_MODEML_ANT1, /**< MODEML_ANT1 Signal. */ + prsSignalMODEML_COHDSADET = PRS_MODEML_COHDSADET, /**< MODEML_COHDSADET Signal. */ + prsSignalMODEML_COHDSALIVE = PRS_MODEML_COHDSALIVE, /**< MODEML_COHDSALIVE Signal. */ + prsSignalMODEML_DCLK = PRS_MODEML_DCLK, /**< MODEML_DCLK Signal. */ + prsSignalMODEML_DOUT = PRS_MODEML_DOUT, /**< MODEML_DOUT Signal. */ + prsSignalMODEML_FRAMEDET = PRS_MODEML_FRAMEDET, /**< MODEML_FRAMEDET Signal. */ +#endif +#if defined(PRS_MODEM_FRAMEDET) + prsSignalMODEM_FRAMEDET = PRS_MODEM_FRAMEDET, /**< MODEM_FRAMEDET Signal. */ + prsSignalMODEM_TIMDET = PRS_MODEM_TIMDET, /**< MODEM_TIMDET Signal. */ + prsSignalMODEM_SYNCSENT = PRS_MODEM_SYNCSENT, /**< MODEM_SYNCSENT Signal. */ + prsSignalMODEM_PRESENT = PRS_MODEM_PRESENT, /**< MODEM_PRESENT Signal. */ + prsSignalMODEM_ANT0 = PRS_MODEM_ANT0, /**< MODEM_ANT0 Signal. */ + prsSignalMODEM_ANT1 = PRS_MODEM_ANT1, /**< MODEM_ANT1 Signal. */ +#endif +#if defined(PRS_MODEM_FRAMESENT) + prsSignalMODEM_FRAMESENT = PRS_MODEM_FRAMESENT, /**< MODEM_FRAMESENT Signal. */ +#endif +#if defined(PRS_MODEM_PREDET) + prsSignalMODEM_PREDET = PRS_MODEM_PREDET, /**< MODEM_PREDET Signal. */ +#endif +#if defined(PRS_MODEM_LRDSADET) + prsSignalMODEM_LRDSADET = PRS_MODEM_LRDSADET, /**< MODEM_LRDSADET Signal. */ + prsSignalMODEM_LRDSALIVE = PRS_MODEM_LRDSALIVE, /**< MODEM_LRDSALIVE Signal. */ +#endif +#if defined(PRS_MODEM_LOWCORR) + prsSignalMODEM_LOWCORR = PRS_MODEM_LOWCORR, /**< MODEM_LOWCORR Signal. */ + prsSignalMODEM_NEWSYMBOL = PRS_MODEM_NEWSYMBOL, /**< MODEM_NEWSYMBOL Signal. */ + prsSignalMODEM_NEWWND = PRS_MODEM_NEWWND, /**< MODEM_NEWWND Signal. */ + prsSignalMODEM_POSTPONE = PRS_MODEM_POSTPONE, /**< MODEM_POSTPONE Signal. */ +#endif +#if defined(PRS_MODEMH_PRESENT) + prsSignalMODEMH_PRESENT = PRS_MODEMH_PRESENT, /**< MODEMH_PRESENT Signal. */ + prsSignalMODEMH_RSSIJUMP = PRS_MODEMH_RSSIJUMP, /**< MODEMH_RSSIJUMP Signal. */ + prsSignalMODEMH_SYNCSENT = PRS_MODEMH_SYNCSENT, /**< MODEMH_SYNCSENT Signal. */ + prsSignalMODEMH_TIMDET = PRS_MODEMH_TIMDET, /**< MODEMH_TIMDET Signal. */ + prsSignalMODEMH_WEAK = PRS_MODEMH_WEAK, /**< MODEMH_WEAK Signal. */ + prsSignalMODEMH_EOF = PRS_MODEMH_EOF, /**< MODEMH_EOF Signal. */ +#endif +#if defined(PRS_MODEMH_SI) + prsSignalMODEMH_SI = PRS_MODEMH_SI, /**< MODEMH_SI Signal. */ +#endif +#if defined(PRS_FRC_DCLK) + prsSignalFRC_DCLK = PRS_FRC_DCLK, /**< FRC_DCLK Signal. */ + prsSignalFRC_DOUT = PRS_FRC_DOUT, /**< FRC_DOUT Signal. */ +#endif +#if defined(PRS_PROTIMERL_BOF) + prsSignalPROTIMERL_BOF = PRS_PROTIMERL_BOF, /**< PROTIMERL_BOF Signal. */ + prsSignalPROTIMERL_CC0 = PRS_PROTIMERL_CC0, /**< PROTIMERL_CC0 Signal. */ + prsSignalPROTIMERL_CC1 = PRS_PROTIMERL_CC1, /**< PROTIMERL_CC1 Signal. */ + prsSignalPROTIMERL_CC2 = PRS_PROTIMERL_CC2, /**< PROTIMERL_CC2 Signal. */ + prsSignalPROTIMERL_CC3 = PRS_PROTIMERL_CC3, /**< PROTIMERL_CC3 Signal. */ + prsSignalPROTIMERL_CC4 = PRS_PROTIMERL_CC4, /**< PROTIMERL_CC4 Signal. */ + prsSignalPROTIMERL_LBTF = PRS_PROTIMERL_LBTF, /**< PROTIMERL_LBTF Signal. */ + prsSignalPROTIMERL_LBTR = PRS_PROTIMERL_LBTR, /**< PROTIMERL_LBTR Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTR) + prsSignalPROTIMER_LBTR = PRS_PROTIMER_LBTR, /**< PROTIMER_LBTR Signal. */ + prsSignalPROTIMER_LBTF = PRS_PROTIMER_LBTF, /**< PROTIMER_LBTF Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTS) + prsSignalPROTIMER_LBTS = PRS_PROTIMER_LBTS, /**< PROTIMER_LBTS Signal. */ +#endif +#if defined(PRS_PROTIMER_POF) + prsSignalPROTIMER_POF = PRS_PROTIMER_POF, /**< PROTIMER_POF Signal. */ + prsSignalPROTIMER_T0MATCH = PRS_PROTIMER_T0MATCH, /**< PROTIMER_T0MATCH Signal. */ + prsSignalPROTIMER_T0UF = PRS_PROTIMER_T0UF, /**< PROTIMER_T0UF Signal. */ + prsSignalPROTIMER_T1MATCH = PRS_PROTIMER_T1MATCH, /**< PROTIMER_T1MATCH Signal. */ + prsSignalPROTIMER_T1UF = PRS_PROTIMER_T1UF, /**< PROTIMER_T1UF Signal. */ + prsSignalPROTIMER_WOF = PRS_PROTIMER_WOF, /**< PROTIMER_WOF Signal. */ +#endif +#if defined(PRS_RAC_ACTIVE) + prsSignalRAC_ACTIVE = PRS_RAC_ACTIVE, /**< RAC_ACTIVE Signal. */ + prsSignalRAC_LNAEN = PRS_RAC_LNAEN, /**< RAC_LNAEN Signal. */ + prsSignalRAC_PAEN = PRS_RAC_PAEN, /**< RAC_PAEN Signal. */ + prsSignalRAC_RX = PRS_RAC_RX, /**< RAC_RX Signal. */ + prsSignalRAC_TX = PRS_RAC_TX, /**< RAC_TX Signal. */ +#endif +#if defined(PRS_RACL_ACTIVE) + prsSignalRACL_ACTIVE = PRS_RACL_ACTIVE, /**< RACL_ACTIVE Signal. */ + prsSignalRACL_LNAEN = PRS_RACL_LNAEN, /**< RACL_LNAEN Signal. */ + prsSignalRACL_PAEN = PRS_RACL_PAEN, /**< RACL_PAEN Signal. */ + prsSignalRACL_RX = PRS_RACL_RX, /**< RACL_RX Signal. */ + prsSignalRACL_TX = PRS_RACL_TX, /**< RACL_TX Signal. */ + prsSignalRACL_CTIOUT0 = PRS_RACL_CTIOUT0, /**< RACL_CTIOUT0 Signal. */ + prsSignalRACL_CTIOUT1 = PRS_RACL_CTIOUT1, /**< RACL_CTIOUT1 Signal. */ + prsSignalRACL_CTIOUT2 = PRS_RACL_CTIOUT2, /**< RACL_CTIOUT2 Signal. */ +#endif +#if defined(PRS_RAC_CTIOUT3) + prsSignalRAC_CTIOUT3 = PRS_RAC_CTIOUT3, /**< RAC_CTIOUT3 Signal. */ +#endif +#if defined(PRS_RAC_AUXADCDATA) + prsSignalRAC_AUXADCDATA = PRS_RAC_AUXADCDATA, /**< RAC_AUXADCDATA Signal. */ + prsSignalRAC_AUXADCDATAVALID = PRS_RAC_AUXADCDATAVALID, /**< RAC_AUXADCDATAVALID Signal. */ +#endif +#if defined(PRS_SYNTH_MUX0) + prsSignalSYNTH_MUX0 = PRS_SYNTH_MUX0, /**< SYNTH_MUX0 Signal. */ + prsSignalSYNTH_MUX1 = PRS_SYNTH_MUX1, /**< SYNTH_MUX1 Signal. */ +#endif +#if defined(PRS_PRORTC_CCV0) + prsSignalPRORTC_CCV0 = PRS_PRORTC_CCV0, /**< PRORTC_CCV0 Signal. */ + prsSignalPRORTC_CCV1 = PRS_PRORTC_CCV1, /**< PRORTC_CCV1 Signal. */ +#endif +#if defined(RFFPLL0) + prsSignalRFFPLL0L_CLKDIGDIV4 = PRS_RFFPLL0L_CLKDIGDIV4, /**< RFFPLL0L CLKDIGDIV4 Signal. */ + prsSignalRFFPLL0L_CLKMODEMDIV4 = PRS_RFFPLL0L_CLKMODEMDIV4, /**< RFFPLL0L CLKMODEMDIV4 Signal. */ +#if defined(PRS_RFFPLL0L_RFBIASFSMSTATE0) + prsSignalRFFPLL0L_RFBIASFSMSTATE0 = PRS_RFFPLL0L_RFBIASFSMSTATE0, /**< RFFPLL0L RFBIASFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE1 = PRS_RFFPLL0L_RFBIASFSMSTATE1, /**< RFFPLL0L RFBIASFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE0 = PRS_RFFPLL0L_RFFPLLFSMSTATE0, /**< RFFPLL0L RFFPLLFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE1 = PRS_RFFPLL0L_RFFPLLFSMSTATE1, /**< RFFPLL0L RFFPLLFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE2 = PRS_RFFPLL0L_RFFPLLFSMSTATE2, /**< RFFPLL0L RFFPLLFSMSTATE2 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE2 = PRS_RFFPLL0L_RFBIASFSMSTATE2, /**< RFFPLL0L RFBIASFSMSTATE2 Signal. */ + prsSignalRFFPLL0_RFFPLLFSMSTATE3 = PRS_RFFPLL0_RFFPLLFSMSTATE3, /**< RFFPLL0 RFFPLLFSMSTATE3 Signal. */ +#endif +#endif +#if defined(FEFILT0) + prsSignalFEFILT0_REMPTY = PRS_FEFILT0_REMPTY, /**< FEFILT0 REMPTY Signal. */ + prsSignalFEFILT0_WFULL = PRS_FEFILT0_WFULL, /**< FEFILT0 WFULL Signal. */ +#endif +#if defined(FEFILT0) + prsSignalFEFILT1_REMPTY = PRS_FEFILT1_REMPTY, /**< FEFILT1 REMPTY Signal. */ + prsSignalFEFILT1_WFULL = PRS_FEFILT1_WFULL, /**< FEFILT1 WFULL Signal. */ +#endif +#if defined(ETAMPDET) + prsSignalETAMPDET_TAMPERSRCETAMPDET = PRS_ETAMPDET_TAMPERSRCETAMPDET, /**< ETAMPDET TAMPERSRCETAMPDET Signal. */ +#endif +#if defined(SMCTRL) + prsSignalSMCTRLL_SOFTM0 = PRS_SMCTRLL_SOFTM0, /**< SMCTRLL SOFTM0 Signal. */ + prsSignalSMCTRLL_SOFTM1 = PRS_SMCTRLL_SOFTM1, /**< SMCTRLL SOFTM1 Signal. */ + prsSignalSMCTRLL_SOFTM2 = PRS_SMCTRLL_SOFTM2, /**< SMCTRLL SOFTM2 Signal. */ + prsSignalSMCTRLL_SOFTM3 = PRS_SMCTRLL_SOFTM3, /**< SMCTRLL SOFTM3 Signal. */ + prsSignalSMCTRLL_SOFTM4 = PRS_SMCTRLL_SOFTM4, /**< SMCTRLL SOFTM4 Signal. */ + prsSignalSMCTRLL_SOFTM5 = PRS_SMCTRLL_SOFTM5, /**< SMCTRLL SOFTM5 Signal. */ + prsSignalSMCTRLL_SOFTM6 = PRS_SMCTRLL_SOFTM6, /**< SMCTRLL SOFTM6 Signal. */ + prsSignalSMCTRLL_SOFTM7 = PRS_SMCTRLL_SOFTM7, /**< SMCTRLL SOFTM7 Signal. */ + prsSignalSMCTRL_SOFTM8 = PRS_SMCTRL_SOFTM8, /**< SMCTRL SOFTM8 Signal. */ + prsSignalSMCTRL_SOFTM9 = PRS_SMCTRL_SOFTM9, /**< SMCTRL SOFTM9 Signal. */ + prsSignalSMCTRL_SOFTM10 = PRS_SMCTRL_SOFTM10, /**< SMCTRL SOFTM10 Signal. */ + prsSignalSMCTRL_SOFTM11 = PRS_SMCTRL_SOFTM11, /**< SMCTRL SOFTM11 Signal. */ +#endif +#if defined(PRS_SEHFRCO_COREEN) + prsSignalSEHFRCO_COREEN = PRS_SEHFRCO_COREEN, /**< SEHFRCO COREEN Signal. */ + prsSignalSEHFRCO_STATE0 = PRS_SEHFRCO_STATE0, /**< SEHFRCO STATE0 Signal. */ + prsSignalSEHFRCO_STATE1 = PRS_SEHFRCO_STATE1, /**< SEHFRCO STATE1 Signal. */ + prsSignalSEHFRCO_STATE2 = PRS_SEHFRCO_STATE2, /**< SEHFRCO STATE2 Signal. */ +#endif +#if defined(PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY) + prsSignalSEATAMPDET_SEATAMPDETSUPTPDELAY = PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY, /**< SEATAMPDET SEATAMPDETSUPTPDELAY Signal. */ +#endif +#if defined(PRS_DCDC_MONO70NSANA) + prsSignalDCDC_MONO70NSANA = PRS_DCDC_MONO70NSANA, /** DCDC Pulses for Coulomb Counter Calibration Signal. */ +#endif +#if defined(PRS_LFRCO_CALMEAS) + prsSignalLFRCO_CALMEAS = PRS_LFRCO_CALMEAS, /** LFRCO Calibration Measure Signal. */ + prsSignalLFRCO_SDM = PRS_LFRCO_SDM, /** LFRCO Sigma Delta Modulator output Signal. */ + prsSignalLFRCO_TCMEAS = PRS_LFRCO_TCMEAS, /** LFRCO Temperature Check Measure Signal. */ +#endif +} PRS_Signal_t; + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Consumers. */ +typedef enum { + prsConsumerNone = 0x000, /**< No PRS consumer */ + prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ + prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ +#if defined(IADC_PRESENT) + prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ + prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ +#endif + prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ + prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ +#if defined(LETIMER0) + prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_CLEAR), /**< LETIMER0 clear consumer. */ + prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_START), /**< LETIMER0 start consumer. */ + prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_STOP), /**< LETIMER0 stop consumer. */ +#endif + prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ + prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ + prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ + prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ + prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ + prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ + prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ + prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ + prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ + prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ + prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ + prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ +#if defined(TIMER4) + prsConsumerTIMER4_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC0), /**< TIMER4 capture/compare channel 0 consumer. */ + prsConsumerTIMER4_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC1), /**< TIMER4 capture/compare channel 1 consumer. */ + prsConsumerTIMER4_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC2), /**< TIMER4 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER5) + prsConsumerTIMER5_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC0), /**< TIMER5 capture/compare channel 0 consumer. */ + prsConsumerTIMER5_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC1), /**< TIMER5 capture/compare channel 1 consumer. */ + prsConsumerTIMER5_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC2), /**< TIMER5 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER6) + prsConsumerTIMER6_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC0), /**< TIMER6 capture/compare channel 0 consumer. */ + prsConsumerTIMER6_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC1), /**< TIMER6 capture/compare channel 1 consumer. */ + prsConsumerTIMER6_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC2), /**< TIMER6 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER7) + prsConsumerTIMER7_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC0), /**< TIMER7 capture/compare channel 0 consumer. */ + prsConsumerTIMER7_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC1), /**< TIMER7 capture/compare channel 1 consumer. */ + prsConsumerTIMER7_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC2), /**< TIMER7 capture/compare channel 2 consumer. */ +#endif +#if defined(USART0) + prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ + prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ + prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 RX consumer. */ + prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ +#endif +#if defined(USART1) + prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ + prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ + prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 TX consumer. */ + prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ +#endif +#if defined(USART2) + prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ + prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ + prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 RX consumer. */ + prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ +#endif +#if defined(EUSART0) + prsConsumerEUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART0_CLK), /**< EUSART0 clk consumer. */ + prsConsumerEUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART0_RX), /**< EUSART0 RX consumer. */ + prsConsumerEUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART0_TRIGGER), /**< EUSART0 trigger consumer. */ +#endif +#if defined(EUSART1) + prsConsumerEUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART1_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART1_RX), /**< EUSART1 RX consumer. */ + prsConsumerEUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART1_TRIGGER), /**< EUSART1 trigger consumer. */ +#endif +#if defined(EUSART2) + prsConsumerEUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART2_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART2_RX), /**< EUSART2 RX consumer. */ + prsConsumerEUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART2_TRIGGER), /**< EUSART2 trigger consumer. */ +#endif +#if defined(EUSART3) + prsConsumerEUSART3_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART3_RX), /**< EUSART3 RX consumer. */ + prsConsumerEUSART3_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART3_TRIGGER), /**< EUSART3 trigger consumer. */ +#endif +#if defined(EUSART4) + prsConsumerEUSART4_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART4_RX), /**< EUSART4 RX consumer. */ + prsConsumerEUSART4_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART4_TRIGGER), /**< EUSART4 trigger consumer. */ +#endif +#if defined(EUART0) + prsConsumerEUART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUART0_RX), /**< EUART0 RX consumer. */ + prsConsumerEUART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUART0_TRIGGER), /**< EUART0 TRIGGER Consumer. */ +#endif + prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ + prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ +#if defined(WDOG1) + prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ + prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ +#endif +#if defined(PCNT0) + prsConsumerPCNT0_IN0 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S0IN), /**< PCNT0 input 0 consumer. */ + prsConsumerPCNT0_IN1 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S1IN), /**< PCNT0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_RTCC_CC2_MASK) + prsConsumerRTCC_CC0 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC0), /**< RTCC capture/compare channel 0 consumer. */ + prsConsumerRTCC_CC1 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC1), /**< RTCC capture/compare channel 1 consumer. */ + prsConsumerRTCC_CC2 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC2), /**< RTCC capture/compare channel 2 consumer. */ +#endif +#if defined(SYSRTC0) + prsConsumerSYSRTC0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN0), /**< SYSRTC0 input 0 consumer. */ + prsConsumerSYSRTC0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN1), /**< SYSRTC0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_HFXO0_OSCREQ_MASK) + prsConsumerHFXO0_OSCREQ = offsetof(PRS_TypeDef, CONSUMER_HFXO0_OSCREQ), /**< OSCREQ consumer. */ + prsConsumerHFXO0_TIMEOUT = offsetof(PRS_TypeDef, CONSUMER_HFXO0_TIMEOUT), /**< HFXO0_TIMEOUT consumer. */ +#endif +#if defined(LESENSE) + prsConsumerLESENSE_START = offsetof(PRS_TypeDef, CONSUMER_LESENSE_START), /**< LESENSE_START consumer. */ +#endif +#if defined(VDAC0) + prsConsumerVDAC0_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH0), /**< VDAC0 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH1), /**< VDAC0 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH0), /**< VDAC0 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH1), /**< VDAC0 SYNC TRIGER CH1 consumer. */ +#endif +#if defined(VDAC1) + prsConsumerVDAC1_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH0), /**< VDAC1 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH1), /**< VDAC1 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH0), /**< VDAC1 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH1), /**< VDAC1 SYNC TRIGER CH1 consumer. */ +#endif +} PRS_Consumer_t; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set level control bit for one or more channels. + * + * @details + * The level value for a channel is XORed with both the pulse possibly issued + * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Note that software level control is only available for asynchronous + * channels on Series 2 devices. + * @endcond + * + * @param[in] level + * Level to use for channels indicated by @p mask. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. + * + * @param[in] mask + * Mask indicating which channels to set level for. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) +{ +#if defined(_PRS_SWLEVEL_MASK) + PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); +#else + PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); +#endif +} + +/***************************************************************************//** + * @brief + * Get level control bit for all channels. + * + * @return + * The current software level configuration. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_LevelGet(void) +{ +#if defined(_PRS_SWLEVEL_MASK) + return PRS->SWLEVEL; +#else + return PRS->ASYNC_SWLEVEL; +#endif +} + +#if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) +/***************************************************************************//** + * @brief + * Get the PRS channel values for all channels. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output values for all channels as a bitset. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) +{ +#if defined(_PRS_ASYNC_PEEK_MASK) + if (type == prsTypeAsync) { + return PRS->ASYNC_PEEK; + } else { + return PRS->SYNC_PEEK; + } +#else + (void) type; + return PRS->PEEK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the PRS channel value for a single channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output value. This is either 0 or 1. + ******************************************************************************/ +__STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) +{ + return (0UL != ((PRS_Values(type) >> ch) & 0x1U)); +} +#endif + +/***************************************************************************//** + * @brief + * Trigger a high pulse (one HFPERCLK) for one or more channels. + * + * @details + * Setting a bit for a channel causes the bit in the register to remain high + * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit + * in PRS SWLEVEL register and the PRS input signal selected for the + * channel(s). + * + * @param[in] channels + * Logical ORed combination of channels to trigger a pulse for. Use + * PRS_SWPULSE_CHnPULSE defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) +{ +#if defined(_PRS_SWPULSE_MASK) + PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; +#else + PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the PRS channel level for one asynchronous PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] level + * true to set the level high (1) and false to set the level low (0). + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) +{ + PRS_LevelSet((uint32_t) level << ch, 0x1UL << ch); +} + +/***************************************************************************//** + * @brief + * Trigger a pulse on one PRS channel. + * + * @param[in] ch + * PRS channel number. + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) +{ + PRS_PulseTrigger(0x1UL << ch); +} + +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge); + +#if defined(PRS_ASYNC_SUPPORTED) +void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal); +#endif +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location); +#endif + +int PRS_GetFreeChannel(PRS_ChType_t type); +void PRS_Reset(void); +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); +#if defined(_SILICON_LABS_32B_SERIES_2) +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource); +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal); +void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); +void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); +void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); +#endif + +/** @} (end addtogroup prs) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ +#endif /* EM_PRS_H */ diff --git a/Libs/platform/emlib/inc/em_ramfunc.h b/Libs/platform/emlib/inc/em_ramfunc.h new file mode 100644 index 0000000..2779c55 --- /dev/null +++ b/Libs/platform/emlib/inc/em_ramfunc.h @@ -0,0 +1,169 @@ +/***************************************************************************//** + * @file + * @brief RAM code support. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RAMFUNC_H +#define EM_RAMFUNC_H + +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +/***************************************************************************//** + * @addtogroup ramfunc RAMFUNC - RAM Function Support + * @brief RAM code support + * @details + * Provides support for executing code from RAM. + * Provides a unified method to manage RAM code across all supported tools. + * @{ + + @note + Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common). + + @note + Functions executing from RAM should not be declared as static. + + @warning + Standard library facilities are available to the tool with GCC in hosted + mode (default), regardless of the section attribute. Calls to standard + libraries placed in the default section may therefore occur. To disable + hosted mode, add '-ffreestanding' to the build command line. This is the + only way to guarantee no calls to standard libraries with GCC. + Read more at www.gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html + + @warning + Keil/ARM uVision users must add a section named "ram_code" in their linker + scatter file. This section must be in RAM memory. Look in the MCU SDK for + example scatter files (ram_code.sct). + + @n @section ramfunc_usage Usage + + In your .h file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DECLARATOR + void MyPrint(const char* string); + @endverbatim + + Issues have been observed with ARM GCC when there is no declarator. It is + recommended to have a declarator also for internal functions but move the + declarator to the .c file. + + In your .c file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DEFINITION_BEGIN + void MyPrint(const char* string) + { + ... + } + SL_RAMFUNC_DEFINITION_END + @endverbatim + + ******************************************************************************/ +/* *INDENT-ON* */ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * This define is not present by default. By compiling with define + * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros + * will be placed in default code space (Flash) instead. + * + * @note + * This define is not present by default. + */ +#if defined(DOXY_DOC_ONLY) +#define SL_RAMFUNC_DISABLE +#endif + +#if defined(SL_RAMFUNC_DISABLE) +/** @brief Compiler ported function declarator for RAM code. */ +#define SL_RAMFUNC_DECLARATOR + +/** @brief Compiler ported function definition begin marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_BEGIN + +/** @brief Compiler ported function definition end marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__CC_ARM) +/* MDK-ARM compiler */ +#define SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") +#define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") + +#elif defined(__ICCARM__) +/* IAR Embedded Workbench */ +#define SL_RAMFUNC_DECLARATOR SL_CODE_RAM +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && (defined(__CROSSWORKS_ARM) || defined(__SES_ARM)) +/* Rowley Crossworks and Segger Embedded Studio */ +#define SL_RAMFUNC_DECLARATOR SL_CODE_RAM +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32) +/* Zephyr environment */ +#define SL_RAMFUNC_DECLARATOR SL_CODE_RAM +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) +/* Simplicity Studio, Atollic and Vanilla armgcc */ +#define SL_RAMFUNC_DECLARATOR SL_CODE_RAM +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated macro names */ +#define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +/** @endcond */ + +/** @} (end addtogroup ramfunc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_RAMFUNC_H */ diff --git a/Libs/platform/emlib/inc/em_rmu.h b/Libs/platform/emlib/inc/em_rmu.h new file mode 100644 index 0000000..81304c0 --- /dev/null +++ b/Libs/platform/emlib/inc/em_rmu.h @@ -0,0 +1,178 @@ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RMU_H +#define EM_RMU_H + +#include "em_device.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) +#include "sl_assert.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup rmu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** RMU reset modes. */ +typedef enum { +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, /**< Reset mode disabled. */ + rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, /**< Reset mode limited. */ + rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, /**< Reset mode extended. */ + rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, /**< Reset mode full. */ +#elif defined(_EMU_RSTCTRL_MASK) + rmuResetModeDisabled = 0, /**< Reset mode disabled. */ + rmuResetModeEnabled = 1, /**< Reset mode enabled. */ +#else + rmuResetModeClear = 0, /**< Reset mode clear. */ + rmuResetModeSet = 1, /**< Reset mode set. */ +#endif +} RMU_ResetMode_TypeDef; + +/** RMU controlled peripheral reset control and reset source control. */ +typedef enum { +#if defined(RMU_CTRL_BURSTEN) + rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ +#endif +#if defined(RMU_CTRL_LOCKUPRDIS) + rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ +#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_WDOGRMODE_MASK) + rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ +#endif +#if defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_SYSRMODE_MASK) + rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ +#endif +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ +#endif + +#if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) + rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ +#endif +#if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) + rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ +#endif +#if defined(_EMU_RSTCTRL_SYSRMODE_MASK) + rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ +#endif +#if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ +#endif +#if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) + rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) + rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD1BODRMODE_MASK) + rmuResetIOVDD1 = _EMU_RSTCTRL_IOVDD1BODRMODE_MASK, /**< IOVDD1 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD2BODRMODE_MASK) + rmuResetIOVDD2 = _EMU_RSTCTRL_IOVDD2BODRMODE_MASK, /**< IOVDD2 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) + rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_SESYSRMODE_MASK) + rmuResetSESys = _EMU_RSTCTRL_SESYSRMODE_MASK, /**< M0+ (SE) system reset select */ +#endif +#if defined(_EMU_RSTCTRL_SELOCKUPRMODE_MASK) + rmuResetSELockup = _EMU_RSTCTRL_SELOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ +#endif +#if defined(_EMU_RSTCTRL_DCIRMODE_MASK) + rmuResetDCI = _EMU_RSTCTRL_DCIRMODE_MASK, /**< DCI reset select */ +#endif +} RMU_Reset_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/** RMU_LockupResetDisable kept for backwards compatibility. */ +#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) + +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); +void RMU_ResetCauseClear(void); +uint32_t RMU_ResetCauseGet(void); + +#if defined(_RMU_CTRL_RESETSTATE_MASK) +/***************************************************************************//** + * @brief + * Set user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @param[in] userState User state to set + ******************************************************************************/ +__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) +{ + EFM_ASSERT(!(userState + & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); + RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) + | (userState << _RMU_CTRL_RESETSTATE_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @return + * Reset surviving user state. + ******************************************************************************/ +__STATIC_INLINE uint32_t RMU_UserResetStateGet(void) +{ + uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) + >> _RMU_CTRL_RESETSTATE_SHIFT; + return userState; +} +#endif + +/** @} (end addtogroup rmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ +#endif /* EM_RMU_H */ diff --git a/Libs/platform/emlib/inc/em_smu.h b/Libs/platform/emlib/inc/em_smu.h new file mode 100644 index 0000000..c36cf98 --- /dev/null +++ b/Libs/platform/emlib/inc/em_smu.h @@ -0,0 +1,1762 @@ +/***************************************************************************//** + * @file + * @brief Security Management Unit (SMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup smu SMU - Security Management Unit + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * SMU forms the control and status/reporting component of bus-level + * security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the Peripheral Protection Unit + * (PPU). PPU provides hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ +#if defined(_SMU_PPUPATD0_CSEN_SHIFT) + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ +#endif +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#if defined(_SMU_PPUPATD0_ACMP0_SHIFT) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ +#endif +#if defined(_SMU_PPUPATD0_ACMP1_SHIFT) + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ +#endif +#if defined(_SMU_PPUPATD0_ADC0_SHIFT) + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ +#endif + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ +#if defined(_SMU_PPUPATD0_LESENSE_SHIFT) + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ +#endif + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ +#if defined(_SMU_PPUPATD0_PCNT0_SHIFT) + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ +#endif + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */ + smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */ + smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ + smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */ + smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SMU_PPUPATD0_SCRATCHPAD) + smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */ +#endif + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ +#if defined(_SMU_PPUPATD0_HFXO0_SHIFT) + smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif + smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */ + smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */ + smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */ + smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */ + smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */ + smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */ + smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */ +#if defined(_SMU_PPUPATD0_TIMER4_SHIFT) + smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER5_SHIFT) + smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER6_SHIFT) + smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER7_SHIFT) + smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */ +#endif +#if defined(_SMU_PPUPATD0_USART0_SHIFT) + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ +#endif +#if defined(_SMU_PPUPATD0_USART1_SHIFT) + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ +#endif +#if defined(_SMU_PPUPATD0_USART2_SHIFT) + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ +#endif + smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */ +#if defined(_SMU_PPUPATD0_I2C1_SHIFT) + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ +#endif +#if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT) + smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */ +#endif +#if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT) + smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */ +#endif + +#if defined(SMU_PPUPATD0_LVGD) + smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */ +#endif + smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */ +#if defined(_SMU_PPUPATD0_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD1_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT) + smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/ +#endif +#if defined(_SMU_PPUPATD0_GPCRC_SHIFT) + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD1_GPCRC_SHIFT) + smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD0_DCDC_SHIFT) + smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD0_RTCC_SHIFT) + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT) + smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_EUSART0_SHIFT) + smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART1_SHIFT) + smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART1_SHIFT) + smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART2_SHIFT) + smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART2_SHIFT) + smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART3_SHIFT) + smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART4_SHIFT) + smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */ +#endif +#if defined(_SMU_PPUPATD1_RTCC_SHIFT) + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD1_SYSRTC_SHIFT) + smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */ +#endif +#if defined(_SMU_PPUPATD1_LCD_SHIFT) + smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */ +#endif +#if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT) + smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */ +#endif +#if defined(_SMU_PPUPATD1_DMEM_SHIFT) + smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */ +#endif +#if defined(_SMU_PPUPATD1_LCDRF_SHIFT) + smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */ +#endif +#if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT) + smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */ +#endif +#if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT) + smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */ +#endif +#if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT) + smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */ +#endif +#if defined(_SMU_PPUPATD1_VDAC0_SHIFT) + smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ +#endif +#if defined(_SMU_PPUPATD1_VDAC1_SHIFT) + smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */ +#endif +#if defined(_SMU_PPUPATD1_PCNT_SHIFT) + smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */ +#endif +#if defined(_SMU_PPUPATD1_LESENSE_SHIFT) + smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ +#endif +#if defined(_SMU_PPUPATD1_HFRCO1_SHIFT) + smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_DCDC_SHIFT) + smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD1_PDM_SHIFT) + smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */ +#endif +#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT) + smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */ +#endif +#if defined(_SMU_PPUPATD1_SEPUF_SHIFT) + smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */ +#endif + smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */ +#if defined(_SMU_PPUPATD1_IADC0_SHIFT) + smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP0_SHIFT) + smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP1_SHIFT) + smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ +#endif +#if defined(_SMU_PPUPATD1_I2C0_SHIFT) + smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ +#endif +#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT) + smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ +#if defined(_SMU_PPUPATD1_WDOG1_SHIFT) + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ +#endif + smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */ +#if defined(_SMU_PPUPATD1_RADIOAES_SHIFT) + smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */ +#endif +#if defined(_SMU_PPUPATD1_EUART0_SHIFT) + smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */ +#endif +#if defined(_SMU_PPUPATD1_BUFC_SHIFT) + smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ +#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT) + smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */ +#endif +#if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT) + smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */ +#endif +#if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT) + smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */ +#endif +#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT) + smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_MVP_SHIFT) + smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */ +#endif +#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT) + smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */ +#endif +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd /**< SMU peripheral end. */ +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedETH : 1; /**< Privileged access enabler for ETH. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */ + bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + + bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */ + bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */ + bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */ + bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { +#if defined(_SMU_PPUNSPATD2_MASK) + uint32_t reg[3]; /**< Peripheral access control array.*/ +#else + uint32_t reg[2]; /**< Peripheral access control array.*/ +#endif + SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/ + } ppu; /**< PPU init array.*/ + bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +/** Default SMU initialization structure settings. */ +#define SMU_INIT_DEFAULT { \ + { { 0 } }, /* No peripherals access protected. */ \ + true /* Enable SMU.*/ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable PPU of SMU. + * + * @param[in] enable + * Set to true to enable PPU; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ +#if defined (_SMU_PPUCTRL_ENABLE_SHIFT) + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +#else + (void)enable; +#endif +} + +/***************************************************************************//** + * @brief + * Initialize PPU of SMU. + * + * @param[in] init + * Pointer to initialization structure that defines which peripherals should + * only be accessed from privileged mode, and if PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0]; + SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#else + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU->PPUPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#endif //SL_TRUSTZONE_SECURE + + SMU_EnablePPU(init->enable); +} +/***************************************************************************//** + * @brief + * Change access settings for a peripheral. + * + * @details + * Set to limit access of a peripheral from privileged mode. + * + * @param[in] peripheral + * ID of the peripheral to change access settings for. + * + * @param[in] privileged + * Set to true if the peripheral should only be accessed from privileged + * mode; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + if (peripheral < 32) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#else + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the peripheral that caused an access fault. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS; +#else + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_CLR = flags; +#else + SMU->IF_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFC = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_CLR = flags; +#else + SMU->IEN_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN &= ~flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * SMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_SET = flags; +#else + SMU->IEN_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN |= flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return SMU_NS_CFGNS->NSIF; +#else + return SMU->IF; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU_NS_CFGNS->NSIEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU_NS_CFGNS->NSIF & tmp; +#else + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU->IF & tmp; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_SET = flags; +#else + SMU->IF_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFS = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/**************************************************************************//** +* @brief +* SMU secure IRQ Handler. +* +* @details +* When a PPU detects an access to a secure peripheral at its non-secure +* address or an access to a non-secure peripheral at its secure +* address, PPUSECIF in SMU_IF is set and the ID of the peripheral being +* accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's +* Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler +* Will handle the interrupt. +******************************************************************************/ +#if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2) +void SMU_SECURE_IRQHandler(void) +{ + if (SMU_IF_PPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC); + } + + if (SMU_IF_BMPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC); + } + + // PPUFS contains the ID of the peripheral caused the fault + // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields. + EFM_ASSERT(SMU->PPUFS); + + while (1) { + // do nothing + } +} +#endif //SL_TRUSTZONE_SECURE + +/** @} (end addtogroup smu) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/Libs/platform/emlib/inc/em_syscfg.h b/Libs/platform/emlib/inc/em_syscfg.h new file mode 100644 index 0000000..1d6a783 --- /dev/null +++ b/Libs/platform/emlib/inc/em_syscfg.h @@ -0,0 +1,174 @@ +/***************************************************************************//** + * @file + * @brief API defining acces to SYSCFG registers + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSCFG_H +#define EM_SYSCFG_H + +#include "em_device.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_service_syscfg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SYSCFG) +/******************************************************************************* + ******************************** TZ SERVICES ********************************** + ******************************************************************************/ + +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) +/******************************************************************************* + * @brief Reads CHIPREV register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readChipRev(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_chiprev_register(); +#else +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + return SYSCFG->CHIPREV; +#endif +} +#endif // defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + +#if defined(_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) +/******************************************************************************* + * @brief Sets DMEM0RAMCTRL RAMWSEN bit to 1 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); +#else + + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL | _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Clears DMEM0RAMCTRL RAMWSEN bit to 0 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); +#else + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Reads DMEM0RAMCTRL RAMWSEN bit + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); +#else + return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; +#endif +} + +#endif //_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) + +/******************************************************************************* + * @brief Reads DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_dmem0retnctrl_register(); +#else + return SYSCFG->DMEM0RETNCTRL; +#endif +} +/******************************************************************************* + * @brief Mask DMEM0RETNCTRL register with provided mask + * + * @param mask - A mask that is to be used to mask the DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_mask_dmem0retnctrl_register(mask); +#else + SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; +#endif +} + +/******************************************************************************* + * @brief Set DMEM0RETNCTRL to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_zero_dmem0retnctrl_register(); +#else + SYSCFG->DMEM0RETNCTRL = 0x0UL; +#endif +} +#endif // _SYSCFG_DMEM0RETNCTRL_MASK + +#if defined(_SYSCFG_CFGSYSTIC_MASK) +/******************************************************************************* + * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +/******************************************************************************* + * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} +#endif //_SYSCFG_CFGSYSTIC_MASK +#endif //SYSCFG +#ifdef __cplusplus +} +#endif +#endif // EM_SYSCFG_H diff --git a/Libs/platform/emlib/inc/em_system.h b/Libs/platform/emlib/inc/em_system.h new file mode 100644 index 0000000..f6547f9 --- /dev/null +++ b/Libs/platform/emlib/inc/em_system.h @@ -0,0 +1,365 @@ +/***************************************************************************//** + * @file + * @brief System API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSTEM_H +#define EM_SYSTEM_H + +#include "em_device.h" +#include "em_system_generic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @brief System API + * @details + * This module contains functions to read information such as RAM and Flash size, + * device unique ID, chip revision, family, and part number from DEVINFO and + * SCB blocks. Functions to configure and read status from FPU are available for + * compatible devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family identifiers. */ +typedef enum { +/* New style family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) + systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) + systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) + systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) + systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) + systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) + systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) + systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) + systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) + systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) + systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) + systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) + systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) + systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) + systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L) + systemPartFamilyZen13L = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L, /**< EFR32 Zen Gecko Series 1 Configuration 3 Led Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S) + systemPartFamilyZen13S = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S, /**< EFR32 Zen Gecko Series 1 Configuration 3 Sensor Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) + systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) + systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) + systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) + systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) + systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) + systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) + systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyMightyRcp21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty RCP Series 2 Config 1 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + systemPartFamilyMighty22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyFlex22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyBlue22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyEfm32Pearl22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + systemPartFamilyFlex23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyZen23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyEfm32Pearl23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilySideWalk23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + systemPartFamilyMighty24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyFlex24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyBlue24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 4 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + systemPartFamilyFlex25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 5 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + systemPartFamilyMighty26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyBlue26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyEfm32Pearl26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + systemPartFamilyMighty27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family */ + systemPartFamilyBlue27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 7 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + systemPartFamilyFlex28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyZen28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilySideWalk28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyEfm32Pearl28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + systemPartFamilyMighty29 = DEVINFO_PART_FAMILY_MG | (29 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 9 Value Device Family */ + systemPartFamilyBlue29 = DEVINFO_PART_FAMILY_BG | (29 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 9 Value Device Family */ +#endif +/* Deprecated family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_G) + systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) + systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) + systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) + systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) + systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) + systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) + systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ +#endif + systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. + Family ID is missing + on unprogrammed parts. */ +} SYSTEM_PartFamily_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Chip revision details. */ +typedef struct { + uint8_t minor; /**< Minor revision number. */ + uint8_t major; /**< Major revision number. */ +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + uint16_t partNumber; /**< Device part number. */ +#else + uint8_t family; /**< Device family number. */ +#endif +} SYSTEM_ChipRevision_TypeDef; + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/** Floating point co-processor access modes. */ +typedef enum { + fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ + fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ + fpuAccessReserved = (0xA << 20), /**< Reserved. */ + fpuAccessFull = (0xF << 20) /**< Full access. */ +} SYSTEM_FpuAccess_TypeDef; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void); + +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) +/***************************************************************************//** + * @brief + * Get DEVINFO revision. + * + * @return + * Revision of the DEVINFO contents. + ******************************************************************************/ +__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) +{ +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); +#elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) + >> _DEVINFO_INFO_DEVINFOREV_SHIFT); +#endif +} +#endif + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/***************************************************************************//** + * @brief + * Set floating point co-processor (FPU) access mode. + * + * @param[in] accessMode + * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef + * for details. + ******************************************************************************/ +__STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) +{ + SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; +} +#endif + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif +#endif /* EM_SYSTEM_H */ diff --git a/Libs/platform/emlib/inc/em_system_generic.h b/Libs/platform/emlib/inc/em_system_generic.h new file mode 100644 index 0000000..fffec7f --- /dev/null +++ b/Libs/platform/emlib/inc/em_system_generic.h @@ -0,0 +1,91 @@ +/***************************************************************************//** + * @file + * @brief System API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_SYSTEM_GENERIC_H +#define EM_SYSTEM_GENERIC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family security capability. */ +typedef enum { + securityCapabilityUnknown, /**< Unknown security capability. */ + securityCapabilityNA, /**< Security capability not applicable. */ + securityCapabilityBasic, /**< Basic security capability. */ + securityCapabilityRoT, /**< Root of Trust security capability. */ + securityCapabilitySE, /**< Secure Element security capability. */ + securityCapabilityVault /**< Secure Vault security capability. */ +} SYSTEM_SecurityCapability_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** DEVINFO calibration address/value pair. */ +typedef struct { + uint32_t address; /**< Peripheral calibration register address. */ + uint32_t calValue; /**< Calibration value for register at address. */ +} +SYSTEM_CalAddrVal_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void); +uint64_t SYSTEM_GetUnique(void); +uint8_t SYSTEM_GetProdRev(void); +uint32_t SYSTEM_GetSRAMBaseAddress(void); +uint16_t SYSTEM_GetSRAMSize(void); +uint16_t SYSTEM_GetFlashSize(void); +uint32_t SYSTEM_GetFlashPageSize(void); +uint16_t SYSTEM_GetPartNumber(void); +uint8_t SYSTEM_GetCalibrationTemperature(void); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_SYSTEM_GENERIC_H */ diff --git a/Libs/platform/emlib/inc/em_timer.h b/Libs/platform/emlib/inc/em_timer.h new file mode 100644 index 0000000..b0ae8e3 --- /dev/null +++ b/Libs/platform/emlib/inc/em_timer.h @@ -0,0 +1,1238 @@ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_TIMER_H +#define EM_TIMER_H + +#include "em_device.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup timer + * @{ + ****************************************************************************** + * @deprecated + * Deprecated macro TIMER_CH_VALID for SDID 80, new code should use TIMER_REF_CH_VALID.*/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of TIMER register block pointer reference for assert statements. */ +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) + +/** Validation of TIMER compare/capture channel number. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define TIMER_CH_VALID(ch) ((ch) < 3) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_CH_VALID(ch) _Pragma("GCC warning \"'TIMER_CH_VALID' macro is deprecated for EFR32xG1, Use TIMER_REF_CH_VALID instead\"") ((ch) < 4) +#else +#define TIMER_CH_VALID(ch) ((ch) < 4) +#endif +#else +#define TIMER_CH_VALID(ch) ((ch) < 3) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_REF_CH_VALID(ref, ch) ((ref == TIMER0) ? ((ch) < 3) : ((ch) < 4)) +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_REF_CH_VALID(ref, ch) +#else +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_CH_VALID(ch) +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Timer compare/capture mode. */ +typedef enum { +#if defined (_TIMER_CC_CTRL_MODE_MASK) + timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ +#endif +#if defined (_TIMER_CC_CFG_MODE_MASK) + timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ +#endif +} TIMER_CCMode_TypeDef; + +/** Clock select. */ +typedef enum { +#if defined (_TIMER_CTRL_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ + timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +#if defined (_TIMER_CFG_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ + timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +} TIMER_ClkSel_TypeDef; + +/** Input capture edge select. */ +typedef enum { + /** Rising edges detected. */ + timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, + + /** Falling edges detected. */ + timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, + + /** Both edges detected. */ + timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, + + /** No edge detection, leave signal as is. */ + timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE +} TIMER_Edge_TypeDef; + +/** Input capture event control. */ +typedef enum { + /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ + timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, + /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ + timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, + /** + * PRS output pulse, interrupt flag, and DMA request set on rising edge (if + * input capture edge = BOTH). + */ + timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, + /** + * PRS output pulse, interrupt flag, and DMA request set on falling edge (if + * input capture edge = BOTH). + */ + timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING +} TIMER_Event_TypeDef; + +/** Input edge action. */ +typedef enum { + /** No action taken. */ + timerInputActionNone = _TIMER_CTRL_FALLA_NONE, + + /** Start counter without reload. */ + timerInputActionStart = _TIMER_CTRL_FALLA_START, + + /** Stop counter without reload. */ + timerInputActionStop = _TIMER_CTRL_FALLA_STOP, + + /** Reload and start counter. */ + timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART +} TIMER_InputAction_TypeDef; + +/** Timer mode. */ +typedef enum { +#if defined (_TIMER_CTRL_MODE_MASK) + timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ +#endif +#if defined (_TIMER_CFG_MODE_MASK) + timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ +#endif +} TIMER_Mode_TypeDef; + +/** Compare/capture output action. */ +typedef enum { + /** No action. */ + timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, + + /** Toggle on event. */ + timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, + + /** Clear on event. */ + timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, + + /** Set on event. */ + timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET +} TIMER_OutputAction_TypeDef; + +/** Prescaler. */ +typedef enum { +#if defined (_TIMER_CTRL_PRESC_MASK) + timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +#if defined (_TIMER_CFG_PRESC_MASK) + timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +} TIMER_Prescale_TypeDef; + +/** Peripheral Reflex System signal. */ +typedef uint8_t TIMER_PRSSEL_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector. New code should use an integer instead of + * using these deprecated enum values. */ +#define timerPRSSELCh0 0UL +#define timerPRSSELCh1 1UL +#define timerPRSSELCh2 2UL +#define timerPRSSELCh3 3UL +#define timerPRSSELCh4 4UL +#define timerPRSSELCh5 5UL +#define timerPRSSELCh6 6UL +#define timerPRSSELCh7 7UL +#define timerPRSSELCh8 8UL +#define timerPRSSELCh9 9UL +#define timerPRSSELCh10 10UL +#define timerPRSSELCh11 11UL +/** @endcond */ + +#if defined (_TIMER_CC_CFG_INSEL_MASK) +/** PRS input type */ +typedef enum { + timerPrsInputNone = 0x0, /**< No PRS input. */ + timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, /**< Synchronous PRS selected. */ + timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, /**< Asynchronous level PRS selected. */ + timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, /**< Asynchronous pulse PRS selected. */ +} TIMER_PrsInput_TypeDef; +#endif + +#if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) +/** DT (Dead Time) Fault Actions. */ +typedef enum { +#if defined(_TIMER_DTFC_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +#if defined(_TIMER_DTFCFG_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +} TIMER_DtiFaultAction_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** TIMER initialization structure. */ +typedef struct { + /** Start counting when initialization completed. */ + bool enable; + + /** Counter shall keep running during debug halt. */ + bool debugRun; + + /** Prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** Clock selection. */ + TIMER_ClkSel_TypeDef clkSel; + +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) + /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ + bool count2x; + + /** ATI (Always Track Inputs) makes CCPOL always track + * the polarity of the inputs. */ + bool ati; + + /** Reload-Start Sets COIST + * When enabled, compare output is set to COIST value on a Reload-Start event. */ + bool rssCoist; +#endif + + /** Action on falling input edge. */ + TIMER_InputAction_TypeDef fallAction; + + /** Action on rising input edge. */ + TIMER_InputAction_TypeDef riseAction; + + /** Counting mode. */ + TIMER_Mode_TypeDef mode; + + /** DMA request clear on active. */ + bool dmaClrAct; + + /** Select X2 or X4 quadrature decode mode (if used). */ + bool quadModeX4; + + /** Determines if only counting up or down once. */ + bool oneShot; + + /** Timer can be start/stop/reload by other timers. */ + bool sync; + +#if defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT) + /** Disable ability of timer to start/stop/reload other timers that have their SYNC bit set. */ + bool disSyncOut; +#endif +} TIMER_Init_TypeDef; + +/** Default configuration for TIMER initialization structure. */ +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) +#if (defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT)) +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false, /* Not started/stopped/reloaded by other timers. */ \ + false /* Disable ability to start/stop/reload other timers. */ \ + } +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif + +/** PRS Output configuration. */ +typedef enum { + timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ + timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ + timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ +} TIMER_PrsOutput_t; + +/** TIMER compare/capture initialization structure. */ +typedef struct { + /** Input capture event control. */ + TIMER_Event_TypeDef eventCtrl; + + /** Input capture edge select. */ + TIMER_Edge_TypeDef edge; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p prsInput + * is enabled. + */ + TIMER_PRSSEL_TypeDef prsSel; + + /** Counter underflow output action. */ + TIMER_OutputAction_TypeDef cufoa; + + /** Counter overflow output action. */ + TIMER_OutputAction_TypeDef cofoa; + + /** Counter match output action. */ + TIMER_OutputAction_TypeDef cmoa; + + /** Compare/capture channel mode. */ + TIMER_CCMode_TypeDef mode; + + /** Enable digital filter. */ + bool filter; + + /** Select TIMERnCCx (false) or PRS input (true). */ + bool prsInput; + + /** + * Compare output initial state. Only used in Output Compare and PWM mode. + * When true, the compare/PWM output is set high when the counter is + * disabled. When counting resumes, this value will represent the initial + * value for the compare/PWM output. If the bit is cleared, the output + * will be cleared when the counter is disabled. + */ + bool coist; + + /** Invert output from compare/capture channel. */ + bool outInvert; + + /** + * PRS output configuration. PRS output from a timer can either be a + * pulse output or a level output that follows the CC out value. + */ + TIMER_PrsOutput_t prsOutput; + +#if defined(_TIMER_CC_CFG_INSEL_MASK) + /** When PRS input is used this field is used to configure the type of + * PRS input. */ + TIMER_PrsInput_TypeDef prsInputType; +#endif +} TIMER_InitCC_TypeDef; + +/** Default configuration for TIMER compare/capture initialization structure. */ +#if defined(_TIMER_CC_CFG_INSEL_MASK) +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + timerPrsInputNone /* No PRS input, so input type is none. */ \ + } +#else +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + } +#endif + +#if defined(_TIMER_DTCTRL_MASK) +/** TIMER Dead Time Insertion (DTI) initialization structure. */ +typedef struct { + /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ + bool enable; + + /** DTI Output Polarity. */ + bool activeLowOut; + + /** DTI Complementary Output Invert. */ + bool invertComplementaryOut; + + /** Enable Automatic Start-up functionality (when debugger exits). */ + bool autoRestart; + + /** Enable/disable PRS as DTI input. */ + bool enablePrsSource; + + /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource + is enabled. */ + TIMER_PRSSEL_TypeDef prsSel; + + /** DTI prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** DTI Rise Time */ + unsigned int riseTime; + + /** DTI Fall Time */ + unsigned int fallTime; + + /** DTI outputs enable bit mask, consisting of one bit per DTI + output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. + This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags + (defined in \_timer.h) OR'ed together. */ + uint32_t outputsEnableMask; + + /** Enable core lockup as a fault source. */ + bool enableFaultSourceCoreLockup; + + /** Enable debugger as a fault source. */ + bool enableFaultSourceDebugger; + + /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ + bool enableFaultSourcePrsSel0; + + /** Select which PRS signal to be PRS fault source 0. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel0; + + /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ + bool enableFaultSourcePrsSel1; + + /** Select which PRS signal to be PRS fault source 1. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel1; + + /** Fault Action */ + TIMER_DtiFaultAction_TypeDef faultAction; +} TIMER_InitDTI_TypeDef; + +/** Default configuration for TIMER DTI initialization structure. */ +#define TIMER_INITDTI_DEFAULT \ + { \ + true, /* Enable the DTI. */ \ + false, /* CC[0|1|2] outputs are active high. */ \ + false, /* CDTI[0|1|2] outputs are not inverted. */ \ + false, /* No auto restart when debugger exits. */ \ + false, /* No PRS source selected. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerPrescale1, /* No prescaling. */ \ + 0, /* No rise time. */ \ + 0, /* No fall time. */ \ + TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ + true, /* Enable core lockup as fault source. */ \ + true, /* Enable debugger as fault source. */ \ + false, /* Disable PRS fault source 0. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + false, /* Disable PRS fault source 1. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerDtiFaultActionInactive, /* No fault action. */ \ + } +#endif /* _TIMER_DTCTRL_MASK */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(TIMER_STATUS_SYNCBUSY) +void TIMER_SyncWait(TIMER_TypeDef * timer); +#endif + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(TIMER4) + || (ref == TIMER4) +#endif +#if defined(TIMER5) + || (ref == TIMER5) +#endif +#if defined(TIMER6) + || (ref == TIMER6) +#endif +#if defined(TIMER7) + || (ref == TIMER7) +#endif +#if defined(TIMER8) + || (ref == TIMER8) +#endif +#if defined(TIMER9) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Check whether the TIMER is valid and supports Dead Timer Insertion (DTI). + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer that supports DTI, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_SupportsDTI(const TIMER_TypeDef *ref) +{ + (void) ref; + + return 0 +#if defined(TIMER0_DTI) +#if (TIMER0_DTI == 1) + || (ref == TIMER0) +#endif +#elif defined(_TIMER_DTCTRL_MASK) + || (ref == TIMER0) +#endif +#if defined(TIMER1_DTI) && (TIMER1_DTI == 1) + || (ref == TIMER1) +#endif +#if defined(TIMER2_DTI) && (TIMER2_DTI == 1) + || (ref == TIMER2) +#endif +#if defined(TIMER3_DTI) && (TIMER3_DTI == 1) + || (ref == TIMER3) +#endif +#if defined(TIMER4_DTI) && (TIMER4_DTI == 1) + || (ref == TIMER4) +#endif +#if defined(TIMER5_DTI) && (TIMER5_DTI == 1) + || (ref == TIMER5) +#endif +#if defined(TIMER6_DTI) && (TIMER6_DTI == 1) + || (ref == TIMER6) +#endif +#if defined(TIMER7_DTI) && (TIMER7_DTI == 1) + || (ref == TIMER7) +#endif +#if defined(TIMER8_DTI) && (TIMER8_DTI == 1) + || (ref == TIMER8) +#endif +#if defined(TIMER9_DTI) && (TIMER9_DTI == 1) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ + (void) ref; + +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ) { + return 0xFFFFFFFFUL; + } +#endif /* defined(WTIMER_PRESENT) */ + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(TIMER_NUM(ref) != -1); + + return (uint32_t)((1ULL << TIMER_CNTWIDTH(TIMER_NUM(ref))) - 1); +#else + return 0xFFFFUL; +#endif /* defined(_SILICON_LABS_32B_SERIES_2) */ +} + +/***************************************************************************//** + * @brief + * Get compare/capture value for the compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICF; + } else { + return timer->CC[ch].OC; + } +#else + return timer->CC[ch].CCV; +#endif +} + +/***************************************************************************//** + * @brief + * Get the buffered compare/capture value for compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current buffered capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICOF; + } else { + return timer->CC[ch].OCB; + } +#else + return timer->CC[ch].CCVB; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value buffer for the compare/capture channel when operating in + * compare or PWM mode. + * + * @details + * The compare value buffer holds the value which will be written to + * TIMERn_CCx_CCV on an update event if the buffer has been updated since + * the last event. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OCB = val; +#else + timer->CC[ch].CCVB = val; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value for compare/capture channel when operating in compare + * or PWM mode. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OC = val; +#else + timer->CC[ch].CCV = val; +#endif +} + +/***************************************************************************//** + * @brief + * Get the TIMER counter value. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * Current TIMER counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) +{ + return timer->CNT; +} + +/***************************************************************************//** + * @brief + * Set the TIMER counter value. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set counter to. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined(TIMER_HAS_SET_CLEAR) + bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; + timer->EN_SET = TIMER_EN_EN; +#endif + timer->CNT = val; +#if defined(TIMER_HAS_SET_CLEAR) + if (!enabled) { + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Start/stop TIMER. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable counting; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + + if (enable) { + timer->CMD = TIMER_CMD_START; + } else { + timer->CMD = TIMER_CMD_STOP; + } +} + +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init); + +#if defined(_TIMER_DTCTRL_MASK) +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); + +/***************************************************************************//** + * @brief + * Enable or disable DTI unit. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable DTI unit; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) +{ +#if defined(TIMER_HAS_SET_CLEAR) + uint32_t timerEn = timer->EN & TIMER_EN_EN; + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + if (enable) { + timer->DTCFG_SET = TIMER_DTCFG_DTEN; + } else { + timer->DTCFG_CLR = TIMER_DTCFG_DTEN; + } + timer->EN_SET = timerEn; +#else + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + if (enable) { + timer->DTCTRL |= TIMER_DTCTRL_DTEN; + } else { + timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Get DTI fault source flags status. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Status of the DTI fault source flags. Returns one or more valid + * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + return timer->DTFAULT; +} + +/***************************************************************************//** + * @brief + * Clear DTI fault source flags. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * DTI fault source(s) to clear. Use one or more valid DTI fault + * source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) + +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTFAULTC = flags; +} +#endif /* _TIMER_DTCTRL_MASK */ + +/***************************************************************************//** + * @brief + * Clear one or more pending TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * Pending TIMER interrupt source(s) to clear. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = flags; +#else + timer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to disable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more TIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * TIMER_IntClear() prior to enabling the interrupt. + + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to enable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending TIMER interrupt flags. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * TIMER interrupt source(s) pending. Returns one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) +{ + return timer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending TIMER interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled TIMER interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn + * register (TIMERx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the TIMER module + * (TIMERx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) +{ + uint32_t ien; + + /* Store TIMER->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = timer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return timer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending TIMER interrupts from SW. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_SET = flags; +#else + timer->IFS = flags; +#endif +} + +#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) +/***************************************************************************//** + * @brief + * Lock some TIMER registers to protect them from being + * modified. + * + * @details + * Refer to the reference manual for TIMER registers that will be locked. + * + * @note + * If locking the TIMER registers, they must be unlocked prior to using any + * TIMER API function that modifies TIMER registers protected by the lock. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; +} +#endif + +void TIMER_Reset(TIMER_TypeDef *timer); + +/***************************************************************************//** + * @brief + * Set the top value buffer for the timer. + * + * @details + * When top value buffer register is updated, value is loaded into + * top value register at the next wrap around. This feature is useful + * in order to update top value safely when timer is running. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOPB = val; +} + +/***************************************************************************//** + * @brief + * Get the top value setting for the timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Current top value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) +{ + return timer->TOP; +} + +/***************************************************************************//** + * @brief + * Set the top value for timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOP = val; +} + +#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) +/***************************************************************************//** + * @brief + * Unlock TIMER to enable writing to locked registers again. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; +} +#endif + +/** @} (end addtogroup timer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ +#endif /* EM_TIMER_H */ diff --git a/Libs/platform/emlib/inc/em_usart.h b/Libs/platform/emlib/inc/em_usart.h new file mode 100644 index 0000000..c4c0305 --- /dev/null +++ b/Libs/platform/emlib/inc/em_usart.h @@ -0,0 +1,1093 @@ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_USART_H +#define EM_USART_H + +#include "em_device.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup usart USART - Synchronous/Asynchronous Serial + * @brief Universal Synchronous/Asynchronous Receiver/Transmitter + * Peripheral API + * @details + * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) + * is a very flexible serial I/O module. It supports full duplex asynchronous UART + * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface + * with ISO7816 Smart-Cards, and IrDA devices. + * + * The USART has a wide selection of operating modes, frame formats, and baud rates. + * All features are supported through the API of this module. + * + * Triple buffering and DMA support makes high data-rates possible with minimal + * CPU intervention. It is possible to transmit and receive large frames while + * the MCU remains in EM1 Sleep. + * + * This module does not support DMA configuration. The UARTDRV and SPIDRV drivers + * provide full support for DMA and more. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @include em_usart_clock_enable.c + * + * To initialize the USART for asynchronous operation (e.g., UART): + * @include em_usart_init_async.c + * + * To initialize the USART for synchronous operation (e.g., SPI): + * @include em_usart_init_sync.c + * + * After pins are assigned for the application/board, enable pins at the + * desired location. Available locations can be obtained from the Pin Definitions + * section in the data sheet. + * @if DOXYDOC_P1_DEVICE + * @include em_usart_route_p1.c + * @note UART hardware flow control is not directly supported in hardware on + * _SILICON_LABS_32B_SERIES_0 parts. + * @endif + * @if DOXYDOC_P2_DEVICE + * @include em_usart_route_p2.c + * @endif + * @note UARTDRV supports all types of UART flow control. Software assisted + * hardware flow control is available for parts without true UART hardware + * flow control. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Databit selection. */ +typedef enum { + usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ + usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ + usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ + usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ + usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ + usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ + usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ + usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ + usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ + usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ + usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ + usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ + usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ +} USART_Databits_TypeDef; + +/** Enable selection. */ +typedef enum { + /** Disable both receiver and transmitter. */ + usartDisable = 0x0, + + /** Enable receiver only, transmitter disabled. */ + usartEnableRx = USART_CMD_RXEN, + + /** Enable transmitter only, receiver disabled. */ + usartEnableTx = USART_CMD_TXEN, + + /** Enable both receiver and transmitter. */ + usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) +} USART_Enable_TypeDef; + +/** Oversampling selection, used for asynchronous operation. */ +typedef enum { + usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ + usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ + usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ + usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ +} USART_OVS_TypeDef; + +/** Parity selection, mainly used for asynchronous operation. */ +typedef enum { + usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ + usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ + usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ +} USART_Parity_TypeDef; + +/** Stop bits selection, used for asynchronous operation. */ +typedef enum { + usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ + usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ + usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ + usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ +} USART_Stopbits_TypeDef; + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, +} USART_HwFlowControl_TypeDef; + +#elif defined(USART_CTRLX_CTSEN) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts +} USART_HwFlowControl_TypeDef; +#endif + +/** Clock polarity/phase mode. */ +typedef enum { + /** Clock idle low, sample on rising edge. */ + usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle low, sample on falling edge. */ + usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, + + /** Clock idle high, sample on falling edge. */ + usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle high, sample on rising edge. */ + usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING +} USART_ClockMode_TypeDef; + +/** Pulse width selection for IrDA mode. */ +typedef enum { + /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ + usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, + + /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ + usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, + + /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ + usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, + + /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ + usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR +} USART_IrDAPw_Typedef; + +/** PRS Channel type */ +typedef uint8_t USART_PRS_Channel_t; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector value. + * New code should use an integer instead. */ +#define usartIrDAPrsCh0 0U +#define usartIrDAPrsCh1 1U +#define usartIrDAPrsCh2 2U +#define usartIrDAPrsCh3 3U +#define usartIrDAPrsCh4 4U +#define usartIrDAPrsCh5 5U +#define usartIrDAPrsCh6 6U +#define usartIrDAPrsCh7 7U +#define usartPrsRxCh0 0U +#define usartPrsRxCh1 1U +#define usartPrsRxCh2 2U +#define usartPrsRxCh3 3U +#define usartPrsRxCh4 4U +#define usartPrsRxCh5 5U +#define usartPrsRxCh6 6U +#define usartPrsRxCh7 7U +#define usartPrsRxCh8 8U +#define usartPrsRxCh9 9U +#define usartPrsRxCh10 10U +#define usartPrsRxCh11 11U +#define usartPrsTriggerCh0 0U +#define usartPrsTriggerCh1 1U +#define usartPrsTriggerCh2 2U +#define usartPrsTriggerCh3 3U +#define usartPrsTriggerCh4 4U +#define usartPrsTriggerCh5 5U +#define usartPrsTriggerCh6 6U +#define usartPrsTriggerCh7 7U +/** @endcond */ + +#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ + usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ + usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ + usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ + usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ + usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ + usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ + usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ + usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ +} USART_I2sJustify_TypeDef; + +#elif defined(_USART_I2SCTRL_MASK) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ + usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ + usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ + usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ + usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ + usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ + usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ + usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ + usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ +} USART_I2sJustify_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Asynchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX is enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Oversampling used. */ + USART_OVS_TypeDef oversampling; + + /** Number of data bits in frame. Notice that UART modules only support 8 or + * 9 data bits. */ + USART_Databits_TypeDef databits; + + /** Parity mode to use. */ + USART_Parity_TypeDef parity; + + /** Number of stop bits to use. */ + USART_Stopbits_TypeDef stopbits; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ + bool mvdis; + + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + + /** Auto CS enabling. */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if (_SILICON_LABS_32B_SERIES > 0) + /** Auto CS hold time in baud cycles. */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles. */ + uint8_t autoCsSetup; + + /** Hardware flow control mode. */ + USART_HwFlowControl_TypeDef hwFlowControl; +#endif +} USART_InitAsync_TypeDef; + +/** USART PRS trigger enable. */ +typedef struct { +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX. */ + bool autoTxTriggerEnable; +#endif + /** Trigger receive via PRS channel. */ + bool rxTriggerEnable; + /** Trigger transmit via PRS channel. */ + bool txTriggerEnable; + /** PRS channel to be used to trigger auto transmission. */ + USART_PRS_Channel_t prsTriggerChannel; +} USART_PrsTriggerInit_TypeDef; + +/** Default configuration for USART asynchronous initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Async struct for the EFM32G device */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Async struct for Series 0 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Async struct for Series 1 and Series 2 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0, /* Auto CS Setup cycles. */ \ + usartHwFlowControlNone /* No HW flow control. */ \ + } +#endif + +/** Default configuration for USART PRS triggering structure. */ +#if defined(USART_TRIGCTRL_AUTOTXTEN) +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable autoTX triggering. */ \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#else +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#endif + +/** Synchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Number of data bits in frame. */ + USART_Databits_TypeDef databits; + + /** Select if to operate in master or slave mode. */ + bool master; + + /** Select if to send most or least significant bit first. */ + bool msbf; + + /** Clock polarity/phase mode. */ + USART_ClockMode_TypeDef clockMode; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX mode. Transmits as long as RX is not full. + * Generates underflows if TX is empty. */ + bool autoTx; +#endif + + /** Auto CS enabling */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if defined(_USART_TIMING_CSHOLD_MASK) + /** Auto CS hold time in baud cycles */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles */ + uint8_t autoCsSetup; +#endif +} USART_InitSync_TypeDef; + +/** Default configuration for USART sync initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 databits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0 /* Auto CS Setup cycles. */ \ + } +#endif + +/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ +typedef struct { + /** General Asynchronous initialization structure. */ + USART_InitAsync_TypeDef async; + + /** Set to invert Rx signal before IrDA demodulator. */ + bool irRxInv; + + /** Set to enable filter on IrDA demodulator. */ + bool irFilt; + + /** Configure the pulse width generated by the IrDA modulator as a fraction + * of the configured USART bit period. */ + USART_IrDAPw_Typedef irPw; + +#if defined(USART_IRCTRL_IRPRSEN) + /** Enable the PRS channel selected by irPrsSel as input to IrDA module + * instead of TX. */ + bool irPrsEn; + + /** PRS can be used as input to the pulse modulator instead of TX. + * This value selects the channel to use. */ + USART_PRS_Channel_t irPrsSel; +#endif +} USART_InitIrDA_TypeDef; + +/** Default configuration for IrDA mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART IrDA struct for the EFM32G device */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART IrDA struct for Series 0 devices */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART IrDA struct for Series 1 and Series 2 devices */ +#if defined(USART_IRCTRL_IRPRSEN) +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#else +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE /* Pulse width is set to ONE. */ \ + } +#endif +#endif + +#if defined(_USART_I2SCTRL_MASK) +/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ +typedef struct { + /** General Synchronous initialization structure. */ + USART_InitSync_TypeDef sync; + + /** I2S mode. */ + USART_I2sFormat_TypeDef format; + + /** Delay on I2S data. Set to add a one-cycle delay between a transition + * on the word-clock and the start of the I2S word. + * Should be set for standard I2S format. */ + bool delay; + + /** Separate DMA Request For Left/Right Data. */ + bool dmaSplit; + + /** Justification of I2S data within the frame. */ + USART_I2sJustify_TypeDef justify; + + /** Stereo or Mono, set to true for mono. */ + bool mono; +} USART_InitI2s_TypeDef; + +/** Default configuration for I2S mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnableTx, /* Enable TX when init completed. */ \ + 0, /* Use current configured reference clock for configuring baudrate. */ \ + 1000000, /* Baudrate 1M bits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Operate as I2S master. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Don't enable USARTRx via PRS. */ \ + usartPrsRxCh0, /* PRS channel selection (dummy). */ \ + false, /* Disable AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0 /* Auto CS Setup cycles */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#endif +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateGet(USART_TypeDef *usart); +void USART_BaudrateSyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate); +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); + +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); + +#if defined(_USART_I2SCTRL_MASK) +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); +#endif +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * Pending USART/UART interrupt source(s) to clear. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_CLR = flags; +#else + usart->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to disable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more USART interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * USART_IntClear() prior to enabling the interrupt. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to enable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending USART interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * USART/UART interrupt source(s) pending. Returns one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) +{ + return usart->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending USART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled USART interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn + * register (USARTx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the USART module + * (USARTx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) +{ + uint32_t ien; + + /* Store USARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = usart->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return usart->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending USART interrupts from SW. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_SET = flags; +#else + usart->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get USART STATUS register. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * STATUS register value. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) +{ + return usart->STATUS; +} + +void USART_Reset(USART_TypeDef *usart); +uint8_t USART_Rx(USART_TypeDef *usart); +uint16_t USART_RxDouble(USART_TypeDef *usart); +uint32_t USART_RxDoubleExt(USART_TypeDef *usart); +uint16_t USART_RxExt(USART_TypeDef *usart); + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is used to quickly receive one 4-8 bits frame by reading the + * RXDATA register directly, without checking the STATUS register for the + * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, + * i.e., waiting is superfluous, in order to quickly read the received data. + * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. + * + * @note + * Because this function does not check whether the RXDATA register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a + * better choice if the validity of the RXDATA register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) +{ + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames, or one 10-16 bit frame. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-8 + * bit frames by reading the RXDOUBLE register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() + * for reception of two 9 bit frames. + * + * @note + * Because this function does not check whether the RXDOUBLE register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is + * normally a better choice if the validity of the RXDOUBLE register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-9 + * bit frames by reading the RXDOUBLEX register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * + * @note + * Because this function does not check whether the RXDOUBLEX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is + * normally a better choice if the validity of the RXDOUBLEX register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) +{ + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is used to quickly receive one 4-9 bit frame, (or part of + * 10-16 bit frame) with extended information by reading the RXDATAX register + * directly, without checking the STATUS register for the RXDATAV flag. This + * can be useful from the RXDATAV interrupt handler, i.e., waiting is + * superfluous, in order to quickly read the received data. + * + * @note + * Because this function does not check whether the RXDATAX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally + * a better choice if the validity of the RXDATAX register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDATAX; +} + +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); +void USART_Tx(USART_TypeDef *usart, uint8_t data); +void USART_TxDouble(USART_TypeDef *usart, uint16_t data); +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); +void USART_TxExt(USART_TypeDef *usart, uint16_t data); + +/** @} (end addtogroup usart) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ +#endif /* EM_USART_H */ diff --git a/Libs/platform/emlib/inc/em_vdac.h b/Libs/platform/emlib/inc/em_vdac.h new file mode 100644 index 0000000..aa2be07 --- /dev/null +++ b/Libs/platform/emlib/inc/em_vdac.h @@ -0,0 +1,773 @@ +/***************************************************************************//** + * @file + * @brief Digital to Analog Converter (VDAC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_VDAC_H +#define EM_VDAC_H + +#include "em_device.h" + +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) + +#include "sl_assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup vdac VDAC - Voltage DAC + * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API + * + * @details + * This module contains functions to control the VDAC peripheral of Silicon + * Labs' 32-bit MCUs and SoCs. VDAC converts digital values to analog + * signals at up to 500 ksps with 12-bit accuracy. VDAC is designed for + * low energy consumption, but can also provide very good performance. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_VDAC0, true);@endcode + * + * Initialize the VDAC with default settings and modify selected fields: + * @code + VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; + + // Set prescaler to get 1 MHz VDAC clock frequency. + vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); // function call for series 0/1 + VDAC_Init(VDAC0, &vdacInit); + + vdacChInit.enable = true; + VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode + * + * Perform a conversion: + * @code + VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode + * + * @note The output stage of a VDAC channel consists of an on-chip operational + * amplifier (OPAMP) in the OPAMP module. This OPAMP is highly configurable; + * and to exploit the VDAC functionality fully, configure the OPAMP using + * the OPAMP API. Using the OPAMP API also loads OPAMP calibration values. + * The default (reset) settings of OPAMP is sufficient for many applications. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC register block pointer reference for assert statements.*/ + +#if VDAC_COUNT == 1 +#define VDAC_REF_VALID(ref) ((ref) == VDAC0) +#elif VDAC_COUNT == 2 +#define VDAC_REF_VALID(ref) (((ref) == VDAC0) || ((ref) == VDAC1)) +#else +#error "Undefined number of VDACs." +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if !defined(_SILICON_LABS_32B_SERIES_2) +/** Channel refresh period. */ +typedef enum { + vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum { + vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V band gap reference. */ + vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V band gap reference. */ + vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V band gap reference. */ + vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V band gap reference. */ + vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Peripheral Reflex System signal used to trigger VDAC channel conversion. */ +typedef enum { + vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS ch 0 triggers conversion. */ + vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS ch 1 triggers conversion. */ + vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS ch 2 triggers conversion. */ + vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS ch 3 triggers conversion. */ + vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS ch 4 triggers conversion. */ + vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS ch 5 triggers conversion. */ + vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS ch 6 triggers conversion. */ + vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS ch 7 triggers conversion. */ +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH8) + vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS ch 8 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH9) + vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS ch 9 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH10) + vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH11) + vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ +#endif +} VDAC_PrsSel_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum { + vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ + vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ + vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ + vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ + vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +} VDAC_TrigMode_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC initialization structure, common for both channels. */ +typedef struct { + /** Selects between main and alternate output path calibration values. */ + bool mainCalibration; + + /** Selects clock from asynchronous or synchronous (with respect to + peripheral clock) source. */ + bool asyncClockMode; + + /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Enable/disable output enable control by CH1 PRS signal. */ + bool outEnablePRS; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; +} VDAC_Init_TypeDef; + +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + true, /* Use main output path calibration values. */ \ + false, /* Use synchronous clock mode. */ \ + false, /* Turn off between sample off conversions.*/ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25Ln, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* VDAC output enable always on. */ \ + false, /* Disable sine mode. */ \ + false /* Single ended mode. */ \ + } + +/** VDAC channel initialization structure. */ +typedef struct { + /** Enable channel. */ + bool enable; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p trigMode + * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ + VDAC_PrsSel_TypeDef prsSel; + + /** Treat the PRS signal asynchronously. */ + bool prsAsync; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continuous.*/ + bool sampleOffMode; +} VDAC_InitChannel_TypeDef; + +/** Default configuration for VDAC channel initialization structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ + { \ + false, /* Leave channel disabled when initialization is done. */ \ + vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ + false, /* Treat PRS channel as a synchronous signal. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + false, /* Channel conversion set to continuous. */ \ + } +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/** Channel refresh period. */ +typedef enum { + vdacRefresh2 = _VDAC_CFG_REFRESHPERIOD_CYCLES2, /**< Refresh every 2 clock cycles. */ + vdacRefresh4 = _VDAC_CFG_REFRESHPERIOD_CYCLES4, /**< Refresh every 4 clock cycles. */ + vdacRefresh8 = _VDAC_CFG_REFRESHPERIOD_CYCLES8, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CFG_REFRESHPERIOD_CYCLES16, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CFG_REFRESHPERIOD_CYCLES32, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CFG_REFRESHPERIOD_CYCLES64, /**< Refresh every 64 clock cycles. */ + vdacRefresh128 = _VDAC_CFG_REFRESHPERIOD_CYCLES128, /**< Refresh every 128 clock cycles. */ + vdacRefresh256 = _VDAC_CFG_REFRESHPERIOD_CYCLES256, /**< Refresh every 256 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Timer overflow period. */ +typedef enum { + vdacCycles2 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2, /**< Overflows every 2 clock cycles. */ + vdacCycles4 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4, /**< Overflows every 4 clock cycles. */ + vdacCycles8 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8, /**< Overflows every 8 clock cycles. */ + vdacCycles16 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16, /**< Overflows every 16 clock cycles. */ + vdacCycles32 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32, /**< Overflows every 32 clock cycles. */ + vdacCycles64 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 /**< Overflows every 64 clock cycles. */ +} VDAC_TimerOverflow_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum { + vdacRef1V25 = _VDAC_CFG_REFRSEL_V125, /**< Internal 1.25 V band gap reference. */ + vdacRef2V5 = _VDAC_CFG_REFRSEL_V25, /**< Internal 2.5 V band gap reference. */ + vdacRefAvdd = _VDAC_CFG_REFRSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CFG_REFRSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Refresh source for VDAC. */ +typedef enum { + vdacRefreshSrcNone = _VDAC_CH0CFG_REFRESHSOURCE_NONE, /**< No refresh source. */ + vdacRefreshSrcRefreshTimer = _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER,/**< Refresh triggered by refresh timer overflow. */ + vdacRefreshSrcSyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS, /**< Refresh triggered by sync PRS. */ + vdacRefreshSrcAsyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS, /**< Refresh triggered by async PRS. */ +} VDAC_RefreshSource_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum { + vdacTrigModeNone = _VDAC_CH0CFG_TRIGMODE_NONE, /**< No conversion trigger source selected. */ + vdacTrigModeSw = _VDAC_CH0CFG_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModeSyncPrs = _VDAC_CH0CFG_TRIGMODE_SYNCPRS, /**< Channel is triggered by Sync PRS input. */ +#if defined(LESENSE_PRESENT) && defined(_VDAC_CH0CFG_TRIGMODE_LESENSE) + vdacTrigModeLesense = _VDAC_CH0CFG_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +#endif + vdacTrigModeInternalTimer = _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER, /**< Channel is triggered by Internal Timer. */ + vdacTrigModeAsyncPrs = _VDAC_CH0CFG_TRIGMODE_ASYNCPRS /**< Channel is triggered by Async PRS input. */ +} VDAC_TrigMode_TypeDef; + +/** Channel power mode. */ +typedef enum { + vdacPowerModeHighPower = _VDAC_CH0CFG_POWERMODE_HIGHPOWER, /**< High power buffer mode. */ + vdacPowerModeLowPower = _VDAC_CH0CFG_POWERMODE_LOWPOWER /**< Low power buffer mode. */ +} VDAC_PowerMode_TypeDef; + +/** VDAC channel Abus port selection. */ +typedef enum { + /** No GPIO selected. */ + vdacChPortNone = _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE, + /** Port A selected. */ + vdacChPortA = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA, + /** Port B selected. */ + vdacChPortB = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB, + /** Port C selected. */ + vdacChPortC = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC, + /** Port D selected. */ + vdacChPortD = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD, +} VDAC_ChPortSel_t; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC initialization structure, common for both channels. */ +typedef struct { + /** Number of prescaled CLK_DAC + 1 for the vdac to warmup. */ + uint32_t warmupTime; + + /** Halt during debug. */ + bool dbgHalt; + + /** Always allow clk_dac. */ + bool onDemandClk; + + /** DMA Wakeup. */ + bool dmaWakeUp; + + /** Bias keep warm enable. */ + bool biasKeepWarm; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Internal timer overflow period. */ + VDAC_TimerOverflow_TypeDef timerOverflow; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Sine reset mode. */ + bool sineReset; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; + +#if defined(VDAC_CFG_SINEMODEPRS) + /** PRS controlled sinemode enable. */ + bool sineModePrsEnable; +#endif +#if defined(VDAC_CFG_OUTENPRS) + /** PRS controlled channel output enable. */ + bool prsOutEnable; +#endif +} VDAC_Init_TypeDef; + +#if defined(VDAC_CFG_SINEMODEPRS) +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + false, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh2, /* Refresh every 2th cycle. */ \ + vdacCycles2, /* Internal overflow every 2th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + false, /* Disable sine mode. */ \ + false, /* Differential mode. */ \ + false, /* PRS controlled sinemode. */ \ + false, /* PRS controlled output enable. */ \ + } +#else +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + false, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh2, /* Refresh every 2th cycle. */ \ + vdacCycles2, /* Internal overflow every 2th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + false, /* Disable sine mode. */ \ + false, /* Differential mode. */ \ + } +#endif + +#if defined(VDAC_CFG_SINEMODEPRS) +/** Sine mode configuration for VDAC initialization structure. */ +#define VDAC_INIT_SINE_GENERATION_MODE \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + true, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + vdacCycles2, /* Internal overflow every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + true, /* Enable sine mode. */ \ + false, /* Differential mode. */ \ + false, /* PRS controlled sinemode. */ \ + false, /* PRS controlled output enable. */ \ + } +#else +/** Sine mode configuration for VDAC initialization structure. */ +#define VDAC_INIT_SINE_GENERATION_MODE \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + true, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + vdacCycles2, /* Internal overflow every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + true, /* Enable sine mode. */ \ + false, /* Differential mode. */ \ + } +#endif + +/** VDAC channel initialization structure. */ +typedef struct { + /** Enable channel. */ + bool enable; + + /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Select high capacitance load mode in conjunction with high power. */ + bool highCapLoadEnable; + + /** Channel x FIFO Low threshold data valid level. */ + uint32_t fifoLowDataThreshold; + + /** Channel refresh source. */ + VDAC_RefreshSource_TypeDef chRefreshSource; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Channel power mode. */ + VDAC_PowerMode_TypeDef powerMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continuous.*/ + bool sampleOffMode; + + /** Vdac channel output pin. */ + uint32_t pin; + + /** Vdac channel output port. */ + VDAC_ChPortSel_t port; + + /** Short High power and low power output. */ + bool shortOutput; + + /** Alternative output enable. */ + bool auxOutEnable; + + /** Main output enable. */ + bool mainOutEnable; + + /** Channel output hold time. */ + uint32_t holdOutTime; +} VDAC_InitChannel_TypeDef; + +/** Default configuration for VDAC channel initialization structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ + { \ + false, /* Leave channel disabled when initialization is done. */ \ + false, /* Turn off between sample off conversions.*/ \ + true, /* Enable High cap mode. */ \ + 0, /* FIFO data low watermark at 0. */ \ + vdacRefreshSrcNone, /* Channel refresh source. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + vdacPowerModeHighPower, /* High power mode enabled. */ \ + false, /* Continuous conversion mode. */ \ + 0, /* ABUS pin selected. */ \ + vdacChPortNone, /* No Analog bus port selected. */ \ + false, /* Output not shorted */ \ + false, /* Alternative output disabled. */ \ + true, /* Main output enabled. */ \ + 0, /* Hold out time. Previously called settle time */ \ + } + +#endif +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value); +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch); + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start/stop Sinemode. + * + * @details + * This function sends the sine mode start/stop signal to the DAC. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] start + * True to start the Sine mode, false to stop it. + ******************************************************************************/ +__STATIC_INLINE void VDAC_SineModeStart(VDAC_TypeDef *vdac, bool start) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + + while (0UL != (vdac->STATUS & VDAC_STATUS_SYNCBUSY)) { + } + + if (start) { + vdac->CMD = VDAC_CMD_SINEMODESTART; + while (0UL == (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { + } + } else { + vdac->CMD = VDAC_CMD_SINEMODESTOP; + while (0UL != (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { + } + } +} +#endif + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 0 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 0 by writing @p value + * to the CH0DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 0 output register CH0DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(value <= _VDAC_CH0DATA_MASK); + vdac->CH0DATA = value; +#elif defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(value <= _VDAC_CH0F_MASK); + vdac->CH0F = value; +#endif +} + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 1 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 1 by writing @p value + * to the CH1DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 1 output register CH1DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(value <= _VDAC_CH1DATA_MASK); + vdac->CH1DATA = value; +#elif defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(value <= _VDAC_CH1F_MASK); + vdac->CH1F = value; +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IF_CLR = flags; +#else + vdac->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IEN_CLR = flags; +#else + vdac->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more VDAC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * VDAC_IntClear() prior to enabling the interrupt. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to enable. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IEN_SET = flags; +#else + vdac->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending VDAC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * VDAC interrupt sources pending. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) +{ + return vdac->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending VDAC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled VDAC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn + * register (VDACx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the VDAC module + * (VDACx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) +{ + uint32_t ien = vdac->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return vdac->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending VDAC interrupts from SW. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IF_SET = flags; +#else + vdac->IFS = flags; +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Get the VDAC Status register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * Current STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_GetStatus(VDAC_TypeDef *vdac) +{ + return vdac->STATUS; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); +#else +uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq); +#endif + +void VDAC_Reset(VDAC_TypeDef *vdac); + +/** @} (end addtogroup vdac) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +#endif /* EM_VDAC_H */ diff --git a/Libs/platform/emlib/inc/em_version.h b/Libs/platform/emlib/inc/em_version.h new file mode 100644 index 0000000..f44110b --- /dev/null +++ b/Libs/platform/emlib/inc/em_version.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief CMSIS and EMLIB versions + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_VERSION_H +#define EM_VERSION_H + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup version VERSION - Version Defines + * @brief Version API + * @details + * Macros specifying the EMLIB and CMSIS version. + * @{ + ******************************************************************************/ + +/* *INDENT-OFF* */ +/** Version number of targeted CMSIS package. */ +#define _CMSIS_VERSION 5.8.0 +/* *INDENT-ON* */ + +/** Major version of CMSIS. */ +#define _CMSIS_VERSION_MAJOR 5 + +/** Minor version of CMSIS. */ +#define _CMSIS_VERSION_MINOR 8 + +/** Patch revision of CMSIS. */ +#define _CMSIS_VERSION_PATCH 0 + +/** @} (end addtogroup version) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_VERSION_H */ diff --git a/Libs/platform/emlib/inc/em_wdog.h b/Libs/platform/emlib/inc/em_wdog.h new file mode 100644 index 0000000..f77281a --- /dev/null +++ b/Libs/platform/emlib/inc/em_wdog.h @@ -0,0 +1,455 @@ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_WDOG_H +#define EM_WDOG_H + +#include "em_device.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup wdog + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Default WDOG instance for deprecated functions. */ +#if !defined(DEFAULT_WDOG) +#if defined(WDOG0) +#define DEFAULT_WDOG WDOG0 +#elif defined(WDOG) +#define DEFAULT_WDOG WDOG +#endif +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Watchdog clock selection. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) +typedef enum { + wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */ + wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */ + wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */ +} WDOG_ClkSel_TypeDef; +#endif + +/** Watchdog period selection. */ +typedef enum { + wdogPeriod_9 = 0x0, /**< 9 clock periods */ + wdogPeriod_17 = 0x1, /**< 17 clock periods */ + wdogPeriod_33 = 0x2, /**< 33 clock periods */ + wdogPeriod_65 = 0x3, /**< 65 clock periods */ + wdogPeriod_129 = 0x4, /**< 129 clock periods */ + wdogPeriod_257 = 0x5, /**< 257 clock periods */ + wdogPeriod_513 = 0x6, /**< 513 clock periods */ + wdogPeriod_1k = 0x7, /**< 1025 clock periods */ + wdogPeriod_2k = 0x8, /**< 2049 clock periods */ + wdogPeriod_4k = 0x9, /**< 4097 clock periods */ + wdogPeriod_8k = 0xA, /**< 8193 clock periods */ + wdogPeriod_16k = 0xB, /**< 16385 clock periods */ + wdogPeriod_32k = 0xC, /**< 32769 clock periods */ + wdogPeriod_64k = 0xD, /**< 65537 clock periods */ + wdogPeriod_128k = 0xE, /**< 131073 clock periods */ + wdogPeriod_256k = 0xF /**< 262145 clock periods */ +} WDOG_PeriodSel_TypeDef; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) +/** Select Watchdog warning timeout period as percentage of timeout. */ +typedef enum { + wdogWarnDisable = 0, /**< Watchdog warning period is disabled. */ + wdogWarnTime25pct = 1, /**< Watchdog warning period is 25% of the timeout. */ + wdogWarnTime50pct = 2, /**< Watchdog warning period is 50% of the timeout. */ + wdogWarnTime75pct = 3, /**< Watchdog warning period is 75% of the timeout. */ +} WDOG_WarnSel_TypeDef; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) +/** Select Watchdog illegal window limit. */ +typedef enum { + wdogIllegalWindowDisable = 0, /**< Watchdog illegal window disabled. */ + wdogIllegalWindowTime12_5pct = 1, /**< Window timeout is 12.5% of the timeout. */ + wdogIllegalWindowTime25_0pct = 2, /**< Window timeout is 25% of the timeout. */ + wdogIllegalWindowTime37_5pct = 3, /**< Window timeout is 37.5% of the timeout. */ + wdogIllegalWindowTime50_0pct = 4, /**< Window timeout is 50% of the timeout. */ + wdogIllegalWindowTime62_5pct = 5, /**< Window timeout is 62.5% of the timeout. */ + wdogIllegalWindowTime75_0pct = 6, /**< Window timeout is 75% of the timeout. */ + wdogIllegalWindowTime87_5pct = 7, /**< Window timeout is 87.5% of the timeout. */ +} WDOG_WinSel_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Watchdog initialization structure. */ +typedef struct { + /** Enable Watchdog when initialization completed. */ + bool enable; + + /** Counter keeps running during debug halt. */ + bool debugRun; + +#if defined(_WDOG_CTRL_CLRSRC_MASK) \ + || defined(_WDOG_CFG_CLRSRC_MASK) + /** Select WDOG clear source: + * False: Write to the clear bit will clear the WDOG counter + * True: Rising edge on the PRS Source 0 will clear the WDOG counter + * */ + bool clrSrc; +#endif + +#if defined(_WDOG_CFG_EM1RUN_MASK) + /** Counter keeps running when in EM1. Available for series2. */ + bool em1Run; +#endif + + /** Counter keeps running when in EM2. */ + bool em2Run; + + /** Counter keeps running when in EM3. */ + bool em3Run; + + /** Block EMU from entering EM4. */ + bool em4Block; + +#if defined(_WDOG_CFG_MASK) + /** When set, a PRS Source 0 missing event will trigger a WDOG reset. */ + bool prs0MissRstEn; + + /** When set, a PRS Source 1 missing event will trigger a WDOG reset. */ + bool prs1MissRstEn; +#endif + + /** Block SW from disabling LFRCO/LFXO oscillators. */ +#if defined(_WDOG_CTRL_SWOSCBLOCK_MASK) + bool swoscBlock; +#endif + + /** Block SW from modifying the configuration (a reset is needed to reconfigure). */ + bool lock; + + /** Clock source to use for Watchdog. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) + WDOG_ClkSel_TypeDef clkSel; +#endif + + /** Watchdog timeout period. */ + WDOG_PeriodSel_TypeDef perSel; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) + /** Select warning time as % of the Watchdog timeout */ + WDOG_WarnSel_TypeDef warnSel; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) + /** Select illegal window time as % of the Watchdog timeout */ + WDOG_WinSel_TypeDef winSel; +#endif + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + || defined(_WDOG_CFG_WDOGRSTDIS_MASK) + /** Disable Watchdog reset output if true */ + bool resetDisable; +#endif +} WDOG_Init_TypeDef; + +/** Suggested default configuration for WDOG initialization structure. */ +#if defined(_WDOG_CFG_MASK) && defined(_WDOG_CFG_EM1RUN_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM1. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CFG_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CTRL_WARNSEL_MASK) \ + && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + && defined(_WDOG_CTRL_WINSEL_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHZ WDOG oscillator. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#else +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHz WDOG oscillator. */ \ + wdogPeriod_256k /* Set longest possible timeout period. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable); +void WDOGn_Feed(WDOG_TypeDef *wdog); +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init); +void WDOGn_Lock(WDOG_TypeDef *wdog); +void WDOGn_SyncWait(WDOG_TypeDef *wdog); +void WDOGn_Unlock(WDOG_TypeDef *wdog); + +#if defined(_WDOG_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntClear(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_CLR = flags; +#else + wdog->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntDisable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_CLR = flags; +#else + wdog->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more WDOG interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * WDOG_IntClear() prior to enabling the interrupt. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntEnable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_SET = flags; +#else + wdog->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending WDOG interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending WDOG interrupt sources. Returns a set of interrupt flags OR-ed + * together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGet(WDOG_TypeDef *wdog) +{ + return wdog->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending WDOG interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending and enabled WDOG interrupt sources. Returns a set of interrupt + * flags OR-ed together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGetEnabled(WDOG_TypeDef *wdog) +{ + uint32_t tmp; + + tmp = wdog->IEN; + + /* Bitwise AND of pending and enabled interrupt flags. */ + return wdog->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending WDOG interrupts from SW. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to set to pending. Use a set of interrupt flags + * (WDOG_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_SET = flags; +#else + wdog->IFS = flags; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get enabled status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is enabled. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsEnabled(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_EN_MASK) + return (wdog->EN & _WDOG_EN_EN_MASK) == WDOG_EN_EN; +#else + return (wdog->CTRL & _WDOG_CTRL_EN_MASK) == WDOG_CTRL_EN; +#endif +} + +/***************************************************************************//** + * @brief + * Get locked status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is locked. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsLocked(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_STATUS_MASK) + return (wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED; +#else + return (wdog->CTRL & _WDOG_CTRL_LOCK_MASK) == WDOG_CTRL_LOCK; +#endif +} + +/** @} (end addtogroup wdog) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ +#endif /* EM_WDOG_H */ diff --git a/Libs/platform/emlib/inc/sli_em_cmu.h b/Libs/platform/emlib/inc/sli_em_cmu.h new file mode 100644 index 0000000..0905384 --- /dev/null +++ b/Libs/platform/emlib/inc/sli_em_cmu.h @@ -0,0 +1,1902 @@ +/***************************************************************************//** + * @file + * @brief Clock Management Unit Private API definition. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_EM_CMU_H +#define SLI_EM_CMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void); + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(bool optimize_divider); + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void); + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void); + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void); + +#define CMU_SYSCLK_SELECT_HFRCODPLL \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ + sli_em_cmu_SYSCLKInitPostClockSelect(true); \ + } while (0) + +#define CMU_SYSCLK_SELECT_HFXO \ + do { \ + sli_em_cmu_HFXOSetForceEnable(); \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(true); \ + if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ + } \ + } while (0) + +#define CMU_SYSCLK_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ + sli_em_cmu_SYSCLKInitPostClockSelect(true); \ + } while (0) + +#define CMU_SYSCLK_SELECT_FSRCO \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(true); \ + } while (0) + +#if defined(RFFPLL_PRESENT) + +#define CMU_SYSCLK_SELECT_RFFPLLSYS \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ + sli_em_cmu_SYSCLKInitPostClockSelect(true); \ + } while (0) + +#endif /* RFFPLL_PRESENT */ + +#if defined(IADC_PRESENT) +#define CMU_IADCCLK_SELECT_EM01GRPACLK \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK + +#if defined(HFRCOEM23_PRESENT) +#define CMU_IADCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_IADCCLK_SELECT_FSRCO \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO +#endif /* IADC_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* KEYSCAN_PRESENT*/ + +#if defined(HFRCOEM23_PRESENT) +#define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* KEYSCAN_PRESENT*/ +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPACLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ + +#define CMU_SYSTICK_SELECT_EM23GRPACLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENSet(); \ + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK + +#define CMU_SYSTICK_SELECT_HCLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENClear(); \ + SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_EM23GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#endif /* LESENSE_PRESENT */ + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM23GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#endif /* LESENSE_PRESENT */ +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM23GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EM4GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM4GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM4GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO + +#define CMU_EM4GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO + +#define CMU_EM4GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL + +#define CMU_EM01GRPBCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO + +#define CMU_EM01GRPBCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO + +#define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 + +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT + +#define CMU_EM01GRPBCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT + +#define CMU_EM01GRPBCLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ + +#define CMU_WDOG0_SELECT_LFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG0_SELECT_PLFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG0_SELECT_LFXO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO + +#define CMU_WDOG0_SELECT_ULFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO + +#define CMU_WDOG0_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 + +#define CMU_WDOG0_SELECT_DISABLED \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +#define CMU_WDOG1_SELECT_LFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG1_SELECT_PLFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG1_SELECT_LFXO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO + +#define CMU_WDOG1_SELECT_ULFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO + +#define CMU_WDOG1_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 + +#define CMU_WDOG1_SELECT_DISABLED \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED +#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ + +#define CMU_DPLLREFCLK_SELECT_HFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_LFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_CLKIN0 \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_DISABLED \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) +#define CMU_TRACECLK_RESTORE_TRACE_PRE() \ + bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ + if (restoreTrace) { \ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#define CMU_TRACECLK_RESTORE_TRACE_POST() \ + if (restoreTrace) { \ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#else +#define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) +#define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define CMU_TRACECLK_SELECT_HCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + #define CMU_TRACECLK_SELECT_SYSCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#define CMU_TRACECLK_SELECT_HFRCODPLLRT \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_TRACECLK_SELECT_HFRCOEM23 \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +#define CMU_EUART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK + +#define CMU_EUART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK + +#define CMU_EUART0_SELECT_DISABLED \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED +#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ + +#if defined(EUSART_PRESENT) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) +#define CMU_EUSART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) +#define CMU_EUSART0_SELECT_EM01GRPCCLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) +#define CMU_EUSART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) +#define CMU_EUSART0_SELECT_FSRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_EUSART0_SELECT_HFRCOEM23 \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) +#define CMU_EUSART0_SELECT_LFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EUSART0_SELECT_PLFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) +#define CMU_EUSART0_SELECT_LFXO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) +#define CMU_EUSART0_SELECT_DISABLED \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ +#endif /* EUSART_PRESENT */ + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ + +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif + +#define CMU_EM01GRPCCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#define CMU_EM01GRPCCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPCCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ +#endif /* _CMU_EM01GRPCCLKCTRL_MASK */ + +#if defined (RTCC_PRESENT) +#define CMU_RTCC_SELECT_LFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_RTCC_SELECT_PLFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_RTCC_SELECT_LFXO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO + +#define CMU_RTCC_SELECT_ULFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO + +#endif /* RTCC_PRESENT */ + +#if defined(SYSRTC_PRESENT) +#define CMU_SYSRTC_SELECT_LFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_SYSRTC_SELECT_PLFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_SYSRTC_SELECT_LFXO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO + +#define CMU_SYSRTC_SELECT_ULFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO + +#define CMU_SYSRTC_SELECT_DISABLED \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED +#endif /* SYSRTC_PRESENT */ + +#if defined(LCD_PRESENT) +#define CMU_LCD_SELECT_LFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_LCD_SELECT_PLFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_LCD_SELECT_LFXO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO + +#define CMU_LCD_SELECT_ULFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO +#endif /* LCD_PRESENT */ + +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_SELECT_FSRCO \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO + +#define CMU_VDAC0_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 + +#define CMU_VDAC0_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK + +#define CMU_VDAC0_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK + +#if (VDAC_COUNT > 1) +#define CMU_VDAC1_SELECT_FSRCO \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO + +#define CMU_VDAC1_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 + +#define CMU_VDAC1_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK + +#define CMU_VDAC1_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK +#endif /* VDAC_COUNT > 1 */ +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +#define CMU_PCNT0_SELECT_EM23GRPACLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK + +#define CMU_PCNT0_SELECT_PCNTEXTCLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK +#endif /* PCNT_PRESENT */ + +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHFCLK_SELECT_FSRCO \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) +#endif /* LESENSE_PRESENT */ + +#if defined(USB_PRESENT) +#define CMU_USB_SELECT_USBPLL0 \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ + } while (0) + +#define CMU_USB_SELECT_LFXO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_USB_SELECT_LFRCO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) +#endif /* USB_PRESENT */ + +#elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @param[in]osc + * Reference to a low-frequency oscillator. One of the following values is valid: + * - cmuOsc_LFXO + * - cmuOsc_LFRCO + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void); + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void); +#endif + +#define CMU_HF_SELECT_LFXO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ + } while (0) + +#define CMU_HF_SELECT_LFRCO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ + } while (0) + +#define CMU_HF_SELECT_HFXO \ + do { \ + sli_em_cmu_HFClockSelectHFXO(); \ + } while (0) + +#define CMU_HF_SELECT_HFRCO \ + do { \ + sli_em_cmu_HFClockSelectHFRCO(); \ + } while (0) + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +#define CMU_HF_SELECT_USHFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +#define CMU_HF_SELECT_HFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +#define CMU_HF_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_HFClockSelectCLKIN0(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +#define CMU_HF_SELECT_USHFRCO \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCO(); \ + } while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ + } while (0) + +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFA_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigHFClock(); \ + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ + } while (0) + +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFB_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#if defined(_CMU_LFCCLKSEL_MASK) +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ + } while (0) + +#define CMU_LFC_SELECT_ULFRCO \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ + } while (0) + +#endif /* _CMU_LFCCLKSEL_MASK */ + +#define CMU_LFE_SELECT_DISABLED \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ + } while (0) + +#define CMU_LFE_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ + } while (0) + +#define CMU_LFE_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ + } while (0) + +#define CMU_LFE_SELECT_ULFRCO \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFE_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ +#endif /* _SILICON_LABS_32B_SERIES_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_CMU_LFCLKSEL_LFAE_MASK) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) +#endif /* CMU_LFA_SELECT_HFCLKLE */ +#endif /* _CMU_LFCLKSEL_LFAE_MASK */ + +#if defined(_CMU_LFCLKSEL_LFBE_MASK) +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) +#endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ +#endif /* _CMU_LFCLKSEL_LFBE_MASK */ + +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) +#endif /* _SILICON_LABS_32B_SERIES_0 */ + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ + } while (0) +#endif /* _CMU_DBGCLKSEL_DBG_MASK */ + +#if defined(CMU_CTRL_DBGCLK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_HFCLK; \ + } while (0) +#endif /* CMU_CTRL_DBGCLK */ + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define CMU_USBC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ + } while (0) + +#define CMU_USBC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ + } while (0) + +#if defined(CMU_STATUS_USBCHFCLKSEL) +#define CMU_USBC_SELECT_HFCLK \ + do { \ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ + } while (0) +#endif /* CMU_STATUS_USBCHFCLKSEL */ + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) +#define CMU_USBC_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ + } while (0) +#endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ +#endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +#define CMU_ADC0ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) +#define CMU_ADC1ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) +#define CMU_SDIOREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) +#define CMU_QSPI0REF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) +#define CMU_USBR_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXOX2 \ + do { \ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) +#define CMU_PDMREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ +#endif /* _SILICON_LABS_32B_SERIES_2 */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_EM_CMU_H */ diff --git a/Libs/platform/emlib/src/em_acmp.c b/Libs/platform/emlib/src/em_acmp.c new file mode 100644 index 0000000..ebb7560 --- /dev/null +++ b/Libs/platform/emlib/src/em_acmp.c @@ -0,0 +1,709 @@ +/***************************************************************************//** + * @file + * @brief Analog Comparator (ACMP) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_acmp.h" +#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) + +#include +#include "em_bus.h" +#include "sl_assert.h" +#include "em_gpio.h" + +/***************************************************************************//** + * @addtogroup acmp ACMP - Analog Comparator + * @brief Analog comparator (ACMP) Peripheral API + * + * @details + * The Analog Comparator is used to compare voltage of two analog inputs + * with a digital output indicating which input voltage is higher. Inputs can + * either be one of the selectable internal references or from external pins. + * Response time and current consumption can be configured by + * altering the current supply to the comparator. + * + * ACMP is available down to EM3 and is able to wake up the system when + * input signals pass a certain threshold. Use @ref ACMP_IntEnable() to enable + * an edge interrupt to use this functionality. + * + * This example shows how to use the em_acmp.h API for comparing an input + * pin to an internal 2.5 V reference voltage. + * + * @if DOXYDOC_P1_DEVICE + * @include em_acmp_compare_s0.c + * @endif + * + * @if DOXYDOC_P2_DEVICE + * @include em_acmp_compare_s1.c + * @endif + * + * @if DOXYDOC_S2_DEVICE + * @include em_acmp_compare_s2.c + * @endif + * + * @note + * ACMP can also be used to compare two separate input pins. + * + * @details + * ACMP also contains specialized hardware for capacitive sensing. This + * module contains the @ref ACMP_CapsenseInit() function to initialize + * ACMP for capacitive sensing and the @ref ACMP_CapsenseChannelSet() function + * to select the current capsense channel. + * + * For applications that require capacitive sensing it is recommended to use a + * library, such as cslib, which is provided by Silicon Labs. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of ACMP register block pointer reference + * for assert statements. */ +#if (ACMP_COUNT == 1) +#define ACMP_REF_VALID(ref) ((ref) == ACMP0) +#elif (ACMP_COUNT == 2) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1)) +#elif (ACMP_COUNT == 3) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1) || ((ref) == ACMP2)) +#elif (ACMP_COUNT == 4) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) \ + || ((ref) == ACMP1) \ + || ((ref) == ACMP2) \ + || ((ref) == ACMP3)) +#else +#error Undefined number of analog comparators (ACMP). +#endif + +/** The maximum value that can be inserted in the route location register + * for the specific device. */ +#if defined(_ACMP_ROUTE_LOCATION_LOC3) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC3 +#elif defined(_ACMP_ROUTE_LOCATION_LOC2) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC2 +#elif defined(_ACMP_ROUTE_LOCATION_LOC1) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC1 +#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_LOC31 +#elif defined(_ACMP_ROUTELOC0_OUTLOC_MASK) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_MASK +#endif + +/** Map ACMP reference to index of device. */ +#if (ACMP_COUNT == 1) +#define ACMP_DEVICE_ID(acmp) ( \ + (acmp) == ACMP0 ? 0 \ + : 0) +#elif (ACMP_COUNT == 2) +#define ACMP_DEVICE_ID(acmp) ( \ + (acmp) == ACMP0 ? 0 \ + : (acmp) == ACMP1 ? 1 \ + : 0) +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set up ACMP for use in capacitive sense applications. + * + * @details + * This function sets up ACMP for use in capacitive sense applications. + * To use the capacitive sense functionality in the ACMP, use + * the PRS output of the ACMP module to count the number of oscillations + * in the capacitive sense circuit (possibly using a TIMER). + * + * @note + * A basic example of capacitive sensing can be found in the STK BSP + * (capsense demo). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * A call to ACMP_CapsenseInit will enable and disable the ACMP peripheral, + * which can cause side effects if it was previously set up. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure ACMP for capacitive + * sensing operation. + ******************************************************************************/ +void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init) +{ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(init->vrefDiv < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); + + ACMP_Disable(acmp); + acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) + | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + ACMP_Enable(acmp); + acmp->INPUTCTRL = (init->resistor << _ACMP_INPUTCTRL_CSRESSEL_SHIFT) + | (init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT) + | (ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + if (!init->enable) { + ACMP_Disable(acmp); + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(init->vddLevelLow < 64); + EFM_ASSERT(init->vddLevelHigh < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + + /* Set the control register. No need to set interrupt modes. */ + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | ACMP_CTRL_ACCURACY_HIGH; + acmp->HYSTERESIS0 = (init->vddLevelHigh << _ACMP_HYSTERESIS0_DIVVA_SHIFT) + | (init->hysteresisLevel_0 << _ACMP_HYSTERESIS0_HYST_SHIFT); + acmp->HYSTERESIS1 = (init->vddLevelLow << _ACMP_HYSTERESIS1_DIVVA_SHIFT) + | (init->hysteresisLevel_1 << _ACMP_HYSTERESIS1_HYST_SHIFT); + /* Select capacitive sensing mode by selecting a resistor and enabling it. */ + acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) + | ACMP_INPUTSEL_CSRESEN + | ACMP_INPUTSEL_VASEL_VDD + | ACMP_INPUTSEL_NEGSEL_VADIV; + BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(init->vddLevel < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + + /* Set the control register. No need to set interrupt modes. */ + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) + | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT); + /* Select capacitive sensing mode by selecting a resistor and enabling it. */ + acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) + | ACMP_INPUTSEL_CSRESEN + | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) + | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT) + | ACMP_INPUTSEL_NEGSEL_CAPSENSE; + BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); +#endif +} + +/***************************************************************************//** + * @brief + * Set the ACMP channel used for capacitive sensing. + * + * @note + * A basic example of capacitive sensing can be found in the STK BSP + * (capsense demo). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Can only be called when the peripheral is enabled. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] channel + * The ACMP channel to use for capacitive sensing (Possel). + ******************************************************************************/ +void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_INPUTSEL_POSSEL_CH7) + /* Make sure that only external channels are used. */ + EFM_ASSERT(channel <= _ACMP_INPUTSEL_POSSEL_CH7); +#elif defined(_ACMP_INPUTCTRL_POSSEL_PD15) + EFM_ASSERT(channel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + EFM_ASSERT(_ACMP_INPUTCTRL_POSSEL_PA0 <= channel); + EFM_ASSERT(channel <= _ACMP_INPUTCTRL_POSSEL_PD15); +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) + /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ + EFM_ASSERT(acmp->EN & ACMP_EN_EN); + + while (acmp->SYNCBUSY != 0U) { + /* Wait for synchronization to finish */ + } + /* Set channel as positive channel in ACMP */ + BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_POSSEL_MASK, + channel << _ACMP_INPUTCTRL_POSSEL_SHIFT); +#else + /* Set channel as a positive channel in ACMP. */ + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, + channel << _ACMP_INPUTSEL_POSSEL_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Disable ACMP. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Disable(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_EN_MASK) + while ((acmp->EN != 0U) && (acmp->SYNCBUSY != 0U)) { + /* Wait for synchronization to finish */ + } + acmp->EN_CLR = ACMP_EN_EN; + +#if defined(_ACMP_EN_DISABLING_MASK) + while (acmp->EN & _ACMP_EN_DISABLING_MASK) { + // Wait for disabling to finish + } +#endif + +#else + acmp->CTRL &= ~ACMP_CTRL_EN; +#endif +} + +/***************************************************************************//** + * @brief + * Enable ACMP. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Enable(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_EN_MASK) + acmp->EN_SET = ACMP_EN_EN; +#else + acmp->CTRL |= ACMP_CTRL_EN; +#endif +} + +#if defined(_ACMP_EXTIFCTRL_MASK) +/***************************************************************************//** + * @brief + * Select and enable external input. + * + * @details + * This is used when an external module needs to take control of the ACMP + * POSSEL field to configure the APORT input for the ACMP. Modules, + * such as LESENSE, use this to change the ACMP input during a scan sequence. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] aport + * This parameter decides which APORT(s) the ACMP will use when it's + * controlled by an external module. + ******************************************************************************/ +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) +{ + acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) + | ACMP_EXTIFCTRL_EN; + while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) { + } +} +#endif + +/***************************************************************************//** + * @brief + * Reset ACMP to the same state that it was in after a hardware reset. + * + * @note + * The GPIO ACMP ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @note + * The peripheral may be enabled and disabled during reset. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Reset(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(ACMP_SWRST_SWRST) + acmp->SWRST_SET = ACMP_SWRST_SWRST; + while (acmp->SWRST & _ACMP_SWRST_RESETTING_MASK) { + } +#else + acmp->IEN = _ACMP_IEN_RESETVALUE; + ACMP_Enable(acmp); + acmp->INPUTCTRL = _ACMP_INPUTCTRL_RESETVALUE; + ACMP_Disable(acmp); + acmp->CFG = PM5507_ACMP_CFG_RESETVALUE; + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + acmp->IF_CLR = _ACMP_IF_MASK; +#endif +#else // Series 0 and Series 1 devices + acmp->IEN = _ACMP_IEN_RESETVALUE; + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + acmp->INPUTSEL = _ACMP_INPUTSEL_RESETVALUE; +#if defined(_ACMP_HYSTERESIS0_HYST_MASK) + acmp->HYSTERESIS0 = _ACMP_HYSTERESIS0_RESETVALUE; + acmp->HYSTERESIS1 = _ACMP_HYSTERESIS1_RESETVALUE; +#endif + acmp->IFC = _ACMP_IF_MASK; +#endif +} + +#if defined(_GPIO_ACMP_ROUTEEN_MASK) +/***************************************************************************//** + * @brief + * Sets up GPIO output from the ACMP. + * + * @note + * GPIO must be enabled in the CMU before this function call, i.e. + * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim + * + * @param[in] acmp + * Pointer to the ACMP peripheral register block. + * + * @param port + * The GPIO port to use. + * + * @param pin + * The GPIO pin to use. + * + * @param enable + * Enable or disable pin output. + * + * @param invert + * Invert output. + ******************************************************************************/ +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, + unsigned int pin, bool enable, bool invert) +{ + int acmpIndex = ACMP_DEVICE_ID(acmp); + + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Make sure that the port/pin combination is valid. */ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + /* Set GPIO inversion */ + acmp->CTRL = (acmp->CTRL & _ACMP_CTRL_NOTRDYVAL_MASK) + | (invert << _ACMP_CTRL_GPIOINV_SHIFT); + + GPIO->ACMPROUTE[acmpIndex].ACMPOUTROUTE = (port << _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT) + | (pin << _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT); + GPIO->ACMPROUTE[acmpIndex].ROUTEEN = enable ? GPIO_ACMP_ROUTEEN_ACMPOUTPEN : 0; +} +#else +/***************************************************************************//** + * @brief + * Set up GPIO output from ACMP. + * + * @note + * GPIO must be enabled in the CMU before this function call, i.e., + * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param location + * The pin location to use. See the data sheet for location to pin mappings. + * + * @param enable + * Enable or disable pin output. + * + * @param invert + * Invert output. + ******************************************************************************/ +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert) +{ + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Sanity checking of location */ + EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_MAX); + + /* Set GPIO inversion */ + BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, + invert << _ACMP_CTRL_GPIOINV_SHIFT); + +#if defined(_ACMP_ROUTE_MASK) + acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT) + | (enable << _ACMP_ROUTE_ACMPPEN_SHIFT); +#endif +#if defined(_ACMP_ROUTELOC0_MASK) + acmp->ROUTELOC0 = location << _ACMP_ROUTELOC0_OUTLOC_SHIFT; + acmp->ROUTEPEN = enable ? ACMP_ROUTEPEN_OUTPEN : 0; +#endif +} +#endif /* defined(_GPIO_ACMP_ROUTEEN_MASK) */ + +/***************************************************************************//** + * @brief + * Set which channels should be used in ACMP comparisons. + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Can only be called when the peripheral is enabled. + * + * @note + * If GPIO is used for both posSel and negSel, they cannot both use even + * or odd pins. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param negSel + * A channel to use on the negative input to the ACMP. + * + * @param posSel + * A channel to use on the positive input to the ACMP. + ******************************************************************************/ +void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, + ACMP_Channel_TypeDef posSel) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Make sure that posSel and negSel channel selectors are valid. */ +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) + EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_DAC0CH1); +#elif defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) + EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_CAPSENSE); +#endif + +#if defined(_ACMP_INPUTSEL_POSSEL_CH7) + EFM_ASSERT(posSel <= _ACMP_INPUTSEL_POSSEL_CH7); +#endif + + /* Make sure that posSel and negSel channel selectors are valid. */ +#if defined(_ACMP_INPUTCTRL_POSSEL_PD15) + EFM_ASSERT(negSel <= _ACMP_INPUTCTRL_POSSEL_PD15); + EFM_ASSERT(posSel <= _ACMP_INPUTCTRL_POSSEL_PD15); + EFM_ASSERT(posSel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + + /* Make sure that posSel and negSel channel selectors don't both + * use odd or even pins. */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + EFM_ASSERT(!((((posSel >= _ACMP_INPUTCTRL_POSSEL_EXTPA) + && (posSel <= _ACMP_INPUTCTRL_POSSEL_EXTPD)) + || (posSel >= _ACMP_INPUTCTRL_POSSEL_PA0)) + && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) + && (posSel % 2 == negSel % 2))); +#else + EFM_ASSERT(!((posSel >= _ACMP_INPUTCTRL_POSSEL_PA0) + && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) + && (posSel % 2 == negSel % 2))); + +#endif +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) + /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ + EFM_ASSERT(acmp->EN & ACMP_EN_EN); + while (acmp->SYNCBUSY != 0U) { + /* Wait for synchronization to finish */ + } + acmp->INPUTCTRL = (acmp->INPUTCTRL & ~(_ACMP_INPUTCTRL_POSSEL_MASK + | _ACMP_INPUTCTRL_NEGSEL_MASK)) + | (negSel << _ACMP_INPUTCTRL_NEGSEL_SHIFT) + | (posSel << _ACMP_INPUTCTRL_POSSEL_SHIFT); +#else + acmp->INPUTSEL = (acmp->INPUTSEL & ~(_ACMP_INPUTSEL_POSSEL_MASK + | _ACMP_INPUTSEL_NEGSEL_MASK)) + | (negSel << _ACMP_INPUTSEL_NEGSEL_SHIFT) + | (posSel << _ACMP_INPUTSEL_POSSEL_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Initialize ACMP. + * + * @cond DOXYDOC_S2_DEVICE + * @note + * A call to ACMP_Init can cause side effects since it can enable/disable + * the peripheral. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure ACMP. + ******************************************************************************/ +void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(init->biasProg + <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); + +// PM-5507: enforce that biasProg is a functional value +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT(init->biasProg >= 4); +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Allow customer to use BIASPROG in [2; 3] + EFM_ASSERT(init->biasProg >= 2); +#else + // Allow customer to use BIASPROG in [0; 3] + // but the implementation of the wait operation would be their responsibility +#endif + + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) + | (init->inputRange << _ACMP_CFG_INPUTRANGE_SHIFT) + | (init->accuracy << _ACMP_CFG_ACCURACY_SHIFT) + | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); + acmp->CTRL = init->inactiveValue << _ACMP_CTRL_NOTRDYVAL_SHIFT; + ACMP_Enable(acmp); + BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_VREFDIV_MASK, + init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT); + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) + | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) + | (init->inputRange << _ACMP_CTRL_INPUTRANGE_SHIFT) + | (init->accuracy << _ACMP_CTRL_ACCURACY_SHIFT) + | (init->powerSource << _ACMP_CTRL_PWRSEL_SHIFT) + | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); + acmp->INPUTSEL = init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT; + acmp->HYSTERESIS0 = init->hysteresisLevel_0; + acmp->HYSTERESIS1 = init->hysteresisLevel_1; + +#elif defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) + | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) + | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) + | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT) + | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); + acmp->INPUTSEL = (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) + | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT); + +#endif + + if (init->enable) { + ACMP_Enable(acmp); + } else { + ACMP_Disable(acmp); + } +} + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/***************************************************************************//** + * @brief + * Set up the VA source. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] vaconfig + * A pointer to the structure used to configure the VA source. This structure + * contains the input source and the 2 divider values. + ******************************************************************************/ +void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig) +{ + EFM_ASSERT(vaconfig->div0 < 64); + EFM_ASSERT(vaconfig->div1 < 64); + + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK, + vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK, + vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK, + vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT); +} +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/***************************************************************************//** + * @brief + * Set up the VB Source. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] vbconfig + * A pointer to the structure used to configure the VB source. This structure + * contains the input source and the 2 divider values. + ******************************************************************************/ +void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig) +{ + EFM_ASSERT(vbconfig->div0 < 64); + EFM_ASSERT(vbconfig->div1 < 64); + + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK, + vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK, + vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK, + vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT); +} +#endif + +/** @} (end addtogroup acmp) */ +#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_burtc.c b/Libs/platform/emlib/src/em_burtc.c new file mode 100644 index 0000000..d79eacf --- /dev/null +++ b/Libs/platform/emlib/src/em_burtc.c @@ -0,0 +1,433 @@ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_burtc.h" +#if defined(BURTC_PRESENT) + +/***************************************************************************//** + * @addtogroup burtc BURTC - Backup RTC + * @brief Backup Real Time Counter (BURTC) Peripheral API + * @details + * This module contains functions to control the BURTC peripheral of Silicon + * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all + * energy modes. The Backup RTC is also available when the system is in backup + * mode. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/***************************************************************************//** + * @brief Convert dividend to a prescaler logarithmic value. Only works for even + * numbers equal to 2^n. + * @param[in] div Unscaled dividend, + * @return Base 2 logarithm of input, as used by fixed prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t divToLog2(uint32_t div) +{ + uint32_t log2; + + /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ + EFM_ASSERT((div > 0UL) && (div <= 32768UL)); + + /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ + log2 = (31UL - __CLZ(div)); + + return log2; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(uint32_t mask) +{ +#if defined(_BURTC_FREEZE_MASK) + /* Avoid deadlock if modifying the same register twice when freeze mode is + activated or when a clock is not selected for the BURTC. If a clock is + not selected, then the sync is done once the clock source is set. */ + if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) + || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) + || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { + return; + } +#endif + + /* Wait for any pending previous write operation to complete */ + /* in low frequency domain. This is only required for the Gecko Family. */ + while ((BURTC->SYNCBUSY & mask) != 0U) { + } +} +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief Initialize BURTC. + * + * @details + * Configures the BURTC peripheral. + * + * @note + * Before initialization, BURTC module must first be enabled by clearing the + * reset bit in the RMU, i.e., + * @verbatim + * RMU_ResetControl(rmuResetBU, rmuResetModeClear); + * @endverbatim + * Compare channel 0 must be configured outside this function, before + * initialization if enable is set to true. The counter will always be reset. + * + * @param[in] burtcInit + * A pointer to the BURTC initialization structure. + ******************************************************************************/ +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t ctrl; + uint32_t presc; + + /* Check initializer structure integrity. */ + EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); + /* Clock divider must be between 1 and 128, really on the form 2^n. */ + EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); + + /* Ignored compare bits during low power operation must be less than 7. */ + /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ + EFM_ASSERT(burtcInit->lowPowerComp <= 6); + /* You cannot enable the BURTC if mode is set to disabled. */ + EFM_ASSERT((burtcInit->enable == false) + || ((burtcInit->enable == true) + && (burtcInit->mode != burtcModeDisable))); + /* Low power mode is only available with LFRCO or LFXO as clock source. */ + EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) + || ((burtcInit->clkSel == burtcClkSelULFRCO) + && (burtcInit->lowPowerMode == burtcLPDisable))); + + /* Calculate a prescaler value from the clock divider input. */ + /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of + value 1 will select a 2 kHz ULFRCO clock, while any other value will + select a 1 kHz ULFRCO clock source. */ + presc = divToLog2(burtcInit->clkDiv); + + /* Make sure all registers are updated simultaneously. */ + if (burtcInit->enable) { + BURTC_FreezeEnable(true); + } + + /* Modification of LPMODE register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_LPMODE); + + /* Configure low power mode. */ + BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); + + /* New configuration. */ + ctrl = (BURTC_CTRL_RSTEN + | (burtcInit->mode) + | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) + | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) + | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) + | (presc << _BURTC_CTRL_PRESC_SHIFT) + | (burtcInit->clkSel) + | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); + + /* Clear interrupts. */ + BURTC_IntClear(0xFFFFFFFF); + + /* Set the new configuration. */ + BURTC->CTRL = ctrl; + + /* Enable BURTC and counter. */ + if (burtcInit->enable) { + /* To enable BURTC counter, disable reset. */ + BURTC_Enable(true); + + /* Clear freeze. */ + BURTC_FreezeEnable(false); + } +#elif defined(_SILICON_LABS_32B_SERIES_2) + uint32_t presc; + + presc = divToLog2(burtcInit->clkDiv); + + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + + BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) + | ((burtcInit->compare0Top ? 1UL : 0UL) << _BURTC_CFG_COMPTOP_SHIFT) + | ((burtcInit->debugRun ? 1UL : 0UL) << _BURTC_CFG_DEBUGRUN_SHIFT); + BURTC->EM4WUEN = ((burtcInit->em4comp ? 1UL : 0UL) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) + | ((burtcInit->em4overflow ? 1UL : 0UL) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); + BURTC->EN_SET = BURTC_EN_EN; + if (burtcInit->start) { + BURTC_Start(); + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral. + * + * @param[in] enable + * true to enable, false to disable. + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#endif + + if ((BURTC->EN == 0U) && !enable) { + /* Trying to disable BURTC when it's already disabled */ + return; + } + + if (BURTC->EN != 0U) { + /* Modifying the enable bit while synchronization is active will BusFault */ + BURTC_SyncWait(); + } + + if (enable) { + BURTC->EN_SET = BURTC_EN_EN; + } else { + BURTC_Stop(); + BURTC_SyncWait(); /* Wait for the stop to synchronize */ + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } +} +#elif defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral reset and start counter + * @param[in] enable + * If true; asserts reset to BURTC, halts counter, if false; deassert reset + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ + /* Note! If mode is disabled, BURTC counter will not start */ + EFM_ASSERT(((enable == true) + && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) + != BURTC_CTRL_MODE_DISABLE)) + || (enable == false)); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); +} +#endif + +/***************************************************************************//** + * @brief Set BURTC compare channel. + * + * @param[in] comp Compare the channel index, must be 0 for current devices. + * + * @param[in] value New compare value. + ******************************************************************************/ +void BURTC_CompareSet(unsigned int comp, uint32_t value) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); + +#if defined(_BURTC_COMP0_MASK) + /* Modification of COMP0 register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_COMP0); + + /* Configure compare channel 0/. */ + BURTC->COMP0 = value; +#else + /* Wait for last potential write to complete. */ + regSync(BURTC_SYNCBUSY_COMP); + + /* Configure compare channel 0 */ + BURTC->COMP = value; + regSync(BURTC_SYNCBUSY_COMP); +#endif +} + +/***************************************************************************//** + * @brief Get the BURTC compare value. + * + * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. + * + * @return The currently configured value for this compare channel. + ******************************************************************************/ +uint32_t BURTC_CompareGet(unsigned int comp) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); +#if defined(_BURTC_COMP0_MASK) + return BURTC->COMP0; +#else + return BURTC->COMP; +#endif +} + +/***************************************************************************//** + * @brief Reset counter + ******************************************************************************/ +void BURTC_CounterReset(void) +{ +#if defined(_BURTC_CTRL_MASK) + /* Set and clear reset bit */ + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); +#else + BURTC_Stop(); + BURTC->CNT = 0U; + BURTC_Start(); +#endif +} + +/***************************************************************************//** + * @brief + * Restore BURTC to reset state. + * @note + * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. + * LOCK will not be reset to default value, as this will disable access + * to core BURTC registers. + ******************************************************************************/ +void BURTC_Reset(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + bool buResetState; + + /* Read reset state, set reset, and restore state. */ + buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); +#elif defined(_SILICON_LABS_32B_SERIES_2) + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_SET = BURTC_EN_EN; + BURTC_Stop(); + BURTC->CNT = 0x0; + BURTC->PRECNT = 0x0; + BURTC->COMP = 0x0; + BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; + BURTC->IEN = _BURTC_IEN_RESETVALUE; + BURTC->IF_CLR = _BURTC_IF_MASK; + /* Wait for all values to synchronize. BusFaults can happen if we don't + * do this before the enable bit is cleared. */ + BURTC_SyncWait(); + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + while (BURTC->SYNCBUSY != 0U) { + // Wait for the EN=0 to synchronize + } +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + BURTC->CFG = _BURTC_CFG_RESETVALUE; +#endif +} + +#if defined(_BURTC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Get the clock frequency of the BURTC. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t BURTC_ClockFreqGet(void) +{ + uint32_t clkSel; + uint32_t clkDiv; + uint32_t frequency; + + clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; + clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; + + switch (clkSel) { + /** Ultra-low frequency (1 kHz) clock. */ + case BURTC_CTRL_CLKSEL_ULFRCO: + if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { + frequency = 2000; /* 2 kHz when clock divisor is 1. */ + } else { + frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different + from 1. */ + } + break; + + /** Low-frequency RC oscillator. */ + case BURTC_CTRL_CLKSEL_LFRCO: + frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + /** Low-frequency crystal oscillator. */ + case BURTC_CTRL_CLKSEL_LFXO: + frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + default: + /* No clock selected for BURTC. */ + frequency = 0; + } + return frequency; +} +#endif + +/** @} (end addtogroup burtc) */ + +#endif /* BURTC_PRESENT */ diff --git a/Libs/platform/emlib/src/em_cmu.c b/Libs/platform/emlib/src/em_cmu.c new file mode 100644 index 0000000..dd704b7 --- /dev/null +++ b/Libs/platform/emlib/src/em_cmu.c @@ -0,0 +1,11864 @@ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_cmu.h" +#if defined(CMU_PRESENT) + +#include +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "em_emu.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +#include "em_msc.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +/***************************************************************************//** + * @addtogroup cmu CMU - Clock Management Unit + * @brief Clock management unit (CMU) Peripheral API + * @details + * This module contains functions for the CMU peripheral of Silicon Labs 32-bit + * MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock + * multiplexers, pre-scalers, calibration modules and wait-states. + * @{ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +// Maximum allowed core frequency vs. wait-states on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL + +// Maximum allowed core frequency vs. wait-states on sram accesses. +#define CMU_MAX_SRAM_FREQ_0WS 50000000UL +#define CMU_MAX_SRAM_FREQ_1WS 80000000UL + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// Maximum allowed core frequency vs. wait-states and vscale on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 20000000UL +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define CMU_MAX_FREQ_0WS_1V1 25000000UL +#define CMU_MAX_FREQ_1WS_1V1 50000000UL +#define CMU_MAX_FREQ_2WS_1V1 75000000UL +#else + #warning "MCU flash wait states not supported" +#endif + +// Maximum allowed PCLK frequency. +#define CMU_MAX_PCLK_FREQ 50000000UL + +// Maximum allowed RHCLK frequency. +#define CMU_MAX_RHCLK_FREQ 40000000UL + +#if defined(EMU_VSCALE_EM01_PRESENT) +// This macro is intended to be used as input to CMU_UpdateWaitStates() +#define VSCALE_DEFAULT (2 - (int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +#if defined(PLFRCO_PRESENT) +// Typical frequency for HFXO as recommanded in the datasheets. +// see AN0016: Oscillator Design Considerations +// +// Recommended for most wireless applications +// to meet transceiver electrical specifications +#define XTAL_38M4 38400000UL +// Recommended for implementing Z-Wave devices +#define XTAL_39M0 39000000UL +// High Precision mode calibration Counts for 38.4MHz +#define LFRCO_NOMCAL_XTAL_38M4 _LFRCO_NOMCAL_RESETVALUE +#define LFRCO_NOMCALINV_XTAL_38M4 _LFRCO_NOMCALINV_RESETVALUE +// High Precision mode calibration Counts for 39.0MHz. +#define LFRCO_NOMCAL_XTAL_39M0 0x0005CFBBUL +#define LFRCO_NOMCALINV_XTAL_39M0 0x0000581AUL +#endif + +#define PLL0_USB_OUTPUT_FREQ 48000000UL + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Table of HFRCOCAL values and their associated min/max frequencies and +// optional band enumerator. +static const struct hfrcoCalTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCODPLLFreq_TypeDef band; +} hfrcoCalTable[] = +{ + // minFreq maxFreq HFRCOCAL value band + { 900000UL, 1080000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, + { 1080000UL, 1300000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1300000UL, 1530000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1530000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1800000UL, 2150000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, + { 2150000UL, 2600000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 2600000UL, 3050000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3050000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3600000UL, 4300000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, + { 4300000UL, 5200000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 5200000UL, 6100000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 6100000UL, 7800000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, + { 7800000UL, 9800000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 9800000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, + { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, + { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, + { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz }, +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + { 80000000UL, 100000000UL, 0xCCF19F00UL, cmuHFRCODPLLFreq_100M0Hz } +#endif +}; + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +#define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ + / sizeof(struct hfrcoCalTableElement)) + +// CTUNE delta needed for some series 2 chips. This delta is added to the tuning capacitance on XO. +// The inter-chip buffered crystal sharing feature added from the EFR32xG23 creates an imbalance +// between XI and XO capacitance load internally on the chip. The delta allows to compensate for +// the difference. +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +static int8_t ctuneDelta = 40; // Recommendation from analog team to counter the internal chip imbalance. +#else +static int8_t ctuneDelta = 0; +#endif +#endif + +static uint8_t pclkDiv = 0; + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUART_PRESENT) +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUSART_PRESENT) +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(LCD_PRESENT) +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(VDAC_PRESENT) +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if (VDAC_COUNT > 1) +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(PCNT_PRESENT) +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(LESENSE_PRESENT) +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +static void rhclkPrescMax(void); +static void rhclkPrescOptimize(void); +#endif +#endif + +#if defined(HFRCOEM23_PRESENT) +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale); +static void flashWaitStateControl(uint32_t coreFreq, int vscale); +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); +#if defined(IADC_PRESENT) +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void pclkDivMax(void); +static void pclkDivOptimize(void); +#if defined(RTCC_PRESENT) +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#elif defined(SYSRTC_PRESENT) +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void waitStateMax(void); +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if WDOG_COUNT > 1 +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(USB_PRESENT) +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +/** @endcond */ + +// The following code is common for all SERIES_2 configurations. + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Calibrate an oscillator. + * + * @details + * Run a calibration of a selectable reference clock againt HCLK. Please + * refer to the reference manual, CMU chapter, for further details. + * + * @note + * This function will not return until calibration measurement is completed. + * + * @param[in] cycles + * The number of HCLK cycles to run calibration. Increasing this number + * increases precision, but the calibration will take more time. + * + * @param[in] ref + * The reference clock used to compare against HCLK. + * + * @return + * The number of ticks the selected reference clock ticked while running + * cycles ticks of the HCLK clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) +{ + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALTOP_CALTOP_MASK + >> _CMU_CALTOP_CALTOP_SHIFT)); +#endif + + CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); + CMU_CalibrateStart(); + return CMU_CalibrateCountGet(); +} + +/***************************************************************************//** + * @brief + * Configure clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * Refer to the reference manual, CMU chapter, for further details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required, and + * the resulting calibration value can be read with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run calibration. Increasing this + * number increases precision, but the calibration will take more time. + * + * @param[in] downSel + * The clock which will be counted down downCycles cycles. + * + * @param[in] upSel + * The reference clock, the number of cycles generated by this clock will + * be counted and added up, the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel) +{ + // Keep untouched configuration settings + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK + | _CMU_CALCTRL_DOWNSEL_MASK +#if defined(_CMU_CALCTRL_CALTOP_MASK) + | _CMU_CALCTRL_CALTOP_MASK +#endif + ); + + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); + calCtrl |= downCycles; +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALTOP_CALTOP_MASK >> _CMU_CALTOP_CALTOP_SHIFT)); + CMU->CALTOP = downCycles << _CMU_CALTOP_CALTOP_SHIFT; +#endif + + // Set down counting clock source selector + switch (downSel) { + case cmuSelect_HCLK: + calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; + break; + + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + // Set up counting clock source selector + switch (upSel) { + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_UPSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} + +/***************************************************************************//** + * @brief + * Get calibration count value. + * + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off, and reading the value will be just needed, where the normal + * case would be that this function call has been triggered by the CALRDY + * interrupt flag. + * + * @return + * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + // Wait until calibration completes, UNLESS continuous calibration mode is on + if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { + // Wait until calibration completes + while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { + } + } + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Direct a clock to a GPIO pin. + * + * @param[in] clkNo + * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2. + * + * @param[in] sel + * Select clock source. + * + * @param[in] clkDiv + * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is + * selected as clock source. + * + * @param[in] port + * GPIO port. + * + * @param[in] pin + * GPIO pin. + * + * @note + * Refer to the reference manual and the datasheet for details on which + * GPIO port/pins that are available. + ******************************************************************************/ +void CMU_ClkOutPinConfig(uint32_t clkNo, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkDiv, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + uint32_t tmp = 0U, mask; + + EFM_ASSERT(pin <= 15U); + + switch (clkNo) { + case 0: + case 1: + EFM_ASSERT((port == 2U) || (port == 3U)); + break; + case 2: + EFM_ASSERT((port == 0U) || (port == 1U)); + break; + default: + EFM_ASSERT(false); + break; + } + + switch (sel) { + case cmuSelect_Disabled: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; + break; + + case cmuSelect_HFRCODPLL: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; + break; +#endif + + case cmuSelect_EXPCLK: + EFM_ASSERT((clkDiv > 0U) && (clkDiv <= 32U)); + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; + break; + + case cmuSelect_LFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; + break; + + case cmuSelect_HCLK: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; + break; + + default: + EFM_ASSERT(false); + break; + } + + mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK + << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); + tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; + + if (sel == cmuSelect_EXPCLK) { + tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; + } + + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; + + if (sel == cmuSelect_Disabled) { + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); + } else { + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + if (clkNo == 0U) { + GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + } else if (clkNo == 1) { + GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + } else { + GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + } + GPIO_PinModeSet(port, pin, gpioModePushPull, 0); + } +} + +/***************************************************************************//** + * @brief + * Get clock divisor. + * + * @param[in] clock + * Clock point to get divisor for. Notice that not all clock points + * have a divisors. Please refer to CMU overview in reference manual. + * + * @return + * The current clock point divisor. 1 is returned + * if @p clock specifies a clock point without divisor. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (ret == 2U ) { // Unused value, illegal prescaler + EFM_ASSERT(false); + } +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + if (!((ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV1) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV2) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV4) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV8) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV16))) { + // Illegal prescaler + EFM_ASSERT(false); + } +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: + ret = (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_PRESC_MASK) + >> _CMU_TRACECLKCTRL_PRESC_SHIFT; + if (!((ret == _CMU_TRACECLKCTRL_PRESC_DIV1) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV2) +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV3) +#endif + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV4))) { + // Illegal prescaler + EFM_ASSERT(false); + } + break; +#endif + + case cmuClock_EXPCLK: + ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) + >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + break; + + case cmuClock_PCLK: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; + break; + + default: + break; + } + return 1U + ret; +} + +/***************************************************************************//** + * @brief + * Set clock divisor. + * + * @param[in] clock + * Clock point to set divisor for. Notice that not all clock points + * have a divisor, please refer to CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use. + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U) + || (div == 8U) || (div == 16U)); +#endif + + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Set new divisor + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); + + // Update CMSIS core clock variable and set optimum wait-states + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 3U) || (div == 4U)); +#else + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#endif + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_TRACECLKCTRL_PRESC_SHIFT); +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + + case cmuClock_EXPCLK: + EFM_ASSERT((div >= 1U) && (div <= 32U)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); + break; + + case cmuClock_PCLK: + EFM_ASSERT((div == 1U) || (div == 2U)); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); + break; + + default: + EFM_ASSERT(false); + break; + } +} + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * Module clocks sre disabled after reset. If a module clock is disabled, the + * registers of that module are not accessible and accessing such registers + * will hardfault the Cortex core. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +SL_WEAK void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg = NULL; + uint32_t bit; + + /* Identify the enable register. */ + if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_NO_EN_REG) { + EFM_ASSERT(false); /* No enable for this clock. */ + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN0_EN_REG) { + reg = &CMU->CLKEN0; + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN1_EN_REG) { + reg = &CMU->CLKEN1; +#if defined(_CMU_CLKEN2_MASK) + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN2_EN_REG) { + reg = &CMU->CLKEN2; +#endif + } else { +#if defined(CRYPTOACC_PRESENT) + reg = &CMU->CRYPTOACCCLKCTRL; +#else + // No register to enable clock. Possible hard fault exception. + EFM_ASSERT(false); +#endif + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_CORE: + case cmuClock_HCLK: + case cmuClock_LDMA: + case cmuClock_GPCRC: + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_I2C1: + case cmuClock_PRS: + case cmuClock_PCLK: + case cmuClock_GPIO: + case cmuClock_USART0: + case cmuClock_USART1: + case cmuClock_USART2: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_I2C0: + case cmuClock_LSPCLK: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: + em4GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; + + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; + + case cmuClock_DPLLREFCLK: + dpllRefClkGet(&ret, NULL); + break; + + case cmuClock_TRACECLK: + traceClkGet(&ret, NULL); + break; + + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + uint32_t freq = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_HCLK: + case cmuClock_CORE: + case cmuClock_ICACHE: + case cmuClock_MSC: + case cmuClock_LDMA: + case cmuClock_SMU: +#if defined(RADIOAES_PRESENT) + case cmuClock_RADIOAES: +#endif +#if defined(CRYPTOACC_PRESENT) + case cmuClock_CRYPTOACC: + case cmuClock_CRYPTOAES: + case cmuClock_CRYPTOPK: +#endif +#if defined(MVP_PRESENT) + case cmuClock_MVP: +#endif + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_PCLK: +#if defined(USART_PRESENT) + case cmuClock_USART0: +#if USART_COUNT > 1 + case cmuClock_USART1: +#endif +#endif + case cmuClock_I2C1: +#if I2C_COUNT > 2 + case cmuClock_I2C2: +#endif +#if I2C_COUNT > 3 + case cmuClock_I2C3: +#endif + case cmuClock_PRS: + case cmuClock_GPIO: + case cmuClock_GPCRC: + case cmuClock_LDMAXBAR: + case cmuClock_SYSCFG: + case cmuClock_DCDC: + case cmuClock_BURAM: + case cmuClock_DPLL0: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_LSPCLK: + case cmuClock_I2C0: + case cmuClock_AMUXCP0: +#if defined(ACMP_PRESENT) + case cmuClock_ACMP0: +#if ACMP_COUNT > 1 + case cmuClock_ACMP1: +#endif +#endif + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + + case cmuClock_TRACECLK: + traceClkGet(&freq, NULL); + ret = freq / CMU_ClockDivGet(cmuClock_TRACECLK); + break; + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; +#if defined(PDM_PRESENT) + case cmuClock_PDM: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(&ret, NULL); + break; +#endif +#if defined(EUART_PRESENT) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(&ret, NULL); + break; +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(&ret, NULL); + break; +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(&ret, NULL); + break; +#endif +#endif + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; +#if WDOG_COUNT > 1 + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; +#endif +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; +#endif +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(&ret, NULL); + break; +#endif +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(&ret, NULL); + break; +#endif +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(&ret, NULL); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(&ret, NULL); + break; +#endif +#endif /* VDAC_PRESENT */ +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(&ret, NULL); + break; +#endif +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(&ret, NULL); + break; +#endif + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(&ret, NULL); + break; + +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(&ret, NULL); + break; +#endif + + case cmuClock_DPLLREFCLK: + dpllRefClkGet(&ret, NULL); + break; + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/***************************************************************************//** + * @brief + * Get currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. + * + * @return + * Reference clock used for clocking selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Error; + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = cmuSelect_HFRCODPLL; + break; + + case CMU_SYSCLKCTRL_CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = cmuSelect_CLKIN0; + break; + + case CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = cmuSelect_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: + ret = cmuSelect_RFFPLLSYS; + break; +#endif + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + sysTickClkGet(NULL, &ret); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + dpllRefClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + case cmuClock_TRACECLK: + traceClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(NULL, &ret); + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(NULL, &ret); + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(NULL, &ret); + break; +#endif + #endif + +// ----------------------------------------------------------------------------- +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(NULL, &ret); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(NULL, &ret); + break; +#endif +#endif +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void) +{ +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Save the previous PCLK divisor + pclkDiv = CMU_ClockDivGet(cmuClock_PCLK); + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif +} + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(bool optimize_divider) +{ + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + if (optimize_divider) { + // Set optimal PCLK divisor + pclkDivOptimize(); + } else { + // Restore previous PCLK divisor + CMU_ClockDivSet(cmuClock_PCLK, pclkDiv); + } +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif +} + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void) +{ +#if defined(_CMU_CLKEN0_MASK) && defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +} + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_setSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief + * Select reference clock/oscillator used for a clock branch. + * + * @param[in] clock + * Clock branch to select reference clock for. + * + * @param[in] ref + * Reference selected for clocking, please refer to reference manual for + * for details on which reference is available for a specific clock branch. + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t tmp = 0U; + bool oscForceEnStatus = false; +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + bool syscfgClkIsOff = false; +#endif +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; +#if defined(_CMU_CLKEN0_MASK) +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif +#endif + // Make sure HFXO is enabled. + oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_FSRCO: + tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case cmuSelect_RFFPLLSYS: + tmp = CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Switch to selected oscillator. + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; + + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + + if (oscForceEnStatus == false) { + switch (ref) { + case cmuSelect_HFXO: + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + break; + + default: + break; + } + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL + & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + case cmuSelect_LFXO: + case cmuSelect_LFRCO: + case cmuSelect_ULFRCO: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_setSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_setSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); + break; + case cmuSelect_HCLK: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_clearSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); + break; + default: + EFM_ASSERT(false); + break; + } + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL + & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + case cmuClock_EM4GRPACLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL + & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; + break; + + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL + & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + switch (ref) { + case cmuSelect_HFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_LFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_Disabled: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL + & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + switch (ref) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + case cmuSelect_HCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + case cmuSelect_SYSCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_SYSCLK; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | tmp; +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_Disabled: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + switch (ref) { +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case cmuSelect_EM01GRPCCLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case cmuSelect_FSRCO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case cmuSelect_LFXO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; + break; +#endif + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case cmuSelect_Disabled: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + case cmuSelect_FSRCO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif + +// ----------------------------------------------------------------------------- +#if defined (RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined (SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_LCDCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_LCDCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_LCDCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif /* VDAC_PRESENT */ +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_PCNTEXTCLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + switch (ref) { + case cmuSelect_USBPLL0: + tmp = CMU_USB0CLKCTRL_CLKSEL_USBPLL0; + break; + case cmuSelect_LFXO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFXO; + break; + case cmuSelect_LFRCO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(PLFRCO_PRESENT) +#if defined(LFRCO_CFG_HIGHPRECEN) + case cmuSelect_LFRCO: + case cmuSelect_PLFRCO: + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { + precision = 500; + } else { + precision = 0xFFFF; + } + break; +#endif +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCODPLL: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Get HFRCODPLL band in use. + * + * @return + * HFRCODPLL band in use. + ******************************************************************************/ +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) +{ + return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCODPLL band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCODPLL frequency band to activate. + ******************************************************************************/ +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + uint32_t freqCal, sysFreq; +#if defined(EMU_VSCALE_EM01_PRESENT) + uint32_t prevFreq; +#endif + + // Get calibration data from DEVINFO + freqCal = HFRCODPLLDevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + // Make sure DPLL is disabled before configuring + if (DPLL0->EN == DPLL_EN_EN) { + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + } + + // Set max wait-states and PCLK divisor while changing core clock + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + } + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCODPLLFreq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCODPLLFreq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + prevFreq = SystemHFRCODPLLClockGet(); + + if ((uint32_t)freq > prevFreq) { + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)freq, true); + } +#endif + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = freqCal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (freqCal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(freq); + } else { + // revert back to previous value + HFRCO0->CAL = hfrcoCalCurrent; +#if defined(EMU_VSCALE_EM01_PRESENT) + freq = (CMU_HFRCODPLLFreq_TypeDef)prevFreq; +#endif + } + + // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access + // wait-state configuration and PCLK divisor for this frequency. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)freq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((uint32_t)freq <= prevFreq) { + /* When decreasing frequency voltage scale must be done after the change. */ + EMU_VScaleEM01ByClock(0, true); + } +#endif +} + +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCODPLL should be switched to a lower + * frequency clock (if possible) prior to calling this function to avoid + * over-clocking. + * + * @param[in] init + * DPLL setup parameter struct. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hclkDivIncreased = false; + uint32_t hfrcoCalVal, lockStatus = 0, hclkDiv = 0, sysFreq; + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + bool hfrcoClamped = false; + bool restoreDpll; + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; + + // Make sure DPLL is disabled before configuring + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); + + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); + EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. + for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCalTable[i].minFreq) + && (init->frequency <= hfrcoCalTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCalVal = hfrcoCalTable[index].value; + + // Check if a calibrated HFRCOCAL.TUNING value is present in device DI page. + if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) + & _HFRCO_CAL_TUNING_MASK) + >> _HFRCO_CAL_TUNING_SHIFT; + hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Increase HCLK divider value (if possible) while locking DPLL to + // avoid over-clocking. + hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); + hclkDivIncreased = true; + if (hclkDiv == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } else if (hclkDiv == 2U) { + CMU_ClockDivSet(cmuClock_HCLK, 4U); + } else { + hclkDivIncreased = false; + } + } + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = hfrcoCalVal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (hfrcoCalVal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) + | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); + + /* For series 2 silicon, macro expansion is used to select clock + * sources since it results in less code size when compared to the legacy + * CMU_ClockSelectSet function. + */ + if (init->refClk == cmuSelect_HFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, HFXO); + } else if (init->refClk == cmuSelect_LFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, LFXO); + } else if (init->refClk == cmuSelect_CLKIN0) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, CLKIN0); + } + + DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) + | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) + | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); + + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(init->frequency); + } else { + hfrcoClamped = true; + HFRCO0->CAL = hfrcoCalCurrent; + } + + /* + * if HFRCO frequency range has been clamped, re-enable DPLL only if it was + * previously enabled + */ + if (!hfrcoClamped || restoreDpll) { + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + + // Lock DPLL + DPLL0->EN_SET = DPLL_EN_EN; + while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK + | DPLL_IF_LOCKFAILLOW + | DPLL_IF_LOCKFAILHIGH))) == 0UL) { + } + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + if (hclkDivIncreased) { + // Restore original HCLK divider + CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); + } + + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); + EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); + + // Set optimal wait-states and PCLK divisor + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + + if (hfrcoClamped) { + return false; + } else if (lockStatus == DPLL_IF_LOCK) { + return true; + } + return false; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the USB PLL control registers. + * + * @note + * The HFXO reference frequency must be updated if crystal value is + * different from default value. + * + * @param[in] pllInit + * USB PLL parameters + ******************************************************************************/ +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit) +{ + CMU->CLKEN1_SET = CMU_CLKEN1_USB; + + USBPLL0->LOCK = USBPLL_LOCK_LOCKKEY_UNLOCK; + + // Stop the PLL for configuration purposes + USBPLL0->CTRL_SET = USBPLL_CTRL_DISONDEMAND; + USBPLL0->CTRL_CLR = USBPLL_CTRL_FORCEEN; + + while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; + + if (pllInit->hfxoRefFreq == cmuHFXORefFreq_39M0Hz) { + // Set DCO in low frequency mode for 39 MHz crystal. + USBPLL0->DCOCTRL_SET = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } else { + USBPLL0->DCOCTRL_CLR = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + USBPLL0->CTRL = (USBPLL0->CTRL & ~(_USBPLL_CTRL_SHUNTREGLPEN_MASK + | _USBPLL_CTRL_DIVR_MASK + | _USBPLL_CTRL_DIVX_MASK + | _USBPLL_CTRL_DIVN_MASK + | _USBPLL_CTRL_DISONDEMAND_MASK + | _USBPLL_CTRL_FORCEEN_MASK)) + | pllInit->hfxoRefFreq + | pllInit->shuntRegEn << _USBPLL_CTRL_SHUNTREGLPEN_SHIFT + | pllInit->disOnDemand << _USBPLL_CTRL_DISONDEMAND_SHIFT + | pllInit->forceEn << _USBPLL_CTRL_FORCEEN_SHIFT; + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + if (pllInit->forceEn) { + CMU_WaitUSBPLLLock(); + } + + if (pllInit->regLock) { + USBPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the RFFPLL control registers. + * + * @param[in] pllInit + * RFF PLL parameters + ******************************************************************************/ +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit) +{ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_RFFPLLSYS); + EFM_ASSERT(pllInit->dividerY >= 8 && pllInit->dividerY <= 31); + EFM_ASSERT(pllInit->dividerX >= 4 && pllInit->dividerX <= 15); + EFM_ASSERT(pllInit->dividerN >= 32 && pllInit->dividerN <= 127); + + CMU->CLKEN1_SET = CMU_CLKEN1_RFFPLL0; + + RFFPLL0->LOCK = RFFPLL_LOCK_LOCKKEY_UNLOCK; + + RFFPLL0->CTRL = (RFFPLL0->CTRL & ~(_RFFPLL_CTRL_DISONDEMAND_MASK | _RFFPLL_CTRL_FORCEEN_MASK)) + | (pllInit->disOnDemand << _RFFPLL_CTRL_DISONDEMAND_SHIFT) + | (pllInit->forceEn << _RFFPLL_CTRL_FORCEEN_SHIFT); + + RFFPLL0->RFFPLLCTRL1 = (RFFPLL0->RFFPLLCTRL1 & ~(_RFFPLL_RFFPLLCTRL1_DIVY_MASK | _RFFPLL_RFFPLLCTRL1_DIVX_MASK | _RFFPLL_RFFPLLCTRL1_DIVN_MASK)) + | (pllInit->dividerY << _RFFPLL_RFFPLLCTRL1_DIVY_SHIFT) + | (pllInit->dividerX << _RFFPLL_RFFPLLCTRL1_DIVX_SHIFT) + | (pllInit->dividerN << _RFFPLL_RFFPLLCTRL1_DIVN_SHIFT); + + // Update CMSIS RFFPLL frequency. + SystemRFFPLLClockSet(pllInit->frequency); + + if (pllInit->forceEn) { + CMU_WaitRFFPLLLock(); + } + + if (pllInit->regLock) { + RFFPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +/**************************************************************************//** + * @brief + * Initialize all HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function returns early if HFXO is + * already selected as SYSCLK. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + // Check all initialization structure members which may overflow target + // bitfield. + EFM_ASSERT(hfxoInit->timeoutCbLsb + <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK + >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteady + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXoStartup + <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXiStartup + <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->coreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->imCoreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + EFM_ASSERT(hfxoInit->coreDegenAna + <= (_HFXO_XTALCTRL_COREDGENANA_MASK + >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneFixAna + <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK + >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); + EFM_ASSERT(hfxoInit->mode + <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); + + // Return early if HFXO is already selected as SYSCLK. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { + return; + } + +#if defined(CMU_CLKEN0_HFXO0) + // Enable HFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable HFXO. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND +#if defined(_HFXO_CTRL_DISONDEMANDBUFOUT_MASK) + | HFXO_CTRL_DISONDEMANDBUFOUT +#endif + ; + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { + } +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + +#if defined(_DEVINFO_HFXOCAL_VTRTRIMANA_MASK) && defined(_HFXO_BUFOUTTRIM_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_VTRTRIMANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, + _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK, + tmp << _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT); + } +#endif + +#if defined(_DEVINFO_HFXOCAL_SHUNTBIASANA_MASK) && defined(_HFXO_LOWPWRCTRL_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, + _HFXO_LOWPWRCTRL_SHUNTBIASANA_MASK, + tmp << _HFXO_LOWPWRCTRL_SHUNTBIASANA_SHIFT); + } +#endif + + // Configure HFXO as specified in initialization struct, use + // timeoutSteadyFirstLock as TIMEOUTSTEADY value. + HFXO0->XTALCFG = + (uint32_t)((hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) + | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) + | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) + | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) + | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) + | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) + | (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) + | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) + | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) + | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + // See [PM-2871] for details. + BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), + 0x00000C00U, + 0x00000002U << 10); +#endif + + HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK + | _HFXO_CFG_ENXIDCBIASANA_MASK + | _HFXO_CFG_MODE_MASK)) + | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) + ? 0 : HFXO_CFG_SQBUFSCHTRGANA) + | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) + | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); + + if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { + // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared. + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | HFXO_CTRL_FORCEEN; + + // Wait for HFXO lock and core bias algorithm to complete. +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS + | HFXO_STATUS_FSMLOCK)) { + } +#else + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS)) { + } +#endif + // Set DISONDEMAND to be able to enter new values for use on subsequent locks. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD = HFXO_CMD_MANUALOVERRIDE; +#endif +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Set new TIMEOUTSTEADY value for use on subsequent locks. + HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) + | (hfxoInit->timeoutSteady + << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); + + // Skip core bias algorithm on subsequent locks. + HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; + + if (hfxoInit->disOnDemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + + if (hfxoInit->forceEn == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + } + } else { + // Lock HFXO in EXTERNAL SINE mode. + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + //See [PM-3665] for details. + if (hfxoInit->mode == cmuHfxoOscMode_ExternalSinePkDet) { + HFXO0->XTALCFG = 0; + HFXO0->XTALCTRL = 0; + + const uint32_t PKDETTHSTARTUP_PARAMETER_1 = 2UL; + BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), + 0x0000F000U | 0x00000F00U, + (PKDETTHSTARTUP_PARAMETER_1 << 12) | (PKDETTHSTARTUP_PARAMETER_1 << 8)); + } +#endif + + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); + } + + if (hfxoInit->regLock) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +#if defined(HFXO0_BUFOUT) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) leader control registers. + * Configure the bufout request input GPIO as a clock request signal + * to add the crystal sharing follower chip as a source of clock request. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @param[in] bufoutInit + * Bufout setup parameters. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // Configure Bufout request GPIO. + GPIO_PinModeSet(port, pin, gpioModeInput, 0U); + GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT + | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; + + BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, + _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK + | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, + bufoutInit->minimalStartupDelay << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT + | bufoutInit->timeoutStartup << _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) follower control registers. + * Configure the clock request signal to a specified GPIO to automatically + * request the high frequency crystal oscillator sine wave clock. + * This function must be used in conjunction with CMU_HFXOInit() configured + * with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @note + * This function can be emulated on XG21/XG22 chips by controlling the clock + * request GPIO to ask the crystal sharing leader clock when needed. + * + * @param[in] prsStatusSelectOutput + * Selected HFXO PRS signal output. + * + * @param[in] prsAsyncCh + * PRS producer asynchronous signal channel. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(prsAsyncCh < PRS_ASYNC_CH_NUM); + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + uint32_t mask = 0U, prsSignal = 0U, value = 0U; + + switch (prsStatusSelectOutput) { + case PRS_Status_select_0: + mask = _HFXO_CTRL_PRSSTATUSSEL0_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS; + break; + + case PRS_Status_select_1: +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Power Manager module requires the HFXO PRS Producer output 1 for its usage. + EFM_ASSERT(false); +#else + mask = _HFXO_CTRL_PRSSTATUSSEL1_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL1_ENS << _HFXO_CTRL_PRSSTATUSSEL1_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1; +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } + + value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT + | prsSignal << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + + mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK + | _PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK + | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; + + BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); + + GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); + + (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[prsAsyncCh] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT + | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; + GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + prsAsyncCh); +} +#endif + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning capacitance. + * + * @param[in] ctune + * The desired tuning capacitance value. Each step corresponds to + * approximately 80fF. Min value is 0. Max value is 255. + * + * @return + * SL_STATUS_OK if initialization parameter is valid. + * SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid. + * + * @note + * While the oscillator is running in steady operation state, it may be + * desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA + * fields in the HFXO_XTALCTRL register. When tuning, care should be taken to + * make small changes to the CTUNE registers. Ideally, change the CTUNE + * registers by one LSB at a time and alternate between the XI and XO + * registers. Sufficient wait time for settling, on the order of + * TIMEOUTSTEADY, should pass before new frequency measurement is taken. + *****************************************************************************/ +SL_WEAK sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Make sure the given CTUNE value is within the allowable range + if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + int32_t ctuneXoana = ctune + CMU_HFXOCTuneDeltaGet(); + if (ctuneXoana < 0) { + ctuneXoana = 0; + } else if (ctuneXoana > (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT)) { + ctuneXoana = (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); // Max value + } + + HFXO0->XTALCTRL = ((HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXOANA_MASK | _HFXO_XTALCTRL_CTUNEXIANA_MASK)) + | ((uint32_t)ctuneXoana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | ((ctune << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) & _HFXO_XTALCTRL_CTUNEXIANA_MASK)); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning capacitance. + * + * @return + * The HFXO crystal tuning capacitance. + * + * @note + This function only returns the CTUNE XI value. The XO value can be + different and can be found using the delta (difference between XI and XO). + See @ref CMU_HFXOCTuneCurrentDeltaGet to retrieve the delta value. + *****************************************************************************/ +SL_WEAK uint32_t CMU_HFXOCTuneGet(void) +{ + uint32_t ctune = 0; + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) + >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return ctune; +} + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning delta. + * + * @param[in] delta + * Chip dependent crystal capacitor bank delta between HFXO XI and XO. + * + * @note + * The delta between XI and XO is applicable for the series 2 EFR32xG2x + * devices only. Neither XI nor XO is actually modified by this function, + * CMU_HFXOCTuneSet() needs to be called for the change to be propagated. + *****************************************************************************/ +void CMU_HFXOCTuneDeltaSet(int32_t delta) +{ + ctuneDelta = (int8_t)delta; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning delta. It can be default recommended delta value + * or value set by CMU_HFXOCTuneDeltaSet. + * + * @return + * Chip dependent crystal capacitor bank tuning delta. + *****************************************************************************/ +int32_t CMU_HFXOCTuneDeltaGet(void) +{ + return (int32_t)ctuneDelta; +} + +/**************************************************************************//** + * @brief + * Get the current delta between HFXO XI and XO. + * + * @return + * the current delta between HFXO XI and XO. + *****************************************************************************/ +int32_t CMU_HFXOCTuneCurrentDeltaGet(void) +{ + uint32_t ctune; + uint32_t ctuneXO; + int32_t ctuneCurrentDelta; + + ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) + >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); + ctuneXO = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXOANA_MASK) + >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); + ctuneCurrentDelta = (int32_t)ctuneXO - (int32_t)ctune; + return ctuneCurrentDelta; +} + +/**************************************************************************//** + * @brief + * Recalibrate the HFXO's Core Bias Current. + * + * @note + * Care should be taken when using this function as it can cause disturbance + * on the HFXO frequency while the optimization is underway. It's recommended + * to only use this function when HFXO isn't being used. It's also a blocking + * function that can be time consuming. + *****************************************************************************/ +SL_WEAK void CMU_HFXOCoreBiasCurrentCalibrate(void) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // These two bits need to be set to allow writing the registers + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) { + // Wait for crystal to startup + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) + != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { + // Making sure HFXO is in steady state + } + + // Start core bias optimization + HFXO0->CMD_SET = HFXO_CMD_COREBIASOPT; + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == HFXO_STATUS_COREBIASOPTRDY) { + // Wait for core bias optimization to start + } + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias optimization to finish + } + + // Force COREBIASANA bitfields modification +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias current value to be written in COREBIASANA bitfields + } + + BUS_RegMaskedWrite(&HFXO0->CTRL, (_HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK), hfxoCtrlBkup); +} + +/**************************************************************************//** + * @brief + * Initialize LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function disables the LFXO to ensure + * a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + EFM_ASSERT(lfxoInit->timeout + <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); + EFM_ASSERT(lfxoInit->mode + <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); + EFM_ASSERT(lfxoInit->gain + <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); + EFM_ASSERT(lfxoInit->capTune + <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + + // Max internal capacitance tuning value is 0x4F (20 pF) + uint8_t ctune = (uint8_t) SL_MIN(0x4FU, lfxoInit->capTune); + +#if defined(CMU_CLKEN0_LFXO) + // Enable LFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + + // Unlock register interface + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable LFXO + LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; + LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; + while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { + } + + // Configure LFXO as specified + LFXO->CAL = ((uint32_t)lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + LFXO->CFG = (uint32_t)((lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) + | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) + | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) + | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT)); + + LFXO->CTRL = (uint32_t)((lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) + | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) + | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) + | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT)); + + if (lfxoInit->regLock) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +#if defined(PLFRCO_PRESENT) +/**************************************************************************//** + * @brief + * Configure the LFRCO precision. + * + * @details + * When enabling high precision mode on the LFRCO the hardware will tune + * the oscillator automatically using the HFXO as a reference. + * + * @note + * Refer to the reference manual and the datasheet for details about + * NOMCAL and NOMCALINV calibration count values. + * + * @param[in] precision + * LFRCO precision, this can be either high or default. + *****************************************************************************/ +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision) +{ + uint32_t ref = 0; + uint32_t nomcal = 0; + uint32_t nomcalinv = 0; + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + LFRCO->CTRL = LFRCO_CTRL_DISONDEMAND; // Force disable + while ((LFRCO->STATUS & LFRCO_STATUS_ENS) != 0U) { + // Wait for LFRCO to stop + } + + if (precision == cmuPrecisionHigh) { + ref = SystemHFXOClockGet(); + // Use precomputed value for HFXO typical frequencies + if (ref == XTAL_38M4) { + nomcal = LFRCO_NOMCAL_XTAL_38M4; + nomcalinv = LFRCO_NOMCALINV_XTAL_38M4; + } else if (ref == XTAL_39M0) { + nomcal = LFRCO_NOMCAL_XTAL_39M0; + nomcalinv = LFRCO_NOMCALINV_XTAL_39M0; + } else { + // Compute calibration count, based on HFXO frequency + nomcal = (5 * ref) >> 9; + nomcalinv = ((1UL << 31) / 5) << 2; + nomcalinv /= (ref >> 9); + } + + LFRCO->NOMCAL = nomcal; + LFRCO->NOMCALINV = nomcalinv; + + LFRCO->CFG = LFRCO_CFG_HIGHPRECEN; + } else { + LFRCO->CFG = 0; + } + LFRCO->CTRL = _LFRCO_CTRL_RESETVALUE; +} +#endif + +/***************************************************************************//** + * @brief + * Get oscillator frequency tuning setting. + * + * @param[in] osc + * Oscillator to get tuning value for. + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret = 0U; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + ret = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK) >> _HFXO_XTALCTRL_COREBIASANA_SHIFT; + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + ret = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production, and the tuning value is + * automatically loaded after a reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * Oscillator to set tuning value for. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ + bool disondemand = false; + bool lfxo_lock_status = false; + uint8_t ctune = 0; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK + >> _LFRCO_CAL_FREQTRIM_SHIFT)); + val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; + while (LFRCO->SYNCBUSY != 0U) { + } + LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) + | (val << _LFRCO_CAL_FREQTRIM_SHIFT); + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + EFM_ASSERT(val <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); + // Make sure HFXO is disable + EFM_ASSERT((HFXO0->STATUS & HFXO_STATUS_ENS) == 0); + + // Set DISONDEMAND if not already set and wait for FSMLOCK to be clear so that + // software can write to register + disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) >> _HFXO_CTRL_DISONDEMAND_SHIFT; + if (disondemand == false) { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Update Core Bias Ana setting and enable Optimization skip + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) + | (val << _HFXO_XTALCTRL_COREBIASANA_SHIFT) + | HFXO_XTALCTRL_SKIPCOREBIASOPT; + // Clear back DISONDEMAND if needed + if (disondemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + lfxo_lock_status = (LFXO->STATUS & _LFXO_STATUS_LOCK_MASK) >> _LFXO_STATUS_LOCK_SHIFT; + // Unlock register interface if register is locked before + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + } + + EFM_ASSERT(val <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for CALBSY bit to clear before writing the tuning value to CAL register + while (((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) >> _LFXO_SYNCBUSY_CAL_SHIFT) != 0U) { + } + LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + // Lock register interface again + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure wait state settings necessary to switch to a given core clock + * frequency at a certain voltage scale level. + * + * @details + * This function will set up the necessary flash wait states. Updating the + * wait state configuration must be done before increasing the clock + * frequency and it must be done after decreasing the clock frequency. + * Updating the wait state configuration must be done before core voltage is + * decreased and it must be done after a core voltage is increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 1, higher number is lower voltage. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + if (vscale > 0) { + flashWaitStateControl(freq, VSCALE_EM01_LOW_POWER); + } else { + flashWaitStateControl(freq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select EM23GRPACLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ + (void)instance; +#if defined(PCNT_PRESENT) + if (external) { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + } else { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + } +#else + (void)external; +#endif +} + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get HFRCOEM23 band in use. + * + * @return + * HFRCOEM23 band in use. + ******************************************************************************/ +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) +{ + return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCOEM23 band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCOEM23 frequency band to activate. + ******************************************************************************/ +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t freqCal; + + // Get calibration data from DEVINFO + freqCal = HFRCOEM23DevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); +#if defined(CMU_CLKEN0_HFRCOEM23) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; +#endif + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCOEM23Freq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCOEM23Freq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + + // Activate new band selection + HFRCOEM23->CAL = freqCal; +} +#endif // defined(HFRCOEM23_PRESENT) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPBCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + switch (CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(EUART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + switch (CMU->EUART0CLKCTRL & _CMU_EUART0CLKCTRL_CLKSEL_MASK) { + case CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(freq, sel); + break; + + case CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(freq, sel); + break; + + default: + if (freq != NULL) { + *freq = 0U; + } + if (sel != NULL) { + *sel = cmuSelect_Error; + } + EFM_ASSERT(false); + break; + } +} +#endif + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUSART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EUSART0CLKCTRL & _CMU_EUSART0CLKCTRL_CLKSEL_MASK) { +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK: + em01GrpcClkGet(&f, NULL); + s = cmuSelect_EM01GRPCCLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case CMU_EUSART0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +/**************************************************************************//** +* @brief +* Get selected oscillator and frequency for @ref cmuClock_EM01GRPCCLK +* clock tree. +* +* @param[out] freq +* The frequency. +* +* @param[out] sel +* The selected oscillator. +******************************************************************************/ +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) + case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + case _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_CMU_EM01GRPCCLKCTRL_MASK) +#endif // defined(EUSART_PRESENT) + +#if defined(LCD_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LCDCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LCDCLKCTRL & _CMU_LCDCLKCTRL_CLKSEL_MASK) { + case CMU_LCDCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(LCD_PRESENT) + +#if defined(VDAC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC0CLKCTRL & _CMU_VDAC0CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if (VDAC_COUNT > 1) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC1CLKCTRL & _CMU_VDAC1CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_PCNT0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->PCNT0CLKCTRL & _CMU_PCNT0CLKCTRL_CLKSEL_MASK) { + case CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0: + f = 0U; // external or PRS source so the frequency is undefined. + s = cmuSelect_PCNTEXTCLK; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(LESENSE_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LESENSEHFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LESENSEHFCLKCTRL & _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) { + case CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +/***************************************************************************//** + * @brief + * Set maximum allowed prescaler for radio clock tree (RHCLK). + ******************************************************************************/ +static void rhclkPrescMax(void) +{ + // Set largest prescaler (DIV2). + CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_RHCLKPRESC; +} + +/***************************************************************************//** + * @brief + * Set radio clock tree prescaler to achieve highest possible frequency + * and still be within spec. + ******************************************************************************/ +static void rhclkPrescOptimize(void) +{ + if (CMU_ClockFreqGet(cmuClock_SYSCLK) <= CMU_MAX_RHCLK_FREQ) { + // Set smallest prescaler (DIV1). + CMU->SYSCLKCTRL_CLR = CMU_SYSCLKCTRL_RHCLKPRESC; + } +} +#endif // ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +#endif // #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get calibrated HFRCOEM23 tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCOEM23 frequency band + ******************************************************************************/ +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCOEM23Freq_1M0Hz: + case cmuHFRCOEM23Freq_2M0Hz: + case cmuHFRCOEM23Freq_4M0Hz: + ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_13M0Hz: + ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_16M0Hz: + ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_19M0Hz: + ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_26M0Hz: + ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_32M0Hz: + ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_40M0Hz: + ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(HFRCOEM23_PRESENT) + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_TRACECLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { +#if defined(_CMU_TRACECLKCTRL_CLKSEL_HCLK) + case CMU_TRACECLKCTRL_CLKSEL_HCLK: + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + break; +#endif +#if defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) + case CMU_TRACECLKCTRL_CLKSEL_SYSCLK: + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } +#else + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; +#endif + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { + case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale) +{ + uint32_t flashWs = MSC_READCTRL_MODE_WS3; + + if (vscale == 0) { + // VScale 1.1V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V1) + else if (freq > CMU_MAX_FREQ_2WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V1) + else if (freq > CMU_MAX_FREQ_1WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V1) + else if (freq > CMU_MAX_FREQ_0WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } else if (vscale >= 1) { + // VScale 1.0V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V0) + else if (freq > CMU_MAX_FREQ_2WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V0) + else if (freq > CMU_MAX_FREQ_1WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V0) + else if (freq > CMU_MAX_FREQ_0WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } + return flashWs; +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency and vscale level. + * + * @note Current implementation sets wait states depending on frequency only. + * This assumes that applications running on Vscale enabled microcontrollers + * never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). + * Series 2 Config 1 devices does not support vscale. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 1 where 0 is the default. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + (void)vscale; + + uint32_t mode; + bool mscLocked; + +#if defined(CMU_CLKEN1_MSC) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + coreFreq *= CMU_ClockDivGet(cmuClock_CORE); +#endif + + // Make sure the MSC is unlocked + mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + // Get current flash read setting + mode = MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK; + + // Set new mode based on the core clock frequency + mode |= getWaitStatesByFrequencyAndVScale(coreFreq, vscale); + + MSC_ReadCTRLSet(mode); + + // Set sram wait states for config 1 mcu. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // Set new mode based on the core clock frequency + if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { + SYSCFG_setDmem0RamCtrlRamwsenBit(); + } else { + SYSCFG_clearDmem0RamCtrlRamwsenBit(); + } +#endif + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +/***************************************************************************//** + * @brief + * Get calibrated HFRCODPLL tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCODPLL frequency band + ******************************************************************************/ +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCODPLLFreq_1M0Hz: + case cmuHFRCODPLLFreq_2M0Hz: + case cmuHFRCODPLLFreq_4M0Hz: + ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_7M0Hz: + ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_13M0Hz: + ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_16M0Hz: + ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_19M0Hz: + ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_26M0Hz: + ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_32M0Hz: + ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_38M0Hz: + ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_48M0Hz: + ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_56M0Hz: + ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_64M0Hz: + ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_80M0Hz: + ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; + break; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + case cmuHFRCODPLLFreq_100M0Hz: + ret = DEVINFO->HFRCODPLLCAL[17].HFRCODPLLCAL; + break; +#endif + + case cmuHFRCODPLLFreq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(IADC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_IADCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { + case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_IADCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. + ******************************************************************************/ +static void pclkDivMax(void) +{ + // Set largest divisor for PCLK clock tree. + CMU_ClockDivSet(cmuClock_PCLK, 2U); +} + +/***************************************************************************//** + * @brief + * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible + * frequency and still be within spec. + ******************************************************************************/ +static void pclkDivOptimize(void) +{ + CMU_ClkDiv_TypeDef div = 2U; + + if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { + div = 1U; + } + CMU_ClockDivSet(cmuClock_PCLK, div); +} + +#if defined(RTCC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { + case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(SYSRTC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSRTCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set wait-states to values valid for maximum allowable core clock frequency. + ******************************************************************************/ +static void waitStateMax(void) +{ + flashWaitStateControl(SystemMaxCoreClockGet(), 0); +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSTICK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + } else { + em23GrpaClkGet(&f, &s); + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(USB_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_USB clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->USB0CLKCTRL & _CMU_USB0CLKCTRL_CLKSEL_MASK) { + case CMU_USB0CLKCTRL_CLKSEL_USBPLL0: + f = PLL0_USB_OUTPUT_FREQ; + s = cmuSelect_USBPLL0; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/** @endcond */ + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** The maximum allowed core frequency when using 0 wait-states on flash access. */ +#define CMU_MAX_FREQ_0WS 16000000 +/** The maximum allowed core frequency when using 1 wait-states on flash access */ +#define CMU_MAX_FREQ_1WS 32000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) +// EFR32xG1x and EFM32xG1x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) +// EFR32xG12x and EFM32xG12x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V1 21330000 +#define CMU_MAX_FREQ_1WS_1V1 32000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) +// EFR32xG13x and EFM32xG13x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) +// EFR32xG14x and EFM32xG14x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) +// EFM32GG11x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) +// EFM32TG11x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 48000000 +#define CMU_MAX_FREQ_0WS_1V0 10000000 +#define CMU_MAX_FREQ_1WS_1V0 21000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) +// EFM32GG12x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#else +#error "Max Flash wait-state frequencies are not defined for this platform." +#endif + +/** The maximum frequency for the HFLE interface. */ +#if defined(CMU_CTRL_HFLE) +/** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_WONDER_FAMILY) \ + || defined(_EZR32_WONDER_FAMILY)) +#define CMU_MAX_FREQ_HFLE 24000000UL +/** The maximum HFLE frequency for other series 0 parts with maximum core clock + higher than 32 MHz. */ +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +#define CMU_MAX_FREQ_HFLE maxFreqHfle() +#endif +#elif defined(CMU_CTRL_WSHFLE) +/** The maximum HFLE frequency for series 1 parts. */ +#define CMU_MAX_FREQ_HFLE 32000000UL +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) +#endif + +#if defined(CMU_HFXOCTRL_MODE_EXTCLK) +/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +#define VSCALE_DEFAULT ((int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; +#endif +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) +#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and + an optional band enumerator. */ +static const struct hfrcoCtrlTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCOFreq_TypeDef band; +} hfrcoCtrlTable[] = +{ + // minFreq maxFreq HFRCOCTRL value band + { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, + { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, + { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, + { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, + { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, + { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } +#else + #error "HFRCOCTRL values not set for this platform." +#endif +}; + +#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ + / sizeof(struct hfrcoCtrlTableElement)) +#endif // CMU_OSCENCMD_DPLLEN + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) +/* Devices with Voltage Scaling needs extra handling of wait states. */ +static const struct flashWsTableElement{ + uint32_t maxFreq; + uint8_t vscale; + uint8_t ws; +} flashWsTable[] = +{ +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ + { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ + { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ +#else + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ +#endif +}; + +#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ + || defined(_CMU_USHFRCOTUNE_MASK) +#ifndef EFM32_USHFRCO_STARTUP_FREQ +#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) +#endif + +static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); +#endif + +static void hfperClkSafePrescaler(void); +static void hfperClkOptimizedPrescaler(void); + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +/***************************************************************************//** + * @brief + * Return maximum allowed frequency for low energy peripherals. + ******************************************************************************/ +static uint32_t maxFreqHfle(void) +{ + uint16_t majorMinorRev; + + switch (SYSTEM_GetFamily()) { + case systemPartFamilyEfm32Leopard: + case systemPartFamilyEzr32Leopard: + /* CHIP MAJOR bit [5:0] */ + majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); + /* CHIP MINOR bit [7:4] */ + majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + + if (majorMinorRev >= 0x0204) { + return 24000000; + } else { + return 32000000; + } + + case systemPartFamilyEfm32Giant: + return 32000000; + + default: + /* Invalid device family. */ + EFM_ASSERT(false); + return 0; + } +} +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Unified definitions for the HFLE wait-state and prescaler fields. */ +#if defined(CMU_CTRL_HFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT +#elif defined(CMU_CTRL_WSHFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Set HFLE wait-states and HFCLKLE prescaler according to wanted HF clock. + * + * @param[in] hfFreq + * The HF clock frequency to use. + * This is: + * CORE clock on Series0 devices. + * HF clock on on Series1 devices. + ******************************************************************************/ +static void setHfLeConfig(uint32_t hfFreq) +{ + unsigned int hfleWs; + uint32_t hflePresc; + + /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the + fields are changed to more than 1 bit. */ + EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); + + /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is + above maxLeFreq. + - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ + + hfleWs = 1; + if (hfFreq <= CMU_MAX_FREQ_HFLE) { + hfleWs = 0; + hflePresc = 0; + } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { + hflePresc = 1; + } else { + hflePresc = 2; + } + BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); + GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) + | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); +} + +#if defined(_CMU_CTRL_HFLE_MASK) +/***************************************************************************//** + * @brief + * Get HFLE wait-state configuration. + * + * @return + * The current wait-state configuration. + ******************************************************************************/ +static uint32_t getHfLeConfig(void) +{ + uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); + return ws; +} +#endif +#endif + +/***************************************************************************//** + * @brief + * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, + * by default also as a debug clock. + * + * @return + * AUX Frequency in Hz. + ******************************************************************************/ +static uint32_t auxClkGet(void) +{ + uint32_t ret; + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) + ret = (uint32_t)auxHfrcoFreq; + +#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) + /* All series 0 families except EFM32G */ + switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { + case CMU_AUXHFRCOCTRL_BAND_1MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 1200000; + } else { + ret = 1000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_7MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 6600000; + } else { + ret = 7000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_11MHZ: + ret = 11000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_14MHZ: + ret = 14000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_21MHZ: + ret = 21000000; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case CMU_AUXHFRCOCTRL_BAND_28MHZ: + ret = 28000000; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + +#else + /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ + ret = 14000000; + +#endif + + return ret; +} + +#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ + || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) +/***************************************************************************//** + * @brief + * Get the HFSRCCLK frequency. + * + * @return + * HFSRCCLK Frequency in Hz. + ******************************************************************************/ +static uint32_t hfSrcClkGet(void) +{ + uint32_t ret; + + ret = SystemHFClockGet(); + return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} +#endif + +/***************************************************************************//** + * @brief + * Get the Debug Trace clock frequency. + * + * @return + * Debug Trace frequency in Hz. + ******************************************************************************/ +static uint32_t dbgClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get selected clock source */ + clk = CMU_ClockSelectGet(cmuClock_DBG); + + switch (clk) { + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +/***************************************************************************//** + * @brief + * Get the ADC n asynchronous clock frequency. + * + * @return + * ADC n asynchronous frequency in Hz. + ******************************************************************************/ +static uint32_t adcAsyncClkGet(uint32_t adc) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (adc) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); + break; + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case 1: + clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_Disabled: + ret = 0; + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFSRCCLK: + ret = hfSrcClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_SDIOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the SDIO reference clock frequency. + * + * @return + * SDIO reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t sdioRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_SDIOREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_QSPICTRL_MASK) +/***************************************************************************//** + * @brief + * Get the QSPI n reference clock frequency. + * + * @return + * QSPI n reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t qspiRefClkGet(uint32_t qspi) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (qspi) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); + break; + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_PDMCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the PDM reference clock frequency. + * + * @return + * PDM reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t pdmRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_PDMREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(USBR_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USB rate clock frequency. + * + * @return + * USB rate clock frequency in Hz. + ******************************************************************************/ +static uint32_t usbRateClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + clk = CMU_ClockSelectGet(cmuClock_USBR); + + switch (clk) { + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFXOX2: + ret = 2u * SystemHFXOClockGet(); + break; + + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + uint32_t mode; +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ +#endif + (void) vscale; /* vscale parameter is only used on some devices. */ + + /* Get mode and SCBTP enable. */ + mode = MSC_ReadCTRLGet() & _MSC_READCTRL_MODE_MASK; + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + /* Devices with MODE and SCBTP in the same register field. */ + switch (mode) { + case MSC_READCTRL_MODE_WS0: + case MSC_READCTRL_MODE_WS1: +#if defined(MSC_READCTRL_MODE_WS2) + case MSC_READCTRL_MODE_WS2: +#endif + scbtpEn = false; + break; + + default: /* WSxSCBTP */ + scbtpEn = true; + break; + } + + /* Set mode based on the core clock frequency and SCBTP enable. */ + if (false) { + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq > CMU_MAX_FREQ_1WS) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); + } +#endif + else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); + } else { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); + } +#else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ + + if (coreFreq <= CMU_MAX_FREQ_0WS) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS) { + mode = 1; + } +#endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ +// End defined(_SILICON_LABS_32B_SERIES_0) + +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_EMU_STATUS_VSCALE_MASK) + + /* These devices have specific requirements on the supported flash wait state + * depending on the frequency and voltage scale level. */ + uint32_t i; + for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { + if ((flashWsTable[i].vscale == (uint8_t)vscale) + && (coreFreq <= flashWsTable[i].maxFreq)) { + break; // Found a matching entry. + } + } + + if (i == FLASH_WS_TABLE_ENTRIES) { + mode = 3; // Worst case flash wait state for unsupported cases. + EFM_ASSERT(false); + } else { + mode = flashWsTable[i].ws; + } + mode = mode << _MSC_READCTRL_MODE_SHIFT; + +#else + /* Devices where MODE and SCBTP are in separate fields and where the device + * either does not support voltage scale or where the voltage scale does + * not impact the flash wait state configuration. */ + if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { + mode = 1; + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq <= CMU_MAX_FREQ_2WS) { + mode = 2; + } +#endif +#if defined(MSC_READCTRL_MODE_WS3) + else if (coreFreq <= CMU_MAX_FREQ_3WS) { + mode = 3; + } +#endif + mode = mode << _MSC_READCTRL_MODE_SHIFT; +#endif +// End defined(_SILICON_LABS_32B_SERIES_1) + +#else +#error "Undefined 32B SERIES!" +#endif + + mode = (MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK) | mode; + MSC_ReadCTRLSet(mode); +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to the most conservative setting for + * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) + * setting. + ******************************************************************************/ +static void flashWaitStateMax(void) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(SystemMaxCoreClockGet(), 0); + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) +/***************************************************************************//** + * @brief + * Configure RAM access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure RAM wait-states. + * + * @param[in] vscale + * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void setRamWaitState(uint32_t coreFreq, int vscale) +{ + uint32_t limit = 38000000; + if (vscale == 2) { + limit = 16000000; + } + + if (coreFreq > limit) { + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } else { + BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } +} +#endif + +#if defined(_MSC_CTRL_WAITMODE_MASK) +/***************************************************************************//** + * @brief + * Configure the wait state for peripheral accesses over the bus to support + * the given bus clock frequency. + * + * @param[in] busFreq + * A peripheral bus clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * ******************************************************************************/ +static void setBusWaitState(uint32_t busFreq, int vscale) +{ + if ((busFreq > 50000000) && (vscale == 0)) { + BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } else { + BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } +} +#endif + +#if defined(PLFRCO_PRESENT) +static bool deviceHasPlfrco(void) +{ + SYSTEM_ChipRevision_TypeDef rev; + + if (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) { + // check the xG13 rev and check if it's >= Rev A3 + SYSTEM_ChipRevisionGet(&rev); + return (rev.major > 1) || (rev.minor >= 3); + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Configure various wait states to switch to a certain frequency + * and a certain voltage scale. + * + * @details + * This function will set up the necessary flash, bus, and RAM wait states. + * Updating the wait state configuration must be done before + * increasing the clock frequency and it must be done after decreasing the + * clock frequency. Updating the wait state configuration must be done before + * core voltage is decreased and it must be done after a core voltage is + * increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2, higher number is lower voltage. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(freq, vscale); +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + setRamWaitState(freq, vscale); +#endif +#if defined(_MSC_CTRL_WAITMODE_MASK) + setBusWaitState(freq, vscale); +#endif + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) +/***************************************************************************//** + * @brief + * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. + ******************************************************************************/ +static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) +{ + uint32_t regIshUpper; + const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK + >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ + regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); + regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + return regIshUpper; +} +#endif + +#if defined(_CMU_HFXOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the HFXO tuning mode. + * + * @return + * The current HFXO tuning mode from the HFXOCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t getHfxoTuningMode(void) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; +#else + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; +#endif +} + +/***************************************************************************//** + * @brief + * Set the HFXO tuning mode. + * + * @param[in] mode + * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or + * HFXO_TUNING_MODE_CMD. + ******************************************************************************/ +__STATIC_INLINE void setHfxoTuningMode(uint32_t mode) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); +#else + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get the LFnCLK frequency based on the current configuration. + * + * @param[in] lfClkBranch + * Selected LF branch. + * + * @return + * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is + * returned. + ******************************************************************************/ +static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) +{ + uint32_t sel; + uint32_t ret = 0; + + switch (lfClkBranch) { + case cmuClock_LFA: + case cmuClock_LFB: +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#endif +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); + + /* Get clock select field */ + switch (lfClkBranch) { + case cmuClock_LFA: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; +#elif defined(_CMU_LFACLKSEL_MASK) + sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + + case cmuClock_LFB: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; +#elif defined(_CMU_LFBCLKSEL_MASK) + sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#if defined(_CMU_LFCLKSEL_LFC_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; +#elif defined(_CMU_LFCCLKSEL_LFC_MASK) + sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; +#endif + +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: + sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Get the clock frequency. */ +#if defined(_CMU_LFCLKSEL_MASK) + switch (sel) { + case _CMU_LFCLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFCLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + +#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: +#if defined(CMU_MAX_FREQ_HFLE) + /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the + * frequency of CMU_HFCORECLKLEDIV2. */ + ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); +#else + ret = SystemCoreClockGet() / 2U; +#endif + break; +#endif + + case _CMU_LFCLKSEL_LFA_DISABLED: + ret = 0; +#if defined(CMU_LFCLKSEL_LFAE) + /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ + if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { + if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA + ? _CMU_LFCLKSEL_LFAE_SHIFT + : _CMU_LFCLKSEL_LFBE_SHIFT)) { + ret = SystemULFRCOClockGet(); + } + } +#endif + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif /* _CMU_LFCLKSEL_MASK */ + +#if defined(_CMU_LFACLKSEL_MASK) + switch (sel) { + case _CMU_LFACLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_ULFRCO: + ret = SystemULFRCOClockGet(); + break; + +#if defined(PLFRCO_PRESENT) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + +#if defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) + case _CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = SystemHFClockGet() + / SL_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); + break; +#endif + + case _CMU_LFACLKSEL_LFA_DISABLED: + ret = 0; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low-frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void syncReg(uint32_t mask) +{ + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { + return; + } + + /* Wait for any pending previous write operation to complete */ + /* in low-frequency domain. */ + while ((CMU->SYNCBUSY & mask) != 0UL) { + } +} + +#if defined(USBC_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USBC frequency. + * + * @return + * USBC frequency in Hz. + ******************************************************************************/ +static uint32_t usbCClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_USBC); + + switch (clk) { + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; +#endif + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + default: + /* Clock is not enabled */ + ret = 0; + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to safe values. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkSafePrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + // Assuming a maximum HFCLK of 72MHz, set prescalers to DIV4. + CMU_ClockPrescSet(cmuClock_HFPER, 3U); + CMU_ClockPrescSet(cmuClock_HFPERB, 3U); + CMU_ClockPrescSet(cmuClock_HFPERC, 3U); +#endif +} + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to give highest possible clock node + * frequency while still beeing within spec. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkOptimizedPrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + uint32_t hfClkFreq, divisor; + + hfClkFreq = SystemHFClockGet(); + + if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { + divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) + if (divisor > 0U) { + divisor--; // Convert to prescaler + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + } else { + divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + + divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + } +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get the AUXHFRCO band in use. + * + * @return + * AUXHFRCO band in use. + ******************************************************************************/ +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL + & _CMU_AUXHFRCOCTRL_BAND_MASK) + >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the AUXHFRCO band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] band + * AUXHFRCO band to activate. + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) +{ + uint32_t tuning; + + /* Read a tuning value from the calibration table. */ + switch (band) { + case cmuAUXHFRCOBand_1MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; + break; + + case cmuAUXHFRCOBand_7MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; + break; + + case cmuAUXHFRCOBand_11MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; + break; + + case cmuAUXHFRCOBand_14MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; + break; + + case cmuAUXHFRCOBand_21MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case cmuAUXHFRCOBand_28MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Set band/tuning. */ + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL + & ~(_CMU_AUXHFRCOCTRL_BAND_MASK + | _CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the AUXHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * AUXHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuAUXHFRCOFreq_1M0Hz: + case cmuAUXHFRCOFreq_2M0Hz: + case cmuAUXHFRCOFreq_4M0Hz: + return DEVINFO->AUXHFRCOCAL0; + + case cmuAUXHFRCOFreq_7M0Hz: + return DEVINFO->AUXHFRCOCAL3; + + case cmuAUXHFRCOFreq_13M0Hz: + return DEVINFO->AUXHFRCOCAL6; + + case cmuAUXHFRCOFreq_16M0Hz: + return DEVINFO->AUXHFRCOCAL7; + + case cmuAUXHFRCOFreq_19M0Hz: + return DEVINFO->AUXHFRCOCAL8; + + case cmuAUXHFRCOFreq_26M0Hz: + return DEVINFO->AUXHFRCOCAL10; + + case cmuAUXHFRCOFreq_32M0Hz: + return DEVINFO->AUXHFRCOCAL11; + + case cmuAUXHFRCOFreq_38M0Hz: + return DEVINFO->AUXHFRCOCAL12; + +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + case cmuAUXHFRCOFreq_48M0Hz: + return DEVINFO->AUXHFRCOCAL13; +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + case cmuAUXHFRCOFreq_50M0Hz: + return DEVINFO->AUXHFRCOCAL14; +#endif + + default: /* cmuAUXHFRCOFreq_UserDefined */ + return 0; + } +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Get the current AUXHFRCO frequency. + * + * @return + * AUXHFRCO frequency. + ******************************************************************************/ +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return auxHfrcoFreq; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Set AUXHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * AUXHFRCO frequency to set + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO index and set global auxHfrcoFreq. */ + freqCal = CMU_AUXHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + auxHfrcoFreq = setFreq; + + /* Wait for any previous sync to complete, then set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } + + /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuAUXHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuAUXHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuAUXHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + CMU->AUXHFRCOCTRL = freqCal; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +/***************************************************************************//** + * @brief + * Calibrate the clock. + * + * @details + * Run a calibration for HFCLK against a selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * This function will not return until the calibration measurement is completed. + * + * @param[in] HFCycles + * The number of HFCLK cycles to run the calibration. Increasing this number + * increases precision but the calibration will take more time. + * + * @param[in] reference + * The reference clock used to compare HFCLK. + * + * @return + * The number of ticks the reference clock after HFCycles ticks on the HF + * clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) +{ + EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set the reference clock source. */ + switch (reference) { + case cmuOsc_LFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + /* Set the top value. */ + CMU->CALCNT = HFCycles; + + /* Start the calibration. */ + CMU->CMD = CMU_CMD_CALSTART; + +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + + return CMU->CALCNT; +} + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +/***************************************************************************//** + * @brief + * Configure the clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required and + * the resulting calibration value can be read out with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run the calibration. Increasing this + * number increases precision but the calibration will take more time. + * + * @param[in] downSel + * The clock, which will be counted down downCycles. + * + * @param[in] upSel + * The reference clock; the number of cycles generated by this clock will + * be counted and added up and the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel) +{ + /* Keep configuration settings untouched. */ + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); + + /* 20 bits of precision to calibration count register. */ + EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set down counting clock source - down counter. */ + switch (downSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Set the top value to be counted down by the downSel clock. */ + CMU->CALCNT = downCycles; + + /* Set the reference clock source - up counter. */ + switch (upSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} +#endif + +/***************************************************************************//** + * @brief + * Get the calibration count register. + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off and only the value needs to be read. In a normal case, + * this function call is triggered by the CALRDY + * interrupt flag. + * @return + * The calibration count, the number of UPSEL clocks + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + /* Wait until calibration completes, UNLESS continuous calibration mode is */ + /* active. */ +#if defined(CMU_CALCTRL_CONT) + if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + } +#else + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Get the clock divisor/prescaler. + * + * @param[in] clock + * A clock point to get the divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference manual. + * + * @return + * The current clock point divisor/prescaler. 1 is returned + * if @p clock specifies a clock point without a divisor/prescaler. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + return 1UL + (uint32_t)CMU_ClockPrescGet(clock); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t divReg; + CMU_ClkDiv_TypeDef ret; + + /* Get divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) + >> _CMU_CTRL_HFCLKDIV_SHIFT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV + & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + + case CMU_HFCORECLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + ret = SL_Log2ToDiv(ret + 1U); + break; +#endif + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16)); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + + return ret; +#endif +} + +/***************************************************************************//** + * @brief + * Set the clock divisor/prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * Clock point to set divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use (<= cmuClkDiv_512). + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t freq; + uint32_t divReg; + + /* Get the divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); + + /* Configure worst case wait states for flash access before setting divisor. */ + flashWaitStateMax(); + + /* Set the divider. */ + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) + | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize flash access wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + /* + This divisor is usually set when changing HF clock to keep HFLE clock + within safe bounds. This code path ignore these constraints. + */ + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div) - 1U; + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + break; +#endif + + case CMU_HFCORECLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + + /* Configure worst case wait states for flash access before setting the divisor. */ + flashWaitStateMax(); + +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet() / div); +#endif + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(freq); +#endif + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (div << _CMU_LFAPRESC0_RTC_SHIFT); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(LCD_PRESENT) + case cmuClock_LCDpre: + EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | ((div - CMU_DivToLog2(cmuClkDiv_16)) + << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif /* defined(LCD_PRESENT) */ + +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif /* defined(LESENSE_PRESENT) */ + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + default: + EFM_ASSERT(false); + break; + } +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * In general, module clocking is disabled after a reset. If a module + * clock is disabled, the registers of that module are not accessible and + * reading from such registers may return undefined values. Writing to + * registers of clock-disabled modules has no effect. + * Avoid accessing module registers of a module with a disabled clock. + * + * @note + * If enabling/disabling an LF clock, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * The clock to enable/disable. Notice that not all defined clock + * points have separate enable/disable control. See the CMU overview + * in the reference manual. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg; + uint32_t bit; + uint32_t sync = 0; + + /* Identify enable register */ + switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { +#if defined(_CMU_CTRL_HFPERCLKEN_MASK) + case CMU_CTRL_EN_REG: + reg = &CMU->CTRL; + break; +#endif + +#if defined(_CMU_HFCORECLKEN0_MASK) + case CMU_HFCORECLKEN0_EN_REG: + reg = &CMU->HFCORECLKEN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + break; +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) + case CMU_HFBUSCLKEN0_EN_REG: + reg = &CMU->HFBUSCLKEN0; + break; +#endif + +#if defined(_CMU_HFPERCLKDIV_MASK) + case CMU_HFPERCLKDIV_EN_REG: + reg = &CMU->HFPERCLKDIV; + break; +#endif + + case CMU_HFPERCLKEN0_EN_REG: + reg = &CMU->HFPERCLKEN0; + break; + +#if defined(_CMU_HFPERCLKEN1_MASK) + case CMU_HFPERCLKEN1_EN_REG: + reg = &CMU->HFPERCLKEN1; + break; +#endif + + case CMU_LFACLKEN0_EN_REG: + reg = &CMU->LFACLKEN0; + sync = CMU_SYNCBUSY_LFACLKEN0; + break; + + case CMU_LFBCLKEN0_EN_REG: + reg = &CMU->LFBCLKEN0; + sync = CMU_SYNCBUSY_LFBCLKEN0; + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case CMU_LFCCLKEN0_EN_REG: + reg = &CMU->LFCCLKEN0; + sync = CMU_SYNCBUSY_LFCCLKEN0; + break; +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + case CMU_LFECLKEN0_EN_REG: + reg = &CMU->LFECLKEN0; + sync = CMU_SYNCBUSY_LFECLKEN0; + break; +#endif + +#if defined(_CMU_SDIOCTRL_MASK) + case CMU_SDIOREF_EN_REG: + reg = &CMU->SDIOCTRL; + enable = !enable; + break; +#endif + +#if defined(_CMU_QSPICTRL_MASK) + case CMU_QSPI0REF_EN_REG: + reg = &CMU->QSPICTRL; + enable = !enable; + break; +#endif +#if defined(_CMU_USBCTRL_MASK) + case CMU_USBRCLK_EN_REG: + reg = &CMU->USBCTRL; + break; +#endif +#if defined(_CMU_PDMCTRL_MASK) + case CMU_PDMREF_EN_REG: + reg = &CMU->PDMCTRL; + break; +#endif + + case CMU_PCNT_EN_REG: + reg = &CMU->PCNTCTRL; + break; + + default: /* Cannot enable/disable a clock point. */ + EFM_ASSERT(false); + return; + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* LF synchronization required. */ + if (sync > 0UL) { + syncReg(sync); + } + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the clock frequency for a clock point. + * + * @param[in] clock + * A clock point to fetch the frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret; + + switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { + case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + break; + + case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPER divider. */ +#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; +#endif +#if defined(_CMU_HFPERPRESC_PRESC_MASK) + ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT); +#endif + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERB prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERC prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#if defined(CRYPTO_PRESENT) \ + || defined(LDMA_PRESENT) \ + || defined(GPCRC_PRESENT) \ + || defined(PRS_PRESENT) \ + || defined(GPIO_PRESENT) + case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); +#if defined(_CMU_HFBUSPRESC_MASK) + ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT); +#endif + break; +#endif + + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT); + break; + + case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(AES_PRESENT) \ + || defined(DMA_PRESENT) \ + || defined(EBI_PRESENT) \ + || defined(USB_PRESENT) + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + { + ret = SystemCoreClockGet(); + } break; +#endif +#endif + + case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + break; + +#if defined(_CMU_LFACLKEN0_RTC_MASK) + case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + break; +#endif + +#if defined(_CMU_LFECLKEN0_RTCC_MASK) + case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER0_MASK) + case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER1_MASK) + case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LCD_MASK) + case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16); +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT); +#endif + break; + +#if defined(_CMU_LCDCTRL_MASK) + case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) + >> _CMU_LCDCTRL_FDIV_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_LFACLKEN0_LESENSE_MASK) + case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + break; +#endif + + case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + break; + +#if defined(_CMU_LFBCLKEN0_LEUART0_MASK) + case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_LEUART1_MASK) + case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_CSEN_MASK) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= SL_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); + break; +#endif + +#if defined(CMU_LFCCLKEN0_USB) + case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFC); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + break; +#endif + + case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = dbgClkGet(); + break; + + case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = auxClkGet(); + break; + +#if defined(USBC_CLOCK_PRESENT) + case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbCClkGet(); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(0); +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(1); +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = sdioRefClkGet(); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = qspiRefClkGet(0); + break; +#endif + +#if defined(USBR_CLOCK_PRESENT) + case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbRateClkGet(); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = pdmRefClkGet(); + break; +#endif + + case (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + ret = SystemCoreClockGet() / CMU_ClockDivGet(clock); +#elif defined(_CMU_HFPRESC_HFCLKLEPRESC_MASK) + ret = SystemHFClockGet() / CMU_ClockDivGet(clock); +#else + ret = SystemCoreClockGet() / 2; +#endif + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Get the clock prescaler. + * + * @param[in] clock + * A clock point to get the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @return + * The prescaler value of the current clock point. 0 is returned + * if @p clock specifies a clock point without a prescaler. + ******************************************************************************/ +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) +{ + uint32_t prescReg; + uint32_t ret; + + /* Get the prescaler register ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT; + break; + + case CMU_HFEXPPRESC_REG: + ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT; + break; + + case CMU_HFCLKLEPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; + ret = SL_Log2ToDiv(ret + 1U) - 1U; + break; + + case CMU_HFPERPRESC_REG: + ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT; + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT; + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT; + break; +#endif + + case CMU_HFCOREPRESC_REG: + ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT; + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCD: + case cmuClock_LCDpre: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_RTC_MASK) + case cmuClock_RTC: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret + 4U) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; +#endif + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; + break; +#endif +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Set the clock prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock point to set the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @param[in] presc + * The clock prescaler. The prescaler value is linked to the clock divider by: + * divider = 'presc' + 1. + ******************************************************************************/ +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) +{ + uint32_t freq; + uint32_t prescReg; + + /* Get the divisor reg ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + EFM_ASSERT(presc < 32U); + + /* Configure worst case wait-states for flash and HFLE, set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); + hfperClkSafePrescaler(); + + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) + | (presc << _CMU_HFPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global + variable). */ + freq = SystemCoreClockGet(); + /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree + prescalers. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + setHfLeConfig(SystemHFClockGet()); + hfperClkOptimizedPrescaler(); + break; + + case CMU_HFEXPPRESC_REG: + EFM_ASSERT(presc < 32U); + + CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) + | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); + break; + + case CMU_HFCLKLEPRESC_REG: + presc = CMU_DivToLog2(presc); + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) + | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); + break; + + case CMU_HFPERPRESC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) + | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) + | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) + | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + + case CMU_HFCOREPRESC_REG: + EFM_ASSERT(presc < 512U); + + /* Configure worst case wait-states for flash. */ + flashWaitStateMax(); + + CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) + | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global variable). + Optimize flash and HFLE wait states. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(RTC_PRESENT) + case cmuClock_RTC: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (presc << _CMU_LFAPRESC0_RTC_SHIFT); + break; +#endif + +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_MASK) +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); +#else + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) + | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + case cmuClock_LCD: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | (presc << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert the prescaler value to a DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4U; + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFEPRESC0_RTCC_MASK) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + break; +#endif + +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); + CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) + | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} +#endif + +/***************************************************************************//** + * @brief + * Get the currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO + * @li #cmuClock_LFC + * @endif @if _SILICON_LABS_32B_SERIES_1 + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT + * @li #cmuClock_USBC + * @endif + * + * @return + * The reference clock used for clocking the selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Disabled; + uint32_t selReg; + + selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selReg) { + case CMU_HFCLKSEL_REG: +#if defined(_CMU_HFCLKSTATUS_MASK) + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { + case CMU_HFCLKSTATUS_SELECTED_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: + ret = cmuSelect_HFRCODIV2; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case CMU_HFCLKSTATUS_SELECTED_CLKIN0: + ret = cmuSelect_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case CMU_HFCLKSTATUS_SELECTED_USHFRCO: + ret = cmuSelect_USHFRCO; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#else + switch (CMU->STATUS + & (CMU_STATUS_HFRCOSEL + | CMU_STATUS_HFXOSEL + | CMU_STATUS_LFRCOSEL +#if defined(CMU_STATUS_USHFRCODIV2SEL) + | CMU_STATUS_USHFRCODIV2SEL +#endif + | CMU_STATUS_LFXOSEL)) { + case CMU_STATUS_LFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_LFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + case CMU_STATUS_HFXOSEL: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_STATUS_USHFRCODIV2SEL) + case CMU_STATUS_USHFRCODIV2SEL: + ret = cmuSelect_USHFRCODIV2; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#endif + break; + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) + case CMU_LFACLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { + case CMU_LFCLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFAE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFACLKSEL_MASK) + switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { + case CMU_LFACLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFACLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFACLKSEL_LFA_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) + case CMU_LFBCLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { + case CMU_LFCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFB_HFCLKLE) + case CMU_LFCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFBE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFBCLKSEL_MASK) + switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { + case CMU_LFBCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFBCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFBCLKSEL_LFB_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + case CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { + case CMU_LFCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_LFECLKSEL_LFE_MASK) + case CMU_LFECLKSEL_REG: + switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { + case CMU_LFECLKSEL_LFE_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFECLKSEL_LFE_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFECLKSEL_LFE_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFECLKSEL_REG */ + +#if defined(_CMU_LFCCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { + case CMU_LFCCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFCCLKSEL_LFC_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFCCLKSEL_REG */ + + case CMU_DBGCLKSEL_REG: +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { + case CMU_DBGCLKSEL_DBG_HFCLK: + ret = cmuSelect_HFCLK; + break; + + case CMU_DBGCLKSEL_DBG_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + +#elif defined(_CMU_CTRL_DBGCLK_MASK) + switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { + case CMU_CTRL_DBGCLK_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_CTRL_DBGCLK_HFCLK: + ret = cmuSelect_HFCLK; + break; + } +#else + ret = cmuSelect_AUXHFRCO; +#endif + break; + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (CMU->STATUS + & (CMU_STATUS_USBCLFXOSEL +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + | CMU_STATUS_USBCHFCLKSEL +#endif +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + | CMU_STATUS_USBCUSHFRCOSEL +#endif + | CMU_STATUS_USBCLFRCOSEL)) { +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + case CMU_STATUS_USBCHFCLKSEL: + ret = cmuSelect_HFCLK; + break; +#endif + +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + case CMU_STATUS_USBCUSHFRCOSEL: + ret = cmuSelect_USHFRCO; + break; +#endif + + case CMU_STATUS_USBCLFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_USBCLFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { + case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { + case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + } + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { + case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { + case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { + case CMU_USBCTRL_USBCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXOX2: + ret = cmuSelect_HFXOX2; + break; + + case CMU_USBCTRL_USBCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFRCO: + ret = cmuSelect_LFRCO; + break; + } + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { + case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + } + break; +#endif + + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc) +{ + if (osc == (uint8_t)cmuOsc_LFXO) { + // Enable LFXO oscillator + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + // Enable LFRCO oscillator + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + } else { + EFM_ASSERT(false); + } + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = SystemHFXOClockGet(); + EMU_VScaleEM01ByClock(vScaleFrequency, false); +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + // Adjust HFXO buffer current for frequencies above 32 MHz. + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + + // Enable HFXO oscillator + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(CMU_HFCLKSEL_HF_HFXO) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + if (((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void) +{ + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void) +{ + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_CLKIN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_USHFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +/***************************************************************************//** + * @brief + * Select the reference clock/oscillator used for a clock branch. + * + * @details + * Notice that if a selected reference is not enabled prior to selecting its + * use, it will be enabled and this function will wait for the selected + * oscillator to be stable. It will however NOT be disabled if another + * reference clock is selected later. + * + * This feature is particularly important if selecting a new reference + * clock for the clock branch clocking the core. Otherwise, the system + * may halt. + * + * @note + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock branch to select reference clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB + * @if _CMU_LFCCLKEN0_MASK + * @li #cmuClock_LFC + * @endif + * @if _CMU_LFECLKEN0_MASK + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG + * @if _CMU_CMD_USBCLKSEL_MASK + * @li #cmuClock_USBC + * @endif + * @if _CMU_USBCTRL_MASK + * @li #cmuClock_USBR + * @endif + * + * @param[in] ref + * A reference selected for clocking. See the reference manual + * for details about references available for a specific clock branch. + * @li #cmuSelect_HFRCO + * @li #cmuSelect_LFRCO + * @li #cmuSelect_HFXO + * @if _CMU_HFXOCTRL_HFXOX2EN_MASK + * @li #cmuSelect_HFXOX2 + * @endif + * @li #cmuSelect_LFXO + * @li #cmuSelect_HFCLKLE + * @li #cmuSelect_AUXHFRCO + * @if _CMU_USHFRCOCTRL_MASK + * @li #cmuSelect_USHFRCO + * @endif + * @li #cmuSelect_HFCLK + * @ifnot DOXYDOC_EFM32_GECKO_FAMILY + * @li #cmuSelect_ULFRCO + * @endif + * @if CMU_OSCENCMD_PLFRCOEN + * @li #cmuSelect_PLFRCO + * @endif + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t select = (uint32_t)cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined(_SILICON_LABS_32B_SERIES_1) + volatile uint32_t *selReg = NULL; +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + uint32_t lfExtended = 0; +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + + /* Start voltage upscaling before the clock is set. */ + if (clock == cmuClock_HF) { + if (ref == cmuSelect_HFXO) { + vScaleFrequency = SystemHFXOClockGet(); + } else if ((ref == cmuSelect_HFRCO) + && ((uint32_t)CMU_HFRCOBandGet() + > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } else { + /* Use the default frequency. */ + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } +#endif + + selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selRegId) { + case CMU_HFCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFXO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFXO; +#endif + osc = cmuOsc_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFRCO; +#endif + osc = cmuOsc_LFRCO; + break; + + case cmuSelect_HFXO: +#if defined(CMU_HFCLKSEL_HF_HFXO) + select = CMU_HFCLKSEL_HF_HFXO; +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + select = CMU_CMD_HFCLKSEL_HFXO; +#endif + osc = cmuOsc_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + /* Adjust HFXO buffer current for frequencies above 32 MHz. */ + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + break; + + case cmuSelect_HFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_HFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_HFRCO; +#endif + osc = cmuOsc_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + break; + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + select = CMU_CMD_HFCLKSEL_USHFRCODIV2; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + select = CMU_HFCLKSEL_HF_HFRCODIV2; + osc = cmuOsc_HFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + select = CMU_HFCLKSEL_HF_CLKIN0; + osc = cmuOsc_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + select = CMU_HFCLKSEL_HF_USHFRCO; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO cannot be used as HFCLK. */ + EFM_ASSERT(false); + return; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + if (osc != cmuOsc_CLKIN0) { + CMU_OscillatorEnable(osc, true, true); + } +#else + CMU_OscillatorEnable(osc, true, true); +#endif + + /* Configure worst case wait-states for flash and set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Wait for voltage upscaling to complete before the clock is set. */ + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + + /* Switch to the selected oscillator. */ +#if defined(_CMU_HFCLKSEL_MASK) + CMU->HFCLKSEL = select; +#else + CMU->CMD = select; +#endif + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + +#if defined(CMU_MAX_FREQ_HFLE) + /* Update the HFLE configuration after 'select' is set. + Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + setHfLeConfig(freq); +#else + setHfLeConfig(SystemHFClockGet()); +#endif +#endif + + /* Optimize flash access wait state setting for the currently selected core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Keep EMU module informed on the source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) + case CMU_LFACLKSEL_REG: + selReg = &CMU->LFACLKSEL; + /* HFCLKCLE can't be used as LFACLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + +#if defined(_CMU_LFCCLKSEL_MASK) + case CMU_LFCCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; + /* HFCLKCLE can't be used as LFCCLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH +#endif + /* Fall through and select the clock source. */ + + case CMU_LFECLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; + /* HFCLKCLE can't be used as LFECLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + + case CMU_LFBCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFACLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: + /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ + setHfLeConfig(SystemHFClockGet()); + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; + break; + + case cmuSelect_ULFRCO: + /* ULFRCO is always on, there is no need to enable it. */ + tmp = _CMU_LFACLKSEL_LFA_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + *selReg = tmp; + break; + +#elif defined(_SILICON_LABS_32B_SERIES_0) + case CMU_LFACLKSEL_REG: + case CMU_LFBCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: +#if defined(CMU_MAX_FREQ_HFLE) + /* Set the HFLE wait-state and divider. */ + freq = SystemCoreClockGet(); + setHfLeConfig(freq); +#endif + /* Ensure HFCORE to LE clocking is enabled. */ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; + break; + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO is always enabled. */ + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + lfExtended = 1; + break; +#endif + + default: + /* An illegal clock source for LFA/LFB selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + if (selRegId == CMU_LFACLKSEL_REG) { +#if defined(_CMU_LFCLKSEL_LFAE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); +#endif + } else { +#if defined(_CMU_LFCLKSEL_LFBE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); +#endif + } + break; + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFRCO; + break; + + default: + /* An illegal clock source for LFC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) + | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) + case CMU_DBGCLKSEL_REG: + switch (ref) { +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; + break; +#endif + +#if defined(CMU_CTRL_DBGCLK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_HFCLK; + break; +#endif + + default: + /* An illegal clock source for debug selected. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: + /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { + } + break; + + case cmuSelect_LFRCO: + /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { + } + break; + +#if defined(CMU_STATUS_USBCHFCLKSEL) + case cmuSelect_HFCLK: + /* Select undivided HFCLK as a clock source for USB. */ + /* The oscillator must already be enabled to avoid a core lockup. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { + } + break; +#endif + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) + case cmuSelect_USHFRCO: + /* Select USHFRCO as a clock source for USB. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { + } + break; +#endif + + default: + /* An illegal clock source for USB. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC0ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC1ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for SDIOREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for QSPI0REF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; + break; + + case cmuSelect_HFXOX2: + /* Only allowed for HFXO frequencies up to 25 MHz. */ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); + + /* Enable HFXO X2. */ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; + break; + + default: + /* An illegal clock source for USBR selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) + | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; + break; + + default: + /* An illegal clock source for PDMREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) + | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + precision = 500; + break; +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCO: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to + * calling this function to avoid over-clocking. + * + * HFCLKLE prescaler is automatically modified before updating HFRCO + * based on the maximum HFLE frequency allowed. + * + * @param[in] init + * DPLL setup parameters. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hfrcoDiv2override = false; + uint32_t hfrcoCtrlVal, lockStatus, sysFreq; + + EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); + EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); + EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK + >> _CMU_HFRCOSS_SSINV_SHIFT)); + EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK + >> _CMU_HFRCOSS_SSAMP_SHIFT)); + +#if defined(_EMU_STATUS_VSCALE_MASK) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find the correct HFRCO band and retrieve a HFRCOCTRL value. + for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCtrlTable[i].minFreq) + && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCtrlVal = hfrcoCtrlTable[index].value; + + // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. + if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) + & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + + // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency + // of the band shifts down by 5.8%. 9 is subtracted to compensate. + if (tuning > 9UL) { + tuning -= 9UL; + } else { + tuning = 0UL; + } + + hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; + } + + // Update the CMSIS frequency SystemHfrcoFreq value. + SystemHfrcoFreq = init->frequency; + + // Set maximum wait-states while changing the core clock. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + } + + // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + setHfLeConfig(init->frequency); + + // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. + hfrcoDiv2override = true; + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; + } + + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; + while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { + } + CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW + | CMU_IFC_DPLLLOCKFAILHIGH; + CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) + | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); + CMU->HFRCOCTRL = hfrcoCtrlVal; + CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) + | ((init->autoRecover ? 1UL : 0UL) + << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) + | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); + CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; + while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY + | CMU_IF_DPLLLOCKFAILLOW + | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { + } + + // Restore to HFRCO + if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) + && (hfrcoDiv2override == true)) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + } + + // If HFRCO is selected as an HF clock, optimize the flash access wait-state + // configuration for this frequency and update the CMSIS core clock variable. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT(init->frequency == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + // Reduce HFLE frequency if possible. + setHfLeConfig(SystemHFClockGet()); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(0, true); +#endif + + if (lockStatus == CMU_IF_DPLLRDY) { + return true; + } + return false; +} +#endif // CMU_OSCENCMD_DPLLEN + +/**************************************************************************//** + * @brief + * CMU low frequency register synchronization freeze control. + * + * @details + * Some CMU registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * Another use case for this feature is using an API (such + * as the CMU API) for modifying several bit fields consecutively in the + * same register. If freeze mode is enabled during this sequence, stalling + * can be avoided. + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing CMU synchronization to LF domain to complete (normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring LF synchronization + * should be done within one freeze enable/disable block to avoid unnecessary + * stalling. + * + * @param[in] enable + * @li true - enable freeze, modified registers are not propagated to the + * LF domain + * @li false - disable freeze, modified registers are propagated to the LF + * domain + *****************************************************************************/ +void CMU_FreezeEnable(bool enable) +{ + if (enable) { + /* Wait for any ongoing LF synchronizations to complete. This */ + /* protects against the rare case when a user */ + /* - modifies a register requiring LF sync */ + /* - then enables freeze before LF sync completed */ + /* - then modifies the same register again */ + /* since modifying a register while it is in sync progress should be */ + /* avoided. */ + while (CMU->SYNCBUSY != 0UL) { + } + + CMU->FREEZE = CMU_FREEZE_REGFREEZE; + } else { + CMU->FREEZE = 0; + } +} + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get HFRCO band in use. + * + * @return + * HFRCO band in use. + ******************************************************************************/ +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) + >> _CMU_HFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set HFRCO band and the tuning value based on the value in the calibration + * table made during production. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] band + * HFRCO band to activate. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t freq; + CMU_Select_TypeDef osc; + + /* Read the tuning value from the calibration table. */ + switch (band) { + case cmuHFRCOBand_1MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) + >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; + break; + + case cmuHFRCOBand_7MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) + >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; + break; + + case cmuHFRCOBand_11MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) + >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; + break; + + case cmuHFRCOBand_14MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) + >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; + break; + + case cmuHFRCOBand_21MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) + >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_HFRCOCTRL_BAND_28MHZ) + case cmuHFRCOBand_28MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) + >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* If HFRCO is used for the core clock, flash access WS has to be considered. */ + osc = CMU_ClockSelectGet(cmuClock_HF); + if (osc == cmuSelect_HFRCO) { + /* Configure worst case wait states for flash access before setting the divider. */ + flashWaitStateMax(); + } + + /* Set band/tuning. */ + CMU->HFRCOCTRL = (CMU->HFRCOCTRL + & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) + | (band << _CMU_HFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); + + /* If HFRCO is used for the core clock, optimize flash WS. */ + if (osc == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + } + +#if defined(CMU_MAX_FREQ_HFLE) + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemCoreClockGet()); +#endif +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the HFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * HFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuHFRCOFreq_1M0Hz: + case cmuHFRCOFreq_2M0Hz: + case cmuHFRCOFreq_4M0Hz: + return DEVINFO->HFRCOCAL0; + + case cmuHFRCOFreq_7M0Hz: + return DEVINFO->HFRCOCAL3; + + case cmuHFRCOFreq_13M0Hz: + return DEVINFO->HFRCOCAL6; + + case cmuHFRCOFreq_16M0Hz: + return DEVINFO->HFRCOCAL7; + + case cmuHFRCOFreq_19M0Hz: + return DEVINFO->HFRCOCAL8; + + case cmuHFRCOFreq_26M0Hz: + return DEVINFO->HFRCOCAL10; + + case cmuHFRCOFreq_32M0Hz: + return DEVINFO->HFRCOCAL11; + + case cmuHFRCOFreq_38M0Hz: + return DEVINFO->HFRCOCAL12; + +#if defined(_DEVINFO_HFRCOCAL13_MASK) + case cmuHFRCOFreq_48M0Hz: + return DEVINFO->HFRCOCAL13; +#endif + +#if defined(_DEVINFO_HFRCOCAL14_MASK) + case cmuHFRCOFreq_56M0Hz: + return DEVINFO->HFRCOCAL14; +#endif + +#if defined(_DEVINFO_HFRCOCAL15_MASK) + case cmuHFRCOFreq_64M0Hz: + return DEVINFO->HFRCOCAL15; +#endif + +#if defined(_DEVINFO_HFRCOCAL16_MASK) + case cmuHFRCOFreq_72M0Hz: + return DEVINFO->HFRCOCAL16; +#endif + + default: /* cmuHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current HFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO calibration for the selected target frequency. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] setFreq + * HFRCO frequency to set. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + uint32_t sysFreq; + uint32_t prevFreq; + + /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ + freqCal = CMU_HFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + prevFreq = SystemHfrcoFreq; + SystemHfrcoFreq = (uint32_t)setFreq; + + /* Set maximum wait-states and set safe HFPER clock-tree prescalers while + changing the core clock. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + hfperClkSafePrescaler(); + } + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } + + /* Check for valid calibration data. */ + EFM_ASSERT(freqCal != UINT_MAX); + + /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + + /* Update HFLE configuration before updating HFRCO. + Use the new set frequency. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ + setHfLeConfig((uint32_t)setFreq); + } + + if ((uint32_t)setFreq > prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)setFreq, true); +#endif + } + + CMU->HFRCOCTRL = freqCal; + + /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration + for this frequency and update the CMSIS core clock variable. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)setFreq); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemHFClockGet()); + + if ((uint32_t)setFreq <= prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When decreasing frequency voltage scale must be done after the change */ + EMU_VScaleEM01ByClock(0, true); +#endif + } + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + } +} +#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +/***************************************************************************//** + * @brief + * Get the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @return + * The startup delay in use. + ******************************************************************************/ +uint32_t CMU_HFRCOStartupDelayGet(void) +{ + return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) + >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @param[in] delay + * The startup delay to set (<= 31). + ******************************************************************************/ +void CMU_HFRCOStartupDelaySet(uint32_t delay) +{ + EFM_ASSERT(delay <= 31); + + delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) + | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); +} +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the USHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * USHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) +{ + switch (freq) { + case cmuUSHFRCOFreq_16M0Hz: + return DEVINFO->USHFRCOCAL7; + + case cmuUSHFRCOFreq_32M0Hz: + return DEVINFO->USHFRCOCAL11; + + case cmuUSHFRCOFreq_48M0Hz: + return DEVINFO->USHFRCOCAL13; + + case cmuUSHFRCOFreq_50M0Hz: + return DEVINFO->USHFRCOCAL14; + + default: /* cmuUSHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current USHFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the USHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * USHFRCO frequency to set. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO calibration values. */ + freqCal = CMU_USHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); + ushfrcoFreq = (uint32_t)setFreq; + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; + + CMU->USHFRCOCTRL = freqCal; +} +#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +/***************************************************************************//** + * @brief + * Enable or disable HFXO autostart. + * + * @param[in] userSel + * Additional user specified enable bit. + * + * @param[in] enEM0EM1Start + * If true, HFXO is automatically started upon entering EM0/EM1 entry from + * EM2/EM3. HFXO selection has to be handled by the user. + * If false, HFXO is not started automatically when entering EM0/EM1. + * + * @param[in] enEM0EM1StartSel + * If true, HFXO is automatically started and immediately selected upon + * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of + * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically + * modified if userSel is specified. + * If false, HFXO is not started or selected automatically when entering + * EM0/EM1. + ******************************************************************************/ +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel) +{ + uint32_t hfxoFreq; + uint32_t hfxoCtrl; + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) + if (enEM0EM1StartSel) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); + } +#endif + + /* Mask supported enable bits. */ +#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) + userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; +#else + userSel = 0; +#endif + + hfxoFreq = SystemHFXOClockGet(); +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(hfxoFreq, true); +#endif + /* Set wait-states for HFXO if automatic start and select is configured. */ + if ((userSel > 0UL) || enEM0EM1StartSel) { + CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT); + setHfLeConfig(hfxoFreq / CMU_ClockDivGet(cmuClock_HF)); + } + + if (enEM0EM1Start || enEM0EM1StartSel) { + /* Enable the HFXO once in order to finish first time calibrations. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + } + + /* Since call to CMU_OscillatorEnable() can change the CMU->HFXOCTRL register, + * it's important to read the CMU->HFXOCTRL register after the call to CMU_OscillatorEnable(). */ + hfxoCtrl = CMU->HFXOCTRL & ~(userSel + | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK + | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); + + hfxoCtrl |= userSel + | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) + | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; +} +#endif + +/**************************************************************************//** + * @brief + * Set HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the HFXO to + * ensure a valid state before update. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + + /* HFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + switch (hfxoInit->mode) { + case cmuOscMode_Crystal: + tmp = CMU_HFXOCTRL_MODE_XTAL; + break; + case cmuOscMode_External: + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + break; + case cmuOscMode_AcCoupled: + tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; + break; + default: + EFM_ASSERT(false); /* Unsupported configuration */ + break; + } + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; + +#if defined(CMU_HFXOCTRL_HFXOX2EN) + /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ + tmp = 0; + if (SystemHFXOClockGet() <= 25000000) { + tmp |= CMU_HFXOCTRL_HFXOX2EN; + } + + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; +#endif + + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) + | (hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); + + /* Set timeouts */ + CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | (hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | (hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); + +#elif defined(_CMU_HFXOCTRL_MASK) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + /* AC coupled external clock not supported. */ + EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); + if (hfxoInit->mode == cmuOscMode_External) { + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + } + + /* Apply control settings. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) + | tmp; + BUS_RegBitWrite(&CMU->HFXOCTRL, + _CMU_HFXOCTRL_LOWPOWER_SHIFT, + (unsigned)hfxoInit->lowPowerMode); + + /* Set XTAL tuning parameters. */ + +#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + /* Set peak detection threshold. */ + CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + | (hfxoInit->thresholdPeakDetect + << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); +#endif + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | ((uint32_t)hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) + | ((uint32_t)hfxoInit->regIshSteadyState + << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) + | getRegIshUpperVal(hfxoInit->regIshSteadyState); + + /* Set timeouts. */ + CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutShuntOptimization + << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); + +#else + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK + | _CMU_CTRL_HFXOBOOST_MASK + | _CMU_CTRL_HFXOMODE_MASK + | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) + | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) + | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) + | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) + | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); +#endif +} + +/***************************************************************************//** + * @brief + * Get the LCD framerate divisor (FDIV) setting. + * + * @return + * The LCD framerate divisor. + ******************************************************************************/ +uint32_t CMU_LCDClkFDIVGet(void) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; +#else + return 0; +#endif /* defined(LCD_PRESENT) */ +} + +/***************************************************************************//** + * @brief + * Set the LCD framerate divisor (FDIV) setting. + * + * @note + * The FDIV field (CMU LCDCTRL register) should only be modified while the + * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function + * will NOT modify FDIV if the LCD module clock is enabled. See + * @ref CMU_ClockEnable() for disabling/enabling LCD clock. + * + * @param[in] div + * The FDIV setting to use. + ******************************************************************************/ +void CMU_LCDClkFDIVSet(uint32_t div) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + EFM_ASSERT(div <= cmuClkDiv_128); + + /* Do not allow modification if LCD clock enabled. */ + if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { + return; + } + + div <<= _CMU_LCDCTRL_FDIV_SHIFT; + div &= _CMU_LCDCTRL_FDIV_MASK; + CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; +#else + (void)div; /* Unused parameter. */ +#endif /* defined(LCD_PRESENT) */ +} + +/**************************************************************************//** + * @brief + * Set LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the LFXO when + * necessary to ensure a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters. + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); + +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK + | _CMU_LFXOCTRL_GAIN_MASK + | _CMU_LFXOCTRL_TIMEOUT_MASK + | _CMU_LFXOCTRL_MODE_MASK)) + | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) + | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) + | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); + + /* If LFXO already contains the correct configuration then there is no need + * to stop the oscillator and apply new settings. The LFXO can be running out + * of reset, in which case there is no need to disable it unless necessary. */ + if (reg != CMU->LFXOCTRL) { + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + CMU->LFXOCTRL = reg; + } +#elif defined(_SILICON_LABS_32B_SERIES_0) + /* LFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + + bool cmuBoost = (lfxoInit->boost & 0x2); + BUS_RegMaskedWrite(&CMU->CTRL, + _CMU_CTRL_LFXOTIMEOUT_MASK + | _CMU_CTRL_LFXOBOOST_MASK + | _CMU_CTRL_LFXOMODE_MASK, + ((uint32_t)lfxoInit->timeout + << _CMU_CTRL_LFXOTIMEOUT_SHIFT) + | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + /* EFM32GG has a "reduce startup boost" field in the EMU */ + bool emuReduce = (lfxoInit->boost & 0x1); + BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); +#endif +#endif +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * WARNING: When this function is called to disable either cmuOsc_LFXO or + * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register + * are reset to the reset value. In other words, if external clock sources are selected + * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared + * and needs to be reconfigured if needed later. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) +{ + uint32_t rdyBitPos; +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t ensBitPos; +#endif +#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) + uint32_t hfxoTrimStatus; +#endif + + uint32_t enBit; + uint32_t disBit; + + switch (osc) { + case cmuOsc_HFRCO: + enBit = CMU_OSCENCMD_HFRCOEN; + disBit = CMU_OSCENCMD_HFRCODIS; + rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_HFXO: + enBit = CMU_OSCENCMD_HFXOEN; + disBit = CMU_OSCENCMD_HFXODIS; + rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; +#endif + break; + + case cmuOsc_AUXHFRCO: + enBit = CMU_OSCENCMD_AUXHFRCOEN; + disBit = CMU_OSCENCMD_AUXHFRCODIS; + rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFRCO: + enBit = CMU_OSCENCMD_LFRCOEN; + disBit = CMU_OSCENCMD_LFRCODIS; + rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFXO: + enBit = CMU_OSCENCMD_LFXOEN; + disBit = CMU_OSCENCMD_LFXODIS; + rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; +#endif + break; + +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + case cmuOsc_USHFRCO: + enBit = CMU_OSCENCMD_USHFRCOEN; + disBit = CMU_OSCENCMD_USHFRCODIS; + rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; +#endif + break; +#endif + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + if (!deviceHasPlfrco()) { + while (true) { // PLFRCO is not available + EFM_ASSERT(false); + } + } + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + + default: + /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled + and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily + intended for information: the ULFRCO is always on. */ + EFM_ASSERT(false); + return; + } + + if (enable) { + #if defined(_CMU_HFXOCTRL_MASK) + bool firstHfxoEnable = false; + + /* Enabling the HFXO for the first time requires special handling. + * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the + * first time the HFXO is enabled. */ + if (osc == cmuOsc_HFXO) { + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); +#endif + + firstHfxoEnable = true; + /* The first time that an external clock is enabled, switch to CMD mode to make sure that + * only SCO and not PDA tuning is performed. */ + if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { + setHfxoTuningMode(HFXO_TUNING_MODE_CMD); + } + } + } +#endif + CMU->OSCENCMD = enBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go high. */ + while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { + } +#endif + + /* Wait for the clock to become ready after enable. */ + if (wait) { + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } +#if defined(_SILICON_LABS_32B_SERIES_1) + if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { + if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) + == CMU_HFXOCTRL_MODE_DIGEXTCLK) { +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + /* External clock mode should only do shunt current optimization. */ + (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, + cmuHFXOTuningMode_ShuntCommand, + true); +#endif + } else { + /* Wait for the peak detection and shunt current optimization + to complete. */ + (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); + } + + /* Disable the HFXO again to apply the trims. Apply trim from + HFXOTRIMSTATUS when disabled. */ + hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); + + /* Restart in CMD mode. */ + CMU->OSCENCMD = enBit; + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } + } +#endif + } + } else { + CMU->OSCENCMD = disBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go low. */ + while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { + } + + if (wait) { + /* Wait for RDY to go low as well. */ + while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { + } + } +#endif + } +} + +/***************************************************************************//** + * @brief + * Get the oscillator frequency tuning setting. + * + * @param[in] osc + * An oscillator to get tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret; + + switch (osc) { + case cmuOsc_LFRCO: + ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) + >> _CMU_LFRCOCTRL_TUNING_SHIFT; + break; + + case cmuOsc_HFRCO: + ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) + >> _CMU_USHFRCOCTRL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_AUXHFRCO: + ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK +#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) + | _CMU_HFXOTRIMSTATUS_REGISH_MASK +#endif + ); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + ret = (CMU->LFXOCTRL & _CMU_LFXOCTRL_TUNING_MASK) >> _CMU_LFXOCTRL_TUNING_SHIFT; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production and the tuning value is + * automatically loaded after reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + uint8_t ctune = 0; +#endif + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + uint32_t regIshUpper; +#endif + + switch (osc) { + case cmuOsc_LFRCO: + EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK + >> _CMU_LFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) + | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); + break; + + case cmuOsc_HFRCO: + EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK + >> _CMU_HFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) + | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK + >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { + } +#endif + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_AUXHFRCO: + EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + + /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ + EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); + + /* Switch to command mode. Automatic SCO and PDA calibration is not done + at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | val + | regIshUpper; +#else + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) + | val; +#endif + + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + EFM_ASSERT(val <= (_CMU_LFXOCTRL_TUNING_MASK >> _CMU_LFXOCTRL_TUNING_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for the CMU_LFXOCTRL is ready for update + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFXOBSY_SHIFT) != 0UL) { + } + CMU->LFXOCTRL = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK)) + | ((uint32_t)ctune << _CMU_LFXOCTRL_TUNING_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/***************************************************************************//** + * @brief + * Wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode) +{ + uint32_t waitFlags; + EFM_ASSERT(osc == cmuOsc_HFXO); + + /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ + (void)osc; + + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + waitFlags = HFXO_TUNING_READY_FLAGS; + } else { + /* Set wait flags for each command and wait. */ + switch (mode) { +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) + case cmuHFXOTuningMode_ShuntCommand: + waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; + break; +#endif + case cmuHFXOTuningMode_Auto: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; + +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + case cmuHFXOTuningMode_PeakShuntCommand: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; +#endif + + default: + waitFlags = _CMU_STATUS_MASK; + EFM_ASSERT(false); + break; + } + } + while ((CMU->STATUS & waitFlags) != waitFlags) { + } + +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Check error flags. */ + if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { + return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Start and optionally wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @param[in] wait + * Wait for tuning optimization to complete. + * true - wait for tuning optimization to complete. + * false - return without waiting. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait) +{ + switch (osc) { + case cmuOsc_HFXO: + if ((unsigned)mode != 0U) { +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Clear the error flag before command write. */ + CMU->IFC = CMU_IFC_HFXOPEAKDETERR; +#endif + CMU->CMD = (uint32_t)mode; + } + if (wait) { + return CMU_OscillatorTuningWait(osc, mode); + } + break; + + default: + EFM_ASSERT(false); + break; + } + return true; +} +#endif + +/**************************************************************************//** + * @brief + * Determine if the currently selected PCNTn clock used is external or LFBCLK. + * + * @param[in] instance + * PCNT instance number to get currently selected clock source for. + * + * @return + * @li true - selected clock is external clock. + * @li false - selected clock is LFBCLK. + *****************************************************************************/ +bool CMU_PCNTClockExternalGet(unsigned int instance) +{ + uint32_t setting; + + switch (instance) { +#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) + case 0: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) + case 1: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) + case 2: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; + break; +#endif +#endif +#endif + + default: + setting = 0; + break; + } + return setting > 0UL ? true : false; +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select LFBCLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ +#if defined(PCNT_PRESENT) + uint32_t setting = 0; + + EFM_ASSERT(instance < (unsigned)PCNT_COUNT); + + if (external) { + setting = 1; + } + + BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); + +#else + (void)instance; /* An unused parameter */ + (void)external; /* An unused parameter */ +#endif +} + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Get USHFRCO band in use. + * + * @return + * USHFRCO band in use. + ******************************************************************************/ +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF + & _CMU_USHFRCOCONF_BAND_MASK) + >> _CMU_USHFRCOCONF_BAND_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the USHFRCO band to use. + * + * @param[in] band + * USHFRCO band to activate. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t fineTuning; + + /* Cannot switch band if USHFRCO is already selected as HF clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCODIV2); + + /* Read tuning value from calibration table. */ + switch (band) { + case cmuUSHFRCOBand_24MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; + ushfrcoFreq = 24000000UL; + break; + + case cmuUSHFRCOBand_48MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; + /* Enable the clock divider before switching the band from 24 to 48 MHz */ + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); + ushfrcoFreq = 48000000UL; + break; + + default: + EFM_ASSERT(false); + return; + } + + /* Set band and tuning. */ + CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) + | (band << _CMU_USHFRCOCONF_BAND_SHIFT); + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) + | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); + CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) + | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); + + /* Disable the clock divider after switching the band from 48 to 24 MHz. */ + if (band == cmuUSHFRCOBand_24MHz) { + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); + } +} +#endif + +#endif // defined(_SILICON_LABS_32B_SERIES_2) +/** @} (end addtogroup cmu) */ +#endif /* defined(CMU_PRESENT) */ diff --git a/Libs/platform/emlib/src/em_core.c b/Libs/platform/emlib/src/em_core.c new file mode 100644 index 0000000..4bc5ae9 --- /dev/null +++ b/Libs/platform/emlib/src/em_core.c @@ -0,0 +1,518 @@ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_core.h" +#include "sl_assert.h" + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup core CORE - Interrupt Handling +/// +/// +/// @warning +/// If you are looking for atomic and critical sections, they have been moved +/// to platform/common in the Core API. +/// +/// @section core_intro Introduction +/// +/// This module provides support for NVIC sections. NVIC sections are like +/// critical sections, except interrupts are masked on an individual IRQ basis. +/// This module also provides an API to relocate the vector table in RAM, and +/// register IRQ handlers in the RAM based interrupt vector table. +/// +/// @li NVIC mask section: Mask interrupts (external interrupts) on an +/// individual IRQ basis. +/// +/// @section core_examples Examples +/// +/// Implement an NVIC critical section: +/// @code{.c} +/// { +/// CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask +/// +/// // Set mask bits for IRQs to block in the NVIC critical section. +/// // In many cases, you can create the disable mask once upon application +/// // startup and use the mask globally throughout the application lifetime. +/// CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); +/// CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); +/// +/// // Enter NVIC critical section with the disable mask +/// CORE_NVIC_SECTION(&mask, +/// ... +/// ... your code goes here ... +/// ... +/// ) +/// } +/// @endcode +/// +/// @section core_vector_tables Interrupt vector tables +/// +/// When using RAM based interrupt vector tables it is the user's responsibility +/// to allocate the table space correctly. The tables must be aligned as specified +/// in the CPU reference manual. +/// +/// Use @ref CORE_InitNvicVectorTable() to initialize a RAM based vector table +/// by copying table entries from a source vector table to a target table. +/// VTOR is set to the address of the target vector table. +/// +/// Use @ref CORE_GetNvicRamTableHandler() @ref CORE_SetNvicRamTableHandler() +/// to get or set the interrupt handler for a specific IRQn. They both use +/// the interrupt vector table defined by the current VTOR register value. +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enter a NVIC mask section. + * + * When a NVIC mask section is entered, specified NVIC interrupts + * are disabled. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[out] nvicState + * Return NVIC interrupts enable mask prior to section entry. + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable within the section. + ******************************************************************************/ +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Disable NVIC interrupts. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable. + ******************************************************************************/ +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Set current NVIC interrupt enable mask. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[out] enable + * A mask specifying which NVIC interrupts are currently enabled. + ******************************************************************************/ +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; + ) +} + +/***************************************************************************//** + * @brief + * Brief NVIC interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[in] enable + * A mask specifying which NVIC interrupts to briefly enable. + * + * @note + * Usually used within an NVIC mask section. + ******************************************************************************/ +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) +{ + CORE_nvicMask_t nvicMask; + + // Get current NVIC enable mask. + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + + // Make a mask with bits set for those interrupts that are currently + // disabled but are set in the enable mask. +#if (CORE_NVIC_REG_WORDS == 1) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + + if (nvicMask.a[0] != 0) { +#elif (CORE_NVIC_REG_WORDS == 2) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { +#elif (CORE_NVIC_REG_WORDS == 3) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[2] &= enable->a[2]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U) || (nvicMask.a[2] != 0U)) { +#endif + + // Enable previously disabled interrupts. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; + + // Disable those interrupts again. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; + } +} + +/***************************************************************************//** + * @brief + * Utility function to set an IRQn bit in a NVIC enable/disable mask. + * + * @deprecated Will be removed from the Simplicity SDK + * Use sl_interrupt_manager_enable from the interrupt_manager service to replace + * the calls to this API. Note that each interrupts will need to be enabled + * individually instead of using a mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to set the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Utility function to clear an IRQn bit in a NVIC enable/disable mask. + * + * @deprecated Will be removed from the Simplicity SDK + * Use sl_interrupt_manager_enable from the interrupt_manager service to replace + * the calls to this API. Note that each interrupts will need to be disabled + * individually instead of using a mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to clear the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); +} + +/***************************************************************************//** + * @brief + * Get the current NVIC enable mask state. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[out] mask + * The current NVIC enable mask. + ******************************************************************************/ +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) +{ + CORE_CRITICAL_SECTION( + *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) +} + +/***************************************************************************//** + * @brief + * Get NVIC disable state for a given mask. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[in] mask + * An NVIC mask to check. + * + * @return + * True if all NVIC interrupt mask bits are clear. + ******************************************************************************/ +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) +{ + CORE_nvicMask_t nvicMask; + + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + +#if (CORE_NVIC_REG_WORDS == 1) + return (mask->a[0] & nvicMask.a[0]) == 0U; + +#elif (CORE_NVIC_REG_WORDS == 2) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U); + +#elif (CORE_NVIC_REG_WORDS == 3) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U) + && ((mask->a[2] & nvicMask.a[2]) == 0U); +#endif +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/***************************************************************************//** + * @brief Internal function to query the state an IRQ. Present for compatibility + * during the deprecation process. + * + * @param[in] irqN IRQ number. + * + * @return True of False depending on if the IRQ is active in the NVIC or not. + ******************************************************************************/ +__STATIC_INLINE bool internal_NvicIRQDisabled(IRQn_Type irqN) +{ + CORE_nvicMask_t *mask; + + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) + == 0UL; +} +/** @endcond */ + +/***************************************************************************//** + * @brief + * Check if an NVIC interrupt is disabled. + * + * @deprecated Will be removed from the Simplicity SDK, please now use the + * function sl_interrupt_manager_is_irq_disabled in the interrupt manager + * service component. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled. + ******************************************************************************/ +bool CORE_NvicIRQDisabled(IRQn_Type irqN) +{ + return internal_NvicIRQDisabled(irqN); +} + +/***************************************************************************//** + * @brief + * Utility function to get the handler for a specific interrupt. + * + * @deprecated Will be removed from the Simplicity SDK + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @return + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); +} + +/***************************************************************************//** + * @brief + * Utility function to set the handler for a specific interrupt. + * + * @deprecated Will be removed from the Simplicity SDK, please now use the + * function sl_interrupt_manager_set_irq_handler in the interrupt manager + * service component. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in] handler + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); +} + +/***************************************************************************//** + * @brief + * Initialize an interrupt vector table by copying table entries from a + * source to a target table. + * + * @note This function will set a new VTOR register value. + * + * @param[in] sourceTable + * The address of the source vector table. + * + * @param[in] sourceSize + * A number of entries in the source vector table. + * + * @param[in] targetTable + * The address of the target (new) vector table. + * + * @param[in] targetSize + * A number of entries in the target vector table. + * + * @param[in] defaultHandler + * An address of the interrupt handler used for target entries for which where there + * is no corresponding source entry (i.e., the target table is larger than the source + * table). + * + * @param[in] overwriteActive + * When true, a target table entry is always overwritten with the + * corresponding source entry. If false, a target table entry is only + * overwritten if it is zero. This makes it possible for an application + * to partly initialize a target table before passing it to this function. + * + ******************************************************************************/ +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive) +{ + uint32_t i; + + // ASSERT on non SRAM-based target table. + EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) + && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); + + // ASSERT if misaligned with respect to the VTOR register implementation. +#if defined(SCB_VTOR_TBLBASE_Msk) + EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk + | SCB_VTOR_TBLBASE_Msk)) == 0U); +#else + EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); +#endif + + // ASSERT if misaligned with respect to the vector table size. + // The vector table address must be aligned at its size rounded up to nearest 2^n. + EFM_ASSERT(((uint32_t)targetTable + & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) + == 0UL); + + for (i = 0; i < targetSize; i++) { + if (overwriteActive) { // Overwrite target entries. + if (i < sourceSize) { // targetSize <= sourceSize + targetTable[i] = sourceTable[i]; + } else { // targetSize > sourceSize + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } else { // Overwrite target entries which are 0. + if (i < sourceSize) { // targetSize <= sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = sourceTable[i]; + } + } else { // targetSize > sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } + } + } + SCB->VTOR = (uint32_t)targetTable; +} + +/***************************************************************************//** + * @brief + * Check if a specific interrupt is disabled or blocked. + * + * @deprecated Will be removed from the Simplicity SDK, please now use the + * function sl_interrupt_manager_is_irq_blocked in the interrupt manager + * service component. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled or blocked. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) +{ + uint32_t irqPri, activeIrq; + +#if (__CORTEX_M >= 3) + uint32_t basepri; + + EFM_ASSERT((irqN >= MemoryManagement_IRQn) + && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); +#else + EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); +#endif + + if ((__get_PRIMASK() & 1U) != 0U) { + return true; // All IRQs are disabled. + } + + if (internal_NvicIRQDisabled(irqN)) { + return true; // The IRQ in question is disabled. + } + + irqPri = NVIC_GetPriority(irqN); +#if (__CORTEX_M >= 3) + basepri = __get_BASEPRI(); + if ((basepri != 0U) + && (irqPri >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { + return true; // The IRQ in question has too low + } // priority vs. BASEPRI. +#endif + + // Check if already in an interrupt handler. If so, an interrupt with a + // higher priority (lower priority value) can preempt. + activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; + if (activeIrq != 0U) { + if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { + return true; // The IRQ in question has too low + } // priority vs. current active IRQ + } + + return false; +} + +/** @} (end addtogroup core) */ diff --git a/Libs/platform/emlib/src/em_dbg.c b/Libs/platform/emlib/src/em_dbg.c new file mode 100644 index 0000000..99ab543 --- /dev/null +++ b/Libs/platform/emlib/src/em_dbg.c @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file + * @brief Debug (DBG) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_dbg.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "em_gpio.h" +#include "em_msc.h" + +/***************************************************************************//** + * @addtogroup dbg DBG - Debug + * @brief Debug (DBG) Peripheral API + * @details + * This module contains functions to control the DBG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The Debug Interface is used to program and debug + * Silicon Labs devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +/***************************************************************************//** + * @brief + * Enable Serial Wire Output (SWO) pin. + * + * @details + * The SWO pin (sometimes denoted SWV, serial wire viewer) allows for + * miscellaneous output to be passed from the Cortex-M3 debug trace module to + * an external debug probe. By default, the debug trace module and pin output + * may be disabled. + * + * Since the SWO pin is only useful when using a debugger, a suggested use + * of this function during startup may be: + * @verbatim + * if (DBG_Connected()) + * { + * DBG_SWOEnable(1); + * } + * @endverbatim + * By checking if the debugger is attached, a setup leading to a higher energy + * consumption when the debugger is attached can be avoided when not using + * a debugger. + * + * Another alternative may be to set the debugger tool chain to configure + * the required setup (similar to the content of this function) by some + * sort of toolchain scripting during its attach/reset procedure. In that + * case, the above suggested code for enabling the SWO pin is not required + * in the application. + * + * @param[in] location + * A pin location used for SWO pin on the application in use. + ******************************************************************************/ +void DBG_SWOEnable(unsigned int location) +{ + int port; + int pin; + +#if defined(GPIO_SWV_PORT) + + port = GPIO_SWV_PORT; + pin = GPIO_SWV_PIN; + +#else + EFM_ASSERT(location < AFCHANLOC_MAX); + #if defined (AF_DBG_SWO_PORT) + port = AF_DBG_SWO_PORT(location); + pin = AF_DBG_SWO_PIN(location); + #elif defined (AF_DBG_SWV_PORT) + port = AF_DBG_SWV_PORT(location); + pin = AF_DBG_SWV_PIN(location); + + #else + #warning "AF debug port is not defined." + #endif +#endif + + /* Port/pin location not defined for the device. */ + if ((pin < 0) || (port < 0)) { + EFM_ASSERT(0); + return; + } + + /* Ensure that the auxiliary clock going to the Cortex debug trace module is enabled. */ +#if !defined(_SILICON_LABS_32B_SERIES_2) + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, false); +#endif + + /* Set the selected pin location for the SWO pin and enable it. */ + GPIO_DbgLocationSet(location); + GPIO_DbgSWOEnable(true); + + /* Configure the SWO pin for output. */ + GPIO_PinModeSet((GPIO_Port_TypeDef)port, pin, gpioModePushPull, 0); +} +#endif + +/** @} (end addtogroup dbg) */ +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ diff --git a/Libs/platform/emlib/src/em_emu.c b/Libs/platform/emlib/src/em_emu.c new file mode 100644 index 0000000..b453df8 --- /dev/null +++ b/Libs/platform/emlib/src/em_emu.c @@ -0,0 +1,4319 @@ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#include "em_emu.h" +#if defined(EMU_PRESENT) && (EMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "em_gpio.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" +#include "em_ramfunc.h" + +#if defined(SL_CATALOG_METRIC_EM23_WAKE_PRESENT) +#include "sli_metric_em23_wake.h" +#include "sli_metric_em23_wake_config.h" +#endif + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) +#include "sli_metric_em4_wake.h" +#endif + +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/* Consistency check, since restoring assumes similar bit positions in */ +/* CMU OSCENCMD and STATUS regs. */ +#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) +#error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) +#error Conflict in HFXOENS and HFXOEN bitpositions +#endif +#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) +#error Conflict in LFRCOENS and LFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) +#error Conflict in LFXOENS and LFXOEN bitpositions +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined(_EFM32_GECKO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_TINY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x001be323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_GIANT_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_WONDER_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_ZERO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00005c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#elif defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00085c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#endif +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ + || (defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) +// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. +#define ERRATA_FIX_EMU_E110_ENABLE +#endif + +/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E108_ENABLE +#endif + +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_EMU_E208_ENABLE +#endif + +/* Enable FETCNT tuning errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE +#endif + +/* Enable LN handshake errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE +typedef enum { + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; +#endif + +/* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S + * while powering the analog peripherals from DVDD, firmware must switch + * over to powering the analog peripherals from AVDD and delay the EM4S entry + * with 30 us. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define ERRATA_FIX_EM4S_DELAY_ENTRY +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) +/* EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. */ +#define ERRATA_FIX_EMU_E220_DECBOD_ENABLE +#define EMU_PORBOD (*(volatile uint32_t *) (EMU_BASE + 0x14C)) +#define EMU_PORBOD_GMC_CALIB_DISABLE (0x1UL << 31) +#endif + +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0 and some devices have a special RAM block + * at the end of their block layout. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2U +#define RAM0_BLOCK_SIZE 0x4000U +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#define RAM0_BLOCKS 1U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM1_BLOCKS 1U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) +#define RAM0_BLOCKS 8U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 8U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 4U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define RAM0_BLOCKS 6U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) +#define RAM0_BLOCKS 32U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if !defined(PWRCFG_DCDCTODVDD_VMIN) +/** DCDCTODVDD output range maximum. */ +#define PWRCFG_DCDCTODVDD_VMIN 1800U +#endif +#if !defined(PWRCFG_DCDCTODVDD_VMAX) +/** DCDCTODVDD output range minimum. */ +#define PWRCFG_DCDCTODVDD_VMAX 3000U +#endif +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) || defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#define DCDC_LP_PFET_CNT 7 +#define DCDC_LP_NFET_CNT 7 +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/* Translate fields with different names across platform generations to common names. */ +#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT +#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT +#endif +#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT +#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT +#endif + +/* Disable LP mode hysteresis in the state machine control. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) +/* Comparator threshold on the high side. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) +#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) + +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/* EMU DCDC MODE set timeout. */ +#define EMU_DCDC_MODE_SET_TIMEOUT 1000000 +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) +#define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) +#define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) +#define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/* As the energy mode at which a temperature measurement was taken at is + * not known, the chosen constant for the TEMPCO calculation is midway between + * the EM0/EM1 constant and the EM2/EM3/EM4 constant. + */ +#define EMU_TEMPCO_CONST (0.273f) +#endif + +#define EMU_EM4_ENTRY_WAIT_LOOPS 200 + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* Static user configuration. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +static uint16_t dcdcMaxCurrent_mA; +static uint16_t dcdcEm01LoadCurrent_mA; +static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; +#endif +#if defined(EMU_VSCALE_EM01_PRESENT) +static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/* Convert from level to EM0/1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + return EMU_CMD_EM01VSCALE1 << ((uint32_t)level - _EMU_STATUS_VSCALE_VSCALE1); +#else + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +#endif +} +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) + __WFI(); // Enter EM2 or EM3 + if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { + for (volatile int i = 0; i < 6; i++) { + } // Dummy wait loop ... + } + +#else + __WFI(); // Enter EM2 or EM3 +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + *(volatile uint32_t*)4; // Clear faulty read data after wakeup +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif +#endif +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ + /* Second part of EMU_E220 DECBOD Errata fix. Calibration needs to be disabled + * quickly when coming out of EM2/EM3. Ram execution is needed to meet timing. + * Calibration is re-enabled after voltage scaling completes. */ + uint32_t temp = EMU_PORBOD | EMU_PORBOD_GMC_CALIB_DISABLE; + __WFI(); + EMU_PORBOD = temp; +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +/***************************************************************************//** + * @brief + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change the oscillator and the voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * + ******************************************************************************/ +typedef enum { + emState_Save, /* Save EMU and CMU state. */ + emState_Restore, /* Restore and unlock. */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) +{ + uint32_t oscEnCmd; + uint32_t cmuLocked; + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined(EMU_VSCALE_PRESENT) + static uint8_t vScaleStatus; + static uint32_t hfrcoCtrl; +#endif + + /* Save or update state. */ + if (action == emState_Save) { + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined(EMU_VSCALE_PRESENT) + /* Save vscale. */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + hfrcoCtrl = CMU->HFRCOCTRL; +#endif + } else { /* Restore state. */ + /* Apply saved configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == true) + /* Restore voltage scaling level if LDO regulator is on. */ +#endif + { + /* Restore EM0 and 1 voltage scaling level. + @ref EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); + } +#endif + /* CMU registers may be locked. */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + +#if defined(_CMU_OSCENCMD_MASK) + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U + ? CMU_OSCENCMD_HFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U + ? CMU_OSCENCMD_AUXHFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U + ? CMU_OSCENCMD_LFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U + ? CMU_OSCENCMD_HFXOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U + ? CMU_OSCENCMD_LFXOEN : 0U; +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U + ? CMU_OSCENCMD_USHFRCOEN : 0U; +#endif + CMU->OSCENCMD = oscEnCmd; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) + /* Wait for upscale to complete and then restore selected clock. */ + EMU_VScaleWait(); + if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { + /* Restore HFRCO frequency which was automatically adjusted by hardware. */ + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { + } + CMU->HFRCOCTRL = hfrcoCtrl; + if (hfClock == cmuSelect_HFRCO) { + /* Optimize wait state after EM2/EM3 wakeup because hardware has + * modified them. */ + CMU_UpdateWaitStates(SystemHfrcoFreq, (int)EMU_VScaleGet()); + } + } +#endif + + switch (hfClock) { + case cmuSelect_LFXO: + CMU_CLOCK_SELECT_SET(HF, LFXO); + break; + case cmuSelect_LFRCO: + CMU_CLOCK_SELECT_SET(HF, LFRCO); + break; + case cmuSelect_HFXO: + CMU_CLOCK_SELECT_SET(HF, HFXO); + break; +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, USHFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, HFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + CMU_CLOCK_SELECT_SET(HF, CLKIN0); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + break; +#endif + } + +#if defined(_CMU_OSCENCMD_MASK) + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } +#endif + + /* Restore CMU register locking */ + if (cmuLocked != 0U) { + CMU_Lock(); + } + } +} +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) +/* Get enable conditions for errata EMU_E107 fix. */ +__STATIC_INLINE bool getErrataFixEmuE107En(void) +{ +#if defined(_EFM32_HAPPY_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) + // all revisions have the errata + return true; +#else + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_EFM32_GECKO_FAMILY) + // all GECKO revisions except Revision E have the errata + return (majorMinorRev <= 0x0103); +#elif defined(_EFM32_GIANT_FAMILY) + // all LEOPARD GECKO (Major = 0x01 Or 0x02) revisions have the errata + // all GIANT GECKO (Major = 0x01) revisions except Revision E have the errata + return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204) || (majorMinorRev == 0x0205); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +#endif /* #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) #else */ +} +#endif /* #if defined(ERRATA_FIX_EMU_E107_ENABLE) */ + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +/* Get enable conditions for errata EMU_E110 fix. */ +__STATIC_INLINE bool getErrataFixEmuE110En(void) +{ + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_ZERO_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + return ((majorMinorRev == 0x0100 || majorMinorRev == 0x0101)); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_WONDER_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + return (majorMinorRev == 0x0204); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +} +#endif /* #if defined(ERRATA_FIX_EMU_E110_ENABLE) */ + +/* LP prepare / LN restore P/NFET count. */ +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) +static void currentLimitersUpdate(void); +static void dcdcFetCntSet(bool lpModeSet) +{ + uint32_t tmp; + static uint32_t emuDcdcMiscCtrlReg; + + if (lpModeSet) { + emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; + tmp = EMU->DCDCMISCCTRL + & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); + tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) + | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = tmp; + currentLimitersUpdate(); + } else { + EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; + currentLimitersUpdate(); + } +} +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +static void dcdcHsFixLnBlock(void) +{ + if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) + || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { + /* Wait for LNRUNNING */ + if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { + while (!(EMU_DCDCSTATUS & (0x1 << 16))) { + } + } + errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; + } +} +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) +/* Configure EMU and CMU for EM2 and 3 voltage downscale. */ +static void vScaleDownEM23Setup(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + + uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; + uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; + + /* Inverse coding. */ + if (em23vs > em01vs) { + EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + /* Set RAM wait states for safe EM2 wakeup. */ + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); +#endif + } else { + EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; + } +} + +/* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ +static void vScaleAfterWakeup(void) +{ + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 + * entry if voltage scaling in EM2/EM3 is enabled. The hardware would + * then update the HFRCO frequency to 19 MHz automatically. */ + uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) + >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; + if (freqRange == 0x08U) { + SystemHfrcoFreq = 19000000; + } + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +typedef enum { + dpllState_Save, /* Save DPLL state. */ + dpllState_Restore, /* Restore DPLL. */ +} dpllState_TypeDef; + +/***************************************************************************//** + * @brief + * Save or restore DPLL state. + * + * @param[in] action + * Value to indicate saving DPLL state or restoring its state. + * + * @note + * The function is used in EMU_Save() and EMU_Restore() to handle the + * DPLL state before entering EM2 or EM3 and after exiting EM2 or EM3. + * The function is required for the EFR32xG22 and EFR32xG27 families. + * On those families devices, the DPLL is disabled automatically when + * entering EM2, EM3. But exiting EM2, EM3 won't re-enable automatically + * the DPLL. Hence, the software needs to re-enable the DPLL upon EM2/3 + * exit. + ******************************************************************************/ +static void dpllState(dpllState_TypeDef action) +{ + CMU_ClkDiv_TypeDef div; + static uint32_t dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + + if (action == dpllState_Save) { + dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; + if (DPLL0->EN == DPLL_EN_EN) { + /* DPLL is in use, save reference clock selection. */ + dpllRefClk = CMU->DPLLREFCLKCTRL; + } + } else { /* Restore */ + if ((dpllRefClk != CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED) + && (DPLL0->EN != DPLL_EN_EN)) { + /* Restore DPLL reference clock selection. */ + CMU->DPLLREFCLKCTRL = dpllRefClk; + /* Only wait for DPLL lock if HFRCODPLL is used as SYSCLK. */ + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + /* Set HCLK prescaler to safe value to avoid overclocking while locking. */ + div = CMU_ClockDivGet(cmuClock_HCLK); + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } + + /* Relock DPLL and wait for ready. */ + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + DPLL0->EN_SET = DPLL_EN_EN; + while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { + } + + /* Restore HCLK prescaler. */ + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 1U); + } + } else { + /* Relock DPLL and exit without waiting for ready. */ + DPLL0->EN_SET = DPLL_EN_EN; + } + } + } +} +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup emu EMU - Energy Management Unit + * @brief Energy Management Unit (EMU) Peripheral API + * @details + * This module contains functions to control the EMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes + * in Silicon Labs microcontrollers. + * @{ + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 0 and 1 configuration. + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure. + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); +} +#endif + +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 2 and 3 configuration. + * + * @param[in] em23Init + * Energy Mode 2 and 3 configuration structure. + ******************************************************************************/ +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) +{ +#if defined(_EMU_CTRL_EMVREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) + : (EMU->CTRL & ~EMU_CTRL_EMVREG); +#elif defined(_EMU_CTRL_EM23VREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) + : (EMU->CTRL & ~EMU_CTRL_EM23VREG); +#else + (void)em23Init; +#endif + +#if defined(EMU_VSCALE_PRESENT) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#if defined(CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) + if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just prior to execution of the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PresleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just after wakeup from the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PostsleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 2 (EM2). + * + * @details + * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO + * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering + * EM0, HFRCO is re-enabled and the core will be clocked by the configured + * HFRCO band. This ensures a quick wakeup from EM2. + * + * However, prior to entering EM2, the core may have been using another + * oscillator than HFRCO. The @p restore parameter gives the user the option + * to restore all HF oscillators according to state prior to entering EM2, + * as well as the clock used to clock the core. This restore procedure is + * handled by SW. However, since handled by SW, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use the HFXO oscillator, which has been + * disabled during EM2 mode, this function will stall until the oscillator + * has stabilized. Stalling time can be reduced by adding interrupt + * support detecting stable oscillator, and an asynchronous switch to the + * original oscillator. See CMU documentation. Such a feature is however + * outside the scope of the implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can not be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO is re-enabled by this function, and NOT used to clock the core, + * this function will not wait for HFXO to stabilize. This must be considered + * by the application if trying to use features relying on that oscillator + * upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM2. It will thus remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(), + * the automatic starting and selecting of the core clocks will be done, + * regardless of the @p restore parameter, when waking up on the wakeup + * sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * Note that the hardware will automatically update the HFRCO frequency in the + * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the + * restore argument to this function is true then software will restore the + * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is + * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and + * all wait states are at a safe value. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM2(bool restore) +{ +#if defined(SLI_METRIC_EM2_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM2_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + + EMU_EM23PresleepHook(); + EMU_EFPEM23PresleepHook(); + +#if defined(_GPIO_IF_EM4WU_MASK) +#if defined(_CMU_CLKEN0_GPIO_SHIFT) + if (CMU->CLKEN0 & CMU_CLKEN0_GPIO) { + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); + } +#else + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif // defined(_CMU_CLKEN0_GPIO_SHIFT) +#endif // defined(_GPIO_IF_EM4WU_MASK) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EFPEM23PostsleepHook(); + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Enter energy mode 3 (EM3). + * + * @details + * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, + * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, + * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When + * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the + * configured HFRCO band. This ensures a quick wakeup from EM3. + * + * However, prior to entering EM3, the core may have been using an + * oscillator other than HFRCO. The @p restore parameter gives the user the option + * to restore all HF/LF oscillators according to state prior to entering EM3, + * as well as the clock used to clock the core. This restore procedure is + * handled by software. However, since it is handled by software, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use an oscillator other than HFRCO, this + * function will stall until the oscillator has stabilized. Stalling time + * can be reduced by adding interrupt support detecting stable oscillator, + * and an asynchronous switch to the original oscillator. See CMU + * documentation. This feature is, however, outside the scope of the + * implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can't be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock + * the core, this function will not wait for those oscillators to stabilize. + * This must be considered by the application if trying to use features + * relying on those oscillators upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM3. It will, therefore, remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM3(bool restore) +{ +#if defined(SLI_METRIC_EM3_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM3_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + +#if defined(_CMU_OSCENCMD_MASK) + uint32_t cmuLocked; + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* Disable LF oscillators. */ + CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; + + /* Restore CMU register locking. */ + if (cmuLocked != 0U) { + CMU_Lock(); + } +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + +#if defined(_GPIO_IF_EM4WU_MASK) +#if defined(_CMU_CLKEN0_GPIO_SHIFT) + if (CMU->CLKEN0 & CMU_CLKEN0_GPIO) { + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); + } +#else + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif // defined(_CMU_CLKEN0_GPIO_SHIFT) +#endif // defined(_GPIO_IF_EM4WU_MASK) + + EMU_EM23PresleepHook(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Save the CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the state to be saved without + * going to sleep. The state can be restored manually by calling + * @ref EMU_Restore(). + ******************************************************************************/ +void EMU_Save(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Save); +#endif +} + +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Restore); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Restore); +#endif +} + +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 4 configuration. + * + * @param[in] em4Init + * Energy Mode 4 configuration structure. + ******************************************************************************/ +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) +{ +#if defined(_EMU_EM4CONF_MASK) + /* Initialization for platforms with EMU->EM4CONF register. */ + uint32_t em4conf = EMU->EM4CONF; + + /* Clear fields that will be reconfigured. */ + em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK + | _EMU_EM4CONF_OSC_MASK + | _EMU_EM4CONF_BURTCWU_MASK + | _EMU_EM4CONF_VREGEN_MASK + | _EMU_EM4CONF_BUBODRSTDIS_MASK); + + /* Configure new settings. */ + em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) + | (em4Init->osc) + | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) + | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) + | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); + + /* Apply configuration. Note that lock can be set after this stage. */ + EMU->EM4CONF = em4conf; + +#elif defined(_EMU_EM4CTRL_EM4STATE_MASK) + /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ + + uint32_t em4ctrl = EMU->EM4CTRL; + + em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK + | _EMU_EM4CTRL_RETAINLFRCO_MASK + | _EMU_EM4CTRL_RETAINULFRCO_MASK + | _EMU_EM4CTRL_EM4STATE_MASK + | _EMU_EM4CTRL_EM4IORETMODE_MASK); + + em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) + | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) + | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) + | (em4Init->em4State == emuEM4Hibernate + ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) + | ((uint32_t)em4Init->pinRetentionMode); + + EMU->EM4CTRL = em4ctrl; +#elif defined(_EMU_EM4CTRL_MASK) + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | (uint32_t)em4Init->pinRetentionMode; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Energy mode 4 pre-sleep hook function. + * + * @details + * This function is called by @ref EMU_EnterEM4() just prior to the sequence + * of writes to put the device in EM4. The function implementation does not + * perform anything, but it is SL_WEAK so that it can be re-implemented in + * application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 4 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM4PresleepHook() but is reserved for + * EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + * Device which is configured in Boost DC-DC mode can not enter EM4. + ******************************************************************************/ +void EMU_EnterEM4(void) +{ + /* Device with Boost DC-DC cannot enter EM4 because Boost DC-DC module does not + * have BYPASS switch so DC-DC converter can not be set to bypass mode. */ +#if (defined(_SILICON_LABS_DCDC_FEATURE) \ + && (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST)) + EFM_ASSERT(false); +#endif + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) + sli_metric_em4_wake_init(); +#endif + int i; + +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); +#else + uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (2U << _EMU_CTRL_EM4CTRL_SHIFT); + uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (3U << _EMU_CTRL_EM4CTRL_SHIFT); +#endif + + /* Make sure that the register write lock is disabled. */ + EMU_Unlock(); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should + * switch to bypass mode before entering EM4S. Other devices handle this + * automatically at the hardware level. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE + || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { + EMU_DCDCModeSet(emuDcdcMode_Bypass); + } + } +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + /* Make sure DCDC Mode is not modified, from this point forward, + * by another code section. */ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + /* Workaround for bug that may cause a Hard Fault on EM4 entry */ + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + /* The buck DC-DC is available in all energy modes except for EM4. + * The DC-DC converter must first be turned off and switched over to bypass mode. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) + EMU_DCDCModeSet(emuDcdcMode_Bypass); +#endif +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) + if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { + /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. + * Full description of errata fix can be found in the errata document. */ + __disable_irq(); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); + *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); + } +#endif + +#if defined(ERRATA_FIX_EMU_E108_ENABLE) + /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ + __disable_irq(); + *(volatile uint32_t *)0x400C80E4 = 0; +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + +#if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) + /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { + BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); + /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement + * before entering EM4. */ + uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { + } + CMU->HFRCOCTRL = freqCal; + CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; + while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { + } + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + __NOP(); + } + } +#endif + + EMU_EM4PresleepHook(); + EMU_EFPEM4PresleepHook(); + +#if defined(_GPIO_IF_EM4WU_MASK) +#if defined(_CMU_CLKEN0_GPIO_SHIFT) + if (CMU->CLKEN0 & CMU_CLKEN0_GPIO) { + // Clear all EM4WU interrupts before entering sleep + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); + } +#else + GPIO_IntClear(_GPIO_IF_EM4WU_MASK); +#endif // defined(_CMU_CLKEN0_GPIO_SHIFT) +#endif // defined(_GPIO_IF_EM4WU_MASK) + + for (i = 0; i < 4; i++) { +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + EMU->EM4CTRL = em4seq2; + EMU->EM4CTRL = em4seq3; + } + EMU->EM4CTRL = em4seq2; +#else + EMU->CTRL = em4seq2; + EMU->CTRL = em4seq3; + } + EMU->CTRL = em4seq2; +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + /* If EM4ERR flag in DCDC->IF is set, mean that device cannot enter EM4, device will be suspended in this assertion */ + EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @details + * This function waits after the EM4 entry request to make sure the CPU + * is properly shutdown or the EM4 entry failed. + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + ******************************************************************************/ +void EMU_EnterEM4Wait(void) +{ + EMU_EnterEM4(); + + // The EM4 entry waiting loop should take 4 cycles by loop minimally (Compiler dependent). + // We would then wait for (EMU_EM4_ENTRY_WAIT_LOOPS * 4) clock cycles. + for (uint16_t i = 0; i < EMU_EM4_ENTRY_WAIT_LOOPS; i++) { + __NOP(); + } +} + +#if defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Enter energy mode 4 hibernate (EM4H). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4H(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); +#endif + EMU_EnterEM4(); +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 shutoff (EM4S). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4S(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); +#endif + EMU_EnterEM4(); +} +#endif + +/***************************************************************************//** + * @brief + * Power down memory block. + * + * @param[in] blocks + * Specifies a logical OR of bits indicating memory blocks to power down. + * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot + * be disabled. See the reference manual for available + * memory blocks for a device. + * + * @note + * Only a POR reset can power up the specified memory block(s) after power down. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. + ******************************************************************************/ +void EMU_MemPwrDown(uint32_t blocks) +{ +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; +#else + (void)blocks; +#endif +} + +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will power down blocks from start to the end of RAM. For xg27, + * it will shut off blocks which are completely enclosed by the memory range + * given by [start, end]. + * + * This is an example to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of the first RAM block is device-specific. + * See the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * The specified memory block(s) will stay off until a call + * to EMU_RamPowerUp() is done. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. Except for xg27, It can only + * have two values: 0 or more than RAM0_END. Any other valid RAM address + * will just do nothing without any error or indication that nothing happened. + * This address is exclusive. If this parameter is 0, all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + (void) start; + + if (end == 0U) { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down. +#if defined(_SILICON_LABS_32B_SERIES_2) + if (end >= RAM0_END) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. + // This condition happens when the block 0 disable bit flag is available in the retention control register. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i); + } +#elif defined(RAM0_BLOCKS) + // These platforms have equally-sized RAM blocks and block 0 cannot be powered down. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); + } +#endif + } +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + else if (end > 0x20006000UL) { + // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB + } +#endif +#endif + + // Power down the selected blocks. +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_maskDmem0RetnCtrl(mask); +#else + // These devices are unable to power down RAM blocks. + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) { + for (unsigned i = 0; i < RAM1_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif + +#if defined(RAM2_MEM_END) + mask = 0; + if (end > RAM2_MEM_END) { + for (unsigned i = 0; i < RAM2_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; + } + } + EMU->RAM2CTRL |= mask; +#endif +} + +/***************************************************************************//** + * @brief + * Power up all available RAM memory blocks. + * + * @details + * This function will power up all the RAM blocks on a device, this means + * that the RAM blocks are retained in EM2/EM3. Note that this functionality + * is not supported on Series 0 devices. Only a reset will power up the RAM + * blocks on a series 0 device. + ******************************************************************************/ +void EMU_RamPowerUp(void) +{ +#if defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM1CTRL_MASK) + EMU->RAM1CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM2CTRL_MASK) + EMU->RAM2CTRL = 0x0UL; +#endif +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_zeroDmem0RetnCtrl(); +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * A peripheral select mask. Use | operator to select multiple peripherals, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = (uint32_t)periMask + & (uint32_t)emuPeripheralRetention_ALL; +} +#endif + +/***************************************************************************//** + * @brief + * Update EMU module with CMU oscillator selection/enable status. + * + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). + ******************************************************************************/ +void EMU_UpdateOscConfig(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Energy mode 01 voltage scaling hook function. + * + * @param[in] voltage + * Voltage scaling level requested. + * + * @details + * This function is called by EMU_VScaleEM01 to let EFP know that voltage scaling + * is requested. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage) +{ + (void)voltage; +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0 or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is primarily needed by the @ref cmu. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* VSCALE frequency is HFSRCCLK. */ + if (clockFrequency == 0U) { +#if defined(_SILICON_LABS_32B_SERIES_2) + hfSrcClockFrequency = SystemSYSCLKGet(); +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; +#endif + } else { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); + } else { + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is useful for upscaling before programming Flash from @ref msc + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfFreq; + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + if (EMU_VScaleGet() == voltage) { + /* Voltage is already at the correct level. */ + return; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + (void)wait; + CORE_DECLARE_IRQ_STATE; + + hfFreq = SystemSYSCLKGet(); + hfSrcClockFrequency = hfFreq; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + CORE_ENTER_CRITICAL(); + EMU->IF_CLR = EMU_IF_VSCALEDONE; + EMU_EFPEM01VScale(voltage); + EMU->CMD = vScaleEM01Cmd(voltage); + + // Note that VSCALEDONE interrupt flag must be used instead of VSCALEBUSY + // because hardware does not set the VSCALEBUSY flag immediately. + while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) + && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { + EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); + // Wait for VSCALE completion. + // SRAM accesses will fault the core while scaling. + } + CORE_EXIT_CRITICAL(); + +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfFreq = SystemHFClockGet(); + hfSrcClockFrequency = hfFreq * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + + if (wait) { + EMU_VScaleWait(); + } +#endif + + if (voltage == emuVScaleEM01_HighPerformance) { + /* Update wait states after scaling up voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] bupdInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) +{ + uint32_t reg; + + /* Set the power connection configuration. */ + reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK + | _EMU_PWRCONF_VOUTSTRONG_MASK + | _EMU_PWRCONF_VOUTMED_MASK + | _EMU_PWRCONF_VOUTWEAK_MASK); + + reg |= bupdInit->resistor + | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) + | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) + | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); + + EMU->PWRCONF = reg; + + /* Set the backup domain inactive mode configuration. */ + reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); + reg |= (bupdInit->inactivePower); + EMU->BUINACT = reg; + + /* Set the backup domain active mode configuration. */ + reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); + reg |= (bupdInit->activePower); + EMU->BUACT = reg; + + /* Set the power control configuration */ + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK + | _EMU_BUCTRL_BODCAL_MASK + | _EMU_BUCTRL_STATEN_MASK + | _EMU_BUCTRL_EN_MASK); + + /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and + release reset. */ + reg |= bupdInit->probe + | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) + | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) + | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); + + /* Enable configuration. */ + EMU->BUCTRL = reg; + + /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ + EMU_BUPinEnable(bupdInit->enable); + + /* If enable is true, release BU reset. If not, keep reset asserted. */ + BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold value. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 8); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) + | (value << _EMU_BUACT_BUEXTHRES_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) + | (value << _EMU_BUINACT_BUENTHRES_SHIFT); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold Range. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 4); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) + | (value << _EMU_BUACT_BUEXRANGE_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) + | (value << _EMU_BUINACT_BUENRANGE_SHIFT); + break; + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] buInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) +{ + uint32_t reg = 0; + + /* Set the backup power configuration. */ + reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + reg |= (uint32_t)(buInit->inactivePwrCon); + reg |= (uint32_t)(buInit->activePwrCon); + reg |= (uint32_t)(buInit->pwrRes); + reg |= (uint32_t)(buInit->voutRes); + reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); + reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +/***************************************************************************//** + * @brief + * Disable Main Backup Power Domain comparator. + * + * @param[in] disableMainBuComparator + * True to disable main BU comparator. + ******************************************************************************/ +void EMU_BUDisMaxCompSet(bool disableMainBuComparator) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); + reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when not in Backup mode. + * + * @param[in] inactPwrCon + * Inactive power configuration. + ******************************************************************************/ +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); + reg |= (uint32_t)(inactPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when in Backup mode. + * + * @param[in] actPwrCon + * Active power configuration. + ******************************************************************************/ +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); + reg |= (uint32_t)(actPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/***************************************************************************//** + * @brief + * Power domain resistor selection. + * + * @param[in] pwrRes + * Resistor selection. + ******************************************************************************/ +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); + reg |= (uint32_t)(pwrRes); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/***************************************************************************//** + * @brief + * B_VOUT resistor select. + * + * @param[in] resistorSel + * Resistor selection. + ******************************************************************************/ +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); + reg |= (uint32_t)(resistorSel); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +/***************************************************************************//** + * @brief + * Enable BU_VIN probing + * + * @param[in] enable + * True to enable BU_VIN probing. False to disable. + ******************************************************************************/ +void EMU_BUBuVinProbeEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); + reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_STATEN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode status export. + * + * @param[in] enable + * True to enable status export. False to disable. + ******************************************************************************/ +void EMU_BUStatEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); + reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_EN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode. + * + * @param[in] enable + * True to enable backup mode. False to disable. + ******************************************************************************/ +void EMU_BUEnableSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); + reg |= (enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum { + dcdcTrimMode_EM234H_LP = 0, +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Load DCDC calibration constants from the DI page. A constant means that calibration + * data that does not change depending on other configuration parameters. + * + * @return + * False if calibration registers are locked. + ******************************************************************************/ +static bool dcdcConstCalibrationLoad(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t val; + volatile uint32_t *reg; + + /* DI calibration data in Flash. */ + volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); + volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); + volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); + volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); + volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); + volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); + + if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { + val = *(diCal_EMU_DCDCLNFREQCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLNVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM0 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM1 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; + *reg = val; + + return true; + } + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + +#else + return true; +#endif +} + +/***************************************************************************//** + * @brief + * Set recommended and validated current optimization and timing settings. + * + ******************************************************************************/ +static void dcdcValidatedConfigSet(void) +{ + uint32_t lnForceCcm; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t dcdcTiming; + SYSTEM_ChipRevision_TypeDef rev; +#endif + + /* Enable duty cycling of the bias. */ + EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; + + /* Set low-noise RCO for LNFORCECCM configuration. + * LNFORCECCM is default 1 for EFR32 + * LNFORCECCM is default 0 for EFM32 + */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + if (lnForceCcm != 0U) { + /* 7 MHz is recommended for LNFORCECCM = 1. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } else { + /* 3 MHz is recommended for LNFORCECCM = 0. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS + | EMU_DCDCMISCCTRL_LPCMPHYSHI; + + SYSTEM_ChipRevisionGet(&rev); + if ((rev.major == 1) + && (rev.minor < 3) + && (errataFixDcdcHsState == errataFixDcdcHsInit)) { + /* LPCMPWAITDIS = 1 */ + EMU_DCDCSMCTRL |= 1; + + dcdcTiming = EMU->DCDCTIMING; + dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK + | _EMU_DCDCTIMING_LNWAIT_MASK + | _EMU_DCDCTIMING_BYPWAIT_MASK); + + dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) + | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) + | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); + EMU->DCDCTIMING = dcdcTiming; + + errataFixDcdcHsState = errataFixDcdcHsTrimSet; + } +#endif +} + +/***************************************************************************//** + * @brief + * Compute current limiters: + * LNCLIMILIMSEL: LN current limiter threshold + * LPCLIMILIMSEL: LP current limiter threshold + * DCDCZDETCTRL: zero detector limiter threshold + ******************************************************************************/ +static void currentLimitersUpdate(void) +{ + uint32_t lncLimSel; + uint32_t zdetLimSel; + uint32_t pFetCnt; + uint16_t maxReverseCurrent_mA; + + /* 80 mA as recommended peak in Application Note AN0948. + The peak current is the average current plus 50% of the current ripple. + Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also + a constant, lpcLimImSel = 1. The following calculation is provided + for documentation only. */ + const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) + / (5 * (DCDC_LP_PFET_CNT + 1))) + - 1; + const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; + + /* Get enabled PFETs. */ + pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) + >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; + + /* Compute the LN current limiter threshold from the nominal user input current and + LN PFETCNT as described in the register description for + EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ + lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) + + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) + / (5U * (pFetCnt + 1U))) + - 1U; + + /* Saturate the register field value. */ + lncLimSel = SL_MIN(lncLimSel, + _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); + + lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); + EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); + + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) + | (lncLimSel | lpcLimSel); + + /* Compute the reverse current limit threshold for the zero detector from the user input + maximum reverse current and LN PFETCNT as described in the register description + for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ + if (dcdcReverseCurrentControl >= 0) { + /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ + maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; + + zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) + + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) + / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); + /* Saturate the register field value. */ + zdetLimSel = SL_MIN(zdetLimSel, + _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK + >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); + + zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); + + EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) + | zdetLimSel; + } +} + +/***************************************************************************//** + * @brief + * Set static variables that hold the user set maximum peak current + * and reverse current. Update limiters. + * + * @param[in] maxCurrent_mA + * Set the maximum peak current that the DCDC can draw from the power source. + * @param[in] reverseCurrentControl + * Reverse the current control as defined by + * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. + ******************************************************************************/ +static void userCurrentLimitsSet(uint32_t maxCurrent_mA, + EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) +{ + dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; + dcdcReverseCurrentControl = reverseCurrentControl; +} + +/***************************************************************************//** + * @brief + * Set DCDC low noise compensator control register. + * + * @param[in] comp + * Low-noise mode compensator trim setpoint. + ******************************************************************************/ +static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) +{ + switch (comp) { + case emuDcdcLnCompCtrl_1u0F: + EMU->DCDCLNCOMPCTRL = 0x57204077UL; + break; + + case emuDcdcLnCompCtrl_4u7F: + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback + * attenuation, and DEVINFOREV. + * + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpCmpBias + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. + ******************************************************************************/ +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) +{ + uint32_t lpcmpHystSel; +#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + (void)lpAttenuation; +#endif + + /* Get calibration data revision. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); + + /* Load LPATT indexed calibration data. */ + if (devinfoRev < 4) { + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; + + if (lpAttenuation) { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; + } else { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; + } + } else +#endif + { + /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; + switch (lpCmpBias) { + case 0: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; + break; + + case 1: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; + break; + + case 2: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; + break; + + case 3: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + } + + /* Set trims. */ + if (trimMode == dcdcTrimMode_EM234H_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + if (trimMode == dcdcTrimMode_EM01_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to look up in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); + switch (switchVal) { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @note + * Do not call this function if the power circuit is configured for NODCDC as + * described in the Power Configurations section of the Reference Manual. + * Instead, call @ref EMU_DCDCPowerOff(). + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + uint32_t lpCmpBiasSelEM234H; + +#if defined(_EMU_PWRCFG_MASK) + /* Set the external power configuration. This enables writing to the other + DCDC registers. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; + + /* EMU->PWRCFG is write-once and POR reset only. Check that + the desired power configuration was set. */ + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + /* If this assert triggers unexpectedly, power cycle the + kit to reset the power configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } +#endif + + /* Load DCDC calibration data from the DI page. */ + (void)dcdcConstCalibrationLoad(); + + /* Check current parameters */ + EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); + EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); + + if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200 mA. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); + } +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10 mA is supported for EM01-LP mode. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); + } +#endif + else { + /* No need to check the EM01 load limit. */ + } + + /* EM2/3/4 current above 10 mA is not supported. */ + EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); + + if (dcdcInit->em234LoadCurrent_uA < 75U) { + lpCmpBiasSelEM234H = 0; + } else if (dcdcInit->em234LoadCurrent_uA < 500U) { + lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { + lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else { + lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } + + /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ + + /* Set DCDC low-power mode comparator bias selection. */ + + /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. + => Updates DCDCMISCCTRL_LNFORCECCM */ + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK + | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) + | ((uint32_t)lpCmpBiasSelEM234H + | (dcdcInit->reverseCurrentControl >= 0 + ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10 mA EM01-LP current is supported. */ + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; +#endif + + /* 2. Set recommended and validated current optimization settings. + <= Depends on LNFORCECCM + => Updates DCDCLNFREQCTRL_RCOBAND */ + dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; + dcdcValidatedConfigSet(); + + /* 3. Updated static currents and limits user data. + Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ + userCurrentLimitsSet(dcdcInit->maxCurrent_mA, + dcdcInit->reverseCurrentControl); + + /* 4. Optimize LN slice based on the given user input load current. + <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND + <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl + => Updates DCDCMISCCTRL_P/NFETCNT + => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL + => Updates DCDCZDETCTRL_ZDETILIMSEL */ + EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); + + /* ======================================================= */ + + /* Set DCDC low noise mode compensator control register. */ + compCtrlSet(dcdcInit->dcdcLnCompCtrl); + + /* Set DCDC output voltage. */ + if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) + /* Select analog peripheral power supply. This must be done before + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower ? 1 : 0); +#endif + +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set EM0 DCDC operating mode. Output voltage set in + @ref EMU_DCDCOutputVoltageSet() above takes effect if mode + is changed from bypass/off mode. */ + EMU_DCDCModeSet(dcdcInit->dcdcMode); + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + /* Select the analog peripheral power supply. This must be done after + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower + == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + ******************************************************************************/ +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Wait for any previous write sync to complete and read DCDC mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + + /* Enable bypass current limiter when not in bypass mode to prevent + excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ + if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); + } + + if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { + /* Mode already set. If already in bypass, make sure the bypass current limiter + is disabled. */ + if (dcdcMode == emuDcdcMode_Bypass) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); + } + return; + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /* Fix for errata DCDC_E203. */ + if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) + && (dcdcMode == emuDcdcMode_LowNoise)) { + errataFixDcdcHsState = errataFixDcdcHsBypassLn; + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_80) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Fix for errata DCDC_E204. */ + if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) + && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { + /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ + EMU_IntClear(EMU_IFC_DCDCLNRUNNING); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; + while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { + } + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) + | (uint32_t)dcdcMode; + + /* Disable bypass current limiter after bypass mode is entered. + Enable the limiter if any other mode is entered. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, + _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, + dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); + + if (dcdcLocked) { + EMU_PowerLock(); + } +} + +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +/***************************************************************************//** + * @brief + * Set DCDC Mode EM23 operating mode. + * + * @param[in] dcdcModeEM23 + * DCDC mode EM23. + ******************************************************************************/ +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23) +{ + bool dcdcLocked; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) + | (uint32_t)dcdcModeEM23; + + if (dcdcLocked) { + EMU_PowerLock(); + } +} +#endif + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @details + * This function powers off the DCDC controller. This function should only be + * used if the external power circuit is wired for no DCDC. If the external power + * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the + * DCDC in bypass mode to disable DCDC. + * + * @return + * Return false if the DCDC could not be disabled. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + bool dcdcModeSet; + +#if defined(_EMU_PWRCFG_MASK) + /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif + + /* Select DVDD as input to the digital regulator. */ +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required + mode could be set. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; + + dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); + EFM_ASSERT(dcdcModeSet); + + return dcdcModeSet; +} + +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode. + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise, the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, + bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)((uint32_t) + (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) + ((EMU->DCDCLNFREQCTRL + & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { + } + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { + EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } else { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } else { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band.*/ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + +/***************************************************************************//** + * @brief + * Set the DCDC output voltage. + * + * @note + * The DCDC is not characterized for the entire valid output voltage range. + * For that reason an upper limit of 3.0V output voltage is enforced. + * + * @param[in] mV + * Target DCDC output voltage in mV. + * + * @param[in] setLpVoltage + * Update LP voltage + * + * @param[in] setLnVoltage + * Update LN voltage + * + * @return + * True if the mV parameter is valid. + ******************************************************************************/ +bool EMU_DCDCOutputVoltageSet(uint32_t mV, + bool setLpVoltage, + bool setLnVoltage) +{ +#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + + bool validOutVoltage; + bool attenuationSet; + uint32_t mVlow = 0; + uint32_t mVhigh = 0; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; + + /* Check that the set voltage is within valid range. + Voltages are obtained from the data sheet. */ + validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX); + + if (!validOutVoltage) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Set attenuation to use and low/high range. */ + attenuationSet = mV > 1800U; + if (attenuationSet) { + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } else { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } + + /* Get 2-point calibration data from DEVINFO. */ + + /* LN mode */ + if (attenuationSet) { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; + } else { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; + } + + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) + ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) + ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif + + /* Calculate output voltage trims. */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); + } + + if (setLpVoltage) { + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* LP VREF is that maximum of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Optimize the DCDC slice count based on the estimated average load current + * in EM0. + * + * @param[in] em0LoadCurrentmA + * Estimated average EM0 load current in mA. + ******************************************************************************/ +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) +{ + uint32_t sliceCount = 0; + uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; + + /* Set the recommended slice count. */ + if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { + if (em0LoadCurrentmA < 20U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 10U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 40U) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else { + /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended + configuration. */ + EFM_ASSERT(false); + } + + /* The selected slices are PSLICESEL + 1. */ + sliceCount--; + + /* Apply slice count to both N and P slice. */ + sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT + | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK + | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) + | sliceCount; + + /* Update the current limiters. */ + currentLimitersUpdate(); +} + +/***************************************************************************//** + * @brief + * Set DCDC Low-noise RCO band. + * + * @param[in] band + * RCO band to set. + ******************************************************************************/ +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) +{ + uint32_t forcedCcm; + forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + + /* DCM mode supports up to 4 MHz LN RCO. */ + EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) + || (forcedCcm != 0U)); + + EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Update slice configuration as this depends on the RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC Boost regulator. + * + * @param[in] dcdcBoostInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + BUS_RegMaskedWrite(&DCDC->CTRL, + _DCDC_CTRL_DVDDBSTPRG_MASK, + ((uint32_t)dcdcBoostInit->outputVoltage << _DCDC_CTRL_DVDDBSTPRG_SHIFT)); +#endif + + DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); + DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT); + DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM23 << _DCDC_BSTEM23CTRL_IPKVAL_SHIFT); + + EMU_BoostExternalShutdownEnable(dcdcBoostInit->externalShutdownEn); + + EMU_DCDCModeSet(emuDcdcMode_Regulation); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Set EM01 mode Boost Peak Current setting. + * + * @param[in] boostPeakCurrentEM01 + * Boost Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, + _DCDC_BSTEM01CTRL_IPKVAL_MASK, + ((uint32_t)boostPeakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT)); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +/***************************************************************************//** + * @brief + * Enable/disable Boost External Shutdown Mode. + * + * @param[in] enable + * The boost DC-DC converter can be activated or deactivated + * from a dedicated BOOST_EN pin on the device if enable is true. + ******************************************************************************/ +void EMU_BoostExternalShutdownEnable(bool enable) +{ + if (enable) { + EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; + } else { + EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; + } +} + +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +/***************************************************************************//** + * @brief + * Set DCDC Boost output voltage. + * + * @param[in] boostOutputVoltage + * Boost output voltage. + ******************************************************************************/ +void EMU_DCDCBoostOutputVoltageSet(const EMU_DcdcBoostOutputVoltage_TypeDef boostOutputVoltage) +{ + bool dcdcLocked = false; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + BUS_RegMaskedWrite(&DCDC->CTRL, + _DCDC_CTRL_DVDDBSTPRG_MASK, + ((uint32_t)boostOutputVoltage << _DCDC_CTRL_DVDDBSTPRG_SHIFT)); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); +} +#endif +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Indicate that the DCDC peripheral bus clock enable has changed allowing + * RAIL to react accordingly. + * + * @details + * This function is called after DCDC has been enabled or disabled. + * The function implementation does not perform anything, but it is SL_WEAK + * so that it can use the RAIL version if needed. + ******************************************************************************/ +SL_WEAK void EMU_DCDCUpdatedHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + * @return + * Returns the status of the DCDC mode set operation. + * @verbatim + * SL_STATUS_OK - Operation completed successfully. + * SL_STATUS_TIMEOUT - Operation EMU DCDC set mode timeout. + * @endverbatim + ******************************************************************************/ +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + sl_status_t error = SL_STATUS_OK; + uint32_t timeout = 0; + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + if (dcdcMode == emuDcdcMode_Bypass) { +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT; + + if (currentDcdcMode != emuDcdcMode_Bypass) { + /* Switch to BYPASS mode if it is not the current mode */ + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for BYPASS switch enable. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_CLR = DCDC_EN_EN; +#endif + } else { + while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for VREGIN voltage to rise above threshold. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } else { + DCDC->IF_CLR = DCDC_IF_REGULATION; + DCDC->CTRL_SET = DCDC_CTRL_MODE; + timeout = 0; + while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for DCDC to complete it's startup. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } + } + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + return error; +} +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT || EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold + << _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT) + | EMU_VREGVDDCMPCTRL_VREGINCMPEN; + +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL | DCDC_SYNCBUSY_EM01CTRL0 | DCDC_SYNCBUSY_EM23CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK + | _DCDC_CTRL_DCMONLYEN_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT) + | ((uint32_t)(dcdcInit->dcmOnlyEn ? 1U : 0U) << _DCDC_CTRL_DCMONLYEN_SHIFT); +#else + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT); +#endif + DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT); + DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM23 << _DCDC_EM23CTRL0_IPKVAL_SHIFT); + + EMU_DCDCModeSet(dcdcInit->mode); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @return + * Returns true. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + EMU_DCDCModeSet(emuDcdcMode_Bypass); + return true; +} + +/***************************************************************************//** + * @brief + * Set EMO1 mode Peak Current setting. + * + * @param[in] peakCurrentEM01 + * Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + +#if defined(_DCDC_EN_EN_MASK) + bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0); + DCDC->EN_SET = DCDC_EN_EN; +#endif + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_EM01CTRL0_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_EM01CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + + BUS_RegMaskedWrite(&DCDC->EM01CTRL0, + _DCDC_EM01CTRL0_IPKVAL_MASK, + ((uint32_t)peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT)); + +#if defined(_DCDC_EN_EN_MASK) + if (!dcdcWasEnabled) { + DCDC->EN_CLR = DCDC_EN_EN; + } +#endif + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +/***************************************************************************//** + * @brief + * Set PFMX mode Peak Current setting. + * + * @param[in] value + * Peak load current coefficient in PFMX mode. + ******************************************************************************/ +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + /* Verification that the parameter is in range. */ + /* if not, restrict value to maximum allowed. */ + EFM_ASSERT(value <= (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)); + if (value > (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)) { + value = (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT); + } + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK) + | value << _DCDC_PFMXCTRL_IPKVAL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKVAL_MASK */ + +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +/***************************************************************************//** + * @brief + * Set Ton_max timeout control. + * + * @param[in] value + * Maximum time for peak current detection. + ******************************************************************************/ +SL_WEAK void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) + | value << _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK */ +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) + +/***************************************************************************//** + * @brief + * Get the calibrated threshold value. + * + * @details + * All VMON channels have two calibration fields in the DI page that + * describes the threshold at 1.86 V and 2.98 V. This function will convert + * the uncalibrated input voltage threshold in millivolts into a calibrated + * threshold. + * + * @param[in] channel + * A VMON channel. + * + * @param[in] threshold + * A desired threshold in millivolts. + * + * @return + * A calibrated threshold value to use. The first digit of the return value is placed + * in the "fine" register fields while the next digits are placed in the + * "coarse" register fields. + ******************************************************************************/ +static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, + int threshold) +{ + uint32_t tDiff = 0; + uint32_t tLow = 0; + uint32_t tHigh = 0; + uint32_t calReg; + + /* Get calibration values for 1.86 V and 2.98 V */ + switch (channel) { + case emuVmonChannel_AVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_ALTAVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_DVDD: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_IOVDD0: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + tDiff = tHigh - tLow; + if (tDiff > 0) { + /* Calculate threshold. + * + * Note that volt is used in the reference manual. However, the results + * should be in millivolts. The precision of Va and Vb are increased in the + * calculation instead of using floating points. + */ + uint32_t va = (1120U * 100U) / (tDiff); + uint32_t vb = (1860U * 100U) - (va * tLow); + // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. + if (va != 0) { + /* Round the threshold to the nearest integer value. */ + return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; + } + } + + /* Uncalibrated device guard. */ + return (uint32_t)threshold; +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel. + * + * @details + * Initialize a VMON channel without hysteresis. If the channel supports + * separate rise and fall triggers, both thresholds will be set to the same + * value. The threshold will be converted to a register field value based + * on calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON initialization structure. + ******************************************************************************/ +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) +{ + uint32_t thresholdCoarse, thresholdFine; + uint32_t threshold; + + EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); + + threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); + thresholdFine = threshold % 10U; + thresholdCoarse = threshold / 10U; + + /* Saturate the threshold to maximum values. */ + if (thresholdCoarse > 0xFU) { + thresholdCoarse = 0xF; + thresholdFine = 9; + } + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_ALTAVDD: + EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_DVDD: + EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); + break; + case emuVmonChannel_IOVDD0: + EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); + break; +#endif + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel with hysteresis (separate rise and fall triggers). + * + * @details + * Initialize a VMON channel which supports hysteresis. The AVDD channel is + * the only channel to support separate rise and fall triggers. The rise and + * fall thresholds will be converted to a register field value based on the + * calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON hysteresis initialization structure. + ******************************************************************************/ +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) +{ + uint32_t riseThreshold; + uint32_t fallThreshold; + + /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ + EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); + EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); + /* The fall threshold has to be lower than rise threshold. */ + EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); + + riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); + fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Enable or disable a VMON channel. + * + * @param[in] channel + * A VMON channel to enable/disable. + * + * @param[in] enable + * Indicates whether to enable or disable. + ******************************************************************************/ +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) +{ + uint32_t volatile * reg; + uint32_t bit; + + switch (channel) { + case emuVmonChannel_AVDD: + reg = &(EMU->VMONAVDDCTRL); + bit = _EMU_VMONAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + reg = &(EMU->VMONALTAVDDCTRL); + bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_DVDD: + reg = &(EMU->VMONDVDDCTRL); + bit = _EMU_VMONDVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_IOVDD0: + reg = &(EMU->VMONIO0CTRL); + bit = _EMU_VMONIO0CTRL_EN_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + reg = &(EMU->VMONIO1CTRL); + bit = _EMU_VMONIO1CTRL_EN_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + reg = &(EMU->VMONBUVDDCTRL); + bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; + break; +#endif + default: + EFM_ASSERT(false); + return; + } + + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the status of a voltage monitor channel. + * + * @param[in] channel + * A VMON channel to get the status for. + * + * @return + * A status of the selected VMON channel. True if the channel is triggered. + ******************************************************************************/ +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) +{ + uint32_t bit; + switch (channel) { + case emuVmonChannel_AVDD: + bit = _EMU_STATUS_VMONAVDD_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + bit = _EMU_STATUS_VMONALTAVDD_SHIFT; + break; + case emuVmonChannel_DVDD: + bit = _EMU_STATUS_VMONDVDD_SHIFT; + break; + case emuVmonChannel_IOVDD0: + bit = _EMU_STATUS_VMONIO0_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + bit = _EMU_STATUS_VMONIO1_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + bit = _EMU_STATUS_VMONBUVDD_SHIFT; + break; +#endif + default: + bit = 0; + EFM_ASSERT(false); + break; + } + + return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; +} +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/***************************************************************************//** + * @brief + * Adjust the bias refresh rate. + * + * @details + * This function is only meant to be used under high-temperature operation on + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will + * increase the typical current consumption. See application note 1027 + * and errata documents for more details. + * + * @param [in] mode + * The new bias refresh rate. + ******************************************************************************/ +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) +{ + uint32_t freq = 0x2u; + bool emuTestLocked = false; + + if (mode == emuBiasMode_1KHz) { + freq = 0x0u; + } + + if (EMU_TESTLOCK == 0x1u) { + emuTestLocked = true; + EMU_TESTLOCK = 0xADE8u; + } + + if (mode == emuBiasMode_Continuous) { + EMU_BIASCONF &= ~0x74u; + } else { + EMU_BIASCONF |= 0x74u; + } + + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; + + if (emuTestLocked) { + EMU_TESTLOCK = 0u; + } +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/***************************************************************************//** + * @brief + * Get temperature in degrees Celsius + * + * @return + * Temperature in degrees Celsius + ******************************************************************************/ +float EMU_TemperatureGet(void) +{ +#if defined(_EMU_TEMP_TEMPLSB_MASK) + return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) + >> _EMU_TEMP_TEMPLSB_SHIFT) + ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +#else + uint32_t val1; + uint32_t val2; + float tempCo; + uint32_t diTemp, diEmu; + + // Calculate calibration temp based on DI page values + diTemp = ((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); + diEmu = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); + tempCo = EMU_TEMPCO_CONST + (diEmu / 100.0f); + + // Read temperature twice to ensure a stable value + do { + val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + } while (val1 != val2); + + return diTemp + tempCo * ((int) diEmu - (int) val1); +#endif +} +#endif // defined(_EMU_TEMP_TEMP_MASK) + +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +/***************************************************************************//** + * @brief + * Enable/disable EFP Direct Mode. + * + * @param[in] enable + * True to enable direct mode. + ******************************************************************************/ +void EMU_EFPDirectModeEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive Decouple voltage. + * + * @details + * Once set, internal LDO will be disabled, and the EMU will control EFP for + * voltage-scaling. Note that because this bit disables the internal LDO + * powering the core, it should not be set until after EFP's DECOUPLE output has + * been configured and enabled. + * + * @param[in] enable + * True to enable EFP to drive Decouple voltage. + ******************************************************************************/ +void EMU_EFPDriveDecoupleSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive DVDD voltage. + * + * @details + * Set this if EFP's DCDC output is powering DVDD supply. This mode assumes that + * internal DCDC is not being used. + * + * @param[in] enable + * True to enable EFP to drive DVDD voltage. + ******************************************************************************/ +void EMU_EFPDriveDvddSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; + } +} +#endif + +#if defined(_EMU_CTRL_HDREGEM2EXITCLIM_MASK) +/***************************************************************************//** + * @brief + * Set to enable HDREG EM2 Exit current limit. + * + * @details + * Limit HDREG max current drawn on EM2 exit by temporarily adjusting its + * output trim so current is pulled from DECOUPLE cap. + * + * @param[in] enable + * True to enable HDREG EM2 Exit current limit. + ******************************************************************************/ +void EMU_HDRegEM2ExitCurrentLimitEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_HDREGEM2EXITCLIM; + } else { + EMU->CTRL_CLR = EMU_CTRL_HDREGEM2EXITCLIM; + } +} +#endif + +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +/***************************************************************************//** + * @brief + * Set the HDREG max current capability limit. + * + * @param[in] current + * HDREG max current capability limit. + ******************************************************************************/ +void EMU_HDRegStopGearSet(EMU_HdregStopGearILmt_TypeDef current) +{ + EMU->CTRL = ((current << _EMU_CTRL_HDREGSTOPGEAR_SHIFT) \ + & _EMU_CTRL_HDREGSTOPGEAR_MASK) | (EMU->CTRL & ~_EMU_CTRL_HDREGSTOPGEAR_MASK); +} +#endif +/** @} (end addtogroup emu) */ +#endif /* __EM_EMU_H */ diff --git a/Libs/platform/emlib/src/em_eusart.c b/Libs/platform/emlib/src/em_eusart.c new file mode 100644 index 0000000..30365bd --- /dev/null +++ b/Libs/platform/emlib/src/em_eusart.c @@ -0,0 +1,1398 @@ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_eusart.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "em_cmu.h" +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +#if defined(EUART_PRESENT) + #define EUSART_REF_VALID(ref) ((ref) == EUART0) + #define EUSART_EM2_CAPABLE(ref) (true) + #define EUSART_RX_FIFO_SIZE 4u +#elif defined(EUSART_PRESENT) + #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1) + #define EUSART_RX_FIFO_SIZE 16u +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ +#if defined(EUSART_DALICFG_DALIEN) +static uint8_t dali_tx_nb_packets[EUSART_COUNT]; +static uint8_t dali_rx_nb_packets[EUSART_COUNT]; +#endif /* EUSART_DALICFG_DALIEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart); + +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit); + +#if defined(EUSART_PRESENT) +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_SpiInit_TypeDef *init); +#endif + +/***************************************************************************//** + * Wait for ongoing sync of register(s) to the low-frequency domain to complete. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param mask A bitmask corresponding to SYNCBUSY register defined bits, + * indicating registers that must complete any ongoing + * synchronization. + ******************************************************************************/ +__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask) +{ + // Wait for any pending previous write operation to have been completed + // in the low-frequency domain. + while ((eusart->SYNCBUSY & mask) != 0U) { + } +} + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs); + +/***************************************************************************//** + * Execute the EUSART peripheral disabling sequence. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes the EUSART when used with the high frequency clock. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to HF. + // The oversampling must not be disabled when using a high frequency clock. + EFM_ASSERT(init->oversampling != eusartOVS0); + + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used with the low frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists and is Low frequency capable. + EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to LF. + // LFXO, LFRCO, ULFRCO can be a clock source in LF. +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + { + CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL; +#if defined(EUART_PRESENT) + if (eusart == EUART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUART0); + } +#endif +#if defined(EUSART_PRESENT) && defined(EUSART0) + if (eusart == EUSART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUSART0); + } +#endif + + EFM_ASSERT( + (clock_source == cmuSelect_ULFRCO) + || (clock_source == cmuSelect_LFXO) + || (clock_source == cmuSelect_LFRCO) + || (clock_source == cmuSelect_EM23GRPACLK) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + || (clock_source == cmuSelect_EM01GRPCCLK) +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + || (clock_source == cmuSelect_EM01GRPACLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK, EM01GRPACLK or EM01GRPCCLK */ +#endif + ); + } +#endif + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(init->oversampling == eusartOVS0); + // The Majority Vote must be disabled when using a low frequency clock. + EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used in IrDA mode with the high or low + * frequency clock. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(irdaInit); + + if (irdaInit->irDALowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(irdaInit->init.baudrate <= 9600); + EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable); + } else { + EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL); +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART when used in SPI mode. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + if (init->master) { + EFM_ASSERT(init->bitRate <= 20000000); + + if (init->advancedSettings) { + EFM_ASSERT(!(init->advancedSettings->prsClockEnable)); + } + } else { + EFM_ASSERT(init->bitRate <= 10000000); + if (init->advancedSettings && init->advancedSettings->forceLoad) { + // If baud-rate is more than 5MHz, a value of 4 is recommended, any values + // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz, + // value of 5 is recommended, values higher than 5 can be used but it may make the load + // error easy to occur. The recommended values for frequency bands should be sufficient + // to work all the time. + EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4) + || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5)); + } + } + + EUSART_SyncInitCommon(eusart, init); +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initializes the EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(daliInit); + + if (daliInit->init.loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should + // be set the same as DALITXDATABITS. + EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT) + == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT)); + } + + if (daliInit->daliLowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(daliInit->init.oversampling == eusartOVS0); + // In LF, max baudrate is 9600. See Note #1. + // but manchester is running at 2x clock 9600 => 4800 + EFM_ASSERT(daliInit->init.baudrate <= 4800); + } else { + EFM_ASSERT(daliInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps + EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit); +} +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the EUSART to its reset state. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart) +{ + // 1. Properly disable the module + EUSART_Disable(eusart); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + // Manual toggling tx_sclk_mst to synchronize handshake + // when switching from SPI master to other modes + // so module is disabling correctly. + uint32_t forcedClkCycle = 4u; + + while (forcedClkCycle--) { + eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK; + eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK; + } +#endif + // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set). + // Set all configurable register to its reset value. + // Note: Program desired settings to all registers that have names ending with CFG in the following sequence: + // a. CFG2 +#if defined(EUSART_PRESENT) + eusart->CFG2 = _EUSART_CFG2_RESETVALUE; +#endif + // b. CFG1 + eusart->CFG1 = _EUSART_CFG1_RESETVALUE; + // c. CFG0 + eusart->CFG0 = _EUSART_CFG0_RESETVALUE; + // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence) + eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE; +#if defined(EUSART_PRESENT) + eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE; +#if defined(EUSART_DALICFG_DALIEN) + eusart->DALICFG = _EUSART_DALICFG_RESETVALUE; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE; + eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE; + eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE; + eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE; + eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE; + eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE; + eusart->IEN = _EUSART_IEN_RESETVALUE; + eusart->IF_CLR = _EUSART_IF_MASK; + + // no need to sync while EN=0, multiple writes can be queued up, + // and the last one will synchronize once EN=1 + eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE; +} + +/***************************************************************************//** + * Enables/disables the EUSART receiver and/or transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable) +{ + uint32_t tmp = 0; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + if (enable == eusartDisable) { + EUSART_Disable(eusart); + } else { + // Enable peripheral to configure Rx and Tx. + eusart->EN_SET = EUSART_EN_EN; + + // Enable or disable Rx and/or Tx + tmp = (enable) + & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK + | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK); + + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + eusart->CMD = tmp; + eusart_sync(eusart, + EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN + | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS); + + // Wait for the status register to be updated. + tmp = 0; + if (_EUSART_CMD_RXEN_MASK & enable) { + tmp |= EUSART_STATUS_RXENS; + } + if (_EUSART_CMD_TXEN_MASK & enable) { + tmp |= EUSART_STATUS_TXENS; + } + while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { + } + } +} + +/***************************************************************************//** + * Receives one 8 bit frame, (or part of 9 bit frame). + * + * @note (1) Handles the case where the RX Fifo Watermark has been set to N frames, + * and when N is greater than one. Attempt to read a frame from the RX Fifo. + * If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU + * interrupt flag is set. If the flag is set, wait to read again until the RXFL + * status flag is set, indicating there are N frames in the RX Fifo, where N + * is equal to the RX watermark level. Once there are N frames in the Fifo, + * read and return one frame. For consecutive N-1 reads there will be data available + * in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating + * delays between reads and sending N data frames in "bursts". + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart) +{ + // If RX watermark has not been configured. + if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) { + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + return (uint8_t)eusart->RXDATA; + } + + // See Note #1. + uint8_t rx_data = eusart->RXDATA; + // If there is underflow i.e Rx data read was unsuccessful + if (eusart->IF & EUSART_IF_RXUF) { + // Wait until data becomes available in Rx fifo + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + // Read Rx data again once data is available in the fifo + rx_data = eusart->RXDATA; + } + + return rx_data; +} + +/***************************************************************************//** + * Receives one 8-9 bit frame with extended information. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart) +{ + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + return (uint16_t)eusart->RXDATA; +} + +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * Transmits one 8-9 bit frame with extended control. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmits one 8-16 bit frame and return received data. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + eusart->TXDATA = (uint32_t)data; + + // Wait for Rx data to be available. + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + return (uint16_t)eusart->RXDATA; +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data) +{ + uint32_t packet; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // First write to TXDATA register should contain 16 LSBs of the TX frame. + // Transmission will not start after this first write. + // Second write to TXDATA register should contain the remaining TX frame bits. + // This second write will result in start of transmission. + packet = (data >> (index * 16)); + // To ensure compatibility with future devices, always write bits [31:16] to 0. + packet &= 0x0000FFFF; + eusart->TXDATA = packet; + } +} + +/***************************************************************************//** + * Receive one frame. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart) +{ + uint32_t data = 0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // When receiving a frame that has more than 16 databits, + // RXDATA register needs to be read twice: + // First read will provide 16 LSBs of the received frame. + // Second read will provide the remaining RX frame bits. + data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16)); + } + return data; +} + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configures the baudrate (or as close as possible to a specified baudrate) + * depending on the current mode of the EU(S)ART peripheral. + * + * @note (1) When the oversampling is disabled, the peripheral clock frequency + * must be at least three times higher than the chosen baud rate. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate) +{ + uint32_t clkdiv; + uint8_t oversample = 0; + + // Prevent dividing by 0. + EFM_ASSERT(baudrate); + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Get the current frequency. + if (!refFreq) { + refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + } + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) { + EFM_ASSERT(baudrate <= refFreq); + + EUSART_Enable_TypeDef txrxEnStatus = eusartDisable; + bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true; + clkdiv = refFreq / baudrate - 1UL; + + // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV), + // the resulting spi master bus clock will be undefined because the result will be truncated. + EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT)); + + if (wasEnabled) { + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + + // Save the state of the reveiver and transmitter before disabling the peripheral. + if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnable; + } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) { + txrxEnStatus = eusartEnableRx; + } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnableTx; + } else { + EFM_ASSERT(false); + } + + // Disable the eusart to be able to modify the CFG2 register. + EUSART_Disable(eusart); + } + + // In Synchronous mode the clock divider that is managing the bitRate + // is located inside the sdiv bitfield of the CFG2 register instead of + // the CLKDIV register combined with the oversample setting for asynchronous mode. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK); + + if (wasEnabled) { + EUSART_Enable(eusart, txrxEnStatus); + } + } else // In asynchronous mode (ex: UART) +#endif + { + // The peripheral must be enabled to configure the baud rate. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + baudrate *= 2; + } +#endif + + /* + * Use integer division to avoid forcing in float division + * utils, and yet keep rounding effect errors to a minimum. + * + * CLKDIV is given by: + * + * CLKDIV = 256 * (fUARTn/(oversample * br) - 1) + * or + * CLKDIV = (256 * fUARTn)/(oversample * br) - 256 + * + * Since fUARTn may be derived from HFCORECLK, consider the overflow when + * using integer arithmetic. + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fUARTn) may become higher than the maximum 32 bit + * integer. Yet, the dividend should be evaluated first before dividing + * to get as small rounding effects as possible. + * Also, harsh restrictions on the maximum fUARTn value should not be made. + * + * Since the last 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula: + * + * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32 + * + * and calculate 1/8 of CLKDIV first. This allows for fUARTn + * up to 128 MHz without overflowing a 32 bit value. + */ + + // Map oversampling. + switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) { + case eusartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case eusartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case eusartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case eusartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + case eusartOVS0: + EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1. + oversample = 1; + break; + + default: + // Invalid input + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + // Calculate and set the CLKDIV with fractional bits. + clkdiv = (32 * refFreq) / (baudrate * oversample); + clkdiv -= 32; + clkdiv *= 8; + + // Verify that the resulting clock divider is within limits. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits. + clkdiv &= _EUSART_CLKDIV_MASK; + + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + eusart->CLKDIV = clkdiv; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + } + } +} + +/***************************************************************************//** + * Gets the current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart) +{ + uint32_t freq; + uint32_t div = 1; + uint32_t br = 0; + EUSART_OVS_TypeDef ovs = eusartOVS0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) { + div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT; + br = freq / (div + 1); + } + // In asynchronous mode (ex: UART) + else +#endif + { + div = eusart->CLKDIV; + ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK); + br = EUSART_AsyncBaudrateCalc(freq, div, ovs); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + br /= 2; + } +#endif + } + + return br; +} + +/***************************************************************************//** + * Enable/Disable reception operations until the configured start frame is + * received. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + eusart->CMD_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + + tmp = 0u; + if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_RXBLOCK; + } + while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Enables/Disables the tristating of the transmitter output. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + eusart->CMD = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + + tmp = 0u; + if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_TXTRI; + } + while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Initializes the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // The peripheral must be enabled to configure the PRS trigger. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK); +#else + +#if defined(EUSART0) + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK); + } +#endif +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK); + } +#endif +#endif + + tmp = ((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + + eusart->TRIGCTRL_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); + + tmp = ~((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + eusart->TRIGCTRL_CLR = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Gets the clock associated to the specified EUSART instance. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Clock corresponding to the eusart. + ******************************************************************************/ +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart) +{ + CMU_Clock_TypeDef clock; + +#if defined(EUART0) + if (eusart == EUART0) { + clock = cmuClock_EUART0; + } +#endif +#if defined(EUSART0) + if (eusart == EUSART0) { + clock = cmuClock_EUSART0; + } +#endif +#if defined(EUSART1) + else if (eusart == EUSART1) { + clock = cmuClock_EUSART1; + } +#endif +#if defined(EUSART2) + else if (eusart == EUSART2) { + clock = cmuClock_EUSART2; + } +#endif +#if defined(EUSART3) + else if (eusart == EUSART3) { + clock = cmuClock_EUSART3; + } +#endif +#if defined(EUSART4) + else if (eusart == EUSART4) { + clock = cmuClock_EUSART4; + } +#endif + else { + EFM_ASSERT(0); + return (CMU_Clock_TypeDef)0u; + } + return clock; +} + +/***************************************************************************//** + * Initializes the EUSART with asynchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + * @param irdaInit Pointer to IrDA initialization structure. + ******************************************************************************/ +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK + | _EUSART_FRAMECFG_STOPBITS_MASK + | _EUSART_FRAMECFG_PARITY_MASK)) + | (uint32_t)(init->databits) + | (uint32_t)(init->parity) + | (uint32_t)(init->stopbits); + + // Configure global configuration register 0. + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK + | _EUSART_CFG0_LOOPBK_MASK + | _EUSART_CFG0_MVDIS_MASK)) + | (uint32_t)(init->oversampling) + | (uint32_t)(init->loopbackEnable) + | (uint32_t)(init->majorityVote); + + if (init->baudrate == 0) { + eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN; + } + + if (init->advancedSettings) { + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK + | _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK + | _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK + | _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK)) + | (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT) + | (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT) + | (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK)) + | (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT) + | (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT); + + // Configure global configuration register 1. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK + | _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT); + + if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts + || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) { + eusart->CFG1 |= EUSART_CFG1_CTSEN; + } + // Enable RTS route pin if necessary. CTS is an input so it is enabled by default. + if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts) + || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) { +#if defined(EUART0) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } else { +#if defined(EUART0) + GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } + eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame; + if (init->advancedSettings->startFrame) { + eusart->CFG1 |= EUSART_CFG1_SFUBRX; + } + if (init->advancedSettings->prsRxEnable) { + eusart->CFG1 |= EUSART_CFG1_RXPRSEN; + // Configure PRS channel as input data line for EUSART. +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK); +#elif defined(EUSART_PRESENT) + + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif +#endif + } + + // Configure global configuration timing register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK) + | (uint32_t)(init->advancedSettings->autoTxDelay); + } + + if (irdaInit) { + if (irdaInit->irDALowFrequencyEnable) { + eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN); + } else { + // Configure IrDA HF configuration register. + eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFFILT_MASK)) + | (uint32_t)(EUSART_IRHFCFG_IRHFEN) + | (uint32_t)(irdaInit->irDAPulseWidth) + | (uint32_t)(irdaInit->irDARxFilterEnable); + } + } + +#if defined(EUSART_DALICFG_DALIEN) + // DALI-specific configuration section + if (daliInit) { + if (init->loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1. + eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT; + } + + if (EUSART_REF_VALID(eusart)) { + uint8_t index = EUSART_NUM(eusart); + + // keep track of the number of 16-bits packet to send + if (daliInit->TXdatabits <= eusartDaliTxDataBits16) { + dali_tx_nb_packets[index] = 1; + } else { + dali_tx_nb_packets[index] = 2; + } + + // keep track of the number of 16-bits packet to receive + if (daliInit->RXdatabits <= eusartDaliRxDataBits16) { + dali_rx_nb_packets[index] = 1; + } else { + dali_rx_nb_packets[index] = 2; + } + } + + // Configure the numbers of bits per TX and RX frames + eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK + | _EUSART_DALICFG_DALIRXDATABITS_MASK)) + | daliInit->TXdatabits + | daliInit->RXdatabits; + eusart->DALICFG_SET = EUSART_DALICFG_DALIEN; + } +#else + (void)(daliInit); +#endif /* EUSART_DALICFG_DALIEN */ + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Configure the baudrate if auto baud detection is not used. + if (init->baudrate) { + EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate); + } + + // Finally enable the Rx and/or Tx channel (as specified). + EUSART_Enable(eusart, init->enable); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART with synchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + EUSART_SpiInit_TypeDef const *init) +{ + void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization. + + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK + | _EUSART_CFG2_CLKPOL_MASK + | _EUSART_CFG2_CLKPHA_MASK + | _EUSART_CFG2_FORCELOAD_MASK)) + | (uint32_t)(init->master) + | (uint32_t)(init->clockMode) + | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default. + + if (advancedSetting_ptr) { + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK + | _EUSART_CFG2_AUTOCS_MASK + | _EUSART_CFG2_AUTOTX_MASK + | _EUSART_CFG2_CSINV_MASK + | _EUSART_CFG2_CLKPRSEN_MASK)) + | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT) + | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT) + | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT) + | (uint32_t)(init->advancedSettings->csPolarity) + | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT); + + // Only applicable to EM2 (low frequency) capable EUSART instances. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK + | _EUSART_CFG1_TXFIW_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT); + } + + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK + | _EUSART_CFG0_LOOPBK_MASK)) + | (uint32_t)(_EUSART_CFG0_SYNC_SYNC) + | (uint32_t)(init->loopbackEnable); + + if (advancedSetting_ptr) { + eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK); + eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT; + + // Configure global configurationTiming register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK + | _EUSART_TIMINGCFG_CSHOLD_MASK + | _EUSART_TIMINGCFG_ICS_MASK + | _EUSART_TIMINGCFG_SETUPWINDOW_MASK)) + | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT) + & _EUSART_TIMINGCFG_CSSETUP_MASK) + | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT) + & _EUSART_TIMINGCFG_CSHOLD_MASK) + | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT) + & _EUSART_TIMINGCFG_ICS_MASK) + | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT) + & _EUSART_TIMINGCFG_SETUPWINDOW_MASK) + ; + } + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK)) + | (uint32_t)(init->databits); + + if (advancedSetting_ptr) { + eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK); + + if (init->advancedSettings->prsRxEnable) { + //Configure PRS channel as input data line for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif + } + + if (init->advancedSettings->prsClockEnable) { + //Configure PRS channel as SCLK input for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK); + } +#endif + } + } + + // Set baudrate for synchronous operation mode. + EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate); + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Finally enable the Rx and/or Tx channel (as specified). + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization. + eusart->CMD = (uint32_t)init->enable; + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} +#endif + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate when the module is in UART mode. + * + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * @param clkdiv Clock division factor to be used. + * @param ovs Oversampling to be used. + * + * @return Computed baudrate from given settings. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + // Out of bound clkdiv. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // Mask out unused bits + clkdiv &= _EUSART_CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * Baudrate in is given by: + * + * br = fUARTn/(oversample * (1 + (CLKDIV / 256))) + * or + * br = (256 * fUARTn)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case eusartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case eusartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case eusartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + case eusartOVS4: + oversample = 1; + factor = 256 / 4; + break; + + case eusartOVS0: + oversample = 1; + factor = 256; + break; + + default: + return 0u; + break; + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fUARTn) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fUARTn value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum + // 32 bit value. However, factor * remainder can become larger than 32-bit + // because of the size of _EUSART_CLKDIV_DIV_MASK on some families. + br = (uint32_t) (factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400. + */ + br += (uint32_t) ((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * Perform EUSART Module disablement - resetting all internal flops/FSM. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart) +{ + if (eusart->EN & _EUSART_EN_EN_MASK) { + // This step should be skipped especially in Synchronous Slave mode when + // external SCLK is not running and CS is active +#if defined(EUSART_PRESENT) + if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK)) +#endif + { + // General Programming Guideline to properly disable the module: + // 1a. Disable TX and RX using TXDIS and RXDIS cmd + eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS; + // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low; + eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS)); + // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low + while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) { + } + } +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + eusart->CLKDIV = eusart->CLKDIV; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + + // Read data until FIFO is emptied + // but taking care not to underflow the receiver + while (eusart->STATUS & EUSART_STATUS_RXFL) { + eusart->RXDATA; + } +#endif + + eusart->EN_CLR = EUSART_EN_EN; + +#if defined(_EUSART_EN_DISABLING_MASK) + // 2. Polling for EUSARTn_EN.DISABLING = 0. + while (eusart->EN & _EUSART_EN_DISABLING_MASK) { + } +#endif + } +} + +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ diff --git a/Libs/platform/emlib/src/em_gpcrc.c b/Libs/platform/emlib/src/em_gpcrc.c new file mode 100644 index 0000000..7c55113 --- /dev/null +++ b/Libs/platform/emlib/src/em_gpcrc.c @@ -0,0 +1,138 @@ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_common.h" +#include "em_gpcrc.h" +#include "sl_assert.h" + +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpcrc + * @{ + ******************************************************************************/ + +/******************************************************************************* + *************************** GLOBAL FUNCTIONS ****************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize the General Purpose Cyclic Redundancy Check (GPCRC) module. + * + * @details + * Use this function to configure the operational parameters of the GPCRC, + * such as the polynomial to use and how the input should be preprocessed + * before entering the CRC calculation. + * + * @note + * This function will not copy the initialization value to the data register + * to prepare for a new CRC calculation. Either call + * @ref GPCRC_Start before each calculation or by use the + * autoInit functionality. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the GPCRC. + ******************************************************************************/ +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init) +{ + uint32_t polySelect; + uint32_t revPoly = 0; + + if (init->crcPoly == 0x04C11DB7) { + polySelect = GPCRC_CTRL_POLYSEL_CRC32; + } else { + // If not using the fixed CRC-32 polynomial, use 16-bit. + EFM_ASSERT((init->crcPoly & 0xFFFF0000UL) == 0U); +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + polySelect = GPCRC_CTRL_POLYSEL_CRC16; +#else + polySelect = GPCRC_CTRL_POLYSEL_16; +#endif + revPoly = SL_RBIT16(init->crcPoly); + } + +#if defined(GPCRC_EN_EN) + if (init->enable) { + gpcrc->EN_SET = GPCRC_EN_EN; + } else { + gpcrc->EN_CLR = GPCRC_EN_EN; + } + + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect); +#else + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect + | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT)); +#endif + +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + if (polySelect == GPCRC_CTRL_POLYSEL_CRC16) { +#else + if (polySelect == GPCRC_CTRL_POLYSEL_16) { +#endif + // Set the CRC polynomial value. + gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK; + } + + // Load the CRC initialization value to GPCRC_INIT. + gpcrc->INIT = init->initValue; +} + +/***************************************************************************//** + * @brief + * Reset GPCRC registers to the hardware reset state. + * + * @note + * The data registers are not reset by this function. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + ******************************************************************************/ +void GPCRC_Reset(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CTRL = _GPCRC_CTRL_RESETVALUE; + gpcrc->POLY = _GPCRC_POLY_RESETVALUE; + gpcrc->INIT = _GPCRC_INIT_RESETVALUE; +} + +/** @} (end addtogroup gpcrc) */ + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_gpio.c b/Libs/platform/emlib/src/em_gpio.c new file mode 100644 index 0000000..9c4ddf4 --- /dev/null +++ b/Libs/platform/emlib/src/em_gpio.c @@ -0,0 +1,452 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + * devices. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_gpio.h" + +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpio GPIO - General Purpose Input/Output + * @brief General Purpose Input/Output (GPIO) API + * @details + * This module contains functions to control the GPIO peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration + * and direct pin manipulation and sensing as well as routing for peripheral + * pin connections. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the pin typically usable in assert statements. */ +#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) +#define GPIO_STRENGTH_VALID(strength) (!((strength) \ + & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ + | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Sets the pin location of the debug pins (Serial Wire interface). + * + * @note + * Changing the pins used for debugging uncontrolled, may result in a lockout. + * + * @param[in] location + * The debug pin location to use (0-3). + ******************************************************************************/ +void GPIO_DbgLocationSet(unsigned int location) +{ +#if defined (_GPIO_ROUTE_SWLOCATION_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) + | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); +#elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) + | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); +#else + (void)location; +#endif +} + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +/***************************************************************************//** + * @brief + * Sets drive mode for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] mode + * Drive mode to use for the port. + ******************************************************************************/ +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) + | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +/***************************************************************************//** + * @brief + * Sets the drive strength for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] strength + * The drive strength to use for the port. + ******************************************************************************/ +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, + GPIO_DriveStrength_TypeDef strength) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); + BUS_RegMaskedWrite(&GPIO->P[port].CTRL, + _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, + strength); +} +#endif + +/***************************************************************************//** + * @brief + * Configure the GPIO external pin interrupt. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * On series 0 devices, the pin number parameter is not used. The + * pin number used on these devices is hardwired to the interrupt with the + * same number. @n + * On series 1 devices, the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The interrupt number to trigger. + * + * @param[in] risingEdge + * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. + * + * @param[in] fallingEdge + * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable) +{ +#if defined (_GPIO_EXTIPSELH_MASK) + uint32_t tmp = 0; +#endif +#if !defined(_GPIO_EXTIPINSELL_MASK) + (void)pin; +#endif + + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_EXTIPINSELL_MASK) + EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); +#endif + + /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls + * pins 8-15 of the interrupt configuration. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPSELL, + _GPIO_EXTIPSELL_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), + (uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); + } else { +#if defined(_GPIO_EXTIPSELH_MASK) + tmp = intNo - 8; +#if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL8_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#else +#error Invalid GPIO_EXTIPINSELH bit fields +#endif +#endif /* #if defined(_GPIO_EXTIPSELH_MASK) */ + } + +#if defined(_GPIO_EXTIPINSELL_MASK) + + /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls + * interrupt 8-15 of the interrupt/pin number mapping. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, + _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); + } else { +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#endif +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#endif + } +#endif + + /* Enable/disable the rising edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); + + /* Enable/disable the falling edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); + + /* Clear any pending interrupt. */ + GPIO_IntClear(1 << intNo); + + /* Finally enable/disable interrupt. */ + BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); +} + +#if _SILICON_LABS_32B_SERIES > 0 +/***************************************************************************//** + * @brief + * Configure EM4WU pins as external level-sensitive interrupts. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * The selected port/pin must be mapped to an existant EM4WU interrupt. + * Each EM4WU signal is connected to a fixed pin. + * Refer to the Alternate Function Table in the device Datasheet for the + * location of each EM4WU signal. For example, on xG22 device, the interrupt + * of EM4WU6 is fixed to pin PC00. + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The EM4WU interrupt number to trigger. + * + * @param[in] polarity + * true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // GPIO pin mode set. + GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity); + + // Enable EM4WU function and set polarity + uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + + GPIO_EM4EnablePinWakeup(pinmask, polarityMask); + + // Enable EM4WU interrupt +#if defined(_SILICON_LABS_32B_SERIES_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); +#else + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Set the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @param[in] mode + * The desired pin mode. + * + * @param[in] out + * A value to set for the pin in the DOUT register. The DOUT setting is important for + * some input mode configurations to determine the pull-up/down direction. + ******************************************************************************/ +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + /* If disabling a pin, do not modify DOUT to reduce the chance of */ + /* a glitch/spike (may not be sufficient precaution in all use cases). */ + if (mode != gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } + + /* There are two registers controlling the pins for each port. The MODEL + * register controls pins 0-7 and MODEH controls pins 8-15. */ + if (pin < 8) { + // Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C) + // Compiler assigned 8 bits for enum. Same thing for other branch. + BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); + } else { + BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4)); + } + + if (mode == gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } +} + +/***************************************************************************//** + * @brief + * Get the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @return + * The pin mode. + ******************************************************************************/ +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + if (pin < 8) { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); + } else { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); + } +} + +#if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin wake-up from EM4. When the function exits, + * EM4 mode can be safely entered. + * + * @note + * It is assumed that the GPIO pin modes are set correctly. + * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. + * + * @param[in] pinmask + * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. + * See Reference Manuals for a pinmask to the GPIO port/pin mapping. + * @param[in] polaritymask + * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. + * See Reference Manuals for pinmask-to-GPIO port/pin mapping. + *****************************************************************************/ +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); + +#if defined(_GPIO_EM4WUPOL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); + GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ + GPIO->EM4WUPOL |= pinmask & polaritymask; +#elif defined(_GPIO_EXTILEVEL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); + GPIO->EXTILEVEL &= ~pinmask; + GPIO->EXTILEVEL |= pinmask & polaritymask; +#endif + GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ + + GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ + +#if defined(_GPIO_CMD_EM4WUCLR_MASK) + GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ +#else + GPIO_IntClear(pinmask); +#endif +} +#endif + +/** @} (end addtogroup gpio) */ + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_i2c.c b/Libs/platform/emlib/src/em_i2c.c new file mode 100644 index 0000000..dde3240 --- /dev/null +++ b/Libs/platform/emlib/src/em_i2c.c @@ -0,0 +1,940 @@ +/***************************************************************************//** + * @file + * @brief Inter-integrated Circuit (I2C) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_i2c.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" + + #include + +/***************************************************************************//** + * @addtogroup i2c I2C - Inter-Integrated Circuit + * @brief Inter-integrated Circuit (I2C) Peripheral API + * @details + * This module contains functions to control the I2C peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C + * buses with the lowest energy consumption possible. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the I2C register block pointer reference for assert statements. */ +#if (I2C_COUNT == 1) +#define I2C_REF_VALID(ref) ((ref) == I2C0) +#elif (I2C_COUNT == 2) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) +#elif (I2C_COUNT == 3) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) +#elif (I2C_COUNT == 4) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2) || ((ref) == I2C3)) +#endif + +/** Error flags indicating that the I2C transfer has failed. */ +/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ +/* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ +/* RXUF is only likely to occur with the software if using a debugger peeking into */ +/* the RXDATA register. Therefore, those types of faults are ignored. */ +#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) +#define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) + +/* Maximum I2C transmission rate constant. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY) +#define I2C_CR_MAX 8 +#else +#define I2C_CR_MAX 4 +#endif +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define I2C_CR_MAX 8 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_CR_MAX 8 +#else +#warning "Max I2C transmission rate constant is not defined" +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Master mode transfer states. */ +typedef enum { + i2cStateStartAddrSend, /**< Send start + (first part of) address. */ + i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ + i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ + i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ + i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ + i2cStateDataSend, /**< Send data. */ + i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ + i2cStateWFData, /**< Wait for data. */ + i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ + i2cStateDone /**< Transfer completed successfully. */ +} I2C_TransferState_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Structure used to store state information on an ongoing master mode transfer. */ +typedef struct { + /** Current state. */ + I2C_TransferState_TypeDef state; + + /** Result return code. */ + I2C_TransferReturn_TypeDef result; + + /** Offset in the current sequence buffer. */ + uint16_t offset; + + /* Index to the current sequence buffer in use. */ + uint8_t bufIndx; + + /** Reference to the I2C transfer sequence definition provided by the user. */ + I2C_TransferSeq_TypeDef *seq; +} I2C_Transfer_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ***************************** LOCAL DATA *******^************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** + * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined + * index (0x3) to reflect a default setting just in case. + */ +static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; + +/** A transfer state information for an ongoing master mode transfer. */ +static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Empty received data buffer. + ******************************************************************************/ +static void flushRx(I2C_TypeDef *i2c) +{ + while (i2c->STATUS & I2C_STATUS_RXDATAV) { + i2c->RXDATA; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current configured I2C bus frequency. + * + * @details + * This frequency is only relevant when acting as master. + * + * @note + * The actual frequency is a real number, this function returns a rounded + * down (truncated) integer value. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @return + * The current I2C frequency in Hz. + ******************************************************************************/ +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) +{ + uint32_t freqHfper = 0; + uint32_t n; + + /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + if (i2c == I2C0) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) + >> _I2C_CTRL_CLHR_SHIFT]; + return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); +} + +/***************************************************************************//** + * @brief + * Set the I2C bus frequency. + * + * @details + * The bus frequency is only relevant when acting as master. The bus + * frequency should not be set higher than the maximum frequency accepted by the + * slowest device on the bus. + * + * Notice that, due to asymmetric requirements on low and high I2C clock + * cycles in the I2C specification, the maximum frequency allowed + * to comply with the specification may be somewhat lower than expected. + * + * See the reference manual, details on I2C clock generation, + * for maximum allowed theoretical frequencies for different modes. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] freqRef + * An I2C reference clock frequency in Hz that will be used. If set to 0, + * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual + * configured value has the consequence of reducing the real I2C frequency. + * + * @param[in] freqScl + * A bus frequency to set (bus speed may be lower due to integer + * prescaling). Safe (according to the I2C specification) maximum frequencies for + * standard fast and fast+ modes are available using I2C_FREQ_ defines. + * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) + * The slowest slave device on a bus must always be considered. + * + * @param[in] i2cMode + * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, + * make sure all devices on the bus support the specified mode. Using a + * non-standard ratio is useful to achieve a higher bus clock in fast and + * fast+ modes. + ******************************************************************************/ +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode) +{ + uint32_t n, minFreq, denominator; + int32_t div; + + /* Avoid dividing by 0. */ + EFM_ASSERT(freqScl); + if (!freqScl) { + return; + } + + /* Ensure mode is valid */ + i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; + + /* Set the CLHR (clock low-to-high ratio). */ + i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; + BUS_RegMaskedWrite(&i2c->CTRL, + _I2C_CTRL_CLHR_MASK, + i2cMode << _I2C_CTRL_CLHR_SHIFT); + + if (freqRef == 0) { + if (i2c == I2C0) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + } + + /* Check the minumum HF peripheral clock. */ + minFreq = UINT_MAX; + if (i2c->CTRL & I2C_CTRL_SLAVE) { + switch (i2cMode) { + case i2cClockHLRStandard: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 4200000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 2000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 2000000; break; +#endif + case i2cClockHLRAsymetric: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 11000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 5000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 5000000; break; +#endif + case i2cClockHLRFast: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 24400000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 14000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 14000000; break; +#endif + default: + /* MISRA requires the default case. */ + break; + } + } else { + /* For master mode, platform 1 and 2 share the same + minimum frequencies. */ + switch (i2cMode) { + case i2cClockHLRStandard: + minFreq = 2000000; break; + case i2cClockHLRAsymetric: + minFreq = 9000000; break; + case i2cClockHLRFast: + minFreq = 20000000; break; + default: + /* MISRA requires default case */ + break; + } + } + + /* Frequency most be larger-than. */ + EFM_ASSERT(freqRef > minFreq); + + /* SCL frequency is given by: + * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) + * + * Therefore, + * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 + * + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[i2cMode]; + denominator = n * freqScl; + + /* Explicitly ensure denominator is never zero. */ + if (denominator == 0) { + EFM_ASSERT(0); + return; + } + /* Perform integer division so that div is rounded up. */ + div = (int32_t)(((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) + / denominator) - 1); + EFM_ASSERT(div >= 0); + EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); + + /* The clock divisor must be at least 1 in slave mode according to the reference */ + /* manual (in which case there is normally no need to set the bus frequency). */ + if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { + div = 1; + } + i2c->CLKDIV = (uint32_t)div; +} + +/***************************************************************************//** + * @brief + * Enable/disable I2C. + * + * @note + * After enabling the I2C (from being disabled), the I2C is in BUSY state. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void I2C_Enable(I2C_TypeDef *i2c, bool enable) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + +#if defined (_I2C_EN_MASK) + BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Initialize I2C. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] init + * A pointer to the I2C initialization structure. + ******************************************************************************/ +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + + i2c->IEN = 0; + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Set SLAVE select mode. */ + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); + + I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); + + I2C_Enable(i2c, init->enable); +} + +/***************************************************************************//** + * @brief + * Reset I2C to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + ******************************************************************************/ +void I2C_Reset(I2C_TypeDef *i2c) +{ + // Cancel ongoing operations and clear TX buffer + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; + i2c->CTRL = _I2C_CTRL_RESETVALUE; + i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; + i2c->SADDR = _I2C_SADDR_RESETVALUE; + i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; + i2c->IEN = _I2C_IEN_RESETVALUE; +#if defined (_I2C_EN_EN_MASK) + i2c->EN = _I2C_EN_RESETVALUE; +#endif + + // Empty received data buffer + flushRx(i2c); + I2C_IntClear(i2c, _I2C_IF_MASK); + /* Do not reset the route register; setting should be done independently. */ +} + +// ***************************************************************************** +/// @brief +/// Continue an initiated I2C transfer (single master mode only). +/// +/// @details +/// This function is used repeatedly after a I2C_TransferInit() to +/// complete a transfer. It may be used in polled mode as the below example +/// shows: +/// @code{.c} +/// I2C_TransferReturn_TypeDef ret; +/// +/// // Do a polled transfer +/// ret = I2C_TransferInit(I2C0, seq); +/// while (ret == i2cTransferInProgress) +/// { +/// ret = I2C_Transfer(I2C0); +/// } +/// @endcode +/// It may also be used in interrupt driven mode, where this function is invoked +/// from the interrupt handler. Notice that, if used in interrupt mode, NVIC +/// interrupts must be configured and enabled for the I2C bus used. I2C +/// peripheral specific interrupts are managed by this software. +/// +/// @note +/// Only single master mode is supported. +/// +/// @param[in] i2c +/// A pointer to the I2C peripheral register block. +/// +/// @return +/// Returns status for an ongoing transfer. +/// @li #i2cTransferInProgress - indicates that transfer not finished. +/// @li #i2cTransferDone - transfer completed successfully. +/// @li otherwise some sort of error has occurred. +/// +// ***************************************************************************** +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) +{ + uint32_t tmp; + uint32_t pending; + I2C_Transfer_TypeDef *transfer; + I2C_TransferSeq_TypeDef *seq; + bool finished = false; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + seq = transfer->seq; + while (!finished) { + pending = i2c->IF; + + /* If some sort of fault, abort transfer. */ + if (pending & I2C_IF_ERRORS) { + if (pending & I2C_IF_ARBLOST) { + /* If an arbitration fault, indicates either a slave device */ + /* not responding as expected, or other master which is not */ + /* supported by this software. */ + transfer->result = i2cTransferArbLost; + } else if (pending & I2C_IF_BUSERR) { + /* A bus error indicates a misplaced start or stop, which should */ + /* not occur in master mode controlled by this software. */ + transfer->result = i2cTransferBusErr; + } + + /* Ifan error occurs, it is difficult to know */ + /* an exact cause and how to resolve. It will be up to a wrapper */ + /* to determine how to handle a fault/recovery if possible. */ + transfer->state = i2cStateDone; + break; + } + + switch (transfer->state) { + /***************************************************/ + /* Send the first start+address (first byte if 10 bit). */ + /***************************************************/ + case i2cStateStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; + + /* In 10 bit address mode, the address following the first */ + /* start always indicates write. */ + } else { + tmp = (uint32_t)(seq->addr) & 0xfe; + + if (seq->flags & I2C_FLAG_READ) { + /* Indicate read request */ + tmp |= 1; + } + } + + transfer->state = i2cStateAddrWFAckNack; + i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ + i2c->CMD = I2C_CMD_START; + finished = true; + break; + + /*******************************************************/ + /* Wait for ACK/NACK on the address (first byte if 10 bit). */ + /*******************************************************/ + case i2cStateAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If a 10 bit address, send the 2nd byte of the address. */ + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + transfer->state = i2cStateAddrWF2ndAckNack; + i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; + } else { + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateWFData; + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + } + finished = true; + break; + + /******************************************************/ + /* Wait for ACK/NACK on the second byte of a 10 bit address. */ + /******************************************************/ + case i2cStateAddrWF2ndAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If using a plain read sequence with a 10 bit address, switch to send */ + /* a repeated start. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateRStartAddrSend; + } + /* Otherwise, expected to write 0 or more bytes. */ + else { + transfer->state = i2cStateDataSend; + } + continue; + } + finished = true; + break; + + /*******************************/ + /* Send a repeated start+address */ + /*******************************/ + case i2cStateRStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (uint32_t)((seq->addr >> 8) & 0x06) | 0xf0; + } else { + tmp = (uint32_t)(seq->addr & 0xfe); + } + + /* If this is a write+read combined sequence, read is about to start. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + /* Indicate a read request. */ + tmp |= 1; + /* If reading only one byte, prepare the NACK now before START command. */ + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } + + transfer->state = i2cStateRAddrWFAckNack; + /* The START command has to be written first since repeated start. Otherwise, */ + /* data would be sent first. */ + i2c->CMD = I2C_CMD_START; + i2c->TXDATA = tmp; + + finished = true; + break; + + /**********************************************************************/ + /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ + /**********************************************************************/ + case i2cStateRAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateWFData; + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + finished = true; + break; + + /*****************************/ + /* Send a data byte to the slave */ + /*****************************/ + case i2cStateDataSend: + /* Reached end of data buffer. */ + if (transfer->offset >= seq->buf[transfer->bufIndx].len) { + /* Move to the next message part. */ + transfer->offset = 0; + transfer->bufIndx++; + + /* Send a repeated start when switching to read mode on the 2nd buffer. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateRStartAddrSend; + continue; + } + + /* Only writing from one buffer or finished both buffers. */ + if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + finished = true; + break; + } + + /* Reprocess in case the next buffer is empty. */ + continue; + } + + /* Send byte. */ + i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); + transfer->state = i2cStateDataWFAckNack; + finished = true; + break; + + /*********************************************************/ + /* Wait for ACK/NACK from the slave after sending data to it. */ + /*********************************************************/ + case i2cStateDataWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + transfer->state = i2cStateDataSend; + continue; + } + finished = true; + break; + + /****************************/ + /* Wait for data from slave */ + /****************************/ + case i2cStateWFData: + if (pending & I2C_IF_RXDATAV) { + uint8_t data; + unsigned int rxLen = seq->buf[transfer->bufIndx].len; + + /* Must read out data not to block further progress. */ + data = (uint8_t)(i2c->RXDATA); + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)) + // Errata I2C_E303. I2C Fails to Indicate New Incoming Data. + uint32_t status = i2c->STATUS; + // look for invalid RXDATAV = 0 and RXFULL = 1 condition + if (((status & I2C_IF_RXDATAV) == 0) & ((status & I2C_IF_RXFULL) != 0)) { + // Performing a dummy read of the RXFIFO (I2C_RXDATA). + // This restores the expected RXDATAV = 1 and RXFULL = 0 condition. + (void)i2c->RXDATA; + // The dummy read will also set the RXUFIF flag bit, which should be ignored and cleared. + I2C_IntClear(i2c, I2C_IF_RXUF); + } +#endif + + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif + + /* Make sure that there is no storing beyond the end of the buffer (just in case). */ + if (transfer->offset < rxLen) { + seq->buf[transfer->bufIndx].data[transfer->offset++] = data; + } + + /* If all requested data is read, the sequence should end. */ + if (transfer->offset >= rxLen) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else { + /* Send ACK and wait for the next byte. */ + i2c->CMD = I2C_CMD_ACK; + + if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { + /* If receiving more than one byte and this is the next + to last byte, transmit the NACK now before receiving + the last byte. */ + i2c->CMD = I2C_CMD_NACK; + } + } + } + finished = true; + break; + + /***********************************/ + /* Wait for STOP to have been sent */ + /***********************************/ + case i2cStateWFStopSent: + if (pending & I2C_IF_MSTOP) { + I2C_IntClear(i2c, I2C_IF_MSTOP); + transfer->state = i2cStateDone; + } + finished = true; + break; + + /******************************/ + /* An unexpected state, software fault */ + /******************************/ + default: + transfer->result = i2cTransferSwFault; + transfer->state = i2cStateDone; + finished = true; + break; + } + } + + if (transfer->state == i2cStateDone) { + /* Disable interrupt sources when done. */ + i2c->IEN = 0; + + /* Update the result unless a fault has already occurred. */ + if (transfer->result == i2cTransferInProgress) { + transfer->result = i2cTransferDone; + } + } + /* Until transfer is done, keep returning i2cTransferInProgress. */ + else { + return i2cTransferInProgress; + } + + return transfer->result; +} + +/***************************************************************************//** + * @brief + * Prepare and start an I2C transfer (single master mode only). + * + * @details + * This function must be invoked to start an I2C transfer + * sequence. To complete the transfer, I2C_Transfer() must + * be used either in polled mode or by adding a small driver wrapper using + * interrupts. + * + * @note + * Only single master mode is supported. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] seq + * A pointer to the sequence structure defining the I2C transfer to take place. The + * referenced structure must exist until the transfer has fully completed. + * + * @return + * Returns the status for an ongoing transfer: + * @li #i2cTransferInProgress - indicates that the transfer is not finished. + * @li Otherwise, an error has occurred. + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq) +{ + I2C_Transfer_TypeDef *transfer; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + EFM_ASSERT(seq); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + /* Check if in a busy state. Since this software assumes a single master, */ + /* issue an abort. The BUSY state is normal after a reset. */ + if (i2c->STATE & I2C_STATE_BUSY) { + i2c->CMD = I2C_CMD_ABORT; + } + + /* Do not try to read 0 bytes. It is not */ + /* possible according to the I2C spec, since the slave will always start */ + /* sending the first byte ACK on an address. The read operation can */ + /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ + if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) + || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) + ) { + return i2cTransferUsageFault; + } + + /* Prepare for a transfer. */ + transfer->state = i2cStateStartAddrSend; + transfer->result = i2cTransferInProgress; + transfer->offset = 0; + transfer->bufIndx = 0; + transfer->seq = seq; + + /* Ensure buffers are empty. */ + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; + flushRx(i2c); + + /* Clear all pending interrupts prior to starting a transfer. */ + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Enable relevant interrupts. */ + /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ + /* that is left for an additional driver wrapper. */ + i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP + | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; + + /* Start a transfer. */ + return I2C_Transfer(i2c); +} + +/** @} (end addtogroup i2c) */ +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_iadc.c b/Libs/platform/emlib/src/em_iadc.c new file mode 100644 index 0000000..8981b26 --- /dev/null +++ b/Libs/platform/emlib/src/em_iadc.c @@ -0,0 +1,1178 @@ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_iadc.h" + +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup iadc IADC - Incremental ADC + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + * @details + * This module contains functions to control the IADC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The IADC is used to convert analog signals into a + * digital representation. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +// Validation of IADC register block pointer reference for assert statements. +#if defined(IADC_NUM) +#define IADC_REF_VALID(ref) (IADC_NUM(ref) != -1) +#else +#if (IADC_COUNT == 1) +#define IADC_REF_VALID(ref) ((ref) == IADC0) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : -1) +#elif (IADC_COUNT == 2) +#define IADC_REF_VALID(ref) (((ref) == IADC0) || ((ref) == IADC1)) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : ((ref) == IADC1) ? 1 : -1) +#endif +#endif + +// Max IADC clock rates +#define IADC_CLK_MAX_FREQ 40000000UL +#define IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ 20000000UL +#define IADC_ANA_CLK_NORMAL_MAX_FREQ 10000000UL +#define IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ 5000000UL +#if defined (_IADC_CFG_ADCMODE_HIGHSPEED) +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : ((adcMode) == iadcCfgModeHighSpeed \ + ? IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ) \ + ) +#else +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ \ + ) +#endif + +#define IADC_ROUND_D2I(n) (int)((n) < 0.0f ? ((n) - 0.5f) : ((n) + 0.5f)) + +#define IADC0_SCANENTRIES IADC0_ENTRIES +#define IADC0_FIFOENTRIES 0x4UL + +#define IADC1_SCANENTRIES IADC1_ENTRIES +#define IADC1_FIFOENTRIES 0x4UL + +#if defined(IADC_ENTRIES) +#define IADC_SCANENTRIES(iadc) IADC_ENTRIES(IADC_NUM(iadc)) +#else +#define IADC_SCANENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_SCANENTRIES \ + : 0UL) +#endif + +#if !defined(IADC_CONFIGNUM) +#define IADC_CONFIGNUM(iadc) ( \ + (iadc) == 0 ? IADC0_CONFIGNUM \ + : 0UL) +#endif + +#define IADC_FIFOENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_FIFOENTRIES \ + : 0UL) + +#define IADC_CMU_CLOCK(iadc) ( \ + (iadc) == IADC0 ? cmuClock_IADC0 \ + : cmuClock_IADC0) + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +static void IADC_disable(IADC_TypeDef *iadc) +{ +#if defined(IADC_STATUS_SYNCBUSY) + while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { + // Wait for synchronization to finish before disable + } +#endif + iadc->EN_CLR = IADC_EN_EN; +#if defined(_IADC_EN_DISABLING_MASK) + while (IADC0->EN & _IADC_EN_DISABLING_MASK) { + } +#endif +} + +static void IADC_enable(IADC_TypeDef *iadc) +{ + iadc->EN_SET = IADC_EN_EN; +} + +static IADC_Result_t IADC_ConvertRawDataToResult(uint32_t rawData, + IADC_Alignment_t alignment) +{ + IADC_Result_t result; + + switch (alignment) { + case iadcAlignRight12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignRight16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignRight20: +#endif + // Mask out ID and replace with sign extension + result.data = (rawData & 0x00FFFFFFUL) + | ((rawData & 0x00800000UL) != 0x0UL ? 0xFF000000UL : 0x0UL); + // Mask out data and shift down + result.id = (uint8_t)((rawData & 0xFF000000UL) >> 24); + break; + + case iadcAlignLeft12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignLeft16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignLeft20: +#endif + result.data = rawData & 0xFFFFFF00UL; + result.id = (uint8_t)(rawData & 0x000000FFUL); + break; + default: + break; + } + return result; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize IADC. + * + * @details + * Initializes common parts for both single conversion and scan sequence. + * In addition, single and/or scan control configuration must be done, please + * refer to @ref IADC_initSingle() and @ref IADC_initScan() respectively. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] allConfigs + * Pointer to structure holding all configs. + ******************************************************************************/ +void IADC_init(IADC_TypeDef *iadc, + const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs) +{ + uint32_t tmp; + uint32_t config; + uint16_t wantedPrescale; + uint8_t srcClkPrescale; + uint32_t adcClkPrescale; + uint8_t timebase; + unsigned uiAnaGain; + uint16_t uiGainCAna; + IADC_CfgAdcMode_t adcMode; +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + float anaGain; + int anaGainRound; + float offsetAna; + float offset2; + int offsetLong; + int offsetAna1HiAccInt; + uint8_t osrValue; + float offsetAnaBase; + float gainSysHiAcc; + float refVoltage = 0; + // Over sampling ratio for high accuracy conversions + const float osrHiAcc[6] = { 16.0, 32.0, 64.0, 92.0, 128.0, 256.0 }; +#endif + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Calculate min allowed SRC_CLK prescaler setting + srcClkPrescale = IADC_calcSrcClkPrescale(iadc, IADC_CLK_MAX_FREQ, 0); + + wantedPrescale = init->srcClkPrescale; + // Use wanted SRC_CLK prescaler setting instead if it is high enough + if (wantedPrescale >= srcClkPrescale) { + srcClkPrescale = wantedPrescale; + } + + IADC_disable(iadc); + + timebase = init->timebase; + if (timebase == 0) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + uint32_t srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE to obtain valid frequency + if (srcClkFreq >= IADC_CLK_MAX_FREQ) { + srcClkFreq = srcClkFreq / srcClkPrescale; + } + // Calculate timebase based on CMU_IADCCLKCTRL + timebase = IADC_calcTimebase(iadc, srcClkFreq); + } + + tmp = (((uint32_t)(init->warmup) << _IADC_CTRL_WARMUPMODE_SHIFT) + & _IADC_CTRL_WARMUPMODE_MASK) + | (((uint32_t)(timebase) << _IADC_CTRL_TIMEBASE_SHIFT) + & _IADC_CTRL_TIMEBASE_MASK) + | (((uint32_t)(srcClkPrescale) << _IADC_CTRL_HSCLKRATE_SHIFT) + & _IADC_CTRL_HSCLKRATE_MASK); + + if (init->iadcClkSuspend0) { + tmp |= IADC_CTRL_ADCCLKSUSPEND0; + } + if (init->iadcClkSuspend1) { + tmp |= IADC_CTRL_ADCCLKSUSPEND1; + } + if (init->debugHalt) { + tmp |= IADC_CTRL_DBGHALT; + } + iadc->CTRL = tmp; + + iadc->TIMER = ((uint32_t) (init->timerCycles) << _IADC_TIMER_TIMER_SHIFT) + & _IADC_TIMER_TIMER_MASK; + + iadc->CMPTHR = (((uint32_t) (init->greaterThanEqualThres) << _IADC_CMPTHR_ADGT_SHIFT) + & _IADC_CMPTHR_ADGT_MASK) + | (((uint32_t) (init->lessThanEqualThres) << _IADC_CMPTHR_ADLT_SHIFT) + & _IADC_CMPTHR_ADLT_MASK); + + // Write configurations + for (config = 0; config < IADC_CONFIGNUM(IADC_NUM(iadc)); config++) { + // Find min allowed ADC_CLK prescaler setting for given mode + adcMode = allConfigs->configs[config].adcMode; + wantedPrescale = allConfigs->configs[config].adcClkPrescale; + adcClkPrescale = IADC_calcAdcClkPrescale(iadc, + IADC_ANA_CLK_MAX_FREQ(adcMode), + 0, + adcMode, + srcClkPrescale); + + // Use wanted ADC_CLK prescaler setting instead if it is high enough + adcClkPrescale = SL_MAX(adcClkPrescale, wantedPrescale); + + tmp = iadc->CFG[config].CFG & ~(_IADC_CFG_ADCMODE_MASK | _IADC_CFG_OSRHS_MASK + | _IADC_CFG_ANALOGGAIN_MASK | _IADC_CFG_REFSEL_MASK +#if defined(_IADC_CFG_DIGAVG_MASK) + | _IADC_CFG_DIGAVG_MASK +#endif + | _IADC_CFG_TWOSCOMPL_MASK +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | _IADC_CFG_OSRHA_MASK +#endif + ); + iadc->CFG[config].CFG = tmp + | (((uint32_t)(adcMode) << _IADC_CFG_ADCMODE_SHIFT) & _IADC_CFG_ADCMODE_MASK) + | (((uint32_t)(allConfigs->configs[config].osrHighSpeed) << _IADC_CFG_OSRHS_SHIFT) + & _IADC_CFG_OSRHS_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | (((uint32_t)(allConfigs->configs[config].osrHighAccuracy) << _IADC_CFG_OSRHA_SHIFT) + & _IADC_CFG_OSRHA_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].analogGain) << _IADC_CFG_ANALOGGAIN_SHIFT) + & _IADC_CFG_ANALOGGAIN_MASK) + | (((uint32_t)(allConfigs->configs[config].reference) << _IADC_CFG_REFSEL_SHIFT) + & _IADC_CFG_REFSEL_MASK) +#if defined(_IADC_CFG_DIGAVG_MASK) + | (((uint32_t)(allConfigs->configs[config].digAvg) << _IADC_CFG_DIGAVG_SHIFT) + & _IADC_CFG_DIGAVG_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].twosComplement) << _IADC_CFG_TWOSCOMPL_SHIFT) + & _IADC_CFG_TWOSCOMPL_MASK); + + uiAnaGain = (iadc->CFG[config].CFG & _IADC_CFG_ANALOGGAIN_MASK) >> _IADC_CFG_ANALOGGAIN_SHIFT; + switch (uiAnaGain) { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + case iadcCfgAnalogGain0P25x: // 0.25x +#endif + case iadcCfgAnalogGain0P5x: // 0.5x + case iadcCfgAnalogGain1x: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + case iadcCfgAnalogGain2x: // 2x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA2_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT); + break; + case iadcCfgAnalogGain3x: // 3x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA3_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT); + break; + case iadcCfgAnalogGain4x: // 4x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA4_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT); + break; + default: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + } + + // Gain and offset correction is applied according to adcMode and oversampling rate. + switch (adcMode) { + float offset; + uint32_t scale; + int iOffset, iOsr; + case iadcCfgModeNormal: +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + case iadcCfgModeHighSpeed: +#endif + offset = 0.0f; + if (uiAnaGain == iadcCfgAnalogGain2x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT); + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT); + } + } else if (uiAnaGain == iadcCfgAnalogGain3x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 2; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 2; + } + } else if (uiAnaGain == iadcCfgAnalogGain4x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 3; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 3; + } + } + + // Set correct gain correction bitfields in scale variable. + tmp = (uint32_t)uiGainCAna & 0x9FFFU; + scale = tmp << _IADC_SCALE_GAIN13LSB_SHIFT; + if ((tmp & 0x8000U) != 0U) { + scale |= IADC_SCALE_GAIN3MSB; + } + + // Adjust offset according to selected OSR. + iOsr = 1U << (((iadc->CFG[config].CFG & _IADC_CFG_OSRHS_MASK) >> _IADC_CFG_OSRHS_SHIFT) + 1U); + if (iOsr == 2) { + if (adcMode == iadcCfgModeNormal) { + offset += (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 & _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK); + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 & _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK); + } + } else { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL1 & _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK) - offset; + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL1 & _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK) - offset; + } + offset /= iOsr / 2.0f; + offset += (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK); + } + + // Compensate offset according to selected reference voltage. + if (allConfigs->configs[config].reference == iadcCfgReferenceInt1V2) { + // Internal reference voltage (VBGR) depends on the chip revision. + offset *= 1.25f / (IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f); + } else { + offset *= 1.25f / (allConfigs->configs[config].vRef / 1000.0f); + } + + // Compensate offset for systematic offset. + offset = (offset * 4.0f) + (640.0f * (256.0f / iOsr)); + + // Apply gain error correction. + if (scale != 0x80000000U) { + offset = (uiGainCAna / 32768.0f) * (offset + 524288.0f) - 524288.0f; + } + + iOffset = IADC_ROUND_D2I(-offset); + // We only have 18 bits available for OFFSET in SCALE register. + // OFFSET is a 2nd complement number. + if (iOffset > 131071) { // Positive overflow at 0x0001FFFF ? + scale |= 0x1FFFFU; + } else if (iOffset < -131072) { // Negative overflow at 0xFFFE0000 ? + scale |= 0x20000U; + } else { + scale |= (uint32_t)iOffset & 0x3FFFFU; + } + iadc->CFG[config].SCALE = scale; + break; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + case iadcCfgModeHighAccuracy: + // Get reference voltage in volts + refVoltage = IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f; + + // Get OSR from config register + osrValue = (iadc->CFG[config].CFG & _IADC_CFG_OSRHA_MASK) >> _IADC_CFG_OSRHA_SHIFT; + + // 1. Calculate gain correction + if ((uint32_t)osrHiAcc[osrValue] == 92U) { + // for OSR = 92, gainSysHiAcc = 0.957457 + gainSysHiAcc = 0.957457; + } else { + // for OSR != 92, gainSysHiAcc = OSR/(OSR + 1) + gainSysHiAcc = osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f); + } + anaGain = (float) uiGainCAna / 32768.0f * gainSysHiAcc; + anaGainRound = IADC_ROUND_D2I(32768.0f * anaGain); + IADC0->CFG[config].SCALE &= ~_IADC_SCALE_MASK; + + // Write GAIN3MSB + if ((uint32_t)anaGainRound & 0x8000) { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN100; + } else { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN011; + } + // Write GAIN13LSB + IADC0->CFG[config].SCALE |= ((uint32_t)anaGainRound & 0x1FFF) << _IADC_SCALE_GAIN13LSB_SHIFT; + + // Get offset value for high accuracy mode from DEVINFO + offsetAna1HiAccInt = (uint16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT; + + // 2. OSR adjustment + // Get offset from DEVINFO + offsetAnaBase = (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT; + // 1 << osrValue is the same as pow(2, osrValue) + offsetAna = offsetAnaBase + (offsetAna1HiAccInt) / (1 << osrValue); + + // 3. Reference voltage adjustment + offsetAna = (offsetAna) * (1.25f / refVoltage); + + // 4. Calculate final offset + offset2 = 262144.0f / osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f) + offsetAna * 4.0f + 524288.0f; + offset2 = (uiGainCAna / 32768.0f * (-1.0f)) * offset2 + 524288.0f; + offsetLong = IADC_ROUND_D2I(offset2); + + // 5. Write offset to scale register + IADC0->CFG[config].SCALE |= (uint32_t)(offsetLong & _IADC_SCALE_OFFSET_MASK); + break; +#endif + default: + // Mode not supported. + EFM_ASSERT(false); + break; + } + iadc->CFG[config].SCHED = ((adcClkPrescale << _IADC_SCHED_PRESCALE_SHIFT) + & _IADC_SCHED_PRESCALE_MASK); + } + IADC_enable(iadc); +} + +/***************************************************************************//** + * @brief + * Initialize IADC scan sequence. + * + * @details + * This function will configure scan mode and set up entries in the scan + * table. The scan table mask can be updated by calling IADC_updateScanMask. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] scanTable + * Pointer to IADC scan table structure. + ******************************************************************************/ +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable) +{ + uint32_t i; + uint32_t tmp; + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + + IADC_disable(iadc); + + iadc->SCANFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SCANFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SCANFIFOCFG_DVL_SHIFT) + & _IADC_SCANFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SCANFIFOCFG_DMAWUFIFOSCAN : 0UL); + + // Clear bitfields for scan conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SCANTRIGSEL_MASK + | _IADC_TRIGGER_SCANTRIGACTION_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SCANTRIGSEL_SHIFT) + & _IADC_TRIGGER_SCANTRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SCANTRIGACTION_SHIFT) + & _IADC_TRIGGER_SCANTRIGACTION_MASK); + + // Write scan table + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = (((uint32_t) (scanTable->entries[i].negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (scanTable->entries[i].posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (scanTable->entries[i].configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (scanTable->entries[i].compare ? IADC_SCAN_CMP : 0UL); + } + + IADC_enable(iadc); + + // Set scan mask + tmp = 0; + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + if (scanTable->entries[i].includeInScan) { + tmp |= (1UL << i) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + } + iadc->MASKREQ = tmp; + + if (init->start) { + IADC_command(iadc, iadcCmdStartScan); + } +} + +/***************************************************************************//** + * @brief + * Initialize single IADC conversion. + * + * @details + * This function will initialize the single conversion and configure the + * single input selection. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC single initialization structure. + * + * @param[in] input + * Pointer to IADC single input selection initialization structure. + ******************************************************************************/ +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + IADC_disable(iadc); + + iadc->SINGLEFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SINGLEFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SINGLEFIFOCFG_DVL_SHIFT) + & _IADC_SINGLEFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE : 0UL); + + // Clear bitfields for single conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SINGLETRIGSEL_MASK + | _IADC_TRIGGER_SINGLETRIGACTION_MASK + | _IADC_TRIGGER_SINGLETAILGATE_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SINGLETRIGSEL_SHIFT) + & _IADC_TRIGGER_SINGLETRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SINGLETRIGACTION_SHIFT) + & _IADC_TRIGGER_SINGLETRIGACTION_MASK) + | (init->singleTailgate ? IADC_TRIGGER_SINGLETAILGATE : 0UL); + + IADC_updateSingleInput(iadc, input); + + IADC_enable(iadc); + + if (init->start) { + IADC_command(iadc, iadcCmdStartSingle); + } +} + +/***************************************************************************//** + * @brief + * Update IADC single input selection. + * + * @details + * This function updates the single input selection. The function can be + * called while single and/or scan conversions are ongoing and the new input + * configuration will take place on the next single conversion. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] input + * Pointer to single input selection structure. + ******************************************************************************/ +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADCn->SINGLE has WSYNC type and can only be written while enabled + IADC_enable(iadc); + + iadc->SINGLE = (((uint32_t) (input->negInput) << _IADC_SINGLE_PINNEG_SHIFT) + & (_IADC_SINGLE_PORTNEG_MASK | _IADC_SINGLE_PINNEG_MASK)) + | (((uint32_t) (input->posInput) << _IADC_SINGLE_PINPOS_SHIFT) + & (_IADC_SINGLE_PORTPOS_MASK | _IADC_SINGLE_PINPOS_MASK)) + | (((uint32_t) (input->configId) << _IADC_SINGLE_CFG_SHIFT) + & _IADC_SINGLE_CFG_MASK) + | (input->compare ? IADC_SINGLE_CMP : 0UL); + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Set mask of IADC scan table entries to include in scan. + * + * @details + * Set mask of scan table entries to include in next scan. This function + * can be called while scan conversions are ongoing, but the new scan mask + * will take effect once the ongoing scan is completed. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] mask + * Mask of scan table entries to include in scan. + ******************************************************************************/ +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + EFM_ASSERT(mask <= ((1UL << IADC_SCANENTRIES(iadc)) - 1UL)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + iadc->MASKREQ = (mask << _IADC_MASKREQ_MASKREQ_SHIFT) + & _IADC_MASKREQ_MASKREQ_MASK; + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Add/update entry in scan table. + * + * @details + * This function will update or add an entry in the scan table with a specific + * ID. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] id + * ID of scan table entry to add. + * + * @param[in] entry + * Pointer to scan table entry structure. + ******************************************************************************/ +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be disabled to update scan table + IADC_disable(iadc); + + // Update entry in scan table + iadc->SCANTABLE[id].SCAN = (((uint32_t) (entry->negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (entry->posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (entry->configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (entry->compare ? IADC_SCAN_CMP : 0UL); + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + if (entry->includeInScan) { + iadc->MASKREQ_SET = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } else { + iadc->MASKREQ_CLR = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Reset IADC to same state as after a HW reset. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + ******************************************************************************/ +void IADC_reset(IADC_TypeDef *iadc) +{ + uint32_t i; + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Write all WSYNC registers to reset value while enabled + IADC_enable(iadc); + + // Stop conversions and timer, before resetting other registers. + iadc->CMD = IADC_CMD_SINGLESTOP | IADC_CMD_SCANSTOP | IADC_CMD_TIMERDIS; + + // Wait for all IADC operations to stop + while ((iadc->STATUS & (IADC_STATUS_CONVERTING + | IADC_STATUS_SCANQUEUEPENDING + | IADC_STATUS_SINGLEQUEUEPENDING + | IADC_STATUS_TIMERACTIVE)) + != 0UL) { + } + + // Reset all WSYNC registers + iadc->MASKREQ = _IADC_MASKREQ_RESETVALUE; + iadc->SINGLE = _IADC_SINGLE_RESETVALUE; + + // Wait for SINGLE and MASQREQ writes to propagate to working registers + while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING + | IADC_STATUS_SINGLEWRITEPENDING)) + != 0UL) { + } + + // Pull from FIFOs until they are empty + + // Errata IADC_E305: Check SINGLEFIFOSTAT to make sure that SINGLEFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { + (void) IADC_pullSingleFifoData(iadc); + } + + // Errata IADC_E305: check SCANFIFOSTAT to make sure that SCANFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { + (void) IADC_pullScanFifoData(iadc); + } + + // Read data registers to clear data valid flags + (void) IADC_readSingleData(iadc); + (void) IADC_readScanData(iadc); + + // Write all WSTATIC registers to reset value while disabled + IADC_disable(iadc); + + // Reset all WSTATIC registers + iadc->CTRL = _IADC_CTRL_RESETVALUE; + iadc->TIMER = _IADC_TIMER_RESETVALUE; + iadc->TRIGGER = _IADC_TRIGGER_RESETVALUE; + + iadc->CMPTHR = _IADC_CMPTHR_RESETVALUE; + iadc->SINGLEFIFOCFG = _IADC_SINGLEFIFOCFG_RESETVALUE; + iadc->SCANFIFOCFG = _IADC_SCANFIFOCFG_RESETVALUE; + + for (i = 0; i < IADC_CONFIGNUM(IADC_NUM(iadc)); i++) { + iadc->CFG[i].CFG = _IADC_CFG_RESETVALUE; + iadc->CFG[i].SCALE = _IADC_SCALE_RESETVALUE; + iadc->CFG[i].SCHED = _IADC_SCHED_RESETVALUE; + } + + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = _IADC_SCAN_RESETVALUE; + } + + // Clear interrupt flags and disable interrupts + IADC_clearInt(iadc, _IADC_IF_MASK); + IADC_disableInt(iadc, _IADC_IEN_MASK); +} + +/***************************************************************************//** + * @brief + * Calculate timebase value in order to get a timebase providing at least 1us. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq Frequency in Hz of reference CLK_SRC_ADC clock. Set to 0 to + * derive srcClkFreq from CLK_CMU_ADC and prescaler HSCLKRATE. + * + * @return + * Timebase value to use for IADC in order to achieve at least 1 us. + ******************************************************************************/ +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); + + if (srcClkFreq == 0UL) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + + // Just in case, make sure we get non-zero frequency for below calculation + if (srcClkFreq == 0UL) { + srcClkFreq = 1; + } + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE + if (srcClkFreq > IADC_CLK_MAX_FREQ) { + uint32_t prescaler = (uint32_t)(IADC0->CTRL & _IADC_CTRL_HSCLKRATE_MASK) >> _IADC_CTRL_HSCLKRATE_SHIFT; + srcClkFreq /= (prescaler + 1); + } + } + + // Determine number of ADCCLK cycle >= 1us + srcClkFreq += 999999UL; + srcClkFreq /= 1000000UL; + + // Convert to N+1 format + srcClkFreq -= 1UL; + + // Limit to max allowed register setting + srcClkFreq = SL_MIN(srcClkFreq, (_IADC_CTRL_TIMEBASE_MASK >> _IADC_CTRL_TIMEBASE_SHIFT)); + + // Return timebase value + return (uint8_t) srcClkFreq; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for CLK_SRC_ADC high speed clock + * + * @details + * The IADC high speed clock is given by: CLK_SRC_ADC / (srcClkPrescaler + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq CLK_SRC_ADC frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of reference CLK_CMU_ADC. Set to 0 + * to use currently defined CMU clock setting for the IADC. + * + * @return + * Divider value to use for IADC in order to achieve a high speed clock value + * <= @p srcClkFreq. + ******************************************************************************/ +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq) +{ + uint32_t ret; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(srcClkFreq); + + // Make sure wanted CLK_SRC_ADC clock is below max allowed frequency + srcClkFreq = SL_MIN(srcClkFreq, IADC_CLK_MAX_FREQ); + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + cmuClkFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } + + ret = (cmuClkFreq + srcClkFreq - 1UL) / srcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + if (ret > _IADC_CTRL_HSCLKRATE_DIV4) { + ret = _IADC_CTRL_HSCLKRATE_DIV4; + } + + return (uint8_t)ret; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for ADC_CLK clock. + * + * @details + * The ADC_CLK is given by: CLK_SRC_ADC / (adcClkprescale + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] adcClkFreq ADC_CLK frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of CLK_CMU_ADC Set to 0 to + * use currently defined IADC clock setting (in CMU). + * + * @param[in] adcMode Mode for IADC config. + * + * @param[in] srcClkPrescaler Precaler setting for ADC_CLK + * + * @return + * Divider value to use for IADC in order to achieve a ADC_CLK frequency + * <= @p adcClkFreq. + ******************************************************************************/ +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler) +{ + uint32_t ret; + uint32_t resFreq; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(adcClkFreq); + + // Make sure wanted analog clock is below max allowed frequency for the given + // mode. + if (adcClkFreq > IADC_ANA_CLK_MAX_FREQ(adcMode)) { + adcClkFreq = IADC_ANA_CLK_MAX_FREQ(adcMode); + } + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + resFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } else { + resFreq = cmuClkFreq; + } + + // Apply CLK_SRC_ADC prescaler + resFreq /= srcClkPrescaler + 1UL; + + ret = (resFreq + adcClkFreq - 1UL) / adcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); + + return (uint16_t)ret; +} + +/***************************************************************************//** + * @brief + * Pull result from single data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing single mode. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing single mode. + * Calling this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Pull result from scan data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Get reference voltage selection. + * + * @param[in] reference + * IADC Reference selection. + * + * @return + * IADC reference voltage in millivolts. + ******************************************************************************/ +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference) +{ + uint32_t refVoltage = 0; + // Get chip revision + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + switch (reference) { + case iadcCfgReferenceInt1V2: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (chipRev.major == 1UL) { + refVoltage = 1210; + } else { + refVoltage = 1180; + } +#else + refVoltage = 1210; +#endif + break; + case iadcCfgReferenceExt1V25: + refVoltage = 1250; + break; +#if defined(_IADC_CFG_REFSEL_VREF2P5) + case iadcCfgReferenceExt2V5: + refVoltage = 2500; + break; +#endif + case iadcCfgReferenceVddx: + refVoltage = 3000; + break; + case iadcCfgReferenceVddX0P8Buf: + refVoltage = 2400; + break; +#if defined(_IADC_CFG_REFSEL_VREFBUF) + case iadcCfgReferenceBuf: + refVoltage = 12500; + break; +#endif +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + case iadcCfgReference0P8Buf: + refVoltage = 1000; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + return refVoltage; +} + +/** @} (end addtogroup iadc) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_ldma.c b/Libs/platform/emlib/src/em_ldma.c new file mode 100644 index 0000000..92a2f31 --- /dev/null +++ b/Libs/platform/emlib/src/em_ldma.c @@ -0,0 +1,461 @@ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_ldma.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup ldma + * @{ + ******************************************************************************/ + +#if defined(LDMA_IRQ_HANDLER_TEMPLATE) +/***************************************************************************//** + * @brief + * A template for an LDMA IRQ handler. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + uint32_t ch; + /* Get all pending and enabled interrupts. */ + uint32_t pending = LDMA_IntGetEnabled(); + + /* Loop on an LDMA error to enable debugging. */ + while (pending & LDMA_IF_ERROR) { + } + + /* Iterate over all LDMA channels. */ + for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { + uint32_t mask = 0x1 << ch; + if (pending & mask) { + /* Clear the interrupt flag. */ + LDMA->IFC = mask; + + /* Perform more actions here, execute callbacks, and so on. */ + } + } +} +#endif + +/***************************************************************************//** + * @brief + * De-initialize the LDMA controller. + * + * LDMA interrupts are disabled and the LDMA clock is stopped. + ******************************************************************************/ +void LDMA_DeInit(void) +{ + NVIC_DisableIRQ(LDMA_IRQn); + LDMA->IEN = 0; +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif +#if defined(LDMA_EN_EN) + LDMA->EN = 0; +#if defined(LDMA_EN_DISABLING) + while (LDMA->EN & _LDMA_EN_DISABLING_MASK) { + } +#endif +#endif + + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable an LDMA channel request. + * + * @details + * Use this function to enable or disable an LDMA channel request. This will + * prevent the LDMA from proceeding after its current transaction if disabled. + * + * @param[in] ch + * LDMA channel to enable or disable requests. + * + * @param[in] enable + * If 'true', the request will be enabled. If 'false', the request will be disabled. + ******************************************************************************/ +void LDMA_EnableChannelRequest(int ch, bool enable) +{ + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); +} + +/***************************************************************************//** + * @brief + * Initialize the LDMA controller. + * + * @details + * This function will disable all the LDMA channels and enable the LDMA bus + * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC + * and set the LDMA IRQ priority to a user-configurable priority. The LDMA + * interrupt priority is configured using the @ref LDMA_Init_t structure. + * + * @note + * Since this function enables the LDMA IRQ, always add a custom + * LDMA_IRQHandler to the application to handle any interrupts + * from LDMA. + * + * @param[in] init + * A pointer to the initialization structure used to configure the LDMA. + ******************************************************************************/ +void LDMA_Init(const LDMA_Init_t *init) +{ + uint32_t ldmaCtrlVal; + EFM_ASSERT(init != NULL); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) + & ~_LDMA_CTRL_NUMFIXED_MASK)); + + EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); + + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif + +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + + ldmaCtrlVal = (uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; + +#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); +#endif + + LDMA->CTRL = ldmaCtrlVal; + +#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + LDMA->SYNCHWEN = ((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); +#endif + +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Enable the LDMA error interrupt. */ + LDMA->IEN = LDMA_IEN_ERROR; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = 0xFFFFFFFFU; +#else + LDMA->IFC = 0xFFFFFFFFU; +#endif + NVIC_ClearPendingIRQ(LDMA_IRQn); + + /* Range is 0-7, where 0 is the highest priority. */ + NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); + + NVIC_EnableIRQ(LDMA_IRQn); +} + +/***************************************************************************//** + * @brief + * Start a DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor + * The transfer descriptor, which can be an array of descriptors linked together. + * Each descriptor's fields stored in RAM will be loaded into the certain + * hardware registers at the proper time to perform the DMA transfer. + ******************************************************************************/ +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor) +{ +#if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + uint32_t tmp; +#endif + CORE_DECLARE_IRQ_STATE; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + EFM_ASSERT(transfer != NULL); + +#if defined (_LDMAXBAR_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); +#elif defined (_LDMA_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); +#endif + + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); + + /* Clear the pending channel interrupt. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + +#if defined(LDMAXBAR) + LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; +#else + LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; +#endif + LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; + LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + | (transfer->ldmaCfgStructBusPort << _LDMA_CH_CFG_STRUCTBUSPORT_SHIFT) + | (transfer->ldmaCfgSrcBusPort << _LDMA_CH_CFG_SRCBUSPORT_SHIFT) + | (transfer->ldmaCfgDstBusPort << _LDMA_CH_CFG_DSTBUSPORT_SHIFT) +#endif + ; + + /* Set the descriptor address. */ + LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; + + /* A critical region. */ + CORE_ENTER_ATOMIC(); + + /* Enable the channel interrupt. */ + BUS_RegMaskedSet(&LDMA->IEN, chMask); + + if (transfer->ldmaReqDis) { + LDMA->REQDIS |= chMask; + } + + if (transfer->ldmaDbgHalt) { + LDMA->DBGHALT |= chMask; + } + +#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + + LDMA->SYNCHWEN_CLR = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + + LDMA->SYNCHWEN_SET = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + +#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + + tmp = LDMA->CTRL; + + if (transfer->ldmaCtrlSyncPrsClrOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK + | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsClrOn) { + tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; + } + + if (transfer->ldmaCtrlSyncPrsSetOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK + | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsSetOn) { + tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; + } + + LDMA->CTRL = tmp; + +#else + + #error "SYNC Set and SYNC Clear not defined" + +#endif + + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ + LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ + + /* A critical region end. */ + CORE_EXIT_ATOMIC(); +} + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/***************************************************************************//** + * @brief + * Start an extended DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor_ext + * The extended transfer descriptor, which can be an array of descriptors + * linked together. Each descriptor's fields stored in RAM will be loaded + * into the certain hardware registers at the proper time to perform the DMA + * transfer. + ******************************************************************************/ +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext) +{ + // Ensure destination interleaving supported for given channel. + EFM_ASSERT(((1 << ch) & LDMA_ILCHNL)); + + LDMA_StartTransfer(ch, + transfer, + (const LDMA_Descriptor_t *)descriptor_ext); +} +#endif + +/***************************************************************************//** + * @brief + * Stop a DMA transfer. + * + * @note + * The DMA will complete the current AHB burst transfer before stopping. + * + * @param[in] ch + * A DMA channel to stop. + ******************************************************************************/ +void LDMA_StopTransfer(int ch) +{ + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHDIS_MASK) + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + LDMA->CHDIS = chMask; + ) +#else + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + BUS_RegMaskedClear(&LDMA->CHEN, chMask); + ) +#endif +} + +/***************************************************************************//** + * @brief + * Check if a DMA transfer has completed. + * + * @param[in] ch + * A DMA channel to check. + * + * @return + * True if transfer has completed, false if not. + ******************************************************************************/ +bool LDMA_TransferDone(int ch) +{ + bool retVal = false; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHSTATUS_MASK) + CORE_ATOMIC_SECTION( + if (((LDMA->CHSTATUS & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#else + CORE_ATOMIC_SECTION( + if (((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#endif + + return retVal; +} + +/***************************************************************************//** + * @brief + * Get the number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * + * @param[in] ch + * The channel number of the transfer to check. + * + * @return + * A number of items remaining in the transfer. + ******************************************************************************/ +uint32_t LDMA_TransferRemainingCount(int ch) +{ + uint32_t remaining, done; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + CORE_ATOMIC_SECTION( + done = LDMA->CHDONE; + remaining = LDMA->CH[ch].CTRL; + ) + + done &= chMask; + + if (done) { + return 0; + } + + remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) + >> _LDMA_CH_CTRL_XFERCNT_SHIFT; + + /* +1 because XFERCNT is 0-based. */ + return remaining + 1; +} + +/** @} (end addtogroup ldma) */ +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ diff --git a/Libs/platform/emlib/src/em_letimer.c b/Libs/platform/emlib/src/em_letimer.c new file mode 100644 index 0000000..230b80a --- /dev/null +++ b/Libs/platform/emlib/src/em_letimer.c @@ -0,0 +1,685 @@ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_letimer.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) +#include "em_cmu.h" +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup letimer LETIMER - Low Energy Timer + * @brief Low Energy Timer (LETIMER) Peripheral API + * @details + * This module contains functions to control the LETIMER peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track + * of time and output configurable waveforms. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** A validation of the valid comparator register for assert statements. */ +#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) + +/** A validation of the LETIMER register block pointer reference for assert statements. */ +#if (LETIMER_COUNT == 1) +#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) +#elif (LETIMER_COUNT == 2) +#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) +#else +#error Undefined number of analog comparators (ACMP). +#endif + +/** A validation of the valid repeat counter register for assert statements. */ +#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. + * + * @note + * See the reference manual chapter about Access to Low Energy Peripherals + * (Asynchronos Registers) for details. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) +{ +#if defined(_LETIMER_FREEZE_MASK) + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { + return; + } +#endif + + /* Wait for any pending write operation to complete. */ + while (letimer->SYNCBUSY & mask) { + } +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the LETIMER compare register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to get, either 0 or 1. + * + * @return + * A compare register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + ret = letimer->COMP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + ret = letimer->COMP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Get LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @return + * Current LETIMER counter value. + ******************************************************************************/ +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + return letimer->CNT; +} + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Set LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] value + * New counter value. + ******************************************************************************/ +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + letimer->CNT = value; +} +#endif + +/***************************************************************************//** + * @brief + * Set the LETIMER compare register value. + * + * @note + * The setting of a compare register requires synchronization into the + * low frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_COMP_REG_VALID(comp) + && ((value & ~(_LETIMER_COMP0_COMP0_MASK + >> _LETIMER_COMP0_COMP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + letimer->COMP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + letimer->COMP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Start/stop LETIMER. + * + * @note + * The enabling/disabling of the LETIMER modifies the LETIMER CMD register + * which requires synchronization into the low-frequency domain. If this + * register is modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START); +#endif + + if (enable) { + letimer->CMD = LETIMER_CMD_START; + } else { + letimer->CMD = LETIMER_CMD_STOP; + } +} + +#if defined(_LETIMER_FREEZE_MASK) +/***************************************************************************//** + * @brief + * LETIMER register synchronization freeze control. + * + * @details + * Some LETIMER registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing LETIMER synchronization to the LF domain to complete (Normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring the LF synchronization + * should be done within one freeze enable/disable block to avoid unecessary + * stalling. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * @li True - enable freeze, modified registers are not propagated to the + * LF domain + * @li False - disables freeze, modified registers are propagated to the LF + * domain + ******************************************************************************/ +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) +{ + if (enable) { + /* + * Wait for any ongoing LF synchronization to complete to + * protect against the rare case when a user + * - modifies a register requiring LF sync + * - then enables freeze before LF sync completed + * - then modifies the same register again + * since modifying a register while it is in sync progress should be + * avoided. + */ + while (letimer->SYNCBUSY) { + } + + letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; + } else { + letimer->FREEZE = 0; + } +} +#endif /* defined(_LETIMER_FREEZE_MASK) */ + +/***************************************************************************//** + * @brief + * Initialize LETIMER. + * + * @details + * Note that the compare/repeat values must be set separately with + * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done + * prior using this function if configuring the LETIMER to start when + * initialization is complete. + * + * @note + * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers + * which require synchronization into the low-frequency domain. If any of those + * registers are modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] init + * A pointer to the LETIMER initialization structure. + ******************************************************************************/ +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) +{ + uint32_t tmp = 0; + + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined (LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled and running. */ + if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP); +#endif + letimer->CMD = LETIMER_CMD_STOP; + } + + /* Configure the DEBUGRUN flag, which sets whether or not the counter should be + * updated when the debugger is active. */ + if (init->debugRun) { + tmp |= LETIMER_CTRL_DEBUGRUN; + } + +#if defined(LETIMER_CTRL_RTCC0TEN) + if (init->rtcComp0Enable) { + tmp |= LETIMER_CTRL_RTCC0TEN; + } + + if (init->rtcComp1Enable) { + tmp |= LETIMER_CTRL_RTCC1TEN; + } +#endif + + if ((init->comp0Top) || (init->topValue != 0U)) { +#if defined (LETIMER_CTRL_COMP0TOP) + tmp |= LETIMER_CTRL_COMP0TOP; + if (init->topValue != 0U) { + letimer->COMP0 = init->topValue; + } +#elif defined (LETIMER_CTRL_CNTTOPEN) + tmp |= LETIMER_CTRL_CNTTOPEN; + if (init->topValue != 0U) { + letimer->TOP = init->topValue; + } +#endif + } + + if (init->bufTop) { + tmp |= LETIMER_CTRL_BUFTOP; + } + + if (init->out0Pol) { + tmp |= LETIMER_CTRL_OPOL0; + } + + if (init->out1Pol) { + tmp |= LETIMER_CTRL_OPOL1; + } + + tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; + tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; + tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; + +#if defined(LETIMER_SYNCBUSY_CTRL) + /* LF register about to be modified requires sync; busy check. */ + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#endif + letimer->CTRL = tmp; + + /* Start the timer if specified to be enabled and not already running. */ + if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_START) + regSync(letimer, LETIMER_SYNCBUSY_START); +#endif + letimer->CMD = LETIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Get the LETIMER repeat register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat register to get, either 0 or 1. + * + * @return + * Repeat register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + /* Wait for sync to complete to read the potentially pending value. */ + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + ret = letimer->REP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + ret = letimer->REP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the LETIMER repeat counter register value. + * + * @note + * The setting of a repeat counter register requires synchronization into the + * low-frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat counter register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_REP_REG_VALID(rep) + && ((value & ~(_LETIMER_REP0_REP0_MASK + >> _LETIMER_REP0_REP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + letimer->REP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + letimer->REP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Reset LETIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_Reset(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + LETIMER_SyncWait(letimer); + +#if defined(LETIMER_SWRST_SWRST) + letimer->SWRST_SET = LETIMER_SWRST_SWRST; + while (letimer->SWRST & _LETIMER_SWRST_RESETTING_MASK) { + } +#else + +#if defined(_LETIMER_FREEZE_MASK) + /* Freeze registers to avoid stalling for LF synchronization. */ + LETIMER_FreezeEnable(letimer, true); +#endif + + /* Make sure disabled first, before resetting other registers. */ + letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR + | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; + letimer->CTRL = _LETIMER_CTRL_RESETVALUE; + letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; + letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; + letimer->REP0 = _LETIMER_REP0_RESETVALUE; + letimer->REP1 = _LETIMER_REP1_RESETVALUE; + letimer->IEN = _LETIMER_IEN_RESETVALUE; + LETIMER_IntClear(letimer, _LETIMER_IF_MASK); + +#if defined(_LETIMER_FREEZE_MASK) + /* Unfreeze registers and pass new settings to LETIMER. */ + LETIMER_FreezeEnable(letimer, false); +#endif + + LETIMER_SyncWait(letimer); + +#if defined (LETIMER_EN_EN) + letimer->EN_CLR = LETIMER_EN_EN; +#if defined(_LETIMER_EN_DISABLING_MASK) + /* + * Currently, there are no chips without SWRST and with LETIMER_EN_DISABLING + * so this code should never be reached, but that way the same pattern of + * checking the disabling bit is spread across emlib, and code is slightly + * more resilient to feature addition/removal. + */ + while (letimer->EN & _LETIMER_EN_DISABLING_MASK) { + } +#endif +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the LETIMER to complete all synchronization of register changes + * and commands. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_SyncWait(LETIMER_TypeDef *letimer) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (letimer->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +/***************************************************************************//** + * @brief + * Set the LETIMER top value. + * + * @note + * The LETIMER is a down-counter, so when the counter reaches 0 then the top + * value will be loaded into the counter. This function can be used to set + * the top value. + * + * If the LETIMER is not already configured to use a top value then this + * function will enable that functionality for the user. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] value + * The top value. This can be a 16 bit value on series-0 and series-1 devices + * and a 24 bit value on series-2 devices. + ******************************************************************************/ +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CTRL) + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#elif defined(LETIMER_SYNCBUSY_TOP) + regSync(letimer, LETIMER_SYNCBUSY_TOP); +#endif + +#if defined(_LETIMER_TOP_MASK) + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { + letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; + } + letimer->TOP = value; +#else + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { + letimer->CTRL |= LETIMER_CTRL_COMP0TOP; + } + LETIMER_CompareSet(letimer, 0, value); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current LETIMER top value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @return + * The top value. This will be a 16 bit value on series-0 and series-1 + * devices and a 24 bit value on series-2 devices. + ******************************************************************************/ +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) +{ +#if defined(_LETIMER_TOP_MASK) + regSync(letimer, LETIMER_SYNCBUSY_TOP); + return letimer->TOP; +#else +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + return letimer->COMP0; +#endif +} + +/** @} (end addtogroup letimer) */ +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_msc.c b/Libs/platform/emlib/src/em_msc.c new file mode 100644 index 0000000..ede8ad9 --- /dev/null +++ b/Libs/platform/emlib/src/em_msc.c @@ -0,0 +1,2081 @@ +/***************************************************************************//** + * @file + * @brief Flash controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_msc.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(__ICCARM__) +/* Suppress warnings originating from use of EFM_ASSERT() with IAR Embedded Workbench */ +#pragma diag_suppress=Ta022,Ta023 +#endif + +#if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) +#error "Running Flash write/erase operations from Flash is not supported on EFM32G." +#endif + +/******************************************************************************* + ****************************** DEFINES ****************************** + ******************************************************************************/ +#if defined(MSC_WRITECTRL_WDOUBLE) +#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) +#else +#define WORDS_PER_DATA_PHASE (1) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata FLASH_E201 - Potential program failure after Power On */ +#define ERRATA_FIX_FLASH_E201_EN +#endif + +#define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 + banks (not RAM2). It is necessary to figure out which is biggest to + calculate the number of DMA descriptors needed. */ +#define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and + RAM2 banks. All banks are of equal size. */ +#define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) +#define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) +#define ECC_RAM2_SYNDROMES_INIT (MSC_ECCCTRL_RAM2ECCEWEN) +#define ECC_RAM2_CORRECTION_EN (MSC_ECCCTRL_RAM2ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ + | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN) + +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK))) + +/* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) + +#define ECC_IF_REG (SYSCFG->IF) +#define ECC_IF_1BIT_ERROR (SYSCFG_IF_RAMERR1B) + +#elif defined(_MPAHBRAM_CTRL_MASK) + +/* From Series 2 Config 3, aka EFR32XG23, ECC is now standalone in the + * MPAHBRAM module */ +#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) +#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) +#endif + +#define ECC_IF_REG (DMEM->IF) +/* number of AHB ports is between 1 and 4 */ +#if defined(MPAHBRAM_IF_AHB3ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B | MPAHBRAM_IF_AHB3ERR1B) +#elif defined(MPAHBRAM_IF_AHB2ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B) +#elif defined(MPAHBRAM_IF_AHB1ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B) +#else +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B) +#endif + +#else + +#error "Unknown device" + +#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */ + +#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + +#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE) +#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE) + +#define ECC_CTRL0_REG (DMEM0->CTRL) +#define ECC_CTRL1_REG (DMEM1->CTRL) + +#define ECC_IFC0_REG (DMEM0->IF_CLR) +#define ECC_IFC1_REG (DMEM1->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) + +#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL) +#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) + +#else + +#define ECC_RAM0_MEM_BASE (SRAM_BASE) +#define ECC_RAM0_MEM_SIZE (SRAM_SIZE) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK))) +#define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) +#define ECC_IFC_REG (SYSCFG->IF_CLR) +#define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) +#define ECC_FAULT_CTRL_REG (SYSCFG->CTRL) +#define ECC_FAULT_EN (SYSCFG_CTRL_RAMECCERRFAULTEN) + +#elif defined(_MPAHBRAM_CTRL_MASK) +#define ECC_CTRL_REG (DMEM->CTRL) +#define ECC_IFC_REG (DMEM->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) +#define ECC_FAULT_CTRL_REG (DMEM->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) +#endif + +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#else + +#error Unknown device. + +#endif + +#define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ + >> _LDMA_CH_CTRL_XFERCNT_SHIFT) +#define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ + +#define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/***************************************************************************//** + * @brief + * Get locked status of the MSC registers. + * + * @detail + * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions + * that can be placed either in flash or in RAM. + ******************************************************************************/ +#if defined(_MSC_STATUS_REGLOCK_MASK) +#define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) +#else +#define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) +#endif + +/******************************************************************************* + ****************************** TYPEDEFS ****************************** + ******************************************************************************/ + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +typedef struct { + uint32_t initSyndromeEnable; + uint32_t correctionEnable; + uint32_t base; + uint32_t size; +} MSC_EccBank_Typedef; + +#endif + +/******************************************************************************* + ****************************** LOCALS ******************************* + ******************************************************************************/ +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +static const MSC_EccBank_Typedef eccBankTbl[MSC_ECC_BANKS] = +{ + { + ECC_RAM0_SYNDROMES_INIT, ECC_RAM0_CORRECTION_EN, + ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE + }, +#if MSC_ECC_BANKS > 1 + { + ECC_RAM1_SYNDROMES_INIT, ECC_RAM1_CORRECTION_EN, + ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE + }, +#if MSC_ECC_BANKS > 2 + { + ECC_RAM2_SYNDROMES_INIT, ECC_RAM2_CORRECTION_EN, + ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE + }, +#endif +#endif +}; +#endif + +/******************************************************************************* + ****************************** FUNCTIONS ****************************** + ******************************************************************************/ +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadWriteData(uint32_t* data, + uint32_t numWords); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadVerifyAddress(uint32_t* address); + +/** @endcond */ + +/***************************************************************************//** + * @addtogroup msc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for a specified MSC status or timeout. + * + * @param[in] mask + * MSC->STATUS register mask to apply when testing for specified status. + * @param[in] value + * The value the MSC->STATUS test is waiting to see. + * @return + * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Specified status criteria fulfilled. + * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * write or erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + + while (timeOut) { + uint32_t status = MSC->STATUS; + + /* if INVADDR is asserted by MSC, BUSY will never go high, can be checked early */ + if (status & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + /* + * if requested operation fails because flash is locked, BUSY will be high + * for a few cycles and it's not safe to clear WRITECTRL.WREN during that + * period. mscStatusWait should return only when it's safe to do so. + * + * So if user is checking BUSY flag, make sure it matches user's expected + * value and only then check the lock bits. Otherwise, do check early and + * bail out if necessary. + */ + + if ((!(mask & MSC_STATUS_BUSY)) + && (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK))) { + return mscReturnLocked; + } + + if ((status & mask) == value) { + if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { + return mscReturnLocked; + } else { + return mscReturnOk; + } + } + + timeOut--; + } + + return mscReturnTimeOut; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. It is assumed that start address is word + * aligned and that numBytes is an integer multiple of four, and that the + * write operation does not cross a flash page boundary. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef writeBurst(uint32_t address, + const uint32_t *data, + uint32_t numBytes) +{ + msc_Return_TypeDef retVal; + + MSC->ADDRB = address; + + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + MSC->WDATA = *data++; + numBytes -= 4; + + while (numBytes) { + retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY); + + if (retVal != mscReturnOk) { + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + return retVal; + } + + MSC->WDATA = *data++; + numBytes -= 4; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Initialize MSC module. Puts MSC hw in a known state. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; +} + +/***************************************************************************//** + * @brief + * Turn off MSC flash write enable and lock MSC registers. + ******************************************************************************/ +void MSC_Deinit(void) +{ + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + // Lock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_CLR = CMU_CLKEN1_MSC; +#endif +} + +/***************************************************************************//** + * @brief + * Set MSC code execution configuration + * + * @param[in] execConfig + * Code execution configuration + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_RDATACTRL_DOUTBUFEN) + mscReadCtrl = MSC->RDATACTRL & ~MSC_RDATACTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_RDATACTRL_DOUTBUFEN; + } + + MSC->RDATACTRL = mscReadCtrl; +#elif defined(MSC_READCTRL_DOUTBUFEN) + mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; + } + MSC->READCTRL = mscReadCtrl; +#endif +} + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * @param[in] startAddress + * Pointer to the flash page to erase. Must be aligned to beginning of page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Operation completed successfully. + * mscReturnInvalidAddr - Operation tried to erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + MSC_Status_TypeDef retVal; + bool wasLocked; + + // Address must be aligned to page boundary + EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. Write data must be aligned to words and + * contain a number of bytes that is divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * The Flash memory is organized into 64-bit wide double-words. + * Each 64-bit double-word can be written only twice using burst write + * operation between erasing cycles. The user's application must store data in + * RAM to sustain burst write operation. + * + * EFR32XG21 RevC is not able to program every word twice before the next erase. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t addr; + const uint8_t *pData; + uint32_t burstLen; + MSC_Status_TypeDef retVal = mscReturnOk; + bool wasLocked; + + // Check alignment (must be aligned to words) + EFM_ASSERT(((uint32_t)address & 0x3U) == 0); + // Check number of bytes, must be divisable by four + EFM_ASSERT((numBytes & 0x3U) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + // Enable flash write + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + + addr = (uint32_t)address; + pData = (uint8_t*)data; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); + + if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) + != mscReturnOk) { + break; + } + + addr += burstLen; + pData += burstLen; + numBytes -= burstLen; + } + + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + MSC_Status_TypeDef retVal; + + if (MSC_IS_LOCKED()) { + return mscReturnLocked; + } + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // Set write enable bit + MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; // Enable Write ctrl access + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; // Start Mass erase procedure + retVal = mscStatusWait(MSC_STATUS_BUSY, 0); // Wait for end of busy flag or a problem (INVADDR, LOCK, REGLOCK, TIMEOUT) + MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; // Reenable mass erase lock bit + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Disable Write ctrl access + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that copying data from flash to flash will be slower than + * copying from RAM to flash. So the source data must be in RAM in order to + * see the write speeds similar to the datasheet numbers. + * + * @note + * This function requires that the LDMA and LDMAXBAR clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash and be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + LDMA->EN_SET = 0x1; + LDMAXBAR->CH[ch].REQSEL = LDMAXBAR_CH_REQSEL_SOURCESEL_MSC + | LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN_SET = (0x1 << ch); + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + + LDMA->CHDONE_CLR = (0x1 << ch); + LDMA->CHDIS_SET = (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief + * Enables the flash controller for writing. + * @note + * This function must be called before flash operations when + * AUXHFRCO clock has been changed from a default band. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_MSC_TIMEBASE_MASK) + uint32_t freq, cycles; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done. Flash erase and write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Unlock the MSC module. */ + MSC->LOCK = MSC_UNLOCK_CODE; + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_TIMEBASE_MASK) + /* Configure MSC->TIMEBASE according to a selected frequency. */ + freq = CMU_ClockFreqGet(cmuClock_AUX); + + /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band + is tuned to 1.2 MHz on newer revisions. */ + if (freq > 1200000) { + /* Calculate a number of clock cycles for 1 us as a base period. */ + freq = (freq * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing. */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_1US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } else { + /* Calculate a number of clock cycles for 5 us as a base period. */ + freq = (freq * 5 * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_5US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } +#endif +} + +/***************************************************************************//** + * @brief + * Disables the flash controller for writing. + ******************************************************************************/ +void MSC_Deinit(void) +{ + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + /* Lock the MSC module.*/ + MSC->LOCK = 0; +} + +/***************************************************************************//** + * @brief + * Set the MSC code execution configuration. + * + * @param[in] execConfig + * The code execution configuration. + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; + if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1; + } else { + /* No change needed. */ + } +#endif + + mscReadCtrl = MSC->READCTRL & ~(0 +#if defined(MSC_READCTRL_SCBTP) + | MSC_READCTRL_SCBTP +#endif +#if defined(MSC_READCTRL_USEHPROT) + | MSC_READCTRL_USEHPROT +#endif +#if defined(MSC_READCTRL_PREFETCH) + | MSC_READCTRL_PREFETCH +#endif +#if defined(MSC_READCTRL_ICCDIS) + | MSC_READCTRL_ICCDIS +#endif +#if defined(MSC_READCTRL_AIDIS) + | MSC_READCTRL_AIDIS +#endif +#if defined(MSC_READCTRL_IFCDIS) + | MSC_READCTRL_IFCDIS +#endif + ); + mscReadCtrl |= (0 +#if defined(MSC_READCTRL_SCBTP) + | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) +#endif +#if defined(MSC_READCTRL_USEHPROT) + | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) +#endif +#if defined(MSC_READCTRL_PREFETCH) + | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) +#endif +#if defined(MSC_READCTRL_ICCDIS) + | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) +#endif +#if defined(MSC_READCTRL_AIDIS) + | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) +#endif +#if defined(MSC_READCTRL_IFCDIS) + | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) +#endif + ); + + MSC->READCTRL = mscReadCtrl; +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Perform the address phase of the flash write cycle. + * @details + * This function performs the address phase of a flash write operation by + * writing the given flash address to the ADDRB register and issuing the + * LADDRIM command to load the address. + * @param[in] address + * An address in flash memory. Must be aligned at a 4 byte boundary. + * @return + * Returns the status of the address load operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the Flash. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) +{ + uint32_t timeOut; + + /* Wait for the MSC to become ready. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Load the address. */ + MSC->ADDRB = (uint32_t)address; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Perform a flash data write phase. + * @details + * This function performs the data phase of a flash write operation by loading + * the given number of 32-bit words to the WDATA register. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numWords + * A number of data words (32-bit) to load. + * @return + * Returns the status of the data load operation. + * @verbatim + * mscReturnOk - An operation completed successfully. + * mscReturnTimeOut - An operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, + uint32_t numWords) +{ + uint32_t timeOut; + uint32_t wordIndex; + bool useWDouble = false; + MSC_Status_TypeDef retval = mscReturnOk; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ + if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { + /* If the number of words to be written is odd, align by writing + a single word first, before setting the WDOUBLE bit. */ + if (numWords & 0x1) { + /* Wait for the MSC to become ready for the next word. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + + /* Clear the double word option to write the initial single word. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; + /* Write first data word. */ + MSC->WDATA = *data++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + + /* Wait for the operation to finish. It may be required to change the WDOUBLE + configuration after the initial write. It should not be changed while BUSY. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + return mscReturnLocked; + } + /* Subtract this initial odd word for the write loop below. */ + numWords -= 1; + retval = mscReturnOk; + } + /* Set the double word option to write two words per + data phase. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; + useWDouble = true; + } +#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ + + /* Write the rest as a double word write if wordsPerDataPhase == 2 */ + if (numWords > 0) { + /* Requires a system core clock at 1MHz or higher */ + EFM_ASSERT(SystemCoreClock >= 1000000); + wordIndex = 0; + while (wordIndex < numWords) { + if (!useWDouble) { + MSC->WDATA = *data++; + wordIndex++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + } else { + /* Trigger a double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + MSC->WDATA = *data++; + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; + MSC->WDATA = *data++; + wordIndex += 2; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; +#endif + } + + /* Wait for the transaction to finish. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for a timeout. */ + if (timeOut == 0) { + retval = mscReturnTimeOut; + break; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + retval = mscReturnLocked; + break; + } +#if defined(_EFM32_GECKO_FAMILY) + MSC->ADDRB += 4; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; +#endif + } + } + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* Clear a double word option, which should not be left on when returning. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif + + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * An internal flash write function. + * @param[in] address + * A write address. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numBytes + * A nsumber of data bytes to load, which must be a multiple of 4 bytes. + * @return + * Returns the status of the data load operation. + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t wordCount; + uint32_t numWords; + uint32_t pageWords; + uint32_t* pData; + bool wasLocked; + MSC_Status_TypeDef retval = mscReturnOk; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Check alignment (must be aligned to words). */ + EFM_ASSERT(((uint32_t) address & 0x3) == 0); + + /* Check a number of bytes. Must be divisible by four. */ + EFM_ASSERT((numBytes & 0x3) == 0); + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Convert bytes to words. */ + numWords = numBytes >> 2; + EFM_ASSERT(numWords > 0); + + /* The following loop splits the data into chunks corresponding to flash pages. + The address is loaded only once per page because the hardware automatically + increments the address internally for each data load inside a page. */ + for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { + /* First, the address is loaded. The address is auto-incremented within a page. + Therefore, the address phase is only needed once for each page. */ + retval = MSC_LoadVerifyAddress(address + wordCount); + if (mscReturnOk != retval) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; + } + /* Compute the number of words to write to the current page. */ + pageWords = + (FLASH_PAGE_SIZE + - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) + / sizeof(uint32_t); + if (pageWords > numWords - wordCount) { + pageWords = numWords - wordCount; + } + /* Write the data in the current page. */ + retval = MSC_LoadWriteData(pData, pageWords); + if (mscReturnOk != retval) { + break; + } + wordCount += pageWords; + pData += pageWords; + } + +#if defined(ERRATA_FIX_FLASH_E201_EN) + /* Fix for errata FLASH_E201 - Potential program failure after Power On. + * + * Check if the first word was programmed correctly. If a failure is detected, + * retry programming of the first word. + * + * A full description of the errata is in the errata document. */ + pData = (uint32_t *) data; + if (*address != *pData) { + retval = MSC_LoadVerifyAddress(address); + if (mscReturnOk == retval) { + retval = MSC_LoadWriteData(pData, 1); + } + } +#endif + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) +#if (WORDS_PER_DATA_PHASE == 2) + /* Turn off the double word write cycle support. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif +#endif + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * @note + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, this is + * achieved automatically by using attributes in the function proctype. For Keil + * uVision IDE, define a section called "ram_code" and place this manually in + * the project's scatter file. + * + * @param[in] startAddress + * A pointer to the flash page to erase. Must be aligned to the beginning of the page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the flash. + * mscReturnTimeOut - The operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + bool wasLocked; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* An address must be aligned to pages. */ + EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash erase requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Load an address. */ + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnInvalidAddr; + } + + /* Send erase page command. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + /* Wait for the erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for write protected page. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnLocked; + } + if (timeOut == 0) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnTimeOut; + } + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is interrupt-safe, but slower than + * MSC_WriteWordFast(), which writes to flash with interrupts disabled. + * Write data must be aligned to words and contain a number of bytes that is + * divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place it + * manually in the project's scatter file. + * + * This function requires a system core clock at 1 MHz or higher. + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the Flash. + * flashReturnTimeOut - The operation timed out waiting for the flash operation + * to complete, or the MSC module timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWordI(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is faster than MSC_WriteWord(), + * but it disables interrupts. Write data must be aligned to words and contain + * a number of bytes that is divisible by four. + * @warning + * This function is only available for certain devices. + * @note + * It is recommended to erase the flash page before performing a write. + * It is required to run this function from RAM on parts that include a + * flash write buffer. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place this manually + * in the project's scatter file. + * + * @deprecated + * This function is deprecated, the functionality is the same as calling + * @ref MSC_WriteWord(). + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from the Flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the flash. + * flashReturnTimeOut - The operation timed out waiting for flash operation + * to complete. Or the MSC timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWord(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +#if (_SILICON_LABS_32B_SERIES > 0) +/***************************************************************************//** + * @brief + * Writes data from RAM to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that this function only supports writing data from RAM to + * flash, it does not support writing data from flash to flash. + * + * @note + * This function requires that the LDMA clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash. Note that this argument must be an address in RAM. + * This function does not support copying data from flash to flash on series-1 + * devices. Must be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + // Verify that the data argument is in RAM + if (((uint32_t)data < SRAM_BASE) || ((uint32_t)data > (SRAM_BASE + SRAM_SIZE))) { + EFM_ASSERT(false); + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].REQSEL = LDMA_CH_REQSEL_SOURCESEL_MSC + | LDMA_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN |= (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + BUS_RegMaskedClear(&LDMA->CHDONE, (0x1 << ch)); + BUS_RegMaskedClear(&LDMA->CHEN, (0x1 << ch)); + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} +#endif + +#if defined(_MSC_MASSLOCK_MASK) +SL_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + bool wasLocked; + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Unlock the device mass erase. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; + + /* Erase the first 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } + +#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) + /* Erase the second 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } +#endif + + /* Restore the mass erase lock. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + /* This will only successfully return if calling function is also in SRAM. */ + return mscReturnOk; +} +SL_RAMFUNC_DEFINITION_END +#endif // defined(_MSC_MASSLOCK_MASK) + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) \ + || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Read and write existing values in RAM (for ECC initialization). + * + * @details + * This function uses core to load and store the existing data + * values in the given RAM bank. + * + * @param[in] eccBank + * Pointer to ECC RAM bank (MSC_EccBank_Typedef) + ******************************************************************************/ +static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) +{ + volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; + const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); + volatile uint32_t *ctrlreg; + uint32_t enableEcc; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ctrlreg = &ECC_CTRL0_REG; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ctrlreg = &ECC_CTRL1_REG; + } else { + EFM_ASSERT(0); + return; + } +#else + ctrlreg = &ECC_CTRL_REG; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + + EFM_ASSERT(ramptr < endptr); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK)) + enableEcc = eccBank->initSyndromeEnable; +#elif defined(_MPAHBRAM_CTRL_MASK) + /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes + to be written in ECC */ + enableEcc = eccBank->correctionEnable; + + /* Enable ECC syndrome write */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG |= eccBank->initSyndromeEnable; + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG |= eccBank->initSyndromeEnable; + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#endif + +#ifndef __GNUC__ +#define __asm__ asm +#endif + + /* + * Performs a read and write of all RAM address to initialize + * ECC syndromes. ECC is initialized by reading a RAM address + * while ECC is disabled and write it back while ECC is enabled. + * + * HardFault could occur if we try to read values from RAM while ECC + * is enabled and not initialized. In this case, ECC tries to correct the + * value and ended giving the wrong value which could be sometimes an + * non-existing address. + * + * So for ECC initialization to work properly, this must ensures that while + * ECC is enabled, RAM will be accessed only through writes, no reads shall + * occur. It's hard to have such guarantee with C code, because the C + * compiler with optimization settings, can get in the way + * and do some unwanted reads while ECC is enabled. Assembly allows such + * guarantee and let ECC be initialized without triggering errors. + */ + + __asm__ volatile ( + "1:\n\t" /* define label 1 */ + "LDR r1, [%[ramptr]]\n\t" /* load content of ramptr into R1, ECC + is disabled to get a correct value */ + "LDR r0, [%[ctrlreg]]\n\t" /* load ctrlreg content into R0 */ + "ORR r0, r0, %[enableEcc]\n\t" /* OR R0 and enableEcc, and store result + in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + enabled from now on */ + "STR r1, [%[ramptr]]\n\t" /* write back ram content where it was, + syndrome will be written in ECC */ + "BIC r0, r0, %[enableEcc]\n\t" /* bit clear enableEcc from R0, and store + result in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + disabled */ + "ADDS %[ramptr], %[ramptr], #4\n\t" /* increment ramptr by 4 (size of + a word) */ + "CMP %[ramptr], %[endptr]\n\t" /* compare ramptr and endptr... */ + "BCC 1b\n\t" /* ... and jump back to label 1 if Carrry + Clear (meaning ramptr < endptr) */ + "ORR r0, r0, %[enableEcc]\n\t" /* and re-enable ECC ASAP to be sure no */ + "STR r0, [%[ctrlreg]]\n\t" /* STR occurs with ECC disabled */ + :[ramptr] "+r" (ramptr) + :[endptr] "r" (endptr), + [ctrlreg] "r" (ctrlreg), + [enableEcc] "r" (enableEcc) + : "r0", "r1", /* R0 and R1 used as temporary registers */ + "memory" /* Memory pointed by ramptr is modified */ + ); +} + +#else + +/***************************************************************************//** + * @brief + * DMA read and write existing values (for ECC initialization). + * + * @details + * This function uses DMA to read and write the existing data values in + * the RAM region specified by start and size. The function will use the + * 2 DMA channels specified by the channels[2] array. + * + * @param[in] start + * Start address of address range in RAM to read/write. + * + * @param[in] size + * Size of address range in RAM to read/write. + * + * @param[in] channels[2] + * Array of 2 DMA channels to use. + ******************************************************************************/ +static void mscEccReadWriteExistingDma(uint32_t start, + uint32_t size, + uint32_t channels[2]) +{ + uint32_t descCnt = 0; + volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; + uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); + /* Assert that the 2 DMA channel numbers are different. */ + EFM_ASSERT(channels[0] != channels[1]); + + /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order + to match the total xfer size of the descriptor chain with the largest + ECC RAM bank. */ + EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); + + /* Initialize LDMA descriptor chain. */ + do { + dmaDesc[descCnt][0] = /* DMA desc CTRL word */ + LDMA_CH_CTRL_STRUCTTYPE_TRANSFER + | LDMA_CH_CTRL_STRUCTREQ + | _LDMA_CH_CTRL_XFERCNT_MASK + | LDMA_CH_CTRL_BLOCKSIZE_ALL + | LDMA_CH_CTRL_REQMODE_ALL + | LDMA_CH_CTRL_SRCINC_ONE + | LDMA_CH_CTRL_SIZE_WORD + | LDMA_CH_CTRL_DSTINC_ONE; + + /* source and destination address */ + dmaDesc[descCnt][1] = start; + dmaDesc[descCnt][2] = start; + /* link to next descriptor */ + dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK + | (((uint32_t) &dmaDesc[descCnt + 1][0]) + & _LDMA_CH_LINK_LINKADDR_MASK); + + start += ECC_DMA_DESC_SIZE; + size -= ECC_DMA_DESC_SIZE; + descCnt++; + } while (size); + + /* Make sure descCnt is valid to avoid out-of-bounds access when writing to + dmaDesc array. */ + if ((descCnt < 2) || (descCnt > ECC_DMA_DESCS)) { + while (true) { + EFM_ASSERT(false); + } + } + + /* Now, divide the descriptor list in two parts, one for each channel, + by setting the link bit and address 0 of the descriptor in the middle + to 0. */ + dmaDesc[(descCnt / 2) - 1][3] = 0; + + /* Set last descriptor link bit and address to 0. */ + dmaDesc[descCnt - 1][3] = 0; + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Start the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif +#endif + /* Round robin scheduling for all channels (0 = no fixed priority channels). + */ + LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + LDMA->CHEN = 0; + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Disable LDMA interrupts, and clear interrupt status. */ + LDMA->IEN = 0; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + + /* Disable looping */ + LDMA->CH[channels[0]].LOOP = 0; + LDMA->CH[channels[1]].LOOP = 0; + + /* Set descriptor address for first channel. */ + LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Set descriptor address for second channel. */ + LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Clear the channel done flags. */ + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); + + /* Start transfer by loading descriptors. */ + LDMA->LINKLOAD = chMask; + + /* Wait until finished. */ + while (!( +#if defined(_LDMA_CHSTATUS_MASK) + ((LDMA->CHSTATUS & chMask) == 0) +#else + ((LDMA->CHEN & chMask) == 0) +#endif + && ((LDMA->CHDONE & chMask) == chMask))) { + } + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Stop the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +#endif +} +#endif // #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Initialize ECC for a given memory bank. + * + * @brief + * This function initializes ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + * @param[in] dmaChannels + * Array of 2 DMA channels that may be used during ECC initialization. + * + ******************************************************************************/ +static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, + uint32_t dmaChannels[2]) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) \ + || defined(_MPAHBRAM_CTRL_MASK) + (void) dmaChannels; +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Disable ECC write */ + ECC_CTRL_REG &= ~eccBank->initSyndromeEnable; +#endif + /* Initialize ECC syndromes by using core cpu to load and store the existing + data values in RAM. */ + mscEccReadWriteExistingPio(eccBank); +#else + /* Enable ECC write */ + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + /* Initialize ECC syndromes by using DMA to read and write the existing + data values in RAM. */ + mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); +#endif + + /* Clear any ECC errors that may have been reported before or during + initialization. */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Enable ECC decoder to detect and report ECC errors. */ + ECC_CTRL_REG |= eccBank->correctionEnable; +#endif + + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Disable ECC for a given memory bank. + * + * @brief + * This function disables ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + ******************************************************************************/ +static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) +{ + /* Disable ECC write (encoder) and checking (decoder). */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } +#else + ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ +} + +/***************************************************************************//** + * @brief + * Configure Error Correcting Code (ECC). + * + * @details + * This function configures ECC support according to the configuration + * input parameter. If the user requests enabling ECC for a given RAM bank + * this function will initialize ECC memory (syndromes) for the bank by + * reading and writing the existing values in memory. I.e. all data is + * preserved. The initialization process runs in a critical section + * disallowing interrupts and thread scheduling, and will consume a + * considerable amount of clock cycles. Therefore the user should carefully + * assess where to call this function. The user can consider to increase + * the clock frequency in order to reduce the execution time. + * This function makes use of 2 DMA channels to move data to/from RAM in an + * efficient way. The user can select which 2 DMA channels to use in order + * to avoid conflicts with the application. However the user must make sure + * that no other DMA operations takes place while this function is executing. + * If the application has been using the DMA controller prior to calling this + * function, the application will need to reinitialize DMA registers after + * this function has completed. + * + * @note + * This function protects the ECC initialization procedure from interrupts + * and other threads by using a critical section (defined by em_core.h) + * When running on RTOS the user may need to override CORE_EnterCritical + * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. + * + * @param[in] eccConfig + * ECC configuration + ******************************************************************************/ +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) +{ + unsigned int cnt; +#if defined(ECC_FAULT_CTRL_REG) + uint32_t faultCtrlReg = ECC_FAULT_CTRL_REG; + /* Disable ECC faults if ecc fault ctrl register is defined. */ + faultCtrlReg &= ~ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif + + /* Loop through the ECC banks array, enable or disable according to + the eccConfig->enableEccBank array. */ + for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { + if (eccConfig->enableEccBank[cnt]) { + mscEccBankInit(&eccBankTbl[cnt], eccConfig->dmaChannels); + } else { + mscEccBankDisable(&eccBankTbl[cnt]); + } + } + +#if defined(ECC_FAULT_CTRL_REG) && !defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) + /* + * Enable ECC faults if ecc fault ctrl register is set. + * On Series 1 Config 1, aka EFM32GG11, ECC faults should stay disabled. + * Reload register first, in case it was modified and/or shared by bank + * init functions. + */ + faultCtrlReg = ECC_FAULT_CTRL_REG; + faultCtrlReg |= ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif +} + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port to use to access DMEM. + * + * @details + * This function configures which MPAHBRAM slave port is used to access DMEM. + * Depending on the use case, it might improve performance by spreading the + * load over the N ports (N is usually 2 or 4), instead of starving because a + * port is used by another master. + * + * @param[in] master + * AHBHOST master to be configured. + * @param[in] port + * AHBHOST slave port to use. + ******************************************************************************/ +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + uint32_t bitfieldMask = DMEM_NUM_PORTS - 1; +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1; +#endif + + /* make sure master is within the mask of port map that can be changed + * make sure port is a sensible value + */ + EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0); + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(port < DMEM_NUM_PORTS); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(port < DMEM0_NUM_PORTS); +#endif + +#if defined(CMU_CLKEN0_SYSCFG) + bool disableSyscfgClk = false; + + if (!(CMU->CLKEN0 & _CMU_CLKEN0_SYSCFG_MASK)) { + disableSyscfgClk = true; + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + } +#endif + + BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, + bitfieldMask << master, + (uint32_t)port << master); + +#if defined(CMU_CLKEN0_SYSCFG) + if (disableSyscfgClk) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port priority for arbitration when multiple concurrent + * transactions to DMEM. + * + * @details + * This function configures which MPAHBRAM slave port will have priority. + * The AHB port arbitration default scheme, round-robin arbitration, is + * selected when portPriority == mscPortPriorityNone. + * + * @note + * Doing this can potentially starve the others AHB port(s). + * + * @param[in] portPriority + * AHBHOST slave port having elevated priority. + ******************************************************************************/ +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); + BUS_RegMaskedWrite(&DMEM1->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Get MPAHBRAM port arbitration priority selection. + * + * @details + * This function returns the AHBHOST slave with raised priority. + * + * @return + * Returns the AHBHOST slave port given priority or none. + ******************************************************************************/ +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void) +{ + uint32_t port = 0; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + port = BUS_RegMaskedRead(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + port = BUS_RegMaskedRead(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#endif + + return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +} +#endif /* if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) */ + +/** @} (end addtogroup msc) */ +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_opamp.c b/Libs/platform/emlib/src/em_opamp.c new file mode 100644 index 0000000..d80f485 --- /dev/null +++ b/Libs/platform/emlib/src/em_opamp.c @@ -0,0 +1,700 @@ +/***************************************************************************//** + * @file + * @brief Operational Amplifier (OPAMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_opamp.h" +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) + +#include "em_system.h" +#include "sl_assert.h" + +/* *INDENT-OFF* */ +/***************************************************************************//** + * @addtogroup opamp OPAMP - Operational Amplifier + * @brief Operational Amplifier (OPAMP) peripheral API + * @details + * This module contains functions to: + * @li OPAMP_Enable() Configure and enable OPAMP. + * @li OPAMP_Disable() Disable OPAMP. + * + * @if DOXYDOC_P1_DEVICE + * All OPAMP functions assume that the DAC clock is running. If DAC is not + * used, the clock can be turned off when OPAMPs are configured. + * @elseif DOXYDOC_P2_DEVICE + * All OPAMP functions assume that the VDAC clock is running. If VDAC is not + * used, the clock can be turned off when the OPAMPs are configured. + * @endif + * + * If the available gain values don't suit the application at hand, the resistor + * ladders can be disabled and external gain programming resistors used. + * + * A number of predefined OPAMP setup macros are available for configuration + * of the most common OPAMP topologies (see figures below). + * + * @note + * The terms POSPAD and NEGPAD in the figures are used to indicate that these + * pads should be connected to a suitable signal ground. + * + * \nUnity gain voltage follower.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_UNITY_GAIN and + * @ref OPA_INIT_UNITY_GAIN_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_UNITY_GAIN. + * @endif + * @verbatim + + |\ + ___________|+\ + | \_______ + ___|_ / | + | | / | + | |/ | + |___________| + @endverbatim + * + * \nNon-inverting amplifier.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_NON_INVERTING and + * @ref OPA_INIT_NON_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_NON_INVERTING. + * @endif + * @verbatim + + |\ + ___________|+\ + | \_______ + ___|_ / | + | | / | + | |/ | + |_____R2____| + | + R1 + | + NEGPAD @endverbatim + * + * \nInverting amplifier.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_INVERTING and + * @ref OPA_INIT_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_INVERTING. + * @endif + * @verbatim + + _____R2____ + | | + | |\ | + ____R1_|___|_\ | + | \____|___ + ___| / + | |+/ + | |/ + | + POSPAD @endverbatim + * + * \nCascaded non-inverting amplifiers.\n + * Use predefined macros @ref OPA_INIT_CASCADED_NON_INVERTING_OPA0, + * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA1 and + * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA2. + * @verbatim + + |\ |\ |\ + ___________|+\ OPA0 ___________|+\ OPA1 ___________|+\ OPA2 + | \_________| | \_________| | \_______ + ___|_ / | ___|_ / | ___|_ / | + | | / | | | / | | | / | + | |/ | | |/ | | |/ | + |_____R2____| |_____R2____| |_____R2____| + | | | + R1 R1 R1 + | | | + NEGPAD NEGPAD NEGPAD @endverbatim + * + * \nCascaded inverting amplifiers.\n + * Use predefined macros @ref OPA_INIT_CASCADED_INVERTING_OPA0, + * @ref OPA_INIT_CASCADED_INVERTING_OPA1 and + * @ref OPA_INIT_CASCADED_INVERTING_OPA2. + * @verbatim + + _____R2____ _____R2____ _____R2____ + | | | | | | + | |\ | | |\ | | |\ | + ____R1_|___|_\ | ____R1_|___|_\ | ____R1_|___|_\ | + | \____|____| | \____|___| | \____|__ + ___| / ___| / ___| / + | |+/ OPA0 | |+/ OPA1 | |+/ OPA2 + | |/ | |/ | |/ + | | | + POSPAD POSPAD POSPAD @endverbatim + * + * \nDifferential driver with two opamp's.\n + * Use predefined macros @ref OPA_INIT_DIFF_DRIVER_OPA0 and + * @ref OPA_INIT_DIFF_DRIVER_OPA1. + * @verbatim + + __________________________ + | + + | _____R2____ + |\ | | | + ___________|+\ OPA0 | | |\ OPA1 | + | \_________|____R1_|___|_\ | _ + ___|_ / | | \____|______ + | | / | ___| / + | |/ | | |+/ + |________________| | |/ + | + POSPAD @endverbatim + * + * \nDifferential receiver with three opamp's.\n + * Use predefined macros @ref OPA_INIT_DIFF_RECEIVER_OPA0, + * @ref OPA_INIT_DIFF_RECEIVER_OPA1 and @ref OPA_INIT_DIFF_RECEIVER_OPA2. + * @verbatim + + |\ + __________|+\ OPA1 + _ | \_________ + ___|_ / | | _____R2____ + | | / | | | | + | |/ | | | |\ | + |___________| |____R1_|___|_\ | + | \____|___ + |\ ____R1_ ___| / + +__________|+\ OPA0 | | |+/ OPA2 + | \_________| | |/ + ___|_ / | R2 + | | / | | + | |/ | NEGPAD OPA0 + |___________| + @endverbatim + * + * @if DOXYDOC_P2_DEVICE + * \nInstrumentation amplifier.\n + * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and + * @ref OPA_INIT_INSTR_AMP_OPA1. + * @verbatim + + |\ + __________|+\ OPA1 + | \______________ + ___|_ / | + | | / | + | |/ R2 + |____________| + | + R1 + | + R1 + ____________| + | | + | R2 + | |\ | + |___|+\ OPA0 | + | \_____|________ + __________|_ / + | / + |/ + + @endverbatim + * @endif + * + * @{ + ******************************************************************************/ +/* *INDENT-ON* */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable an Operational Amplifier. + * + * @if DOXYDOC_P1_DEVICE + * @param[in] dac + * A pointer to the DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @param[in] dac + * A pointer to the VDAC peripheral register block. + * @endif + * + * @param[in] opa + * Selects an OPA, valid values are OPA0, OPA1, and OPA2. + ******************************************************************************/ +void OPAMP_Disable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(DAC_REF_VALID(dac)); + EFM_ASSERT(DAC_OPA_VALID(opa)); + + if (opa == OPA0) { + dac->CH0CTRL &= ~DAC_CH0CTRL_EN; + dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN; + } else if (opa == OPA1) { + dac->CH1CTRL &= ~DAC_CH1CTRL_EN; + dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN; + } else { /* OPA2 */ + dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + + if (opa == OPA0) { +#if defined(VDAC_STATUS_OPA0ENS) + dac->CMD |= VDAC_CMD_OPA0DIS; + while (dac->STATUS & VDAC_STATUS_OPA0ENS) { + } +#endif +#if defined(VDAC_STATUS_OPA1ENS) + } else if (opa == OPA1) { + dac->CMD |= VDAC_CMD_OPA1DIS; + while (dac->STATUS & VDAC_STATUS_OPA1ENS) { + } +#endif +#if defined(VDAC_STATUS_OPA2ENS) + } else if (opa == OPA2) { + dac->CMD |= VDAC_CMD_OPA2DIS; + while (dac->STATUS & VDAC_STATUS_OPA2ENS) { + } +#endif + } else { /* OPA3 */ +#if defined(VDAC_STATUS_OPA3ENS) + dac->CMD |= VDAC_CMD_OPA3DIS; + while (dac->STATUS & VDAC_STATUS_OPA3ENS) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Configure and enable an Operational Amplifier. + * + * @if DOXYDOC_P1_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags + * (defined in \_dac.h) OR'ed together. @n @n + * For OPA0: + * @li DAC_OPA0MUX_OUTPEN_OUT0 + * @li DAC_OPA0MUX_OUTPEN_OUT1 + * @li DAC_OPA0MUX_OUTPEN_OUT2 + * @li DAC_OPA0MUX_OUTPEN_OUT3 + * @li DAC_OPA0MUX_OUTPEN_OUT4 + * + * For OPA1: + * @li DAC_OPA1MUX_OUTPEN_OUT0 + * @li DAC_OPA1MUX_OUTPEN_OUT1 + * @li DAC_OPA1MUX_OUTPEN_OUT2 + * @li DAC_OPA1MUX_OUTPEN_OUT3 + * @li DAC_OPA1MUX_OUTPEN_OUT4 + * + * For OPA2: + * @li DAC_OPA2MUX_OUTPEN_OUT0 + * @li DAC_OPA2MUX_OUTPEN_OUT1 + * + * E.g: @n + * init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT4; + * + * @param[in] dac + * A pointer to the DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + * (defined in \_vdac.h) OR'ed together. @n @n + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + * + * For example: @n + * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + * @param[in] dac + * A pointer to the VDAC peripheral register block. + * @endif + * + * @param[in] opa + * Selects an OPA, valid values are OPA0, OPA1, and OPA2. + * + * @param[in] init + * A pointer to a structure containing OPAMP initialization information. + ******************************************************************************/ +void OPAMP_Enable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa, + const OPAMP_Init_TypeDef *init) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t gain; + + EFM_ASSERT(DAC_REF_VALID(dac)); + EFM_ASSERT(DAC_OPA_VALID(opa)); + EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK + >> _DAC_BIASPROG_BIASPROG_SHIFT)); + + if (opa == OPA0) { + EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_BIASPROG_MASK + | DAC_BIASPROG_HALFBIAS)) + | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); + + if (init->defaultOffset) { + gain = dac->CAL & _DAC_CAL_GAIN_MASK; + SYSTEM_GetCalibrationValue(&dac->CAL); + dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; + } else { + EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK + >> _DAC_CAL_CH0OFFSET_SHIFT)); + + dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK) + | (init->offset << _DAC_CAL_CH0OFFSET_SHIFT); + } + + dac->OPA0MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA0MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA0MUX_PPEN : 0); + + dac->CH0CTRL |= DAC_CH0CTRL_EN; + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA0SHORT + | _DAC_OPACTRL_OPA0LPFDIS_MASK + | DAC_OPACTRL_OPA0HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA0SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA0LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0) + | DAC_OPACTRL_OPA0EN; + } else if ( opa == OPA1 ) { + EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_BIASPROG_MASK + | DAC_BIASPROG_HALFBIAS)) + | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); + + if (init->defaultOffset) { + gain = dac->CAL & _DAC_CAL_GAIN_MASK; + SYSTEM_GetCalibrationValue(&dac->CAL); + dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; + } else { + EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK + >> _DAC_CAL_CH1OFFSET_SHIFT)); + + dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK) + | (init->offset << _DAC_CAL_CH1OFFSET_SHIFT); + } + + dac->OPA1MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA1MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA1MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA1MUX_PPEN : 0); + + dac->CH1CTRL |= DAC_CH1CTRL_EN; + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA1SHORT + | _DAC_OPACTRL_OPA1LPFDIS_MASK + | DAC_OPACTRL_OPA1HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA1SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA1LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0) + | DAC_OPACTRL_OPA1EN; + } else { /* OPA2 */ + EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE) + || (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD) + || (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP) + || (init->posSel == DAC_OPA2MUX_POSSEL_OPATAP)); + + EFM_ASSERT((init->outMode & ~DAC_OPA2MUX_OUTMODE) == 0); + + EFM_ASSERT((init->outPen & ~_DAC_OPA2MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_OPA2BIASPROG_MASK + | DAC_BIASPROG_OPA2HALFBIAS)) + | (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0); + + if (init->defaultOffset) { + SYSTEM_GetCalibrationValue(&dac->OPAOFFSET); + } else { + EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK + >> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT)); + dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK) + | (init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT); + } + + dac->OPA2MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA2MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA2MUX_PPEN : 0); + + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA2SHORT + | _DAC_OPACTRL_OPA2LPFDIS_MASK + | DAC_OPACTRL_OPA2HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA2SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA2LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA2LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) + | DAC_OPACTRL_OPA2EN; + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + uint32_t calData = 0; + uint32_t warmupTime; + + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK + >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); + EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK + >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); + EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); + EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) + || (init->drvStr == opaDrvStrLowAccLowStr) + || (init->drvStr == opaDrvStrHighAccHighStr) + || (init->drvStr == opaDrvStrHigherAccHighStr)); + + /* Disable OPAMP before writing to registers. */ + OPAMP_Disable(dac, opa); + + /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ + switch (opa) { +#if defined(VDAC_STATUS_OPA0ENS) + case OPA0: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA1ENS) + case OPA1: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA2ENS) + case OPA2: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA3ENS) + case OPA3: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL0 : DEVINFO->OPA3CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL1 : DEVINFO->OPA3CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL2 : DEVINFO->OPA3CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL3 : DEVINFO->OPA3CAL7); + break; + } + break; +#endif + } + if (!init->defaultOffsetN) { + EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK + >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) + | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); + } + if (!init->defaultOffsetP) { + EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK + >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) + | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); + } + + dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); + + dac->OPA[opa].MUX = (uint32_t)init->resSel + | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel; + + dac->OPA[opa].OUT = (uint32_t)init->outMode + | (uint32_t)init->outPen; + + switch (init->drvStr) { + case opaDrvStrHigherAccHighStr: + warmupTime = 6; + break; + + case opaDrvStrHighAccHighStr: + warmupTime = 8; + break; + + case opaDrvStrLowAccLowStr: + warmupTime = 85; + break; + + case opaDrvStrLowerAccLowStr: + default: + warmupTime = 100; + break; + } + + dac->OPA[opa].TIMER = (uint32_t)(init->settleTime + << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) + | (uint32_t)(warmupTime + << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) + | (uint32_t)(init->startupDly + << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); + + dac->OPA[opa].CTRL = (init->aportYMasterDisable + ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) + | (init->aportXMasterDisable + ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) + | (uint32_t)init->prsOutSel + | (uint32_t)init->prsSel + | (uint32_t)init->prsMode + | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) + | (init->halfDrvStr + ? VDAC_OPA_CTRL_OUTSCALE_HALF + : VDAC_OPA_CTRL_OUTSCALE_FULL) + | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) + | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) + | (uint32_t)init->drvStr; + + if (opa == OPA0) { +#if defined(VDAC_STATUS_OPA0ENS) + dac->CMD |= VDAC_CMD_OPA0EN; +#endif +#if defined(VDAC_STATUS_OPA1ENS) + } else if (opa == OPA1) { + dac->CMD |= VDAC_CMD_OPA1EN; +#endif +#if defined(VDAC_STATUS_OPA2ENS) + } else if (opa == OPA2) { + dac->CMD |= VDAC_CMD_OPA2EN; +#endif +#if defined(VDAC_STATUS_OPA3ENS) + } else { /* OPA3 */ + dac->CMD |= VDAC_CMD_OPA3EN; +#endif + } + +#endif +} + +/** @} (end addtogroup opamp) */ + +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_pcnt.c b/Libs/platform/emlib/src/em_pcnt.c new file mode 100644 index 0000000..aaf007d --- /dev/null +++ b/Libs/platform/emlib/src/em_pcnt.c @@ -0,0 +1,1067 @@ +/***************************************************************************//** + * @file + * @brief Pulse Counter (PCNT) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_pcnt.h" +#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) + +#include "em_cmu.h" +#include "sl_assert.h" +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup pcnt PCNT - Pulse Counter + * @brief Pulse Counter (PCNT) Peripheral API + * @details + * This module contains functions to control the PCNT peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The PCNT decodes incoming pulses. The module has + * a quadrature mode which may be used to decode the speed and direction of a + * mechanical shaft. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the PCNT register block pointer reference for assert statements. */ +#if (PCNT_COUNT == 1) +#define PCNT_REF_VALID(ref) ((ref) == PCNT0) +#elif (PCNT_COUNT == 2) +#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1)) +#elif (PCNT_COUNT == 3) +#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) \ + || ((ref) == PCNT2)) +#else +#error "Undefined number of pulse counters (PCNT)." +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_2) +static PCNT_CntEvent_TypeDef initCntEvent; +static PCNT_CntEvent_TypeDef initAuxCntEvent; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Map PCNT structure into an instance number. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @return + * An instance number. + ******************************************************************************/ +__STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt) +{ + return ((uint32_t)pcnt - PCNT0_BASE) / 0x400; +} +#endif +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Reset PCNT counters and TOP register. + * + * @note + * Notice that special SYNCBUSY handling is not applicable for the RSTEN + * bit of the control register, so we don't need to wait for it when only + * modifying RSTEN. (It would mean undefined wait time if clocked by an external + * clock.) The SYNCBUSY bit will however be set, leading to a synchronization + * in the LF domain, with, in reality, no changes. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + ******************************************************************************/ +void PCNT_CounterReset(PCNT_TypeDef *pcnt) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Enable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Disable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); +#else + /* Reset of the CNT and TOP register. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_CNTRST | PCNT_CMD_AUXCNTRST; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + pcnt->TOP = _PCNT_TOP_RESETVALUE; +#endif +} + +/***************************************************************************//** + * @brief + * Set PCNT operational mode. + * + * @details + * Notice that this function does not do any configuration. Setting operational + * mode is normally only required after initialization is done, and if not + * done as part of initialization or if requiring to disable/reenable pulse + * counter. + * + * @note + * This function may stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module, since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] mode + * An operational mode to use for PCNT. + ******************************************************************************/ +void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode) +{ + uint32_t tmp; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* Set as specified. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK; + tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT; + + /* LF register about to be modified requires sync; busy check. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = tmp; +#else + /* Disable module if disable mode is passed. */ + if (mode == pcntModeDisable) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + return; + } + /* Check if given mode is same as already configured. */ + tmp = (pcnt->CFG & _PCNT_CFG_MODE_MASK) >> _PCNT_CFG_MODE_SHIFT; + if (tmp != mode) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + pcnt->CFG_SET = (uint32_t)mode << _PCNT_CFG_MODE_SHIFT; + } + /* Enable module */ + pcnt->EN_SET = PCNT_EN_EN; + /* Start Counters*/ + if (initCntEvent != pcntCntEventNone) { + PCNT_StartMainCnt(pcnt); + } + if (initAuxCntEvent != pcntCntEventNone) { + PCNT_StartAuxCnt(pcnt); + } + +#endif +} + +/***************************************************************************//** + * @brief + * Returns if the PCNT module is enabled or not. + * + * @details + * Notice that this function does not do any configuration. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @return Returns TRUE if the module is enabled. + ******************************************************************************/ +bool PCNT_IsEnabled(PCNT_TypeDef *pcnt) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + return ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE); +#else + return (pcnt->EN & _PCNT_EN_EN_MASK); +#endif +} + +/***************************************************************************//** + * @brief + * Set the counter and top values. + * + * @details + * The pulse counter is disabled while changing these values and reenabled + * (if originally enabled) when values have been set. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module, since stall time may be + * undefined. The counter should normally only be set when + * operating in (or about to enable) #pcntModeOvsSingle mode. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] count + * A value to set in the counter register. + * + * @param[in] top + * A value to set in the top register. + ******************************************************************************/ +void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + uint32_t ctrl; +#endif + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > top); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > top); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > top); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Keep the current control setting, must be restored. */ + ctrl = pcnt->CTRL; + + /* If enabled, disable pulse counter before changing values. */ + if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE; + } + + /* Load into TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = count; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + + /* This bit has no effect on rev. C and onwards parts - for compatibility. */ + pcnt->CMD = PCNT_CMD_LTOPBIM; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + /* Load TOP into CNT. */ + pcnt->CMD = PCNT_CMD_LCNTIM; + + /* Restore TOP. ('count' setting has been loaded into pcnt->TOP, better + * to use 'top' than pcnt->TOP in compare, since latter may not + * be visible yet.) */ + if (top != count) { + /* Wait for the command to sync LCNTIM before setting TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + /* Load into TOPB. No need to check for TOPB sync complete, which + * has been ensured above. */ + pcnt->TOPB = top; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LTOPBIM; + } + + /* Reenable if it was enabled. */ + PCNT_Enable(pcnt, (PCNT_Mode_TypeDef)(ctrl & _PCNT_CTRL_MODE_MASK)); + if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD); + pcnt->CTRL = ctrl; + } +#else + /* Load into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + pcnt->TOP = count; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + + /* Load TOP into CNT. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LCNTIM; + + if (top != count) { + /* Wait for the command to sync LCNTIM before setting TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + pcnt->TOP = top; + } +#endif +} + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Enable/disable the selected PRS input of PCNT. + * + * @details + * Notice that this function does not do any configuration. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] prsInput + * PRS input (S0 or S1) of the selected PCNT module. + * + * @param[in] enable + * Set to true to enable, false to disable the selected PRS input. + ******************************************************************************/ +void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, + PCNT_PRSInput_TypeDef prsInput, + bool enable) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + bool module_enable = PCNT_IsEnabled(pcnt); + + /* Disable module before writing to CFG register. */ + if (module_enable == true) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif +#endif + + /* Enable/disable the selected PRS input on the selected PCNT module. */ + switch (prsInput) { + /* Enable/disable PRS input S0. */ + case pcntPRSInputS0: +#if defined(_PCNT_INPUT_MASK) + BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2) + BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S0PRSEN_SHIFT, enable); +#endif + break; + + /* Enable/disable PRS input S1. */ + case pcntPRSInputS1: +#if defined(_PCNT_INPUT_MASK) + BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2) + BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S1PRSEN_SHIFT, enable); +#endif + break; + + /* An invalid parameter, asserted. */ + default: + EFM_ASSERT(0); + break; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* Re-Enable if necessary the PCNT module after change. */ + if (module_enable == true) { + pcnt->EN_SET = PCNT_EN_EN; + } +#endif +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * PCNT register synchronization freeze control. + * + * @details + * Some PCNT registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several registers to be + * modified before passing them to the LF domain simultaneously, which + * takes place when the freeze mode is disabled. + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing PCNT synchronization to the LF domain to complete (normally + * synchronization will not be in progress). However, for this reason, when + * using freeze mode, modifications of registers requiring the LF synchronization + * should be done within one freeze enable/disable block to avoid unnecessary + * stalling. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] enable + * @li True - enable freeze, modified registers are not propagated to the + * LF domain. + * @li False - disables freeze, modified registers are propagated to LF + * domain. + ******************************************************************************/ +void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + if (enable) { + /* Wait for any ongoing LF synchronization to complete to + * protect against the rare case when a user: + * - modifies a register requiring LF sync + * - then enables freeze before LF sync completed + * - then modifies the same register again + * since modifying a register while it is in sync progress should be + * avoided. */ + while (pcnt->SYNCBUSY) { + } + + pcnt->FREEZE = PCNT_FREEZE_REGFREEZE; + } else { + pcnt->FREEZE = 0; + } +} +#endif + +/***************************************************************************//** + * @brief + * Initialize the pulse counter. + * + * @details + * This function will configure the pulse counter. The clock selection is + * configured as follows, depending on operational mode: + * + * @li #pcntModeOvsSingle - Use LFACLK. + * @li #pcntModeExtSingle - Use external PCNTn_S0 pin. + * @li #pcntModeExtQuad - Use external PCNTn_S0 pin. + * + * Notice that the LFACLK must be enabled in all modes, since some basic setup + * is done with this clock even if the external pin clock usage mode is chosen. + * The pulse counter clock for the selected instance must also be enabled + * prior to initialization. + * + * Notice that pins used by the PCNT module must be properly configured + * by the user explicitly through setting the ROUTE register for + * the PCNT to work as intended. + * + * Writing to CNT will not occur in external clock modes (EXTCLKQUAD and + * EXTCLKSINGLE) because the external clock rate is unknown. The user should + * handle it manually depending on the application. + * + * TOPB is written for all modes but in external clock mode it will take + * 3 external clock cycles to sync to TOP. + * + * + * @note + * Initializing requires synchronization into the low-frequency domain. This + * may cause a delay. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure. + ******************************************************************************/ +void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init) +{ + unsigned int inst = 0; + uint32_t tmp; + + (void)&tmp; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->top); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->top); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->top); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Map the pointer to an instance. */ + inst = PCNT_Map(pcnt); +#endif + +#if defined(_PCNT_INPUT_MASK) + /* Selecting the PRS channels for the PRS input sources of the PCNT. These are + * written with a Read-Modify-Write sequence to keep the value of the + * input enable bits which can be modified using PCNT_PRSInputEnable(). */ + tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK); + tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) + | ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT); + pcnt->INPUT = tmp; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Build the CTRL setting, except for mode. */ + tmp = 0; + if (init->negEdge) { + tmp |= PCNT_CTRL_EDGE_NEG; + } + + if (init->countDown) { + tmp |= PCNT_CTRL_CNTDIR_DOWN; + } + +#if defined(PCNT_CTRL_FILT) + if (init->filter) { + tmp |= PCNT_CTRL_FILT; + } +#endif + +#if defined(PCNT_CTRL_HYST) + if (init->hyst) { + tmp |= PCNT_CTRL_HYST; + } +#endif + +#if defined(PCNT_CTRL_S1CDIR) + if (init->s1CntDir) { + tmp |= PCNT_CTRL_S1CDIR; + } +#endif + + /* Configure counter events for regular and auxiliary counters. */ +#if defined(_PCNT_CTRL_CNTEV_SHIFT) + tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; +#endif + +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) + { + /* Modify the auxCntEvent value before writing to the AUXCNTEV field in + the CTRL register because the AUXCNTEV field values are different than + the CNTEV field values, and cntEvent and auxCntEvent are of the same type + PCNT_CntEvent_TypeDef. + */ + uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */ + switch (init->auxCntEvent) { + case pcntCntEventBoth: + auxCntEventField = pcntCntEventNone; + break; + +#if defined(_PCNT_CTRL_CNTEV_NONE) + case pcntCntEventNone: + auxCntEventField = pcntCntEventBoth; + break; +#endif + + case pcntCntEventUp: + case pcntCntEventDown: + auxCntEventField = init->auxCntEvent; + break; + + default: + /* An invalid parameter, asserted. */ + EFM_ASSERT(0); + break; + } + tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT; + } +#endif + + /* Reset the pulse counter while changing the clock source. The reset bit */ + /* is asynchronous, no need to check for SYNCBUSY. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Select LFACLK to clock in the control setting. */ + CMU_PCNTClockExternalSet(inst, false); + + /* Handling depends on whether using an external clock. */ + switch (init->mode) { + case pcntModeExtSingle: + case pcntModeExtQuad: + tmp |= ((uint32_t)init->mode) << _PCNT_CTRL_MODE_SHIFT; + + /* In most cases, the SYNCBUSY bit is set due to the reset bit set and waiting + * for asynchronous reset bit is strictly not necessary. + * In theory, other operations on CTRL register may have been done + * outside this function, so wait. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + + /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing + * the clock source to an external clock. */ + pcnt->CTRL = PCNT_CTRL_RSTEN; + + /* Wait until the CTRL write is synchronized into the LF domain. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + + /* Change to the external clock BEFORE disabling reset. */ + CMU_PCNTClockExternalSet(inst, true); + + /* Write to TOPB. If using the external clock, TOPB will sync to TOP at the same + * time as the mode ensuring that if the user chooses to count + * down, the first "countable" pulse will make CNT go to TOP and not 0xFF + * (default TOP value). */ + pcnt->TOPB = init->top; + + /* This bit has no effect on rev. C and onwards parts - for compatibility. */ + pcnt->CMD = PCNT_CMD_LTOPBIM; + + /* Write the CTRL register with the configurations. + * This should be written after TOPB in the eventuality of a pulse between + * these two writes that would cause the CTRL register to be synced one + * clock cycle earlier than the TOPB. */ + pcnt->CTRL = tmp; + + /* There are no syncs for TOP, CMD, or CTRL because the clock rate is unknown + * and the program could stall. + * These will be synced within 3 clock cycles of the external clock. / + * For the same reason CNT cannot be written here. */ + break; + + /* pcntModeDisable */ + /* pcntModeOvsSingle */ + /* pcntModeOvsQuadx */ + default: + /* No need to set disabled mode if already disabled. */ + if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + /* Set control to disabled mode and leave reset on until ensured disabled. + * No need to wait for CTRL SYNCBUSY completion. It was + * triggered by the reset bit above, which is asynchronous. */ + pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN; + + /* Wait until the CTRL write is synchronized into the LF domain before proceeding + * to disable reset. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + } + + /* Disable reset bit. The counter should now be in disabled mode. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); + + /* Set the counter and top values as specified. */ + PCNT_CounterTopSet(pcnt, init->counter, init->top); + + /* Enter oversampling mode if selected. */ + if (init->mode != pcntModeDisable) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT); + } + break; + } + +#else + /* If PCNT is enabled wait for all SYNCBUSY signals to complete. */ + if (pcnt->EN == 1U) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + + /* Disable PCNT. */ + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + /* Build the CFG setting. */ + pcnt->CFG &= ~(_PCNT_CFG_DEBUGHALT_MASK | _PCNT_CFG_FILTEN_MASK | _PCNT_CFG_HYST_MASK); + pcnt->CFG |= (((uint32_t)init->filter) << _PCNT_CFG_FILTEN_SHIFT) + | (((uint32_t)init->hyst) << _PCNT_CFG_HYST_SHIFT) + | (((uint32_t)init->debugHalt) << _PCNT_CFG_DEBUGHALT_SHIFT); + + /* Set Mode setting. */ + /* Write the CFG register with the configurations. */ + if (init->mode != pcntModeDisable) { + pcnt->CFG = ((pcnt->CFG & (~_PCNT_CFG_MODE_MASK)) | (((uint32_t)init->mode) << _PCNT_CFG_MODE_SHIFT)); + } + + pcnt->EN_SET = PCNT_EN_EN; + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + + /* Build the CTRL setting */ + tmp = (((uint32_t)init->negEdge) << _PCNT_CTRL_EDGE_SHIFT) + | (((uint32_t)init->countDown) << _PCNT_CTRL_CNTDIR_SHIFT) + | (((uint32_t)init->s1CntDir) << _PCNT_CTRL_S1CDIR_SHIFT); + + /* Configure counter events for regular and auxiliary counters. */ + if (init->cntEvent != PCNT_CNT_EVENT_NONE) { + tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; + } + if (init->auxCntEvent != PCNT_CNT_EVENT_NONE) { + tmp |= ((uint32_t)init->auxCntEvent) << _PCNT_CTRL_AUXCNTEV_SHIFT; + } + + pcnt->CTRL = tmp; + + /* Set PRS inputs */ + EFM_ASSERT(init->s0PRS < PRS_ASYNC_CH_NUM); + EFM_ASSERT(init->s1PRS < PRS_ASYNC_CH_NUM); + PRS->CONSUMER_PCNT0_S0IN = init->s0PRS; + PRS->CONSUMER_PCNT0_S1IN = init->s1PRS; + + if (init->mode == pcntModeExtSingle || init->mode == pcntModeExtQuad) { + /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing + the clock source to an external clock. */ + pcnt->CMD_SET = PCNT_CMD_CORERST; + /* Change to the external clock. */ + CMU_PCNTClockExternalSet(inst, true); + } else { + /* Change to the internal clock. */ + CMU_PCNTClockExternalSet(inst, false); + } + + /* Start counter(s) */ + if (init->cntEvent != pcntCntEventNone) { + PCNT_StartMainCnt(pcnt); + } + if (init->auxCntEvent != pcntCntEventNone) { + PCNT_StartAuxCnt(pcnt); + } + + PCNT_CounterTopSet(pcnt, init->counter, init->top); + PCNT_TopBufferSet(pcnt, init->top); + + /* Save values of primary and auxiliary counter event. */ + initCntEvent = init->cntEvent; + initAuxCntEvent = init->auxCntEvent; + + if (init->mode == pcntModeDisable) { + /* Disable PCNT. */ + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Reset PCNT to the same state that it was in after a hardware reset. + * + * @details + * Notice the LFACLK must be enabled, since some basic reset is done with + * this clock. The pulse counter clock for the selected instance must also + * be enabled prior to initialization. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + ******************************************************************************/ +void PCNT_Reset(PCNT_TypeDef *pcnt) +{ + unsigned int inst = 0; + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* A map pointer to the instance and clock information. */ + inst = PCNT_Map(pcnt); + pcnt->IEN = _PCNT_IEN_RESETVALUE; + + /* Notice that special SYNCBUSY handling is not applicable for the RSTEN + * bit of the control register, so no need to wait for it when only + * modifying RSTEN. The SYNCBUSY bit will be set, leading to a + * synchronization in the LF domain, with, in reality, no changes to the LF domain. + * Enable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Select LFACLK as default. */ + CMU_PCNTClockExternalSet(inst, false); + + PCNT_TopBufferSet(pcnt, _PCNT_TOPB_RESETVALUE); + + /* Reset CTRL leaving RSTEN set. */ + pcnt->CTRL = _PCNT_CTRL_RESETVALUE | PCNT_CTRL_RSTEN; + + /* Disable reset after CTRL register has been synchronized. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); + + /* Clear pending interrupts. */ + pcnt->IFC = _PCNT_IFC_MASK; + + /* Do not reset route register, setting should be done independently. */ +#else + /* Disable PCNT module. */ + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; + + /* Select LFACLK as default. */ + /* Recommended to switch to internal clock before reset. */ + CMU_PCNTClockExternalSet(inst, false); + + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } + + /* Clear registers. */ + pcnt->SWRST_SET = PCNT_SWRST_SWRST; + + while (pcnt->SWRST & PCNT_SWRST_RESETTING) { + } + +#endif +} + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Set the filter configuration. + * + * @details + * This function will configure the PCNT input filter when the PCNT mode is + * configured to take an LFA-derived clock as an input clock. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] config + * A pointer to the configuration structure to be applied. + * + * @param[in] enable + * Indicates whether to enable or disable filtering. + ******************************************************************************/ +void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) +{ + uint32_t ovscfg = 0; +#if defined(_SILICON_LABS_32B_SERIES_2) + bool module_enable = false; +#endif + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) + /* Construct the new filter setting value. */ + ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT) + | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT); + + /* Set the new configuration. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG); + pcnt->OVSCFG = ovscfg; + + /* Set new state of the filter. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + if (enable) { + pcnt->CTRL |= PCNT_CTRL_FILT; + } else { + pcnt->CTRL &= ~PCNT_CTRL_FILT; + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + /* Disable module before changing CFG register. */ + module_enable = PCNT_IsEnabled(pcnt); + if (module_enable == true) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + /* Construct the new filter setting value. */ + ovscfg = ((config->filtLen & _PCNT_OVSCTRL_FILTLEN_MASK) << _PCNT_OVSCTRL_FILTLEN_SHIFT) + | ((config->flutterrm & 0x1) << _PCNT_OVSCTRL_FLUTTERRM_SHIFT); + + /* Set the new configuration. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCTRL); + pcnt->OVSCTRL = ovscfg; + + /* Set new state of the filter. */ + if (enable) { + pcnt->CFG |= PCNT_CFG_FILTEN; + } else { + pcnt->CFG &= ~PCNT_CFG_FILTEN; + } + + /* Re-Enable module if necessary after change. */ + if (module_enable == true) { + pcnt->EN_SET = PCNT_EN_EN; + } +#endif +} +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) +/***************************************************************************//** + * @brief + * Set Triggered Compare and Clear configuration. + * + * @details + * This function will configure the PCNT TCC (Triggered Compare and Clear) + * module. This module can, upon a configurable trigger source, compare the + * current counter value with the configured TOP value. Upon match, the counter + * will be reset and the TCC PRS output and TCC interrupt flag will be set. + * + * Since there is a comparison with the TOP value, the counter will not stop + * counting nor wrap when hitting the TOP value, but it will keep on counting + * until its maximum value. Then, it will not wrap, but stop counting + * and set the overflow flag. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] config + * A pointer to the configuration structure to be applied. + ******************************************************************************/ +void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config) +{ + uint32_t ctrl = 0; + uint32_t mask = _PCNT_CTRL_TCCMODE_MASK + | _PCNT_CTRL_TCCPRESC_MASK + | _PCNT_CTRL_TCCCOMP_MASK + | _PCNT_CTRL_PRSGATEEN_MASK + | _PCNT_CTRL_TCCPRSPOL_MASK + | _PCNT_CTRL_TCCPRSSEL_MASK; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* Construct the TCC part of the configuration register. */ + ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT) & _PCNT_CTRL_TCCMODE_MASK; + ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT) & _PCNT_CTRL_TCCPRESC_MASK; + ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT) & _PCNT_CTRL_TCCCOMP_MASK; + ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT) & _PCNT_CTRL_TCCPRSSEL_MASK; + ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT) & _PCNT_CTRL_TCCPRSPOL_MASK; + ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT) & _PCNT_CTRL_PRSGATEEN_MASK; + + /* Load new TCC configuration to PCNT. LF register requires a sync check before write. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl; +} +#endif + +/***************************************************************************//** + * @brief + * Set top buffer value. + * + * @note + * This function may stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] val + * A value to set in the top buffer register. + ******************************************************************************/ +void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* LF register about to be modified require sync. busy check */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = val; +} + +/***************************************************************************//** + * @brief + * Set the top value. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] val + * A value to set in the top register. + ******************************************************************************/ +void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > val); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > val); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > val); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* LF register about to be modified requires sync; busy check. */ + + /* Load into TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = val; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LTOPBIM; +#else + /* LF register about to be modified requires sync; busy check. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + /* Load into TOP. */ + pcnt->TOP = val; +#endif +} + +/** @} (end addtogroup pcnt) */ +#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_prs.c b/Libs/platform/emlib/src/em_prs.c new file mode 100644 index 0000000..3b906f8 --- /dev/null +++ b/Libs/platform/emlib/src/em_prs.c @@ -0,0 +1,661 @@ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_prs.h" +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup prs PRS - Peripheral Reflex System + * @brief Peripheral Reflex System (PRS) Peripheral API + * @details + * This module contains functions to control the PRS peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous + * communication between peripherals on the MCU or SoC. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/* Generic defines for async and sync signals applying to all TIMER instances. + * Those defines map to TIMER2 but it could be any TIMER instance number. */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get PRS source signal for a channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] ch + * channel number. + * + * @return + * PRS signal assigned to the channel. + ******************************************************************************/ +static PRS_Signal_t getSignal(unsigned int ch, PRS_ChType_t type) +{ + PRS_Signal_t signal; + +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + if (type == prsTypeAsync) { + signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL + & (_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK)); + } else { + signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL + & (_PRS_SYNC_CH_CTRL_SOURCESEL_MASK | _PRS_SYNC_CH_CTRL_SIGSEL_MASK)); + } +#else + (void) type; + signal = (PRS_Signal_t) (PRS->CH[ch].CTRL + & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK)); +#endif + return signal; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Convert an async PRS source to a sync source. + * + * @details + * This conversion must be done because the id's of the same peripheral + * source is different depending on if it's used as an asynchronous PRS source + * or a synchronous PRS source. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @return + * The id of the corresponding synchronous PRS source. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource) +{ + uint32_t syncSource = 0; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_NONE; + break; +#if defined(IADC_PRESENT) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; + break; +#endif + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; + break; +#if defined(TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4; + break; +#endif +#if defined(TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5; + break; +#endif +#if defined(TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6; + break; +#endif +#if defined(TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7; + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0; + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + return syncSource; +} + +/***************************************************************************//** + * @brief + * Convert an async PRS signal to a sync signal. + * + * @details + * PRS values for some peripherals signals differ between asynchronous and + * synchronous PRS channels. This function must be used to handle the + * conversion. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @param[in] asyncSignal + * The id of the asynchronous PRS signal. + * + * @return + * The id of the corresponding synchronous PRS signal. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) +{ + uint32_t syncSignal = asyncSignal; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: +#endif + /* Async and sync signal values are consistent across all timers instances. + * Generic defines are used. */ + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#if defined(IADC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif + default: + // No translation + break; + } + return syncSignal; +} +#endif + +/***************************************************************************//** + * @brief + * Set a source and signal for a channel. + * + * @param[in] ch + * A channel to define the signal and source for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x + * defines. + * + * @param[in] edge + * An edge (for selected source/signal) to generate the pulse for. + ******************************************************************************/ +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge) +{ +#if defined(_PRS_SYNC_CH_CTRL_MASK) + (void) edge; + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); +#else + EFM_ASSERT(ch < PRS_CHAN_COUNT); + PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_CH_CTRL_SIGSEL_MASK) + | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; +#endif +} + +#if defined(PRS_ASYNC_SUPPORTED) +/***************************************************************************//** + * @brief + * Set the source and asynchronous signal for a channel. + * + * @details + * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in + * EM2/EM3. + * There is a limitation to reflexes operating in asynchronous mode in + * that they can only be used by a subset of the reflex consumers. See + * the PRS chapter in the reference manual for the complete list of + * supported asynchronous signals and consumers. + * + * @note + * This function is not supported on EFM32GxxxFyyy parts. + * In asynchronous mode, the edge detector only works in EM0 and should + * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) + * by default. + * + * @param[in] ch + * A channel to define the source and asynchronous signal for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * An asynchronous signal (for selected @p source) to use. Use one of the + * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. + ******************************************************************************/ +SL_WEAK void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal) +{ + PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); +} +#endif + +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] location + * PRS routing location. + ******************************************************************************/ +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location) +{ + EFM_ASSERT(ch < PRS_CHAN_COUNT); + +#if defined(_PRS_ROUTE_MASK) + PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) + | (1 << ch); +#else + uint32_t shift = (ch % 4) * 8; + uint32_t mask = location << shift; + uint32_t locationGroup = ch / 4; + /* Since all ROUTELOCx registers are in consecutive memory locations, treat them + * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ + volatile uint32_t * routeloc = &PRS->ROUTELOC0; + routeloc[locationGroup] |= mask; + PRS->ROUTEPEN |= 1 << ch; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Search for the first free PRS channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * Channel number >= 0 if an unused PRS channel was found. If no free PRS + * channel was found then -1 is returned. + ******************************************************************************/ +SL_WEAK int PRS_GetFreeChannel(PRS_ChType_t type) +{ + int ch = -1; + PRS_Signal_t signal; + int max; + + if (type == prsTypeAsync) { + max = PRS_ASYNC_CHAN_COUNT; + } else { + max = PRS_SYNC_CHAN_COUNT; + } + + for (int i = 0; i < max; i++) { + signal = getSignal(i, type); + if (signal == prsSignalNone) { + ch = i; + break; + } + } + return ch; +} + +/***************************************************************************//** + * @brief + * Reset all PRS channels + * + * @details + * This function will reset all the PRS channel configuration. + ******************************************************************************/ +void PRS_Reset(void) +{ + unsigned int i; + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS->ASYNC_SWLEVEL = 0; + for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { + PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; + } + for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { + PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; + } +#else + PRS->SWLEVEL = 0x0; + for (i = 0; i < PRS_CHAN_COUNT; i++) { + PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; + } +#endif +} + +/***************************************************************************//** + * @brief + * Connect a PRS signal to a channel. + * + * @details + * This function will make the PRS signal available on the specific channel. + * Only a single PRS signal can be connected to any given channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] signal + * This is the PRS signal that should be placed on the channel. + ******************************************************************************/ +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) +{ +#if defined(_PRS_ASYNC_CH_CTRL_MASK) + // Series 2 devices + uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; + uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + if (type == prsTypeAsync) { + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A + | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + signalField = PRS_ConvertToSyncSignal(sourceField, signalField); + sourceField = PRS_ConvertToSyncSource(sourceField); + PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); + } +#else + // Series 0 and Series 1 devices + uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK + | _PRS_CH_CTRL_SIGSEL_MASK); + if (type == prsTypeAsync) { +#if defined(PRS_ASYNC_SUPPORTED) + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | PRS_CH_CTRL_ASYNC + | signalField; +#endif + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | signalField; + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Connect a peripheral consumer to a PRS channel. + * + * @details + * Different peripherals can use PRS channels as their input. This function + * can be used to connect a peripheral consumer to a PRS channel. Multiple + * consumers can be connected to a single PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] consumer + * This is the PRS consumer. + ******************************************************************************/ +SL_WEAK void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) +{ + EFM_ASSERT((uint32_t)consumer <= 0xFFF); + volatile uint32_t * addr = (volatile uint32_t *) PRS; + uint32_t offset = (uint32_t) consumer; + addr = addr + offset / 4; + + if (consumer != prsConsumerNone) { + if (type == prsTypeAsync) { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} + +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. Some devices for instance can only route + * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 + * can only be routed to GPIO pins PCx and PDx + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO pin + ******************************************************************************/ +SL_WEAK void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) +{ + volatile uint32_t * addr; + if (type == prsTypeAsync) { + addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; + } else { + addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; + } + addr += ch; + *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) + | ((uint32_t)pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); + + if (type == prsTypeAsync) { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); + } else { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); + } +} + +/***************************************************************************//** + * @brief + * Combine two PRS channels using a logic function. + * + * @details + * This function allows you to combine the output of one PRS channel with the + * the signal of another PRS channel using various logic functions. Note that + * for series 2, config 1 devices, the hardware only allows a PRS channel to + * be combined with the previous channel. So for instance channel 5 can be + * combined only with channel 4. + * + * The logic function operates on two PRS channels called A and B. The output + * of PRS channel B is combined with the PRS source configured for channel A + * to produce an output. This output is used as the output of channel A. + * + * @param[in] chA + * PRS Channel for the A input. + * + * @param[in] chB + * PRS Channel for the B input. + * + * @param[in] logic + * The logic function to use when combining the Channel A and Channel B. The + * output of the logic function is the output of Channel A. Function like + * AND, OR, XOR, NOT and more are available. + ******************************************************************************/ +SL_WEAK void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) +{ + EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); + EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); + +#else + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL + & ~(_PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_AUXSEL_MASK)) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT) + | ((uint32_t)chB << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT); +#endif +} +#endif + +/** @} (end addtogroup prs) */ +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_rmu.c b/Libs/platform/emlib/src/em_rmu.c new file mode 100644 index 0000000..f1bbfe6 --- /dev/null +++ b/Libs/platform/emlib/src/em_rmu.c @@ -0,0 +1,402 @@ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_rmu.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) + +#include "sl_common.h" +#include "em_emu.h" +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup rmu RMU - Reset Management Unit + * @brief Reset Management Unit (RMU) Peripheral API + * @details + * This module contains functions to control the RMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is + * responsible for connecting the different reset sources to the reset lines of + * the MCU or SoC. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ***************************** DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_RMU_RSTCAUSE_MASK) + +/** Reset cause XMASKS for series-0 and series-1 devices. + Reset cause zero and "don't care" bit definitions (XMASKs). + An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK + is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask + in @ref RMU_ResetCauseMasks_Typedef. */ + +/* EFM32G */ +#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ +#define NUM_RSTCAUSES 7 + +/* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ +#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ +#define NUM_RSTCAUSES 11 + +/* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ +#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ +#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ +#define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ +#define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ +#define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ +#define NUM_RSTCAUSES 16 + +/* EFM32xG1, EFM32xG12, EFM32xG13 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 9 + +/* EFM32GG11 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 10 + +#else +#error "RMU_RSTCAUSE XMASKs are not defined for this family." +#endif + +/* Pin reset definitions. */ +#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) +#define LB_CLW0_PINRESETSOFT (1 << 2) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#define ERRATA_FIX_EMU_E208_EN +#endif + +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask type for series-0 and series-1 devices. */ +typedef struct { + /** Reset cause 1 bits. */ + uint32_t resetCauseMask; + /** Reset cause 0 and "don't care" bits. */ + uint32_t resetCauseZeroXMask; +} RMU_ResetCauseMasks_Typedef; +#endif + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask table. */ +static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = +{ + { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, +#if defined(RMU_RSTCAUSE_BODUNREGRST) + { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODREGRST) + { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_AVDDBOD) + { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DVDDBOD) + { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DECBOD) + { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif + { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, + { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, + { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, + { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, +#if defined(RMU_RSTCAUSE_EM4RST) + { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_EM4WURST) + { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD0) + { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD1) + { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) + { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, + { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, + { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, + { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#elif defined(RMU_RSTCAUSE_BUMODERST) + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#endif +}; +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************** TEST ******************************** + ******************************************************************************/ +#if defined(EMLIB_REGRESSION_TEST) +/* A test variable that replaces the RSTCAUSE cause register when testing + the RMU_ResetCauseGet function. */ +extern uint32_t rstCause; +#else +static uint32_t rstCause = UINT32_MAX; +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable/enable reset for various peripherals and signal sources. + * + * @param[in] reset Reset types to enable/disable.s + * + * @param[in] mode Reset mode. + ******************************************************************************/ +#if defined(__GNUC__) && __GNUC__ >= 11 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wanalyzer-shift-count-overflow" +#endif +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) +{ + /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ +#if defined(_RMU_CTRL_PINRMODE_MASK) + uint32_t val; +#endif + uint32_t shift; + + shift = SL_CTZ((uint32_t)reset); +#if defined(_EMU_RSTCTRL_MASK) + BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); +#elif defined(_RMU_CTRL_PINRMODE_MASK) + EFM_ASSERT(shift < 32); + val = (uint32_t)mode << shift; + RMU->CTRL = (RMU->CTRL & ~reset) | val; +#else + BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); +#endif +} +#if defined(__GNUC__) && __GNUC__ >= 11 +#pragma GCC diagnostic pop +#endif + +/***************************************************************************//** + * @brief + * Clear the reset cause register. + * + * @details + * This function clears all the reset cause bits of the RSTCAUSE register. + * The reset cause bits must be cleared by software before a new reset occurs. + * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). + ******************************************************************************/ +void RMU_ResetCauseClear(void) +{ +#if defined(_EMU_RSTCTRL_MASK) + EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; +#else + RMU->CMD = RMU_CMD_RCCLR; +#endif + +#if defined(EMU_AUXCTRL_HRCCLR) + { + uint32_t locked; + + /* Clear reset causes not cleared with the RMU CMD register. */ + /* (If EMU registers are locked, they must be unlocked first) */ + locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; + if (locked) { + EMU_Unlock(); + } + + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); + + if (locked) { + EMU_Lock(); + } + } +#endif +} + +/***************************************************************************//** + * @brief + * Get the cause of the last reset. + * + * @details + * To be useful, the reset cause must be cleared by software before a new + * reset occurs. Otherwise, reset causes may accumulate. See @ref + * RMU_ResetCauseClear(). This function call will return the main cause for + * reset, which can be a bit mask (several causes) and clear away "noise". + * + * @return + * A reset cause mask. See the reference manual for a description + * of the reset cause mask. + ******************************************************************************/ +uint32_t RMU_ResetCauseGet(void) +{ +#if !defined(EMLIB_REGRESSION_TEST) + if (rstCause != UINT32_MAX) { + // RMU_ResetCauseGet() has already been called since boot. Return what was already obtained. + return rstCause; + } +#endif + +#if defined(_EMU_RSTCAUSE_MASK) +#if !defined(EMLIB_REGRESSION_TEST) + rstCause = EMU->RSTCAUSE; +#endif + return rstCause; +#endif + +#if defined(_RMU_RSTCAUSE_MASK) +#if !defined(EMLIB_REGRESSION_TEST) + rstCause = RMU->RSTCAUSE; +#endif + uint32_t validRstCause = 0; + uint32_t zeroXMask; + uint32_t i; + + for (i = 0; i < NUM_RSTCAUSES; i++) { + zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Handle soft/hard pin reset. */ + if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { + /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ + switch (resetCauseMasks[i].resetCauseMask) { + case RMU_RSTCAUSE_LOCKUPRST: + /* Fallthrough */ + case RMU_RSTCAUSE_SYSREQRST: + /* Fallthrough */ + case RMU_RSTCAUSE_WDOGRST: + /* Fallthrough */ + case RMU_RSTCAUSE_EM4RST: + zeroXMask |= RMU_RSTCAUSE_EXTRST; + break; + default: + /* MISRA requires a default case. */ + break; + } + } +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Ignore BOD flags impacted by EMU_E208. */ + if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { + zeroXMask &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif + + /* Check reset cause requirements. Note that a bit is "don't care" if 0 in + both resetCauseMask and resetCauseZeroXMask. */ + if ((rstCause & resetCauseMasks[i].resetCauseMask) + && !(rstCause & zeroXMask)) { + /* Add this reset-cause to the mask of qualified reset-causes. */ + validRstCause |= resetCauseMasks[i].resetCauseMask; + } + } +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Clear BOD flags impacted by EMU_E208. */ + if (validRstCause & RMU_RSTCAUSE_EM4RST) { + validRstCause &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif +#if !defined(EMLIB_REGRESSION_TEST) + // keep validRstCause in the static local variable for future calls + rstCause = validRstCause +#endif + return validRstCause; +#endif +} + +/** @} (end addtogroup rmu) */ +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_system.c b/Libs/platform/emlib/src/em_system.c new file mode 100644 index 0000000..dbeac7d --- /dev/null +++ b/Libs/platform/emlib/src/em_system.c @@ -0,0 +1,433 @@ +/***************************************************************************//** + * @file + * @brief System Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_system.h" +#include "sl_assert.h" +#include +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Bit mask used to extract the part number value without the new naming + * bitfield. */ +#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 +#define SYSCFG_CHIPREV_PARTNUMBER0 0xF + +/* Bit mask to convert NON-SECURE to SECURE */ +#define CONVERT_NS_TO_S (~(1 << 28U)) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get a chip major/minor revision. + * + * @param[out] rev + * A location to place the chip revision information. + ******************************************************************************/ +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) +{ +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ + uint32_t chiprev = SYSCFG_readChipRev(); +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + rev->partNumber = ((chiprev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chiprev & SYSCFG_CHIPREV_PARTNUMBER0); +#else + rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; +#endif + rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; + rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; +#else + uint8_t tmp; + + EFM_ASSERT(rev); + + /* CHIP FAMILY bit [5:2] */ + tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) + >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + /* CHIP FAMILY bit [1:0] */ + tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) + >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + rev->family = tmp; + + /* CHIP MAJOR bit [3:0] */ + rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT); + + /* CHIP MINOR bit [7:4] */ + tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + rev->minor = tmp; +#endif +} + +/***************************************************************************//** + * @brief + * Get a factory calibration value for a given peripheral register. + * + * @param[in] regAddress + * The peripheral calibration register address to get a calibration value for. If + * the calibration value is found, this register is updated with the + * calibration value. + * + * @return + * True if a calibration value exists, false otherwise. + ******************************************************************************/ +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) +{ + SYSTEM_CalAddrVal_TypeDef * p, * end; + + uint32_t s_regAddress = (uint32_t)regAddress; + s_regAddress = s_regAddress & CONVERT_NS_TO_S; + +#if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) + p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; + end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; +#else + p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); + end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; +#endif + + for (; p < end; p++) { + if (p->address == 0) { + /* p->address == 0 marks the end of the table */ + return false; + } + if (p->address == s_regAddress) { + *regAddress = p->calValue; + return true; + } + } + /* Nothing found for regAddress. */ + return false; +} + +/***************************************************************************//** + * @brief + * Get family security capability. + * + * @note + * This function retrieves the family security capability based on the + * device number. The device number is one letter and 3 digits: + * DEVICENUMBER = (alpha-'A')*1000 + numeric. i.e. 0d = "A000"; 1123d = "B123". + * The security capabilities are represented by ::SYSTEM_SecurityCapability_TypeDef. + * + * @return + * Security capability of MCU. + ******************************************************************************/ +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void) +{ + SYSTEM_SecurityCapability_TypeDef sc; + +#if (_SILICON_LABS_32B_SERIES == 0) + sc = securityCapabilityNA; +#elif (_SILICON_LABS_32B_SERIES == 1) + sc = securityCapabilityBasic; +#else + sc = securityCapabilityUnknown; +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + uint16_t mcuFeatureSetMajor; + uint16_t deviceNumber; + deviceNumber = SYSTEM_GetPartNumber(); + mcuFeatureSetMajor = 'A' + (deviceNumber / 1000); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" + mcuFeatureSetMajor = 'C'; +#endif + + switch (mcuFeatureSetMajor) { + case 'A': + sc = securityCapabilitySE; + break; + + case 'B': + sc = securityCapabilityVault; + break; + + case 'C': + sc = securityCapabilityRoT; + break; + + default: + sc = securityCapabilityUnknown; + break; + } +#endif + + return sc; +} + +/***************************************************************************//** + * @brief + * Get the unique number for this device. + * + * @return + * Unique number for this device. + ******************************************************************************/ +uint64_t SYSTEM_GetUnique(void) +{ +#if defined (_DEVINFO_EUI64H_MASK) + uint32_t tmp = DEVINFO->EUI64L; + return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; +#elif defined(_DEVINFO_UNIQUEH_MASK) + uint32_t tmp = DEVINFO->UNIQUEL; + return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; +#else +#error (em_system.c): Location of device unique number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the production revision for this part. + * + * @return + * Production revision for this part. + ******************************************************************************/ +uint8_t SYSTEM_GetProdRev(void) +{ +#if defined (_DEVINFO_PART_PROD_REV_MASK) + return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) + >> _DEVINFO_PART_PROD_REV_SHIFT); +#elif defined (_DEVINFO_INFO_PRODREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) + >> _DEVINFO_INFO_PRODREV_SHIFT); +#else +#error (em_system.c): Location of production revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the SRAM Base Address. + * + * @note + * This function is used to retrieve the base address of the SRAM. + * + * @return + * Base address SRAM (32-bit unsigned integer). + ******************************************************************************/ +uint32_t SYSTEM_GetSRAMBaseAddress(void) +{ + return (uint32_t)SRAM_BASE; +} + +/***************************************************************************//** + * @brief + * Get the SRAM size (in KB). + * + * @note + * This function retrieves SRAM size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use SRAM_SIZE instead. + * + * @return + * Size of internal SRAM (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetSRAMSize(void) +{ + uint16_t sizekb; + +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; + } +#endif + sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH. */ + sizekb--; +#endif + + return sizekb; +} + +/***************************************************************************//** + * @brief + * Get the flash size (in KB). + * + * @note + * This function retrieves flash size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_SIZE instead. + * + * @return + * Size of internal flash (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetFlashSize(void) +{ +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + } +#endif + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the flash page size in bytes. + * + * @note + * This function retrieves flash page size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_PAGE_SIZE instead. + * + * @return + * Page size of internal flash in bytes. + ******************************************************************************/ +uint32_t SYSTEM_GetFlashPageSize(void) +{ + uint32_t tmp; + +#if defined(_SILICON_LABS_32B_SERIES_0) + +#if defined(_EFM32_GIANT_FAMILY) + if (SYSTEM_GetProdRev() < 18) { + /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ + return FLASH_PAGE_SIZE; + } +#elif defined(_EFM32_ZERO_FAMILY) + if (SYSTEM_GetProdRev() < 24) { + /* Early Zero devices have an incorrect DEVINFO flash page size */ + return FLASH_PAGE_SIZE; + } +#endif +#endif + +#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; +#elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; +#else +#error (em_system.c): Location of flash page size is not defined. +#endif + + return 1UL << ((tmp + 10UL) & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Get the MCU part number. + * + * @return + * The part number of MCU. + ******************************************************************************/ +uint16_t SYSTEM_GetPartNumber(void) +{ +#if defined(_DEVINFO_PART_DEVICENUM_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) + >> _DEVINFO_PART_DEVICENUM_SHIFT); +#elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) + >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); +#else +#error (em_system.c): Location of device part number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the calibration temperature (in degrees Celsius). + * + * @return + * Calibration temperature in Celsius. + ******************************************************************************/ +uint8_t SYSTEM_GetCalibrationTemperature(void) +{ +#if defined(_DEVINFO_CAL_TEMP_MASK) + return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) + >> _DEVINFO_CAL_TEMP_SHIFT); +#elif defined(_DEVINFO_CALTEMP_TEMP_MASK) + return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) + >> _DEVINFO_CALTEMP_TEMP_SHIFT); +#else +#error (em_system.c): Location of calibration temperature is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the MCU family identifier. + * + * @note + * This function retrieves family ID by reading the chip's device info + * structure in flash memory. Users can retrieve family ID directly + * by reading DEVINFO->PART item and decode with mask and shift + * \#defines defined in \_devinfo.h (refer to code + * below for details). + * + * @return + * Family identifier of MCU. + ******************************************************************************/ +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) +{ +#if defined(_DEVINFO_PART_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK + | _DEVINFO_PART_FAMILYNUM_MASK)))); +#elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) + >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); +#else + #error (em_system.h): Location of device family name is not defined. +#endif +} + +/** @} (end addtogroup system) */ diff --git a/Libs/platform/emlib/src/em_timer.c b/Libs/platform/emlib/src/em_timer.c new file mode 100644 index 0000000..c542a8b --- /dev/null +++ b/Libs/platform/emlib/src/em_timer.c @@ -0,0 +1,520 @@ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_timer.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup timer TIMER - Timer/Counter + * @brief Timer/Counter (TIMER) Peripheral API + * @details + * The timer module consists of three main parts: + * @li General timer configuration and enable control. + * @li Compare/capture control. + * @li Dead time insertion control (may not be available for all timers). + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) + +/** Map TIMER reference to index of device. */ +#if defined(TIMER9) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : (timer) == TIMER8 ? 8 \ + : (timer) == TIMER9 ? 9 \ + : -1) +#elif defined(TIMER7) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : -1) +#elif defined(TIMER4) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : -1) +#else +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : -1) +#endif + +#define TIMER_INPUT_CHANNEL_DTI 3UL +#define TIMER_INPUT_CHANNEL_DTIFS1 4UL +#define TIMER_INPUT_CHANNEL_DTIFS2 5UL + +/** + * TIMER PRS registers are moved into the PRS register space on series 2 devices. + * The PRS Consumer registers for a timer consist of 6 registers. + * + * [0] - CC0 PRS Consumer + * [1] - CC1 PRS Consumer + * [2] - CC2 PRS Consumer + * [3] - DTI PRS Consumer + * [4] - DTIFS1 PRS Consumer + * [5] - DTIFS2 PRS Consumer + */ +typedef struct { + __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ +} PRS_TIMERn_Consumer_TypeDef; + +typedef struct { + PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; +} PRS_TIMERn_TypeDef; + +/** + * @brief Configure a timer capture/compare channel to use a PRS channel as input. + * + * @param[in] timer + * + * @param[in] cc + * Timer input channel. Valid input is 0-5. + * 0 - CC0 + * 1 - CC1 + * 2 - CC2 + * 3 - DTI + * 4 - DTIFS1 + * 5 - DTIFS2 + * + * @param[in] prsCh + * PRS channel number. + * + * @param[in] async + * true for asynchronous PRS channel, false for synchronous PRS channel. + */ +static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) +{ + int i = TIMER_DEVICE_ID(timer); + volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; + EFM_ASSERT(i >= 0); + + if (i >= 0) { + if (async) { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize TIMER. + * + * @details + * Notice that the counter top must be configured separately with, for instance + * TIMER_TopSet(). In addition, compare/capture and dead-time insertion + * initialization must be initialized separately if used, which should probably + * be done prior to using this function if configuring the TIMER to + * start when initialization is completed. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + uint32_t ctrlRegVal = 0; + +#if defined (_TIMER_CFG_PRESC_SHIFT) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) + | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) + | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) + | (init->oneShot ? TIMER_CFG_OSMEN : 0) + | (init->sync ? TIMER_CFG_SYNC : 0) + | (init->disSyncOut ? TIMER_CFG_DISSYNCOUT : 0) + | (init->ati ? TIMER_CFG_ATI : 0) + | (init->rssCoist ? TIMER_CFG_RSSCOIST : 0); + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ + if (!(init->enable)) { + timer->CMD = TIMER_CMD_STOP; + } + + /* Reset the counter. */ + timer->CNT = _TIMER_CNT_RESETVALUE; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) + | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) + | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) + | (init->oneShot ? TIMER_CTRL_OSMEN : 0) +#if defined(TIMER_CTRL_DISSYNCOUT) + | (init->disSyncOut ? TIMER_CTRL_DISSYNCOUT : 0) +#endif + | (init->sync ? TIMER_CTRL_SYNC : 0); + +#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) && defined(TIMER_CTRL_RSSCOIST) + ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) + | (init->ati ? TIMER_CTRL_ATI : 0) + | (init->rssCoist ? TIMER_CTRL_RSSCOIST : 0); +#endif + +#else + ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | (init->count2x ? TIMER_CTRL_X2CNT : 0); +#endif + + timer->CTRL = ctrlRegVal; + + /* Start the timer if specified to be enabled (doesn't hurt if already started). */ + if (init->enable) { + timer->CMD = TIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Initialize the TIMER compare/capture channel. + * + * @details + * Notice that if operating the channel in compare mode, the CCV and CCVB register + * must be set separately, as required. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] ch + * A compare/capture channel to initialize for. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + EFM_ASSERT(TIMER_REF_CH_VALIDATE(timer, ch)); + +#if defined (_TIMER_CC_CFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CC[ch].CFG = + ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) + | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) + | (init->coist ? TIMER_CC_CFG_COIST : 0) + | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); + + if (init->prsInput) { + timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; + bool async = (init->prsInputType != timerPrsInputSync); + timerPrsConfig(timer, ch, init->prsSel, async); + } else { + timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; + } + timer->EN_SET = TIMER_EN_EN; + + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); +#else + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) + | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) + | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) + | (init->coist ? TIMER_CC_CTRL_COIST : 0) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) +#if defined(_TIMER_CC_CTRL_PRSCONF_MASK) + | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) +#endif + ; +#endif +} + +#if defined(_TIMER_DTCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize the TIMER DTI unit. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER DTI initialization structure. + ******************************************************************************/ +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + /* Make sure the DTI unit is disabled while initializing. */ + TIMER_EnableDTI(timer, false); + +#if defined (_TIMER_DTCFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) + | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); + if (init->enablePrsSource) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); + } + + timer->DTTIMECFG = + ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); + + timer->DTFCFG = + (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) + | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); + + if (init->enableFaultSourcePrsSel0) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); + } + if (init->enableFaultSourcePrsSel1) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); + } + + timer->EN_SET = TIMER_EN_EN; +#endif + +#if defined(TIMER_DTCTRL_DTDAS) + /* Set up the DTCTRL register. + The enable bit will be set at the end of the function if specified. */ + timer->DTCTRL = + (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) + | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) + | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) + | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); +#endif + +#if defined (TIMER_DTCFG_DTDAS) + timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); +#endif + +#if defined (_TIMER_DTTIME_DTPRESC_SHIFT) + /* Set up the DTTIME register. */ + timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); +#endif + +#if defined (TIMER_DTFC_DTLOCKUPFEN) + /* Set up the DTFC register. */ + timer->DTFC = + (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) + | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) + | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) + | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); +#endif + + /* Set up the DTOGEN register. */ + timer->DTOGEN = init->outputsEnableMask; + + /* Clear any previous DTI faults. */ + TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); + + /* Enable/disable before returning. */ + TIMER_EnableDTI(timer, init->enable); +} +#endif + +/***************************************************************************//** + * @brief + * Reset the TIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + ******************************************************************************/ +void TIMER_Reset(TIMER_TypeDef *timer) +{ + int i; + + EFM_ASSERT(TIMER_REF_VALID(timer)); + +#if defined(TIMER_EN_EN) + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Make sure disabled first, before resetting other registers. */ + timer->CMD = TIMER_CMD_STOP; + + timer->CTRL = _TIMER_CTRL_RESETVALUE; + timer->IEN = _TIMER_IEN_RESETVALUE; +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = _TIMER_IF_MASK; +#else + timer->IFC = _TIMER_IFC_MASK; +#endif + timer->TOPB = _TIMER_TOPB_RESETVALUE; + /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ + timer->TOP = _TIMER_TOP_RESETVALUE; + timer->CNT = _TIMER_CNT_RESETVALUE; + /* Do not reset the route register, setting should be done independently. */ + /* Note: The ROUTE register may be locked by the DTLOCK register. */ + + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; +#if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) + timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; + timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; +#endif +#if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ + && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) + timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; + timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; +#endif + } + + /* Reset dead time insertion module, which has no effect on timers without DTI. */ +#if defined(_TIMER_DTCFG_MASK) + timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) + /* Unlock DTI registers first if locked. */ + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTTIME = _TIMER_DTTIME_RESETVALUE; + timer->DTFC = _TIMER_DTFC_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#endif + +#if defined(_TIMER_CFG_MASK) + TIMER_SyncWait(timer); + /* CFG registers must be reset after the timer is disabled */ + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = _TIMER_CFG_RESETVALUE; + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; + } + timer->DTCFG = _TIMER_DTCFG_RESETVALUE; + timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; + timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; +#endif +} + +#if defined(TIMER_STATUS_SYNCBUSY) +/** + * @brief Wait for pending synchronization to finish + * + * @param[in] timer + */ +void TIMER_SyncWait(TIMER_TypeDef * timer) +{ + while (((timer->EN & TIMER_EN_EN) != 0U) + && ((timer->STATUS & TIMER_STATUS_SYNCBUSY) != 0U)) { + /* Wait for synchronization to complete */ + } +} +#endif + +/** @} (end addtogroup timer) */ +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_usart.c b/Libs/platform/emlib/src/em_usart.c new file mode 100644 index 0000000..0b8cef0 --- /dev/null +++ b/Libs/platform/emlib/src/em_usart.c @@ -0,0 +1,1444 @@ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_usart.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" +#if defined(USART_CTRLX_CTSEN) +#include "em_gpio.h" +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of USART register block pointer reference for assert statements. */ +#if (USART_COUNT == 1) && defined(USART0) +#define USART_REF_VALID(ref) ((ref) == USART0) + +#elif (USART_COUNT == 1) && defined(USART1) +#define USART_REF_VALID(ref) ((ref) == USART1) + +#elif (USART_COUNT == 2) && defined(USART2) +#define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + +#elif (USART_COUNT == 2) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + +#elif (USART_COUNT == 3) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2)) +#elif (USART_COUNT == 4) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3)) +#elif (USART_COUNT == 5) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4)) +#elif (USART_COUNT == 6) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4) || ((ref) == USART5)) +#else +#error "Undefined number of USARTs." +#endif + +#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) + #if (USARTRF_COUNT == 1) && defined(USARTRF0) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) + #elif (USARTRF_COUNT == 1) && defined(USARTRF1) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) + #else + #define USARTRF_REF_VALID(ref) (0) + #endif +#else + #define USARTRF_REF_VALID(ref) (0) +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +// If GG11 or TG11 + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) + #elif defined(USART3) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) + #elif defined(USART2) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) + #else + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(USART0) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif (USART_COUNT == 1) && defined(USART1) + #define USART_IRDA_VALID(ref) ((ref) == USART1) + #elif defined(USARTRF0) + #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) + #else + #define USART_IRDA_VALID(ref) (0) + #endif +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_I2S_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(USART4) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) + #elif defined(USART3) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) + #else + #define USART_I2S_VALID(ref) ((ref) == USART1) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + #endif +#endif + +#if defined(UART_COUNT) && (UART_COUNT == 1) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) ((ref) == UART0) +#elif defined(UART_COUNT) && (UART_COUNT == 2) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) +#else + #define UART_REF_VALID(ref) (0) +#endif + +#if defined(_USART_CLKDIV_DIVEXT_MASK) + #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) +#else + #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Rx input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_INPUT_MASK) + usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) + | USART_INPUT_RXPRS; +#elif defined(USART_CTRLX_RXPRSEN) + if (usart == USART0) { + PRS->CONSUMER_USART0_RX = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_RX = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_RX = ch; + } +#endif + usart->CTRLX |= USART_CTRLX_RXPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_SHIFT) + usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) + | USART_IRCTRL_IRPRSEN; +#else + (void)ch; + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) && defined(CONSUMER_USART0_IR) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ + if (usart == USART0) { + PRS->CONSUMER_USART0_IR = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_IR = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_IR = ch; + } +#endif + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +} +#endif + +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Trigger input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_MASK) + usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) + | (ch << _USART_TRIGCTRL_TSEL_SHIFT); +#else + if (usart == USART0) { + PRS->CONSUMER_USART0_TRIGGER = ch; + } +#if (USART_COUNT > 1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_TRIGGER = ch; + } +#endif +#if (USART_COUNT > 2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_TRIGGER = ch; + } +#endif +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup usart + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Configure USART/UART operating in asynchronous mode to use a given + * baudrate (or as close as possible to a specified baudrate). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] refFreq + * USART/UART reference clock frequency in Hz. If set to 0, + * the currently configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART/UART. + * + * @param[in] ovs + * Oversampling to be used. Normal is 16x oversampling but lower oversampling + * may be used to achieve higher rates or better baudrate accuracy in some + * cases. Notice that lower oversampling frequency makes the channel more + * vulnerable to bit faults during reception due to clock inaccuracies + * compared to the link partner. + ******************************************************************************/ +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs) +{ + uint32_t clkdiv; + uint32_t oversample = 0; + + /* Inhibit divide by 0 */ + EFM_ASSERT(baudrate); + + /* + * Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * CLKDIV in asynchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) + * or + * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fHFPERCLK) may become higher than max 32 bit + * integer. Yet, we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. + * Too harsh restrictions on maximum fHFPERCLK value should not be made. + * + * It is possible to factorize 256 and oversample/br. However, + * since the last 6 or 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula + * + * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) + * or + * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) + * + * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK + * up to 1 GHz without overflowing a 32 bit value. + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* Map oversampling. */ + switch (ovs) { + case usartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case usartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case usartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case usartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + default: + /* Invalid input */ + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + /* Calculate and set CLKDIV with fractional bits. + * The added (oversample*baudrate)/2 in the first line is to round the + * divisor to the nearest fractional divisor. */ + #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) + /* Devices with 2 fractional bits. CLKDIV[7:6] */ + clkdiv = 4 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 4; + clkdiv *= 64; + #else + /* Devices with 5 fractional bits. CLKDIV[7:3] */ + clkdiv = 32 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 32; + clkdiv *= 8; + #endif + + /* Verify that the resulting clock divider is within limits. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Make sure that reserved bits are not written to. */ + clkdiv &= CLKDIV_MASK; + + usart->CTRL &= ~_USART_CTRL_OVS_MASK; + usart->CTRL |= ovs; + usart->CLKDIV = clkdiv; + } +} + +/***************************************************************************//** + * @brief + * Calculate baudrate for USART/UART given reference frequency, clock division, + * and oversampling rate (if async mode). + * + * @details + * This function returns the baudrate that a USART/UART module will use if + * configured with the given frequency, clock divisor, and mode. Notice that + * this function will not use the hardware configuration. It can be used + * to determine if a given configuration is sufficiently accurate for the + * application. + * + * @param[in] refFreq + * USART/UART HF peripheral frequency used. + * + * @param[in] clkdiv + * A clock division factor to be used. + * + * @param[in] syncmode + * @li True - synchronous mode operation. + * @li False - asynchronous mode operation. + * + * @param[in] ovs + * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. + * + * @return + * Baudrate with given settings. + ******************************************************************************/ +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + /* Out of bound clkdiv. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Mask out unused bits */ + clkdiv &= CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division */ + /* utils and yet keep rounding effect errors to a minimum. */ + + /* Baudrate calculation depends on if synchronous or asynchronous mode. */ + if (syncmode) { + /* + * Baudrate is given by: + * + * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (128 * fHFPERCLK)/(256 + CLKDIV) + */ + oversample = 1; /* Not used in sync mode, i.e., 1 */ + factor = 128; + } else { + /* + * Baudrate in asynchronous mode is given by: + * + * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case usartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case usartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case usartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + default: + oversample = 1; + factor = 256 / 4; + break; + } + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fHFPERCLK) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fHFPERCLK value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ + /* 32 bit value. However, factor * remainder can become larger than 32-bit */ + /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ + br = (uint32_t)(factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. + */ + br += (uint32_t)((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * @brief + * Get the current baudrate for USART/UART. + * + * @details + * This function returns the actual baudrate (not considering oscillator + * inaccuracies) used by a USART/UART peripheral. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * The current baudrate. + ******************************************************************************/ +uint32_t USART_BaudrateGet(USART_TypeDef *usart) +{ + uint32_t freq; + USART_OVS_TypeDef ovs; + bool syncmode; + + if (usart->CTRL & USART_CTRL_SYNC) { + syncmode = true; + } else { + syncmode = false; + } + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + freq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + freq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + freq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + freq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); + return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); +} + +/***************************************************************************//** + * @brief + * Configure the USART operating in synchronous mode to use a given baudrate + * (or as close as possible to a specified baudrate). + * + * @details + * The configuration will be set to use a baudrate <= the specified baudrate + * to ensure that the baudrate does not exceed the specified value. + * + * The fractional clock division is suppressed, although the hardware design allows it. + * It could cause half clock cycles to exceed a specified limit and thus + * potentially violate specifications for the slave device. In some special + * situations, a fractional clock division may be useful even in synchronous + * mode, but in those cases it must be directly adjusted, possibly assisted + * by USART_BaudrateCalc(): + * + * @warning + * The consequence of the aforementioned suppression of the fractional part of + * the clock divider is that some frequencies won't be achievable. The divider + * will only be able to be an integer value so the reference clock will only be + * dividable by N (where N is a positive integer). + * + * @param[in] usart + * A pointer to the USART peripheral register block. (Cannot be used on UART + * modules.) + * + * @param[in] refFreq + * A USART reference clock frequency in Hz that will be used. If set to 0, + * the currently-configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART. + ******************************************************************************/ +void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) +{ + uint32_t clkdiv; + + /* Prevent dividing by 0. */ + EFM_ASSERT(baudrate); + + /* + * CLKDIV in synchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* + * The clock divider computation is done by using unsigned integer. + * The goal is to truncate the fractional part of the resulting + * clock divider value. + * Note: The divider field of the USART->CLKDIV register is of the following form: + * xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider + * and y is the 5 bits fractional part. + */ + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; + + /* Verify that resulting clock divider is within limits. */ + EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); + + usart->CLKDIV = clkdiv; +} + +/***************************************************************************//** + * @brief + * Enable/disable USART/UART receiver and/or transmitter. + * + * @details + * Notice that this function does not do any configuration. Enabling should + * normally be done after initialization (if not enabled as part + * of initialization). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] enable + * Select the status for the receiver/transmitter. + ******************************************************************************/ +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) +{ + uint32_t tmp; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Disable as specified. */ + tmp = ~((uint32_t)enable); + tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; + usart->CMD = tmp << 1; + + /* Enable as specified. */ + usart->CMD = (uint32_t)enable; + +#if defined(USART_EN_EN) + if (enable == usartDisable) { + usart->EN_CLR = USART_EN_EN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Initialize USART/UART for normal asynchronous mode. + * + * @details + * This function will configure basic settings to operate in normal + * asynchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic async setup. + ******************************************************************************/ +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + +#if defined(USART_CTRL_MVDIS) + /* Disable the majority vote if specified. */ + if (init->mvdis) { + usart->CTRL |= USART_CTRL_MVDIS; + } +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + /* Configure the PRS input mode. */ + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, stopbits, and parity. */ + usart->FRAME = (uint32_t)init->databits + | (uint32_t)init->stopbits + | (uint32_t)init->parity; + + /* Configure baudrate. */ + USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); + +#endif + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) + usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); + usart->ROUTEPEN |= init->hwFlowControl; + +#elif defined(USART_CTRLX_CTSEN) + if ((init->hwFlowControl == usartHwFlowControlRts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { +#if USART_COUNT > 1 + GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_SET[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } else { +#if USART_COUNT > 1 + GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_CLR[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } + + if ((init->hwFlowControl == usartHwFlowControlCts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { + usart->CTRLX_SET = USART_CTRLX_CTSEN; + } else { + usart->CTRLX_CLR = USART_CTRLX_CTSEN; + } +#endif + + /* Finally, enable (as specified). */ + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for synchronous mode. + * + * @details + * This function will configure basic settings to operate in + * synchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure basic async setup. + ******************************************************************************/ +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Set bits for synchronous mode. */ + usart->CTRL |= (USART_CTRL_SYNC) + | (uint32_t)init->clockMode + | (init->msbf ? USART_CTRL_MSBF : 0); + +#if defined(_USART_CTRL_AUTOTX_MASK) + usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, leave stopbits and parity at reset default (not used). */ + usart->FRAME = (uint32_t)init->databits + | USART_FRAME_STOPBITS_DEFAULT + | USART_FRAME_PARITY_DEFAULT; + + /* Configure the baudrate. */ + USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); + + /* Finally, enable (as specified). */ + if (init->master) { + usart->CMD = USART_CMD_MASTEREN; + } + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); +#endif + + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for asynchronous IrDA mode. + * + * @details + * This function will configure basic settings to operate in + * asynchronous IrDA mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and IRCTRL + * registers. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure async IrDA setup. + * + * @note + * Not all USART instances support IrDA. See the data sheet for your device. + * + ******************************************************************************/ +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) +{ + EFM_ASSERT(USART_IRDA_VALID(usart)); + + /* Initialize USART as an async device. */ + USART_InitAsync(usart, &(init->async)); + + /* Set IrDA modulation to RZI (return-to-zero-inverted). */ + usart->CTRL |= USART_CTRL_TXINV; + + /* Invert the Rx signal before the demodulator if enabled. */ + if (init->irRxInv) { + usart->CTRL |= USART_CTRL_RXINV; + } + + /* Configure IrDA. */ + usart->IRCTRL = (uint32_t)init->irPw + | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); + +#if defined(USART_IRCTRL_IRPRSEN) + if (init->irPrsEn) { + prsIrInput(usart, init->irPrsSel); + } +#endif + + /* Enable IrDA. */ + usart->IRCTRL |= USART_IRCTRL_IREN; +} + +#if defined(_USART_I2SCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize USART for I2S mode. + * + * @details + * This function will configure basic settings to operate in I2S + * mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and I2SCTRL + * registers. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic I2S setup. + * + * @note + * This function does not apply to all USART's. See the chip Reference Manual. + * + ******************************************************************************/ +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) +{ + USART_Enable_TypeDef enable; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_I2S_VALID(usart)); + + /* Override the enable setting. */ + enable = init->sync.enable; + init->sync.enable = usartDisable; + + /* Initialize USART as a sync device. */ + USART_InitSync(usart, &init->sync); + + /* Configure and enable I2CCTRL register according to the selected mode. */ + usart->I2SCTRL = (uint32_t)init->format + | (uint32_t)init->justify + | (init->delay ? USART_I2SCTRL_DELAY : 0) + | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) + | (init->mono ? USART_I2SCTRL_MONO : 0) + | USART_I2SCTRL_EN; + + if (enable != usartDisable) { + USART_Enable(usart, enable); + } +} +#endif + +/***************************************************************************//** + * @brief + * Initialize the automatic transmissions using PRS channel as a trigger. + * @note + * Initialize USART with USART_Init() before setting up the PRS configuration. + * + * @param[in] usart + * A pointer to USART to configure. + * + * @param[in] init + * A pointer to the initialization structure. + ******************************************************************************/ +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) +{ + uint32_t trigctrl; + + prsTriggerInput(usart, init->prsTriggerChannel); + /* Clear values that will be reconfigured. */ + trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK + | _USART_TRIGCTRL_TXTEN_MASK +#if defined(USART_TRIGCTRL_AUTOTXTEN) + | _USART_TRIGCTRL_AUTOTXTEN_MASK +#endif + ); + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + if (init->autoTxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_AUTOTXTEN; + } +#endif + if (init->txTriggerEnable) { + trigctrl |= USART_TRIGCTRL_TXTEN; + } + if (init->rxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_RXTEN; + } + usart->TRIGCTRL = trigctrl; +} + +/***************************************************************************//** + * @brief + * Reset USART/UART to the same state that it was in after a hardware reset. + * + * @param[in] usart + * A pointer to USART/UART peripheral register block. + ******************************************************************************/ +void USART_Reset(USART_TypeDef *usart) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart) ); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; + /* Make sure disabled first, before resetting other registers. */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->CTRLX = _USART_CTRLX_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IF_CLR = _USART_IF_MASK; + usart->TIMING = _USART_TIMING_RESETVALUE; + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } + usart->EN_CLR = USART_EN_EN; + +#else + /* Make sure disabled first, before resetting other registers */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IFC = _USART_IFC_MASK; +#if defined(_USART_TIMING_MASK) + usart->TIMING = _USART_TIMING_RESETVALUE; +#endif +#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) + usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; + usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; +#else + usart->ROUTE = _USART_ROUTE_RESETVALUE; +#endif + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + +#if defined(_USART_INPUT_RESETVALUE) + usart->INPUT = _USART_INPUT_RESETVALUE; +#endif + +#if defined(_USART_I2SCTRL_RESETVALUE) + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-8 bits. See @ref USART_RxExt() for reception of + * 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataGet() to read the RXDATA + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_Rx(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames or one 10-16 bit frame. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. See @ref USART_RxDoubleExt() for + * reception of two 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxDouble(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint32_t USART_RxDoubleExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-9 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint16_t)usart->RXDATAX; +} + +/***************************************************************************//** + * @brief + * Perform one 8 bit frame SPI transfer. + * + * @note + * This function will stall if the transmit buffer is full. When a transmit + * buffer becomes available, data is written and the function will wait until + * data is fully transmitted. The SPI return value is then read out and + * returned. + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] data + * Data to transmit. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) +{ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; + while (!(usart->STATUS & USART_STATUS_TXC)) { + } + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from + * @p data and one bit as specified by CTRL register, BIT8DV field. + * See USART_TxExt() for transmitting 9 bit frame with full control of + * all 9 bits. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit. See details above for more information. + ******************************************************************************/ +void USART_Tx(USART_TypeDef *usart, uint8_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * each byte in @p data are transmitted. If frame length is 9, 8 bits are + * transmitted from each byte in @p data adding one bit as specified by the CTRL + * register, BIT8DV field, to each byte. See USART_TxDoubleExt() + * for transmitting two 9 bit frames with full control of all 9 bits. + * + * If the frame length is 10-16, 10-16 (least significant) bits from @p data + * are transmitted. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit, the least significant byte holds the frame transmitted + * first. See details above for more info. + ******************************************************************************/ +void USART_TxDouble(USART_TypeDef *usart, uint16_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLE = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Contains two 16 bit words + * concatenated. Least significant word holds the frame transmitted first. If the frame + * length is 4-9, two frames with 4-9 least significant bits from each 16 bit + * word are transmitted. + * @par + * If the frame length is 10-16 bits, 8 data bits are taken from the least + * significant 16 bit word and the remaining bits from the other 16 bit word. + * @par + * Additional control bits are available as documented in the reference + * manual (set to 0 if not used). For 10-16 bit frame length, these control + * bits are taken from the most significant 16 bit word. + ******************************************************************************/ +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) +{ + /* Check that transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLEX = data; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Least significant bit contains + * frame bits. Additional control bits are available as documented in + * the reference manual (set to 0 if not used). + ******************************************************************************/ +void USART_TxExt(USART_TypeDef *usart, uint16_t data) +{ + /* Check that the transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATAX = (uint32_t)data; +} + +/** @} (end addtogroup usart) */ +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_vdac.c b/Libs/platform/emlib/src/em_vdac.c new file mode 100644 index 0000000..c4ad2e3 --- /dev/null +++ b/Libs/platform/emlib/src/em_vdac.c @@ -0,0 +1,636 @@ +/***************************************************************************//** + * @file + * @brief Digital to Analog Converter (VDAC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_vdac.h" +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) +#include "em_cmu.h" + +/***************************************************************************//** + * @addtogroup vdac + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the VDAC channel for assert statements. */ +#define VDAC_CH_VALID(ch) ((ch) <= 1) + +/** A maximum VDAC clock. */ +#define VDAC_MAX_CLOCK 1000000 + +/** The maximum clock frequency of the internal clock oscillator, 10 MHz + 20%. */ +#define VDAC_INTERNAL_CLOCK_FREQ 12000000 + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_VDAC_EN_MASK) +static void VDAC_DisableModule(VDAC_TypeDef* vdac) +{ + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + /* Wait for all synchronizations to finish */ + if (vdac->EN & VDAC_EN_EN) { + vdac->CMD = _VDAC_CMD_CH0DIS_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS)) { + } + + vdac->CMD = _VDAC_CMD_CH1DIS_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH1ENS)) { + } + +#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + vdac->CMD = VDAC_CMD_CH0FIFOFLUSH | VDAC_CMD_CH1FIFOFLUSH; + + while (vdac->STATUS & (VDAC_STATUS_SYNCBUSY | VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { + } +#endif + vdac->EN_CLR = _VDAC_EN_EN_MASK; + while (vdac->EN & _VDAC_EN_DISABLING_MASK) { + } + } +} +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable the VDAC channel. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] ch + * A channel to enable/disable. + * + * @param[in] enable + * True to enable VDAC channel, false to disable. + ******************************************************************************/ +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + +#if defined(_VDAC_STATUS_SYNCBUSY_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } +#endif + + if (ch == 0) { + if (enable) { + vdac->CMD = VDAC_CMD_CH0EN; + while ((vdac->STATUS & VDAC_STATUS_CH0ENS) == 0) { + } + } else { + vdac->CMD = VDAC_CMD_CH0DIS; + while (vdac->STATUS & VDAC_STATUS_CH0ENS) { + } +#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + vdac->CMD = VDAC_CMD_CH0FIFOFLUSH; + while (vdac->STATUS & VDAC_STATUS_CH0FIFOFLBUSY) { + } +#endif + } + } else { + if (enable) { + vdac->CMD = VDAC_CMD_CH1EN; + while ((vdac->STATUS & VDAC_STATUS_CH1ENS) == 0) { + } + } else { + vdac->CMD = VDAC_CMD_CH1DIS; + while (vdac->STATUS & VDAC_STATUS_CH1ENS) { + } + +#if defined(_VDAC_CMD_CH1FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + vdac->CMD = VDAC_CMD_CH1FIFOFLUSH; + while (vdac->STATUS & VDAC_STATUS_CH1FIFOFLBUSY) { + } +#endif + } + } +} + +/***************************************************************************//** + * @brief + * Initialize VDAC. + * + * @details + * Initializes the common parts for both channels. This function will also load + * calibration values from the Device Information (DI) page into the VDAC + * calibration register. + * To complete a VDAC setup, channel control configuration must also be done. + * See VDAC_InitChannel(). + * + * @note + * This function will disable both channels prior to configuration. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] init + * A pointer to the VDAC initialization structure. + ******************************************************************************/ +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + uint32_t config = 0; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + uint32_t cal; + uint32_t const volatile *calData; + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + + /* Get the OFFSETTRIM calibration value. */ + cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) + >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) + << _VDAC_CAL_OFFSETTRIM_SHIFT; + + if (init->mainCalibration) { + calData = &DEVINFO->VDAC0MAINCAL; + } else { + calData = &DEVINFO->VDAC0ALTCAL; + } + + /* Get the correct GAINERRTRIM calibration value. */ + switch (init->reference) { + case vdacRef1V25Ln: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; + break; + + case vdacRef2V5Ln: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; + break; + + case vdacRef1V25: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; + break; + + case vdacRef2V5: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; + break; + + case vdacRefAvdd: + case vdacRefExtPin: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; + break; + } + + /* Set the sGAINERRTRIM calibration value. */ + cal |= config << _VDAC_CAL_GAINERRTRIM_SHIFT; + + /* Get the GAINERRTRIMCH1 calibration value. */ + switch (init->reference) { + case vdacRef1V25Ln: + case vdacRef1V25: + case vdacRefAvdd: + case vdacRefExtPin: + config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; + break; + + case vdacRef2V5Ln: + case vdacRef2V5: + config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; + break; + } + + /* Set the GAINERRTRIM calibration value. */ + cal |= config << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; + + config = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) + | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) + & _VDAC_CTRL_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) + | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); + + /* Write to VDAC registers. */ + vdac->CAL = cal; + vdac->CTRL = config; +#elif defined(_SILICON_LABS_32B_SERIES_2) + + VDAC_DisableModule(vdac); + + config = ( +#if defined(VDAC_CFG_SINEMODEPRS) + ((uint32_t)init->sineModePrsEnable ? VDAC_CFG_SINEMODEPRS : 0U) | +#endif +#if defined(VDAC_CFG_OUTENPRS) + ((uint32_t)init->prsOutEnable ? VDAC_CFG_OUTENPRS : 0U) | +#endif + (((uint32_t)init->warmupTime << _VDAC_CFG_WARMUPTIME_SHIFT) & _VDAC_CFG_WARMUPTIME_MASK) + | ((uint32_t)init->dbgHalt << _VDAC_CFG_DBGHALT_SHIFT) + | ((uint32_t)init->onDemandClk << _VDAC_CFG_ONDEMANDCLK_SHIFT) + | ((uint32_t)init->dmaWakeUp << _VDAC_CFG_DMAWU_SHIFT) + | ((uint32_t)init->biasKeepWarm << _VDAC_CFG_BIASKEEPWARM_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CFG_REFRESHPERIOD_SHIFT) + | ((uint32_t)init->timerOverflow << _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CFG_PRESC_SHIFT) & _VDAC_CFG_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CFG_REFRSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CFG_CH0PRESCRST_SHIFT) + | ((uint32_t)init->sineReset << _VDAC_CFG_SINERESET_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CFG_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CFG_DIFF_SHIFT)); + + vdac->CFG = config; +#endif +} + +/***************************************************************************//** + * @brief + * Initialize a VDAC channel. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] init + * A pointer to the VDAC channel initialization structure. + * + * @param[in] ch + * A channel number to initialize. + ******************************************************************************/ +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch) +{ + uint32_t channelConfig, vdacStatus; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + vdacStatus = vdac->STATUS; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + + channelConfig = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); + + if (ch == 0) { + vdac->CH0CTRL = channelConfig; + } else { + vdac->CH1CTRL = channelConfig; + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + + VDAC_DisableModule(vdac); + + channelConfig = ((uint32_t)init->warmupKeepOn << _VDAC_CH0CFG_KEEPWARM_SHIFT) + | ((uint32_t)init->highCapLoadEnable << _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT) + | (((uint32_t)init->fifoLowDataThreshold << _VDAC_CH0CFG_FIFODVL_SHIFT) & _VDAC_CH0CFG_FIFODVL_MASK) + | ((uint32_t)init->chRefreshSource << _VDAC_CH0CFG_REFRESHSOURCE_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CFG_TRIGMODE_SHIFT) + | ((uint32_t)init->powerMode << _VDAC_CH0CFG_POWERMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CFG_CONVMODE_SHIFT); + + if (ch == 0) { + vdac->CH0CFG = channelConfig; + + vdac->OUTTIMERCFG = ((uint32_t)(vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK))) + | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK); + + vdac->EN_SET = _VDAC_EN_EN_MASK; + + vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH0_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK | _VDAC_OUTCTRL_SHORTCH0_MASK | _VDAC_OUTCTRL_AUXOUTENCH0_MASK | _VDAC_OUTCTRL_MAINOUTENCH0_MASK))) + | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH0_MASK) + | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT) + | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH0_SHIFT) + | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT) + | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT); + } else if (ch == 1) { + vdac->CH1CFG = channelConfig; + + vdac->OUTTIMERCFG = (vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK)) + | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK); + + vdac->EN_SET = _VDAC_EN_EN_MASK; + + vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH1_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK | _VDAC_OUTCTRL_SHORTCH1_MASK | _VDAC_OUTCTRL_AUXOUTENCH1_MASK | _VDAC_OUTCTRL_MAINOUTENCH1_MASK))) + | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH1_MASK) + | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT) + | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH1_SHIFT) + | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT) + | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT); + } +#endif + + /* Check if the channel must be enabled. */ + if (init->enable) { + if (ch == 0) { + vdac->CMD = VDAC_CMD_CH0EN; + } else { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + + /* Check if the other channel had to be turned off above + * and needs to be turned on again. */ + if (ch == 0) { + if (vdacStatus & VDAC_STATUS_CH1ENS) { + vdac->CMD = VDAC_CMD_CH1EN; + } + } else { + if (vdacStatus & VDAC_STATUS_CH0ENS) { + vdac->CMD = VDAC_CMD_CH0EN; + } + } +} + +/***************************************************************************//** + * @brief + * Set the output signal of a VDAC channel to a given value. + * + * @details + * This function sets the output signal of a VDAC channel by writing @p value + * to the corresponding CHnDATA register. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] channel + * A channel number to set the output of. + * + * @param[in] value + * A value to write to the channel output register CHnDATA. + ******************************************************************************/ +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value) +{ + switch (channel) { + case 0: + VDAC_Channel0OutputSet(vdac, value); + break; + case 1: + VDAC_Channel1OutputSet(vdac, value); + break; + default: + EFM_ASSERT(0); + break; + } +} + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Calculate the prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by the input clock divided by the prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * The maximum VDAC clock is 1 MHz. The input clock is HFPERCLK/HFPERCCLK + * when VDAC synchronous mode is selected, or an internal oscillator of + * 10 MHz +/- 20% when asynchronous mode is selected. + * + * @note + * If the requested VDAC frequency is low and the maximum prescaler value can't + * adjust the actual VDAC frequency lower than requested, the maximum prescaler + * value is returned resulting in a higher VDAC frequency than requested. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below maximum allowed VDAC clock. + * + * @param[in] syncMode Set to true if you intend to use VDAC in synchronous + * mode. + * + * @param[in] hfperFreq Frequency in Hz of HFPERCLK/HFPERCCLK oscillator. + * Set to 0 to use the currently defined HFPERCLK/HFPERCCLK clock setting. + * This parameter is only used when syncMode is set to true. + * + * @return + * A prescaler value to use for VDAC to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) +{ + uint32_t ret, refFreq; + + /* Make sure that the selected VDAC clock is below the maximum value. */ + if (vdacFreq > VDAC_MAX_CLOCK) { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (!syncMode) { + refFreq = VDAC_INTERNAL_CLOCK_FREQ; + } else { + if (hfperFreq) { + refFreq = hfperFreq; + } else { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); + } + } + + /* Iterate to determine the best prescaler value. Start with the lowest */ + /* prescaler value to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT); ret++) { + if ((refFreq / (ret + 1)) <= vdacFreq) { + break; + } + } + + /* If ret is higher than the maximum prescaler value, make sure to return + the maximum value. */ + if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) { + ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; + } + + return ret; +} +#else +/***************************************************************************//** + * @brief + * Calculate the prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by the input clock divided by the prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * The maximum VDAC clock is 1 MHz. + * + * @note + * If the requested VDAC frequency is low and the maximum prescaler value can't + * adjust the actual VDAC frequency lower than requested, the maximum prescaler + * value is returned resulting in a higher VDAC frequency than requested. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below maximum allowed VDAC clock. + * + * @return + * A prescaler value to use for VDAC to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq) +{ + uint32_t ret = 0; + uint32_t refFreq = 0; + + /* Make sure that the selected VDAC clock is below the maximum value. */ + if (vdacFreq > VDAC_MAX_CLOCK) { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (vdac == VDAC0) { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); + } +#if defined(VDAC1) + else if (vdac == VDAC1) { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC1); + } +#endif + else { + EFM_ASSERT(0); + } + + /* Iterate to determine the best prescaler value. Start with the lowest */ + /* prescaler value to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT); ret++) { + if ((refFreq / (ret + 1)) <= vdacFreq) { + break; + } + } + + /* If ret is higher than the maximum prescaler value, make sure to return + the maximum value. */ + if (ret > (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT)) { + ret = _VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT; + } + + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Reset VDAC to same state that it was in after a hardwares reset. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + ******************************************************************************/ +void VDAC_Reset(VDAC_TypeDef *vdac) +{ +#if defined(VDAC_SWRST_SWRST) + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + /* Wait for all synchronizations to finish and disable the vdac channels */ + if (vdac->EN & VDAC_EN_EN) { + vdac->CMD = _VDAC_CMD_CH0DIS_MASK; + while (vdac->STATUS & VDAC_STATUS_CH0ENS ) { + } + + vdac->CMD = _VDAC_CMD_CH1DIS_MASK; + while (vdac->STATUS & VDAC_STATUS_CH1ENS ) { + } + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + vdac->CMD = _VDAC_CMD_CH0FIFOFLUSH_MASK | _VDAC_CMD_CH1FIFOFLUSH_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { + } + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + } + + vdac->SWRST_SET = VDAC_SWRST_SWRST; + while (vdac->SWRST & _VDAC_SWRST_RESETTING_MASK) { + } + +#else + /* Disable channels before resetting other registers. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; + vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; + vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; + vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; + vdac->CTRL = _VDAC_CTRL_RESETVALUE; + vdac->IEN = _VDAC_IEN_RESETVALUE; + vdac->IFC = _VDAC_IFC_MASK; + vdac->CAL = _VDAC_CAL_RESETVALUE; +#endif +} + +/** @} (end addtogroup vdac) */ +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ diff --git a/Libs/platform/emlib/src/em_wdog.c b/Libs/platform/emlib/src/em_wdog.c new file mode 100644 index 0000000..4fa0346 --- /dev/null +++ b/Libs/platform/emlib/src/em_wdog.c @@ -0,0 +1,355 @@ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_wdog.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include "em_bus.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup wdog WDOG - Watchdog + * @brief Watchdog (WDOG) Peripheral API + * @details + * This module contains functions to control the WDOG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The WDOG resets the system in case of a fault + * condition. + * @{ + ******************************************************************************/ + +/** In some scenarioes when the watchdog is disabled the synchronization + * register might be set and not be cleared until the watchdog is enabled + * again. This will happen when for instance some watchdog register is modified + * while the watchdog clock is disabled. In these scenarioes we need to make + * sure that the software does not wait forever. */ +#define WDOG_SYNC_TIMEOUT 30000 + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable the watchdog timer. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + * + * @param[in] enable + * True to enable Watchdog, false to disable. Watchdog cannot be disabled if + * it's been locked. + ******************************************************************************/ +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable) +{ + // SYNCBUSY may stall when locked. +#if defined(_WDOG_STATUS_MASK) + if ((wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED) { + return; + } +#else + if (wdog->CTRL & WDOG_CTRL_LOCK) { + return; + } +#endif + +#if defined(_WDOG_EN_MASK) + if (!enable) { + while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + } +#endif + } else { + wdog->EN_SET = WDOG_EN_EN; + } +#else + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + + bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); + + // Make sure to only write to the CTRL register if we are changing mode + if (wdogState != enable) { + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); + } +#endif +} + +/***************************************************************************//** + * @brief + * Feed WDOG. + * + * @details + * When WDOG is activated, it must be fed (i.e., clearing the counter) + * before it reaches the defined timeout period. Otherwise, WDOG + * will generate a reset. + * + * @note + * Note that WDOG is an asynchronous peripheral and when calling the + * WDOGn_Feed() function the hardware starts the process of clearing the + * counter. This process takes some time before it completes depending on the + * selected oscillator (up to 4 peripheral clock cycles). When using the + * ULFRCO for instance as the oscillator the watchdog runs on a 1 kHz clock + * and a watchdog clear operation might take up to 4 ms. + * + * If the device enters EM2 or EM3 while a command is in progress then that + * command will be aborted. An application can use @ref WDOGn_SyncWait() + * to wait for a command to complete. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Feed(WDOG_TypeDef *wdog) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + + // WDOG should not be fed while it is disabled. + if (!(wdog->CTRL & WDOG_CTRL_EN)) { + return; + } + + // If a previous clearing is synchronized to the LF domain, there + // is no point in waiting for it to complete before clearing over again. + // This avoids stalling the core in the typical use case where some idle loop + // keeps clearing WDOG. + if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + return; + } + // Before writing to the WDOG_CMD register, make sure that + // any previous write to the WDOG_CTRL is complete. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + wdog->CMD = WDOG_CMD_CLEAR; + +#else // Series 2 devices + + CORE_DECLARE_IRQ_STATE; + + // WDOG should not be fed while it is disabled. + if ((wdog->EN & WDOG_EN_EN) == 0U) { + return; + } + + // We need an atomic section around the check for sync and the clear command + // because sending a clear command while a previous command is being synchronized + // will cause a BusFault. + CORE_ENTER_ATOMIC(); + if ((wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) == 0U) { + wdog->CMD = WDOG_CMD_CLEAR; + } + CORE_EXIT_ATOMIC(); + +#endif +} + +/***************************************************************************//** + * @brief + * Initialize WDOG (assuming the WDOG configuration has not been + * locked). + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] init + * The structure holding the WDOG configuration. A default setting + * #WDOG_INIT_DEFAULT is available for initialization. + ******************************************************************************/ +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init) +{ +#if defined(_WDOG_CFG_MASK) + // Handle series-2 devices + + if (wdog->EN != 0U) { + while (wdog->SYNCBUSY != 0U) { + // Wait for any potential synchronization to finish + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } + + wdog->CFG = (init->debugRun ? WDOG_CFG_DEBUGRUN : 0U) + | (init->clrSrc ? WDOG_CFG_CLRSRC : 0U) +#if defined(_WDOG_CFG_EM1RUN_MASK) + | (init->em1Run ? WDOG_CFG_EM1RUN : 0U) +#endif + | (init->em2Run ? WDOG_CFG_EM2RUN : 0U) + | (init->em3Run ? WDOG_CFG_EM3RUN : 0U) + | (init->em4Block ? WDOG_CFG_EM4BLOCK : 0U) + | (init->prs0MissRstEn ? WDOG_CFG_PRS0MISSRSTEN : 0U) + | (init->prs1MissRstEn ? WDOG_CFG_PRS1MISSRSTEN : 0U) + | (init->resetDisable ? WDOG_CFG_WDOGRSTDIS : 0U) + | ((uint32_t)(init->warnSel) << _WDOG_CFG_WARNSEL_SHIFT) + | ((uint32_t)(init->winSel) << _WDOG_CFG_WINSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CFG_PERSEL_SHIFT); + + WDOGn_Enable(wdog, init->enable); + + if (init->lock) { + WDOGn_Lock(wdog); + } +#else + // Handle series-0 and series-1 devices + uint32_t setting; + + setting = (init->enable ? WDOG_CTRL_EN : 0U) + | (init->debugRun ? WDOG_CTRL_DEBUGRUN : 0U) +#if defined(_WDOG_CTRL_CLRSRC_MASK) + | (init->clrSrc ? WDOG_CTRL_CLRSRC : 0U) +#endif + | (init->em2Run ? WDOG_CTRL_EM2RUN : 0U) + | (init->em3Run ? WDOG_CTRL_EM3RUN : 0U) + | (init->em4Block ? WDOG_CTRL_EM4BLOCK : 0U) + | (init->swoscBlock ? WDOG_CTRL_SWOSCBLOCK : 0U) + | (init->lock ? WDOG_CTRL_LOCK : 0U) + | ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT); + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) + setting |= (init->resetDisable ? WDOG_CTRL_WDOGRSTDIS : 0U); +#endif +#if defined(_WDOG_CTRL_WARNSEL_MASK) + setting |= ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT); +#endif +#if defined(_WDOG_CTRL_WINSEL_MASK) + setting |= ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT); +#endif + + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + wdog->CTRL = setting; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the WDOG configuration. + * + * @details + * This prevents errors from overwriting the WDOG configuration, possibly + * disabling it. Only a reset can unlock the WDOG configuration once locked. + * + * If the LFRCO or LFXO clocks are used to clock WDOG, + * consider using the option of inhibiting those clocks to be disabled. + * See the WDOG_Enable() initialization structure. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Lock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_LOCK; +#else + // Wait for any pending previous write operation to have been completed in + // the low-frequency domain. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + // Disable writing to the control register. + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the WDOG to complete all synchronization of register changes + * and commands. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_SyncWait(WDOG_TypeDef *wdog) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((wdog->EN != 0U) && (wdog->SYNCBUSY != 0U)) { + // Wait for synchronization to finish + } +#else + while (wdog->SYNCBUSY != 0U) { + // Wait for synchronization to finish + } +#endif +} + +/***************************************************************************//** + * @brief + * Unlock the WDOG configuration. + * + * @details + * Note that this function will have no effect on devices where a reset is + * the only way to unlock the watchdog. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Unlock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_UNLOCK; +#else + (void) wdog; +#endif +} + +/** @} (end addtogroup wdog) */ +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ diff --git a/Libs/platform/peripheral/inc/peripheral_sysrtc.h b/Libs/platform/peripheral/inc/peripheral_sysrtc.h new file mode 100644 index 0000000..500c115 --- /dev/null +++ b/Libs/platform/peripheral/inc/peripheral_sysrtc.h @@ -0,0 +1,32 @@ +/***************************************************************************//** + * @file + * @brief System Real Time Counter (SYSRTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Compatibility layer. peripheral_sysrtc.h has been renamed to sl_hal_sysrtc.h +#include "sl_hal_sysrtc.h" diff --git a/Libs/platform/peripheral/inc/peripheral_sysrtc_compat.h b/Libs/platform/peripheral/inc/peripheral_sysrtc_compat.h new file mode 100644 index 0000000..2321e8b --- /dev/null +++ b/Libs/platform/peripheral/inc/peripheral_sysrtc_compat.h @@ -0,0 +1,33 @@ +/***************************************************************************//** + * @file + * @brief SYSRTC Compatibility Layer. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Compatibility layer. peripheral_sysrtc_compat.h has been renamed to +// sl_hal_sysrtc_compat.h +#include "sl_hal_sysrtc_compat.h" diff --git a/Libs/platform/peripheral/inc/sl_hal_bus.h b/Libs/platform/peripheral/inc/sl_hal_bus.h new file mode 100644 index 0000000..4283af0 --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_bus.h @@ -0,0 +1,274 @@ +/***************************************************************************//** + * @file + * @brief RAM and peripheral bit-field set, clear, read and write API. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_BUS_H +#define SL_HAL_BUS_H + +#include "sl_assert.h" +#include "sl_core.h" +#include "em_device.h" +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup bus BUS - Bitfield Read/Write + * @brief BUS register and RAM bit-field read/write API + * @details + * API to perform field set/clear/write/read access to RAM and peripheral's registers. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a 32-bit word in RAM. + * + * @param[in] addr An address of a 32-bit word in RAM. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void sl_hal_bus_ram_write_bit(volatile uint32_t *addr, + uint32_t bit, + uint32_t val) +{ + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a 32-bit word in RAM. + * + * @param[in] addr RAM address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int sl_hal_bus_ram_read_bit(volatile const uint32_t *addr, + uint32_t bit) +{ + return ((*addr) >> bit) & 1UL; +} + +/***************************************************************************//** + * @brief + * Perform a single-bit atomic write operation on a peripheral register. + * + * @details + * This function uses built-in hardware 4K-aliased addressing that allows to + * perform an atomic read-modify-write operation on a single register bit. + * See the reference manual for more details about alias addressing. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_COMMON, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE void sl_hal_bus_reg_write_bit(volatile uint32_t *addr, + uint32_t bit, + uint32_t val) +{ + EFM_ASSERT(bit < 32U); + +#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr; + if (val != 0U) { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + } else { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + } + *(volatile uint32_t *)aliasAddr = 1UL << bit; +#else + uint32_t tmp = *addr; + + // Make sure val is not more than 1 because only one bit needs to be set. + *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit atomic read operation on a peripheral register. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int sl_hal_bus_reg_read_bit(volatile const uint32_t *addr, + uint32_t bit) +{ + return ((*addr) >> bit) & 1UL; +} + +/***************************************************************************//** + * @brief + * Perform an atomic masked set operation on a peripheral register address. + * + * @details + * A peripheral register masked set provides a set operation of a bit-mask + * in a peripheral register. All 1s in the mask are set to 1 in the register. + * All 0s in the mask are not changed in the register. + * RAMs and special peripherals are not supported. + * + * @note + * This function uses built-in hardware 4K-aliased addressing that allows to + * perform an atomic read-modify-write operation. + * See the reference manual for more details about alias addressing. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to set. + ******************************************************************************/ +__STATIC_INLINE void sl_hal_bus_reg_set_mask(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_SET_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr |= mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform an atomic masked clear operation on the peripheral register address. + * + * @details + * A peripheral register masked clear provides a clear operation of a bit-mask + * in a peripheral register. All 1s in the mask are set to 0 in the register. + * All 0s in the mask are not changed in the register. + * RAMs and special peripherals are not supported. + * + * @note + * This function uses built-in hardware 4K-aliased addressing that allows to + * perform an atomic read-modify-write operation. + * See the reference manual for more details about alias addressing. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to clear. + ******************************************************************************/ +__STATIC_INLINE void sl_hal_bus_reg_clear_mask(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr &= ~mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform peripheral register masked write. + * + * @details + * This function first reads the peripheral register and updates only bits + * that are set in the mask with content of val. Typically, the mask is a + * bit-field in the register and the value val is within the mask. + * + * @note + * The read-modify-write operation is executed in a critical section to + * guarantee atomicity. Note that atomicity can only be guaranteed if register + * is modified only by the core, and not by other peripherals (like DMA). + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @param[in] val A peripheral register value. The value must be shifted to the + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. The + register value is masked to prevent involuntary spillage. + ******************************************************************************/ +__STATIC_INLINE void sl_hal_bus_reg_write_mask(volatile uint32_t *addr, + uint32_t mask, + uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + *addr = (*addr & ~mask) | (val & mask); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Perform a peripheral register masked read. + * + * @details + * Read an unshifted and masked value from a peripheral register. + * + * @note + * This operation is not hardware accelerated. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @return + * An unshifted and masked register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t sl_hal_bus_reg_read_mask(volatile const uint32_t *addr, + uint32_t mask) +{ + return *addr & mask; +} + +/** @} (end addtogroup bus) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_HAL_BUS_H */ diff --git a/Libs/platform/peripheral/inc/sl_hal_gpio.h b/Libs/platform/peripheral/inc/sl_hal_gpio.h new file mode 100644 index 0000000..87df889 --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_gpio.h @@ -0,0 +1,915 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_GPIO_H +#define SL_HAL_GPIO_H + +#include "em_device.h" + +#if defined(GPIO_PRESENT) + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "sl_assert.h" +#include "sl_device_gpio.h" +#include "sl_code_classification.h" + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup gpio GPIO - General Purpose Input Output +/// @brief General Purpose Input Output peripheral +/// +/// @li @ref gpio_intro +/// +///@n @section gpio_intro Introduction +/// This module contains functions to control the GPIO peripheral of Silicon Labs 32-bit MCUs and SoCs. +/// The GPIO peripheral is used for interrupt configuration, pin configuration and direct pin manipulation +/// as well as routing for peripheral pin connections. +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************** DEFINES ********************************** + ******************************************************************************/ + +/// Define for port specific pin mask +#if defined(GPIO_PA_MASK) +#define SL_HAL_GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) +#else +#define SL_HAL_GPIO_PORT_A_PIN_MASK 0 +#endif +#if defined(GPIO_PB_MASK) +#define SL_HAL_GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) +#else +#define SL_HAL_GPIO_PORT_B_PIN_MASK 0 +#endif +#if defined(GPIO_PC_MASK) +#define SL_HAL_GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) +#else +#define SL_HAL_GPIO_PORT_C_PIN_MASK 0 +#endif +#if defined(GPIO_PD_MASK) +#define SL_HAL_GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) +#else +#define SL_HAL_GPIO_PORT_D_PIN_MASK 0 +#endif +#if defined(GPIO_PE_MASK) +#define SL_HAL_GPIO_PORT_E_PIN_MASK (GPIO_PE_MASK) +#else +#define SL_HAL_GPIO_PORT_E_PIN_MASK 0 +#endif +#if defined(GPIO_PF_MASK) +#define SL_HAL_GPIO_PORT_F_PIN_MASK (GPIO_PF_MASK) +#else +#define SL_HAL_GPIO_PORT_F_PIN_MASK 0 +#endif +#if defined(GPIO_PG_MASK) +#define SL_HAL_GPIO_PORT_G_PIN_MASK (GPIO_PG_MASK) +#else +#define SL_HAL_GPIO_PORT_G_PIN_MASK 0 +#endif +#if defined(GPIO_PH_MASK) +#define SL_HAL_GPIO_PORT_H_PIN_MASK (GPIO_PH_MASK) +#else +#define SL_HAL_GPIO_PORT_H_PIN_MASK 0 +#endif +#if defined(GPIO_PI_MASK) +#define SL_HAL_GPIO_PORT_I_PIN_MASK (GPIO_PI_MASK) +#else +#define SL_HAL_GPIO_PORT_I_PIN_MASK 0 +#endif +#if defined(GPIO_PJ_MASK) +#define SL_HAL_GPIO_PORT_J_PIN_MASK (GPIO_PJ_MASK) +#else +#define SL_HAL_GPIO_PORT_J_PIN_MASK 0 +#endif +#if defined(GPIO_PK_MASK) +#define SL_HAL_GPIO_PORT_K_PIN_MASK (GPIO_PK_MASK) +#else +#define SL_HAL_GPIO_PORT_K_PIN_MASK 0 +#endif + +/// Define for port specific pin count +#if defined(GPIO_PA_COUNT) +#define SL_HAL_GPIO_PORT_A_PIN_COUNT (GPIO_PA_COUNT) +#else +#define SL_HAL_GPIO_PORT_A_PIN_COUNT 0 +#endif +#if defined(GPIO_PB_COUNT) +#define SL_HAL_GPIO_PORT_B_PIN_COUNT (GPIO_PB_COUNT) +#else +#define SL_HAL_GPIO_PORT_B_PIN_COUNT 0 +#endif +#if defined(GPIO_PC_COUNT) +#define SL_HAL_GPIO_PORT_C_PIN_COUNT (GPIO_PC_COUNT) +#else +#define SL_HAL_GPIO_PORT_C_PIN_COUNT 0 +#endif +#if defined(GPIO_PD_COUNT) +#define SL_HAL_GPIO_PORT_D_PIN_COUNT (GPIO_PD_COUNT) +#else +#define SL_HAL_GPIO_PORT_D_PIN_COUNT 0 +#endif +#if defined(GPIO_PE_COUNT) +#define SL_HAL_GPIO_PORT_E_PIN_COUNT (GPIO_PE_COUNT) +#else +#define SL_HAL_GPIO_PORT_E_PIN_COUNT 0 +#endif +#if defined(GPIO_PF_COUNT) +#define SL_HAL_GPIO_PORT_F_PIN_COUNT (GPIO_PF_COUNT) +#else +#define SL_HAL_GPIO_PORT_F_PIN_COUNT 0 +#endif +#if defined(GPIO_PG_COUNT) +#define SL_HAL_GPIO_PORT_G_PIN_COUNT (GPIO_PG_COUNT) +#else +#define SL_HAL_GPIO_PORT_G_PIN_COUNT 0 +#endif +#if defined(GPIO_PH_COUNT) +#define SL_HAL_GPIO_PORT_H_PIN_COUNT (GPIO_PH_COUNT) +#else +#define SL_HAL_GPIO_PORT_H_PIN_COUNT 0 +#endif +#if defined(GPIO_PI_COUNT) +#define SL_HAL_GPIO_PORT_I_PIN_COUNT (GPIO_PI_COUNT) +#else +#define SL_HAL_GPIO_PORT_I_PIN_COUNT 0 +#endif +#if defined(GPIO_PJ_COUNT) +#define SL_HAL_GPIO_PORT_J_PIN_COUNT (GPIO_PJ_COUNT) +#else +#define SL_HAL_GPIO_PORT_J_PIN_COUNT 0 +#endif +#if defined(GPIO_PK_COUNT) +#define SL_HAL_GPIO_PORT_K_PIN_COUNT (GPIO_PK_COUNT) +#else +#define SL_HAL_GPIO_PORT_K_PIN_COUNT 0 +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/// Highest GPIO port number. + +#if (SL_HAL_GPIO_PORT_K_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 10 +#elif (SL_HAL_GPIO_PORT_J_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 9 +#elif (SL_HAL_GPIO_PORT_I_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 8 +#elif (SL_HAL_GPIO_PORT_H_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 7 +#elif (SL_HAL_GPIO_PORT_G_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 6 +#elif (SL_HAL_GPIO_PORT_F_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 5 +#elif (SL_HAL_GPIO_PORT_E_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 4 +#elif (SL_HAL_GPIO_PORT_D_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 3 +#elif (SL_HAL_GPIO_PORT_C_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 2 +#elif (SL_HAL_GPIO_PORT_B_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 1 +#elif (SL_HAL_GPIO_PORT_A_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 0 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +/// Highest GPIO pin number. +#define SL_HAL_GPIO_PIN_MAX 15 + +/// @endcond + +#define SL_HAL_GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? SL_HAL_GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? SL_HAL_GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? SL_HAL_GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? SL_HAL_GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? SL_HAL_GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? SL_HAL_GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? SL_HAL_GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? SL_HAL_GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? SL_HAL_GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? SL_HAL_GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? SL_HAL_GPIO_PORT_K_PIN_COUNT \ + : 0) + +#define SL_HAL_GPIO_PORT_MASK(port) ( \ + ((int)port) == 0 ? SL_HAL_GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? SL_HAL_GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? SL_HAL_GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? SL_HAL_GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? SL_HAL_GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? SL_HAL_GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? SL_HAL_GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? SL_HAL_GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? SL_HAL_GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? SL_HAL_GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? SL_HAL_GPIO_PORT_K_PIN_MASK \ + : 0UL) + +/// Validation of port. +#define SL_HAL_GPIO_PORT_IS_VALID(port) (SL_HAL_GPIO_PORT_MASK(port) != 0x0UL) + +/// Validation of port and pin. +#define SL_HAL_GPIO_PORT_PIN_IS_VALID(port, pin) ((((SL_HAL_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) + +/// Max interrupt lines for external and EM4 interrupts. +#define SL_HAL_GPIO_INTERRUPT_MAX 15 + +/// Shift value for EM4WUEN +#define SL_HAL_GPIO_EM4WUEN_SHIFT _GPIO_EM4WUEN_EM4WUEN_SHIFT + +/// Masks for even and odd interrupt bits. +#define SL_HAL_GPIO_INT_IF_EVEN_MASK ((_GPIO_IF_MASK) & 0x55555555UL) +#define SL_HAL_GPIO_INT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) + +/// Validation of mode. +#define SL_HAL_GPIO_MODE_IS_VALID(mode) ((mode & _GPIO_P_MODEL_MODE0_MASK) == mode) + +/// Validation of interrupt number and pin. +#define SL_HAL_GPIO_INTNO_PIN_VALID(int_no, pin) (((int_no) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Set the mode for a GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] mode The desired pin mode. + * @param[in] output_value A value to set for the pin in the DOUT register. The DOUT setting is important for + * some input mode configurations to determine the pull-up/down direction. + ******************************************************************************/ +void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value); + +/***************************************************************************//** + * Get the mode for a GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return Return the pin mode. + ******************************************************************************/ +sl_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Configure the GPIO external pin interrupt by connecting external interrupt id with gpio pin. + * + * @note This function configure the pin interrupt with pin ,port and external interrupt id as input. + * If external interrupt id is provided as input it will be considered as the input or else + * available interrupt number will be generated by looping through the interrupt group and will be used. + * User can provide SL_HAL_GPIO_INTERRUPT_UNAVAILABLE if user don't want to provide interrupt id. + * @note the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (int_no / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * @note It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref sl_hal_gpio_disable_interrupts() for more information. + * The GPIO interrupt handler must be in place before enabling the interrupt. + * Notice that any pending interrupt for the selected interrupt is cleared by this function. + * Notice that only interrupt will be configured by this function. It is not enabled. + * It is recommended to enable interrupts after configuring the GPIO pin interrupt if needed. + * See @ref sl_hal_gpio_enable_interrupts() for more information. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] int_no The interrupt number to trigger. + * @param[in] flags Interrupt configuration flags. @ref sl_hal_gpio_interrupt_flag_t for more information. + * + * @return Return the available interrupt number + ******************************************************************************/ +int32_t sl_hal_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t int_no, + sl_gpio_interrupt_flag_t flags); + +/**************************************************************************//** + * Enable GPIO pin wake-up from EM4. When the function exits, + * EM4 mode can be safely entered. + * + * @note It is assumed that the GPIO pin modes are set correctly. + * Valid modes are SL_GPIO_MODE_INPUT and SL_GPIO_MODE_INPUT_PULL. + * + * @param[in] pinmask A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. + * @param[in] polaritymask A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. + *****************************************************************************/ +void sl_hal_gpio_enable_pin_em4_wakeup(uint32_t pinmask, + uint32_t polaritymask); + +/***************************************************************************//** + * Configure EM4WU pins as external level-sensitive interrupts. + * + * @note It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref sl_hal_gpio_disable_interrupts() for more information. + * The provided port, pin and int_no inputs should be valid EM4 related parameters + * because there are dedicated port, pin and EM4 Wakeup interrupt combination for + * configuring the port, pin for EM4 functionality. + * User can provide SL_HAL_GPIO_INTERRUPT_UNAVAILABLE if user don't want to provide interrupt id. + * The GPIO interrupt handler must be in place before enabling the interrupt. + * Notice that any pending interrupt for the selected interrupt is cleared by this function. + * Notice that any only EM4WU interrupt is configured by this function. It is not enabled. + * It is recommended to enable interrupts after configuring the GPIO pin interrupt if needed. + * See @ref sl_hal_gpio_enable_interrupts() for more information. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] int_no The EM4WU interrupt number to trigger. + * @param[in] polarity true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * + * @return Return the available EM4WU interrupt number + ******************************************************************************/ +int32_t sl_hal_gpio_configure_wakeup_em4_external_interrupt(const sl_gpio_t *gpio, + int32_t int_no, + bool polarity); + +/***************************************************************************//** + * Lock the GPIO configuration. + * + * @note Configuration lock affects the GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_CTRL, + * GPIO_Px_PINLOCKN, GPIO_EXTIPSELL, GPIO_EXTIPSELH, GPIO_EXTIPINSELL, + * GPIO_EXTIPINSELH, GPIO_INSENSE, GPIO_ROUTE, GPIO_ROUTEPEN, and + * GPIO_ROUTELOC0 registers when they are present on a specific device. + * @note Unwanted or accidental changes to GPIO configuration can be avoided by + * using the configuration lock register. Any value other than 0xA534 written to + * GPIO_LOCK enables the configuration lock. Pins are unlocked by a reset or + * by writing 0xA534 to the GPIO_LOCK register. + ******************************************************************************/ +__INLINE void sl_hal_gpio_lock(void) +{ + GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Unlock the GPIO configuration. + * + * @note Configuration lock affects the GPIO_Px_MODEL, GPIO_Px_MODEH, GPIO_Px_CTRL, + * GPIO_Px_PINLOCKN, GPIO_EXTIPSELL, GPIO_EXTIPSELH, GPIO_EXTIPINSELL, + * GPIO_EXTIPINSELH, GPIO_INSENSE, GPIO_ROUTE, GPIO_ROUTEPEN, and + * GPIO_ROUTELOC0 registers when they are present on a specific device. + * @note Unwanted or accidental changes to GPIO configuration can be avoided by + * using the configuration lock register. Any value other than 0xA534 written to + * GPIO_LOCK enables the configuration lock. Pins are unlocked by a reset or + * by writing 0xA534 to the GPIO_LOCK register. + ******************************************************************************/ +__INLINE void sl_hal_gpio_unlock(void) +{ + GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Gets the GPIO configuration state. + * + * @return Return the GPIO lock state. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_lock_status(void) +{ + return GPIO->GPIOLOCKSTATUS; +} + +/***************************************************************************//** + * Set a single pin in GPIO data out register to 1. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_GPIO, SL_CODE_CLASS_TIME_CRITICAL) +__INLINE void sl_hal_gpio_set_pin(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + GPIO->P_SET[gpio->port].DOUT = 1UL << gpio->pin; +} + +/***************************************************************************//** + * Set bits GPIO data out register to 1. + * + * @param[in] port The GPIO port to access. + * @param[in] pins Bit mask for bits to set to 1 in DOUT register. + ******************************************************************************/ +__INLINE void sl_hal_gpio_set_port(sl_gpio_port_t port, + uint32_t pins) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + GPIO->P_SET[port].DOUT = pins; +} + +/***************************************************************************//** + * Set GPIO port data out register. + * + * @param[in] port The GPIO port to access. + * @param[in] val Value to write to port data out register. + * @param[in] mask Mask indicating which bits to modify. + ******************************************************************************/ +__INLINE void sl_hal_gpio_set_port_value(sl_gpio_port_t port, + uint32_t val, + uint32_t mask) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); +} + +/***************************************************************************//** + * Set slewrate for pins on a GPIO port which are configured into normal modes. + * + * @param[in] port The GPIO port to configure. + * @param[in] slewrate The slewrate to configure for pins on this GPIO port. + ******************************************************************************/ +__INLINE void sl_hal_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK + >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL + & ~_GPIO_P_CTRL_SLEWRATE_MASK) + | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT); +} + +/***************************************************************************//** + * Set slewrate for pins on a GPIO port which are configured into alternate modes. + * + * @param[in] port The GPIO port to configure. + * @param[in] slewrate_alt The slewrate to configure for pins using alternate modes on this GPIO port. + ******************************************************************************/ +__INLINE void sl_hal_gpio_set_slew_rate_alternate(sl_gpio_port_t port, + uint8_t slewrate_alt) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(slewrate_alt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK + >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL + & ~_GPIO_P_CTRL_SLEWRATEALT_MASK) + | (slewrate_alt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); +} + +/***************************************************************************//** + * Get slewrate for pins on a GPIO port. + * + * @param[in] port The GPIO port to access to get slew rate. + * + * @return Return the slewrate setting for the selected GPIO port. + ******************************************************************************/ +__INLINE uint8_t sl_hal_gpio_get_slew_rate(sl_gpio_port_t port) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + return (GPIO->P[port].CTRL & _GPIO_P_CTRL_SLEWRATE_MASK) >> _GPIO_P_CTRL_SLEWRATE_SHIFT; +} + +/***************************************************************************//** + * Get slewrate for pins on a GPIO port which are configured into alternate modes. + * + * @param[in] port The GPIO port to access to get slew rate. + * + * @return Return the alternate slewrate setting for selected GPIO port. + ******************************************************************************/ +__INLINE uint8_t sl_hal_gpio_get_slew_rate_alternate(sl_gpio_port_t port) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + return (GPIO->P[port].CTRL & _GPIO_P_CTRL_SLEWRATEALT_MASK) >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT; +} + +/***************************************************************************//** + * Set a single pin in GPIO data out port register to 0. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + ******************************************************************************/ +__INLINE void sl_hal_gpio_clear_pin(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + GPIO->P_CLR[gpio->port].DOUT = 1UL << gpio->pin; +} + +/***************************************************************************//** + * Set bits in DOUT register for a port to 0. + * + * @param[in] port The GPIO port to access. + * @param[in] pins Bit mask for bits to clear in DOUT register. + ******************************************************************************/ +__INLINE void sl_hal_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + GPIO->P_CLR[port].DOUT = pins; +} + +/***************************************************************************//** + * Read the pad value for a single pin in a GPIO port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin. + * + * @return The pin value, 0 or 1. + ******************************************************************************/ +__INLINE bool sl_hal_gpio_get_pin_input(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + bool pin_input = ((GPIO->P[gpio->port].DIN) >> gpio->pin) & 1UL; + + return pin_input; +} + +/***************************************************************************//** + * Get current setting for a pin in a GPIO port data out register. + * + * @param[in] gpio Pointer to GPIO structure with port and pin. + * + * @return The DOUT setting for the requested pin, 0 or 1. + ******************************************************************************/ +__INLINE bool sl_hal_gpio_get_pin_output(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + bool pin_output = ((GPIO->P[gpio->port].DOUT) >> gpio->pin) & 1UL; + + return pin_output; +} + +/***************************************************************************//** + * Read the pad values for GPIO port. + * + * @param[in] port The GPIO port to access. + * + * @return The pad values for the GPIO port. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_port_input(sl_gpio_port_t port) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + return GPIO->P[port].DIN; +} + +/***************************************************************************//** + * Get current setting for a GPIO port data out register. + * + * @param[in] port The GPIO port to access. + * + * @return The data out setting for the requested port. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_port_output(sl_gpio_port_t port) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + return GPIO->P[port].DOUT; +} + +/***************************************************************************//** + * Toggle a single pin in GPIO port data out register. + * + * @param[in] gpio Pointer to GPIO structure with port and pin. + ******************************************************************************/ +__INLINE void sl_hal_gpio_toggle_pin(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + GPIO->P_TGL[gpio->port].DOUT = 1UL << gpio->pin; +} + +/***************************************************************************//** + * Toggle pins in GPIO port data out register. + * + * @param[in] port The GPIO port to access. + * @param[in] pins Bit mask with pins to toggle. + ******************************************************************************/ +__INLINE void sl_hal_gpio_toggle_port(sl_gpio_port_t port, + uint32_t pins) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); + + GPIO->P_TGL[port].DOUT = pins; +} + +/***************************************************************************//** + * Enable one or more GPIO interrupts. + * + * @param[in] flags GPIO interrupt sources to enable. + ******************************************************************************/ +__INLINE void sl_hal_gpio_enable_interrupts(uint32_t flags) +{ + GPIO->IEN_SET = flags; +} + +/***************************************************************************//** + * Disable one or more GPIO interrupts. + * + * @param[in] flags GPIO interrupt sources to disable. + ******************************************************************************/ +__INLINE void sl_hal_gpio_disable_interrupts(uint32_t flags) +{ + GPIO->IEN_CLR = flags; +} + +/***************************************************************************//** + * Clear one or more pending GPIO interrupts. + * + * @param[in] flags Bitwise logic OR of GPIO interrupt sources to clear. + ******************************************************************************/ +__INLINE void sl_hal_gpio_clear_interrupts(uint32_t flags) +{ + GPIO->IF_CLR = flags; +} + +/**************************************************************************//** + * Set one or more pending GPIO interrupts from SW. + * + * @param[in] flags GPIO interrupt sources to set to pending. + *****************************************************************************/ +__INLINE void sl_hal_gpio_set_interrupts(uint32_t flags) +{ + GPIO->IF_SET = flags; +} + +/***************************************************************************//** + * Get pending GPIO interrupts. + * + * @return GPIO interrupt sources pending. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_pending_interrupts(void) +{ + return GPIO->IF; +} + +/***************************************************************************//** + * Get enabled GPIO interrupts. + * + * @return Enabled GPIO interrupt sources. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_enabled_interrupts(void) +{ + return GPIO->IEN; +} + +/***************************************************************************//** + * Get enabled and pending GPIO interrupt flags. + * + * @return Enabled and pending interrupt sources. + * + * @note Useful for handling more interrupt sources in the same interrupt handler. + ******************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_enabled_pending_interrupts(void) +{ + uint32_t tmp; + + tmp = GPIO->IEN; + + return GPIO->IF & tmp; +} + +/***************************************************************************//** + * The available external interrupt number getter. + * + * @param[in] pin The GPIO pin to access. + * @param[in] enabled_interrupts_mask Contains enabled GPIO interrupts mask. + * + * @return The available interrupt number based on interrupt and pin grouping. + ******************************************************************************/ +__INLINE int32_t sl_hal_gpio_get_external_interrupt_number(uint8_t pin, + uint32_t enabled_interrupts_mask) +{ + uint32_t interrupt_to_check; + uint32_t int_group_start = (pin & 0xFFC); + int32_t int_no = -1; + // loop through the interrupt group, starting + // from the pin number, and take + // the first available. + for (uint8_t i = 0; i < 4; i++) { + interrupt_to_check = int_group_start + ((pin + i) & 0x3); // modulo 4 + if (((enabled_interrupts_mask >> interrupt_to_check) & 0x1) == 0) { + int_no = interrupt_to_check; + break; + } + } + return int_no; +} + +/***************************************************************************//** + * The available em4 wakeup interrupt number getter. + * + * @param[in] gpio Pointer to GPIO structure with port and pin. + * + * @return The available em4 wakeup interrupt number based on associated port and pin. + ******************************************************************************/ +__INLINE int32_t sl_hal_gpio_get_em4_interrupt_number(const sl_gpio_t *gpio) +{ + EFM_ASSERT(gpio != NULL); + int32_t em4_int_no; + + if (false) { + // Check all the EM4WU Pins and check if given port, pin matches any of them. + #if defined(GPIO_EM4WU0_PORT) + } else if (GPIO_EM4WU0_PORT == gpio->port && GPIO_EM4WU0_PIN == gpio->pin) { + em4_int_no = 0; + #endif + #if defined(GPIO_EM4WU1_PORT) + } else if (GPIO_EM4WU1_PORT == gpio->port && GPIO_EM4WU1_PIN == gpio->pin) { + em4_int_no = 1; + #endif + #if defined(GPIO_EM4WU3_PORT) + } else if (GPIO_EM4WU3_PORT == gpio->port && GPIO_EM4WU3_PIN == gpio->pin) { + em4_int_no = 3; + #endif + #if defined(GPIO_EM4WU4_PORT) + } else if (GPIO_EM4WU4_PORT == gpio->port && GPIO_EM4WU4_PIN == gpio->pin) { + em4_int_no = 4; + #endif + #if defined(GPIO_EM4WU6_PORT) + } else if (GPIO_EM4WU6_PORT == gpio->port && GPIO_EM4WU6_PIN == gpio->pin) { + em4_int_no = 6; + #endif + #if defined(GPIO_EM4WU7_PORT) + } else if (GPIO_EM4WU7_PORT == gpio->port && GPIO_EM4WU7_PIN == gpio->pin) { + em4_int_no = 7; + #endif + #if defined(GPIO_EM4WU8_PORT) + } else if (GPIO_EM4WU8_PORT == gpio->port && GPIO_EM4WU8_PIN == gpio->pin) { + em4_int_no = 8; + #endif + #if defined(GPIO_EM4WU9_PORT) + } else if (GPIO_EM4WU9_PORT == gpio->port && GPIO_EM4WU9_PIN == gpio->pin) { + em4_int_no = 9; + #endif + #if defined(GPIO_EM4WU10_PORT) + } else if (GPIO_EM4WU10_PORT == gpio->port && GPIO_EM4WU10_PIN == gpio->pin) { + em4_int_no = 10; + #endif + } else { + em4_int_no = -1; + } + + return em4_int_no; +} + +/*************************************************************************//** +* Disable GPIO pin wake-up from EM4. +* +* @param[in] pinmask Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. +*****************************************************************************/ +__INLINE void sl_hal_gpio_disable_pin_em4_wakeup(uint32_t pinmask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); + + GPIO->EM4WUEN &= ~pinmask; +} + +/**************************************************************************//** + * Enable GPIO pin retention of output enable, output value, pull enable, and + * pull direction in EM4. + * + * @note The behavior of this function depends on the configured GPIO retention mode. + * If the GPIO retention mode is configured to be "SWUNLATCH" then this + * function will not change anything. If the retention mode is anything else + * then this function will set the GPIO retention mode to "EM4EXIT" when the + * enable argument is true, and "Disabled" when false. + * + * @param[in] enable true - enable EM4 pin retention. + * false - disable EM4 pin retention. + *****************************************************************************/ +__INLINE void sl_hal_gpio_set_pin_em4_retention(bool enable) +{ + // Leave configuration alone when software unlatch is used. + uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; + + if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { + return; + } + + if (enable) { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; + } else { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_DISABLE; + } +} + +/**************************************************************************//** + * Check which GPIO pin(s) that caused a wake-up from EM4. + * + * @return Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the wake-up. + *****************************************************************************/ +__INLINE uint32_t sl_hal_gpio_get_pin_em4_wakeup_cause(void) +{ + return GPIO->IF & _GPIO_EM4WUEN_EM4WUEN_MASK; +} + +/***************************************************************************//** + * Enable/Disable serial wire output pin. + * + * @note Enabling this pin is not sufficient to fully enable serial wire output, + * which is also dependent on issues outside the GPIO module. + * @note If debug port is locked, SWO pin is not disabled automatically. To avoid + * information leakage through SWO, disable SWO pin after locking debug port. + * + * @param[in] enable false - disable serial wire viewer pin (default after reset). + * true - enable serial wire viewer pin. + ******************************************************************************/ +__INLINE void sl_hal_gpio_enable_debug_swo(bool enable) +{ + uint32_t bit = enable ? 0x1UL : 0x0UL; + + if (bit != 0U) { + GPIO->TRACEROUTEPEN_SET = 1UL << _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT; + } else { + GPIO->TRACEROUTEPEN_CLR = 1UL << _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT; + } +} + +/***************************************************************************//** + * Enable/disable serial wire clock pin. + * + * @note Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable false - disable serial wire clock. + * true - enable serial wire clock (default after reset). + ******************************************************************************/ +__INLINE void sl_hal_gpio_enable_debug_swd_clk(bool enable) +{ + uint32_t bit = enable ? 0x1UL : 0x0UL; + + if (bit != 0U) { + GPIO->DBGROUTEPEN_SET = 1UL << _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT; + } else { + GPIO->DBGROUTEPEN_CLR = 1UL << _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT; + } +} + +/***************************************************************************//** + * Enable/disable serial wire data I/O pin. + * + * @note Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable false - disable serial wire data pin. + * true - enable serial wire data pin (default after reset). + ******************************************************************************/ +__INLINE void sl_hal_gpio_enable_debug_swd_io(bool enable) +{ + uint32_t bit = enable ? 0x1UL : 0x0UL; + + if (bit != 0U) { + GPIO->DBGROUTEPEN_SET = 1UL << _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT; + } else { + GPIO->DBGROUTEPEN_CLR = 1UL << _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT; + } +} + +/** @} (end addtogroup gpio) */ + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PRESENT */ +#endif /* SL_HAL_GPIO_H */ diff --git a/Libs/platform/peripheral/inc/sl_hal_syscfg.h b/Libs/platform/peripheral/inc/sl_hal_syscfg.h new file mode 100644 index 0000000..4f417e7 --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_syscfg.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief API defining access to SYSCFG registers + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_SYSCFG_H +#define SL_HAL_SYSCFG_H + +#include + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_service_syscfg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup syscfg SYSTEM CONFIGURATION - System Configurations + * @brief Syscfg API + * @details + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/******************************************************************************* + ******************************** TZ SERVICES ********************************** + ******************************************************************************/ + +/******************************************************************************* + * @brief + * Reads CHIPREV register. + ******************************************************************************/ +uint32_t sl_hal_syscfg_read_chip_rev(void); + +/******************************************************************************* + * @brief + * Set SYSTICEXTCLKEN bit in CFGSYSTIC to one. + ******************************************************************************/ +void sl_hal_syscfg_set_systicextclken_cfgsystic(void); + +/******************************************************************************* + * @brief + * Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero. + ******************************************************************************/ +void sl_hal_syscfg_clear_systicextclken_cfgsystic(void); + +#ifdef __cplusplus +} +#endif +#endif // SL_HAL_SYSCFG_H diff --git a/Libs/platform/peripheral/inc/sl_hal_sysrtc.h b/Libs/platform/peripheral/inc/sl_hal_sysrtc.h new file mode 100644 index 0000000..e3a9b8a --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_sysrtc.h @@ -0,0 +1,445 @@ +/***************************************************************************//** + * @file + * @brief System Real Time Counter (SYSRTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_SYSRTC_H +#define SL_HAL_SYSRTC_H + +#include "em_device.h" + +#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) +#include +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_hal_sysrtc_compat.h" +#include "sl_enum.h" + +/***************************************************************************//** + * @addtogroup sysrtc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/// Minimum compare channels for SYSRTC group. +#define SYSRTC_GROUP_MIN_CHANNEL_COMPARE 1u +/// Maximum compare channels for SYSRTC group. +#define SYSRTC_GROUP_MAX_CHANNEL_COMPARE 2u + +/// Minimum capture channels for SYSRTC group. +#define SYSRTC_GROUP_MIN_CHANNEL_CAPTURE 0u +/// Maximum capture channels for SYSRTC group. +#define SYSRTC_GROUP_MAX_CHANNEL_CAPTURE 1u + +/// Sysrtc group number. +#if !defined(SYSRTC_GROUP_NUMBER) +#define SYSRTC_GROUP_NUMBER 1u +#endif + +/// Validation of valid SYSRTC group for assert statements. +#define SYSRTC_GROUP_VALID(group) ((unsigned)(group) < SYSRTC_GROUP_NUMBER) + +/******************************************************************************* + ********************************* ENUM ************************************ + ******************************************************************************/ + +/// Capture input edge select. +SL_ENUM(sl_hal_sysrtc_capture_edge_t) { + SL_HAL_SYSRTC_CAPTURE_EDGE_RISING = 0, ///< Rising edges detected. + SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING, ///< Falling edges detected. + SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH ///< Both edges detected. +}; + +/// Compare match output action mode. +SL_ENUM(sl_hal_sysrtc_compare_match_out_action_t) { + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR = 0, ///< Clear output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET, ///< Set output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE, ///< Generate a pulse. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE, ///< Toggle output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF ///< Export CMPIF. +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/// SYSRTC configuration structure. +typedef struct { + bool enable_debug_run; ///< Counter shall keep running during debug halt. +} sl_hal_sysrtc_config_t; + +/// Suggested default values for SYSRTC configuration structure. +#define SYSRTC_CONFIG_DEFAULT \ + { \ + false, /* Disable updating during debug halt. */ \ + } + +/// Compare channel configuration structure. +typedef struct { + sl_hal_sysrtc_compare_match_out_action_t compare_match_out_action; ///< Compare mode channel match output action. +} sl_hal_sysrtc_group_channel_compare_config_t; + +/// Capture channel configuration structure. +typedef struct { + sl_hal_sysrtc_capture_edge_t capture_input_edge; ///< Capture mode channel input edge. +} sl_hal_sysrtc_group_channel_capture_config_t; + +/// Group configuration structure. +typedef struct { + bool compare_channel0_enable; ///< Enable/Disable compare channel 0 + bool compare_channel1_enable; ///< Enable/Disable compare channel 1 + bool capture_channel0_enable; ///< Enable/Disable capture channel 0 + sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel0_config; ///< Pointer to compare channel 0 config + sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel1_config; ///< Pointer to compare channel 1 config + sl_hal_sysrtc_group_channel_capture_config_t const *p_capture_channel0_config; ///< Pointer to capture channel 0 config +} sl_hal_sysrtc_group_config_t; + +/// Suggested default values for compare channel configuration structure. +#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_DEFAULT \ + { \ + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE \ + } + +/// Compare channel configuration for starting HFXO using PRS. +#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_EARLY_WAKEUP \ + { \ + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF \ + } + +/// Suggested default values for capture channel configuration structure. +#define SYSRTC_GROUP_CHANNEL_CAPTURE_CONFIG_DEFAULT \ + { \ + SL_HAL_SYSRTC_CAPTURE_EDGE_RISING \ + } + +/// Suggested default values for SYSRTC group configuration structure. +#define SYSRTC_GROUP_CONFIG_DEFAULT \ + { \ + true, /* Enable compare channel 0. */ \ + false, /* Disable compare channel 1. */ \ + false, /* Disable capture channel 0. */ \ + NULL, /* NULL Pointer to configuration structure for compare channel 0*/ \ + NULL, /* NULL Pointer to configuration structure for compare channel 1*/ \ + NULL /* NULL Pointer to configuration structure for capture channel 0*/ \ + } + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initializes SYSRTC module. + * + * Note that the compare values must be set separately with + * (sl_hal_sysrtc_set_group_compare_channel_value()), which should probably be + * done prior to the use of this function if configuring the SYSRTC to start + * when initialization is completed. + * + * @param[in] p_config A pointer to the SYSRTC initialization structure + * variable. + ******************************************************************************/ +void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config); + +/***************************************************************************//** + * Enables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_enable(void); + +/***************************************************************************//** + * Disables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_disable(void); + +/***************************************************************************//** + * Waits for the SYSRTC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +__INLINE void sl_hal_sysrtc_wait_sync(void) +{ + while ((SYSRTC0->EN & SYSRTC_EN_EN) && (SYSRTC0->SYNCBUSY != 0U)) { + // Wait for all synchronizations to finish + } +} + +/***************************************************************************//** + * Waits for the SYSRTC to complete reseting or disabling procedure. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_wait_ready(void) +{ + while ((SYSRTC0->SWRST & _SYSRTC_SWRST_RESETTING_MASK) || (SYSRTC0->EN & _SYSRTC_EN_DISABLING_MASK) || (SYSRTC0->SYNCBUSY != 0U)) { + // Wait for all synchronizations to finish + } +} + +/***************************************************************************//** + * Starts SYSRTC counter. + * + * This function will send a start command to the SYSRTC peripheral. The SYSRTC + * peripheral will use some LF clock ticks before the command is executed. + * The sl_hal_sysrtc_wait_sync() function can be used to wait for the start + * command to be executed. + * + * @note This function requires the SYSRTC to be enabled. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_start(void) +{ + sl_hal_sysrtc_wait_sync(); + SYSRTC0->CMD = SYSRTC_CMD_START; +} + +/***************************************************************************//** + * Stops the SYSRTC counter. + * + * This function will send a stop command to the SYSRTC peripheral. The SYSRTC + * peripheral will use some LF clock ticks before the command is executed. + * The sl_hal_sysrtc_wait_sync() function can be used to wait for the stop + * command to be executed. + * + * @note This function requires the SYSRTC to be enabled. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_stop(void) +{ + sl_hal_sysrtc_wait_sync(); + SYSRTC0->CMD = SYSRTC_CMD_STOP; +} + +/***************************************************************************//** + * Restores SYSRTC to its reset state. + ******************************************************************************/ +void sl_hal_sysrtc_reset(void); + +/***************************************************************************//** + * Gets SYSRTC STATUS register value. + * + * @return Current STATUS register value. + ******************************************************************************/ +__INLINE uint32_t sl_hal_sysrtc_get_status(void) +{ + return SYSRTC0->STATUS; +} + +/***************************************************************************//** + * Locks SYSRTC registers. + * + * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, + * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written + * to. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_lock(void) +{ + SYSRTC0->LOCK = ~SYSRTC_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Unlocks SYSRTC registers. + * + * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, + * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written + * to. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_unlock(void) +{ + SYSRTC0->LOCK = SYSRTC_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Gets SYSRTC counter value. + * + * @return Current SYSRTC counter value. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +__INLINE uint32_t sl_hal_sysrtc_get_counter(void) +{ + // Wait for Counter to synchronize before getting value + sl_hal_sysrtc_wait_sync(); + + return SYSRTC0->CNT; +} + +/***************************************************************************//** + * Sets the SYSRTC counter value. + * + * @param[in] value The new SYSRTC counter value. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_set_counter(uint32_t value) +{ + // Wait for Counter to synchronize before getting value + sl_hal_sysrtc_wait_sync(); + + SYSRTC0->CNT = value; +} + +/***************************************************************************//** + * Initializes the selected SYSRTC group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] p_group_config Pointer to group configuration structure + * variable. + ******************************************************************************/ +void sl_hal_sysrtc_init_group(uint8_t group_number, + sl_hal_sysrtc_group_config_t const *p_group_config); + +/***************************************************************************//** + * Enables one or more SYSRTC interrupts for the given group. + * + * @note Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * sl_hal_sysrtc_clear_group_interrupts() prior to enabling the interrupt. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to enable. + * Use a set of interrupt flags OR-ed together to set + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Disables one or more SYSRTC interrupts for the given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to disable. + * Use a set of interrupt flags OR-ed together to disable + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Clears one or more pending SYSRTC interrupts for the given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to clear. + * Use a set of interrupt flags OR-ed together to clear + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Gets pending SYSRTC interrupt flags for the given group. + * + * @note Event bits are not cleared by using this function. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Pending SYSRTC interrupt sources. + * Returns a set of interrupt flags OR-ed together for multiple + * interrupt sources in the SYSRTC group. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number); + +/***************************************************************************//** + * Gets enabled and pending SYSRTC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note Interrupt flags are not cleared by using this function. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Pending and enabled SYSRTC interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in SYSRTC_GRPx_IEN and + * - the pending interrupt flags SYSRTC_GRPx_IF. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number); + +/***************************************************************************//** + * Sets one or more pending SYSRTC interrupts for the given group from Software. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to set to pending. + * Use a set of interrupt flags OR-ed together to set + * multiple interrupt sources for the SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Gets SYSRTC compare register value for selected channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] channel Channel selector. + * + * @return Compare register value. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, + uint8_t channel); + +/***************************************************************************//** + * Sets SYSRTC compare register value for selected channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] channel Channel selector. + * + * @param[in] value Compare register value. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, + uint8_t channel, + uint32_t value); + +/***************************************************************************//** + * Gets SYSRTC input capture register value for capture channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Capture register value. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number); + +/** @} (end addtogroup sysrtc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ +#endif /* SL_HAL_SYSRTC_H */ diff --git a/Libs/platform/peripheral/inc/sl_hal_sysrtc_compat.h b/Libs/platform/peripheral/inc/sl_hal_sysrtc_compat.h new file mode 100644 index 0000000..f7e727c --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_sysrtc_compat.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SYSRTC Compatibility Layer. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_SYSRTC_COMPAT_H +#define SL_HAL_SYSRTC_COMPAT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Enum. +#define SL_SYSRTC_CAPTURE_EDGE_RISING SL_HAL_SYSRTC_CAPTURE_EDGE_RISING +#define SL_SYSRTC_CAPTURE_EDGE_FALLING SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING +#define SL_SYSRTC_CAPTURE_EDGE_BOTH SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF +#define sl_sysrtc_capture_edge_t sl_hal_sysrtc_capture_edge_t +#define sl_sysrtc_compare_match_out_action_t sl_hal_sysrtc_compare_match_out_action_t + +// Structure. +#define sl_sysrtc_config_t sl_hal_sysrtc_config_t +#define sl_sysrtc_group_channel_compare_config_t sl_hal_sysrtc_group_channel_compare_config_t +#define sl_sysrtc_group_channel_capture_config_t sl_hal_sysrtc_group_channel_capture_config_t +#define sl_sysrtc_group_config_t sl_hal_sysrtc_group_config_t + +// Function. +#define sl_sysrtc_init sl_hal_sysrtc_init +#define sl_sysrtc_enable sl_hal_sysrtc_enable +#define sl_sysrtc_disable sl_hal_sysrtc_disable +#define sl_sysrtc_wait_sync sl_hal_sysrtc_wait_sync +#define sl_sysrtc_wait_ready sl_hal_sysrtc_wait_ready +#define sl_sysrtc_start sl_hal_sysrtc_start +#define sl_sysrtc_stop sl_hal_sysrtc_stop +#define sl_sysrtc_reset sl_hal_sysrtc_reset +#define sl_sysrtc_get_status sl_hal_sysrtc_get_status +#define sl_sysrtc_lock sl_hal_sysrtc_lock +#define sl_sysrtc_unlock sl_hal_sysrtc_unlock +#define sl_sysrtc_get_counter sl_hal_sysrtc_get_counter +#define sl_sysrtc_set_counter sl_hal_sysrtc_set_counter +#define sl_sysrtc_init_group sl_hal_sysrtc_init_group +#define sl_sysrtc_enable_group_interrupts sl_hal_sysrtc_enable_group_interrupts +#define sl_sysrtc_disable_group_interrupts sl_hal_sysrtc_disable_group_interrupts +#define sl_sysrtc_clear_group_interrupts sl_hal_sysrtc_clear_group_interrupts +#define sl_sysrtc_get_group_interrupts sl_hal_sysrtc_get_group_interrupts +#define sl_sysrtc_get_group_enabled_interrupts sl_hal_sysrtc_get_group_enabled_interrupts +#define sl_sysrtc_set_group_interrupts sl_hal_sysrtc_set_group_interrupts +#define sl_sysrtc_get_group_compare_channel_value sl_hal_sysrtc_get_group_compare_channel_value +#define sl_sysrtc_set_group_compare_channel_value sl_hal_sysrtc_set_group_compare_channel_value +#define sl_sysrtc_get_group_capture_channel_value sl_hal_sysrtc_get_group_capture_channel_value + +#ifdef __cplusplus +} +#endif + +#endif // SL_HAL_SYSRTC_COMPAT_H diff --git a/Libs/platform/peripheral/inc/sl_hal_system.h b/Libs/platform/peripheral/inc/sl_hal_system.h new file mode 100644 index 0000000..08e26b9 --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_system.h @@ -0,0 +1,146 @@ +/***************************************************************************//** + * @file + * @brief System API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_HAL_SYSTEM_H +#define _SL_HAL_SYSTEM_H + +#include "em_device.h" +#include "sl_hal_system_generic.h" +#include "sl_enum.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @brief System API + * @details + * This module contains functions to read information such as RAM and Flash size, + * device unique ID, chip revision, family, and part number from DEVINFO and + * SCB blocks. Functions to configure and read status from FPU are available for + * compatible devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Family identifiers. +SL_ENUM_GENERIC(sl_hal_system_part_family_t, uint32_t) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_RCP_21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty RCP Series 2 Config 1 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_ZEN_23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Zen Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_SIDEWALK_23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 4 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 4 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 5 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 6 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 7 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_ZEN_28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Zen Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_SIDEWALK_28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + SL_HAL_SYSTEM_PART_FAMILY_BLUETOOTH_301 = DEVINFO_PART0_PROTOCOL_BLUETOOTH \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Bluetooth Config 1 Value Device Family (BG) + SL_HAL_SYSTEM_PART_FAMILY_PROPRIETARY_301 = DEVINFO_PART0_PROTOCOL_PROPRIETARY \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Proprietary Config 1 Value Device Family (FG) + SL_HAL_SYSTEM_PART_FAMILY_FIFTEENPFOUR_301 = DEVINFO_PART0_PROTOCOL_FIFTEENPFOUR \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 15.4 Config 1 Value Device Family (MG) + SL_HAL_SYSTEM_PART_FAMILY_PEARL_301 = DEVINFO_PART0_PROTOCOL_PEARL \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Pearl Config 1 Value Device Family (PG) + SL_HAL_SYSTEM_PART_FAMILY_WIFI_301 = DEVINFO_PART0_PROTOCOL_WIFI \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Wifi Config 1 Value Device Family (WG) + SL_HAL_SYSTEM_PART_FAMILY_ZWAVE_301 = DEVINFO_PART0_PROTOCOL_ZWAVE \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Zwave Config 1 Value Device Family (ZG) +#endif + SL_HAL_SYSTEM_PART_FAMILY_UNKNOWN = 0xFF ///< Unknown Device Family. Family ID is missing on unprogrammed parts. +}; + +/***************************************************************************//** + * @brief + * Get the MCU family identifier. + * + * @return + * Family identifier of MCU. + * + * @note + * This function retrieves family ID by reading the chip's device info + * structure in flash memory. Users can retrieve family ID directly + * by reading DEVINFO->PART item and decode with mask and shift + * \#defines defined in \_devinfo.h (refer to code + * below for details). + ******************************************************************************/ +sl_hal_system_part_family_t sl_hal_system_get_family(void); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SL_HAL_SYSTEM_H */ diff --git a/Libs/platform/peripheral/inc/sl_hal_system_generic.h b/Libs/platform/peripheral/inc/sl_hal_system_generic.h new file mode 100644 index 0000000..27b7fca --- /dev/null +++ b/Libs/platform/peripheral/inc/sl_hal_system_generic.h @@ -0,0 +1,344 @@ +/***************************************************************************//** + * @file + * @brief System API (Generic) + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_HAL_SYSTEM_GENERIC_H +#define _SL_HAL_SYSTEM_GENERIC_H + +#include "sl_enum.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Family security capability. +SL_ENUM(sl_hal_system_security_capability_t) { + /// Unknown security capability. + SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN, + /// Security capability not applicable. + SL_SYSTEM_SECURITY_CAPABILITY_NA, + /// Basic security capability. + SL_SYSTEM_SECURITY_CAPABILITY_BASIC, + /// Root of Trust security capability. + SL_SYSTEM_SECURITY_CAPABILITY_ROT, + /// Secure Element security capability. + SL_SYSTEM_SECURITY_CAPABILITY_SE, + /// Secure Vault security capability. + SL_SYSTEM_SECURITY_CAPABILITY_VAULT +}; + +/// Floating point co-processor access modes. +SL_ENUM_GENERIC(sl_hal_system_fpu_access_t, uint32_t) { + /// Access denied, any attempted access generates a NOCP UsageFault. + SL_SYSTEM_FPU_ACCESS_DENIED = (0x0 << 20), + /// Privileged access only, an unprivileged access generates a NOCP UsageFault. + SL_SYSTEM_FPU_ACCESS_PRIVILEGED_ONLY = (0x5 << 20), + /// Reserved. + SL_SYSTEM_FPU_ACCESS_RESERVED = (0xA << 20), + /// Full access. + SL_SYSTEM_FPU_ACCESS_FULL = (0xF << 20) +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/// Chip revision details. +typedef struct { + uint8_t minor; ///< Minor revision number. + uint8_t major; ///< Major revision number. + uint16_t part_number; ///< Device part number. (0xFFFF if unavailable) + uint16_t family; ///< Device family number. (0xFFFF if unavailable) +} sl_hal_system_chip_revision_t; + +/// ADC Calibration DEVINFO Structures. +typedef struct sl_hal_system_devinfo_adc_cal_data_t { + uint8_t trim_vros0; + uint8_t trim_vros1; + uint8_t trim_gain_4x; + uint8_t trim_gain_0x3_int; +} sl_hal_system_devinfo_adc_cal_data_t; + +typedef struct sl_hal_system_devinfo_adc_offset_t { + uint8_t trim_off_1x; + uint8_t trim_off_2x; + uint8_t trim_off_4x; + uint8_t dummy_byte; +} sl_hal_system_devinfo_adc_offset_t; + +typedef struct sl_hal_system_devinfo_adc_t { + sl_hal_system_devinfo_adc_cal_data_t cal_data; + sl_hal_system_devinfo_adc_offset_t offset; +} sl_hal_system_devinfo_adc_t; + +/// Temperature DEVINFO Structure. +typedef struct sl_hal_system_devinfo_temperature_t { + uint16_t emu_temp_room; + uint16_t cal_temp; +} sl_hal_system_devinfo_temperature_t; + +/// Chip features Structure. +typedef struct sl_hal_system_features { + char feature1; + char feature2; + char feature3; +} sl_hal_system_features_t; + +/******************************************************************************* + ************************** GLOBAL CONSTANTS ******************************* + ******************************************************************************/ + +extern const sl_hal_system_devinfo_adc_t SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + +extern const sl_hal_system_devinfo_temperature_t SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/******************************************************************************* + * @brief + * Get the chip revision. + * + * @param [out] + * rev Pointer to return the chip revision to. + * + * @warning + * The chip revision structure may be returned with either the partnumber or + * family unpopulated (0xFFFF) depending on the device. + ******************************************************************************/ +void sl_hal_system_get_chip_revision(sl_hal_system_chip_revision_t *rev); + +/***************************************************************************//** + * @brief + * Get DEVINFO revision. + * + * @return + * Revision of the DEVINFO contents. + ******************************************************************************/ +uint8_t sl_hal_system_get_devinfo_rev(void); + +/***************************************************************************//** + * @brief + * Get the default factory calibration value for HFRCO oscillator. + * + * @return + * HFRCOCAL default value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_default_calibration(void); + +/***************************************************************************//** + * @brief + * Get the speed factory calibration value for HFRCO oscillator. + * + * @return + * HFRCOCAL speed value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_speed_calibration(void); + +/***************************************************************************//** + * @brief Get the HFRCO calibration based on the frequency band. + * + * @param[in] frequency + * Frequency for which to retrieve calibration. + * + * @return + * HFRCOCAL value for the given band. + * + * @note + * Those calibrations are only valid for the HFRCO oscillator when used with + * the DPLL module. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency); + +/***************************************************************************//** + * @brief + * Get a factory calibration value for HFRCOEM23 oscillator. + * + * @param [in] + * HFRCOEM23 frequency for which to retrieve calibration. + * + * @return + * HFRCOEM23 calibration value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcoem23_calibration(uint32_t frequency); + +/***************************************************************************//** + * @brief + * Get a factory calibration value for HFXOCAL. + * + * @return + * HFXOCAL value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfxocal(void); + +/***************************************************************************//** + * @brief + * Get family security capability. + * + * @note + * This function retrieves the family security capability based on the + * device number. + * + * @return + * Security capability of MCU. + ******************************************************************************/ +sl_hal_system_security_capability_t sl_hal_system_get_security_capability(void); + +/***************************************************************************//** + * @brief + * Get the unique number for this device. + * + * @return + * Unique number for this device. + ******************************************************************************/ +uint64_t sl_hal_system_get_unique(void); + +/***************************************************************************//** + * @brief + * Get the production revision for this part. + * + * @return + * Production revision for this part. + ******************************************************************************/ +uint8_t sl_hal_system_get_prod_rev(void); + +/***************************************************************************//** + * @brief + * Get the SRAM Base Address. + * + * @return + * Base address SRAM (32-bit unsigned integer). + ******************************************************************************/ +uint32_t sl_hal_system_get_sram_base_address(void); + +/***************************************************************************//** + * @brief + * Get the SRAM size (in KB). + * + * @note + * This function retrieves SRAM size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use SRAM_SIZE instead. + * + * @return + * Size of internal SRAM (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_sram_size(void); + +/***************************************************************************//** + * @brief + * Get the flash size (in KB). + * + * @note + * This function retrieves flash size by reading the chip device info structure or + * DEVINFO->EMBMSIZE (embedded flash. not the case for S3 for now) or + * user config (external flash). + * + * @return + * Size of flash (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_flash_size(void); + +/***************************************************************************//** + * @brief + * Get the flash page size in bytes. + * + * @note + * This function retrieves flash page size by reading the SE or + * user config (external flash) + * + * @return + * Page size of flash in bytes. + ******************************************************************************/ +uint32_t sl_hal_system_get_flash_page_size(void); + +/***************************************************************************//** + * @brief + * Get the MCU part number. + * + * @return + * The part number of MCU. + ******************************************************************************/ +uint16_t sl_hal_system_get_part_number(void); + +/***************************************************************************//** + * @brief + * Get the SoC or MCU features. + * + * @return + * The features of the current SoC or MCU. + * + * @note The features can be decoded by referring to the SoC or MCU datasheet. + ******************************************************************************/ +sl_hal_system_features_t sl_hal_system_get_part_features(void); + +/***************************************************************************//** + * @brief + * Get the temperature information. + * + * @param[out] info + * Pointer to variable where to store the temperature info. + ******************************************************************************/ +void sl_hal_system_get_temperature_info(sl_hal_system_devinfo_temperature_t *info); + +/***************************************************************************//** + * @brief + * Set floating point co-processor (FPU) access mode. + * + * @param[in] accessMode + * Floating point co-processor access mode. + ******************************************************************************/ +void sl_hal_system_fpu_set_access_mode(sl_hal_system_fpu_access_t access_mode); + +/***************************************************************************//** + * @brief Get the ADC calibration info. + * + * @param[out] info + * Pointer to variable where to store the adc calibration info. + ******************************************************************************/ +void sl_hal_system_get_adc_calibration_info(sl_hal_system_devinfo_adc_t *info); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SL_HAL_SYSTEM_GENERIC_H */ diff --git a/Libs/platform/peripheral/src/sl_hal_gpio.c b/Libs/platform/peripheral/src/sl_hal_gpio.c new file mode 100644 index 0000000..c941bc6 --- /dev/null +++ b/Libs/platform/peripheral/src/sl_hal_gpio.c @@ -0,0 +1,432 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_hal_gpio.h" +#if defined(GPIO_PRESENT) +#include "sl_hal_bus.h" + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ +extern __INLINE void sl_hal_gpio_lock(void); +extern __INLINE void sl_hal_gpio_unlock(void); +extern __INLINE uint32_t sl_hal_gpio_get_lock_status(void); +extern __INLINE void sl_hal_gpio_set_pin(const sl_gpio_t *gpio); +extern __INLINE void sl_hal_gpio_set_port(sl_gpio_port_t port, + uint32_t pins); +extern __INLINE void sl_hal_gpio_set_port_value(sl_gpio_port_t port, + uint32_t val, + uint32_t mask); +extern __INLINE void sl_hal_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate); +extern __INLINE void sl_hal_gpio_set_slew_rate_alternate(sl_gpio_port_t port, + uint8_t slewrate_alt); +extern __INLINE uint8_t sl_hal_gpio_get_slew_rate(sl_gpio_port_t port); +extern __INLINE uint8_t sl_hal_gpio_get_slew_rate_alternate(sl_gpio_port_t port); +extern __INLINE void sl_hal_gpio_clear_pin(const sl_gpio_t *gpio); +extern __INLINE void sl_hal_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins); +extern __INLINE bool sl_hal_gpio_get_pin_input(const sl_gpio_t *gpio); +extern __INLINE bool sl_hal_gpio_get_pin_output(const sl_gpio_t *gpio); +extern __INLINE uint32_t sl_hal_gpio_get_port_input(sl_gpio_port_t port); +extern __INLINE uint32_t sl_hal_gpio_get_port_output(sl_gpio_port_t port); +extern __INLINE void sl_hal_gpio_toggle_pin(const sl_gpio_t *gpio); +extern __INLINE void sl_hal_gpio_toggle_port(sl_gpio_port_t port, + uint32_t pins); +extern __INLINE void sl_hal_gpio_enable_interrupts(uint32_t flags); +extern __INLINE void sl_hal_gpio_disable_interrupts(uint32_t flags); +extern __INLINE void sl_hal_gpio_clear_interrupts(uint32_t flags); +extern __INLINE void sl_hal_gpio_set_interrupts(uint32_t flags); +extern __INLINE uint32_t sl_hal_gpio_get_pending_interrupts(void); +extern __INLINE uint32_t sl_hal_gpio_get_enabled_interrupts(void); +extern __INLINE uint32_t sl_hal_gpio_get_enabled_pending_interrupts(void); +extern __INLINE int32_t sl_hal_gpio_get_external_interrupt_number(uint8_t pin, + uint32_t enabled_interrupts_mask); +extern __INLINE int32_t sl_hal_gpio_get_em4_interrupt_number(const sl_gpio_t *gpio); +extern __INLINE void sl_hal_gpio_set_pin_em4_retention(bool enable); +extern __INLINE void sl_hal_gpio_disable_pin_em4_wakeup (uint32_t pinmask); +extern __INLINE uint32_t sl_hal_gpio_get_pin_em4_wakeup_cause(void); +extern __INLINE void sl_hal_gpio_enable_debug_swo(bool enable); +extern __INLINE void sl_hal_gpio_enable_debug_swd_clk(bool enable); +extern __INLINE void sl_hal_gpio_enable_debug_swd_io(bool enable); + +/***************************************************************************//** + * Sets the mode for GPIO pin. + ******************************************************************************/ +void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value) +{ + sl_gpio_mode_t gpio_mode = SL_GPIO_MODE_DISABLED; + + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); + + switch (mode) { +#if defined(_GPIO_P_MODEL_MODE0_DISABLED) + case SL_GPIO_MODE_DISABLED: + gpio_mode = _GPIO_P_MODEL_MODE0_DISABLED; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUT) + case SL_GPIO_MODE_INPUT: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULL) + case SL_GPIO_MODE_INPUT_PULL: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUTPULL; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULLFILTER) + case SL_GPIO_MODE_INPUT_PULL_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULL) + case SL_GPIO_MODE_PUSH_PULL: + gpio_mode = _GPIO_P_MODEL_MODE0_PUSHPULL; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + case SL_GPIO_MODE_PUSH_PULL_ALTERNATE: + gpio_mode = _GPIO_P_MODEL_MODE0_PUSHPULLALT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDOR) + case SL_GPIO_MODE_WIRED_OR: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDOR; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN) + case SL_GPIO_MODE_WIRED_OR_PULL_DOWN: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDAND) + case SL_GPIO_MODE_WIRED_AND: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDAND; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDFILTER) + case SL_GPIO_MODE_WIRED_AND_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUP) + case SL_GPIO_MODE_WIRED_AND_PULLUP: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER) + case SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + EFM_ASSERT(SL_HAL_GPIO_MODE_IS_VALID(gpio_mode)); + + // If disabling a pin, do not modify DOUT to reduce the chance of + // a glitch/spike (may not be sufficient precaution in all use cases). + // As mode settings are dependent on DOUT values, setting output value + // prior to mode. @ref enum - sl_gpio_mode_t + if (mode != SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_hal_gpio_set_pin(gpio); + } else { + sl_hal_gpio_clear_pin(gpio); + } + } + + // There are two registers controlling the pins for each port. + // The MODEL register controls pins 0-7 and MODEH controls pins 8-15. + if (gpio->pin < 8) { + sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEL), 0xFu << (gpio->pin * 4), gpio_mode << (gpio->pin * 4)); + } else { + sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEH), 0xFu << ((gpio->pin - 8) * 4), gpio_mode << ((gpio->pin - 8) * 4)); + } + + // SL_GPIO_MODE_DISABLED based on DOUT Value (low/high) act as two different configurations. + // By setting mode to disabled first and then modifying the DOUT value, so that + // previous mode configuration on given pin not effected. + if (mode == SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_hal_gpio_set_pin(gpio); + } else { + sl_hal_gpio_clear_pin(gpio); + } + } +} + +/***************************************************************************//** + * Get the mode for a GPIO pin. + ******************************************************************************/ +sl_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio) +{ + sl_gpio_mode_t mode = SL_GPIO_MODE_DISABLED; + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + + // Determine the current mode of the GPIO pin based on the pin number. + if (gpio->pin < 8) { + mode = (sl_gpio_mode_t) ((GPIO->P[gpio->port].MODEL >> (gpio->pin * 4)) & 0xF); + } else { + mode = (sl_gpio_mode_t) ((GPIO->P[gpio->port].MODEH >> ((gpio->pin - 8) * 4)) & 0xF); + } + + // Map the hardware-specific mode to the corresponding sl_gpio_mode_t value + switch (mode) { +#if defined(_GPIO_P_MODEL_MODE0_DISABLED) + case _GPIO_P_MODEL_MODE0_DISABLED: + return SL_GPIO_MODE_DISABLED; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUT) + case _GPIO_P_MODEL_MODE0_INPUT: + return SL_GPIO_MODE_INPUT; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULL) + case _GPIO_P_MODEL_MODE0_INPUTPULL: + return SL_GPIO_MODE_INPUT_PULL; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULLFILTER) + case _GPIO_P_MODEL_MODE0_INPUTPULLFILTER: + return SL_GPIO_MODE_INPUT_PULL_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULL) + case _GPIO_P_MODEL_MODE0_PUSHPULL: + return SL_GPIO_MODE_PUSH_PULL; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + case _GPIO_P_MODEL_MODE0_PUSHPULLALT: + return SL_GPIO_MODE_PUSH_PULL_ALTERNATE; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDOR) + case _GPIO_P_MODEL_MODE0_WIREDOR: + return SL_GPIO_MODE_WIRED_OR; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN) + case _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN: + return SL_GPIO_MODE_WIRED_OR_PULL_DOWN; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDAND) + case _GPIO_P_MODEL_MODE0_WIREDAND: + return SL_GPIO_MODE_WIRED_AND; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDFILTER: + return SL_GPIO_MODE_WIRED_AND_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUP) + case _GPIO_P_MODEL_MODE0_WIREDANDPULLUP: + return SL_GPIO_MODE_WIRED_AND_PULLUP; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER: + return SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + case _GPIO_P_MODEL_MODE0_WIREDANDALT: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP) + case _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER; +#endif + default: + EFM_ASSERT(false); + return mode; // returning the default state + } +} + +/***************************************************************************//** + * Configure the GPIO pin interrupt. + ******************************************************************************/ +int32_t sl_hal_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t int_no, + sl_gpio_interrupt_flag_t flags) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_GPIO_FLAG_IS_VALID(flags)); + EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); + + if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE && int_no >= 0) { + #if defined(_GPIO_EXTIPINSELL_MASK) + EFM_ASSERT(SL_HAL_GPIO_INTNO_PIN_VALID(int_no, gpio->pin)); + #endif + } + + #if !defined(_GPIO_EXTIPINSELL_MASK) + int_no = gpio->pin; + #endif + + if (int_no == SL_GPIO_INTERRUPT_UNAVAILABLE) { + uint32_t interrupts_enabled = sl_hal_gpio_get_enabled_interrupts(); + int_no = sl_hal_gpio_get_external_interrupt_number(gpio->pin, interrupts_enabled); + } + + if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE && int_no >= 0) { + if (int_no < 8) { + // The EXTIPSELL register controls pins 0-7 of the interrupt configuration. + #if defined(_GPIO_EXTIPSELL_EXTIPSEL0_MASK) + sl_hal_bus_reg_write_mask(&GPIO->EXTIPSELL, + _GPIO_EXTIPSELL_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * int_no), + (uint32_t)gpio->port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * int_no)); + #endif + // The EXTIPINSELL register controls interrupt 0-7 of the interrupt/pin number mapping. + #if defined(_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) + sl_hal_bus_reg_write_mask(&GPIO->EXTIPINSELL, + _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * int_no), + ((gpio->pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * int_no)); + #endif + } else { + // EXTIPSELH controls pins 8-15 of the interrupt configuration. + #if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) + uint32_t tmp = int_no - 8; + sl_hal_bus_reg_write_mask(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), + (uint32_t)gpio->port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); + #endif + // EXTIPINSELH controls interrupt 8-15 of the interrupt/pin number mapping. + #if defined(_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + sl_hal_bus_reg_write_mask(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), + ((gpio->pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); + #endif + } + + // Enable/disable rising edge interrupt. + (((flags & SL_GPIO_INTERRUPT_RISING_EDGE) == SL_GPIO_INTERRUPT_RISING_EDGE) + || ((flags & SL_GPIO_INTERRUPT_RISING_FALLING_EDGE) == SL_GPIO_INTERRUPT_RISING_FALLING_EDGE)) \ + ? sl_hal_bus_reg_write_bit(&(GPIO->EXTIRISE), int_no, true) \ + : sl_hal_bus_reg_write_bit(&(GPIO->EXTIRISE), int_no, false); + + // Enable/disable falling edge interrupt. + (((flags & SL_GPIO_INTERRUPT_FALLING_EDGE) == SL_GPIO_INTERRUPT_FALLING_EDGE) + || (flags & SL_GPIO_INTERRUPT_RISING_FALLING_EDGE) == SL_GPIO_INTERRUPT_RISING_FALLING_EDGE) \ + ? sl_hal_bus_reg_write_bit(&(GPIO->EXTIFALL), int_no, true) \ + : sl_hal_bus_reg_write_bit(&(GPIO->EXTIFALL), int_no, false); + + // Clear any pending interrupt. + sl_hal_gpio_clear_interrupts(1 << int_no); + } + + return int_no; +} + +/**************************************************************************//** + * Enable GPIO pin wake-up from EM4. When the function exits, + * EM4 mode can be safely entered. + *****************************************************************************/ +void sl_hal_gpio_enable_pin_em4_wakeup(uint32_t pinmask, + uint32_t polaritymask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); + EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); + + GPIO->EM4WUPOL &= ~pinmask; // Set the wakeup polarity. + GPIO->EM4WUPOL |= pinmask & polaritymask; + GPIO->EM4WUEN |= pinmask; // Enable wakeup. + + sl_hal_gpio_set_pin_em4_retention(true); // Enable the pin retention. + sl_hal_gpio_clear_interrupts(pinmask); // clear any pending interrupt. +} + +/***************************************************************************//** + * Configure EM4WU pins as external level-sensitive interrupts. + ******************************************************************************/ +int32_t sl_hal_gpio_configure_wakeup_em4_external_interrupt(const sl_gpio_t *gpio, + int32_t int_no, + bool polarity) +{ + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); + + int32_t em4_int_no = sl_hal_gpio_get_em4_interrupt_number(gpio); + + if (int_no == SL_GPIO_INTERRUPT_UNAVAILABLE) { + int_no = em4_int_no; + } + + if (em4_int_no == SL_GPIO_INTERRUPT_UNAVAILABLE || int_no != em4_int_no) { + return SL_GPIO_INTERRUPT_UNAVAILABLE; + } + + if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + // GPIO pin mode set. + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_INPUT_PULL_FILTER, (unsigned int)!polarity); + + // Enable EM4WU function and set polarity. + uint32_t polarityMask = (uint32_t)polarity << (int_no + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + uint32_t pinmask = 1UL << (int_no + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + + sl_hal_gpio_enable_pin_em4_wakeup(pinmask, polarityMask); + } + + return int_no; +} + +#endif /* defined(GPIO_PRESENT)*/ diff --git a/Libs/platform/peripheral/src/sl_hal_sysrtc.c b/Libs/platform/peripheral/src/sl_hal_sysrtc.c new file mode 100644 index 0000000..97bc929 --- /dev/null +++ b/Libs/platform/peripheral/src/sl_hal_sysrtc.c @@ -0,0 +1,1012 @@ +/***************************************************************************//** + * @file + * @brief System Real Time Counter (SYSRTC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_hal_sysrtc.h" +#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) +#include "sl_assert.h" +#include "stddef.h" + +/***************************************************************************//** + * @addtogroup sysrtc SYSRTC - System Real Time Counter + * @brief System Real Time Counter (SYSRTC) Peripheral API + * @details + * This module contains functions to control the SYSRTC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The SYSRTC ensures timekeeping in low energy modes. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +extern __INLINE void sl_hal_sysrtc_wait_sync(void); +extern __INLINE void sl_hal_sysrtc_wait_ready(void); +extern __INLINE void sl_hal_sysrtc_start(void); +extern __INLINE void sl_hal_sysrtc_stop(void); +extern __INLINE uint32_t sl_hal_sysrtc_get_status(void); +extern __INLINE void sl_hal_sysrtc_lock(void); +extern __INLINE void sl_hal_sysrtc_unlock(void); +extern __INLINE uint32_t sl_hal_sysrtc_get_counter(void); +extern __INLINE void sl_hal_sysrtc_set_counter(uint32_t value); + +/***************************************************************************//** + * Initializes SYSRTC module. + ******************************************************************************/ +void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config) +{ + // Wait to be ready + sl_hal_sysrtc_wait_ready(); + + if (SYSRTC0->EN == SYSRTC_EN_EN) { + // Disable the module + sl_hal_sysrtc_disable(); + // Wait to be ready + sl_hal_sysrtc_wait_ready(); + } + + // Set configuration + SYSRTC0->CFG = (p_config->enable_debug_run ? 1UL : 0UL) << _SYSRTC_CFG_DEBUGRUN_SHIFT; +} + +/***************************************************************************//** + * Enables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_enable(void) +{ + // Wait if disabling + sl_hal_sysrtc_wait_ready(); + + // Enable SYSRTC module + SYSRTC0->EN_SET = SYSRTC_EN_EN; + + // Start counter + SYSRTC0->CMD = SYSRTC_CMD_START; +} + +/***************************************************************************//** + * Disables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_disable(void) +{ + if (SYSRTC0->EN != SYSRTC_EN_EN) { + return; + } + + // Stop counter + sl_hal_sysrtc_stop(); + + // Disable module + SYSRTC0->EN_CLR = SYSRTC_EN_EN; +} + +/***************************************************************************//** + * Restores SYSRTC to its reset state. + ******************************************************************************/ +void sl_hal_sysrtc_reset(void) +{ + // Reset timer + SYSRTC0->SWRST = SYSRTC_SWRST_SWRST; +} + +/***************************************************************************//** + * Initializes the selected SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_init_group(uint8_t group_number, + sl_hal_sysrtc_group_config_t const *p_group_config) +{ + uint32_t temp = 0; + + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT); + if (p_group_config->p_compare_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT); + } + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT); + if (p_group_config->p_compare_channel1_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); + } +#endif +#ifdef SYSRTC_GRP0_CTRL_CAP0EN + temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT); + if (p_group_config->p_capture_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); + } +#endif + SYSRTC0->GRP0_CTRL = temp; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP0EN_SHIFT); + if (p_group_config->p_compare_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP0CMOA_SHIFT); + } +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP1EN_SHIFT); + if (p_group_config->p_compare_channel1_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP1CMOA_SHIFT); + } +#endif +#ifdef SYSRTC_GRP1_CTRL_CAP0EN + temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CAP0EN_SHIFT); + if (p_group_config->p_capture_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP1_CTRL_CAP0EDGE_SHIFT); + } +#endif + SYSRTC0->GRP1_CTRL = temp; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: +// SYSRTC0->GRP2_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP0EN_SHIFT) +// | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + SYSRTC0->GRP2_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP2_CTRL_CAP0EN + SYSRTC0->GRP2_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP2_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + SYSRTC0->GRP3_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP3_CTRL_CAP0EN + SYSRTC0->GRP3_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP3_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + SYSRTC0->GRP4_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP4_CTRL_CAP0EN + SYSRTC0->GRP4_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP4_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + SYSRTC0->GRP5_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP5_CTRL_CAP0EN + SYSRTC0->GRP5_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP5_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + SYSRTC0->GRP6_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP6_CTRL_CAP0EN + SYSRTC0->GRP6_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP6_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + SYSRTC0->GRP7_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP7_CTRL_CAP0EN + SYSRTC0->GRP7_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP7_CTRL_CAP0EDGE_SHIFT); +#endif + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Enables one or more SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IEN_SET = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Disables one or more SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IEN_CLR = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Clears one or more pending SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IF_CLR = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets pending SYSRTC interrupt flags for the given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + return SYSRTC0->GRP0_IF; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + return SYSRTC0->GRP1_IF; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + return SYSRTC0->GRP2_IF; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + return SYSRTC0->GRP3_IF; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + return SYSRTC0->GRP4_IF; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + return SYSRTC0->GRP5_IF; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + return SYSRTC0->GRP6_IF; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + return SYSRTC0->GRP7_IF; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Gets enabled and pending SYSRTC interrupt flags. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number) +{ + uint32_t ien = 0; + + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + ien = SYSRTC0->GRP0_IEN; + return SYSRTC0->GRP0_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + ien = SYSRTC0->GRP1_IEN; + return SYSRTC0->GRP1_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + ien = SYSRTC0->GRP2_IEN; + return SYSRTC0->GRP2_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + ien = SYSRTC0->GRP3_IEN; + return SYSRTC0->GRP3_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + ien = SYSRTC0->GRP4_IEN; + return SYSRTC0->GRP4_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + ien = SYSRTC0->GRP5_IEN; + return SYSRTC0->GRP5_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + ien = SYSRTC0->GRP6_IEN; + return SYSRTC0->GRP6_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + ien = SYSRTC0->GRP7_IEN; + return SYSRTC0->GRP7_IF & ien; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Sets one or more pending SYSRTC interrupts for the given group from Software. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IF_SET = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets SYSRTC compare register value for selected channel of given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, + uint8_t channel) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + switch (channel) { + case 0: + return SYSRTC0->GRP0_CMP0VALUE; + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP0_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + switch (channel) { + case 0: + return SYSRTC0->GRP1_CMP0VALUE; + +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP1_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + switch (channel) { + case 0: + return SYSRTC0->GRP2_CMP0VALUE; + +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP2_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + switch (channel) { + case 0: + return SYSRTC0->GRP3_CMP0VALUE; + +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP3_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + switch (channel) { + case 0: + return SYSRTC0->GRP4_CMP0VALUE; + +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP4_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + switch (channel) { + case 0: + return SYSRTC0->GRP5_CMP0VALUE; + +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP5_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + switch (channel) { + case 0: + return SYSRTC0->GRP6_CMP0VALUE; + +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP6_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + switch (channel) { + case 0: + return SYSRTC0->GRP7_CMP0VALUE; + +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP7_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Sets SYSRTC compare register value for selected channel of given group. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, + uint8_t channel, + uint32_t value) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + switch (channel) { + case 0: + SYSRTC0->GRP0_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + case 1: + SYSRTC0->GRP0_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + switch (channel) { + case 0: + SYSRTC0->GRP1_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + case 1: + SYSRTC0->GRP1_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + switch (channel) { + case 0: + SYSRTC0->GRP2_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + case 1: + SYSRTC0->GRP2_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + switch (channel) { + case 0: + SYSRTC0->GRP3_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + case 1: + SYSRTC0->GRP3_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + switch (channel) { + case 0: + SYSRTC0->GRP4_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + case 1: + SYSRTC0->GRP4_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + switch (channel) { + case 0: + SYSRTC0->GRP5_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + case 1: + SYSRTC0->GRP5_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + switch (channel) { + case 0: + SYSRTC0->GRP6_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + case 1: + SYSRTC0->GRP6_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + switch (channel) { + case 0: + SYSRTC0->GRP7_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + case 1: + SYSRTC0->GRP7_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets SYSRTC input capture register value for selected channel of given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { +#ifdef SYSRTC_GRP0_CTRL_CAP0EN + case 0: + return SYSRTC0->GRP0_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 1 +#ifdef SYSRTC_GRP1_CTRL_CAP0EN + case 1: + return SYSRTC0->GRP1_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 2 +#ifdef SYSRTC_GRP2_CTRL_CAP0EN + case 2: + return SYSRTC0->GRP2_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 3 +#ifdef SYSRTC_GRP3_CTRL_CAP0EN + case 3: + return SYSRTC0->GRP3_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 4 +#ifdef SYSRTC_GRP4_CTRL_CAP0EN + case 4: + return SYSRTC0->GRP4_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 5 +#ifdef SYSRTC_GRP5_CTRL_CAP0EN + case 5: + return SYSRTC0->GRP5_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 6 +#ifdef SYSRTC_GRP6_CTRL_CAP0EN + case 6: + return SYSRTC0->GRP6_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 7 +#ifdef SYSRTC_GRP7_CTRL_CAP0EN + case 7: + return SYSRTC0->GRP7_CAP0VALUE; +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/** @} (end addtogroup sysrtc) */ +#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ diff --git a/Libs/platform/peripheral/src/sl_hal_system.c b/Libs/platform/peripheral/src/sl_hal_system.c new file mode 100644 index 0000000..d2f0852 --- /dev/null +++ b/Libs/platform/peripheral/src/sl_hal_system.c @@ -0,0 +1,662 @@ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_hal_system.h" +#include "sl_hal_syscfg.h" +#include "em_device.h" +#include +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +#include "sl_se_manager.h" +#include "sli_se_manager_device_data.h" +#endif +#include "sl_status.h" +#include "sl_assert.h" +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** DEFINES ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Bit mask used to extract the part number value without the new naming + * bitfield. */ +#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 +#define SYSCFG_CHIPREV_PARTNUMBER0 0xF + +/** @endcond */ + +#define HFRCO_DPLL_FREQUENCY_TABLE_SIZE 11 + +#define DEVINFO_TEMPERATURE_CALTEMP_INTEGER_SHIFT 4 + +/******************************************************************************* + ******************************* TYPEDEF *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +typedef struct hfrco_dpll_cal_element { + uint32_t min_freq; + uint32_t max_freq; +} hfrco_dpll_cal_element_t; +#endif + +/******************************************************************************* + ****************************** CONSTANTS ********************************** + ******************************************************************************/ +const sl_hal_system_devinfo_adc_t SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES = { + .cal_data = { + .trim_vros0 = 0, + .trim_vros1 = 0, + .trim_gain_4x = 0, + .trim_gain_0x3_int = 0 + }, + .offset = { + .trim_off_1x = 0, + .trim_off_2x = 0, + .trim_off_4x = 0 + } +}; + +const sl_hal_system_devinfo_temperature_t SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES = { + .emu_temp_room = 0, + .cal_temp = 0 +}; + +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +static const hfrco_dpll_cal_element_t HFRCO_DPLL_FREQUENCY_TABLE[HFRCO_DPLL_FREQUENCY_TABLE_SIZE] = { + { .min_freq = 16000000, .max_freq = 20000000 }, // 18MHz calibration central frequency + { .min_freq = 20000000, .max_freq = 24500000 }, // 22MHz calibration central frequency + { .min_freq = 24500000, .max_freq = 30000000 }, // 27MHz calibration central frequency + { .min_freq = 30000000, .max_freq = 36000000 }, // 33MHz calibration central frequency + { .min_freq = 36000000, .max_freq = 42500000 }, // 39MHz calibration central frequency + { .min_freq = 42500000, .max_freq = 50500000 }, // 46MHz calibration central frequency + { .min_freq = 50500000, .max_freq = 60000000 }, // 55MHz calibration central frequency + { .min_freq = 60000000, .max_freq = 70000000 }, // 65MHz calibration central frequency + { .min_freq = 70000000, .max_freq = 80000000 }, // 75MHz calibration central frequency + { .min_freq = 80000000, .max_freq = 90000000 }, // 85MHz calibration central frequency + { .min_freq = 90000000, .max_freq = 100000000 } // 95MHz calibration central frequency +}; +#endif + +/******************************************************************************* + ****************************** UTILITY ************************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief Get the nth ASCII character of a specified number. + * + * @param[in] input_number + * The number where the digit will be taken. + * + * @param[in] position + * The digit position. + * + * @return + * The ASCII value of the specified digit. + ******************************************************************************/ +char sli_get_n_digit(uint16_t input_number, uint8_t position) +{ + uint32_t exp[] = { 10, 100, 1000, 10000, 100000 }; + uint32_t number = input_number; + + if (position > 4) { + EFM_ASSERT(false); + return '0'; + } + + number = (number % exp[position]); + + if (position != 0) { + number = number / (exp[position - 1]); + } + + return (char)number + '0'; +} +#endif + +#if defined(_DEVINFO_PART0_DIECODE0_MASK) && defined(_SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief Convert hexadecimal ASCII character to integer value. + * + * @param[in] character + * The character to be coverted to a number. + * + * @return + * The uint8_t value of the character given in parameter. + ******************************************************************************/ +uint8_t sli_hex_ascii_to_value(char character) +{ + if (character >= '0' && character <= '9') { + return character - '0'; + } else if (character >= 'A' && character <= 'F') { + return character - 'A'; + } + + return 0U; +} +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/******************************************************************************* + * @brief Get CHIPREV register. + ******************************************************************************/ +void sl_hal_system_get_chip_revision(sl_hal_system_chip_revision_t *rev) +{ +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + uint32_t chip_rev = sl_hal_syscfg_read_chip_rev(); + + rev->minor = (chip_rev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; + rev->major = (chip_rev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + rev->part_number = ((chip_rev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chip_rev & SYSCFG_CHIPREV_PARTNUMBER0); + rev->family = (uint16_t)0xFFFF; +#elif defined(_SYSCFG_CHIPREV_FAMILY_MASK) + rev->part_number = (uint16_t)0xFFFF; + rev->family = (chip_rev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; +#else + #error No Chip Revision Part Number or Family +#endif +} + +/***************************************************************************//** + * @brief Get the MCU family identifier. + ******************************************************************************/ +sl_hal_system_part_family_t sl_hal_system_get_family(void) +{ +#if defined(_DEVINFO_PART_FAMILY_MASK) + return (DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK + | _DEVINFO_PART_FAMILYNUM_MASK)); +#else + return (DEVINFO->PART0 & (_DEVINFO_PART0_PROTOCOL_MASK + | _DEVINFO_PART0_SERIES_MASK + | _DEVINFO_PART0_DIECODE0_MASK)); +#endif +} + +/***************************************************************************//** + * @brief Get DEVINFO revision. + ******************************************************************************/ +uint8_t sl_hal_system_get_devinfo_rev(void) +{ +#if defined(_DEVINFO_INFO_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) + >> _DEVINFO_INFO_DEVINFOREV_SHIFT); +#elif defined(_DEVINFO_REVISION_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->REVISION & _DEVINFO_REVISION_DEVINFOREV_MASK) + >> _DEVINFO_REVISION_DEVINFOREV_SHIFT); +#else +#error (sl_hal_system.c): Location of devinfo revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the default factory calibration value for HFRCO oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_default_calibration(void) +{ +#if defined(_DEVINFO_HFRCOCALDEFAULT_MASK) + return DEVINFO->HFRCOCALDEFAULT; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get the speed factory calibration value for HFRCO oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_speed_calibration(void) +{ +#if defined(_DEVINFO_HFRCOCALSPEED_MASK) + return DEVINFO->HFRCOCALSPEED; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get the HFRCO calibration based on the frequency band. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + uint8_t band_index = 0xFF; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset; + uint32_t calibration_value = 0; + + for (uint8_t i = 0; i < HFRCO_DPLL_FREQUENCY_TABLE_SIZE; i++) { + if ((frequency >= HFRCO_DPLL_FREQUENCY_TABLE[i].min_freq) + && (frequency <= HFRCO_DPLL_FREQUENCY_TABLE[i].max_freq)) { + band_index = i; + break; + } + } + + if (band_index >= HFRCO_DPLL_FREQUENCY_TABLE_SIZE) { + return 0; + } + + // Calculate memory offset based on the band index we want. + offset = (band_index * 4) + DEVINFO_GP_HFRCODPLLBAND0_OFFSET; + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + return 0; + } + + // Send the SE command to retrieve the HFRCODPLL calibration for a given band from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, &calibration_value); + if (status != SL_STATUS_OK) { + return 0; + } + + return calibration_value; +#else + (void)frequency; + return 0; +#endif +} + +/***************************************************************************//** + * Get a factory calibration value for HFRCOCEM23 oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcoem23_calibration(uint32_t frequency) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset; + uint32_t calibration_value = 0; + + // Determine offset based on HFRCOEM23 frequency. + if (frequency == 40000000UL) { +#if defined(DEVINFO_GP_HFRCOEM2340MHZ_OFFSET) + offset = DEVINFO_GP_HFRCOEM2340MHZ_OFFSET; +#else + // Default to 20Mhz. + offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; +#endif + } else { + offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; + } + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + return 0; + } + + // Send the SE command to retrieve the HFRCOEM23 calibration from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, &calibration_value); + if (status != SL_STATUS_OK) { + return 0; + } + + return calibration_value; +#else + (void)frequency; + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get a factory calibration value for HFXOCAL. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfxocal(void) +{ +#if defined(_DEVINFO_HFXOCAL_MASK) + return DEVINFO->HFXOCAL; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get family security capability. + ******************************************************************************/ +sl_hal_system_security_capability_t sl_hal_system_get_security_capability(void) +{ + sl_hal_system_security_capability_t sc = SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN; + + uint16_t mcu_feature_set_major; + uint16_t device_number; + device_number = sl_hal_system_get_part_number(); + mcu_feature_set_major = 'A' + (device_number / 1000); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" + mcu_feature_set_major = 'C'; +#endif + + switch (mcu_feature_set_major) { + case 'A': + sc = SL_SYSTEM_SECURITY_CAPABILITY_SE; + break; + + case 'B': + sc = SL_SYSTEM_SECURITY_CAPABILITY_VAULT; + break; + + case 'C': + sc = SL_SYSTEM_SECURITY_CAPABILITY_ROT; + break; + + default: + sc = SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN; + break; + } + + return sc; +} + +/***************************************************************************//** + * @brief Get the unique number for this device. + ******************************************************************************/ +uint64_t sl_hal_system_get_unique(void) +{ + uint32_t tmp = DEVINFO->EUI64L; + return ((uint64_t)DEVINFO->EUI64H << 32) | tmp; +} + +/***************************************************************************//** + * @brief Get the production revision for this part. + ******************************************************************************/ +uint8_t sl_hal_system_get_prod_rev(void) +{ +#if defined(_DEVINFO_INFO_PRODREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) + >> _DEVINFO_INFO_PRODREV_SHIFT); +#elif defined(_DEVINFO_REVISION_PRODREV_MASK) + return (uint8_t)((DEVINFO->REVISION & _DEVINFO_REVISION_PRODREV_MASK) + >> _DEVINFO_REVISION_PRODREV_SHIFT); +#else +#error (sl_hal_system.c): Location of production revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the SRAM Base Address. + ******************************************************************************/ +uint32_t sl_hal_system_get_sram_base_address(void) +{ + return SRAM_BASE; +} + +/***************************************************************************//** + * @brief Get the SRAM size (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_sram_size(void) +{ +#if defined(_DEVINFO_MSIZE_SRAM_MASK) + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT); +#elif defined(_DEVINFO_EMBSIZE_RAM_MASK) + return (uint16_t)((DEVINFO->EMBSIZE & _DEVINFO_EMBSIZE_RAM_MASK) + >> _DEVINFO_EMBSIZE_RAM_SHIFT); +#else + #error (sl_hal_system.c): Location of SRAM Size is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the flash size (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_flash_size(void) +{ +#if defined(_DEVINFO_MSIZE_FLASH_MASK) + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT); +#elif defined(_DEVINFO_STACKMSIZE_FLASH_MASK) + uint16_t stacked_flach_size = (uint16_t)((DEVINFO->STACKMSIZE & _DEVINFO_STACKMSIZE_FLASH_MASK) + >> _DEVINFO_STACKMSIZE_FLASH_SHIFT); + + if (stacked_flach_size == 0) { + // Defined in linker script for external flash provided by customers. + extern uint32_t __flash_size__; + // Get flash size in kB. + stacked_flach_size = (uint16_t)(uintptr_t)&__flash_size__ / 1024; + } + + return stacked_flach_size; +#endif +} + +/***************************************************************************//** + * @brief Get the flash page size in bytes. + ******************************************************************************/ +uint32_t sl_hal_system_get_flash_page_size(void) +{ +#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + uint32_t tmp; + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; + return 1UL << ((tmp + 10UL) & 0x1FUL); +#else + // Defined in linker script for external flash provided by customers. + extern uint32_t __flash_page_size__; + return (uintptr_t)&__flash_page_size__; +#endif +} + +/***************************************************************************//** + * @brief Get the MCU part number. + ******************************************************************************/ +uint16_t sl_hal_system_get_part_number(void) +{ +#if defined(_DEVINFO_PART_DEVICENUM_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) + >> _DEVINFO_PART_DEVICENUM_SHIFT); +#elif defined(_DEVINFO_PART0_DIECODE0_MASK) && defined(_SILICON_LABS_SECURITY_FEATURE_VAULT) + // Encode features to the series 2 format. + // Add security level vault high for SIxG301. + uint16_t device_number = 1000; + uint32_t register_value = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE1_MASK) >> _DEVINFO_PART1_FEATURE1_SHIFT; + + device_number = sli_hex_ascii_to_value((char)register_value) * 100; + + register_value = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE2_MASK) >> _DEVINFO_PART1_FEATURE2_SHIFT; + device_number += sli_hex_ascii_to_value((char)register_value) * 10; + + register_value = (DEVINFO->PART2 & _DEVINFO_PART2_FEATURE3_MASK) >> _DEVINFO_PART2_FEATURE3_SHIFT; + device_number += sli_hex_ascii_to_value((char)register_value); + + return device_number; +#else +#error (em_system.c): Location of device part number is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the SoC or MCU features. + ******************************************************************************/ +sl_hal_system_features_t sl_hal_system_get_part_features(void) +{ + sl_hal_system_features_t part_features = { .feature1 = '0', .feature2 = '0', .feature3 = '0' }; + +#if defined(_SILICON_LABS_32B_SERIES_2) + uint16_t device_number = ((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) >> _DEVINFO_PART_DEVICENUM_SHIFT); + + part_features.feature1 = sli_get_n_digit(device_number, 2); + part_features.feature2 = sli_get_n_digit(device_number, 1); + part_features.feature3 = sli_get_n_digit(device_number, 0); + +#elif defined(_SILICON_LABS_32B_SERIES_3) + + part_features.feature1 = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE1_MASK) >> _DEVINFO_PART1_FEATURE1_SHIFT; + part_features.feature2 = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE2_MASK) >> _DEVINFO_PART1_FEATURE2_SHIFT; + part_features.feature3 = (DEVINFO->PART2 & _DEVINFO_PART2_FEATURE3_MASK) >> _DEVINFO_PART2_FEATURE3_SHIFT; + +#else +#error Not defined for this die. +#endif + + return part_features; +} + +/***************************************************************************//** + * @brief Get the temperature information. + ******************************************************************************/ +void sl_hal_system_get_temperature_info(sl_hal_system_devinfo_temperature_t *info) +{ +#if defined(_DEVINFO_CALTEMP_MASK) || defined(_DEVINFO_EMUTEMP_MASK) +#if defined(_DEVINFO_CALTEMP_TEMP_MASK) + info->cal_temp = ((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) + >> _DEVINFO_CALTEMP_TEMP_SHIFT); +#else + info->cal_temp = 0; +#endif +#if defined(_DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) + info->emu_temp_room = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) + >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); +#else + info->emu_temp_room = 0; +#endif +#elif defined (_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset = DEVINFO_GP_TEMPERATURE_OFFSET; + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + return; + } + + // Send the SE command to retrieve the temperature information from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, (uint32_t*)info); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + return; + } + + // Divide the temperature by 16 to retrieve only the integer part of the temperature value. + info->cal_temp = info->cal_temp >> DEVINFO_TEMPERATURE_CALTEMP_INTEGER_SHIFT; +#else + (void)info; +#endif +} + +/******************************************************************************* + * @brief Reads CHIPREV register. + ******************************************************************************/ +uint32_t sl_hal_syscfg_read_chip_rev(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_chiprev_register(); +#else + return SYSCFG->CHIPREV; +#endif +} + +/******************************************************************************* + * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one. + ******************************************************************************/ +void sl_hal_syscfg_set_systicextclken_cfgsystic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +/******************************************************************************* + * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero. + ******************************************************************************/ +void sl_hal_syscfg_clear_systicextclken_cfgsystic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/***************************************************************************//** + * @brief Set floating point co-processor (FPU) access mode. + ******************************************************************************/ +void sl_hal_system_fpu_set_access_mode(sl_hal_system_fpu_access_t access_mode) +{ + SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | access_mode; +} +#endif + +/***************************************************************************//** + * @brief Get the ADC calibration info. + ******************************************************************************/ +void sl_hal_system_get_adc_calibration_info(sl_hal_system_devinfo_adc_t *info) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset = DEVINFO_GP_ADC0CALDATA_OFFSET; + EFM_ASSERT(info != NULL); + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + return; + } + + // Send the SE command to retrieve the ADC calibration from the DEVINFO OTP section + status = sli_se_device_data_read_chunk(&se_command_ctx, + otp_section_id, + offset, + sizeof(sl_hal_system_devinfo_adc_offset_t), + info); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + return; + } +#else + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; +#endif +} + +/** @} (end addtogroup system) */ diff --git a/Libs/platform/service/clock_manager/inc/sl_clock_manager.h b/Libs/platform/service/clock_manager/inc/sl_clock_manager.h new file mode 100644 index 0000000..e2eb053 --- /dev/null +++ b/Libs/platform/service/clock_manager/inc/sl_clock_manager.h @@ -0,0 +1,661 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager APIs. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_H +#define SL_CLOCK_MANAGER_H + +#include +#include +#include "sl_status.h" +#include "sl_enum.h" +#include "sl_device_clock.h" +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup clock_manager Clock Manager + * + * @details + * ## Overview + * + * Clock Manager is a platform-level software module that manages + * the device's oscillators and clock tree. + * The Clock Manager module is split into two main parts: The Initialization part + * and the Runtime part. The runtime part has its component + * \a clock_manager_runtime and can be used independently from the initialization + * part. The \a clock_manager component includes both the initialization part and the + * runtime part and it should be the component added to your project slcp file. + * + * ## Initialization + * The initialization part includes the configuration files + * \a sl_clock_manager_oscillator_config.h and \a sl_clock_manager_tree_config.h. + * As their name indicates, those C header files are used to configure the different + * device oscillators and the device clock tree. Those header files use the CMSIS + * Configuration Wizard Annotations and are specific to each device. + * The API function sl_clock_manager_init() is used to initialize the Clock Manager + * module based on the configuration values specified in the two configuration files. + * This function must be called early during your initialization sequence. + * If the SL System component (@ref system) is used by your application, the + * sl_clock_manager_init() call will be added automatically to your initialization + * sequence. + * + * ### Oscillators Configuration + * Oscillators' configurations are all grouped in the \a sl_clock_manager_oscillator_config.h + * file. Crystal-based oscillators, HFXO and LFXO, have an enable/disable configuration to + * indicate if the required crystal is present or not. In the absence of the required + * crystal, the configuration must be disabled and the associated oscillator will + * not be initialized. + * + * The HFXO configuration also provides the configuration for the Crystal Sharing + * feature when supported by the device. This feature allows to use the dedicated + * HFCLKOUT pin to output a sinusoidal clock that can be used as the HFXO + * input for another EFR device. In the configuration, you need to specify if your + * device is the leader or the follower. The leader will be the one outputting the + * clock and the follower, the one receiving the clock signal. In the leader configuration, + * the GPIO pin is used to receive the request from the follower. You can refer to your + * device datasheet to know the available location for the HFXO BUFOUT_REQ pin. + * In the follower mode, the pin configuration can be used to send an HFXO request + * signal to the leader. The "High Frequency Clock Ouput" section of your device + * reference manual also provides more details about this feature. + * + * The first HFRCO module, whose output clock is called HFRCODPLL, can be connected to + * the DPLL module to have a better precision clock. When the DPLL is enabled through + * the configuration define \a SL_CLOCK_MANAGER_HFRCO_DPLL_EN, the DPLL settings + * take precedence over the HFRCO band configuration. + * + * ### Clock Tree Configuration + * The device clock tree configurations are all grouped in the + * \a sl_clock_manager_tree_config.h file. Refer to your device's reference manual for + * the clock tree diagram and see which peripherals are connected to which clock branches. + * In the configuration file, each clock branch can be independently configured. + * However, to facilitate the clock setup for users, two additional configurations + * were added: \a SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE and + * \a SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE. Those configurations allow the selection + * of the default high-frequency and low-frequency oscillators to be used inside the clock + * tree. Every clock branch that can benefit from those default selections will use them + * by default. + * On certain devices, the @ref power_manager module offers an Execution Modes feature + * with the \a SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN configuration. When this feature + * is enabled, the \a SL_CLOCK_MANAGER_SYSCLK_SOURCE configuration could be overriden by the + * Execution Modes feature. Refer to the description of \a SL_CLOCK_MANAGER_SYSCLK_SOURCE in + * \a sl_clock_manager_tree_config.h file to know if this is the case. + * + * Some peripherals have an internal clock divider. Those are not handled by the + * Clock Manager configuration. The peripheral driver will usually expose the divider + * configuration when such a divider is present inside the peripheral module. + * + * The Clock tree configuration is available at compile-time only. The Clock Manager + * module does not offer API functions to manipulate the clock tree at runtime. + * + * The more oscillators are used by different clock branches the more power + * consumption you will have. To limit your power consumption, you can try to limit the + * number of oscillators used. So for example, only use one High-frequency oscillator + * and one Low-frequency oscillator across the clock tree. However, if the + * application is radio-based, the HFXO oscillator is mandatory for the Radio + * clock branch and if the Radio clock branch is connected to the SYSCLK branch, + * this will limit you to use HFXO for SYSCLK as well. In this specific case, SYSCLK + * could also be configured to use HFRCO with DPLL, but the chosen frequency must be two + * times the HFXO frequency so that the Radio module can retrieve the HF crystal frequency + * with its divider. This will also come with an increase in power consumption since both + * HFXO and HFRCO oscillators will be used. Refer to your device reference manual to know + * if your Radio clock is connected to the SYSCLK clock branch or not. + * + * @note The Clock Manager Initialization is incompatible with the \a device_init_clocks + * (@ref device_init_clocks), \a device_init_hfxo (@ref device_init_hfxo), + * \a device_init_hfrco (@ref device_init_hfrco) \a device_init_dpll (@ref device_init_dpll), + * \a device_init_rffpll (@ref device_init_rffpll), \a device_init_usbpll (@ref device_init_usbpll), + * \a device_init_lfxo (@ref device_init_lfxo) and \a device_init_lfrco (@ref device_init_lfrco) + * components. + * This does not mean that the \a device_init component (@ref device_init) is incompatible with the + * \a clock_manager component. The \a device_init component can pull other initialization + * modules like EMU and DCDC that are not related to clocks. Therefore, both + * \a device_init and \a clock_manager should be present in your project file. SLC will + * take care of pulling only the sub \a device_init_xxx components that are needed. + * + * The runtime part, which is associated with the \a clock_manager_runtime component, + * has also an initialization function of its own, sl_clock_manager_runtime_init(). + * This function must also be part of the initialization sequence. If the SL System + * component (@ref system) is used by your application, the + * sl_clock_manager_runtime_init() call will be added automatically to your + * initialization sequence. + * + * ## Functionalities + * The Runtime part includes functionalities related to oscillators, clock tree + * and the CMU hardware module features. The main functionalities are: + * - Retrieving the frequency or precision of an oscillator or clock branch + * - Enabling/Disabling modules' bus clock + * - Retrieving or setting calibration values for oscillators + * - Exporting clocks to GPIO + * - Starting an RCO Calibration process based on a reference clock source + * + * ### Retrieve the frequency or precision of an oscillator or clock branch + * API functions sl_clock_manager_get_oscillator_frequency() and + * sl_clock_manager_get_oscillator_precision() allow retrieving respectively + * the frequency and precision of a given oscillator. Similar functions + * exist for clock branches: sl_clock_manager_get_clock_branch_frequency() and + * sl_clock_manager_get_clock_branch_precision(). + * + * To retrieve the frequency or precision of a specific peripheral, you will + * first need to retrieve to which clock branch this peripheral is connected. + * To do so, the Device Manager and its @ref device_peripheral + * can be used. The below code example shows how to retrieve the clock branch + * of the TIMER0 peripheral. + * + * @code{.c} + * #include "sl_clock_manager.h" + * #include "sl_device_peripheral.h" + * + * sl_status_t status; + * uint32_t freq; + * sl_clock_branch_t clock_branch; + * + * clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_TIMER0); + * status = sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq); + * @endcode + * + * ### Enable/Disable modules' bus clock + * Before accessing a peripheral's register interface, its bus clock must be enabled, + * or else a bus fault exception will be triggered. API functions + * sl_clock_manager_enable_bus_clock() and sl_clock_manager_disable_bus_clock() + * allow to perform such operations. + * + * Note that the peripheral clock will automatically be enabled when a peripheral + * is enabled with the clock on-demand feature. + * + * ### Oscillator Calibration + * The Clock Manager initialization, if present, will calibrate the different + * oscillators during the initialization sequence, but sometimes calibration + * values must be updated during runtime in certain conditions, for example, if + * the device temperature changes too much. This is considered an advanced + * functionality and users must be careful as to when to use this functionality. + * + * API functions sl_clock_manager_set_rc_oscillator_calibration() and + * sl_clock_manager_get_rc_oscillator_calibration() allow to set or get the + * CAL register of HFRCO and LFRCO oscillators. Not all devices have an LFRCO + * module with a CAL register. Some LFRCO modules will have a high-precision + * configuration allowing to use the HFXO to auto-calibrate the LFRCO. Refer + * to your device reference manual to retrieve oscillator specifications. + * + * API functions sl_clock_manager_set_hfxo_calibration() and + * sl_clock_manager_get_hfxo_calibration() allow to set or get the \a COREBIASANA + * inside the HFXO \a XTALCTRL register. The HFXO module has a Core Bias Optimization + * stage at the end of the oscillator startup sequence that allows to further + * optimize current consumption. This optimization will automatically set the + * \a COREBIASANA bitfield when finished. Upon reset, this optimization will run + * the first time HFXO is started and afterwards, the \a XTALCTRL->SKIPCOREBIASOPT + * bit will automatically be set so that next time HFXO is started during the + * application lifetime, the optimization stage will be skipped. This optimization + * stage takes a while to run, in the order of hundreds of milliseconds, therefore + * we don't want it to run each time HFXO is started. + * With the function sl_clock_manager_set_hfxo_calibration() it is possible to + * manually set the \a COREBIASANA bitfield and set the \a SKIPCOREBIASOPT bit. + * This function will usually be used in the context of an EM4 wake-up where to + * save on the initialization sequence time, we want to skip the Core Bias Optimization + * stage and manually set the value that would have previously been retrieved with + * sl_clock_manager_get_hfxo_calibration() and saved in an EM4 retained memory. + * In this context, sl_clock_manager_set_hfxo_calibration() will need to be called + * early in the initialization sequence, before the usual clock initialization + * function. + * + * slx_clock_manager_hfxo_set_ctune(), slx_clock_manager_hfxo_get_ctune() and + * slx_clock_manager_hfxo_calibrate_ctune() functions allow to manipulate the + * HFXO tuning capacitances. Changing the CTUNE value while HFXO is running + * can result in significant clock glitches for one clock period. Therefore, + * those functions should be used with caution. The difference between the + * slx_clock_manager_hfxo_set_ctune() and slx_clock_manager_hfxo_calibrate_ctune() + * functions is that the calibration one will also start and wait for the HFXO + * Core Bias Optimization stage to complete. + * + * API functions sl_clock_manager_set_lfxo_calibration() and + * sl_clock_manager_get_lfxo_calibration() allow to set and get the LFXO CTUNE + * value. + * + * ### Export clocks to GPIO + * The CMU module offers the functionality to export a given clock source to a + * GPIO pin. Refer to function sl_clock_manager_set_gpio_clock_output() for more + * details and the #sl_clock_manager_export_clock_source_t enum for a list of + * acceptable clock sources. Note that there is a specific clock branch named + * EXPCLK that is usually connected to the SYSCLK and offers an additional divider. + * + * ### RCO Calibration + * The CMU module also offers RCO Calibration hardware support. This can be + * used to calibrate at runtime HFRCO and LFRCO oscillators using a high-precision + * reference clock. Refer to your device reference manual for more + * details about this functionality. API function + * sl_clock_manager_configure_rco_calibration() can be used to configure the + * calibration process. Then sl_clock_manager_start_rco_calibration() and + * sl_clock_manager_stop_rco_calibration() can be called to start/stop the + * process. sl_clock_manager_wait_rco_calibration() function can be called to + * actively wait for the process to finish. And finally, + * sl_clock_manager_get_rco_calibration_count() can be called to retrieve the + * calibration process result. + * + * @{ + ******************************************************************************/ + +/// Export clock source. +/// This is to be used with the sl_clock_manager_set_gpio_clock_output() API function. +SL_ENUM(sl_clock_manager_export_clock_source_t) { + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_DISABLED, ///< Export Clock Source Disabled + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_FSRCO, ///< Export Clock Source FSRCO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFXO, ///< Export Clock Source HFXO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFRCODPLL, ///< Export Clock Source HFRCODPLL + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFRCOEM23, ///< Export Clock Source HFRCOEM23 + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFEXPCLK, ///< Export Clock Source HFEXPCLK + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_LFXO, ///< Export Clock Source LFXO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_PLFRCO, ///< Export Clock Source PLFRCO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_LFRCO, ///< Export Clock Source LFRCO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_ULFRCO, ///< Export Clock Source ULFRCO + SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HCLK, ///< Export Clock Source HCLK +}; + +/// Export clock output selection. +/// This is to be used with the sl_clock_manager_set_gpio_clock_output() API function. +SL_ENUM(sl_clock_manager_export_clock_output_select_t) { + SL_CLOCK_MANAGER_EXPORT_CLOCK_OUTPUT_SELECT_0 = 0, ///< Export Clock Output #0 + SL_CLOCK_MANAGER_EXPORT_CLOCK_OUTPUT_SELECT_1, ///< Export Clock Output #1 + SL_CLOCK_MANAGER_EXPORT_CLOCK_OUTPUT_SELECT_2, ///< Export Clock Output #2 +}; + +/// Clocks available for Calibration. +/// This is to be used with the sl_clock_manager_configure_rco_calibration() API function. +SL_ENUM(sl_clock_manager_clock_calibration_t) { + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HCLK, ///< Clock Calibration HCLK + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_PRS, ///< Clock Calibration PRS + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFXO, ///< Clock Calibration HFXO + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFXO, ///< Clock Calibration LFXO + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCODPLL, ///< Clock Calibration HFRCODPLL + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCOEM23, ///< Clock Calibration HFRCOEM23 + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_FSRCO, ///< Clock Calibration FSRCO + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFRCO, ///< Clock Calibration LFRCO + SL_CLOCK_MANAGER_CLOCK_CALIBRATION_ULFRCO ///< Clock Calibration ULFRCO +}; + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Performs Clock Manager runtime initialization. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_runtime_init(void); + +/***************************************************************************//** + * Gets frequency of given oscillator. + * + * @param[in] oscillator Oscillator + * + * @param[out] frequency Oscillator's frequency in Hertz + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_get_oscillator_frequency(sl_oscillator_t oscillator, + uint32_t *frequency); + +/***************************************************************************//** + * Gets precision of given oscillator. + * + * @param[in] oscillator Oscillator + * + * @param[out] precision Oscillator's precision in PPM + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_oscillator_precision(sl_oscillator_t oscillator, + uint16_t *precision); + +/***************************************************************************//** + * Gets frequency of given clock branch. + * + * @param[in] clock_branch Clock Branch + * + * @param[out] frequency Clock Branch's frequency in Hertz + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_get_clock_branch_frequency(sl_clock_branch_t clock_branch, + uint32_t *frequency); + +/***************************************************************************//** + * Gets precision of given clock branch. + * + * @param[in] clock_branch Clock Branch + * + * @param[out] precision Clock Branch's precision in PPM + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_clock_branch_precision(sl_clock_branch_t clock_branch, + uint16_t *precision); + +/***************************************************************************//** + * Enables the given module's bus clock. + * + * @param[in] module_bus_clock module's bus clock to enable. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note modules' bus clocks are defined in the + * @ref device_clock in the Bus Clock Defines section. + ******************************************************************************/ +sl_status_t sl_clock_manager_enable_bus_clock(sl_bus_clock_t module_bus_clock); + +/***************************************************************************//** + * Disables the given module's bus clock. + * + * @param[in] module_bus_clock module's bus clock to disable. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note modules' bus clocks are defined in the + * @ref device_clock in the Bus Clock Defines section. + ******************************************************************************/ +sl_status_t sl_clock_manager_disable_bus_clock(sl_bus_clock_t module_bus_clock); + +/***************************************************************************//** + * Configures one clock export output with specified clock source. + * + * @param[in] export_clock_source One of the exportable clock source. + * + * @param[in] output_select Selected export clock output channel. + * + * @param[in] hfexp_divider HFEXP clock divider (1 to 32). + * Note: This parameter only affects the EXPCLK + * branch frequency. + * + * @param[in] port GPIO port to output exported clock. + * + * @param[in] pin GPIO pin number to output exported clock. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_gpio_clock_output(sl_clock_manager_export_clock_source_t export_clock_source, + sl_clock_manager_export_clock_output_select_t output_select, + uint16_t hfexp_divider, + uint32_t port, + uint32_t pin); + +/***************************************************************************//** + * Sets the RC oscillator frequency tuning control. + * + * @param[in] oscillator RC Oscillator to set tuning value for. + * + * @param[in] val The RC oscillator frequency tuning setting to use. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note RC Oscillator tuning is done during production, and the tuning value is + * loaded after a reset by the Clock Manager initialization code. + * Changing the tuning value from the calibrated value is for more advanced + * use. Certain oscillators also have build-in tuning optimization. + * + * @note Supported RC oscillators include: + * - SL_OSCILLATOR_HFRCODPLL + * - SL_OSCILLATOR_HFRCOEM23 + * - SL_OSCILLATOR_LFRCO + ******************************************************************************/ +sl_status_t sl_clock_manager_set_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t val); + +/***************************************************************************//** + * Gets the RC oscillator frequency tuning setting. + * + * @param[in] oscillator An RC oscillator to get tuning value for. + * + * @param[out] val The RC oscillator frequency tuning setting in use. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note Supported RC oscillators include: + * - SL_OSCILLATOR_HFRCODPLL + * - SL_OSCILLATOR_HFRCOEM23 + * - SL_OSCILLATOR_LFRCO + ******************************************************************************/ +sl_status_t sl_clock_manager_get_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t *val); + +/***************************************************************************//** + * Sets the HFXO calibration value. + * + * @param[in] val + * The HFXO calibration setting to use. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_hfxo_calibration(uint32_t val); + +/***************************************************************************//** + * Gets the HFXO calibration value. + * + * @param[out] val The current HFXO calibration value. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_hfxo_calibration(uint32_t *val); + +/***************************************************************************//** + * Sets the HFXO's CTUNE. + * + * @param[in] ctune The HFXO's CTUNE value. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note Sets the XI value to the given ctune value and sets the XO value based + * on that same value, but with an offset that is hardware dependent. + * Updating CTune while the crystal oscillator is running can + * result in significant clock glitches for one XO clock period. + * Should be used with caution. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_set_ctune(uint32_t ctune); + +/***************************************************************************//** + * Gets the HFXO's CTUNE. + * + * @param[out] ctune The returned HFXO's CTUNE value. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function only returns the CTUNE XI value. + * The XO value follows the XI value with a fixed delta that is + * hardware dependent. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_get_ctune(uint32_t *ctune); + +/***************************************************************************//** + * Updates the tuning capacitances and calibrate the Core Bias Current. + * + * @param[in] ctune The HFXO's CTUNE value. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note Calibrating the CTUNE is time consuming and will cause glitches on the + * HFXO's clock. Care and caution should be taken when using this API. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_calibrate_ctune(uint32_t ctune); + +/***************************************************************************//** + * Sets the LFXO frequency tuning control. + * + * @param[in] val The LFXO frequency tuning setting to use. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_lfxo_calibration(uint32_t val); + +/***************************************************************************//** + * Gets the LFXO frequency tuning setting. + * + * @param[out] val The LFXO frequency tuning setting to use. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_lfxo_calibration(uint32_t *val); + +/***************************************************************************//** + * Configures the RCO calibration. + * + * @param[in] cycles Number of cycles to run calibration. Increasing this + * number increases precision, but the calibration will + * take more time. + * + * @param[in] down_counter_selection + * The clock which will be counted down cycles. + * + * @param[in] up_counter_selection + * The number of cycles generated by this clock will be counted and + * added up, the result can be given with + * sl_clock_manager_get_rco_calibration_count(). + * + * @param[in] continuous_calibration + * Flag when true configures continuous calibration. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note RCO calibration related functions are not thread-safe and should + * therefore not be called across multiple tasks. + ******************************************************************************/ +sl_status_t sl_clock_manager_configure_rco_calibration(uint32_t cycles, + sl_clock_manager_clock_calibration_t down_counter_selection, + sl_clock_manager_clock_calibration_t up_counter_selection, + bool continuous_calibration); + +/***************************************************************************//** + * Starts the RCO calibration. + * + * @note RCO calibration related functions are not thread-safe and should + * therefore not be called across multiple tasks. + ******************************************************************************/ +void sl_clock_manager_start_rco_calibration(void); + +/***************************************************************************//** + * Stops the RCO calibration. + * + * @note RCO calibration related functions are not thread-safe and should + * therefore not be called across multiple tasks. + ******************************************************************************/ +void sl_clock_manager_stop_rco_calibration(void); + +/***************************************************************************//** + * Waits for the RCO calibration to finish. + * + * @note RCO calibration related functions are not thread-safe and should + * therefore not be called across multiple tasks. + ******************************************************************************/ +void sl_clock_manager_wait_rco_calibration(void); + +/***************************************************************************//** + * Gets calibration count value, returns the value of the up counter. + * + * @param[out] count Calibration count value. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note RCO calibration related functions are not thread-safe and should + * therefore not be called across multiple tasks. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_rco_calibration_count(uint32_t *count); + +/***************************************************************************//** + * Waits for USBPLL clock to be ready. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_wait_usbpll(void); + +/***************************************************************************//** + * When this callback function is called, it means that HFXO failed twice in + * a row to start with normal configurations. This may mean that there is a + * bad crystal. When getting this callback, HFXO is running but its properties + * (frequency, precision) are not guaranteed. This should be considered as an + * error situation. + * + * @note This callback will be called only when the + * SL_CLOCK_MANAGER_HFXO_SLEEPY_CRYSTAL_SUPPORT config is enabled + ******************************************************************************/ +void sl_clock_manager_hfxo_notify_consecutive_failed_startups(void); + +/***************************************************************************//** + * Sets the external FLASH reference clock. + * + * @param[in] oscillator Oscillator used to clock the external FLASH. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + * + * @note This API is not thread-safe and should therefore not be called + * across multiple tasks. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_set_ext_flash_clk(sl_oscillator_t oscillator); + +/***************************************************************************//** + * Gets the external FLASH clock source. + * + * @param[out] oscillator Oscillator used to clock the external FLASH. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_clock_manager_get_ext_flash_clk(sl_oscillator_t *oscillator); + +/** @} (end addtogroup clock_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_CLOCK_MANAGER_H diff --git a/Libs/platform/service/clock_manager/inc/sl_clock_manager_init.h b/Libs/platform/service/clock_manager/inc/sl_clock_manager_init.h new file mode 100644 index 0000000..2feb840 --- /dev/null +++ b/Libs/platform/service/clock_manager/inc/sl_clock_manager_init.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Init APIs. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_INIT_H +#define SL_CLOCK_MANAGER_INIT_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup clock_manager Clock Manager + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Initializes Oscillators and Clock branches. + * + * @return Status code. + * SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_clock_manager_init(void); + +/** @} (end addtogroup clock_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_CLOCK_MANAGER_INIT_H diff --git a/Libs/platform/service/clock_manager/inc/sli_clock_manager.h b/Libs/platform/service/clock_manager/inc/sli_clock_manager.h new file mode 100644 index 0000000..205c46e --- /dev/null +++ b/Libs/platform/service/clock_manager/inc/sli_clock_manager.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Private API definition. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_CLOCK_MANAGER_H +#define SLI_CLOCK_MANAGER_H + +#include "sl_clock_manager.h" +#include "sl_status.h" +#include "sl_compiler.h" +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Set SYSCLK clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_set_sysclk_source(sl_oscillator_t source); + +/***************************************************************************//** + * Get SYSCLK clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_get_sysclk_source(sl_oscillator_t *source); + +/***************************************************************************//** + * When this callback function is called, it means that HFXO is ready. + ******************************************************************************/ +__WEAK void sli_clock_manager_notify_hfxo_ready(void); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CLOCK_MANAGER_H diff --git a/Libs/platform/service/clock_manager/src/sl_clock_manager.c b/Libs/platform/service/clock_manager/src/sl_clock_manager.c new file mode 100644 index 0000000..67faff9 --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sl_clock_manager.c @@ -0,0 +1,313 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager API implementations. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_clock_manager.h" +#include "sl_clock_manager.h" +#include "sli_clock_manager.h" +#include "sli_clock_manager_hal.h" +#include "sl_assert.h" +#include "cmsis_compiler.h" + +/***************************************************************************//** + * Performs Clock Manager runtime initialization. + ******************************************************************************/ +sl_status_t sl_clock_manager_runtime_init(void) +{ + return sli_clock_manager_hal_runtime_init(); +} + +/***************************************************************************//** + * Gets frequency of given oscillator. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_oscillator_frequency(sl_oscillator_t oscillator, + uint32_t *frequency) +{ + if (frequency == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_oscillator_frequency(oscillator, frequency); +} + +/***************************************************************************//** + * Gets precision of given oscillator. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_oscillator_precision(sl_oscillator_t oscillator, + uint16_t *precision) +{ + if (precision == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_oscillator_precision(oscillator, precision); +} + +/***************************************************************************//** + * Gets frequency of given clock branch. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_clock_branch_frequency(sl_clock_branch_t clock_branch, + uint32_t *frequency) +{ + if (frequency == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_clock_branch_frequency(clock_branch, frequency); +} + +/***************************************************************************//** + * Gets precision of given clock branch. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_clock_branch_precision(sl_clock_branch_t clock_branch, + uint16_t *precision) +{ + if (precision == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_clock_branch_precision(clock_branch, precision); +} + +/***************************************************************************//** + * Enables the given module's bus clock. + ******************************************************************************/ +sl_status_t sl_clock_manager_enable_bus_clock(sl_bus_clock_t module_bus_clock) +{ + return sli_clock_manager_hal_enable_bus_clock(module_bus_clock, true); +} + +/***************************************************************************//** + * Disables the given module's bus clock. + ******************************************************************************/ +sl_status_t sl_clock_manager_disable_bus_clock(sl_bus_clock_t module_bus_clock) +{ + return sli_clock_manager_hal_enable_bus_clock(module_bus_clock, false); +} + +/***************************************************************************//** + * Configures one clock export output with specified clock source. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_gpio_clock_output(sl_clock_manager_export_clock_source_t export_clock_source, + sl_clock_manager_export_clock_output_select_t output_select, + uint16_t hfexp_divider, + uint32_t port, + uint32_t pin) +{ + return sli_clock_manager_hal_set_gpio_clock_output(export_clock_source, output_select, hfexp_divider, port, pin); +} + +/***************************************************************************//** + * Sets the RC oscillator frequency tuning control. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t val) +{ + return sli_clock_manager_hal_set_rc_oscillator_calibration(oscillator, val); +} + +/***************************************************************************//** + * Gets the RC oscillator frequency tuning setting. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t *val) +{ + if (val == NULL) { + return SL_STATUS_NULL_POINTER; + } + return sli_clock_manager_hal_get_rc_oscillator_calibration(oscillator, val); +} + +/***************************************************************************//** + * Sets the HFXO calibration value. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_hfxo_calibration(uint32_t val) +{ + return sli_clock_manager_hal_set_hfxo_calibration(val); +} + +/***************************************************************************//** + * Gets the HFXO calibration value. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_hfxo_calibration(uint32_t *val) +{ + if (val == NULL) { + return SL_STATUS_NULL_POINTER; + } + return sli_clock_manager_hal_get_hfxo_calibration(val); +} + +/***************************************************************************//** + * Sets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_set_ctune(uint32_t ctune) +{ + return sli_clock_manager_hal_hfxo_set_ctune(ctune); +} + +/***************************************************************************//** + * Gets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_get_ctune(uint32_t *ctune) +{ + if (ctune == NULL) { + return SL_STATUS_NULL_POINTER; + } + return sli_clock_manager_hal_hfxo_get_ctune(ctune); +} + +/***************************************************************************//** + * Updates the tuning capacitances and calibrate the Core Bias Current. + ******************************************************************************/ +sl_status_t slx_clock_manager_hfxo_calibrate_ctune(uint32_t ctune) +{ + return sli_clock_manager_hal_hfxo_calibrate_ctune(ctune); +} + +/***************************************************************************//** + * Sets the LFXO frequency tuning control. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_lfxo_calibration(uint32_t val) +{ + return sli_clock_manager_hal_set_lfxo_calibration(val); +} + +/***************************************************************************//** + * Gets the LFXO frequency tuning setting. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_lfxo_calibration(uint32_t *val) +{ + if (val == NULL) { + return SL_STATUS_NULL_POINTER; + } + return sli_clock_manager_hal_get_lfxo_calibration(val); +} + +/***************************************************************************//** + * Configures the RCO calibration. + ******************************************************************************/ +sl_status_t sl_clock_manager_configure_rco_calibration(uint32_t cycles, + sl_clock_manager_clock_calibration_t down_counter_selection, + sl_clock_manager_clock_calibration_t up_counter_selection, + bool continuous_calibration) +{ + return sli_clock_manager_hal_configure_rco_calibration(cycles, down_counter_selection, up_counter_selection, continuous_calibration); +} + +/***************************************************************************//** + * Starts the RCO calibration. + ******************************************************************************/ +void sl_clock_manager_start_rco_calibration(void) +{ + sli_clock_manager_hal_start_rco_calibration(); +} + +/***************************************************************************//** + * Stops the RCO calibration. + ******************************************************************************/ +void sl_clock_manager_stop_rco_calibration(void) +{ + sli_clock_manager_hal_stop_rco_calibration(); +} + +/***************************************************************************//** + * Waits for the RCO calibration to finish. + ******************************************************************************/ +void sl_clock_manager_wait_rco_calibration(void) +{ + sli_clock_manager_hal_wait_rco_calibration(); +} + +/***************************************************************************//** + * Gets calibration count value. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_rco_calibration_count(uint32_t *count) +{ + if (count == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_rco_calibration_count(count); +} + +/***************************************************************************//** + * Sets SYSCLK clock source. + ******************************************************************************/ +sl_status_t sli_clock_manager_set_sysclk_source(sl_oscillator_t source) +{ + return sli_clock_manager_hal_set_sysclk_source(source); +} + +/***************************************************************************//** + * Gets SYSCLK clock source. + ******************************************************************************/ +sl_status_t sli_clock_manager_get_sysclk_source(sl_oscillator_t *source) +{ + if (source == NULL) { + return SL_STATUS_NULL_POINTER; + } + + return sli_clock_manager_hal_get_sysclk_source(source); +} + +/***************************************************************************//** + * Waits for USBPLL clock to be ready. + ******************************************************************************/ +sl_status_t sl_clock_manager_wait_usbpll(void) +{ + return sli_clock_manager_hal_wait_usbpll(); +} + +/***************************************************************************//** + * When this callback function is called, it means that HFXO failed twice in + * a row to start with normal configurations. This may mean that there is a + * bad crystal. When getting this callback, HFXO is running but its properties + * (frequency, precision) are not guaranteed. This should be considered as an + * error situation. + ******************************************************************************/ +__WEAK void sl_clock_manager_hfxo_notify_consecutive_failed_startups(void) +{ + EFM_ASSERT(false); +} + +/***************************************************************************//** + * Sets the external FLASH reference clock. + ******************************************************************************/ +sl_status_t sl_clock_manager_set_ext_flash_clk(sl_oscillator_t oscillator) +{ + return sli_clock_manager_hal_set_ext_flash_clk(oscillator); +} + +/***************************************************************************//** + * Gets the external FLASH clock source. + ******************************************************************************/ +sl_status_t sl_clock_manager_get_ext_flash_clk(sl_oscillator_t *oscillator) +{ + return sli_clock_manager_hal_get_ext_flash_clk(oscillator); +} diff --git a/Libs/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c b/Libs/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c new file mode 100644 index 0000000..8d3900b --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c @@ -0,0 +1,1040 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager HAL API implementations. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_core.h" +#include "sl_clock_manager.h" +#include "sli_clock_manager.h" +#include "sli_clock_manager_hal.h" +#include "em_cmu.h" +#include "em_bus.h" +#include "em_device.h" +#include "em_gpio.h" + +/***************************************************************************//** + * Performs Clock Manager runtime initialization. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_runtime_init(void) +{ + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets frequency of given oscillator. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_oscillator_frequency(sl_oscillator_t oscillator, + uint32_t *frequency) +{ + switch (oscillator) { + case SL_OSCILLATOR_FSRCO: + *frequency = SystemFSRCOClockGet(); + break; + + case SL_OSCILLATOR_HFXO: + *frequency = SystemHFXOClockGet(); + break; + + case SL_OSCILLATOR_HFRCODPLL: + *frequency = SystemHFRCODPLLClockGet(); + break; + +#if defined(HFRCOEM23_PRESENT) + case SL_OSCILLATOR_HFRCOEM23: + *frequency = SystemHFRCOEM23ClockGet(); + break; +#endif + +#if defined(RFFPLL_PRESENT) + case SL_OSCILLATOR_RFFPLL: + *frequency = SystemRFFPLLClockGet(); + break; +#endif + +#if defined(USBPLL_PRESENT) + case SL_OSCILLATOR_USBPLL: + *frequency = CMU_ClockFreqGet(cmuClock_USB); + break; +#endif + + case SL_OSCILLATOR_LFXO: + *frequency = SystemLFXOClockGet(); + break; + + case SL_OSCILLATOR_LFRCO: + *frequency = SystemLFRCOClockGet(); + break; + + case SL_OSCILLATOR_ULFRCO: + *frequency = SystemULFRCOClockGet(); + break; + + default: + *frequency = 0U; + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets precision of given oscillator. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_oscillator_precision(sl_oscillator_t oscillator, + uint16_t *precision) +{ + switch (oscillator) { + case SL_OSCILLATOR_HFXO: + *precision = CMU_HFXOPrecisionGet(); + break; + + case SL_OSCILLATOR_LFXO: + *precision = CMU_LFXOPrecisionGet(); + break; + + case SL_OSCILLATOR_LFRCO: +#if defined(LFRCO_CFG_HIGHPRECEN) + if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { + *precision = 500; + } else { + *precision = 0xFFFF; + return SL_STATUS_NOT_AVAILABLE; + } +#else + *precision = 0xFFFF; + return SL_STATUS_NOT_AVAILABLE; +#endif + break; + + case SL_OSCILLATOR_FSRCO: + case SL_OSCILLATOR_HFRCODPLL: + case SL_OSCILLATOR_ULFRCO: +#if defined(HFRCOEM23_PRESENT) + case SL_OSCILLATOR_HFRCOEM23: +#endif + *precision = 0xFFFF; + return SL_STATUS_NOT_AVAILABLE; + +#if defined(RFFPLL_PRESENT) + case SL_OSCILLATOR_RFFPLL: + *precision = 0xFFFF; + return SL_STATUS_NOT_AVAILABLE; +#endif + +#if defined(USBPLL_PRESENT) + case SL_OSCILLATOR_USBPLL: + *precision = 0xFFFF; + return SL_STATUS_NOT_AVAILABLE; +#endif + + default: + *precision = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets frequency of given clock branch. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_clock_branch_frequency(sl_clock_branch_t clock_branch, + uint32_t *frequency) +{ + CORE_DECLARE_IRQ_STATE; + + sl_status_t return_status = SL_STATUS_OK; + + CORE_ENTER_ATOMIC(); + + switch (clock_branch) { + case SL_CLOCK_BRANCH_SYSCLK: + *frequency = SystemSYSCLKGet(); + break; + + case SL_CLOCK_BRANCH_HCLK: + *frequency = CMU_ClockFreqGet(cmuClock_HCLK); + break; + + case SL_CLOCK_BRANCH_PCLK: + *frequency = CMU_ClockFreqGet(cmuClock_PCLK); + break; + + case SL_CLOCK_BRANCH_LSPCLK: + *frequency = CMU_ClockFreqGet(cmuClock_LSPCLK); + break; + +#if defined(_CMU_TRACECLKCTRL_MASK) + case SL_CLOCK_BRANCH_TRACECLK: + *frequency = CMU_ClockFreqGet(cmuClock_TRACECLK); + break; +#endif +#if defined(_CMU_EXPORTCLKCTRL_MASK) + case SL_CLOCK_BRANCH_EXPORTCLK: + *frequency = CMU_ClockFreqGet(cmuClock_EXPCLK); + break; +#endif +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPACLK: + *frequency = CMU_ClockFreqGet(cmuClock_EM01GRPACLK); + break; +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPBCLK: + *frequency = CMU_ClockFreqGet(cmuClock_EM01GRPBCLK); + break; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPCCLK: + *frequency = CMU_ClockFreqGet(cmuClock_EM01GRPCCLK); + break; +#endif +#if defined(_CMU_EM23GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM23GRPACLK: + *frequency = CMU_ClockFreqGet(cmuClock_EM23GRPACLK); + break; +#endif +#if defined(_CMU_EM4GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM4GRPACLK: + *frequency = CMU_ClockFreqGet(cmuClock_EM4GRPACLK); + break; +#endif +#if defined(_CMU_IADCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_IADCCLK: + *frequency = CMU_ClockFreqGet(cmuClock_IADCCLK); + break; +#endif +#if defined(_CMU_WDOG0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_WDOG0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_WDOG0CLK); + break; +#endif +#if defined(_CMU_WDOG1CLKCTRL_MASK) + case SL_CLOCK_BRANCH_WDOG1CLK: + *frequency = CMU_ClockFreqGet(cmuClock_WDOG1CLK); + break; +#endif +#if defined(_CMU_RTCCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_RTCCCLK: + *frequency = CMU_ClockFreqGet(cmuClock_RTCCCLK); + break; +#endif +#if defined(_CMU_SYSRTC0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_SYSRTCCLK: + *frequency = CMU_ClockFreqGet(cmuClock_SYSRTCCLK); + break; +#endif +#if defined(_CMU_EUART0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_EUART0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_EUART0CLK); + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_EUSART0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_EUSART0CLK); + break; +#endif +#if defined(LCD_PRESENT) && defined(_CMU_LCDCLKCTRL_MASK) + case SL_CLOCK_BRANCH_LCDCLK: + *frequency = CMU_ClockFreqGet(cmuClock_LCDCLK); + break; +#endif +#if defined(_CMU_PCNT0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_PCNT0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_PCNT0CLK); + break; +#endif + + case SL_CLOCK_BRANCH_SYSTICKCLK: + *frequency = CMU_ClockFreqGet(cmuClock_SYSTICK); + break; + +#if defined(_CMU_LESENSEHFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_LESENSEHFCLK: + *frequency = CMU_ClockFreqGet(cmuClock_LESENSEHFCLK); + break; +#endif +#if defined(_CMU_VDAC0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_VDAC0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_VDAC0CLK); + break; +#endif +#if defined(_CMU_VDAC1CLKCTRL_MASK) + case SL_CLOCK_BRANCH_VDAC1CLK: + *frequency = CMU_ClockFreqGet(cmuClock_VDAC1CLK); + break; +#endif +#if defined(_CMU_USB0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_USB0CLK: + *frequency = CMU_ClockFreqGet(cmuClock_USB); + break; +#endif +#if defined(_CMU_DPLLREFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_DPLLREFCLK: + *frequency = CMU_ClockFreqGet(cmuClock_DPLLREFCLK); + break; +#endif + + default: + *frequency = 0U; + return_status = SL_STATUS_INVALID_PARAMETER; + break; + } + + CORE_EXIT_ATOMIC(); + + return return_status; +} + +/***************************************************************************//** + * Gets precision of given clock branch. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_clock_branch_precision(sl_clock_branch_t clock_branch, + uint16_t *precision) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t return_status = SL_STATUS_OK; + + CORE_ENTER_ATOMIC(); + + switch (clock_branch) { + case SL_CLOCK_BRANCH_SYSCLK: + case SL_CLOCK_BRANCH_HCLK: + case SL_CLOCK_BRANCH_PCLK: + case SL_CLOCK_BRANCH_LSPCLK: + case SL_CLOCK_BRANCH_EXPORTCLK: + *precision = CMU_HF_ClockPrecisionGet(cmuClock_SYSCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; + +#if defined(_CMU_TRACECLKCTRL_MASK) + case SL_CLOCK_BRANCH_TRACECLK: +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; +#else + *precision = CMU_HF_ClockPrecisionGet(cmuClock_SYSCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } +#endif + break; + +#endif +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPACLK: + *precision = CMU_HF_ClockPrecisionGet(cmuClock_EM01GRPACLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPBCLK: + *precision = CMU_HF_ClockPrecisionGet(cmuClock_EM01GRPBCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM01GRPCCLK: + *precision = CMU_HF_ClockPrecisionGet(cmuClock_EM01GRPCCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_EM23GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM23GRPACLK: + *precision = CMU_LF_ClockPrecisionGet(cmuClock_EM23GRPACLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_EM4GRPACLKCTRL_MASK) + case SL_CLOCK_BRANCH_EM4GRPACLK: + *precision = CMU_LF_ClockPrecisionGet(cmuClock_EM4GRPACLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_IADCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_IADCCLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_WDOG0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_WDOG0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_WDOG1CLKCTRL_MASK) + case SL_CLOCK_BRANCH_WDOG1CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_RTCCCLKCTRL_MASK) + case SL_CLOCK_BRANCH_RTCCCLK: + *precision = CMU_LF_ClockPrecisionGet(cmuClock_RTCCCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_SYSRTC0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_SYSRTCCLK: + *precision = CMU_LF_ClockPrecisionGet(cmuClock_SYSRTCCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_EUART0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_EUART0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_EUSART0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(LCD_PRESENT) && defined(_CMU_LCDCLKCTRL_MASK) + case SL_CLOCK_BRANCH_LCDCLK: + *precision = CMU_LF_ClockPrecisionGet(cmuClock_LCDCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_PCNT0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_PCNT0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif + + case SL_CLOCK_BRANCH_SYSTICKCLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; + +#if defined(_CMU_LESENSEHFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_LESENSEHFCLK: + *precision = CMU_HF_ClockPrecisionGet(cmuClock_LESENSEHFCLK); + if (*precision == 0xFFFF) { + return_status = SL_STATUS_NOT_AVAILABLE; + } + break; +#endif +#if defined(_CMU_VDAC0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_VDAC0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_VDAC1CLKCTRL_MASK) + case SL_CLOCK_BRANCH_VDAC1CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif +#if defined(_CMU_USB0CLKCTRL_MASK) + case SL_CLOCK_BRANCH_USB0CLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif + +#if defined(_CMU_DPLLREFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_DPLLREFCLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif + + default: + *precision = 0U; + return_status = SL_STATUS_INVALID_PARAMETER; + break; + } + + CORE_EXIT_ATOMIC(); + + return return_status; +} + +/***************************************************************************//** + * Enables/Disables the given module's bus clock. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_enable_bus_clock(sl_bus_clock_t module_bus_clock, bool enable) +{ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + volatile uint32_t *reg = NULL; + uint32_t bit; + uint32_t clken_index; + + if (module_bus_clock == SL_BUS_CLOCK_INVALID) { + return SL_STATUS_NOT_AVAILABLE; + } + + bit = (*module_bus_clock & _BUS_CLOCK_CLKEN_BIT_MASK) >> _BUS_CLOCK_CLKEN_BIT_SHIFT; + clken_index = (*module_bus_clock & _BUS_CLOCK_CLKENX_MASK) >> _BUS_CLOCK_CLKENX_SHIFT; + + if (clken_index == BUS_CLOCK_CLKEN0) { + reg = &CMU->CLKEN0; + } else if (clken_index == BUS_CLOCK_CLKEN1) { + reg = &CMU->CLKEN1; +#if defined(_CMU_CLKEN2_MASK) + } else if (clken_index == BUS_CLOCK_CLKEN2) { + reg = &CMU->CLKEN2; +#endif + } else { + return SL_STATUS_NOT_AVAILABLE; + } + + // Enable/disable bus clock. + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +#else // defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + (void)enable; + (void)module_bus_clock; +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configures the exported clock feature on CMU to output user selected + * clock source specified GPIO pin. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_gpio_clock_output(sl_clock_manager_export_clock_source_t export_clock_source, + sl_clock_manager_export_clock_output_select_t output_select, + uint16_t divider, + uint32_t port, + uint32_t pin) +{ + CMU_Select_TypeDef cmu_clock_select; + CORE_DECLARE_IRQ_STATE; + + switch (export_clock_source) { + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_DISABLED: + cmu_clock_select = cmuSelect_Disabled; + break; +#if defined(FSRCO_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_FSRCO: + cmu_clock_select = cmuSelect_FSRCO; + break; +#endif +#if defined(HFXO_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFXO: + cmu_clock_select = cmuSelect_HFXO; + break; +#endif +#if defined(DPLL_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFRCODPLL: + cmu_clock_select = cmuSelect_HFRCODPLL; + break; +#endif +#if defined(HFRCOEM23_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFRCOEM23: + cmu_clock_select = cmuSelect_HFRCOEM23; + break; +#endif + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HFEXPCLK: + cmu_clock_select = cmuSelect_EXPCLK; + break; +#if defined(LFXO_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_LFXO: + cmu_clock_select = cmuSelect_LFXO; + break; +#endif +#if defined(PLFRCO_PRESENT) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_PLFRCO: + cmu_clock_select = cmuSelect_PLFRCO; + break; +#endif +#if defined(LFRCO) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_LFRCO: + cmu_clock_select = cmuSelect_LFRCO; + break; +#endif +#if defined(ULFRCO) + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_ULFRCO: + cmu_clock_select = cmuSelect_ULFRCO; + break; +#endif + case SL_CLOCK_MANAGER_EXPORT_CLOCK_SOURCE_HCLK: + cmu_clock_select = cmuSelect_HCLK; + break; + + default: + return SL_STATUS_NOT_SUPPORTED; + } + + CORE_ENTER_ATOMIC(); + + CMU_ClkOutPinConfig((uint32_t)output_select, cmu_clock_select, (CMU_ClkDiv_TypeDef)divider, port, pin); + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the RC oscillator frequency tuning control. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t val) +{ + switch (oscillator) { + case SL_OSCILLATOR_HFRCODPLL: + CMU_OscillatorTuningSet(cmuOsc_HFRCODPLL, val); + break; + +#if defined(HFRCOEM23_PRESENT) + case SL_OSCILLATOR_HFRCOEM23: + CMU_OscillatorTuningSet(cmuOsc_HFRCOEM23, val); + break; +#endif + + case SL_OSCILLATOR_LFRCO: + CMU_OscillatorTuningSet(cmuOsc_LFRCO, val); + break; + + default: + return SL_STATUS_NOT_SUPPORTED; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the RC oscillator frequency tuning setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t *val) +{ + switch (oscillator) { + case SL_OSCILLATOR_HFRCODPLL: + *val = CMU_OscillatorTuningGet(cmuOsc_HFRCODPLL); + break; + +#if defined(HFRCOEM23_PRESENT) + case SL_OSCILLATOR_HFRCOEM23: + *val = CMU_OscillatorTuningGet(cmuOsc_HFRCOEM23); + break; +#endif + + case SL_OSCILLATOR_LFRCO: + *val = CMU_OscillatorTuningGet(cmuOsc_LFRCO); + break; + + default: + *val = 0; + return SL_STATUS_NOT_SUPPORTED; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets HFXO calibration value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_hfxo_calibration(uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + CMU_OscillatorTuningSet(cmuOsc_HFXO, val); + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the HFXO calibration value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_hfxo_calibration(uint32_t *val) +{ + *val = CMU_OscillatorTuningGet(cmuOsc_HFXO); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_set_ctune(uint32_t ctune) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t return_status = SL_STATUS_OK; + + CORE_ENTER_ATOMIC(); + return_status = CMU_HFXOCTuneSet(ctune); + CORE_EXIT_ATOMIC(); + + return return_status; +} + +/***************************************************************************//** + * Gets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_get_ctune(uint32_t *ctune) +{ + *ctune = CMU_HFXOCTuneGet(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Updates the tuning capacitances and calibrate the Core Bias Current. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_calibrate_ctune(uint32_t ctune) +{ + uint32_t hfxo_ctrl_backup = HFXO0->CTRL; + + // Having the FORCEEN here prevents the enabling and disabling of HFXO in + // each function calls. + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) + != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { + // Wait for crystal to startup + } + + sl_status_t status = CMU_HFXOCTuneSet(ctune); + + if (status == SL_STATUS_OK) { + CMU_HFXOCoreBiasCurrentCalibrate(); + } + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxo_ctrl_backup); + + return status; +} + +/***************************************************************************//** + * Sets LFXO frequency tuning control. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_lfxo_calibration(uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + CMU_OscillatorTuningSet(cmuOsc_LFXO, val); + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the LFXO frequency tuning setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_lfxo_calibration(uint32_t *val) +{ + *val = CMU_OscillatorTuningGet(cmuOsc_LFXO); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configures the RCO calibration. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_configure_rco_calibration(uint32_t cycles, + sl_clock_manager_clock_calibration_t down_counter_selection, + sl_clock_manager_clock_calibration_t up_counter_selection, + bool continuous_calibration) +{ + CMU_Select_TypeDef down_selection; + CMU_Select_TypeDef up_selection; + + switch (down_counter_selection) { + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFXO: + down_selection = cmuSelect_HFXO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFXO: + down_selection = cmuSelect_LFXO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCODPLL: + down_selection = cmuSelect_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCOEM23: + down_selection = cmuSelect_HFRCOEM23; + break; +#endif + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_FSRCO: + down_selection = cmuSelect_FSRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFRCO: + down_selection = cmuSelect_LFRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_ULFRCO: + down_selection = cmuSelect_ULFRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_PRS: + down_selection = cmuSelect_PRS; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HCLK: + down_selection = cmuSelect_HCLK; + break; + + default: + return SL_STATUS_NOT_AVAILABLE; + } + + switch (up_counter_selection) { + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFXO: + up_selection = cmuSelect_HFXO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFXO: + up_selection = cmuSelect_LFXO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCODPLL: + up_selection = cmuSelect_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HFRCOEM23: + up_selection = cmuSelect_HFRCOEM23; + break; +#endif + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_FSRCO: + up_selection = cmuSelect_FSRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_LFRCO: + up_selection = cmuSelect_LFRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_ULFRCO: + up_selection = cmuSelect_ULFRCO; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_PRS: + up_selection = cmuSelect_PRS; + break; + + case SL_CLOCK_MANAGER_CLOCK_CALIBRATION_HCLK: + return SL_STATUS_NOT_SUPPORTED; + + default: + return SL_STATUS_NOT_AVAILABLE; + } + + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + CMU_CalibrateConfig(cycles, down_selection, up_selection); + CMU_CalibrateCont(continuous_calibration); + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Starts the RCO calibration. + ******************************************************************************/ +void sli_clock_manager_hal_start_rco_calibration(void) +{ + CMU_CalibrateStart(); +} + +/***************************************************************************//** + * Stops the RCO calibration. + ******************************************************************************/ +void sli_clock_manager_hal_stop_rco_calibration(void) +{ + CMU_CalibrateStop(); +} + +/***************************************************************************//** + * Waits for the RCO calibration to finish. + ******************************************************************************/ +void sli_clock_manager_hal_wait_rco_calibration(void) +{ + // Wait until calibration completes, UNLESS continuous calibration mode is on + if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { + // Wait until calibration completes + while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) ; + } +} + +/***************************************************************************//** + * Gets calibration count value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_rco_calibration_count(uint32_t *count) +{ + *count = CMU->CALCNT; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Updates SYSCLK clock source clock. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_sysclk_source(sl_oscillator_t source) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t return_status = SL_STATUS_OK; + + CORE_ENTER_ATOMIC(); + + switch (source) { + case SL_OSCILLATOR_FSRCO: + sli_em_cmu_SYSCLKInitPreClockSelect(); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_FSRCO; + sli_em_cmu_SYSCLKInitPostClockSelect(false); + break; + case SL_OSCILLATOR_HFXO: + sli_em_cmu_SYSCLKInitPreClockSelect(); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_HFXO; + sli_em_cmu_SYSCLKInitPostClockSelect(false); + break; + case SL_OSCILLATOR_HFRCODPLL: + sli_em_cmu_SYSCLKInitPreClockSelect(); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; + sli_em_cmu_SYSCLKInitPostClockSelect(false); + break; +#if defined(CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS) + case SL_OSCILLATOR_RFFPLL: + sli_em_cmu_SYSCLKInitPreClockSelect(); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; + sli_em_cmu_SYSCLKInitPostClockSelect(false); + break; +#endif + case SL_OSCILLATOR_CLKIN0: + sli_em_cmu_SYSCLKInitPreClockSelect(); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; + sli_em_cmu_SYSCLKInitPostClockSelect(false); + break; + default: + return_status = SL_STATUS_INVALID_PARAMETER; + break; + } + + CORE_EXIT_ATOMIC(); + + return return_status; +} + +/***************************************************************************//** + * Gets SYSCLK clock source clock. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_sysclk_source(sl_oscillator_t *source) +{ + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case CMU_SYSCLKCTRL_CLKSEL_FSRCO: + *source = SL_OSCILLATOR_FSRCO; + break; + case CMU_SYSCLKCTRL_CLKSEL_HFXO: + *source = SL_OSCILLATOR_HFXO; + break; + case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + *source = SL_OSCILLATOR_HFRCODPLL; + break; + case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + *source = SL_OSCILLATOR_CLKIN0; + break; +#if defined(CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS) + case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: + *source = SL_OSCILLATOR_RFFPLL; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Waits for USBPLL clock to be ready. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_wait_usbpll(void) +{ +#if defined(USBPLL_PRESENT) + while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) + != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { + // Wait for USB PLL lock and ready + } + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +/***************************************************************************//** + * Sets the external FLASH reference clock. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_ext_flash_clk(sl_oscillator_t oscillator) +{ + (void)oscillator; + return SL_STATUS_NOT_AVAILABLE; +} + +/***************************************************************************//** + * Gets the external FLASH clock source. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_ext_flash_clk(sl_oscillator_t *oscillator) +{ + if (oscillator == NULL) { + return SL_STATUS_NULL_POINTER; + } + + (void)oscillator; + return SL_STATUS_NOT_AVAILABLE; +} diff --git a/Libs/platform/service/clock_manager/src/sl_clock_manager_init.c b/Libs/platform/service/clock_manager/src/sl_clock_manager_init.c new file mode 100644 index 0000000..77482f4 --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sl_clock_manager_init.c @@ -0,0 +1,40 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Init API implementations. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_clock_manager_init.h" +#include "sli_clock_manager_init_hal.h" + +/***************************************************************************//** + * Initializes Oscillators and Clock branches. + ******************************************************************************/ +sl_status_t sl_clock_manager_init(void) +{ + return sli_clock_manager_hal_init(); +} diff --git a/Libs/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c b/Libs/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c new file mode 100644 index 0000000..e7dcd40 --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c @@ -0,0 +1,886 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Init HAL API implementations. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_clock_manager_oscillator_config.h" +#include "sl_clock_manager_tree_config.h" +#include "sli_clock_manager_init_hal.h" +#include "sl_clock_manager.h" +#include "sl_status.h" +#include "sl_assert.h" +#include "em_device.h" +#include "em_cmu.h" +#include "sl_gpio.h" + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#include "sli_clock_manager_runtime_configuration.h" +#endif + +#if defined(RFFPLL_PRESENT) +#if defined(SL_CLOCK_MANAGER_RFFPLL_BAND) && (SL_CLOCK_MANAGER_RFFPLL_BAND == 7) +#ifdef SL_CLOCK_MANAGER_AUTO_BAND_VALID +#include "rail_config.h" +#endif +#endif +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +// Fetch HFXO CTUNE value from USERDATA page as a manufacturing token +#define MFG_CTUNE_HFXO_ADDR 0x0FE00100UL +#define MFG_CTUNE_HFXO_VAL (*((uint16_t *) (MFG_CTUNE_HFXO_ADDR))) + +// Fetch LFXO CTUNE value from USERDATA page as a manufacturing token +#define MFG_CTUNE_LFXO_ADDR 0x0FE0009CUL +#define MFG_CTUNE_LFXO_VAL (*((uint8_t *) (MFG_CTUNE_LFXO_ADDR))) + +#if defined(RFFPLL_PRESENT) +// If RADIO_CONFIG_RFFPLL_CONFIG_PRESENT is not defined, either there is no +// radio configuration in the project or the radio configuration that is +// present does not include an RFFPLL configuration. +// In either case, the Auto-Band feature cannot work, so fall back to the +// default band (Band 9xx). +#if defined(SL_CLOCK_MANAGER_RFFPLL_BAND) && (SL_CLOCK_MANAGER_RFFPLL_BAND == 7) +#ifndef RADIO_CONFIG_RFFPLL_CONFIG_PRESENT +#undef SL_CLOCK_MANAGER_RFFPLL_BAND +#define SL_CLOCK_MANAGER_RFFPLL_BAND 6 +#endif +#endif +#endif + +// Allocated PRS channel for crystal sharing +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +#define HFXO_CRYSTSAL_SHARING_PRS_CHANNEL 0 +#endif + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#define FUNCTION_SCOPE +#else +#define FUNCTION_SCOPE static +#endif + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +#if defined(RFFPLL_PRESENT) +typedef struct { + uint32_t frequency; // Host target frequency. + uint8_t divider_y; // Divider Y for digital. + uint8_t divider_x; // Divider X for Radio. + uint8_t divider_n; // Feedback divider N. +} clock_manager_rffpll_config_t; +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(RFFPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) \ + && (SL_CLOCK_MANAGER_RFFPLL_CUSTOM_BAND == 0) \ + && !((SL_CLOCK_MANAGER_RFFPLL_BAND == 7) && defined(RADIO_CONFIG_RFFPLL_CONFIG_PRESENT)) +// Table of possible radio frequency bands and their associated settings. +static clock_manager_rffpll_config_t rffpll_band_config_39MHz[] = { + { 97500000, 23, 7, 115 }, // Band 450 MHz + { 98380000, 22, 7, 111 }, // Band 470 MHz + { 97500000, 23, 7, 115 }, // Band 780 MHz + { 97500000, 20, 6, 100 }, // Band 863 MHz + { 97500000, 23, 7, 115 }, // Band 896 MHz + { 96520000, 20, 6, 99 }, // Band 928 MHz + { 97500000, 20, 6, 100 } // Band 9xx MHz (covers from 901 to 928 MHz) +}; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +uint32_t SLI_CLOCK_MANAGER_HFXO_MODE = SL_CLOCK_MANAGER_HFXO_MODE; +uint32_t SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY = SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT; +uint32_t SLI_CLOCK_MANAGER_HFRCO_BAND = SL_CLOCK_MANAGER_HFRCO_BAND; +#endif + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(HFXO_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && SL_CLOCK_MANAGER_HFXO_EN == 1 +/***************************************************************************//** + * Initializes HFXO Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_hfxo(void) +{ + CMU_HFXOInit_TypeDef clock_manager_hfxo_init = CMU_HFXOINIT_DEFAULT; + clock_manager_hfxo_init.mode = SLI_CLOCK_MANAGER_HFXO_MODE >> _HFXO_CFG_MODE_SHIFT; + + if (SLI_CLOCK_MANAGER_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { + clock_manager_hfxo_init = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; +#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) + } else if (SLI_CLOCK_MANAGER_HFXO_MODE == cmuHfxoOscMode_ExternalSinePkDet) { + clock_manager_hfxo_init = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINEPKDET; +#endif + } + + int ctune = -1; + +#if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) + // Use HFXO tuning value from DEVINFO if available (PCB modules) + if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { + ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; + } +#endif + + // Use HFXO tuning value from MFG token in UD page if not already set + if ((ctune == -1) +#if defined(SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN) + && (SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN == 1) +#endif + && (MFG_CTUNE_HFXO_VAL <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT))) { + ctune = MFG_CTUNE_HFXO_VAL; + } + + // Use HFXO tuning value from configurations as fallback + if (ctune == -1) { + ctune = SL_CLOCK_MANAGER_HFXO_CTUNE; + } + + // Configure CTUNE XI and XO. + if (ctune != -1) { + clock_manager_hfxo_init.ctuneXiAna = (uint8_t)ctune; + + // Ensure CTUNE XO plus a delta is within the correct range. The delta accounts for internal chip + // load imbalance on some series 2 chips. + ctune += CMU_HFXOCTuneDeltaGet(); + if (ctune < 0) { + ctune = 0; + } else if (ctune > ((int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT))) { + ctune = (int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); + } + clock_manager_hfxo_init.ctuneXoAna = ctune; + } + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + if (SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY != SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT) { + clock_manager_hfxo_init.ctuneFixAna = SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY; + } +#endif + +#if defined(SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN) && (SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN == 1) + // Set port and pin. + GPIO_Port_TypeDef port = SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT; + unsigned int pin = SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN; + + // Enable HFXO and GPIO bus clocks. + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_HFXO0); + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); +#if defined(SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN) && (SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN == 1) + // Initialize Crystal sharing follower. + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_PRS); + + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + uint32_t mask = 0U, value = 0U; + + bool was_locked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + HFXO0->IEN_SET = HFXO_IEN_BUFOUTRDY; + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_PRSSTATUSSEL0_MASK, (_HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT)); + + if (was_locked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } + + value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT + | _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + + mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK + | _PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK + | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; + + BUS_RegMaskedWrite(&(PRS->ASYNC_CH[HFXO_CRYSTSAL_SHARING_PRS_CHANNEL].CTRL), mask, value); + + GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); + + (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[HFXO_CRYSTSAL_SHARING_PRS_CHANNEL] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT + | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; + GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + HFXO_CRYSTSAL_SHARING_PRS_CHANNEL); + + //sl_clock_manager_disable_bus_clock(SL_BUS_CLOCK_PRS); +#elif defined(SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN) && (SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN == 1) + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // Configure Bufout request GPIO. + GPIO_PinModeSet(port, pin, gpioModeInput, 0U); + + GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT + | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; + + bool was_locked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; + + BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, + _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK + | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, + ((uint32_t)SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN) << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT + | SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP); + + if (was_locked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +#endif +#endif + + SystemHFXOClockSet(SL_CLOCK_MANAGER_HFXO_FREQ); + CMU_HFXOInit(&clock_manager_hfxo_init); + CMU_HFXOPrecisionSet(SL_CLOCK_MANAGER_HFXO_PRECISION); + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + if (SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY == SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT) { + SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEFIXANA_MASK) >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT; + } +#endif + + return SL_STATUS_OK; +} +#endif + +#if defined(LFXO_PRESENT) \ + && defined(SL_CLOCK_MANAGER_LFXO_EN) && SL_CLOCK_MANAGER_LFXO_EN == 1 +/***************************************************************************//** + * Initializes LFXO Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_lfxo(void) +{ + CMU_LFXOInit_TypeDef clock_manager_lfxo_init = CMU_LFXOINIT_DEFAULT; + + clock_manager_lfxo_init.mode = SL_CLOCK_MANAGER_LFXO_MODE >> _LFXO_CFG_MODE_SHIFT; + clock_manager_lfxo_init.timeout = SL_CLOCK_MANAGER_LFXO_TIMEOUT >> _LFXO_CFG_TIMEOUT_SHIFT; + clock_manager_lfxo_init.capTune = 0xFF; + +#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 +#if defined(_DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) + // Use LFXO tuning value from DEVINFO if available (PCB modules) + if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_LFXOCALVAL_MASK) == _DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { + clock_manager_lfxo_init.capTune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK; + } +#endif +#endif + + if ((clock_manager_lfxo_init.capTune == 0xFF) +#if defined(SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN) + && (SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN == 1) +#endif + && (MFG_CTUNE_LFXO_VAL <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT))) { + clock_manager_lfxo_init.capTune = MFG_CTUNE_LFXO_VAL; + } + + if (clock_manager_lfxo_init.capTune == 0xFF) { + clock_manager_lfxo_init.capTune = SL_CLOCK_MANAGER_LFXO_CTUNE; + } + + CMU_LFXOInit(&clock_manager_lfxo_init); + CMU_LFXOPrecisionSet(SL_CLOCK_MANAGER_LFXO_PRECISION); + + return SL_STATUS_OK; +} +#endif + +/***************************************************************************//** + * Initializes Clock Input CLKIN0. + ******************************************************************************/ +static sl_status_t init_clkin0(void) +{ + sl_status_t status = SL_STATUS_OK; + +#if (defined(SL_CLOCK_MANAGER_SYSCLK_SOURCE) && (SL_CLOCK_MANAGER_SYSCLK_SOURCE == CMU_SYSCLKCTRL_CLKSEL_CLKIN0)) \ + || (defined(SL_CLOCK_MANAGER_DPLL_REFCLK) && (SL_CLOCK_MANAGER_DPLL_REFCLK == CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0)) \ + || (defined(SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE) && (SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE == CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0)) + +#if !defined(SL_CLOCK_MANAGER_CLKIN0_PORT) || !defined(SL_CLOCK_MANAGER_CLKIN0_PIN) +#error "Invalid configuration: CLKIN0 reference can't be use without configuring SL_CLOCK_MANAGER_CLKIN0 with a valid port and pin." +#endif + + sl_gpio_t clkin0_gpio = { SL_CLOCK_MANAGER_CLKIN0_PORT, SL_CLOCK_MANAGER_CLKIN0_PIN }; + + status = sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + if (status != SL_STATUS_OK) { + return status; + } + + status = sl_gpio_set_pin_mode(&clkin0_gpio, SL_GPIO_MODE_INPUT, false); + if (status == SL_STATUS_OK) { + GPIO->CMUROUTE.CLKIN0ROUTE = (clkin0_gpio.port << _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT) + | (clkin0_gpio.pin << _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT); + } +#endif + return status; +} + +#if defined(HFRCO_PRESENT) +/***************************************************************************//** + * Initializes HFRCODPLL Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_hfrcodpll(void) +{ +#if defined(SL_CLOCK_MANAGER_HFRCO_DPLL_EN) && (SL_CLOCK_MANAGER_HFRCO_DPLL_EN == 1) + CMU_DPLLInit_TypeDef clock_manager_dpll_init = { + .frequency = SL_CLOCK_MANAGER_DPLL_FREQ, + .n = SL_CLOCK_MANAGER_DPLL_N, + .m = SL_CLOCK_MANAGER_DPLL_M, + .edgeSel = SL_CLOCK_MANAGER_DPLL_EDGE, + .lockMode = SL_CLOCK_MANAGER_DPLL_LOCKMODE, + .autoRecover = SL_CLOCK_MANAGER_DPLL_AUTORECOVER, + .ditherEn = SL_CLOCK_MANAGER_DPLL_DITHER + }; + + // Convert the DPLL Reference clock configuration to emlib CMU_Select_TypeDef type. + switch (SL_CLOCK_MANAGER_DPLL_REFCLK) { + case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + clock_manager_dpll_init.refClk = cmuSelect_HFXO; + break; + case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + clock_manager_dpll_init.refClk = cmuSelect_LFXO; + break; + case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + clock_manager_dpll_init.refClk = cmuSelect_CLKIN0; + break; + default: + return SL_STATUS_INVALID_CONFIGURATION; + } + + CMU_Select_TypeDef selected_sysclk = CMU_ClockSelectGet(cmuClock_SYSCLK); + + if (selected_sysclk == cmuSelect_HFRCODPLL) { + // The CMU should not be running from the HFRCO. If necessary, the CMU + // should switch to the FSRCO until after the DPLL has locked to avoid + // over-clocking due to overshoot. + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_FSRCO; + } + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_DPLL0, true); +#endif + + bool success = CMU_DPLLLock(&clock_manager_dpll_init); + + // If CMU was initially running from HFRCO switch back from FSRCO. + if (selected_sysclk == cmuSelect_HFRCODPLL) { + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; + } + + // If DPLL lock was unsuccessful, return status fail. + if (!success) { + // Disable DPLL0 if lock failed. +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_DPLL0, false); +#endif + return SL_STATUS_FAIL; + } +#else + CMU_HFRCODPLLBandSet(SLI_CLOCK_MANAGER_HFRCO_BAND); +#endif + return SL_STATUS_OK; +} +#endif + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * Initializes HFRCOEM23 Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_hfrcoem23(void) +{ + CMU_HFRCOEM23BandSet(SL_CLOCK_MANAGER_HFRCOEM23_BAND); + + return SL_STATUS_OK; +} +#endif + +#if defined(LFRCO_PRESENT) +/***************************************************************************//** + * Initializes LFRCO Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_lfrco(void) +{ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LFRCO, true); +#endif + +#if defined(PLFRCO_PRESENT) +#if !(defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1)) + EFM_ASSERT(SL_CLOCK_MANAGER_LFRCO_PRECISION != cmuPrecisionHigh); +#endif + CMU_LFRCOSetPrecision(SL_CLOCK_MANAGER_LFRCO_PRECISION); +#endif + + return SL_STATUS_OK; +} +#endif + +#if defined(RFFPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) +/***************************************************************************//** + * Initializes RFFPLL Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_rffpll(void) +{ + CMU_RFFPLL_Init_TypeDef rffpll_init = CMU_RFFPLL_DEFAULT; + + // Overwrite default configurations. +#if (SL_CLOCK_MANAGER_RFFPLL_CUSTOM_BAND == 1) + // Custom settings provided by the user. + rffpll_init.frequency = SL_CLOCK_MANAGER_RFFPLL_FREQ; + rffpll_init.dividerY = SL_CLOCK_MANAGER_RFFPLL_DIV_Y; + rffpll_init.dividerX = SL_CLOCK_MANAGER_RFFPLL_DIV_X; + rffpll_init.dividerN = SL_CLOCK_MANAGER_RFFPLL_DIV_N; +#elif (SL_CLOCK_MANAGER_RFFPLL_BAND == 7) && defined(RADIO_CONFIG_RFFPLL_CONFIG_PRESENT) + // Settings from the RAIL lib. + rffpll_init.frequency = radioConfigRffpllConfig->sysclkFreqHz; + rffpll_init.dividerY = ((radioConfigRffpllConfig->dividers & RAIL_RFFPLL_DIVIDERY_MASK) >> RAIL_RFFPLL_DIVIDERY_SHIFT); + rffpll_init.dividerX = ((radioConfigRffpllConfig->dividers & RAIL_RFFPLL_DIVIDERX_MASK) >> RAIL_RFFPLL_DIVIDERX_SHIFT); + rffpll_init.dividerN = ((radioConfigRffpllConfig->dividers & RAIL_RFFPLL_DIVIDERN_MASK) >> RAIL_RFFPLL_DIVIDERN_SHIFT); +#else + // Pre-determined settings. + rffpll_init.frequency = rffpll_band_config_39MHz[SL_CLOCK_MANAGER_RFFPLL_BAND].frequency; + rffpll_init.dividerY = rffpll_band_config_39MHz[SL_CLOCK_MANAGER_RFFPLL_BAND].divider_y; + rffpll_init.dividerX = rffpll_band_config_39MHz[SL_CLOCK_MANAGER_RFFPLL_BAND].divider_x; + rffpll_init.dividerN = rffpll_band_config_39MHz[SL_CLOCK_MANAGER_RFFPLL_BAND].divider_n; +#endif + + // Initialize RFFPLL. + CMU_RFFPLLInit(&rffpll_init); + + // Update RFFPLL frequency in System file + SystemRFFPLLClockSet(rffpll_init.frequency); + + // At this point, RFFPLL has been initialized. The clock source for SYSCLK can be + // RFFPLLSYS input clock. If you want RFFPLLSYS, configure SL_CLOCK_MANAGER_SYSCLK_SOURCE + // to CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS. + + return SL_STATUS_OK; +} +#endif + +#if defined(USBPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) +/***************************************************************************//** + * Initializes USBPLL Oscillator. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_usbpll(void) +{ + CMU_USBPLL_Init_TypeDef usbpll_config; + uint32_t hfxo_freq = SystemHFXOClockGet(); + + // Validate that HFXO frequency is adequate for USB PLL and set the right frequency. + switch (hfxo_freq) { + case 38000000: + usbpll_config.hfxoRefFreq = cmuHFXORefFreq_38M0Hz; + break; + + case 38400000: + usbpll_config.hfxoRefFreq = cmuHFXORefFreq_38M4Hz; + break; + + case 39000000: + usbpll_config.hfxoRefFreq = cmuHFXORefFreq_39M0Hz; + break; + + case 40000000: + usbpll_config.hfxoRefFreq = cmuHFXORefFreq_40M0Hz; + break; + + default: + return SL_STATUS_FAIL; + } + + // Set additional configurations. + usbpll_config.shuntRegEn = false; + usbpll_config.disOnDemand = false; + usbpll_config.regLock = true; + + // Set Force Enable feature at first to force the PLL to start and validate it works. + usbpll_config.forceEn = true; + + // Initialize USB PLL and wait for it to be ready. + CMU_USBPLLInit(&usbpll_config); + + // Remove the Force Enable feature to let PLL module on-demand. + usbpll_config.forceEn = false; + + // Re-initialized without the Force Enable feature. + CMU_USBPLLInit(&usbpll_config); + + return SL_STATUS_OK; +} +#endif + +/***************************************************************************//** + * Initializes Clock branches. + ******************************************************************************/ +FUNCTION_SCOPE sl_status_t init_clock_branches(void) +{ + // Initialize SYSCLK clock branch. +#if defined(SL_CLOCK_MANAGER_SYSCLK_SOURCE) + sli_em_cmu_SYSCLKInitPreClockSelect(); +#if (SL_CLOCK_MANAGER_SYSCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(SYSCLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(SYSCLK, SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(SYSCLK, SL_CLOCK_MANAGER_SYSCLK_SOURCE); +#endif + sli_em_cmu_SYSCLKInitPostClockSelect(false); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK | _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) + | SL_CLOCK_MANAGER_HCLK_DIVIDER + | SL_CLOCK_MANAGER_PCLK_DIVIDER; +#else + EFM_ASSERT(false); +#endif + + // Initialize TRACECLK clock branch. +#if defined(CoreDebug_DEMCR_TRCENA_Msk) + // Disable the Core Debug module if already enabled + bool trace_on = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (trace_on) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif +#if defined(SL_CLOCK_MANAGER_TRACECLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(TRACECLK, SL_CLOCK_MANAGER_TRACECLK_SOURCE); +#endif +#if defined(SL_CLOCK_MANAGER_TRACECLK_DIVIDER) + CMU->TRACECLKCTRL |= SL_CLOCK_MANAGER_TRACECLK_DIVIDER; +#endif +#if defined(CoreDebug_DEMCR_TRCENA_Msk) + // Enable back the Core Debug module if it was already enabled + if (trace_on) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + // Ensure TraceClk configs are defined if TraceClk is present. +#if defined(_CMU_TRACECLKCTRL_MASK) && !(defined(SL_CLOCK_MANAGER_TRACECLK_SOURCE) || defined(SL_CLOCK_MANAGER_TRACECLK_DIVIDER)) + EFM_ASSERT(false); +#endif + + // Initialize EM01GRPACLK clock branch. +#if defined(SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE) +#if (SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPACLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(EM01GRPACLK, SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPACLK, SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif + + // Initialize EM01GRPBCLK clock branch. +#if defined(PDM_PRESENT) +#if defined(SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE) +#if (SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPBCLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(EM01GRPBCLK, SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPBCLK, SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize EM01GRPCCLK clock branch. +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#if defined(SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE) +#if (SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPCCLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(EM01GRPCCLK, SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(EM01GRPCCLK, SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize IADCCLK clock branch. +#if defined(SL_CLOCK_MANAGER_IADCCLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(IADCCLK, SL_CLOCK_MANAGER_IADCCLK_SOURCE); +#else + EFM_ASSERT(false); +#endif + + // Initialize LESENSEHFCLK clock branch. +#if defined(LESENSE_PRESENT) +#if defined(SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(LESENSEHFCLK, SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE); +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize EM23GRPACLK clock branch. +#if defined(SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE) +#if (SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EM23GRPACLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(EM23GRPACLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(EM23GRPACLK, SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif + + // Initialize EM4GRPACLK clock branch. +#if defined(SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE) +#if (SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EM4GRPACLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(EM4GRPACLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(EM4GRPACLK, SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif + + // Initialize RTCC clock branch. +#if defined(RTCC_PRESENT) +#if defined(SL_CLOCK_MANAGER_RTCCCLK_SOURCE) +#if (SL_CLOCK_MANAGER_RTCCCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(RTCCCLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(RTCCCLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(RTCCCLK, SL_CLOCK_MANAGER_RTCCCLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize SYSRTC clock branch. +#if defined(SYSRTC_PRESENT) +#if defined(SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE) +#if (SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(SYSRTC0CLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(SYSRTC0CLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(SYSRTC0CLK, SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize WDOG0 clock branch. +#if defined(SL_CLOCK_MANAGER_WDOG0CLK_SOURCE) +#if (SL_CLOCK_MANAGER_WDOG0CLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(WDOG0CLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(WDOG0CLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(WDOG0CLK, SL_CLOCK_MANAGER_WDOG0CLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif + + // Initialize WDOG1 clock branch. +#if WDOG_COUNT > 1 +#if defined(SL_CLOCK_MANAGER_WDOG1CLK_SOURCE) +#if (SL_CLOCK_MANAGER_WDOG1CLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(WDOG1CLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(WDOG1CLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(WDOG1CLK, SL_CLOCK_MANAGER_WDOG1CLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize LCD clock branch. +#if defined(LCD_PRESENT) +#if defined(SL_CLOCK_MANAGER_LCDCLK_SOURCE) +#if (SL_CLOCK_MANAGER_LCDCLK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(LCDCLK, CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(LCDCLK, SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION)); +#else + CLOCK_MANAGER_CLOCK_SELECT_SET(LCDCLK, SL_CLOCK_MANAGER_LCDCLK_SOURCE); +#endif +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize PCNT0 clock branch. +#if defined(PCNT_PRESENT) +#if defined(SL_CLOCK_MANAGER_PCNT0CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(PCNT0CLK, SL_CLOCK_MANAGER_PCNT0CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize EUSART0 +#if defined(EUSART_PRESENT) +#if defined(SL_CLOCK_MANAGER_EUSART0CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EUSART0CLK, SL_CLOCK_MANAGER_EUSART0CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize EUART +#if defined(EUART_PRESENT) +#if defined(SL_CLOCK_MANAGER_EUART0CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(EUART0CLK, SL_CLOCK_MANAGER_EUART0CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif +#endif + + // Initialize SYSTICK clock branch. +#if defined(SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE) +#if (SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE == 1) + CMU_CLOCK_SELECT_SET(SYSTICK, EM23GRPACLK); +#elif (SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE == 0) + CMU_CLOCK_SELECT_SET(SYSTICK, HCLK); +#else + EFM_ASSERT(false); +#endif +#else + EFM_ASSERT(false); +#endif + + // Initialize VDAC0 clock branch. +#if defined(VDAC_PRESENT) +#if defined(SL_CLOCK_MANAGER_VDAC0CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(VDAC0CLK, SL_CLOCK_MANAGER_VDAC0CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif + + // Initialize VDAC1 clock branch. +#if VDAC_COUNT > 1 +#if defined(SL_CLOCK_MANAGER_VDAC1CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(VDAC1CLK, SL_CLOCK_MANAGER_VDAC1CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif +#endif +#endif + + return SL_STATUS_OK; +} + +/******************************************************************************* + ********************** GLOBAL INTERNAL FUNCTIONS ************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initializes Oscillators and Clock branches. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_init(void) +{ + sl_status_t status; + +#if defined(SYSRTC_PRESENT) + status = sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_SYSRTC0); + if (status != SL_STATUS_OK) { + return status; + } +#endif + + // Initialize Oscillators +#if defined(LFXO_PRESENT) \ + && defined(SL_CLOCK_MANAGER_LFXO_EN) && (SL_CLOCK_MANAGER_LFXO_EN == 1) + status = init_lfxo(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(HFXO_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) + status = init_hfxo(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + + status = init_clkin0(); + if (status != SL_STATUS_OK) { + return status; + } + +#if defined(HFRCO_PRESENT) + status = init_hfrcodpll(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(HFRCOEM23_PRESENT) + status = init_hfrcoem23(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(LFRCO_PRESENT) + status = init_lfrco(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(RFFPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) + status = init_rffpll(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(USBPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) + status = init_usbpll(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + + // Initialize Clock branches + status = init_clock_branches(); + if (status != SL_STATUS_OK) { + return status; + } + + return SL_STATUS_OK; +} diff --git a/Libs/platform/service/clock_manager/src/sli_clock_manager_hal.h b/Libs/platform/service/clock_manager/src/sli_clock_manager_hal.h new file mode 100644 index 0000000..bb7e3f7 --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sli_clock_manager_hal.h @@ -0,0 +1,198 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager HAL APIs. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_HAL_H +#define SL_CLOCK_MANAGER_HAL_H + +#include "sl_clock_manager.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Performs Clock Manager runtime initialization. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_runtime_init(void); + +/***************************************************************************//** + * Gets frequency of given oscillator. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_get_oscillator_frequency(sl_oscillator_t oscillator, + uint32_t *frequency); + +/***************************************************************************//** + * Gets precision of given oscillator. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_oscillator_precision(sl_oscillator_t oscillator, + uint16_t *precision); + +/***************************************************************************//** + * Gets frequency of given clock branch. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_get_clock_branch_frequency(sl_clock_branch_t clock_branch, + uint32_t *frequency); + +/***************************************************************************//** + * Gets precision of given clock branch. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_clock_branch_precision(sl_clock_branch_t clock_branch, + uint16_t *precision); + +/***************************************************************************//** + * Enables/Disables the bus clock associated with the given module. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_enable_bus_clock(sl_bus_clock_t module, + bool enable); + +/***************************************************************************//** + * Configures the exported clock feature on CMU to output user selected + * clock source specified GPIO pin. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_gpio_clock_output(sl_clock_manager_export_clock_source_t export_clock_source, + sl_clock_manager_export_clock_output_select_t output_select, + uint16_t divider, + uint32_t port, + uint32_t pin); + +/***************************************************************************//** + * Sets the RC oscillator frequency tuning control. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t val); + +/***************************************************************************//** + * Gets the RC oscillator frequency tuning setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_rc_oscillator_calibration(sl_oscillator_t oscillator, + uint32_t *val); + +/***************************************************************************//** + * Sets the HFXO calibration value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_hfxo_calibration(uint32_t val); + +/***************************************************************************//** + * Gets the HFXO calibration value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_hfxo_calibration(uint32_t *val); + +/***************************************************************************//** + * Sets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_set_ctune(uint32_t ctune); + +/***************************************************************************//** + * Gets the HFXO CTUNE setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_get_ctune(uint32_t *ctune); + +/***************************************************************************//** + * Updates the tuning capacitances and calibrate the Core Bias Current. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_hfxo_calibrate_ctune(uint32_t ctune); + +/***************************************************************************//** + * Sets the LFXO frequency tuning control. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_set_lfxo_calibration(uint32_t val); + +/***************************************************************************//** + * Gets the LFXO frequency tuning setting. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_lfxo_calibration(uint32_t *val); + +/***************************************************************************//** + * Configures the RCO calibration. + *****************************************************************************/ +sl_status_t sli_clock_manager_hal_configure_rco_calibration(uint32_t cycles, + sl_clock_manager_clock_calibration_t down_counter_selection, + sl_clock_manager_clock_calibration_t up_counter_selection, + bool continuous_calibration); + +/***************************************************************************//** + * Starts the RCO calibration. + ******************************************************************************/ +void sli_clock_manager_hal_start_rco_calibration (void); + +/***************************************************************************//** + * Stops the RCO calibration. + ******************************************************************************/ +void sli_clock_manager_hal_stop_rco_calibration(void); + +/***************************************************************************//** + * Waits for the RCO calibration to finish. + ******************************************************************************/ +void sli_clock_manager_hal_wait_rco_calibration(void); + +/***************************************************************************//** + * Gets calibration count value. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_get_rco_calibration_count(uint32_t *count); + +/***************************************************************************//** + * Sets SYSCLK clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_set_sysclk_source(sl_oscillator_t source); + +/***************************************************************************//** + * Gets SYSCLK clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_get_sysclk_source(sl_oscillator_t *source); + +/***************************************************************************//** + * Waits for USBPLL clock to be ready. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_wait_usbpll(void); + +/***************************************************************************//** + * Sets the external FLASH reference clock. + * + * @note This API is not thread-safe and should therefore not be called + * across multiple tasks. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_set_ext_flash_clk(sl_oscillator_t oscillator); + +/***************************************************************************//** + * Gets the external FLASH clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_get_ext_flash_clk(sl_oscillator_t *oscillator); + +#ifdef __cplusplus +} +#endif + +#endif // SL_CLOCK_MANAGER_HAL_H diff --git a/Libs/platform/service/clock_manager/src/sli_clock_manager_init_hal.h b/Libs/platform/service/clock_manager/src/sli_clock_manager_init_hal.h new file mode 100644 index 0000000..04562b2 --- /dev/null +++ b/Libs/platform/service/clock_manager/src/sli_clock_manager_init_hal.h @@ -0,0 +1,111 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager Init HAL APIs. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_INIT_HAL_H +#define SL_CLOCK_MANAGER_INIT_HAL_H + +#include "sl_status.h" +#include "sl_clock_manager_tree_config.h" +#include "sl_clock_manager_oscillator_config.h" +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************** MACROS ************************************ + ******************************************************************************/ + +#if (SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION _HFRCODPLL +#elif (SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION _HFXO +#elif (SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_CONCATENATION _FSRCO +#else +#error "SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE configuration value is invalid." +#endif + +#if (SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO) +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION _LFRCO +#elif (SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO) +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION _LFXO +#elif (SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE == SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO) +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_CONCATENATION _ULFRCO +#else +#error "SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE configuration value is invalid." +#endif + +#define CLOCK_MANAGER_CLOCK_SELECT_SET(clock_branch, clock_source) \ + do { \ + CMU->clock_branch##CTRL = (CMU->clock_branch##CTRL & ~_CMU_##clock_branch##CTRL_CLKSEL_MASK) \ + | clock_source; \ + } while (0) + +#define CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE_NX(clock_branch, clock_source) CMU_##clock_branch##CTRL_CLKSEL##clock_source +#define CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(clock_branch, clock_source) CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE_NX(clock_branch, clock_source) + +#if !defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#define SLI_CLOCK_MANAGER_HFXO_MODE SL_CLOCK_MANAGER_HFXO_MODE +#define SLI_CLOCK_MANAGER_HFRCO_BAND SL_CLOCK_MANAGER_HFRCO_BAND +#endif // #if !defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + +#if defined(SL_CLOCK_MANAGER_SOCPLL_EN) && (SL_CLOCK_MANAGER_SOCPLL_EN == 1) +#if defined(SL_CLOCK_MANAGER_SOCPLL_ADVANCED_SETTINGS) && (SL_CLOCK_MANAGER_SOCPLL_ADVANCED_SETTINGS == 0) +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) || (defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1)) +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK SOCPLL_CTRL_REFCLKSEL_REF_HFXO +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ SL_CLOCK_MANAGER_HFXO_FREQ +#else +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK SOCPLL_CTRL_REFCLKSEL_REF_HFRCO +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ SL_CLOCK_MANAGER_HFRCO_BAND +#endif +#define SL_CLOCK_MANAGER_SOCPLL_FRACTIONAL_EN 1 +// SOCPLL Formula: SOCPLL_FREQ = REFCLK_FREQ * (DIVN+2 + DIVF/1024) / 6 +// SL_CLOCK_MANAGER_SOCPLL_DIVN is rounded down and SL_CLOCK_MANAGER_SOCPLL_DIVF is rounded to the closest integer. +#define SL_CLOCK_MANAGER_SOCPLL_DIVN (6ULL * SL_CLOCK_MANAGER_SOCPLL_FREQ / SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ - 2ULL) +#define SL_CLOCK_MANAGER_SOCPLL_DIVF ((6ULL * 1024ULL * SL_CLOCK_MANAGER_SOCPLL_FREQ + SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ / 2ULL) / SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ - 1024ULL * (SL_CLOCK_MANAGER_SOCPLL_DIVN + 2ULL)) +#endif +#endif + +/******************************************************************************* + ****************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initializes Oscillators and Clock branches. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_init(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_CLOCK_MANAGER_INIT_HAL_H diff --git a/Libs/platform/service/device_init/inc/sl_device_init_dcdc.h b/Libs/platform/service/device_init/inc/sl_device_init_dcdc.h new file mode 100644 index 0000000..bfa0e9e --- /dev/null +++ b/Libs/platform/service/device_init/inc/sl_device_init_dcdc.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_DCDC_H +#define SL_DEVICE_INIT_DCDC_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_dcdc DCDC Initialization + * @brief Initialize the DC-DC converter. + * @details + * Configures the DC-DC converter. If the DC-DC converter is not to be + * used, the configuration option `SL_DEVICE_INIT_DCDC_ENABLE` can be disabled, + * and the converter will be powered off. On Series 1 devices, this option + * should only be used when DVDD is externally powered. + * + * To enable the bypass switch and short the DC-DC converter input to + * the DC-DC output, set the configuration option `SL_DEVICE_INIT_DCDC_BYPASS`. + * + * See **AN0948 Power Configurations and DC-DC** for further details about DC-DC + * converter configuration and operation. + * + * - Series 1: [AN0948](https://www.silabs.com/documents/public/application-notes/an0948-power-configurations-and-dcdc.pdf) + * - Series 2: [AN0948.2](https://www.silabs.com/documents/public/application-notes/an0948.2-efr32-series-2-power-configurations-and-dcdc.pdf) + * @{ + */ + +// ----------------------------------------------------------------------------- +// Defines + +/// @brief DC/DC Converter Type +#define SL_DEVICE_INIT_DCDC_TYPE_BUCK 0 ///< Buck Type +#define SL_DEVICE_INIT_DCDC_TYPE_BOOST 1 ///< Boost Type + +/** + * Initialize DCDC + * + * @details + * Configure and start the DCDC + * + * @return Status code + * @retval SL_STATUS_OK DC-DC converter initialized successfully + */ +sl_status_t sl_device_init_dcdc(void); + +/** + * @} device_init_dcdc + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_DCDC_H diff --git a/Libs/platform/service/device_init/src/sl_device_init_dcdc_s2.c b/Libs/platform/service/device_init/src/sl_device_init_dcdc_s2.c new file mode 100644 index 0000000..d00ada8 --- /dev/null +++ b/Libs/platform/service/device_init/src/sl_device_init_dcdc_s2.c @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_dcdc.h" +#include "sl_device_init_dcdc_config.h" + +#include "em_emu.h" + +sl_status_t sl_device_init_dcdc(void) +{ +#if !defined(SL_DEVICE_INIT_DCDC_TYPE) || (defined(SL_DEVICE_INIT_DCDC_TYPE) && (SL_DEVICE_INIT_DCDC_TYPE == SL_DEVICE_INIT_DCDC_TYPE_BUCK)) +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; +#if SL_DEVICE_INIT_DCDC_BYPASS + dcdcInit.mode = emuDcdcMode_Bypass; +#endif + EMU_DCDCInit(&dcdcInit); +#if SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE + EMU_DCDCSetPFMXModePeakCurrent(SL_DEVICE_INIT_DCDC_PFMX_IPKVAL); +#endif +#else // SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCPowerOff(); +#endif // SL_DEVICE_INIT_DCDC_ENABLE +#else // SL_DEVICE_INIT_DCDC_TYPE +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + dcdcBoostInit.outputVoltage = SL_DEVICE_INIT_DCDC_BOOST_OUTPUT; +#endif + EMU_DCDCBoostInit(&dcdcBoostInit); +#endif +#endif //SL_DEVICE_INIT_DCDC_TYPE + return SL_STATUS_OK; +} diff --git a/Libs/platform/service/device_manager/clocks/sl_device_clock_efr32xg24.c b/Libs/platform/service/device_manager/clocks/sl_device_clock_efr32xg24.c new file mode 100644 index 0000000..082ff3a --- /dev/null +++ b/Libs/platform/service/device_manager/clocks/sl_device_clock_efr32xg24.c @@ -0,0 +1,339 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Clock Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "em_device.h" +#include "sl_device_clock.h" + +/***************************************************************************//** + * @addtogroup device_clock Device Manager Clock + * @{ + ******************************************************************************/ + +#if defined(_CMU_CLKEN1_ACMP0_SHIFT) +// Define ACMP0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ACMP0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ACMP0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_ACMP1_SHIFT) +// Define ACMP1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ACMP1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ACMP1_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_AGC_SHIFT) +// Define AGC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_AGC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_AGC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_AMUXCP0_SHIFT) +// Define AMUXCP0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_AMUXCP0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_BUFC_SHIFT) +// Define BUFC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BUFC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_BUFC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_BURAM_SHIFT) +// Define BURAM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BURAM_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURAM_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_BURTC_SHIFT) +// Define BURTC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BURTC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURTC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_DCDC_SHIFT) +// Define DCDC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DCDC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DCDC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_DMEM_SHIFT) +// Define DMEM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DMEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_DMEM_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_DPLL0_SHIFT) +// Define DPLL0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DPLL0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DPLL0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_ECAIFADC_SHIFT) +// Define ECAIFADC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ECAIFADC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_EUSART0_SHIFT) +// Define EUSART0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_EUSART0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_EUSART1_SHIFT) +// Define EUSART1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_EUSART1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART1_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_FRC_SHIFT) +// Define FRC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_FRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_FRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_FSRCO_SHIFT) +// Define FSRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_FSRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_FSRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_GPCRC_SHIFT) +// Define GPCRC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPCRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_GPIO_SHIFT) +// Define GPIO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_GPIO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPIO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_HFRCO0_SHIFT) +// Define HFRCO0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFRCO0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_HFRCOEM23_SHIFT) +// Define HFRCOEM23 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFRCOEM23_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_HFXO0_SHIFT) +// Define HFXO0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HFXO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFXO0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_HOSTMAILBOX_SHIFT) +// Define HOSTMAILBOX peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_HOSTMAILBOX_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_I2C0_SHIFT) +// Define I2C0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_I2C0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_I2C1_SHIFT) +// Define I2C1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_I2C1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_IADC0_SHIFT) +// Define IADC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_IADC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_IADC0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_ICACHE0_SHIFT) +// Define ICACHE0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ICACHE0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_KEYSCAN_SHIFT) +// Define KEYSCAN peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_KEYSCAN_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LDMA_SHIFT) +// Define LDMA0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LDMA0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMA_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LDMAXBAR_SHIFT) +// Define LDMAXBAR0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMAXBAR_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LETIMER0_SHIFT) +// Define LETIMER0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LETIMER0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LFRCO_SHIFT) +// Define LFRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LFXO_SHIFT) +// Define LFXO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LFXO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFXO_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_MODEM_SHIFT) +// Define MODEM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_MODEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MODEM_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_MSC_SHIFT) +// Define MSC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_MSC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MSC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_MVP_SHIFT) +// Define MVP peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_MVP_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MVP_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_PCNT0_SHIFT) +// Define PCNT0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PCNT0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PCNT0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_PROTIMER_SHIFT) +// Define PROTIMER peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PROTIMER_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_PRS_SHIFT) +// Define PRS peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PRS_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_PRS_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RAC_SHIFT) +// Define RAC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RAC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RAC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_RADIOAES_SHIFT) +// Define RADIOAES peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_RADIOAES_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFCRC_SHIFT) +// Define RFCRC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFCRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFCRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFECA0_SHIFT) +// Define RFECA0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFECA0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFECA0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFECA1_SHIFT) +// Define RFECA1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFECA1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFECA1_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFMAILBOX_SHIFT) +// Define RFMAILBOX peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFMAILBOX_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFSCRATCHPAD_SHIFT) +// Define RFSCRATCHPAD peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFSCRATCHPAD_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SEMAILBOXHOST_SHIFT) +// Define SEMAILBOX peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SEMAILBOXHOST_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SMU_SHIFT) +// Define SMU peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SMU_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SMU_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SYNTH_SHIFT) +// Define SYNTH peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SYNTH_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SYNTH_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_SYSCFG_SHIFT) +// Define SYSCFG peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_SYSCFG_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_SYSRTC0_SHIFT) +// Define SYSRTC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_SYSRTC0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER0_SHIFT) +// Define TIMER0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER1_SHIFT) +// Define TIMER1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER2_SHIFT) +// Define TIMER2 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER2_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER2_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER3_SHIFT) +// Define TIMER3 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER3_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER3_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER4_SHIFT) +// Define TIMER4 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER4_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER4_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_ULFRCO_SHIFT) +// Define ULFRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_ULFRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_USART0_SHIFT) +// Define USART0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_USART0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_USART0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_VDAC0_SHIFT) +// Define VDAC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_VDAC0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_VDAC0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_VDAC1_SHIFT) +// Define VDAC1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_VDAC1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_VDAC1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_WDOG0_SHIFT) +// Define WDOG0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_WDOG0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_WDOG0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_WDOG1_SHIFT) +// Define WDOG1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_WDOG1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_WDOG1_SHIFT; +#endif + +/** @} (end addtogroup device_clock) */ diff --git a/Libs/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c b/Libs/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c new file mode 100644 index 0000000..c053f3d --- /dev/null +++ b/Libs/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Peripheral Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "em_device.h" +#include "sl_device_peripheral.h" +#include "sl_device_clock.h" + +/***************************************************************************//** + * @addtogroup device_peripheral Device Abstraction Peripheral + * @{ + ******************************************************************************/ + +#if defined(ACMP0_BASE) +// Define peripheral ACMP0. +const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ACMP0 }; +#endif + +#if defined(ACMP1_BASE) +// Define peripheral ACMP1. +const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = ACMP1_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ACMP1 }; +#endif + +#if defined(BURAM_BASE) +// Define peripheral BURAM. +const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_BURAM }; +#endif + +#if defined(BURTC_BASE) +// Define peripheral BURTC. +const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM4GRPACLK, + .bus_clock = SL_BUS_CLOCK_BURTC }; +#endif + +#if defined(CMU_BASE) +// Define peripheral CMU. +const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; +#endif + +#if defined(DCDC_BASE) +// Define peripheral DCDC. +const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_DCDC }; +#endif + +#if defined(DMEM_BASE) +// Define peripheral DMEM. +const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_DMEM }; +#endif + +#if defined(DPLL0_BASE) +// Define peripheral DPLL0. +const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE, + .clk_branch = SL_CLOCK_BRANCH_DPLLREFCLK, + .bus_clock = SL_BUS_CLOCK_DPLL0 }; +#endif + +#if defined(EMU_BASE) +// Define peripheral EMU. +const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; +#endif + +#if defined(EUSART0_BASE) +// Define peripheral EUSART0. +const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EUSART0CLK, + .bus_clock = SL_BUS_CLOCK_EUSART0 }; +#endif + +#if defined(EUSART1_BASE) +// Define peripheral EUSART1. +const sl_peripheral_val_t sl_peripheral_val_eusart1 = { .base = EUSART1_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPCCLK, + .bus_clock = SL_BUS_CLOCK_EUSART1 }; +#endif + +#if defined(FSRCO_BASE) +// Define peripheral FSRCO. +const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = FSRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_FSRCO }; +#endif + +#if defined(GPCRC_BASE) +// Define peripheral GPCRC0. +const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = GPCRC_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_GPCRC0 }; +#endif + +#if defined(GPIO_BASE) +// Define peripheral GPIO. +const sl_peripheral_val_t sl_peripheral_val_gpio = { .base = GPIO_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_GPIO }; +#endif + +#if defined(HFRCO0_BASE) +// Define peripheral HFRCO0. +const sl_peripheral_val_t sl_peripheral_val_hfrco0 = { .base = HFRCO0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_HFRCO0 }; +#endif + +#if defined(HFRCOEM23_BASE) +// Define peripheral HFRCOEM23. +const sl_peripheral_val_t sl_peripheral_val_hfrcoem23 = { .base = HFRCOEM23_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_HFRCOEM23 }; +#endif + +#if defined(HFXO0_BASE) +// Define peripheral HFXO0. +const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_HFXO0 }; +#endif + +#if defined(HOSTMAILBOX_BASE) +// Define peripheral HOSTMAILBOX. +const sl_peripheral_val_t sl_peripheral_val_hostmailbox = { .base = HOSTMAILBOX_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_HOSTMAILBOX }; +#endif + +#if defined(I2C0_BASE) +// Define peripheral I2C0. +const sl_peripheral_val_t sl_peripheral_val_i2c0 = { .base = I2C0_BASE, + .clk_branch = SL_CLOCK_BRANCH_LSPCLK, + .bus_clock = SL_BUS_CLOCK_I2C0 }; +#endif + +#if defined(I2C1_BASE) +// Define peripheral I2C1. +const sl_peripheral_val_t sl_peripheral_val_i2c1 = { .base = I2C1_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_I2C1 }; +#endif + +#if defined(IADC0_BASE) +// Define peripheral IADC0. +const sl_peripheral_val_t sl_peripheral_val_iadc0 = { .base = IADC0_BASE, + .clk_branch = SL_CLOCK_BRANCH_IADCCLK, + .bus_clock = SL_BUS_CLOCK_IADC0 }; +#endif + +#if defined(ICACHE0_BASE) +// Define peripheral ICACHE0. +const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ICACHE0 }; +#endif + +#if defined(KEYSCAN_BASE) +// Define peripheral KEYSCAN. +const sl_peripheral_val_t sl_peripheral_val_keyscan = { .base = KEYSCAN_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_KEYSCAN }; +#endif + +#if defined(LDMA_BASE) +// Define peripheral LDMA0. +const sl_peripheral_val_t sl_peripheral_val_ldma0 = { .base = LDMA_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_LDMA0 }; +#endif + +#if defined(LDMAXBAR_BASE) +// Define peripheral LDMAXBAR0. +const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0 = { .base = LDMAXBAR_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_LDMAXBAR0 }; +#endif + +#if defined(LETIMER0_BASE) +// Define peripheral LETIMER0. +const sl_peripheral_val_t sl_peripheral_val_letimer0 = { .base = LETIMER0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM23GRPACLK, + .bus_clock = SL_BUS_CLOCK_LETIMER0 }; +#endif + +#if defined(LFRCO_BASE) +// Define peripheral LFRCO. +const sl_peripheral_val_t sl_peripheral_val_lfrco = { .base = LFRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_LFRCO }; +#endif + +#if defined(LFXO_BASE) +// Define peripheral LFXO. +const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = LFXO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_LFXO }; +#endif + +#if defined(MSC_BASE) +// Define peripheral MSC. +const sl_peripheral_val_t sl_peripheral_val_msc = { .base = MSC_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_MSC }; +#endif + +#if defined(MVP_BASE) +// Define peripheral MVP. +const sl_peripheral_val_t sl_peripheral_val_mvp = { .base = MVP_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_MVP }; +#endif + +#if defined(PCNT0_BASE) +// Define peripheral PCNT0. +const sl_peripheral_val_t sl_peripheral_val_pcnt0 = { .base = PCNT0_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCNT0CLK, + .bus_clock = SL_BUS_CLOCK_PCNT0 }; +#endif + +#if defined(PRS_BASE) +// Define peripheral PRS. +const sl_peripheral_val_t sl_peripheral_val_prs = { .base = PRS_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_PRS }; +#endif + +#if defined(RADIOAES_BASE) +// Define peripheral RADIOAES. +const sl_peripheral_val_t sl_peripheral_val_radioaes = { .base = RADIOAES_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_RADIOAES }; +#endif + +#if defined(SCRATCHPAD_BASE) +// Define peripheral SCRATCHPAD. +const sl_peripheral_val_t sl_peripheral_val_scratchpad = { .base = SCRATCHPAD_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_INVALID }; +#endif + +#if defined(SEMAILBOX_HOST_BASE) +// Define peripheral SEMAILBOX. +const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; +#endif + +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + +#if defined(SYSCFG_BASE) +// Define peripheral SYSCFG. +const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SYSCFG }; +#endif + +#if defined(SYSRTC0_BASE) +// Define peripheral SYSRTC0. +const sl_peripheral_val_t sl_peripheral_val_sysrtc0 = { .base = SYSRTC0_BASE, + .clk_branch = SL_CLOCK_BRANCH_SYSRTCCLK, + .bus_clock = SL_BUS_CLOCK_SYSRTC0 }; +#endif + +#if defined(TIMER0_BASE) +// Define peripheral TIMER0. +const sl_peripheral_val_t sl_peripheral_val_timer0 = { .base = TIMER0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER0 }; +#endif + +#if defined(TIMER1_BASE) +// Define peripheral TIMER1. +const sl_peripheral_val_t sl_peripheral_val_timer1 = { .base = TIMER1_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER1 }; +#endif + +#if defined(TIMER2_BASE) +// Define peripheral TIMER2. +const sl_peripheral_val_t sl_peripheral_val_timer2 = { .base = TIMER2_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER2 }; +#endif + +#if defined(TIMER3_BASE) +// Define peripheral TIMER3. +const sl_peripheral_val_t sl_peripheral_val_timer3 = { .base = TIMER3_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER3 }; +#endif + +#if defined(TIMER4_BASE) +// Define peripheral TIMER4. +const sl_peripheral_val_t sl_peripheral_val_timer4 = { .base = TIMER4_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER4 }; +#endif + +#if defined(ULFRCO_BASE) +// Define peripheral ULFRCO. +const sl_peripheral_val_t sl_peripheral_val_ulfrco = { .base = ULFRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ULFRCO }; +#endif + +#if defined(USART0_BASE) +// Define peripheral USART0. +const sl_peripheral_val_t sl_peripheral_val_usart0 = { .base = USART0_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_USART0 }; +#endif + +#if defined(VDAC0_BASE) +// Define peripheral VDAC0. +const sl_peripheral_val_t sl_peripheral_val_vdac0 = { .base = VDAC0_BASE, + .clk_branch = SL_CLOCK_BRANCH_VDAC0CLK, + .bus_clock = SL_BUS_CLOCK_VDAC0 }; +#endif + +#if defined(VDAC1_BASE) +// Define peripheral VDAC1. +const sl_peripheral_val_t sl_peripheral_val_vdac1 = { .base = VDAC1_BASE, + .clk_branch = SL_CLOCK_BRANCH_VDAC1CLK, + .bus_clock = SL_BUS_CLOCK_VDAC1 }; +#endif + +#if defined(WDOG0_BASE) +// Define peripheral WDOG0. +const sl_peripheral_val_t sl_peripheral_val_wdog0 = { .base = WDOG0_BASE, + .clk_branch = SL_CLOCK_BRANCH_WDOG0CLK, + .bus_clock = SL_BUS_CLOCK_WDOG0 }; +#endif + +#if defined(WDOG1_BASE) +// Define peripheral WDOG1. +const sl_peripheral_val_t sl_peripheral_val_wdog1 = { .base = WDOG1_BASE, + .clk_branch = SL_CLOCK_BRANCH_WDOG1CLK, + .bus_clock = SL_BUS_CLOCK_WDOG1 }; +#endif + +/** @} (end addtogroup device_peripheral) */ diff --git a/Libs/platform/service/device_manager/inc/sl_device_clock.h b/Libs/platform/service/device_manager/inc/sl_device_clock.h new file mode 100644 index 0000000..e35bb26 --- /dev/null +++ b/Libs/platform/service/device_manager/inc/sl_device_clock.h @@ -0,0 +1,806 @@ +/***************************************************************************//** + * @file + * @brief Device Manager Clocks. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SL_DEVICE_CLOCK_H +#define SL_DEVICE_CLOCK_H + +#include "sl_enum.h" +#include + +#if defined(DEVICE_CLOCK_INTERNAL_PRESENT) +#include "sli_device_clock_internal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup device_clock Device Manager Clock + * @details + * ## Overview + * + * The Device Manager Clock module defines the different oscillators, + * clock branches and bus clock values that exist across all Silicon Labs + * devices. + * + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// ENUMS + +/// Oscillators +SL_ENUM(sl_oscillator_t) { + SL_OSCILLATOR_FSRCO, ///< FSRCO Oscillator + SL_OSCILLATOR_HFRCODPLL, ///< HFRCODPLL Oscillator + SL_OSCILLATOR_HFXO, ///< HFXO Oscillator + SL_OSCILLATOR_HFRCOEM23, ///< HFRCOEM23 Oscillator + SL_OSCILLATOR_RFFPLL, ///< RFFPLL Oscillator + SL_OSCILLATOR_USBPLL, ///< USBPLL Oscillator + SL_OSCILLATOR_SOCPLL, ///< SOCPLL Oscillator + SL_OSCILLATOR_LFXO, ///< LFXO Oscillator + SL_OSCILLATOR_LFRCO, ///< LFRCO Oscillator + SL_OSCILLATOR_ULFRCO, ///< ULFRCO Oscillator + SL_OSCILLATOR_CLKIN0, ///< CLKIN0 Oscillator + SL_OSCILLATOR_FLPLL ///< FLPLL Oscillator +}; + +/// Clock Branches +SL_ENUM(sl_clock_branch_t) { + SL_CLOCK_BRANCH_SYSCLK, ///< SYSCLK Clock Branch + SL_CLOCK_BRANCH_HCLK, ///< HCLK Clock Branch + SL_CLOCK_BRANCH_HCLKRADIO, ///< HCLK Radio Clock Branch + SL_CLOCK_BRANCH_PCLK, ///< PCLK Clock Branch + SL_CLOCK_BRANCH_LSPCLK, ///< LSPCLK Clock Branch + SL_CLOCK_BRANCH_TRACECLK, ///< TRACECLK Clock Branch + SL_CLOCK_BRANCH_ADCCLK, ///< ADCCLK Clock Branch + SL_CLOCK_BRANCH_EXPORTCLK, ///< EXPORTCLK Clock Branch + SL_CLOCK_BRANCH_EM01GRPACLK, ///< EM01GRPACLK Clock Branch + SL_CLOCK_BRANCH_EM01GRPBCLK, ///< EM01GRPBCLK Clock Branch + SL_CLOCK_BRANCH_EM01GRPCCLK, ///< EM01GRPCCLK Clock Branch + SL_CLOCK_BRANCH_EM01GRPDCLK, ///< EM01GRPDCLK Clock Branch + SL_CLOCK_BRANCH_EM23GRPACLK, ///< EM23GRPACLK Clock Branch + SL_CLOCK_BRANCH_EM4GRPACLK, ///< EM4GRPACLK Clock Branch + SL_CLOCK_BRANCH_QSPISYSCLK, ///< QSPISYSCLK Clock Branch + SL_CLOCK_BRANCH_IADCCLK, ///< IADCCLK Clock Branch + SL_CLOCK_BRANCH_WDOG0CLK, ///< WDOG0CLK Clock Branch + SL_CLOCK_BRANCH_WDOG1CLK, ///< WDOG1CLK Clock Branch + SL_CLOCK_BRANCH_RTCCCLK, ///< RTCCCLK Clock Branch + SL_CLOCK_BRANCH_SYSRTCCLK, ///< SYSRTCCLK Clock Branch + SL_CLOCK_BRANCH_EUART0CLK, ///< EUART0CLK Clock Branch + SL_CLOCK_BRANCH_EUSART0CLK, ///< EUSART0CLK Clock Branch + SL_CLOCK_BRANCH_DPLLREFCLK, ///< DPLLREFCLK Clock Branch + SL_CLOCK_BRANCH_I2C0CLK, ///< I2C0CLK Clock Branch + SL_CLOCK_BRANCH_LCDCLK, ///< LCDCLK Clock Branch + SL_CLOCK_BRANCH_PIXELRZCLK, ///< PIXELRZCLK Clock Branch + SL_CLOCK_BRANCH_PCNT0CLK, ///< PCNT0CLK Clock Branch + SL_CLOCK_BRANCH_PRORTCCLK, ///< PCNT0CLK Clock Branch + SL_CLOCK_BRANCH_SYSTICKCLK, ///< SYSTICKCLK Clock Branch + SL_CLOCK_BRANCH_LESENSEHFCLK, ///< LESENSEHFCLK Clock Branch + SL_CLOCK_BRANCH_VDAC0CLK, ///< VDAC0CLK Clock Branch + SL_CLOCK_BRANCH_VDAC1CLK, ///< VDAC1CLK Clock Branch + SL_CLOCK_BRANCH_USB0CLK, ///< USB0CLK Clock Branch + SL_CLOCK_BRANCH_FLPLLREFCLK, ///< FLPLLREFCLK Clock Branch + SL_CLOCK_BRANCH_INVALID ///< INVALID Clock Branch +}; + +// ---------------------------------------------------------------------------- +// DEFINES + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +// CLKEN bitfield shift in bus clock value. +#define _BUS_CLOCK_CLKEN_BIT_SHIFT 0 + +// CLKEN bitfield mask in bus clock value. +#define _BUS_CLOCK_CLKEN_BIT_MASK 0x3FUL + +// CLKENx register number shift in bus clock value. +#define _BUS_CLOCK_CLKENX_SHIFT 6 + +// CLKENx register number mask in bus clock value. +#define _BUS_CLOCK_CLKENX_MASK 0x1C0UL + +// CLKEN0 value in bus clock. +#define BUS_CLOCK_CLKEN0 0x0UL + +// CLKEN1 value in bus clock. +#define BUS_CLOCK_CLKEN1 0x1UL + +// CLKEN2 value in bus clock. +#define BUS_CLOCK_CLKEN2 0x2UL + +// CLKENHV value in bus clock. +#define BUS_CLOCK_CLKENHV 0x3UL + +/// @endcond + +/***************************************************************************//** + * @name Bus Clock Defines + * Those defines can be used as constant of type sl_bus_clock_t and thus can + * be used as argument for function sl_clock_manager_enable_bus_clock() and + * sl_clock_manager_disable_bus_clock() in @ref clock_manager. + * The values of those defines are device specific. + * @{ + ******************************************************************************/ + +/// Define for INVALID peripheral bus clock pointer. +#define SL_BUS_CLOCK_INVALID (0) + +/// Define for ACMP0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_ACMP0 (&SL_BUS_CLOCK_ACMP0_VALUE) + +/// Define for ACMP1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_ACMP1 (&SL_BUS_CLOCK_ACMP1_VALUE) + +/// Define for ADC0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_ADC0 (&SL_BUS_CLOCK_ADC0_VALUE) + +/// Define for AGC peripheral bus clock pointer. +#define SL_BUS_CLOCK_AGC (&SL_BUS_CLOCK_AGC_VALUE) + +/// Define for AMUXCP0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_AMUXCP0 (&SL_BUS_CLOCK_AMUXCP0_VALUE) + +/// Define for BUFC peripheral bus clock pointer. +#define SL_BUS_CLOCK_BUFC (&SL_BUS_CLOCK_BUFC_VALUE) + +/// Define for BURAM peripheral bus clock pointer. +#define SL_BUS_CLOCK_BURAM (&SL_BUS_CLOCK_BURAM_VALUE) + +/// Define for BURTC peripheral bus clock pointer. +#define SL_BUS_CLOCK_BURTC (&SL_BUS_CLOCK_BURTC_VALUE) + +/// Define for CRYPTOACC peripheral bus clock pointer. +#define SL_BUS_CLOCK_CRYPTOACC (&SL_BUS_CLOCK_CRYPTOACC_VALUE) + +/// Define for DCDC peripheral bus clock pointer. +#define SL_BUS_CLOCK_DCDC (&SL_BUS_CLOCK_DCDC_VALUE) + +/// Define for DEVINFO peripheral bus clock pointer. +#define SL_BUS_CLOCK_DEVINFO (&SL_BUS_CLOCK_DEVINFO_VALUE) + +/// Define for DMEM peripheral bus clock pointer. +#define SL_BUS_CLOCK_DMEM (&SL_BUS_CLOCK_DMEM_VALUE) + +/// Define for DPLL0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_DPLL0 (&SL_BUS_CLOCK_DPLL0_VALUE) + +/// Define for ECAIFADC peripheral bus clock pointer. +#define SL_BUS_CLOCK_ECAIFADC (&SL_BUS_CLOCK_ECAIFADC_VALUE) + +/// Define for ETAMPDET peripheral bus clock pointer. +#define SL_BUS_CLOCK_ETAMPDET (&SL_BUS_CLOCK_ETAMPDET_VALUE) + +/// Define for EUART0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUART0 (&SL_BUS_CLOCK_EUART0_VALUE) + +/// Define for EUSART0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUSART0 (&SL_BUS_CLOCK_EUSART0_VALUE) + +/// Define for EUSART1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUSART1 (&SL_BUS_CLOCK_EUSART1_VALUE) + +/// Define for EUSART2 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUSART2 (&SL_BUS_CLOCK_EUSART2_VALUE) + +/// Define for EUSART3 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUSART3 (&SL_BUS_CLOCK_EUSART3_VALUE) + +/// Define for EUSART4 peripheral bus clock pointer. +#define SL_BUS_CLOCK_EUSART4 (&SL_BUS_CLOCK_EUSART4_VALUE) + +/// Define for FRC peripheral bus clock pointer. +#define SL_BUS_CLOCK_FRC (&SL_BUS_CLOCK_FRC_VALUE) + +/// Define for FSRCO peripheral bus clock pointer. +#define SL_BUS_CLOCK_FSRCO (&SL_BUS_CLOCK_FSRCO_VALUE) + +/// Define for GPCRC0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_GPCRC0 (&SL_BUS_CLOCK_GPCRC0_VALUE) + +/// Define for GPIO peripheral bus clock pointer. +#define SL_BUS_CLOCK_GPIO (&SL_BUS_CLOCK_GPIO_VALUE) + +/// Define for HFRCO0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_HFRCO0 (&SL_BUS_CLOCK_HFRCO0_VALUE) + +/// Define for HFRCOEM23 peripheral bus clock pointer. +#define SL_BUS_CLOCK_HFRCOEM23 (&SL_BUS_CLOCK_HFRCOEM23_VALUE) + +/// Define for HFXO0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_HFXO0 (&SL_BUS_CLOCK_HFXO0_VALUE) + +/// Define for HOSTMAILBOX peripheral bus clock pointer. +#define SL_BUS_CLOCK_HOSTMAILBOX (&SL_BUS_CLOCK_HOSTMAILBOX_VALUE) + +/// Define for HOSTPORTAL peripheral bus clock pointer. +#define SL_BUS_CLOCK_HOSTPORTAL (&SL_BUS_CLOCK_HOSTPORTAL_VALUE) + +/// Define for I2C0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_I2C0 (&SL_BUS_CLOCK_I2C0_VALUE) + +/// Define for I2C1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_I2C1 (&SL_BUS_CLOCK_I2C1_VALUE) + +/// Define for I2C2 peripheral bus clock pointer. +#define SL_BUS_CLOCK_I2C2 (&SL_BUS_CLOCK_I2C2_VALUE) + +/// Define for I2C3 peripheral bus clock pointer. +#define SL_BUS_CLOCK_I2C3 (&SL_BUS_CLOCK_I2C3_VALUE) + +/// Define for IADC0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_IADC0 (&SL_BUS_CLOCK_IADC0_VALUE) + +/// Define for ICACHE0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_ICACHE0 (&SL_BUS_CLOCK_ICACHE0_VALUE) + +/// Define for IFADCDEBUG peripheral bus clock pointer. +#define SL_BUS_CLOCK_IFADCDEBUG (&SL_BUS_CLOCK_IFADCDEBUG_VALUE) + +/// Define for KEYSCAN peripheral bus clock pointer. +#define SL_BUS_CLOCK_KEYSCAN (&SL_BUS_CLOCK_KEYSCAN_VALUE) + +/// Define for KSU peripheral bus clock pointer. +#define SL_BUS_CLOCK_KSU (&SL_BUS_CLOCK_KSU_VALUE) + +/// Define for L2ICACHE0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_L2ICACHE0 (&SL_BUS_CLOCK_L2ICACHE0_VALUE) + +/// Define for LCD peripheral bus clock pointer. +#define SL_BUS_CLOCK_LCD (&SL_BUS_CLOCK_LCD_VALUE) + +/// Define for LDMA0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_LDMA0 (&SL_BUS_CLOCK_LDMA0_VALUE) + +/// Define for LDMAXBAR0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_LDMAXBAR0 (&SL_BUS_CLOCK_LDMAXBAR0_VALUE) + +/// Define for LEDDRV0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_LEDDRV0 (&SL_BUS_CLOCK_LEDDRV0_VALUE) + +/// Define for LESENSE peripheral bus clock pointer. +#define SL_BUS_CLOCK_LESENSE (&SL_BUS_CLOCK_LESENSE_VALUE) + +/// Define for LETIMER0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_LETIMER0 (&SL_BUS_CLOCK_LETIMER0_VALUE) + +/// Define for LFRCO peripheral bus clock pointer. +#define SL_BUS_CLOCK_LFRCO (&SL_BUS_CLOCK_LFRCO_VALUE) + +/// Define for LFXO peripheral bus clock pointer. +#define SL_BUS_CLOCK_LFXO (&SL_BUS_CLOCK_LFXO_VALUE) + +/// Define for LPWAES peripheral bus clock pointer. +#define SL_BUS_CLOCK_LPWAES (&SL_BUS_CLOCK_LPWAES_VALUE) + +/// Define for LPW0PORTAL peripheral bus clock pointer. +#define SL_BUS_CLOCK_LPW0PORTAL (&SL_BUS_CLOCK_LPW0PORTAL_VALUE) + +/// Define for MODEM peripheral bus clock pointer. +#define SL_BUS_CLOCK_MODEM (&SL_BUS_CLOCK_MODEM_VALUE) + +/// Define for MSC peripheral bus clock pointer. +#define SL_BUS_CLOCK_MSC (&SL_BUS_CLOCK_MSC_VALUE) + +/// Define for MVP peripheral bus clock pointer. +#define SL_BUS_CLOCK_MVP (&SL_BUS_CLOCK_MVP_VALUE) + +/// Define for PCNT0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_PCNT0 (&SL_BUS_CLOCK_PCNT0_VALUE) + +/// Define for PDM peripheral bus clock pointer. +#define SL_BUS_CLOCK_PDM (&SL_BUS_CLOCK_PDM_VALUE) + +/// Define for PIXELRZ0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_PIXELRZ0 (&SL_BUS_CLOCK_PIXELRZ0_VALUE) + +/// Define for PIXELRZ1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_PIXELRZ1 (&SL_BUS_CLOCK_PIXELRZ1_VALUE) + +/// Define for PRORTC peripheral bus clock pointer. +#define SL_BUS_CLOCK_PRORTC (&SL_BUS_CLOCK_PRORTC_VALUE) + +/// Define for PROTIMER peripheral bus clock pointer. +#define SL_BUS_CLOCK_PROTIMER (&SL_BUS_CLOCK_PROTIMER_VALUE) + +/// Define for PRS peripheral bus clock pointer. +#define SL_BUS_CLOCK_PRS (&SL_BUS_CLOCK_PRS_VALUE) + +/// Define for RAC peripheral bus clock pointer. +#define SL_BUS_CLOCK_RAC (&SL_BUS_CLOCK_RAC_VALUE) + +/// Define for RADIOAES peripheral bus clock pointer. +#define SL_BUS_CLOCK_RADIOAES (&SL_BUS_CLOCK_RADIOAES_VALUE) + +/// Define for RDMAILBOX0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_RDMAILBOX0 (&SL_BUS_CLOCK_RDMAILBOX0_VALUE) + +/// Define for RDMAILBOX1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_RDMAILBOX1 (&SL_BUS_CLOCK_RDMAILBOX1_VALUE) + +/// Define for RDSCRATCHPAD peripheral bus clock pointer. +#define SL_BUS_CLOCK_RDSCRATCHPAD (&SL_BUS_CLOCK_RDSCRATCHPAD_VALUE) + +/// Define for RFCRC peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFCRC (&SL_BUS_CLOCK_RFCRC_VALUE) + +/// Define for RFECA0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFECA0 (&SL_BUS_CLOCK_RFECA0_VALUE) + +/// Define for RFECA1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFECA1 (&SL_BUS_CLOCK_RFECA1_VALUE) + +/// Define for RFFPLL0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFFPLL0 (&SL_BUS_CLOCK_RFFPLL0_VALUE) + +/// Define for RFMAILBOX peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFMAILBOX (&SL_BUS_CLOCK_RFMAILBOX_VALUE) + +/// Define for RFSCRATCHPAD peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFSCRATCHPAD (&SL_BUS_CLOCK_RFSCRATCHPAD_VALUE) + +/// Define for RFSENSE peripheral bus clock pointer. +#define SL_BUS_CLOCK_RFSENSE (&SL_BUS_CLOCK_RFSENSE_VALUE) + +/// Define for RPA peripheral bus clock pointer. +#define SL_BUS_CLOCK_RPA (&SL_BUS_CLOCK_RPA_VALUE) + +/// Define for RTCC peripheral bus clock pointer. +#define SL_BUS_CLOCK_RTCC (&SL_BUS_CLOCK_RTCC_VALUE) + +/// Define for SCRATCHPAD peripheral bus clock pointer. +#define SL_BUS_CLOCK_SCRATCHPAD (&SL_BUS_CLOCK_SCRATCHPAD_VALUE) + +/// Define for SEMAILBOX peripheral bus clock pointer. +#define SL_BUS_CLOCK_SEMAILBOX (&SL_BUS_CLOCK_SEMAILBOX_VALUE) + +/// Define for SEMAPHORE0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_SEMAPHORE0 (&SL_BUS_CLOCK_SEMAPHORE0_VALUE) + +/// Define for SEMAPHORE1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_SEMAPHORE1 (&SL_BUS_CLOCK_SEMAPHORE1_VALUE) + +/// Define for SEPORTAL peripheral bus clock pointer. +#define SL_BUS_CLOCK_SEPORTAL (&SL_BUS_CLOCK_SEPORTAL_VALUE) + +/// Define for SMU peripheral bus clock pointer. +#define SL_BUS_CLOCK_SMU (&SL_BUS_CLOCK_SMU_VALUE) + +/// Define for SOCPLL0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_SOCPLL0 (&SL_BUS_CLOCK_SOCPLL0_VALUE) + +/// Define for SYMCRYPTO peripheral bus clock pointer. +#define SL_BUS_CLOCK_SYMCRYPTO (&SL_BUS_CLOCK_SYMCRYPTO_VALUE) + +/// Define for SYNTH peripheral bus clock pointer. +#define SL_BUS_CLOCK_SYNTH (&SL_BUS_CLOCK_SYNTH_VALUE) + +/// Define for SYSCFG peripheral bus clock pointer. +#define SL_BUS_CLOCK_SYSCFG (&SL_BUS_CLOCK_SYSCFG_VALUE) + +/// Define for SYSRTC0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_SYSRTC0 (&SL_BUS_CLOCK_SYSRTC0_VALUE) + +/// Define for TIMER0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER0 (&SL_BUS_CLOCK_TIMER0_VALUE) + +/// Define for TIMER1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER1 (&SL_BUS_CLOCK_TIMER1_VALUE) + +/// Define for TIMER2 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER2 (&SL_BUS_CLOCK_TIMER2_VALUE) + +/// Define for TIMER3 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER3 (&SL_BUS_CLOCK_TIMER3_VALUE) + +/// Define for TIMER4 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER4 (&SL_BUS_CLOCK_TIMER4_VALUE) + +/// Define for TIMER5 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER5 (&SL_BUS_CLOCK_TIMER5_VALUE) + +/// Define for TIMER6 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER6 (&SL_BUS_CLOCK_TIMER6_VALUE) + +/// Define for TIMER7 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER7 (&SL_BUS_CLOCK_TIMER7_VALUE) + +/// Define for TIMER8 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER8 (&SL_BUS_CLOCK_TIMER8_VALUE) + +/// Define for TIMER9 peripheral bus clock pointer. +#define SL_BUS_CLOCK_TIMER9 (&SL_BUS_CLOCK_TIMER9_VALUE) + +/// Define for ULFRCO peripheral bus clock pointer. +#define SL_BUS_CLOCK_ULFRCO (&SL_BUS_CLOCK_ULFRCO_VALUE) + +/// Define for USART0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_USART0 (&SL_BUS_CLOCK_USART0_VALUE) + +/// Define for USART1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_USART1 (&SL_BUS_CLOCK_USART1_VALUE) + +/// Define for USART2 peripheral bus clock pointer. +#define SL_BUS_CLOCK_USART2 (&SL_BUS_CLOCK_USART2_VALUE) + +/// Define for USB peripheral bus clock pointer. +#define SL_BUS_CLOCK_USB (&SL_BUS_CLOCK_USB_VALUE) + +/// Define for VDAC0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_VDAC0 (&SL_BUS_CLOCK_VDAC0_VALUE) + +/// Define for VDAC1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_VDAC1 (&SL_BUS_CLOCK_VDAC1_VALUE) + +/// Define for WDOG0 peripheral bus clock pointer. +#define SL_BUS_CLOCK_WDOG0 (&SL_BUS_CLOCK_WDOG0_VALUE) + +/// Define for WDOG1 peripheral bus clock pointer. +#define SL_BUS_CLOCK_WDOG1 (&SL_BUS_CLOCK_WDOG1_VALUE) + +/// @} (end bus_clock_defines) + +// ---------------------------------------------------------------------------- +// TYPEDEFS + +/// The bus clock typedef. +typedef const uint32_t* sl_bus_clock_t; + +// ---------------------------------------------------------------------------- +// EXTERNS + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +// External declaration for invalid peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_INVALID_VALUE; + +// External declaration for ACMP0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ACMP0_VALUE; + +// External declaration for ACMP1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ACMP1_VALUE; + +// External declaration for ADC0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ADC0_VALUE; + +// External declaration for AGC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_AGC_VALUE; + +// External declaration for AMUXCP0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE; + +// External declaration for BUFC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_BUFC_VALUE; + +// External declaration for BURAM peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_BURAM_VALUE; + +// External declaration for BURTC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_BURTC_VALUE; + +// External declaration for CRYPTOACC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_CRYPTOACC_VALUE; + +// External declaration for DCDC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_DCDC_VALUE; + +// External declaration for DEVINFO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_DEVINFO_VALUE; + +// External declaration for DMEM peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_DMEM_VALUE; + +// External declaration for DPLL0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_DPLL0_VALUE; + +// External declaration for ECAIFADC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE; + +// External declaration for ETAMPDET peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ETAMPDET_VALUE; + +// External declaration for EUART0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUART0_VALUE; + +// External declaration for EUSART0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUSART0_VALUE; + +// External declaration for EUSART1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUSART1_VALUE; + +// External declaration for EUSART2 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUSART2_VALUE; + +// External declaration for EUSART3 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUSART3_VALUE; + +// External declaration for EUSART4 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_EUSART4_VALUE; + +// External declaration for FRC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_FRC_VALUE; + +// External declaration for FSRCO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_FSRCO_VALUE; + +// External declaration for GPCRC0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE; + +// External declaration for GPIO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_GPIO_VALUE; + +// External declaration for HFRCO0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE; + +// External declaration for HFRCOEM23 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE; + +// External declaration for HFXO0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_HFXO0_VALUE; + +// External declaration for HOSTMAILBOX peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE; + +// External declaration for HOSTPORTAL peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_HOSTPORTAL_VALUE; + +// External declaration for I2C0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_I2C0_VALUE; + +// External declaration for I2C1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_I2C1_VALUE; + +// External declaration for I2C2 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_I2C2_VALUE; + +// External declaration for I2C3 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_I2C3_VALUE; + +// External declaration for IADC0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_IADC0_VALUE; + +// External declaration for ICACHE0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE; + +// External declaration for IFADCDEBUG peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_IFADCDEBUG_VALUE; + +// External declaration for KEYSCAN peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE; + +// External declaration for KSU peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_KSU_VALUE; + +// External declaration for L2ICACHE0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_L2ICACHE0_VALUE; + +// External declaration for LCD peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LCD_VALUE; + +// External declaration for LDMA0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LDMA0_VALUE; + +// External declaration for LDMAXBAR0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE; + +// External declaration for LEDDRV0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LEDDRV0_VALUE; + +// External declaration for LESENSE peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LESENSE_VALUE; + +// External declaration for LETIMER0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE; + +// External declaration for LFRCO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LFRCO_VALUE; + +// External declaration for LFXO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LFXO_VALUE; + +// External declaration for LPWAES peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LPWAES_VALUE; + +// External declaration for LPW0PORTAL peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE; + +// External declaration for MODEM peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_MODEM_VALUE; + +// External declaration for MSC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_MSC_VALUE; + +// External declaration for MVP peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_MVP_VALUE; + +// External declaration for PCNT0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PCNT0_VALUE; + +// External declaration for PDM peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PDM_VALUE; + +// External declaration for PIXELRZ0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PIXELRZ0_VALUE; + +// External declaration for PIXELRZ1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PIXELRZ1_VALUE; + +// External declaration for PRORTC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PRORTC_VALUE; + +// External declaration for PROTIMER peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE; + +// External declaration for PRS peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_PRS_VALUE; + +// External declaration for RAC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RAC_VALUE; + +// External declaration for RADIOAES peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE; + +// External declaration for RDMAILBOX0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RDMAILBOX0_VALUE; + +// External declaration for RDMAILBOX1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RDMAILBOX1_VALUE; + +// External declaration for RDSCRATCHPAD peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RDSCRATCHPAD_VALUE; + +// External declaration for RFCRC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFCRC_VALUE; + +// External declaration for RFECA0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFECA0_VALUE; + +// External declaration for RFECA1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFECA1_VALUE; + +// External declaration for RFFPLL0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFFPLL0_VALUE; + +// External declaration for RFMAILBOX peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE; + +// External declaration for RFSCRATCHPAD peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE; + +// External declaration for RFSENSE peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RFSENSE_VALUE; + +// External declaration for RPA peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RPA_VALUE; + +// External declaration for RTCC peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_RTCC_VALUE; + +// External declaration for SCRATCHPAD peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SCRATCHPAD_VALUE; + +// External declaration for SEMAILBOX peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE; + +// External declaration for SEMAPHORE0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SEMAPHORE0_VALUE; + +// External declaration for SEMAPHORE1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SEMAPHORE1_VALUE; + +// External declaration for SEPORTAL peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SEPORTAL_VALUE; + +// External declaration for SMU peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SMU_VALUE; + +// External declaration for SOCPLL0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SOCPLL0_VALUE; + +// External declaration for SYMCRYPTO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SYMCRYPTO_VALUE; + +// External declaration for SYNTH peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SYNTH_VALUE; + +// External declaration for SYSCFG peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE; + +// External declaration for SYSRTC0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE; + +// External declaration for TIMER0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER0_VALUE; + +// External declaration for TIMER1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER1_VALUE; + +// External declaration for TIMER2 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER2_VALUE; + +// External declaration for TIMER3 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER3_VALUE; + +// External declaration for TIMER4 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER4_VALUE; + +// External declaration for TIMER5 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER5_VALUE; + +// External declaration for TIMER6 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER6_VALUE; + +// External declaration for TIMER7 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER7_VALUE; + +// External declaration for TIMER8 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER8_VALUE; + +// External declaration for TIMER9 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_TIMER9_VALUE; + +// External declaration for ULFRCO peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE; + +// External declaration for USART0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_USART0_VALUE; + +// External declaration for USART1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_USART1_VALUE; + +// External declaration for USART2 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_USART2_VALUE; + +// External declaration for USB peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_USB_VALUE; + +// External declaration for VDAC0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_VDAC0_VALUE; + +// External declaration for VDAC1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_VDAC1_VALUE; + +// External declaration for WDOG0 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_WDOG0_VALUE; + +// External declaration for WDOG1 peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_WDOG1_VALUE; + +/// @endcond + +/** @} (end addtogroup device_clock) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_CLOCK_H diff --git a/Libs/platform/service/device_manager/inc/sl_device_gpio.h b/Libs/platform/service/device_manager/inc/sl_device_gpio.h new file mode 100644 index 0000000..e976151 --- /dev/null +++ b/Libs/platform/service/device_manager/inc/sl_device_gpio.h @@ -0,0 +1,670 @@ +/***************************************************************************//** + * @file + * @brief Device Manager GPIO. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SL_DEVICE_GPIO_H +#define SL_DEVICE_GPIO_H + +#include +#include +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup device_gpio Device Manager GPIO + * @details + * ## Overview + * + * The Device Manager GPIO component defines the macros, + * structures, and enums that are used common across GPIO driver and + * peripheral. + * + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// ENUMS + +/// GPIO ports IDs. +SL_ENUM(sl_gpio_port_t) { + SL_GPIO_PORT_A = 0, + SL_GPIO_PORT_B = 1, + SL_GPIO_PORT_C = 2, + SL_GPIO_PORT_D = 3, + SL_GPIO_PORT_E = 4, + SL_GPIO_PORT_F = 5, + SL_GPIO_PORT_G = 6, + SL_GPIO_PORT_H = 7, + SL_GPIO_PORT_I = 8, + SL_GPIO_PORT_J = 9, + SL_GPIO_PORT_K = 10, +}; + +/// GPIO Pin Modes. +SL_ENUM(sl_gpio_mode_t) { + /// Input disabled. Pull-up if DOUT is set. + SL_GPIO_MODE_DISABLED, + + /// Input enabled. Filter if DOUT is set. + SL_GPIO_MODE_INPUT, + + /// Input enabled. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL, + + /// Input enabled with filter. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL_FILTER, + + /// Push-pull output. + SL_GPIO_MODE_PUSH_PULL, + + /// Push-pull using alternate control. + SL_GPIO_MODE_PUSH_PULL_ALTERNATE, + + /// Wired-or output. + SL_GPIO_MODE_WIRED_OR, + + /// Wired-or output with pull-down. + SL_GPIO_MODE_WIRED_OR_PULL_DOWN, + + /// Open-drain output. + SL_GPIO_MODE_WIRED_AND, + + /// Open-drain output with filter. + SL_GPIO_MODE_WIRED_AND_FILTER, + + /// Open-drain output with pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP, + + /// Open-drain output with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER, + + /// Open-drain output using alternate control. + SL_GPIO_MODE_WIRED_AND_ALTERNATE, + + /// Open-drain output using alternate control with filter. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER, + + /// Open-drain output using alternate control with pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP, + + /// Open-drain output using alternate control with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER, +}; + +/// GPIO Interrupt Configuration flags. +SL_ENUM(sl_gpio_interrupt_flag_t) { + /// No edge configured. + SL_GPIO_INTERRUPT_NO_EDGE = 0, + + /// Interrupt on rising edge. + SL_GPIO_INTERRUPT_RISING_EDGE = (1 << 0), + + /// Interrupt on falling edge. + SL_GPIO_INTERRUPT_FALLING_EDGE = (1 << 1), + + /// Interrupt on both rising and falling edge. + SL_GPIO_INTERRUPT_RISING_FALLING_EDGE = (1 << 2) +}; + +/******************************************************************************* + ******************************** DEFINES ********************************** + ******************************************************************************/ + +#define SL_GPIO_INTERRUPT_UNAVAILABLE (-1) + +/// Validation of flag. +#define SL_GPIO_FLAG_IS_VALID(flag) ((flag == SL_GPIO_INTERRUPT_NO_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_EDGE) || (flag == SL_GPIO_INTERRUPT_FALLING_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_FALLING_EDGE)) + +/// Define for available ports and pins +#define PA0 (&pa0) +#define PA1 (&pa1) +#define PA2 (&pa2) +#define PA3 (&pa3) +#define PA4 (&pa4) +#define PA5 (&pa5) +#define PA6 (&pa6) +#define PA7 (&pa7) +#define PA8 (&pa8) +#define PA9 (&pa9) +#define PA10 (&pa10) +#define PA11 (&pa11) +#define PA12 (&pa12) +#define PA13 (&pa13) +#define PA14 (&pa14) +#define PA15 (&pa15) +#define PA16 (&pa16) +#define PA17 (&pa17) +#define PA18 (&pa18) +#define PA19 (&pa19) +#define PA20 (&pa20) +#define PA21 (&pa21) +#define PA22 (&pa22) +#define PA23 (&pa23) +#define PA24 (&pa24) +#define PA25 (&pa25) +#define PA26 (&pa26) +#define PA27 (&pa27) +#define PA28 (&pa28) +#define PA29 (&pa29) +#define PA30 (&pa30) +#define PA31 (&pa31) + +#define PB0 (&pb0) +#define PB1 (&pb1) +#define PB2 (&pb2) +#define PB3 (&pb3) +#define PB4 (&pb4) +#define PB5 (&pb5) +#define PB6 (&pb6) +#define PB7 (&pb7) +#define PB8 (&pb8) +#define PB9 (&pb9) +#define PB10 (&pb10) +#define PB11 (&pb11) +#define PB12 (&pb12) +#define PB13 (&pb13) +#define PB14 (&pb14) +#define PB15 (&pb15) +#define PB16 (&pb16) +#define PB17 (&pb17) +#define PB18 (&pb18) +#define PB19 (&pb19) +#define PB20 (&pb20) +#define PB21 (&pb21) +#define PB22 (&pb22) +#define PB23 (&pb23) +#define PB24 (&pb24) +#define PB25 (&pb25) +#define PB26 (&pb26) +#define PB27 (&pb27) +#define PB28 (&pb28) +#define PB29 (&pb29) +#define PB30 (&pb30) +#define PB31 (&pb31) + +#define PC0 (&pc0) +#define PC1 (&pc1) +#define PC2 (&pc2) +#define PC3 (&pc3) +#define PC4 (&pc4) +#define PC5 (&pc5) +#define PC6 (&pc6) +#define PC7 (&pc7) +#define PC8 (&pc8) +#define PC9 (&pc9) +#define PC10 (&pc10) +#define PC11 (&pc11) +#define PC12 (&pc12) +#define PC13 (&pc13) +#define PC14 (&pc14) +#define PC15 (&pc15) +#define PC16 (&pc16) +#define PC17 (&pc17) +#define PC18 (&pc18) +#define PC19 (&pc19) +#define PC20 (&pc20) +#define PC21 (&pc21) +#define PC22 (&pc22) +#define PC23 (&pc23) +#define PC24 (&pc24) +#define PC25 (&pc25) +#define PC26 (&pc26) +#define PC27 (&pc27) +#define PC28 (&pc28) +#define PC29 (&pc29) +#define PC30 (&pc30) +#define PC31 (&pc31) + +#define PD0 (&pd0) +#define PD1 (&pd1) +#define PD2 (&pd2) +#define PD3 (&pd3) +#define PD4 (&pd4) +#define PD5 (&pd5) +#define PD6 (&pd6) +#define PD7 (&pd7) +#define PD8 (&pd8) +#define PD9 (&pd9) +#define PD10 (&pd10) +#define PD11 (&pd11) +#define PD12 (&pd12) +#define PD13 (&pd13) +#define PD14 (&pd14) +#define PD15 (&pd15) +#define PD16 (&pd16) +#define PD17 (&pd17) +#define PD18 (&pd18) +#define PD19 (&pd19) +#define PD20 (&pd20) +#define PD21 (&pd21) +#define PD22 (&pd22) +#define PD23 (&pd23) +#define PD24 (&pd24) +#define PD25 (&pd25) +#define PD26 (&pd26) +#define PD27 (&pd27) +#define PD28 (&pd28) +#define PD29 (&pd29) +#define PD30 (&pd30) +#define PD31 (&pd31) + +#define PE0 (&pe0) +#define PE1 (&pe1) +#define PE2 (&pe2) +#define PE3 (&pe3) +#define PE4 (&pe4) +#define PE5 (&pe5) +#define PE6 (&pe6) +#define PE7 (&pe7) +#define PE8 (&pe8) +#define PE9 (&pe9) +#define PE10 (&pe10) +#define PE11 (&pe11) +#define PE12 (&pe12) +#define PE13 (&pe13) +#define PE14 (&pe14) +#define PE15 (&pe15) +#define PE16 (&pe16) +#define PE17 (&pe17) +#define PE18 (&pe18) +#define PE19 (&pe19) +#define PE20 (&pe20) +#define PE21 (&pe21) +#define PE22 (&pe22) +#define PE23 (&pe23) +#define PE24 (&pe24) +#define PE25 (&pe25) +#define PE26 (&pe26) +#define PE27 (&pe27) +#define PE28 (&pe28) +#define PE29 (&pe29) +#define PE30 (&pe30) +#define PE31 (&pe31) + +#define PF0 (&pf0) +#define PF1 (&pf1) +#define PF2 (&pf2) +#define PF3 (&pf3) +#define PF4 (&pf4) +#define PF5 (&pf5) +#define PF6 (&pf6) +#define PF7 (&pf7) +#define PF8 (&pf8) +#define PF9 (&pf9) +#define PF10 (&pf10) +#define PF11 (&pf11) +#define PF12 (&pf12) +#define PF13 (&pf13) +#define PF14 (&pf14) +#define PF15 (&pf15) +#define PF16 (&pf16) +#define PF17 (&pf17) +#define PF18 (&pf18) +#define PF19 (&pf19) +#define PF20 (&pf20) +#define PF21 (&pf21) +#define PF22 (&pf22) +#define PF23 (&pf23) +#define PF24 (&pf24) +#define PF25 (&pf25) +#define PF26 (&pf26) +#define PF27 (&pf27) +#define PF28 (&pf28) +#define PF29 (&pf29) +#define PF30 (&pf30) +#define PF31 (&pf31) + +#define PG0 (&pg0) +#define PG1 (&pg1) +#define PG2 (&pg2) +#define PG3 (&pg3) +#define PG4 (&pg4) +#define PG5 (&pg5) +#define PG6 (&pg6) +#define PG7 (&pg7) +#define PG8 (&pg8) +#define PG9 (&pg9) +#define PG10 (&pg10) +#define PG11 (&pg11) +#define PG12 (&pg12) +#define PG13 (&pg13) +#define PG14 (&pg14) +#define PG15 (&pg15) +#define PG16 (&pg16) +#define PG17 (&pg17) +#define PG18 (&pg18) +#define PG19 (&pg19) +#define PG20 (&pg20) +#define PG21 (&pg21) +#define PG22 (&pg22) +#define PG23 (&pg23) +#define PG24 (&pg24) +#define PG25 (&pg25) +#define PG26 (&pg26) +#define PG27 (&pg27) +#define PG28 (&pg28) +#define PG29 (&pg29) +#define PG30 (&pg30) +#define PG31 (&pg31) + +#define PH0 (&ph0) +#define PH1 (&ph1) +#define PH2 (&ph2) +#define PH3 (&ph3) +#define PH4 (&ph4) +#define PH5 (&ph5) +#define PH6 (&ph6) +#define PH7 (&ph7) +#define PH8 (&ph8) +#define PH9 (&ph9) +#define PH10 (&ph10) +#define PH11 (&ph11) +#define PH12 (&ph12) +#define PH13 (&ph13) +#define PH14 (&ph14) +#define PH15 (&ph15) +#define PH16 (&ph16) +#define PH17 (&ph17) +#define PH18 (&ph18) +#define PH19 (&ph19) +#define PH20 (&ph20) +#define PH21 (&ph21) +#define PH22 (&ph22) +#define PH23 (&ph23) +#define PH24 (&ph24) +#define PH25 (&ph25) +#define PH26 (&ph26) +#define PH27 (&ph27) +#define PH28 (&ph28) +#define PH29 (&ph29) +#define PH30 (&ph30) +#define PH31 (&ph31) + +#define PI0 (&pi0) +#define PI1 (&pi1) +#define PI2 (&pi2) +#define PI3 (&pi3) +#define PI4 (&pi4) +#define PI5 (&pi5) +#define PI6 (&pi6) +#define PI7 (&pi7) +#define PI8 (&pi8) +#define PI9 (&pi9) +#define PI10 (&pi10) +#define PI11 (&pi11) +#define PI12 (&pi12) +#define PI13 (&pi13) +#define PI14 (&pi14) +#define PI15 (&pi15) +#define PI16 (&pi16) +#define PI17 (&pi17) +#define PI18 (&pi18) +#define PI19 (&pi19) +#define PI20 (&pi20) +#define PI21 (&pi21) +#define PI22 (&pi22) +#define PI23 (&pi23) +#define PI24 (&pi24) +#define PI25 (&pi25) +#define PI26 (&pi26) +#define PI27 (&pi27) +#define PI28 (&pi28) +#define PI29 (&pi29) +#define PI30 (&pi30) +#define PI31 (&pi31) + +#define PJ0 (&pj0) +#define PJ1 (&pj1) +#define PJ2 (&pj2) +#define PJ3 (&pj3) +#define PJ4 (&pj4) +#define PJ5 (&pj5) +#define PJ6 (&pj6) +#define PJ7 (&pj7) +#define PJ8 (&pj8) +#define PJ9 (&pj9) +#define PJ10 (&pj10) +#define PJ11 (&pj11) +#define PJ12 (&pj12) +#define PJ13 (&pj13) +#define PJ14 (&pj14) +#define PJ15 (&pj15) +#define PJ16 (&pj16) +#define PJ17 (&pj17) +#define PJ18 (&pj18) +#define PJ19 (&pj19) +#define PJ20 (&pj20) +#define PJ21 (&pj21) +#define PJ22 (&pj22) +#define PJ23 (&pj23) +#define PJ24 (&pj24) +#define PJ25 (&pj25) +#define PJ26 (&pj26) +#define PJ27 (&pj27) +#define PJ28 (&pj28) +#define PJ29 (&pj29) +#define PJ30 (&pj30) +#define PJ31 (&pj31) + +#define PK0 (&pk0) +#define PK1 (&pk1) +#define PK2 (&pk2) +#define PK3 (&pk3) +#define PK4 (&pk4) +#define PK5 (&pk5) +#define PK6 (&pk6) +#define PK7 (&pk7) +#define PK8 (&pk8) +#define PK9 (&pk9) +#define PK10 (&pk10) +#define PK11 (&pk11) +#define PK12 (&pk12) +#define PK13 (&pk13) +#define PK14 (&pk14) +#define PK15 (&pk15) +#define PK16 (&pk16) +#define PK17 (&pk17) +#define PK18 (&pk18) +#define PK19 (&pk19) +#define PK20 (&pk20) +#define PK21 (&pk21) +#define PK22 (&pk22) +#define PK23 (&pk23) +#define PK24 (&pk24) +#define PK25 (&pk25) +#define PK26 (&pk26) +#define PK27 (&pk27) +#define PK28 (&pk28) +#define PK29 (&pk29) +#define PK30 (&pk30) +#define PK31 (&pk31) + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/// Structure for GPIO Port and Pin. +typedef struct { + uint8_t port; + uint8_t pin; +} sl_gpio_t; + +// ---------------------------------------------------------------------------- +// EXTERNS + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +extern const sl_gpio_t pa0; +extern const sl_gpio_t pa1; +extern const sl_gpio_t pa2; +extern const sl_gpio_t pa3; +extern const sl_gpio_t pa4; +extern const sl_gpio_t pa5; +extern const sl_gpio_t pa6; +extern const sl_gpio_t pa7; +extern const sl_gpio_t pa8; +extern const sl_gpio_t pa9; +extern const sl_gpio_t pa10; +extern const sl_gpio_t pa11; +extern const sl_gpio_t pa12; +extern const sl_gpio_t pa13; +extern const sl_gpio_t pa14; +extern const sl_gpio_t pa15; +extern const sl_gpio_t pa16; +extern const sl_gpio_t pa17; +extern const sl_gpio_t pa18; +extern const sl_gpio_t pa19; +extern const sl_gpio_t pa20; +extern const sl_gpio_t pa21; +extern const sl_gpio_t pa22; +extern const sl_gpio_t pa23; +extern const sl_gpio_t pa24; +extern const sl_gpio_t pa25; +extern const sl_gpio_t pa26; +extern const sl_gpio_t pa27; +extern const sl_gpio_t pa28; +extern const sl_gpio_t pa29; +extern const sl_gpio_t pa30; +extern const sl_gpio_t pa31; +extern const sl_gpio_t pa32; + +extern const sl_gpio_t pb0; +extern const sl_gpio_t pb1; +extern const sl_gpio_t pb2; +extern const sl_gpio_t pb3; +extern const sl_gpio_t pb4; +extern const sl_gpio_t pb5; +extern const sl_gpio_t pb6; +extern const sl_gpio_t pb7; +extern const sl_gpio_t pb8; +extern const sl_gpio_t pb9; +extern const sl_gpio_t pb10; +extern const sl_gpio_t pb11; +extern const sl_gpio_t pb12; +extern const sl_gpio_t pb13; +extern const sl_gpio_t pb14; +extern const sl_gpio_t pb15; +extern const sl_gpio_t pb16; +extern const sl_gpio_t pb17; +extern const sl_gpio_t pb18; +extern const sl_gpio_t pb19; +extern const sl_gpio_t pb20; +extern const sl_gpio_t pb21; +extern const sl_gpio_t pb22; +extern const sl_gpio_t pb23; +extern const sl_gpio_t pb24; +extern const sl_gpio_t pb25; +extern const sl_gpio_t pb26; +extern const sl_gpio_t pb27; +extern const sl_gpio_t pb28; +extern const sl_gpio_t pb29; +extern const sl_gpio_t pb30; +extern const sl_gpio_t pb31; +extern const sl_gpio_t pb32; + +extern const sl_gpio_t pc0; +extern const sl_gpio_t pc1; +extern const sl_gpio_t pc2; +extern const sl_gpio_t pc3; +extern const sl_gpio_t pc4; +extern const sl_gpio_t pc5; +extern const sl_gpio_t pc6; +extern const sl_gpio_t pc7; +extern const sl_gpio_t pc8; +extern const sl_gpio_t pc9; +extern const sl_gpio_t pc10; +extern const sl_gpio_t pc11; +extern const sl_gpio_t pc12; +extern const sl_gpio_t pc13; +extern const sl_gpio_t pc14; +extern const sl_gpio_t pc15; +extern const sl_gpio_t pc16; +extern const sl_gpio_t pc17; +extern const sl_gpio_t pc18; +extern const sl_gpio_t pc19; +extern const sl_gpio_t pc20; +extern const sl_gpio_t pc21; +extern const sl_gpio_t pc22; +extern const sl_gpio_t pc23; +extern const sl_gpio_t pc24; +extern const sl_gpio_t pc25; +extern const sl_gpio_t pc26; +extern const sl_gpio_t pc27; +extern const sl_gpio_t pc28; +extern const sl_gpio_t pc29; +extern const sl_gpio_t pc30; +extern const sl_gpio_t pc31; +extern const sl_gpio_t pc32; + +extern const sl_gpio_t pd0; +extern const sl_gpio_t pd1; +extern const sl_gpio_t pd2; +extern const sl_gpio_t pd3; +extern const sl_gpio_t pd4; +extern const sl_gpio_t pd5; +extern const sl_gpio_t pd6; +extern const sl_gpio_t pd7; +extern const sl_gpio_t pd8; +extern const sl_gpio_t pd9; +extern const sl_gpio_t pd10; +extern const sl_gpio_t pd11; +extern const sl_gpio_t pd12; +extern const sl_gpio_t pd13; +extern const sl_gpio_t pd14; +extern const sl_gpio_t pd15; +extern const sl_gpio_t pd16; +extern const sl_gpio_t pd17; +extern const sl_gpio_t pd18; +extern const sl_gpio_t pd19; +extern const sl_gpio_t pd20; +extern const sl_gpio_t pd21; +extern const sl_gpio_t pd22; +extern const sl_gpio_t pd23; +extern const sl_gpio_t pd24; +extern const sl_gpio_t pd25; +extern const sl_gpio_t pd26; +extern const sl_gpio_t pd27; +extern const sl_gpio_t pd28; +extern const sl_gpio_t pd29; +extern const sl_gpio_t pd30; +extern const sl_gpio_t pd31; +extern const sl_gpio_t pd32; + +/// @endcond + +/** @} (end addtogroup device_gpio) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_GPIO_H diff --git a/Libs/platform/service/device_manager/inc/sl_device_peripheral.h b/Libs/platform/service/device_manager/inc/sl_device_peripheral.h new file mode 100644 index 0000000..594d919 --- /dev/null +++ b/Libs/platform/service/device_manager/inc/sl_device_peripheral.h @@ -0,0 +1,2821 @@ +/**************************************************************************//** + * @file + * @brief Device Manager API Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef SL_DEVICE_PERIPHERAL_H +#define SL_DEVICE_PERIPHERAL_H + +#include "sl_device_peripheral_types.h" +#include "sl_code_classification.h" +#include "em_device.h" +#if 1 +#if defined(DEVICE_PERIPHERAL_INTERNAL_PRESENT) +#include "sli_device_peripheral_internal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup device_peripheral Device Abstraction Peripheral + * @details + * ## Overview + * + * The Device Abstraction Peripheral module defines the different peripherals + * that exist across all Silicon Labs devices and their utility functions. + * + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// DEFINES + +/***************************************************************************//** + * @name Peripheral Defines + * Those defines can be used as constant of type sl_peripheral_t. + * The values of those defines are device specific. + * @{ + ******************************************************************************/ + +/// Define pointer to ACMP0 peripheral structure. +#define SL_PERIPHERAL_ACMP0 (&sl_peripheral_val_acmp0) + +/// Define pointer to ACMP1 peripheral structure. +#define SL_PERIPHERAL_ACMP1 (&sl_peripheral_val_acmp1) + +/// Define pointer to ADC0 peripheral structure. +#define SL_PERIPHERAL_ADC0 (&sl_peripheral_val_adc0) + +/// Define pointer to AES peripheral structure. +#define SL_PERIPHERAL_AES (&sl_peripheral_val_aes) + +/// Define pointer to AMUXCP0 peripheral structure. +#define SL_PERIPHERAL_AMUXCP0 (&sl_peripheral_val_amuxcp0) + +/// Define pointer to BUFC peripheral structure. +#define SL_PERIPHERAL_BUFC (&sl_peripheral_val_bufc) + +/// Define pointer to BURAM peripheral structure. +#define SL_PERIPHERAL_BURAM (&sl_peripheral_val_buram) + +/// Define pointer to BURTC peripheral structure. +#define SL_PERIPHERAL_BURTC (&sl_peripheral_val_burtc) + +/// Define pointer to CMU peripheral structure. +#define SL_PERIPHERAL_CMU (&sl_peripheral_val_cmu) + +/// Define pointer to CRYPTOACC peripheral structure. +#define SL_PERIPHERAL_CRYPTOACC (&sl_peripheral_val_cryptoacc) + +/// Define pointer to DCDC peripheral structure. +#define SL_PERIPHERAL_DCDC (&sl_peripheral_val_dcdc) + +/// Define pointer to DEVINFO peripheral structure. +#define SL_PERIPHERAL_DEVINFO (&sl_peripheral_val_devinfo) + +/// Define pointer to DMEM peripheral structure. +#define SL_PERIPHERAL_DMEM (&sl_peripheral_val_dmem) + +/// Define pointer to DMEM0 peripheral structure. +#define SL_PERIPHERAL_DMEM0 (&sl_peripheral_val_dmem0) + +/// Define pointer to DMEM1 peripheral structure. +#define SL_PERIPHERAL_DMEM1 (&sl_peripheral_val_dmem1) + +/// Define pointer to DPLL0 peripheral structure. +#define SL_PERIPHERAL_DPLL0 (&sl_peripheral_val_dpll0) + +/// Define pointer to EMU peripheral structure. +#define SL_PERIPHERAL_EMU (&sl_peripheral_val_emu) + +/// Define pointer to ETAMPDET peripheral structure. +#define SL_PERIPHERAL_ETAMPDET (&sl_peripheral_val_etampdet) + +/// Define pointer to EUART0 peripheral structure. +#define SL_PERIPHERAL_EUART0 (&sl_peripheral_val_euart0) + +/// Define pointer to EUSART0 peripheral structure. +#define SL_PERIPHERAL_EUSART0 (&sl_peripheral_val_eusart0) + +/// Define pointer to EUSART1 peripheral structure. +#define SL_PERIPHERAL_EUSART1 (&sl_peripheral_val_eusart1) + +/// Define pointer to EUSART2 peripheral structure. +#define SL_PERIPHERAL_EUSART2 (&sl_peripheral_val_eusart2) + +/// Define pointer to EUSART3 peripheral structure. +#define SL_PERIPHERAL_EUSART3 (&sl_peripheral_val_eusart3) + +/// Define pointer to EUSART4 peripheral structure. +#define SL_PERIPHERAL_EUSART4 (&sl_peripheral_val_eusart4) + +/// Define pointer to FSRCO peripheral structure. +#define SL_PERIPHERAL_FSRCO (&sl_peripheral_val_fsrco) + +/// Define pointer to GPCRC0 peripheral structure. +#define SL_PERIPHERAL_GPCRC0 (&sl_peripheral_val_gpcrc0) + +/// Define pointer to GPIO peripheral structure. +#define SL_PERIPHERAL_GPIO (&sl_peripheral_val_gpio) + +/// Define pointer to HFRCO0 peripheral structure. +#define SL_PERIPHERAL_HFRCO0 (&sl_peripheral_val_hfrco0) + +/// Define pointer to HFRCOEM23 peripheral structure. +#define SL_PERIPHERAL_HFRCOEM23 (&sl_peripheral_val_hfrcoem23) + +/// Define pointer to HFXO0 peripheral structure. +#define SL_PERIPHERAL_HFXO0 (&sl_peripheral_val_hfxo0) + +/// Define pointer to HOSTMAILBOX peripheral structure. +#define SL_PERIPHERAL_HOSTMAILBOX (&sl_peripheral_val_hostmailbox) + +/// Define pointer to HOSTPORTAL peripheral structure. +#define SL_PERIPHERAL_HOSTPORTAL (&sl_peripheral_val_hostportal) + +/// Define pointer to I2C0 peripheral structure. +#define SL_PERIPHERAL_I2C0 (&sl_peripheral_val_i2c0) + +/// Define pointer to I2C1 peripheral structure. +#define SL_PERIPHERAL_I2C1 (&sl_peripheral_val_i2c1) + +/// Define pointer to I2C2 peripheral structure. +#define SL_PERIPHERAL_I2C2 (&sl_peripheral_val_i2c2) + +/// Define pointer to I2C3 peripheral structure. +#define SL_PERIPHERAL_I2C3 (&sl_peripheral_val_i2c3) + +/// Define pointer to IADC0 peripheral structure. +#define SL_PERIPHERAL_IADC0 (&sl_peripheral_val_iadc0) + +/// Define pointer to ICACHE0 peripheral structure. +#define SL_PERIPHERAL_ICACHE0 (&sl_peripheral_val_icache0) + +/// Define pointer to KEYSCAN peripheral structure. +#define SL_PERIPHERAL_KEYSCAN (&sl_peripheral_val_keyscan) + +/// Define pointer to L1ICACHE0 peripheral structure. +#define SL_PERIPHERAL_L1ICACHE0 (&sl_peripheral_val_l1icache0) + +/// Define pointer to L2ICACHE0 peripheral structure. +#define SL_PERIPHERAL_L2ICACHE0 (&sl_peripheral_val_l2icache0) + +/// Define pointer to LCD peripheral structure. +#define SL_PERIPHERAL_LCD (&sl_peripheral_val_lcd) + +/// Define pointer to LCDRF peripheral structure. +#define SL_PERIPHERAL_LCDRF (&sl_peripheral_val_lcdrf) + +/// Define pointer to LDMA0 peripheral structure. +#define SL_PERIPHERAL_LDMA0 (&sl_peripheral_val_ldma0) + +/// Define pointer to LDMAXBAR0 peripheral structure. +#define SL_PERIPHERAL_LDMAXBAR0 (&sl_peripheral_val_ldmaxbar0) + +/// Define pointer to LEDDRV0 peripheral structure. +#define SL_PERIPHERAL_LEDDRV0 (&sl_peripheral_val_leddrv0) + +/// Define pointer to LESENSE peripheral structure. +#define SL_PERIPHERAL_LESENSE (&sl_peripheral_val_lesense) + +/// Define pointer to LETIMER0 peripheral structure. +#define SL_PERIPHERAL_LETIMER0 (&sl_peripheral_val_letimer0) + +/// Define pointer to LFRCO peripheral structure. +#define SL_PERIPHERAL_LFRCO (&sl_peripheral_val_lfrco) + +/// Define pointer to LFXO peripheral structure. +#define SL_PERIPHERAL_LFXO (&sl_peripheral_val_lfxo) + +/// Define pointer to LPWAES peripheral structure. +#define SL_PERIPHERAL_LPWAES (&sl_peripheral_val_lpwaes) + +/// Define pointer to LPW0PORTAL peripheral structure. +#define SL_PERIPHERAL_LPW0PORTAL (&sl_peripheral_val_lpw0portal) + +/// Define pointer to LVGD peripheral structure. +#define SL_PERIPHERAL_LVGD (&sl_peripheral_val_lvgd) + +/// Define pointer to MPAHBRAM peripheral structure. +#define SL_PERIPHERAL_MPAHBRAM (&sl_peripheral_val_mpahbram) + +/// Define pointer to MSC peripheral structure. +#define SL_PERIPHERAL_MSC (&sl_peripheral_val_msc) + +/// Define pointer to MVP peripheral structure. +#define SL_PERIPHERAL_MVP (&sl_peripheral_val_mvp) + +/// Define pointer to PCNT0 peripheral structure. +#define SL_PERIPHERAL_PCNT0 (&sl_peripheral_val_pcnt0) + +/// Define pointer to PDM peripheral structure. +#define SL_PERIPHERAL_PDM (&sl_peripheral_val_pdm) + +/// Define pointer to PFMXPPRF peripheral structure. +#define SL_PERIPHERAL_PFMXPPRF (&sl_peripheral_val_pfmxpprf) + +/// Define pointer to PIXELRZ0 peripheral structure. +#define SL_PERIPHERAL_PIXELRZ0 (&sl_peripheral_val_pixelrz0) + +/// Define pointer to PIXELRZ1 peripheral structure. +#define SL_PERIPHERAL_PIXELRZ1 (&sl_peripheral_val_pixelrz1) + +/// Define pointer to PRORTC peripheral structure. +#define SL_PERIPHERAL_PRORTC (&sl_peripheral_val_prortc) + +/// Define pointer to PRS peripheral structure. +#define SL_PERIPHERAL_PRS (&sl_peripheral_val_prs) + +/// Define pointer to RADIOAES peripheral structure. +#define SL_PERIPHERAL_RADIOAES (&sl_peripheral_val_radioaes) + +/// Define pointer to RFFPLL0 peripheral structure. +#define SL_PERIPHERAL_RFFPLL0 (&sl_peripheral_val_rffpll0) + +/// Define pointer to RPA peripheral structure. +#define SL_PERIPHERAL_RPA (&sl_peripheral_val_rpa) + +/// Define pointer to RTCC peripheral structure. +#define SL_PERIPHERAL_RTCC (&sl_peripheral_val_rtcc) + +/// Define pointer to SCRATCHPAD peripheral structure. +#define SL_PERIPHERAL_SCRATCHPAD (&sl_peripheral_val_scratchpad) + +/// Define pointer to SEMAILBOX peripheral structure. +#define SL_PERIPHERAL_SEMAILBOX (&sl_peripheral_val_semailbox) + +/// Define pointer to SEMAPHORE0 peripheral structure. +#define SL_PERIPHERAL_SEMAPHORE0 (&sl_peripheral_val_semaphore0) + +/// Define pointer to SEMAPHORE1 peripheral structure. +#define SL_PERIPHERAL_SEMAPHORE1 (&sl_peripheral_val_semaphore1) + +/// Define pointer to SEPORTAL peripheral structure. +#define SL_PERIPHERAL_SEPORTAL (&sl_peripheral_val_seportal) + +/// Define pointer to SEPUF peripheral structure. +#define SL_PERIPHERAL_SEPUF (&sl_peripheral_val_sepuf) + +/// Define pointer to SMU peripheral structure. +#define SL_PERIPHERAL_SMU (&sl_peripheral_val_smu) + +/// Define pointer to SOCPLL0 peripheral structure. +#define SL_PERIPHERAL_SOCPLL0 (&sl_peripheral_val_socpll0) + +/// Define pointer to SYMCRYPTO peripheral structure. +#define SL_PERIPHERAL_SYMCRYPTO (&sl_peripheral_val_symcrypto) + +/// Define pointer to SYSCFG peripheral structure. +#define SL_PERIPHERAL_SYSCFG (&sl_peripheral_val_syscfg) + +/// Define pointer to SYSRTC0 peripheral structure. +#define SL_PERIPHERAL_SYSRTC0 (&sl_peripheral_val_sysrtc0) + +/// Define pointer to TIMER0 peripheral structure. +#define SL_PERIPHERAL_TIMER0 (&sl_peripheral_val_timer0) + +/// Define pointer to TIMER1 peripheral structure. +#define SL_PERIPHERAL_TIMER1 (&sl_peripheral_val_timer1) + +/// Define pointer to TIMER2 peripheral structure. +#define SL_PERIPHERAL_TIMER2 (&sl_peripheral_val_timer2) + +/// Define pointer to TIMER3 peripheral structure. +#define SL_PERIPHERAL_TIMER3 (&sl_peripheral_val_timer3) + +/// Define pointer to TIMER4 peripheral structure. +#define SL_PERIPHERAL_TIMER4 (&sl_peripheral_val_timer4) + +/// Define pointer to TIMER5 peripheral structure. +#define SL_PERIPHERAL_TIMER5 (&sl_peripheral_val_timer5) + +/// Define pointer to TIMER6 peripheral structure. +#define SL_PERIPHERAL_TIMER6 (&sl_peripheral_val_timer6) + +/// Define pointer to TIMER7 peripheral structure. +#define SL_PERIPHERAL_TIMER7 (&sl_peripheral_val_timer7) + +/// Define pointer to TIMER8 peripheral structure. +#define SL_PERIPHERAL_TIMER8 (&sl_peripheral_val_timer8) + +/// Define pointer to TIMER9 peripheral structure. +#define SL_PERIPHERAL_TIMER9 (&sl_peripheral_val_timer9) + +/// Define pointer to ULFRCO peripheral structure. +#define SL_PERIPHERAL_ULFRCO (&sl_peripheral_val_ulfrco) + +/// Define pointer to USART0 peripheral structure. +#define SL_PERIPHERAL_USART0 (&sl_peripheral_val_usart0) + +/// Define pointer to USART1 peripheral structure. +#define SL_PERIPHERAL_USART1 (&sl_peripheral_val_usart1) + +/// Define pointer to USART2 peripheral structure. +#define SL_PERIPHERAL_USART2 (&sl_peripheral_val_usart2) + +/// Define pointer to USB peripheral structure. +#define SL_PERIPHERAL_USB (&sl_peripheral_val_usb) + +/// Define pointer to USBAHB peripheral structure. +#define SL_PERIPHERAL_USBAHB (&sl_peripheral_val_usbahb) + +/// Define pointer to USBPLL0 peripheral structure. +#define SL_PERIPHERAL_USBPLL0 (&sl_peripheral_val_usbpll0) + +/// Define pointer to VDAC0 peripheral structure. +#define SL_PERIPHERAL_VDAC0 (&sl_peripheral_val_vdac0) + +/// Define pointer to VDAC1 peripheral structure. +#define SL_PERIPHERAL_VDAC1 (&sl_peripheral_val_vdac1) + +/// Define pointer to WDOG0 peripheral structure. +#define SL_PERIPHERAL_WDOG0 (&sl_peripheral_val_wdog0) + +/// Define pointer to WDOG1 peripheral structure. +#define SL_PERIPHERAL_WDOG1 (&sl_peripheral_val_wdog1) + +/// @} (end peripheral_defines) + +// ---------------------------------------------------------------------------- +// TYPEDEFS + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(__ICCARM__) +// Disable IAR multiple typedefs declaration warning. +#pragma diag_suppress=Pe301 +#endif + +// Declare peripheral structure for ACMP. +//typedef struct acmp_typedef ACMP_TypeDef; + +// Declare peripheral structure for ADC. +typedef struct adc_typedef ADC_TypeDef; + +// Declare peripheral structure for AES. +//typedef struct aes_typedef AES_TypeDef; + +// Declare peripheral structure for AMUXCP. +//typedef struct amuxcp_typedef AMUXCP_TypeDef; + +// Declare peripheral structure for BUFC. +typedef struct bufc_typedef BUFC_TypeDef; + +// Declare peripheral structure for BURAM. +//typedef struct buram_typedef BURAM_TypeDef; + +// Declare peripheral structure for BURTC. +//typedef struct burtc_typedef BURTC_TypeDef; + +// Declare peripheral structure for CMU. +//typedef struct cmu_typedef CMU_TypeDef; + +// Declare peripheral structure for CRYPTOACC. +typedef struct cryptoacc_typedef CRYPTOACC_TypeDef; + +// Declare peripheral structure for CRYPTOACC_PKCTRL. +typedef struct cryptoacc_pkctrl_typedef CRYPTOACC_PKCTRL_TypeDef; + +// Declare peripheral structure for CRYPTOACC_RNGCTRL. +typedef struct cryptoacc_rngctrl_typedef CRYPTOACC_RNGCTRL_TypeDef; + +// Declare peripheral structure for DCDC. +typedef struct dcdc_typedef DCDC_TypeDef; + +// Declare peripheral structure for DEVINFO. +//typedef struct devinfo_typedef DEVINFO_TypeDef; + +// Declare peripheral structure for DPLL. +//typedef struct dpll_typedef DPLL_TypeDef; + +// Declare peripheral structure for EMU. +//typedef struct emu_typedef EMU_TypeDef; + +// Declare peripheral structure for EMU_CFGNS. +typedef struct emu_cfgns_typedef EMU_CFGNS_TypeDef; + +// Declare peripheral structure for ETAMPDET. +typedef struct etampdet_typedef ETAMPDET_TypeDef; + +// Declare peripheral structure for EUSART. +//typedef struct eusart_typedef EUSART_TypeDef; + +// Declare peripheral structure for FSRCO. +//typedef struct fsrco_typedef FSRCO_TypeDef; + +// Declare peripheral structure for GPCRC. +//typedef struct gpcrc_typedef GPCRC_TypeDef; + +// Declare peripheral structure for GPIO. +//typedef struct gpio_typedef GPIO_TypeDef; + +// Declare peripheral structure for HFRCO. +//typedef struct hfrco_typedef HFRCO_TypeDef; + +// Declare peripheral structure for HFXO. +//typedef struct hfxo_typedef HFXO_TypeDef; + +// Declare peripheral structure for HOSTPORTAL. +typedef struct hostportal_typedef HOSTPORTAL_TypeDef; + +// Declare peripheral structure for HYDRARAM. +typedef struct hydraram_typedef HYDRARAM_TypeDef; + +// Declare peripheral structure for I2C. +//typedef struct i2c_typedef I2C_TypeDef; + +// Declare peripheral structure for IADC. +//typedef struct iadc_typedef IADC_TypeDef; + +// Declare peripheral structure for ICACHE. +//typedef struct icache_typedef ICACHE_TypeDef; + +// Declare peripheral structure for KEYSCAN. +//typedef struct keyscan_typedef KEYSCAN_TypeDef; + +// Declare peripheral structure for L2CACHE. +typedef struct l2cache_typedef L2CACHE_TypeDef; + +// Declare peripheral structure for LCD. +typedef struct lcd_typedef LCD_TypeDef; + +// Declare peripheral structure for LCDRF. +typedef struct lcdrf_typedef LCDRF_TypeDef; + +// Declare peripheral structure for LDMA. +//typedef struct ldma_typedef LDMA_TypeDef; + +// Declare peripheral structure for LDMAXBAR. +//typedef struct ldmaxbar_typedef LDMAXBAR_TypeDef; + +// Declare peripheral structure for LEDDRV. +typedef struct leddrv_typedef LEDDRV_TypeDef; + +// Declare peripheral structure for LESENSE. +typedef struct lesense_typedef LESENSE_TypeDef; + +// Declare peripheral structure for LETIMER. +//typedef struct letimer_typedef LETIMER_TypeDef; + +// Declare peripheral structure for LFRCO. +//typedef struct lfrco_typedef LFRCO_TypeDef; + +// Declare peripheral structure for LFXO. +//typedef struct lfxo_typedef LFXO_TypeDef; + +// Declare peripheral structure for LPWAES. +typedef struct lpwaes_typedef LPWAES_TypeDef; + +// Declare peripheral structure for LPW0PORTAL. +typedef struct lpw0portal_typedef LPW0PORTAL_TypeDef; + +// Declare peripheral structure for LVGD. +typedef struct lvgd_typedef LVGD_TypeDef; + +// Declare peripheral structure for MAILBOX. +//typedef struct mailbox_typedef MAILBOX_TypeDef; + +// Declare peripheral structure for MPAHBRAM. +//typedef struct mpahbram_typedef MPAHBRAM_TypeDef; + +// Declare peripheral structure for MSC. +//typedef struct msc_typedef MSC_TypeDef; + +// Declare peripheral structure for MVP. +//typedef struct mvp_typedef MVP_TypeDef; + +// Declare peripheral structure for PCNT. +//typedef struct pcnt_typedef PCNT_TypeDef; + +// Declare peripheral structure for PDM. +typedef struct pdm_typedef PDM_TypeDef; + +// Declare peripheral structure for PFMXPPRF. +typedef struct pfmxpprf_typedef PFMXPPRF_TypeDef; + +// Declare peripheral structure for PIXELRZ. +typedef struct pixelrz_typedef PIXELRZ_TypeDef; + +// Declare peripheral structure for PRS. +//typedef struct prs_typedef PRS_TypeDef; + +// Declare peripheral structure for RFFPLL. +typedef struct rffpll_typedef RFFPLL_TypeDef; + +// Declare peripheral structure for RPA. +typedef struct rpa_typedef RPA_TypeDef; + +// Declare peripheral structure for RTCC. +typedef struct rtcc_typedef RTCC_TypeDef; + +// Declare peripheral structure for SCRATCHPAD. +//typedef struct scratchpad_typedef SCRATCHPAD_TypeDef; + +// Declare peripheral structure for SEMAILBOX_AHBHOST. +typedef struct semailbox_ahbhost_typedef SEMAILBOX_AHBHOST_TypeDef; + +// Declare peripheral structure for SEMAILBOX_HOST. +//typedef struct semailbox_host_typedef SEMAILBOX_HOST_TypeDef; + +// Declare peripheral structure for SEMAPHORE. +typedef struct semaphore_typedef SEMAPHORE_TypeDef; + +// Declare peripheral structure for SEPORTAL. +typedef struct seportal_typedef SEPORTAL_TypeDef; + +// Declare peripheral structure for SEPUF_APBCFG. +typedef struct sepuf_apbcfg_typedef SEPUF_APBCFG_TypeDef; + +// Declare peripheral structure for SMU. +//typedef struct smu_typedef SMU_TypeDef; + +// Declare peripheral structure for SOCPLL. +typedef struct socpll_typedef SOCPLL_TypeDef; + +// Declare peripheral structure for SYMCRYPTO. +typedef struct symcrypto_typedef SYMCRYPTO_TypeDef; + +// Declare peripheral structure for SYSCFG. +//typedef struct syscfg_typedef SYSCFG_TypeDef; + +// Declare peripheral structure for SYSCFG_CFGNS. +//typedef struct syscfg_cfgns_typedef SYSCFG_CFGNS_TypeDef; + +// Declare peripheral structure for SYSRTC. +//typedef struct sysrtc_typedef SYSRTC_TypeDef; + +// Declare peripheral structure for TIMER. +//typedef struct timer_typedef TIMER_TypeDef; + +// Declare peripheral structure for ULFRCO. +//typedef struct ulfrco_typedef ULFRCO_TypeDef; + +// Declare peripheral structure for USART. +//typedef struct usart_typedef USART_TypeDef; + +// Declare peripheral structure for USBAHB_AHBS. +typedef struct usbahb_ahbs_typedef USBAHB_AHBS_TypeDef; + +// Declare peripheral structure for USBPLL. +typedef struct usbpll_typedef USBPLL_TypeDef; + +// Declare peripheral structure for USB_APBS. +typedef struct usb_apbs_typedef USB_APBS_TypeDef; + +// Declare peripheral structure for VDAC. +//typedef struct vdac_typedef VDAC_TypeDef; + +// Declare peripheral structure for WDOG. +//typedef struct wdog_typedef WDOG_TypeDef; + +#if defined(__ICCARM__) +// Disable IAR multiple typedefs declaration warning. +#pragma diag_default=Pe301 +#endif + +/// @endcond + +// ---------------------------------------------------------------------------- +// EXTERNS + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +// External declaration for ACMP0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_acmp0; + +// External declaration for ACMP1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_acmp1; + +// External declaration for ADC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_adc0; + +// External declaration for AES peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_aes; + +// External declaration for AMUXCP0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_amuxcp0; + +// External declaration for BUFC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_bufc; + +// External declaration for BURAM peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_buram; + +// External declaration for BURTC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_burtc; + +// External declaration for CMU peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_cmu; + +// External declaration for CRYPTOACC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_cryptoacc; + +// External declaration for DCDC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_dcdc; + +// External declaration for DEVINFO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_devinfo; + +// External declaration for DMEM peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_dmem; + +// External declaration for DMEM0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_dmem0; + +// External declaration for DMEM1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_dmem1; + +// External declaration for DPLL0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_dpll0; + +// External declaration for EMU peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_emu; + +// External declaration for ETAMPDET peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_etampdet; + +// External declaration for EUART0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_euart0; + +// External declaration for EUSART0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_eusart0; + +// External declaration for EUSART1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_eusart1; + +// External declaration for EUSART2 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_eusart2; + +// External declaration for EUSART3 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_eusart3; + +// External declaration for EUSART4 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_eusart4; + +// External declaration for FSRCO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_fsrco; + +// External declaration for GPCRC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_gpcrc0; + +// External declaration for GPIO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_gpio; + +// External declaration for HFRCO0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_hfrco0; + +// External declaration for HFRCOEM23 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_hfrcoem23; + +// External declaration for HFXO0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_hfxo0; + +// External declaration for HOSTMAILBOX peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_hostmailbox; + +// External declaration for HOSTPORTAL peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_hostportal; + +// External declaration for I2C0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_i2c0; + +// External declaration for I2C1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_i2c1; + +// External declaration for I2C2 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_i2c2; + +// External declaration for I2C3 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_i2c3; + +// External declaration for IADC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_iadc0; + +// External declaration for ICACHE0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_icache0; + +// External declaration for KEYSCAN peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_keyscan; + +// External declaration for L1ICACHE0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_l1icache0; + +// External declaration for L2ICACHE0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_l2icache0; + +// External declaration for LCD peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lcd; + +// External declaration for LCDRF peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lcdrf; + +// External declaration for LDMA0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_ldma0; + +// External declaration for LDMAXBAR0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0; + +// External declaration for LEDDRV0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_leddrv0; + +// External declaration for LESENSE peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lesense; + +// External declaration for LETIMER0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_letimer0; + +// External declaration for LFRCO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lfrco; + +// External declaration for LFXO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lfxo; + +// External declaration for LPWAES peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lpwaes; + +// External declaration for LPW0PORTAL peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lpw0portal; + +// External declaration for LVGD peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lvgd; + +// External declaration for MPAHBRAM peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_mpahbram; + +// External declaration for MSC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_msc; + +// External declaration for MVP peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_mvp; + +// External declaration for PCNT0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_pcnt0; + +// External declaration for PDM peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_pdm; + +// External declaration for PFMXPPRF peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_pfmxpprf; + +// External declaration for PIXELRZ0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_pixelrz0; + +// External declaration for PIXELRZ1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_pixelrz1; + +// External declaration for PRORTC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_prortc; + +// External declaration for PRS peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_prs; + +// External declaration for RADIOAES peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_radioaes; + +// External declaration for RFFPLL0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_rffpll0; + +// External declaration for RPA peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_rpa; + +// External declaration for RTCC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_rtcc; + +// External declaration for SCRATCHPAD peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_scratchpad; + +// External declaration for SEMAILBOX peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_semailbox; + +// External declaration for SEMAPHORE0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_semaphore0; + +// External declaration for SEMAPHORE1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_semaphore1; + +// External declaration for SEPORTAL peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_seportal; + +// External declaration for SEPUF peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_sepuf; + +// External declaration for SMU peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_smu; + +// External declaration for SOCPLL0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_socpll0; + +// External declaration for SYMCRYPTO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_symcrypto; + +// External declaration for SYSCFG peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_syscfg; + +// External declaration for SYSRTC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_sysrtc0; + +// External declaration for TIMER0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer0; + +// External declaration for TIMER1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer1; + +// External declaration for TIMER2 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer2; + +// External declaration for TIMER3 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer3; + +// External declaration for TIMER4 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer4; + +// External declaration for TIMER5 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer5; + +// External declaration for TIMER6 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer6; + +// External declaration for TIMER7 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer7; + +// External declaration for TIMER8 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer8; + +// External declaration for TIMER9 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_timer9; + +// External declaration for ULFRCO peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_ulfrco; + +// External declaration for USART0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usart0; + +// External declaration for USART1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usart1; + +// External declaration for USART2 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usart2; + +// External declaration for USB peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usb; + +// External declaration for USBAHB peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usbahb; + +// External declaration for USBPLL0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_usbpll0; + +// External declaration for VDAC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_vdac0; + +// External declaration for VDAC1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_vdac1; + +// External declaration for WDOG0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_wdog0; + +// External declaration for WDOG1 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_wdog1; + +/// @endcond + +// ---------------------------------------------------------------------------- +// FUNCTIONS + +/***************************************************************************//** + * The base address getter for ACMP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ACMP_TypeDef *sl_device_peripheral_acmp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ACMP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ADC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ADC_TypeDef *sl_device_peripheral_adc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ADC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for AES. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline AES_TypeDef *sl_device_peripheral_aes_get_base_addr(const sl_peripheral_t peripheral) +{ + return (AES_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for AMUXCP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline AMUXCP_TypeDef *sl_device_peripheral_amuxcp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (AMUXCP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BUFC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BUFC_TypeDef *sl_device_peripheral_bufc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BUFC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BURAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BURAM_TypeDef *sl_device_peripheral_buram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BURAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BURTC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BURTC_TypeDef *sl_device_peripheral_burtc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BURTC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CMU_TypeDef *sl_device_peripheral_cmu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_TypeDef *sl_device_peripheral_cryptoacc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC_PKCTRL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_PKCTRL_TypeDef *sl_device_peripheral_cryptoacc_pkctrl_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_PKCTRL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC_RNGCTRL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_RNGCTRL_TypeDef *sl_device_peripheral_cryptoacc_rngctrl_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_RNGCTRL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DCDC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DCDC_TypeDef *sl_device_peripheral_dcdc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DCDC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DEVINFO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DEVINFO_TypeDef *sl_device_peripheral_devinfo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DEVINFO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DPLL_TypeDef *sl_device_peripheral_dpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EMU_TypeDef *sl_device_peripheral_emu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EMU_CFGNS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EMU_CFGNS_TypeDef *sl_device_peripheral_emu_cfgns_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EMU_CFGNS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ETAMPDET. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ETAMPDET_TypeDef *sl_device_peripheral_etampdet_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ETAMPDET_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EUSART. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EUSART_TypeDef *sl_device_peripheral_eusart_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EUSART_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for FSRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline FSRCO_TypeDef *sl_device_peripheral_fsrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (FSRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for GPCRC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline GPCRC_TypeDef *sl_device_peripheral_gpcrc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (GPCRC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for GPIO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline GPIO_TypeDef *sl_device_peripheral_gpio_get_base_addr(const sl_peripheral_t peripheral) +{ + return (GPIO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HFRCO_TypeDef *sl_device_peripheral_hfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HFXO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HFXO_TypeDef *sl_device_peripheral_hfxo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HFXO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HOSTPORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HOSTPORTAL_TypeDef *sl_device_peripheral_hostportal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HOSTPORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HYDRARAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HYDRARAM_TypeDef *sl_device_peripheral_hydraram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HYDRARAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for I2C. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline I2C_TypeDef *sl_device_peripheral_i2c_get_base_addr(const sl_peripheral_t peripheral) +{ + return (I2C_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for IADC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline IADC_TypeDef *sl_device_peripheral_iadc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (IADC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ICACHE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ICACHE_TypeDef *sl_device_peripheral_icache_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ICACHE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for KEYSCAN. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline KEYSCAN_TypeDef *sl_device_peripheral_keyscan_get_base_addr(const sl_peripheral_t peripheral) +{ + return (KEYSCAN_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for L2CACHE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline L2CACHE_TypeDef *sl_device_peripheral_l2cache_get_base_addr(const sl_peripheral_t peripheral) +{ + return (L2CACHE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LCD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LCD_TypeDef *sl_device_peripheral_lcd_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LCD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LCDRF. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LCDRF_TypeDef *sl_device_peripheral_lcdrf_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LCDRF_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LDMA. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LDMA_TypeDef *sl_device_peripheral_ldma_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LDMA_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LDMAXBAR. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LDMAXBAR_TypeDef *sl_device_peripheral_ldmaxbar_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LDMAXBAR_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LEDDRV. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LEDDRV_TypeDef *sl_device_peripheral_leddrv_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LEDDRV_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LESENSE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LESENSE_TypeDef *sl_device_peripheral_lesense_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LESENSE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LETIMER. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LETIMER_TypeDef *sl_device_peripheral_letimer_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LETIMER_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LFRCO_TypeDef *sl_device_peripheral_lfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LFXO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LFXO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LPWAES. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LPWAES_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LPW0PORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LPW0PORTAL_TypeDef *sl_device_peripheral_lpw0portal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LPW0PORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LVGD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LVGD_TypeDef *sl_device_peripheral_lvgd_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LVGD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MAILBOX. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MAILBOX_TypeDef *sl_device_peripheral_mailbox_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MAILBOX_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MPAHBRAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MPAHBRAM_TypeDef *sl_device_peripheral_mpahbram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MPAHBRAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MSC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MSC_TypeDef *sl_device_peripheral_msc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MSC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MVP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MVP_TypeDef *sl_device_peripheral_mvp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MVP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PCNT. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PCNT_TypeDef *sl_device_peripheral_pcnt_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PCNT_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PDM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PDM_TypeDef *sl_device_peripheral_pdm_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PDM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PFMXPPRF. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PFMXPPRF_TypeDef *sl_device_peripheral_pfmxpprf_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PFMXPPRF_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PIXELRZ. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PIXELRZ_TypeDef *sl_device_peripheral_pixelrz_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PIXELRZ_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PRS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PRS_TypeDef *sl_device_peripheral_prs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PRS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RFFPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RFFPLL_TypeDef *sl_device_peripheral_rffpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RFFPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RPA. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RPA_TypeDef *sl_device_peripheral_rpa_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RPA_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RTCC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RTCC_TypeDef *sl_device_peripheral_rtcc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RTCC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SCRATCHPAD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SCRATCHPAD_TypeDef *sl_device_peripheral_scratchpad_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SCRATCHPAD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAILBOX_AHBHOST. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAILBOX_AHBHOST_TypeDef *sl_device_peripheral_semailbox_ahbhost_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAILBOX_AHBHOST_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAILBOX_HOST. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAILBOX_HOST_TypeDef *sl_device_peripheral_semailbox_host_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAILBOX_HOST_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAPHORE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAPHORE_TypeDef *sl_device_peripheral_semaphore_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAPHORE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEPORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEPORTAL_TypeDef *sl_device_peripheral_seportal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEPORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEPUF_APBCFG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEPUF_APBCFG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SOCPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SOCPLL_TypeDef *sl_device_peripheral_socpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SOCPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYMCRYPTO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYMCRYPTO_TypeDef *sl_device_peripheral_symcrypto_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYMCRYPTO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSCFG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSCFG_TypeDef *sl_device_peripheral_syscfg_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSCFG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSCFG_CFGNS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSCFG_CFGNS_TypeDef *sl_device_peripheral_syscfg_cfgns_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSCFG_CFGNS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSRTC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSRTC_TypeDef *sl_device_peripheral_sysrtc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSRTC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for TIMER. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline TIMER_TypeDef *sl_device_peripheral_timer_get_base_addr(const sl_peripheral_t peripheral) +{ + return (TIMER_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ULFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ULFRCO_TypeDef *sl_device_peripheral_ulfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ULFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USART. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USART_TypeDef *sl_device_peripheral_usart_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USART_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USBAHB_AHBS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USBAHB_AHBS_TypeDef *sl_device_peripheral_usbahb_ahbs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USBAHB_AHBS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USBPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USBPLL_TypeDef *sl_device_peripheral_usbpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USBPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USB_APBS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USB_APBS_TypeDef *sl_device_peripheral_usb_apbs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USB_APBS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for VDAC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline VDAC_TypeDef *sl_device_peripheral_vdac_get_base_addr(const sl_peripheral_t peripheral) +{ + return (VDAC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for WDOG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline WDOG_TypeDef *sl_device_peripheral_wdog_get_base_addr(const sl_peripheral_t peripheral) +{ + return (WDOG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The clock branch getter. + * + * @param peripheral A pointer to peripheral. + * + * @return The clock branch of the peripheral. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DEVICE_PERIPHERAL, SL_CODE_CLASS_TIME_CRITICAL) +inline sl_clock_branch_t sl_device_peripheral_get_clock_branch(const sl_peripheral_t peripheral) +{ + return peripheral->clk_branch; +} + +/***************************************************************************//** + * The bus clock getter. + * + * @param peripheral A pointer to peripheral. + * + * @return The bus clock of the peripheral. + ******************************************************************************/ +inline sl_bus_clock_t sl_device_peripheral_get_bus_clock(const sl_peripheral_t peripheral) +{ + return peripheral->bus_clock; +} + +/** @} (end addtogroup device_peripheral) */ + +#ifdef __cplusplus +} +#endif + +#else +#if defined(DEVICE_PERIPHERAL_INTERNAL_PRESENT) +#include "sli_device_peripheral_internal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup device_peripheral Device Abstraction Peripheral + * @details + * ## Overview + * + * The Device Abstraction Peripheral module defines the different peripherals + * that exist across all Silicon Labs devices and their utility functions. + * + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// DEFINES + +/***************************************************************************//** + * @name Peripheral Defines + * Those defines can be used as constant of type sl_peripheral_t. + * The values of those defines are device specific. + * @{ + ******************************************************************************/ + +/// Define pointer to ADC0 peripheral structure. +#define SL_PERIPHERAL_ADC0 (&sl_peripheral_val_adc0) + + +/// Define pointer to BUFC peripheral structure. +#define SL_PERIPHERAL_BUFC (&sl_peripheral_val_bufc) + +/// Define pointer to CRYPTOACC peripheral structure. +#define SL_PERIPHERAL_CRYPTOACC (&sl_peripheral_val_cryptoacc) + +// Declare peripheral structure for ADC. +typedef struct adc_typedef ADC_TypeDef; + + +// Declare peripheral structure for BUFC. +typedef struct bufc_typedef BUFC_TypeDef; + +// Declare peripheral structure for CRYPTOACC. +typedef struct cryptoacc_typedef CRYPTOACC_TypeDef; + +// Declare peripheral structure for CRYPTOACC_PKCTRL. +typedef struct cryptoacc_pkctrl_typedef CRYPTOACC_PKCTRL_TypeDef; + +// Declare peripheral structure for CRYPTOACC_RNGCTRL. +typedef struct cryptoacc_rngctrl_typedef CRYPTOACC_RNGCTRL_TypeDef; + + +// External declaration for ADC0 peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_adc0; + +// External declaration for BUFC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_bufc; + +// External declaration for CRYPTOACC peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_cryptoacc; + + +// ---------------------------------------------------------------------------- +// FUNCTIONS + +/***************************************************************************//** + * The base address getter for ACMP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ACMP_TypeDef *sl_device_peripheral_acmp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ACMP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ADC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ADC_TypeDef *sl_device_peripheral_adc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ADC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for AES. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline AES_TypeDef *sl_device_peripheral_aes_get_base_addr(const sl_peripheral_t peripheral) +{ + return (AES_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for AMUXCP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline AMUXCP_TypeDef *sl_device_peripheral_amuxcp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (AMUXCP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BUFC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BUFC_TypeDef *sl_device_peripheral_bufc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BUFC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BURAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BURAM_TypeDef *sl_device_peripheral_buram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BURAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for BURTC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline BURTC_TypeDef *sl_device_peripheral_burtc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (BURTC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CMU_TypeDef *sl_device_peripheral_cmu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_TypeDef *sl_device_peripheral_cryptoacc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC_PKCTRL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_PKCTRL_TypeDef *sl_device_peripheral_cryptoacc_pkctrl_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_PKCTRL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for CRYPTOACC_RNGCTRL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline CRYPTOACC_RNGCTRL_TypeDef *sl_device_peripheral_cryptoacc_rngctrl_get_base_addr(const sl_peripheral_t peripheral) +{ + return (CRYPTOACC_RNGCTRL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DCDC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DCDC_TypeDef *sl_device_peripheral_dcdc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DCDC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DEVINFO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DEVINFO_TypeDef *sl_device_peripheral_devinfo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DEVINFO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for DPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline DPLL_TypeDef *sl_device_peripheral_dpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (DPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EMU_TypeDef *sl_device_peripheral_emu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EMU_CFGNS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EMU_CFGNS_TypeDef *sl_device_peripheral_emu_cfgns_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EMU_CFGNS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ETAMPDET. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ETAMPDET_TypeDef *sl_device_peripheral_etampdet_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ETAMPDET_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for EUSART. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline EUSART_TypeDef *sl_device_peripheral_eusart_get_base_addr(const sl_peripheral_t peripheral) +{ + return (EUSART_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for FSRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline FSRCO_TypeDef *sl_device_peripheral_fsrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (FSRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for GPCRC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline GPCRC_TypeDef *sl_device_peripheral_gpcrc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (GPCRC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for GPIO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline GPIO_TypeDef *sl_device_peripheral_gpio_get_base_addr(const sl_peripheral_t peripheral) +{ + return (GPIO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HFRCO_TypeDef *sl_device_peripheral_hfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HFXO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HFXO_TypeDef *sl_device_peripheral_hfxo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HFXO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HOSTPORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HOSTPORTAL_TypeDef *sl_device_peripheral_hostportal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HOSTPORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for HYDRARAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline HYDRARAM_TypeDef *sl_device_peripheral_hydraram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (HYDRARAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for I2C. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline I2C_TypeDef *sl_device_peripheral_i2c_get_base_addr(const sl_peripheral_t peripheral) +{ + return (I2C_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for IADC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline IADC_TypeDef *sl_device_peripheral_iadc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (IADC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ICACHE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ICACHE_TypeDef *sl_device_peripheral_icache_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ICACHE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for KEYSCAN. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline KEYSCAN_TypeDef *sl_device_peripheral_keyscan_get_base_addr(const sl_peripheral_t peripheral) +{ + return (KEYSCAN_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for L2CACHE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline L2CACHE_TypeDef *sl_device_peripheral_l2cache_get_base_addr(const sl_peripheral_t peripheral) +{ + return (L2CACHE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LCD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LCD_TypeDef *sl_device_peripheral_lcd_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LCD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LCDRF. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LCDRF_TypeDef *sl_device_peripheral_lcdrf_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LCDRF_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LDMA. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LDMA_TypeDef *sl_device_peripheral_ldma_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LDMA_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LDMAXBAR. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LDMAXBAR_TypeDef *sl_device_peripheral_ldmaxbar_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LDMAXBAR_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LEDDRV. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LEDDRV_TypeDef *sl_device_peripheral_leddrv_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LEDDRV_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LESENSE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LESENSE_TypeDef *sl_device_peripheral_lesense_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LESENSE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LETIMER. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LETIMER_TypeDef *sl_device_peripheral_letimer_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LETIMER_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LFRCO_TypeDef *sl_device_peripheral_lfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LFXO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LFXO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LPWAES. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LPWAES_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LPW0PORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LPW0PORTAL_TypeDef *sl_device_peripheral_lpw0portal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LPW0PORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for LVGD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LVGD_TypeDef *sl_device_peripheral_lvgd_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LVGD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MAILBOX. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MAILBOX_TypeDef *sl_device_peripheral_mailbox_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MAILBOX_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MPAHBRAM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MPAHBRAM_TypeDef *sl_device_peripheral_mpahbram_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MPAHBRAM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MSC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MSC_TypeDef *sl_device_peripheral_msc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MSC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for MVP. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline MVP_TypeDef *sl_device_peripheral_mvp_get_base_addr(const sl_peripheral_t peripheral) +{ + return (MVP_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PCNT. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PCNT_TypeDef *sl_device_peripheral_pcnt_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PCNT_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PDM. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PDM_TypeDef *sl_device_peripheral_pdm_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PDM_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PFMXPPRF. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PFMXPPRF_TypeDef *sl_device_peripheral_pfmxpprf_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PFMXPPRF_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PIXELRZ. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PIXELRZ_TypeDef *sl_device_peripheral_pixelrz_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PIXELRZ_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for PRS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline PRS_TypeDef *sl_device_peripheral_prs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (PRS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RFFPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RFFPLL_TypeDef *sl_device_peripheral_rffpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RFFPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RPA. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RPA_TypeDef *sl_device_peripheral_rpa_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RPA_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for RTCC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline RTCC_TypeDef *sl_device_peripheral_rtcc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (RTCC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SCRATCHPAD. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SCRATCHPAD_TypeDef *sl_device_peripheral_scratchpad_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SCRATCHPAD_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAILBOX_AHBHOST. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAILBOX_AHBHOST_TypeDef *sl_device_peripheral_semailbox_ahbhost_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAILBOX_AHBHOST_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAILBOX_HOST. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAILBOX_HOST_TypeDef *sl_device_peripheral_semailbox_host_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAILBOX_HOST_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEMAPHORE. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEMAPHORE_TypeDef *sl_device_peripheral_semaphore_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEMAPHORE_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEPORTAL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEPORTAL_TypeDef *sl_device_peripheral_seportal_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEPORTAL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SEPUF_APBCFG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SEPUF_APBCFG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SMU_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SOCPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SOCPLL_TypeDef *sl_device_peripheral_socpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SOCPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYMCRYPTO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYMCRYPTO_TypeDef *sl_device_peripheral_symcrypto_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYMCRYPTO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSCFG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSCFG_TypeDef *sl_device_peripheral_syscfg_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSCFG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSCFG_CFGNS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSCFG_CFGNS_TypeDef *sl_device_peripheral_syscfg_cfgns_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSCFG_CFGNS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for SYSRTC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SYSRTC_TypeDef *sl_device_peripheral_sysrtc_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SYSRTC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for TIMER. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline TIMER_TypeDef *sl_device_peripheral_timer_get_base_addr(const sl_peripheral_t peripheral) +{ + return (TIMER_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for ULFRCO. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline ULFRCO_TypeDef *sl_device_peripheral_ulfrco_get_base_addr(const sl_peripheral_t peripheral) +{ + return (ULFRCO_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USART. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USART_TypeDef *sl_device_peripheral_usart_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USART_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USBAHB_AHBS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USBAHB_AHBS_TypeDef *sl_device_peripheral_usbahb_ahbs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USBAHB_AHBS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USBPLL. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USBPLL_TypeDef *sl_device_peripheral_usbpll_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USBPLL_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for USB_APBS. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline USB_APBS_TypeDef *sl_device_peripheral_usb_apbs_get_base_addr(const sl_peripheral_t peripheral) +{ + return (USB_APBS_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for VDAC. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline VDAC_TypeDef *sl_device_peripheral_vdac_get_base_addr(const sl_peripheral_t peripheral) +{ + return (VDAC_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The base address getter for WDOG. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline WDOG_TypeDef *sl_device_peripheral_wdog_get_base_addr(const sl_peripheral_t peripheral) +{ + return (WDOG_TypeDef *)peripheral->base; +} + +/***************************************************************************//** + * The clock branch getter. + * + * @param peripheral A pointer to peripheral. + * + * @return The clock branch of the peripheral. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DEVICE_PERIPHERAL, SL_CODE_CLASS_TIME_CRITICAL) +inline sl_clock_branch_t sl_device_peripheral_get_clock_branch(const sl_peripheral_t peripheral) +{ + return peripheral->clk_branch; +} + +/***************************************************************************//** + * The bus clock getter. + * + * @param peripheral A pointer to peripheral. + * + * @return The bus clock of the peripheral. + ******************************************************************************/ +inline sl_bus_clock_t sl_device_peripheral_get_bus_clock(const sl_peripheral_t peripheral) +{ + return peripheral->bus_clock; +} + +/** @} (end addtogroup device_peripheral) */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif // SL_DEVICE_PERIPHERAL_H diff --git a/Libs/platform/service/device_manager/inc/sl_device_peripheral_types.h b/Libs/platform/service/device_manager/inc/sl_device_peripheral_types.h new file mode 100644 index 0000000..eea9d62 --- /dev/null +++ b/Libs/platform/service/device_manager/inc/sl_device_peripheral_types.h @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file + * @brief Device Manager API Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef SL_DEVICE_PERIPHERAL_TYPES_H +#define SL_DEVICE_PERIPHERAL_TYPES_H + +#include "sl_device_clock.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup device_peripheral Device Abstraction Peripheral + * + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// TYPEDEFS + +/// Define peripheral structure. +typedef struct sl_peripheral { + uint32_t base; ///< Peripheral base address. + sl_clock_branch_t clk_branch; ///< Peripheral clock branch. + sl_bus_clock_t bus_clock; ///< Peripheral bus clock. +} sl_peripheral_val_t; + +/// Define peripheral typedef. +typedef const sl_peripheral_val_t* sl_peripheral_t; + +/** @} (end addtogroup device_peripheral) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_PERIPHERAL_TYPES_H diff --git a/Libs/platform/service/device_manager/src/sl_device_clock.c b/Libs/platform/service/device_manager/src/sl_device_clock.c new file mode 100644 index 0000000..f24c3af --- /dev/null +++ b/Libs/platform/service/device_manager/src/sl_device_clock.c @@ -0,0 +1,351 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Clock API Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "sl_device_clock.h" +#include "cmsis_compiler.h" + +/***************************************************************************//** + * @addtogroup device_clock Device Manager Clock + * @{ + ******************************************************************************/ + +// External declaration for ACMP0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ACMP0_VALUE = 0xFFFFFFFF; + +// External declaration for ACMP1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ACMP1_VALUE = 0xFFFFFFFF; + +// External declaration for ADC0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ADC0_VALUE = 0xFFFFFFFF; + +// External declaration for AGC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_AGC_VALUE = 0xFFFFFFFF; + +// External declaration for AMUXCP0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE = 0xFFFFFFFF; + +// External declaration for BUFC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_BUFC_VALUE = 0xFFFFFFFF; + +// External declaration for BURAM peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_BURAM_VALUE = 0xFFFFFFFF; + +// External declaration for BURTC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_BURTC_VALUE = 0xFFFFFFFF; + +// External declaration for CRYPTOACC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_CRYPTOACC_VALUE = 0xFFFFFFFF; + +// External declaration for DCDC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_DCDC_VALUE = 0xFFFFFFFF; + +// External declaration for DEVINFO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_DEVINFO_VALUE = 0xFFFFFFFF; + +// External declaration for DMEM peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_DMEM_VALUE = 0xFFFFFFFF; + +// External declaration for DPLL0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_DPLL0_VALUE = 0xFFFFFFFF; + +// External declaration for ECAIFADC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ECAIFADC_VALUE = 0xFFFFFFFF; + +// External declaration for ETAMPDET peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ETAMPDET_VALUE = 0xFFFFFFFF; + +// External declaration for EUART0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUART0_VALUE = 0xFFFFFFFF; + +// External declaration for EUSART0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUSART0_VALUE = 0xFFFFFFFF; + +// External declaration for EUSART1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUSART1_VALUE = 0xFFFFFFFF; + +// External declaration for EUSART2 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUSART2_VALUE = 0xFFFFFFFF; + +// External declaration for EUSART3 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUSART3_VALUE = 0xFFFFFFFF; + +// External declaration for EUSART4 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_EUSART4_VALUE = 0xFFFFFFFF; + +// External declaration for FRC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_FRC_VALUE = 0xFFFFFFFF; + +// External declaration for FSRCO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_FSRCO_VALUE = 0xFFFFFFFF; + +// External declaration for GPCRC0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE = 0xFFFFFFFF; + +// External declaration for GPIO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_GPIO_VALUE = 0xFFFFFFFF; + +// External declaration for HFRCO0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE = 0xFFFFFFFF; + +// External declaration for HFRCOEM23 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_HFRCOEM23_VALUE = 0xFFFFFFFF; + +// External declaration for HFXO0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_HFXO0_VALUE = 0xFFFFFFFF; + +// External declaration for HOSTMAILBOX peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_HOSTMAILBOX_VALUE = 0xFFFFFFFF; + +// External declaration for HOSTPORTAL peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_HOSTPORTAL_VALUE = 0xFFFFFFFF; + +// External declaration for I2C0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_I2C0_VALUE = 0xFFFFFFFF; + +// External declaration for I2C1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_I2C1_VALUE = 0xFFFFFFFF; + +// External declaration for I2C2 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_I2C2_VALUE = 0xFFFFFFFF; + +// External declaration for I2C3 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_I2C3_VALUE = 0xFFFFFFFF; + +// External declaration for IADC0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_IADC0_VALUE = 0xFFFFFFFF; + +// External declaration for ICACHE0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE = 0xFFFFFFFF; + +// External declaration for IFADCDEBUG peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_IFADCDEBUG_VALUE = 0xFFFFFFFF; + +// External declaration for KEYSCAN peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_KEYSCAN_VALUE = 0xFFFFFFFF; + +// External declaration for KSU peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_KSU_VALUE = 0xFFFFFFFF; + +// External declaration for L2ICACHE0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_L2ICACHE0_VALUE = 0xFFFFFFFF; + +// External declaration for LCD peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LCD_VALUE = 0xFFFFFFFF; + +// External declaration for LDMA0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LDMA0_VALUE = 0xFFFFFFFF; + +// External declaration for LDMAXBAR0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE = 0xFFFFFFFF; + +// External declaration for LEDDRV0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LEDDRV0_VALUE = 0xFFFFFFFF; + +// External declaration for LESENSE peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LESENSE_VALUE = 0xFFFFFFFF; + +// External declaration for LETIMER0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE = 0xFFFFFFFF; + +// External declaration for LFRCO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = 0xFFFFFFFF; + +// External declaration for LFXO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LFXO_VALUE = 0xFFFFFFFF; + +// External declaration for LPWAES peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LPWAES_VALUE = 0xFFFFFFFF; + +// External declaration for LPW0PORTAL peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE = 0xFFFFFFFF; + +// External declaration for MODEM peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_MODEM_VALUE = 0xFFFFFFFF; + +// External declaration for MSC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_MSC_VALUE = 0xFFFFFFFF; + +// External declaration for MVP peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_MVP_VALUE = 0xFFFFFFFF; + +// External declaration for PCNT0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PCNT0_VALUE = 0xFFFFFFFF; + +// External declaration for PDM peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PDM_VALUE = 0xFFFFFFFF; + +// External declaration for PIXELRZ0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PIXELRZ0_VALUE = 0xFFFFFFFF; + +// External declaration for PIXELRZ1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PIXELRZ1_VALUE = 0xFFFFFFFF; + +// External declaration for PRORTC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PRORTC_VALUE = 0xFFFFFFFF; + +// External declaration for PROTIMER peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE = 0xFFFFFFFF; + +// External declaration for PRS peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_PRS_VALUE = 0xFFFFFFFF; + +// External declaration for RAC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RAC_VALUE = 0xFFFFFFFF; + +// External declaration for RADIOAES peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE = 0xFFFFFFFF; + +// External declaration for RDMAILBOX0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RDMAILBOX0_VALUE = 0xFFFFFFFF; + +// External declaration for RDMAILBOX1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RDMAILBOX1_VALUE = 0xFFFFFFFF; + +// External declaration for RDSCRATCHPAD peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RDSCRATCHPAD_VALUE = 0xFFFFFFFF; + +// External declaration for RFCRC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFCRC_VALUE = 0xFFFFFFFF; + +// External declaration for RFECA0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFECA0_VALUE = 0xFFFFFFFF; + +// External declaration for RFECA1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFECA1_VALUE = 0xFFFFFFFF; + +// External declaration for RFFPLL0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFFPLL0_VALUE = 0xFFFFFFFF; + +// External declaration for RFMAILBOX peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFMAILBOX_VALUE = 0xFFFFFFFF; + +// External declaration for RFSCRATCHPAD peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFSCRATCHPAD_VALUE = 0xFFFFFFFF; + +// External declaration for RFSENSE peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RFSENSE_VALUE = 0xFFFFFFFF; + +// External declaration for RPA peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RPA_VALUE = 0xFFFFFFFF; + +// External declaration for RTCC peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_RTCC_VALUE = 0xFFFFFFFF; + +// External declaration for SCRATCHPAD peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SCRATCHPAD_VALUE = 0xFFFFFFFF; + +// External declaration for SEMAILBOX peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE = 0xFFFFFFFF; + +// External declaration for SEMAPHORE0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SEMAPHORE0_VALUE = 0xFFFFFFFF; + +// External declaration for SEMAPHORE1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SEMAPHORE1_VALUE = 0xFFFFFFFF; + +// External declaration for SEPORTAL peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SEPORTAL_VALUE = 0xFFFFFFFF; + +// External declaration for SMU peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SMU_VALUE = 0xFFFFFFFF; + +// External declaration for SOCPLL0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SOCPLL0_VALUE = 0xFFFFFFFF; + +// External declaration for SYMCRYPTO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SYMCRYPTO_VALUE = 0xFFFFFFFF; + +// External declaration for SYNTH peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SYNTH_VALUE = 0xFFFFFFFF; + +// External declaration for SYSCFG peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE = 0xFFFFFFFF; + +// External declaration for SYSRTC0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_SYSRTC0_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER0_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER1_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER2 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER2_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER3 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER3_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER4 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER4_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER5 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER5_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER6 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER6_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER7 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER7_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER8 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER8_VALUE = 0xFFFFFFFF; + +// External declaration for TIMER9 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_TIMER9_VALUE = 0xFFFFFFFF; + +// External declaration for ULFRCO peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE = 0xFFFFFFFF; + +// External declaration for USART0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_USART0_VALUE = 0xFFFFFFFF; + +// External declaration for USART1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_USART1_VALUE = 0xFFFFFFFF; + +// External declaration for USART2 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_USART2_VALUE = 0xFFFFFFFF; + +// External declaration for USB peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_USB_VALUE = 0xFFFFFFFF; + +// External declaration for VDAC0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_VDAC0_VALUE = 0xFFFFFFFF; + +// External declaration for VDAC1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_VDAC1_VALUE = 0xFFFFFFFF; + +// External declaration for WDOG0 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_WDOG0_VALUE = 0xFFFFFFFF; + +// External declaration for WDOG1 peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_WDOG1_VALUE = 0xFFFFFFFF; + +/** @} (end addtogroup device_clock) */ diff --git a/Libs/platform/service/device_manager/src/sl_device_gpio.c b/Libs/platform/service/device_manager/src/sl_device_gpio.c new file mode 100644 index 0000000..0910971 --- /dev/null +++ b/Libs/platform/service/device_manager/src/sl_device_gpio.c @@ -0,0 +1,403 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Clock API Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "sl_device_gpio.h" +#include "cmsis_compiler.h" + +/***************************************************************************//** + * @addtogroup device_gpio Device Manager GPIO + * @{ + ******************************************************************************/ + +/// Declarations for port and pins +const sl_gpio_t pa0 = { .port = SL_GPIO_PORT_A, .pin = 0 }; +const sl_gpio_t pa1 = { .port = SL_GPIO_PORT_A, .pin = 1 }; +const sl_gpio_t pa2 = { .port = SL_GPIO_PORT_A, .pin = 2 }; +const sl_gpio_t pa3 = { .port = SL_GPIO_PORT_A, .pin = 3 }; +const sl_gpio_t pa4 = { .port = SL_GPIO_PORT_A, .pin = 4 }; +const sl_gpio_t pa5 = { .port = SL_GPIO_PORT_A, .pin = 5 }; +const sl_gpio_t pa6 = { .port = SL_GPIO_PORT_A, .pin = 6 }; +const sl_gpio_t pa7 = { .port = SL_GPIO_PORT_A, .pin = 7 }; +const sl_gpio_t pa8 = { .port = SL_GPIO_PORT_A, .pin = 8 }; +const sl_gpio_t pa9 = { .port = SL_GPIO_PORT_A, .pin = 9 }; +const sl_gpio_t pa10 = { .port = SL_GPIO_PORT_A, .pin = 10 }; +const sl_gpio_t pa11 = { .port = SL_GPIO_PORT_A, .pin = 11 }; +const sl_gpio_t pa12 = { .port = SL_GPIO_PORT_A, .pin = 12 }; +const sl_gpio_t pa13 = { .port = SL_GPIO_PORT_A, .pin = 13 }; +const sl_gpio_t pa14 = { .port = SL_GPIO_PORT_A, .pin = 14 }; +const sl_gpio_t pa15 = { .port = SL_GPIO_PORT_A, .pin = 15 }; +const sl_gpio_t pa16 = { .port = SL_GPIO_PORT_A, .pin = 16 }; +const sl_gpio_t pa17 = { .port = SL_GPIO_PORT_A, .pin = 17 }; +const sl_gpio_t pa18 = { .port = SL_GPIO_PORT_A, .pin = 18 }; +const sl_gpio_t pa19 = { .port = SL_GPIO_PORT_A, .pin = 19 }; +const sl_gpio_t pa20 = { .port = SL_GPIO_PORT_A, .pin = 20 }; +const sl_gpio_t pa21 = { .port = SL_GPIO_PORT_A, .pin = 21 }; +const sl_gpio_t pa22 = { .port = SL_GPIO_PORT_A, .pin = 22 }; +const sl_gpio_t pa23 = { .port = SL_GPIO_PORT_A, .pin = 23 }; +const sl_gpio_t pa24 = { .port = SL_GPIO_PORT_A, .pin = 24 }; +const sl_gpio_t pa25 = { .port = SL_GPIO_PORT_A, .pin = 25 }; +const sl_gpio_t pa26 = { .port = SL_GPIO_PORT_A, .pin = 26 }; +const sl_gpio_t pa27 = { .port = SL_GPIO_PORT_A, .pin = 27 }; +const sl_gpio_t pa28 = { .port = SL_GPIO_PORT_A, .pin = 28 }; +const sl_gpio_t pa29 = { .port = SL_GPIO_PORT_A, .pin = 29 }; +const sl_gpio_t pa30 = { .port = SL_GPIO_PORT_A, .pin = 30 }; +const sl_gpio_t pa31 = { .port = SL_GPIO_PORT_A, .pin = 31 }; + +const sl_gpio_t pb0 = { .port = SL_GPIO_PORT_B, .pin = 0 }; +const sl_gpio_t pb1 = { .port = SL_GPIO_PORT_B, .pin = 1 }; +const sl_gpio_t pb2 = { .port = SL_GPIO_PORT_B, .pin = 2 }; +const sl_gpio_t pb3 = { .port = SL_GPIO_PORT_B, .pin = 3 }; +const sl_gpio_t pb4 = { .port = SL_GPIO_PORT_B, .pin = 4 }; +const sl_gpio_t pb5 = { .port = SL_GPIO_PORT_B, .pin = 5 }; +const sl_gpio_t pb6 = { .port = SL_GPIO_PORT_B, .pin = 6 }; +const sl_gpio_t pb7 = { .port = SL_GPIO_PORT_B, .pin = 7 }; +const sl_gpio_t pb8 = { .port = SL_GPIO_PORT_B, .pin = 8 }; +const sl_gpio_t pb9 = { .port = SL_GPIO_PORT_B, .pin = 9 }; +const sl_gpio_t pb10 = { .port = SL_GPIO_PORT_B, .pin = 10 }; +const sl_gpio_t pb11 = { .port = SL_GPIO_PORT_B, .pin = 11 }; +const sl_gpio_t pb12 = { .port = SL_GPIO_PORT_B, .pin = 12 }; +const sl_gpio_t pb13 = { .port = SL_GPIO_PORT_B, .pin = 13 }; +const sl_gpio_t pb14 = { .port = SL_GPIO_PORT_B, .pin = 14 }; +const sl_gpio_t pb15 = { .port = SL_GPIO_PORT_B, .pin = 15 }; +const sl_gpio_t pb16 = { .port = SL_GPIO_PORT_B, .pin = 16 }; +const sl_gpio_t pb17 = { .port = SL_GPIO_PORT_B, .pin = 17 }; +const sl_gpio_t pb18 = { .port = SL_GPIO_PORT_B, .pin = 18 }; +const sl_gpio_t pb19 = { .port = SL_GPIO_PORT_B, .pin = 19 }; +const sl_gpio_t pb20 = { .port = SL_GPIO_PORT_B, .pin = 20 }; +const sl_gpio_t pb21 = { .port = SL_GPIO_PORT_B, .pin = 21 }; +const sl_gpio_t pb22 = { .port = SL_GPIO_PORT_B, .pin = 22 }; +const sl_gpio_t pb23 = { .port = SL_GPIO_PORT_B, .pin = 23 }; +const sl_gpio_t pb24 = { .port = SL_GPIO_PORT_B, .pin = 24 }; +const sl_gpio_t pb25 = { .port = SL_GPIO_PORT_B, .pin = 25 }; +const sl_gpio_t pb26 = { .port = SL_GPIO_PORT_B, .pin = 26 }; +const sl_gpio_t pb27 = { .port = SL_GPIO_PORT_B, .pin = 27 }; +const sl_gpio_t pb28 = { .port = SL_GPIO_PORT_B, .pin = 28 }; +const sl_gpio_t pb29 = { .port = SL_GPIO_PORT_B, .pin = 29 }; +const sl_gpio_t pb30 = { .port = SL_GPIO_PORT_B, .pin = 30 }; +const sl_gpio_t pb31 = { .port = SL_GPIO_PORT_B, .pin = 31 }; + +const sl_gpio_t pc0 = { .port = SL_GPIO_PORT_C, .pin = 0 }; +const sl_gpio_t pc1 = { .port = SL_GPIO_PORT_C, .pin = 1 }; +const sl_gpio_t pc2 = { .port = SL_GPIO_PORT_C, .pin = 2 }; +const sl_gpio_t pc3 = { .port = SL_GPIO_PORT_C, .pin = 3 }; +const sl_gpio_t pc4 = { .port = SL_GPIO_PORT_C, .pin = 4 }; +const sl_gpio_t pc5 = { .port = SL_GPIO_PORT_C, .pin = 5 }; +const sl_gpio_t pc6 = { .port = SL_GPIO_PORT_C, .pin = 6 }; +const sl_gpio_t pc7 = { .port = SL_GPIO_PORT_C, .pin = 7 }; +const sl_gpio_t pc8 = { .port = SL_GPIO_PORT_C, .pin = 8 }; +const sl_gpio_t pc9 = { .port = SL_GPIO_PORT_C, .pin = 9 }; +const sl_gpio_t pc10 = { .port = SL_GPIO_PORT_C, .pin = 10 }; +const sl_gpio_t pc11 = { .port = SL_GPIO_PORT_C, .pin = 11 }; +const sl_gpio_t pc12 = { .port = SL_GPIO_PORT_C, .pin = 12 }; +const sl_gpio_t pc13 = { .port = SL_GPIO_PORT_C, .pin = 13 }; +const sl_gpio_t pc14 = { .port = SL_GPIO_PORT_C, .pin = 14 }; +const sl_gpio_t pc15 = { .port = SL_GPIO_PORT_C, .pin = 15 }; +const sl_gpio_t pc16 = { .port = SL_GPIO_PORT_C, .pin = 16 }; +const sl_gpio_t pc17 = { .port = SL_GPIO_PORT_C, .pin = 17 }; +const sl_gpio_t pc18 = { .port = SL_GPIO_PORT_C, .pin = 18 }; +const sl_gpio_t pc19 = { .port = SL_GPIO_PORT_C, .pin = 19 }; +const sl_gpio_t pc20 = { .port = SL_GPIO_PORT_C, .pin = 20 }; +const sl_gpio_t pc21 = { .port = SL_GPIO_PORT_C, .pin = 21 }; +const sl_gpio_t pc22 = { .port = SL_GPIO_PORT_C, .pin = 22 }; +const sl_gpio_t pc23 = { .port = SL_GPIO_PORT_C, .pin = 23 }; +const sl_gpio_t pc24 = { .port = SL_GPIO_PORT_C, .pin = 24 }; +const sl_gpio_t pc25 = { .port = SL_GPIO_PORT_C, .pin = 25 }; +const sl_gpio_t pc26 = { .port = SL_GPIO_PORT_C, .pin = 26 }; +const sl_gpio_t pc27 = { .port = SL_GPIO_PORT_C, .pin = 27 }; +const sl_gpio_t pc28 = { .port = SL_GPIO_PORT_C, .pin = 28 }; +const sl_gpio_t pc29 = { .port = SL_GPIO_PORT_C, .pin = 29 }; +const sl_gpio_t pc30 = { .port = SL_GPIO_PORT_C, .pin = 30 }; +const sl_gpio_t pc31 = { .port = SL_GPIO_PORT_C, .pin = 31 }; + +const sl_gpio_t pd0 = { .port = SL_GPIO_PORT_D, .pin = 0 }; +const sl_gpio_t pd1 = { .port = SL_GPIO_PORT_D, .pin = 1 }; +const sl_gpio_t pd2 = { .port = SL_GPIO_PORT_D, .pin = 2 }; +const sl_gpio_t pd3 = { .port = SL_GPIO_PORT_D, .pin = 3 }; +const sl_gpio_t pd4 = { .port = SL_GPIO_PORT_D, .pin = 4 }; +const sl_gpio_t pd5 = { .port = SL_GPIO_PORT_D, .pin = 5 }; +const sl_gpio_t pd6 = { .port = SL_GPIO_PORT_D, .pin = 6 }; +const sl_gpio_t pd7 = { .port = SL_GPIO_PORT_D, .pin = 7 }; +const sl_gpio_t pd8 = { .port = SL_GPIO_PORT_D, .pin = 8 }; +const sl_gpio_t pd9 = { .port = SL_GPIO_PORT_D, .pin = 9 }; +const sl_gpio_t pd10 = { .port = SL_GPIO_PORT_D, .pin = 10 }; +const sl_gpio_t pd11 = { .port = SL_GPIO_PORT_D, .pin = 11 }; +const sl_gpio_t pd12 = { .port = SL_GPIO_PORT_D, .pin = 12 }; +const sl_gpio_t pd13 = { .port = SL_GPIO_PORT_D, .pin = 13 }; +const sl_gpio_t pd14 = { .port = SL_GPIO_PORT_D, .pin = 14 }; +const sl_gpio_t pd15 = { .port = SL_GPIO_PORT_D, .pin = 15 }; +const sl_gpio_t pd16 = { .port = SL_GPIO_PORT_D, .pin = 16 }; +const sl_gpio_t pd17 = { .port = SL_GPIO_PORT_D, .pin = 17 }; +const sl_gpio_t pd18 = { .port = SL_GPIO_PORT_D, .pin = 18 }; +const sl_gpio_t pd19 = { .port = SL_GPIO_PORT_D, .pin = 19 }; +const sl_gpio_t pd20 = { .port = SL_GPIO_PORT_D, .pin = 20 }; +const sl_gpio_t pd21 = { .port = SL_GPIO_PORT_D, .pin = 21 }; +const sl_gpio_t pd22 = { .port = SL_GPIO_PORT_D, .pin = 22 }; +const sl_gpio_t pd23 = { .port = SL_GPIO_PORT_D, .pin = 23 }; +const sl_gpio_t pd24 = { .port = SL_GPIO_PORT_D, .pin = 24 }; +const sl_gpio_t pd25 = { .port = SL_GPIO_PORT_D, .pin = 25 }; +const sl_gpio_t pd26 = { .port = SL_GPIO_PORT_D, .pin = 26 }; +const sl_gpio_t pd27 = { .port = SL_GPIO_PORT_D, .pin = 27 }; +const sl_gpio_t pd28 = { .port = SL_GPIO_PORT_D, .pin = 28 }; +const sl_gpio_t pd29 = { .port = SL_GPIO_PORT_D, .pin = 29 }; +const sl_gpio_t pd30 = { .port = SL_GPIO_PORT_D, .pin = 30 }; +const sl_gpio_t pd31 = { .port = SL_GPIO_PORT_D, .pin = 31 }; + +const sl_gpio_t pe0 = { .port = SL_GPIO_PORT_E, .pin = 0 }; +const sl_gpio_t pe1 = { .port = SL_GPIO_PORT_E, .pin = 1 }; +const sl_gpio_t pe2 = { .port = SL_GPIO_PORT_E, .pin = 2 }; +const sl_gpio_t pe3 = { .port = SL_GPIO_PORT_E, .pin = 3 }; +const sl_gpio_t pe4 = { .port = SL_GPIO_PORT_E, .pin = 4 }; +const sl_gpio_t pe5 = { .port = SL_GPIO_PORT_E, .pin = 5 }; +const sl_gpio_t pe6 = { .port = SL_GPIO_PORT_E, .pin = 6 }; +const sl_gpio_t pe7 = { .port = SL_GPIO_PORT_E, .pin = 7 }; +const sl_gpio_t pe8 = { .port = SL_GPIO_PORT_E, .pin = 8 }; +const sl_gpio_t pe9 = { .port = SL_GPIO_PORT_E, .pin = 9 }; +const sl_gpio_t pe10 = { .port = SL_GPIO_PORT_E, .pin = 10 }; +const sl_gpio_t pe11 = { .port = SL_GPIO_PORT_E, .pin = 11 }; +const sl_gpio_t pe12 = { .port = SL_GPIO_PORT_E, .pin = 12 }; +const sl_gpio_t pe13 = { .port = SL_GPIO_PORT_E, .pin = 13 }; +const sl_gpio_t pe14 = { .port = SL_GPIO_PORT_E, .pin = 14 }; +const sl_gpio_t pe15 = { .port = SL_GPIO_PORT_E, .pin = 15 }; +const sl_gpio_t pe16 = { .port = SL_GPIO_PORT_E, .pin = 16 }; +const sl_gpio_t pe17 = { .port = SL_GPIO_PORT_E, .pin = 17 }; +const sl_gpio_t pe18 = { .port = SL_GPIO_PORT_E, .pin = 18 }; +const sl_gpio_t pe19 = { .port = SL_GPIO_PORT_E, .pin = 19 }; +const sl_gpio_t pe20 = { .port = SL_GPIO_PORT_E, .pin = 20 }; +const sl_gpio_t pe21 = { .port = SL_GPIO_PORT_E, .pin = 21 }; +const sl_gpio_t pe22 = { .port = SL_GPIO_PORT_E, .pin = 22 }; +const sl_gpio_t pe23 = { .port = SL_GPIO_PORT_E, .pin = 23 }; +const sl_gpio_t pe24 = { .port = SL_GPIO_PORT_E, .pin = 24 }; +const sl_gpio_t pe25 = { .port = SL_GPIO_PORT_E, .pin = 25 }; +const sl_gpio_t pe26 = { .port = SL_GPIO_PORT_E, .pin = 26 }; +const sl_gpio_t pe27 = { .port = SL_GPIO_PORT_E, .pin = 27 }; +const sl_gpio_t pe28 = { .port = SL_GPIO_PORT_E, .pin = 28 }; +const sl_gpio_t pe29 = { .port = SL_GPIO_PORT_E, .pin = 29 }; +const sl_gpio_t pe30 = { .port = SL_GPIO_PORT_E, .pin = 30 }; +const sl_gpio_t pe31 = { .port = SL_GPIO_PORT_E, .pin = 31 }; + +const sl_gpio_t pf0 = { .port = SL_GPIO_PORT_F, .pin = 0 }; +const sl_gpio_t pf1 = { .port = SL_GPIO_PORT_F, .pin = 1 }; +const sl_gpio_t pf2 = { .port = SL_GPIO_PORT_F, .pin = 2 }; +const sl_gpio_t pf3 = { .port = SL_GPIO_PORT_F, .pin = 3 }; +const sl_gpio_t pf4 = { .port = SL_GPIO_PORT_F, .pin = 4 }; +const sl_gpio_t pf5 = { .port = SL_GPIO_PORT_F, .pin = 5 }; +const sl_gpio_t pf6 = { .port = SL_GPIO_PORT_F, .pin = 6 }; +const sl_gpio_t pf7 = { .port = SL_GPIO_PORT_F, .pin = 7 }; +const sl_gpio_t pf8 = { .port = SL_GPIO_PORT_F, .pin = 8 }; +const sl_gpio_t pf9 = { .port = SL_GPIO_PORT_F, .pin = 9 }; +const sl_gpio_t pf10 = { .port = SL_GPIO_PORT_F, .pin = 10 }; +const sl_gpio_t pf11 = { .port = SL_GPIO_PORT_F, .pin = 11 }; +const sl_gpio_t pf12 = { .port = SL_GPIO_PORT_F, .pin = 12 }; +const sl_gpio_t pf13 = { .port = SL_GPIO_PORT_F, .pin = 13 }; +const sl_gpio_t pf14 = { .port = SL_GPIO_PORT_F, .pin = 14 }; +const sl_gpio_t pf15 = { .port = SL_GPIO_PORT_F, .pin = 15 }; +const sl_gpio_t pf16 = { .port = SL_GPIO_PORT_F, .pin = 16 }; +const sl_gpio_t pf17 = { .port = SL_GPIO_PORT_F, .pin = 17 }; +const sl_gpio_t pf18 = { .port = SL_GPIO_PORT_F, .pin = 18 }; +const sl_gpio_t pf19 = { .port = SL_GPIO_PORT_F, .pin = 19 }; +const sl_gpio_t pf20 = { .port = SL_GPIO_PORT_F, .pin = 20 }; +const sl_gpio_t pf21 = { .port = SL_GPIO_PORT_F, .pin = 21 }; +const sl_gpio_t pf22 = { .port = SL_GPIO_PORT_F, .pin = 22 }; +const sl_gpio_t pf23 = { .port = SL_GPIO_PORT_F, .pin = 23 }; +const sl_gpio_t pf24 = { .port = SL_GPIO_PORT_F, .pin = 24 }; +const sl_gpio_t pf25 = { .port = SL_GPIO_PORT_F, .pin = 25 }; +const sl_gpio_t pf26 = { .port = SL_GPIO_PORT_F, .pin = 26 }; +const sl_gpio_t pf27 = { .port = SL_GPIO_PORT_F, .pin = 27 }; +const sl_gpio_t pf28 = { .port = SL_GPIO_PORT_F, .pin = 28 }; +const sl_gpio_t pf29 = { .port = SL_GPIO_PORT_F, .pin = 29 }; +const sl_gpio_t pf30 = { .port = SL_GPIO_PORT_F, .pin = 30 }; +const sl_gpio_t pf31 = { .port = SL_GPIO_PORT_F, .pin = 31 }; + +const sl_gpio_t pg0 = { .port = SL_GPIO_PORT_G, .pin = 0 }; +const sl_gpio_t pg1 = { .port = SL_GPIO_PORT_G, .pin = 1 }; +const sl_gpio_t pg2 = { .port = SL_GPIO_PORT_G, .pin = 2 }; +const sl_gpio_t pg3 = { .port = SL_GPIO_PORT_G, .pin = 3 }; +const sl_gpio_t pg4 = { .port = SL_GPIO_PORT_G, .pin = 4 }; +const sl_gpio_t pg5 = { .port = SL_GPIO_PORT_G, .pin = 5 }; +const sl_gpio_t pg6 = { .port = SL_GPIO_PORT_G, .pin = 6 }; +const sl_gpio_t pg7 = { .port = SL_GPIO_PORT_G, .pin = 7 }; +const sl_gpio_t pg8 = { .port = SL_GPIO_PORT_G, .pin = 8 }; +const sl_gpio_t pg9 = { .port = SL_GPIO_PORT_G, .pin = 9 }; +const sl_gpio_t pg10 = { .port = SL_GPIO_PORT_G, .pin = 10 }; +const sl_gpio_t pg11 = { .port = SL_GPIO_PORT_G, .pin = 11 }; +const sl_gpio_t pg12 = { .port = SL_GPIO_PORT_G, .pin = 12 }; +const sl_gpio_t pg13 = { .port = SL_GPIO_PORT_G, .pin = 13 }; +const sl_gpio_t pg14 = { .port = SL_GPIO_PORT_G, .pin = 14 }; +const sl_gpio_t pg15 = { .port = SL_GPIO_PORT_G, .pin = 15 }; +const sl_gpio_t pg16 = { .port = SL_GPIO_PORT_G, .pin = 16 }; +const sl_gpio_t pg17 = { .port = SL_GPIO_PORT_G, .pin = 17 }; +const sl_gpio_t pg18 = { .port = SL_GPIO_PORT_G, .pin = 18 }; +const sl_gpio_t pg19 = { .port = SL_GPIO_PORT_G, .pin = 19 }; +const sl_gpio_t pg20 = { .port = SL_GPIO_PORT_G, .pin = 20 }; +const sl_gpio_t pg21 = { .port = SL_GPIO_PORT_G, .pin = 21 }; +const sl_gpio_t pg22 = { .port = SL_GPIO_PORT_G, .pin = 22 }; +const sl_gpio_t pg23 = { .port = SL_GPIO_PORT_G, .pin = 23 }; +const sl_gpio_t pg24 = { .port = SL_GPIO_PORT_G, .pin = 24 }; +const sl_gpio_t pg25 = { .port = SL_GPIO_PORT_G, .pin = 25 }; +const sl_gpio_t pg26 = { .port = SL_GPIO_PORT_G, .pin = 26 }; +const sl_gpio_t pg27 = { .port = SL_GPIO_PORT_G, .pin = 27 }; +const sl_gpio_t pg28 = { .port = SL_GPIO_PORT_G, .pin = 28 }; +const sl_gpio_t pg29 = { .port = SL_GPIO_PORT_G, .pin = 29 }; +const sl_gpio_t pg30 = { .port = SL_GPIO_PORT_G, .pin = 30 }; +const sl_gpio_t pg31 = { .port = SL_GPIO_PORT_G, .pin = 31 }; + +const sl_gpio_t ph0 = { .port = SL_GPIO_PORT_H, .pin = 0 }; +const sl_gpio_t ph1 = { .port = SL_GPIO_PORT_H, .pin = 1 }; +const sl_gpio_t ph2 = { .port = SL_GPIO_PORT_H, .pin = 2 }; +const sl_gpio_t ph3 = { .port = SL_GPIO_PORT_H, .pin = 3 }; +const sl_gpio_t ph4 = { .port = SL_GPIO_PORT_H, .pin = 4 }; +const sl_gpio_t ph5 = { .port = SL_GPIO_PORT_H, .pin = 5 }; +const sl_gpio_t ph6 = { .port = SL_GPIO_PORT_H, .pin = 6 }; +const sl_gpio_t ph7 = { .port = SL_GPIO_PORT_H, .pin = 7 }; +const sl_gpio_t ph8 = { .port = SL_GPIO_PORT_H, .pin = 8 }; +const sl_gpio_t ph9 = { .port = SL_GPIO_PORT_H, .pin = 9 }; +const sl_gpio_t ph10 = { .port = SL_GPIO_PORT_H, .pin = 10 }; +const sl_gpio_t ph11 = { .port = SL_GPIO_PORT_H, .pin = 11 }; +const sl_gpio_t ph12 = { .port = SL_GPIO_PORT_H, .pin = 12 }; +const sl_gpio_t ph13 = { .port = SL_GPIO_PORT_H, .pin = 13 }; +const sl_gpio_t ph14 = { .port = SL_GPIO_PORT_H, .pin = 14 }; +const sl_gpio_t ph15 = { .port = SL_GPIO_PORT_H, .pin = 15 }; +const sl_gpio_t ph16 = { .port = SL_GPIO_PORT_H, .pin = 16 }; +const sl_gpio_t ph17 = { .port = SL_GPIO_PORT_H, .pin = 17 }; +const sl_gpio_t ph18 = { .port = SL_GPIO_PORT_H, .pin = 18 }; +const sl_gpio_t ph19 = { .port = SL_GPIO_PORT_H, .pin = 19 }; +const sl_gpio_t ph20 = { .port = SL_GPIO_PORT_H, .pin = 20 }; +const sl_gpio_t ph21 = { .port = SL_GPIO_PORT_H, .pin = 21 }; +const sl_gpio_t ph22 = { .port = SL_GPIO_PORT_H, .pin = 22 }; +const sl_gpio_t ph23 = { .port = SL_GPIO_PORT_H, .pin = 23 }; +const sl_gpio_t ph24 = { .port = SL_GPIO_PORT_H, .pin = 24 }; +const sl_gpio_t ph25 = { .port = SL_GPIO_PORT_H, .pin = 25 }; +const sl_gpio_t ph26 = { .port = SL_GPIO_PORT_H, .pin = 26 }; +const sl_gpio_t ph27 = { .port = SL_GPIO_PORT_H, .pin = 27 }; +const sl_gpio_t ph28 = { .port = SL_GPIO_PORT_H, .pin = 28 }; +const sl_gpio_t ph29 = { .port = SL_GPIO_PORT_H, .pin = 29 }; +const sl_gpio_t ph30 = { .port = SL_GPIO_PORT_H, .pin = 30 }; +const sl_gpio_t ph31 = { .port = SL_GPIO_PORT_H, .pin = 31 }; + +const sl_gpio_t pi0 = { .port = SL_GPIO_PORT_I, .pin = 0 }; +const sl_gpio_t pi1 = { .port = SL_GPIO_PORT_I, .pin = 1 }; +const sl_gpio_t pi2 = { .port = SL_GPIO_PORT_I, .pin = 2 }; +const sl_gpio_t pi3 = { .port = SL_GPIO_PORT_I, .pin = 3 }; +const sl_gpio_t pi4 = { .port = SL_GPIO_PORT_I, .pin = 4 }; +const sl_gpio_t pi5 = { .port = SL_GPIO_PORT_I, .pin = 5 }; +const sl_gpio_t pi6 = { .port = SL_GPIO_PORT_I, .pin = 6 }; +const sl_gpio_t pi7 = { .port = SL_GPIO_PORT_I, .pin = 7 }; +const sl_gpio_t pi8 = { .port = SL_GPIO_PORT_I, .pin = 8 }; +const sl_gpio_t pi9 = { .port = SL_GPIO_PORT_I, .pin = 9 }; +const sl_gpio_t pi10 = { .port = SL_GPIO_PORT_I, .pin = 10 }; +const sl_gpio_t pi11 = { .port = SL_GPIO_PORT_I, .pin = 11 }; +const sl_gpio_t pi12 = { .port = SL_GPIO_PORT_I, .pin = 12 }; +const sl_gpio_t pi13 = { .port = SL_GPIO_PORT_I, .pin = 13 }; +const sl_gpio_t pi14 = { .port = SL_GPIO_PORT_I, .pin = 14 }; +const sl_gpio_t pi15 = { .port = SL_GPIO_PORT_I, .pin = 15 }; +const sl_gpio_t pi16 = { .port = SL_GPIO_PORT_I, .pin = 16 }; +const sl_gpio_t pi17 = { .port = SL_GPIO_PORT_I, .pin = 17 }; +const sl_gpio_t pi18 = { .port = SL_GPIO_PORT_I, .pin = 18 }; +const sl_gpio_t pi19 = { .port = SL_GPIO_PORT_I, .pin = 19 }; +const sl_gpio_t pi20 = { .port = SL_GPIO_PORT_I, .pin = 20 }; +const sl_gpio_t pi21 = { .port = SL_GPIO_PORT_I, .pin = 21 }; +const sl_gpio_t pi22 = { .port = SL_GPIO_PORT_I, .pin = 22 }; +const sl_gpio_t pi23 = { .port = SL_GPIO_PORT_I, .pin = 23 }; +const sl_gpio_t pi24 = { .port = SL_GPIO_PORT_I, .pin = 24 }; +const sl_gpio_t pi25 = { .port = SL_GPIO_PORT_I, .pin = 25 }; +const sl_gpio_t pi26 = { .port = SL_GPIO_PORT_I, .pin = 26 }; +const sl_gpio_t pi27 = { .port = SL_GPIO_PORT_I, .pin = 27 }; +const sl_gpio_t pi28 = { .port = SL_GPIO_PORT_I, .pin = 28 }; +const sl_gpio_t pi29 = { .port = SL_GPIO_PORT_I, .pin = 29 }; +const sl_gpio_t pi30 = { .port = SL_GPIO_PORT_I, .pin = 30 }; +const sl_gpio_t pi31 = { .port = SL_GPIO_PORT_I, .pin = 31 }; + +const sl_gpio_t pj0 = { .port = SL_GPIO_PORT_J, .pin = 0 }; +const sl_gpio_t pj1 = { .port = SL_GPIO_PORT_J, .pin = 1 }; +const sl_gpio_t pj2 = { .port = SL_GPIO_PORT_J, .pin = 2 }; +const sl_gpio_t pj3 = { .port = SL_GPIO_PORT_J, .pin = 3 }; +const sl_gpio_t pj4 = { .port = SL_GPIO_PORT_J, .pin = 4 }; +const sl_gpio_t pj5 = { .port = SL_GPIO_PORT_J, .pin = 5 }; +const sl_gpio_t pj6 = { .port = SL_GPIO_PORT_J, .pin = 6 }; +const sl_gpio_t pj7 = { .port = SL_GPIO_PORT_J, .pin = 7 }; +const sl_gpio_t pj8 = { .port = SL_GPIO_PORT_J, .pin = 8 }; +const sl_gpio_t pj9 = { .port = SL_GPIO_PORT_J, .pin = 9 }; +const sl_gpio_t pj10 = { .port = SL_GPIO_PORT_J, .pin = 10 }; +const sl_gpio_t pj11 = { .port = SL_GPIO_PORT_J, .pin = 11 }; +const sl_gpio_t pj12 = { .port = SL_GPIO_PORT_J, .pin = 12 }; +const sl_gpio_t pj13 = { .port = SL_GPIO_PORT_J, .pin = 13 }; +const sl_gpio_t pj14 = { .port = SL_GPIO_PORT_J, .pin = 14 }; +const sl_gpio_t pj15 = { .port = SL_GPIO_PORT_J, .pin = 15 }; +const sl_gpio_t pj16 = { .port = SL_GPIO_PORT_J, .pin = 16 }; +const sl_gpio_t pj17 = { .port = SL_GPIO_PORT_J, .pin = 17 }; +const sl_gpio_t pj18 = { .port = SL_GPIO_PORT_J, .pin = 18 }; +const sl_gpio_t pj19 = { .port = SL_GPIO_PORT_J, .pin = 19 }; +const sl_gpio_t pj20 = { .port = SL_GPIO_PORT_J, .pin = 20 }; +const sl_gpio_t pj21 = { .port = SL_GPIO_PORT_J, .pin = 21 }; +const sl_gpio_t pj22 = { .port = SL_GPIO_PORT_J, .pin = 22 }; +const sl_gpio_t pj23 = { .port = SL_GPIO_PORT_J, .pin = 23 }; +const sl_gpio_t pj24 = { .port = SL_GPIO_PORT_J, .pin = 24 }; +const sl_gpio_t pj25 = { .port = SL_GPIO_PORT_J, .pin = 25 }; +const sl_gpio_t pj26 = { .port = SL_GPIO_PORT_J, .pin = 26 }; +const sl_gpio_t pj27 = { .port = SL_GPIO_PORT_J, .pin = 27 }; +const sl_gpio_t pj28 = { .port = SL_GPIO_PORT_J, .pin = 28 }; +const sl_gpio_t pj29 = { .port = SL_GPIO_PORT_J, .pin = 29 }; +const sl_gpio_t pj30 = { .port = SL_GPIO_PORT_J, .pin = 30 }; +const sl_gpio_t pj31 = { .port = SL_GPIO_PORT_J, .pin = 31 }; + +const sl_gpio_t pk0 = { .port = SL_GPIO_PORT_K, .pin = 0 }; +const sl_gpio_t pk1 = { .port = SL_GPIO_PORT_K, .pin = 1 }; +const sl_gpio_t pk2 = { .port = SL_GPIO_PORT_K, .pin = 2 }; +const sl_gpio_t pk3 = { .port = SL_GPIO_PORT_K, .pin = 3 }; +const sl_gpio_t pk4 = { .port = SL_GPIO_PORT_K, .pin = 4 }; +const sl_gpio_t pk5 = { .port = SL_GPIO_PORT_K, .pin = 5 }; +const sl_gpio_t pk6 = { .port = SL_GPIO_PORT_K, .pin = 6 }; +const sl_gpio_t pk7 = { .port = SL_GPIO_PORT_K, .pin = 7 }; +const sl_gpio_t pk8 = { .port = SL_GPIO_PORT_K, .pin = 8 }; +const sl_gpio_t pk9 = { .port = SL_GPIO_PORT_K, .pin = 9 }; +const sl_gpio_t pk10 = { .port = SL_GPIO_PORT_K, .pin = 10 }; +const sl_gpio_t pk11 = { .port = SL_GPIO_PORT_K, .pin = 11 }; +const sl_gpio_t pk12 = { .port = SL_GPIO_PORT_K, .pin = 12 }; +const sl_gpio_t pk13 = { .port = SL_GPIO_PORT_K, .pin = 13 }; +const sl_gpio_t pk14 = { .port = SL_GPIO_PORT_K, .pin = 14 }; +const sl_gpio_t pk15 = { .port = SL_GPIO_PORT_K, .pin = 15 }; +const sl_gpio_t pk16 = { .port = SL_GPIO_PORT_K, .pin = 16 }; +const sl_gpio_t pk17 = { .port = SL_GPIO_PORT_K, .pin = 17 }; +const sl_gpio_t pk18 = { .port = SL_GPIO_PORT_K, .pin = 18 }; +const sl_gpio_t pk19 = { .port = SL_GPIO_PORT_K, .pin = 19 }; +const sl_gpio_t pk20 = { .port = SL_GPIO_PORT_K, .pin = 20 }; +const sl_gpio_t pk21 = { .port = SL_GPIO_PORT_K, .pin = 21 }; +const sl_gpio_t pk22 = { .port = SL_GPIO_PORT_K, .pin = 22 }; +const sl_gpio_t pk23 = { .port = SL_GPIO_PORT_K, .pin = 23 }; +const sl_gpio_t pk24 = { .port = SL_GPIO_PORT_K, .pin = 24 }; +const sl_gpio_t pk25 = { .port = SL_GPIO_PORT_K, .pin = 25 }; +const sl_gpio_t pk26 = { .port = SL_GPIO_PORT_K, .pin = 26 }; +const sl_gpio_t pk27 = { .port = SL_GPIO_PORT_K, .pin = 27 }; +const sl_gpio_t pk28 = { .port = SL_GPIO_PORT_K, .pin = 28 }; +const sl_gpio_t pk29 = { .port = SL_GPIO_PORT_K, .pin = 29 }; +const sl_gpio_t pk30 = { .port = SL_GPIO_PORT_K, .pin = 30 }; +const sl_gpio_t pk31 = { .port = SL_GPIO_PORT_K, .pin = 31 }; + +/** @} (end addtogroup device_gpio) */ diff --git a/Libs/platform/service/device_manager/src/sl_device_peripheral.c b/Libs/platform/service/device_manager/src/sl_device_peripheral.c new file mode 100644 index 0000000..2fbb556 --- /dev/null +++ b/Libs/platform/service/device_manager/src/sl_device_peripheral.c @@ -0,0 +1,769 @@ +/**************************************************************************//** + * @file + * @brief Device Manager API Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "sl_device_peripheral.h" +#include "sl_device_clock.h" +#include "cmsis_compiler.h" +#include "em_device.h" +/***************************************************************************//** + * Device Abstraction Peripheral default values. + ******************************************************************************/ +// Weak definition of peripheral ACMP0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral ACMP1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_acmp1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral ADC0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_adc0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral AES. +__WEAK const sl_peripheral_val_t sl_peripheral_val_aes = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral AMUXCP0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_amuxcp0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral BUFC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_bufc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral BURAM. +__WEAK const sl_peripheral_val_t sl_peripheral_val_buram = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral BURTC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral CMU. +__WEAK const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral CRYPTOACC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_cryptoacc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DCDC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DEVINFO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_devinfo = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DMEM. +__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DMEM0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DMEM1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_dmem1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral DPLL0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EMU. +__WEAK const sl_peripheral_val_t sl_peripheral_val_emu = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral ETAMPDET. +__WEAK const sl_peripheral_val_t sl_peripheral_val_etampdet = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUART0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_euart0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUSART0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUSART1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUSART2. +__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart2 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUSART3. +__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart3 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral EUSART4. +__WEAK const sl_peripheral_val_t sl_peripheral_val_eusart4 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral FSRCO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral GPCRC0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral GPIO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_gpio = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral HFRCO0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_hfrco0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral HFRCOEM23. +__WEAK const sl_peripheral_val_t sl_peripheral_val_hfrcoem23 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral HFXO0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral HOSTMAILBOX. +__WEAK const sl_peripheral_val_t sl_peripheral_val_hostmailbox = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral HOSTPORTAL. +__WEAK const sl_peripheral_val_t sl_peripheral_val_hostportal = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral I2C0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral I2C1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral I2C2. +__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c2 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral I2C3. +__WEAK const sl_peripheral_val_t sl_peripheral_val_i2c3 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral IADC0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_iadc0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral ICACHE0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral KEYSCAN. +__WEAK const sl_peripheral_val_t sl_peripheral_val_keyscan = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral L1ICACHE0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_l1icache0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral L2ICACHE0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_l2icache0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LCD. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lcd = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LCDRF. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lcdrf = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LDMA0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_ldma0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LDMAXBAR0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LEDDRV0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_leddrv0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LESENSE. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lesense = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LETIMER0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_letimer0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LFRCO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lfrco = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LFXO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LPWAES. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lpwaes = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LPW0PORTAL. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lpw0portal = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral LVGD. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lvgd = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral MPAHBRAM. +__WEAK const sl_peripheral_val_t sl_peripheral_val_mpahbram = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral MSC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_msc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral MVP. +__WEAK const sl_peripheral_val_t sl_peripheral_val_mvp = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PCNT0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_pcnt0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PDM. +__WEAK const sl_peripheral_val_t sl_peripheral_val_pdm = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PFMXPPRF. +__WEAK const sl_peripheral_val_t sl_peripheral_val_pfmxpprf = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PIXELRZ0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_pixelrz0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PIXELRZ1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_pixelrz1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PRORTC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_prortc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral PRS. +__WEAK const sl_peripheral_val_t sl_peripheral_val_prs = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral RADIOAES. +__WEAK const sl_peripheral_val_t sl_peripheral_val_radioaes = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral RFFPLL0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_rffpll0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral RPA. +__WEAK const sl_peripheral_val_t sl_peripheral_val_rpa = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral RTCC. +__WEAK const sl_peripheral_val_t sl_peripheral_val_rtcc = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SCRATCHPAD. +__WEAK const sl_peripheral_val_t sl_peripheral_val_scratchpad = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SEMAILBOX. +__WEAK const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SEMAPHORE0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_semaphore0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SEMAPHORE1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_semaphore1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SEPORTAL. +__WEAK const sl_peripheral_val_t sl_peripheral_val_seportal = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SEPUF. +__WEAK const sl_peripheral_val_t sl_peripheral_val_sepuf = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SMU. +__WEAK const sl_peripheral_val_t sl_peripheral_val_smu = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SOCPLL0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_socpll0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SYMCRYPTO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_symcrypto = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SYSCFG. +__WEAK const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral SYSRTC0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_sysrtc0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER2. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer2 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER3. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer3 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER4. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer4 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER5. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer5 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER6. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer6 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER7. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer7 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER8. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer8 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral TIMER9. +__WEAK const sl_peripheral_val_t sl_peripheral_val_timer9 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral ULFRCO. +__WEAK const sl_peripheral_val_t sl_peripheral_val_ulfrco = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USART0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usart0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USART1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usart1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USART2. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usart2 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USB. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usb = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USBAHB. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usbahb = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral USBPLL0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_usbpll0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral VDAC0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_vdac0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral VDAC1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_vdac1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral WDOG0. +__WEAK const sl_peripheral_val_t sl_peripheral_val_wdog0 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +// Weak definition of peripheral WDOG1. +__WEAK const sl_peripheral_val_t sl_peripheral_val_wdog1 = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + +#if defined(__ICCARM__) +// Disable IAR multiple typedefs declaration warning. +#pragma diag_suppress=Pe301 +#endif + +// External base address getter declaration for ACMP. +extern ACMP_TypeDef *sl_device_peripheral_acmp_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for ADC. +extern ADC_TypeDef *sl_device_peripheral_adc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for AES. +extern AES_TypeDef *sl_device_peripheral_aes_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for AMUXCP. +extern AMUXCP_TypeDef *sl_device_peripheral_amuxcp_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for BUFC. +extern BUFC_TypeDef *sl_device_peripheral_bufc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for BURAM. +extern BURAM_TypeDef *sl_device_peripheral_buram_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for BURTC. +extern BURTC_TypeDef *sl_device_peripheral_burtc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for CMU. +extern CMU_TypeDef *sl_device_peripheral_cmu_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for CRYPTOACC. +extern CRYPTOACC_TypeDef *sl_device_peripheral_cryptoacc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for CRYPTOACC_PKCTRL. +extern CRYPTOACC_PKCTRL_TypeDef *sl_device_peripheral_cryptoacc_pkctrl_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for CRYPTOACC_RNGCTRL. +extern CRYPTOACC_RNGCTRL_TypeDef *sl_device_peripheral_cryptoacc_rngctrl_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for DCDC. +extern DCDC_TypeDef *sl_device_peripheral_dcdc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for DEVINFO. +extern DEVINFO_TypeDef *sl_device_peripheral_devinfo_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for DPLL. +extern DPLL_TypeDef *sl_device_peripheral_dpll_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for EMU. +extern EMU_TypeDef *sl_device_peripheral_emu_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for EMU_CFGNS. +extern EMU_CFGNS_TypeDef *sl_device_peripheral_emu_cfgns_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for ETAMPDET. +extern ETAMPDET_TypeDef *sl_device_peripheral_etampdet_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for EUSART. +extern EUSART_TypeDef *sl_device_peripheral_eusart_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for FSRCO. +extern FSRCO_TypeDef *sl_device_peripheral_fsrco_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for GPCRC. +extern GPCRC_TypeDef *sl_device_peripheral_gpcrc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for GPIO. +extern GPIO_TypeDef *sl_device_peripheral_gpio_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for HFRCO. +extern HFRCO_TypeDef *sl_device_peripheral_hfrco_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for HFXO. +extern HFXO_TypeDef *sl_device_peripheral_hfxo_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for HOSTPORTAL. +extern HOSTPORTAL_TypeDef *sl_device_peripheral_hostportal_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for HYDRARAM. +extern HYDRARAM_TypeDef *sl_device_peripheral_hydraram_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for I2C. +extern I2C_TypeDef *sl_device_peripheral_i2c_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for IADC. +extern IADC_TypeDef *sl_device_peripheral_iadc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for ICACHE. +extern ICACHE_TypeDef *sl_device_peripheral_icache_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for KEYSCAN. +extern KEYSCAN_TypeDef *sl_device_peripheral_keyscan_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for L2CACHE. +extern L2CACHE_TypeDef *sl_device_peripheral_l2cache_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LCD. +extern LCD_TypeDef *sl_device_peripheral_lcd_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LCDRF. +extern LCDRF_TypeDef *sl_device_peripheral_lcdrf_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LDMA. +extern LDMA_TypeDef *sl_device_peripheral_ldma_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LDMAXBAR. +extern LDMAXBAR_TypeDef *sl_device_peripheral_ldmaxbar_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LEDDRV. +extern LEDDRV_TypeDef *sl_device_peripheral_leddrv_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LESENSE. +extern LESENSE_TypeDef *sl_device_peripheral_lesense_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LETIMER. +extern LETIMER_TypeDef *sl_device_peripheral_letimer_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LFRCO. +extern LFRCO_TypeDef *sl_device_peripheral_lfrco_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LFXO. +extern LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LPWAES. +extern LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LPW0PORTAL. +extern LPW0PORTAL_TypeDef *sl_device_peripheral_lpw0portal_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for LVGD. +extern LVGD_TypeDef *sl_device_peripheral_lvgd_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for MAILBOX. +extern MAILBOX_TypeDef *sl_device_peripheral_mailbox_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for MPAHBRAM. +extern MPAHBRAM_TypeDef *sl_device_peripheral_mpahbram_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for MSC. +extern MSC_TypeDef *sl_device_peripheral_msc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for MVP. +extern MVP_TypeDef *sl_device_peripheral_mvp_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for PCNT. +extern PCNT_TypeDef *sl_device_peripheral_pcnt_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for PDM. +extern PDM_TypeDef *sl_device_peripheral_pdm_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for PFMXPPRF. +extern PFMXPPRF_TypeDef *sl_device_peripheral_pfmxpprf_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for PIXELRZ. +extern PIXELRZ_TypeDef *sl_device_peripheral_pixelrz_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for PRS. +extern PRS_TypeDef *sl_device_peripheral_prs_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for RFFPLL. +extern RFFPLL_TypeDef *sl_device_peripheral_rffpll_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for RPA. +extern RPA_TypeDef *sl_device_peripheral_rpa_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for RTCC. +extern RTCC_TypeDef *sl_device_peripheral_rtcc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SCRATCHPAD. +extern SCRATCHPAD_TypeDef *sl_device_peripheral_scratchpad_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SEMAILBOX_AHBHOST. +extern SEMAILBOX_AHBHOST_TypeDef *sl_device_peripheral_semailbox_ahbhost_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SEMAILBOX_HOST. +extern SEMAILBOX_HOST_TypeDef *sl_device_peripheral_semailbox_host_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SEMAPHORE. +extern SEMAPHORE_TypeDef *sl_device_peripheral_semaphore_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SEPORTAL. +extern SEPORTAL_TypeDef *sl_device_peripheral_seportal_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SEPUF_APBCFG. +extern SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SMU. +extern SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SOCPLL. +extern SOCPLL_TypeDef *sl_device_peripheral_socpll_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SYMCRYPTO. +extern SYMCRYPTO_TypeDef *sl_device_peripheral_symcrypto_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SYSCFG. +extern SYSCFG_TypeDef *sl_device_peripheral_syscfg_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SYSCFG_CFGNS. +extern SYSCFG_CFGNS_TypeDef *sl_device_peripheral_syscfg_cfgns_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for SYSRTC. +extern SYSRTC_TypeDef *sl_device_peripheral_sysrtc_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for TIMER. +extern TIMER_TypeDef *sl_device_peripheral_timer_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for ULFRCO. +extern ULFRCO_TypeDef *sl_device_peripheral_ulfrco_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for USART. +extern USART_TypeDef *sl_device_peripheral_usart_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for USBAHB_AHBS. +extern USBAHB_AHBS_TypeDef *sl_device_peripheral_usbahb_ahbs_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for USBPLL. +extern USBPLL_TypeDef *sl_device_peripheral_usbpll_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for USB_APBS. +extern USB_APBS_TypeDef *sl_device_peripheral_usb_apbs_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for VDAC. +extern VDAC_TypeDef *sl_device_peripheral_vdac_get_base_addr(const sl_peripheral_t peripheral); + +// External base address getter declaration for WDOG. +extern WDOG_TypeDef *sl_device_peripheral_wdog_get_base_addr(const sl_peripheral_t peripheral); + +// External clock branch getter declaration. +extern sl_clock_branch_t sl_device_peripheral_get_clock_branch(const sl_peripheral_t peripheral); + +// External bus clock getter declaration. +extern sl_bus_clock_t sl_device_peripheral_get_bus_clock(const sl_peripheral_t peripheral); + +#if defined(__ICCARM__) +// Disable IAR multiple typedefs declaration warning. +#pragma diag_default=Pe301 +#endif diff --git a/Libs/platform/service/hfxo_manager/inc/sl_hfxo_manager.h b/Libs/platform/service/hfxo_manager/inc/sl_hfxo_manager.h new file mode 100644 index 0000000..b011f76 --- /dev/null +++ b/Libs/platform/service/hfxo_manager/inc/sl_hfxo_manager.h @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup hfxo_manager HFXO Manager + * @brief HFXO Manager + * @details + * ## Overview + * + * HFXO Manager is a platform service module intended to manage the High + * Frequency Crystal Oscillator (HFXO) module and offer related functionalities + * and services. + * For the moment, this module is only supported on Silicon Labs series 2 + * devices. + * Among others, it handles the HFXO startup failures. This is to support + * sleepy crystals (crystals where the ESR value could change unexpectedly up + * to 5 times its value during the startup). In case of a failure during the + * HFXO startup, the HFXO Manager will retry the startup process with more + * aggressive settings (sleepy crystal settings) to try waking up the crystal + * from its sleepy state so that the ESR value can fall back to normal values. + * Once the crystal is out of its sleepy state, the module will put back the + * normal settings ensuring the right oscillation frequency. This feature can + * be enabled/disabled via the configuration define + * SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT. + * The module catches startup failures through interrupts using the HFXO + * interrupt handler. If your application also needs the HFXO interrupt + * handler, the configuration define SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER + * can be used to remove the HFXO interrupt handler definition from the HFXO + * Manager so that it can be defined in your application. In that case, your + * definition of the HFXO Interrupt Handler will need to call the + * sl_hfxo_manager_irq_handler() function so that HFXO Manager can continue + * to work properly. + * The HFXO Manager is also required by the Power Manager module for some + * internal features and therefore becomes mandatory every time the Power + * Manager is present. + * + * + * ## Initialization + * + * Two functions are required to initialize the module. + * sl_hfxo_manager_init_hardware() is to initialize the HFXO interrupts and + * must therefore be called before any other HFXO initialization functions like + * the emlib CMU_HFXOInit() or device_init function sl_device_init_hfxo(). + * The second initialization function sl_hfxo_manager_init() is required for + * internal use and needs to be called before going to sleep. + * + * @{ + ******************************************************************************/ + +#ifndef SL_HFXO_MANAGER_H +#define SL_HFXO_MANAGER_H + +#include "sl_status.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @brief Sleepy Crystal settings +typedef struct sl_hfxo_manager_sleepy_xtal_settings { + uint32_t ana_ctune; ///< Tuning Capacitance values for XI and XO during startup intermediate and steady stages + uint32_t core_bias_current; ///< Core Bias current value during all stages +} sl_hfxo_manager_sleepy_xtal_settings_t; + +/***************************************************************************//** + * HFXO Manager module hardware specific initialization. + ******************************************************************************/ +void sl_hfxo_manager_init_hardware(void); + +/***************************************************************************//** + * Initialize HFXO Manager module. + * + * @return Status Code. + ******************************************************************************/ +sl_status_t sl_hfxo_manager_init(void); + +/***************************************************************************//** + * Updates Sleepy Crystal settings. + * + * @param settings Pointer to settings structure + * + * @return Status Code. + * + * @note Those settings are temporarily used to force oscillation on sleepy + * crystal. + * Default values should be enough to wake-up sleepy crystals. Otherwise, + * this function can be used. + ******************************************************************************/ +sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(const sl_hfxo_manager_sleepy_xtal_settings_t *settings); + +/***************************************************************************//** + * When this callback function is called, it means that HFXO failed twice in + * a row to start with normal configurations. This may mean that there is a + * bad crystal. When getting this callback, HFXO is running but its properties + * (frequency, precision) are not guaranteed. This should be considered as an + * error situation. + ******************************************************************************/ +void sl_hfxo_manager_notify_consecutive_failed_startups(void); + +/***************************************************************************//** + * HFXO Manager HFXO interrupt handler. + * + * @note This function must be called by the HFXO interrupt handler in order + * to support the HFXO Manager module. + * This function handles the HFXO_IF_RDY, HFXO_IF_DNSERR and + * HFXO_XTALCTRL_SKIPCOREBIASOPT interrupt flags. + ******************************************************************************/ +void sl_hfxo_manager_irq_handler(void); + +/** @} (end addtogroup hfxo_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_HFXO_MANAGER_H diff --git a/Libs/platform/service/hfxo_manager/inc/sli_hfxo_manager.h b/Libs/platform/service/hfxo_manager/inc/sli_hfxo_manager.h new file mode 100644 index 0000000..6da1114 --- /dev/null +++ b/Libs/platform/service/hfxo_manager/inc/sli_hfxo_manager.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_HFXO_MANAGER_H +#define SLI_HFXO_MANAGER_H + +#include +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_SLEEPTIMER_PRESENT) && defined(SYSRTC_PRESENT) +#include "sli_sleeptimer.h" +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) +#define HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * HFXO Manager module hardware specific initialization. + ******************************************************************************/ +void sli_hfxo_manager_init_hardware(void); + +/***************************************************************************//** + * Function to call just before starting HFXO, to save current tick count. + ******************************************************************************/ +void sli_hfxo_manager_begin_startup_measurement(void); + +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) +/***************************************************************************//** + * Function to call when a SYSRTC compare match event produces a PRS signal to + start HFXO. + ******************************************************************************/ +void sli_hfxo_manager_retrieve_begining_startup_measurement(void); +#endif + +/***************************************************************************//** + * Function to call just after HFXO becomes ready, to save current tick count + * and calculate HFXO startup time. + ******************************************************************************/ +void sli_hfxo_manager_end_startup_measurement(void); + +/***************************************************************************//** + * Retrieves HFXO startup time average value. + ******************************************************************************/ +uint32_t sli_hfxo_manager_get_startup_time(void); + +/***************************************************************************//** + * Retrieves HFXO startup time latest value. + ******************************************************************************/ +uint32_t sli_hfxo_manager_get_latest_startup_time(void); + +/***************************************************************************//** + * Checks if HFXO is ready and, if needed, waits for it to be. + * + * @param wait True, to wait for HFXO to be ready. + * False, otherwise. + * + * @return True, if HFXO is ready. + * False, otherwise. + * + * @note This will also make sure we are not in the process of restarting HFXO + * with different settings. + ******************************************************************************/ +bool sli_hfxo_manager_is_hfxo_ready(bool wait); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_HFXO_MANAGER_H */ diff --git a/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager.c b/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager.c new file mode 100644 index 0000000..f7fa043 --- /dev/null +++ b/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager.c @@ -0,0 +1,235 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#include "sl_hfxo_manager.h" +#include "sli_hfxo_manager.h" +#include "sli_hfxo_manager_internal.h" +#include "sl_sleeptimer.h" +#include "sl_assert.h" +#include "sl_status.h" +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ +// Table size of HFXO wake-up time measurement +#define HFXO_STARTUP_TIME_TABLE_SIZE 10 + +// Default time value in microseconds required to wake-up the hfxo oscillator. +#define HFXO_STARTUP_TIME_DEFAULT_VALUE_US (600u) + +/******************************************************************************* + ***************************** DATA TYPES ********************************** + ******************************************************************************/ + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Time in ticks required for HFXO start-up after wake-up from sleep. +static volatile uint32_t hfxo_startup_time_tick = 0; + +static volatile uint32_t hfxo_last_startup_time = 0; + +static uint32_t hfxo_startup_time_table[HFXO_STARTUP_TIME_TABLE_SIZE]; + +static uint8_t hfxo_startup_time_table_index = 0; + +static uint32_t hfxo_startup_time_sum_average = 0; + +static volatile uint32_t hfxo_startup_time_tc_initial = 0; + +static volatile bool hfxo_measurement_on = false; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * HFXO Manager module hardware specific initialization. + ******************************************************************************/ +void sl_hfxo_manager_init_hardware(void) +{ + sli_hfxo_manager_init_hardware(); +} + +/***************************************************************************//** + * Initialize HFXO Manager module. + ******************************************************************************/ +sl_status_t sl_hfxo_manager_init(void) +{ + sl_status_t status; + + // Initialize Sleeptimer module in case not already done. + status = sl_sleeptimer_init(); + if (status != SL_STATUS_OK) { + return status; + } +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + // Additional Sleeptimer HW configuration if SYSRTC is used + sli_sleeptimer_hal_hfxo_manager_integration_init(); +#endif + + // Set HFXO startup time to conservative default value + hfxo_startup_time_tick = (((HFXO_STARTUP_TIME_DEFAULT_VALUE_US * sl_sleeptimer_get_timer_frequency()) + (1000000 - 1)) / 1000000); + for (uint8_t i = 0; i < HFXO_STARTUP_TIME_TABLE_SIZE; i++) { + hfxo_startup_time_table[i] = hfxo_startup_time_tick; + hfxo_startup_time_sum_average += hfxo_startup_time_tick; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Updates Sleepy Crystal settings. + * + * @param settings Pointer to settings structure + * + * @return Status Code. + * + * @note Those settings are temporarily used to force oscillation on sleepy + * crystal. + * Default values should be enough to wake-up sleepy crystals. Otherwise, + * this function can be used. + ******************************************************************************/ +sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(const sl_hfxo_manager_sleepy_xtal_settings_t *settings) +{ + return sli_hfxo_manager_update_sleepy_xtal_settings_hardware(settings); +} + +/***************************************************************************//** + * When this callback function is called, it means that HFXO failed twice in + * a row to start with normal configurations. This may mean that there is a + * bad crystal. When getting this callback, HFXO is running but its properties + * (frequency, precision) are not guaranteed. This should be considered as an + * error situation. + ******************************************************************************/ +__WEAK void sl_hfxo_manager_notify_consecutive_failed_startups(void) +{ + EFM_ASSERT(false); +} + +/******************************************************************************* + ********************** GLOBAL INTERNAL FUNCTIONS ************************** + ******************************************************************************/ + +/***************************************************************************//** + * Function to call just before starting HFXO, to save current tick count. + ******************************************************************************/ +void sli_hfxo_manager_begin_startup_measurement(void) +{ + hfxo_measurement_on = true; + hfxo_startup_time_tc_initial = sl_sleeptimer_get_tick_count(); +} + +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) +/***************************************************************************//** + * Function to retrieve the capture channel value that was saved when + * HFXO became enabled. + * + * @note SYSRTC Capture channel is used to save when HFXO becomes enabled. + * The HFXO startup measurement will only be done based on the capture + * channel if the capture value is valid. + ******************************************************************************/ +void sli_hfxo_manager_retrieve_begining_startup_measurement(void) +{ + // ULFRCO does not have the precision to measure the HFXO startup time. + // So just return if ULFRCO is used as source oscillator. + if (sl_sleeptimer_get_timer_frequency() <= SystemULFRCOClockGet()) { + return; + } + + uint32_t startup_time = sli_sleeptimer_get_capture(); + + if (startup_time != 0) { + hfxo_startup_time_tc_initial = startup_time; + hfxo_measurement_on = true; + } +} +#endif + +/***************************************************************************//** + * Function to call just after HFXO becomes ready, to save current tick count + * and calculate HFXO startup time. + ******************************************************************************/ +void sli_hfxo_manager_end_startup_measurement(void) +{ + uint32_t default_startup_ticks; + + if (hfxo_measurement_on == false) { + return; + } + + hfxo_last_startup_time = sl_sleeptimer_get_tick_count() - hfxo_startup_time_tc_initial; + + // With low precision clock, the HFXO startup time measure could be zero. + // In that case, ensure it's a least 1 tick. + hfxo_last_startup_time = (hfxo_last_startup_time == 0) ? 1 : hfxo_last_startup_time; + + // Skip measurement if value is out of bound + default_startup_ticks = (((HFXO_STARTUP_TIME_DEFAULT_VALUE_US * sl_sleeptimer_get_timer_frequency()) + (1000000 - 1)) / 1000000); + EFM_ASSERT(hfxo_last_startup_time <= default_startup_ticks); + if (hfxo_last_startup_time > default_startup_ticks) { + hfxo_measurement_on = false; + return; + } + + // Calculate average for HFXO restore time + hfxo_startup_time_sum_average -= (int32_t)hfxo_startup_time_table[hfxo_startup_time_table_index] - (int32_t)hfxo_last_startup_time; + hfxo_startup_time_table[hfxo_startup_time_table_index] = hfxo_last_startup_time; + hfxo_startup_time_tick = ((hfxo_startup_time_sum_average + (HFXO_STARTUP_TIME_TABLE_SIZE - 1) ) / HFXO_STARTUP_TIME_TABLE_SIZE); + + // Update index of wakeup time table + hfxo_startup_time_table_index++; + hfxo_startup_time_table_index %= HFXO_STARTUP_TIME_TABLE_SIZE; + + hfxo_measurement_on = false; +} + +/***************************************************************************//** + * Retrieves HFXO startup time average value. + * + * @return HFXO startup time average value. + ******************************************************************************/ +uint32_t sli_hfxo_manager_get_startup_time(void) +{ + return hfxo_startup_time_tick; +} + +/***************************************************************************//** + * Retrieves HFXO startup time latest value. + * + * @return HFXO startup time latest value. + ******************************************************************************/ +uint32_t sli_hfxo_manager_get_latest_startup_time(void) +{ + return hfxo_last_startup_time; +} diff --git a/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c b/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c new file mode 100644 index 0000000..a97d01d --- /dev/null +++ b/Libs/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c @@ -0,0 +1,410 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager HAL series 2 Devices. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "sl_assert.h" +#include "sl_core.h" +#include "sli_hfxo_manager.h" +#include "sl_hfxo_manager.h" +#include "sl_hfxo_manager_config.h" +#include "sl_status.h" +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +#if (defined(SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT) \ + && (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) \ + && defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT)) +#error Component power_manager_deepsleep_blocking_hfxo_restore is not compatible with SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT configuration +#endif + +// Defines for hidden field FORCERAWCLK in HFXO_CTRL register +#define _HFXO_MANAGER_CTRL_FORCERAWCLK_SHIFT 31 +#define _HFXO_MANAGER_CTRL_FORCERAWCLK_MASK 0x80000000UL +#define HFXO_MANAGER_CTRL_FORCERAWCLK (0x1UL << _HFXO_MANAGER_CTRL_FORCERAWCLK_SHIFT) + +// Defines for hidden PKDETCTRL register +#define HFXO_MANAGER_PKDETCTRL (*((volatile uint32_t *)(HFXO0_BASE + 0x34UL))) +#define _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT 8 +#define _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK 0xF00UL +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V105MV (0x00000000UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V132MV (0x00000001UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V157MV (0x00000002UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V184MV (0x00000003UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V210MV (0x00000004UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V236MV (0x00000005UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V262MV (0x00000006UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V289MV (0x00000007UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V315MV (0x00000008UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V341MV (0x00000009UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V367MV (0x0000000AUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V394MV (0x0000000BUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V420MV (0x0000000CUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V446MV (0x0000000DUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V472MV (0x0000000EUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) +#define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V499MV (0x0000000FUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT) + +// IRQ Name depending on devices +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define HFXO_IRQ_NUMBER HFXO00_IRQn +#define HFXO_IRQ_HANDLER_FUNCTION HFXO00_IRQHandler +#else +#define HFXO_IRQ_NUMBER HFXO0_IRQn +#define HFXO_IRQ_HANDLER_FUNCTION HFXO0_IRQHandler +#endif + +// Default values for the Sleepy Crystal settings +// Should be enough to guaranty HFXO startup +#define SLEEPY_XTAL_SETTING_DEFAULT_PKDETTHSTARTUPI HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V157MV +#define SLEEPY_XTAL_SETTING_DEFAULT_CTUNEANA 100u +#define SLEEPY_XTAL_SETTING_DEFAULT_COREBIAS 255u + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Error flag to indicate if we failed the startup process +static volatile bool error_flag = false; + +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) +// Error retry counter +static volatile uint8_t error_try_cnt = 0; + +// Error State status +static volatile bool in_error_state = false; + +// Variables to save normal settings +static uint32_t pkdettusstartupi_saved; +static uint32_t ctunexiana_saved; +static uint32_t ctunexoana_saved; +static uint32_t corebiasana_saved; +static uint32_t corebiasstartup_saved; +static uint32_t corebiasstartupi_saved; + +// Variables for Sleepy Crystal settings +static uint32_t sleepy_xtal_settings_pkdettusstartupi = SLEEPY_XTAL_SETTING_DEFAULT_PKDETTHSTARTUPI; // Value already shifted +static uint32_t sleepy_xtal_settings_ctuneana = SLEEPY_XTAL_SETTING_DEFAULT_CTUNEANA; +static uint32_t sleepy_xtal_settings_corebias = SLEEPY_XTAL_SETTING_DEFAULT_COREBIAS; +#endif + +/***************************************************************************//** + * HFXO ready notification callback for internal use with power manager + ******************************************************************************/ +__WEAK void sli_hfxo_manager_notify_ready_for_power_manager(void); + +/***************************************************************************//** + * HFXO PRS ready notification callback for internal use with power manager + ******************************************************************************/ +__WEAK void sli_hfxo_notify_ready_for_power_manager_from_prs(void); + +/***************************************************************************//** + * Hardware specific initialization. + ******************************************************************************/ +void sli_hfxo_manager_init_hardware(void) +{ + // Increase HFXO Interrupt priority so that it won't be masked by BASEPRI + // and will preempt other interrupts. + NVIC_SetPriority(HFXO_IRQ_NUMBER, CORE_ATOMIC_BASE_PRIORITY_LEVEL - 1); + + // Enable HFXO Interrupt if HFXO is used +#if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2 + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + + HFXO0->IEN_CLR = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR; +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + HFXO0->IEN_CLR = HFXO_IEN_PRSRDY; +#endif + + HFXO0->IF_CLR = HFXO_IF_RDY | HFXO_IF_DNSERR | HFXO_IEN_COREBIASOPTERR; +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + HFXO0->IF_CLR = HFXO_IF_PRSRDY; +#endif + + NVIC_ClearPendingIRQ(HFXO_IRQ_NUMBER); + NVIC_EnableIRQ(HFXO_IRQ_NUMBER); + + HFXO0->IEN_SET = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR; + +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + HFXO0->IEN_SET = HFXO_IEN_PRSRDY; + HFXO0->CTRL &= ~(_HFXO_CTRL_DISONDEMANDPRS_MASK & HFXO_CTRL_DISONDEMANDPRS_DEFAULT); + HFXO0->CTRL |= HFXO_CTRL_PRSSTATUSSEL1_ENS; +#endif +} + +/***************************************************************************//** + * Updates sleepy crystal settings in specific hardware registers. + ******************************************************************************/ +sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(const sl_hfxo_manager_sleepy_xtal_settings_t *settings) +{ +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) + EFM_ASSERT(settings->ana_ctune <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)); + EFM_ASSERT(settings->core_bias_current <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); + + sleepy_xtal_settings_ctuneana = settings->ana_ctune; + sleepy_xtal_settings_corebias = settings->core_bias_current; + + return SL_STATUS_OK; +#else + (void)settings; + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +/***************************************************************************//** + * Checks if HFXO is ready and, if needed, waits for it to be. + * + * @note This will also make sure we are not in the process of restarting HFXO + * with different settings. + ******************************************************************************/ +bool sli_hfxo_manager_is_hfxo_ready(bool wait) +{ + bool ready = false; + + do { +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + ready = (((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_PRSRDY)) != 0) && !error_flag) ? true : false; +#else + ready = (((HFXO0->STATUS & HFXO_STATUS_RDY) != 0) && !error_flag) ? true : false; +#endif + } while (!ready && wait); + + return ready; +} + +#if (SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER == 0) +/******************************************************************************* + * HFXO interrupt handler. + * + * @note The HFXOx_IRQHandler provided by HFXO Manager will call + * @ref sl_hfxo_manager_irq_handler. Configure SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER + * if the application wants to implement its own HFXOx_IRQHandler. + ******************************************************************************/ +void HFXO_IRQ_HANDLER_FUNCTION(void) +{ + sl_hfxo_manager_irq_handler(); +} +#endif + +/******************************************************************************* + * HFXO Manager HFXO interrupt handler. + ******************************************************************************/ +void sl_hfxo_manager_irq_handler(void) +{ + uint32_t irq_flag = HFXO0->IF; +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) + bool disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) ? true : false; + bool forceen = (HFXO0->CTRL & _HFXO_CTRL_FORCEEN_MASK) ? true : false; +#endif + +#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON) + if (irq_flag & HFXO_IF_PRSRDY) { + // Clear PRS RDY flag and EM23ONDEMAND + HFXO0->IF_CLR = irq_flag & HFXO_IF_PRSRDY; + HFXO0->CTRL_CLR = HFXO_CTRL_EM23ONDEMAND; + + // Only retrieve start of measurement if HFXO is not already ready. + if ((HFXO0->STATUS & HFXO_STATUS_RDY) == 0) { + sli_hfxo_manager_retrieve_begining_startup_measurement(); + } + + // Notify power manager HFXO is ready + sli_hfxo_notify_ready_for_power_manager_from_prs(); + sli_hfxo_manager_notify_ready_for_power_manager(); + + // Update sleep on isr exit flag + sli_sleeptimer_update_sleep_on_isr_exit(true); + + // Reset PRS signal through Sleeptimer + sli_sleeptimer_reset_prs_signal(); + } +#endif + + // RDY Interrupt Flag Handling + if (irq_flag & HFXO_IF_RDY) { + // Clear Ready flag + HFXO0->IF_CLR = irq_flag & HFXO_IF_RDY; + +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) + if (error_flag) { + // Clear error flag, i.e. we successfully stated HFXO with the modified settings + error_flag = false; + + // If it's the first time we succeed after an error, try back the normal settings + if (error_try_cnt <= 1) { + // Disable HFXO. + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + + while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) { + } + + // Put back normal settings + HFXO_MANAGER_PKDETCTRL = (HFXO_MANAGER_PKDETCTRL & ~_HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK) | pkdettusstartupi_saved; + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXIANA_MASK | _HFXO_XTALCTRL_CTUNEXOANA_MASK)) + | ctunexiana_saved + | ctunexoana_saved; + HFXO0->XTALCFG = (HFXO0->XTALCFG & ~(_HFXO_XTALCFG_COREBIASSTARTUPI_MASK | _HFXO_XTALCFG_COREBIASSTARTUP_MASK)) + | corebiasstartup_saved + | corebiasstartupi_saved; + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) | corebiasana_saved; + + // Put back FORCEEN and DISONDEMAND state + if (!disondemand) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } else { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } + if (forceen) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } else { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + } + } else { + // Call notification function to tell users that sleepy crystal settings are kept + // This should only happen if you are in test condition or if you have a bad crystal. + sl_hfxo_manager_notify_consecutive_failed_startups(); + in_error_state = true; + } + } else { + sli_hfxo_manager_end_startup_measurement(); + + sli_hfxo_manager_notify_ready_for_power_manager(); + + // Clear counter since we successfully started HFXO with normal settings + // or we are just keeping sleepy crystal settings indefinitely. + error_try_cnt = 0; + } +#else + sli_hfxo_manager_end_startup_measurement(); + + sli_hfxo_manager_notify_ready_for_power_manager(); +#endif + } + + // DNSERR Interrupt Flag Handling + if (irq_flag & HFXO_IF_DNSERR) { + // Clear error flag + HFXO0->IF_CLR = irq_flag & HFXO_IF_DNSERR; + +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) + // We should not fail twice in a row + EFM_ASSERT(error_flag == false); + + // Update global variables related to error. + error_flag = true; + error_try_cnt++; + + // Save current settings + pkdettusstartupi_saved = (HFXO_MANAGER_PKDETCTRL & _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK); + ctunexiana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK); + ctunexoana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXOANA_MASK); + corebiasana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK); + corebiasstartup_saved = (HFXO0->XTALCFG & _HFXO_XTALCFG_COREBIASSTARTUP_MASK); + corebiasstartupi_saved = (HFXO0->XTALCFG & _HFXO_XTALCFG_COREBIASSTARTUPI_MASK); + + // Disable HFXO. + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + + // Use FORCERAWCLK bit to exit error state when disabling + HFXO0->CTRL_SET = HFXO_MANAGER_CTRL_FORCERAWCLK; + while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { + } + HFXO0->CTRL_CLR = HFXO_MANAGER_CTRL_FORCERAWCLK; + + // Change settings: + //Reduce Peak Detection Threshold for Startup Intermediate stage to 2 (V157MV) + HFXO_MANAGER_PKDETCTRL = (HFXO_MANAGER_PKDETCTRL & ~_HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK) | sleepy_xtal_settings_pkdettusstartupi; + // Reduce CTUNE values for steady stage + if (((ctunexiana_saved >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) > 100) + || ((ctunexoana_saved >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) > 100)) { + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXIANA_MASK | _HFXO_XTALCTRL_CTUNEXOANA_MASK)) + | (sleepy_xtal_settings_ctuneana << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) + | (sleepy_xtal_settings_ctuneana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); + } + // Increase core bias current at all stages + HFXO0->XTALCFG = (HFXO0->XTALCFG & ~(_HFXO_XTALCFG_COREBIASSTARTUPI_MASK | _HFXO_XTALCFG_COREBIASSTARTUP_MASK)) + | ((sleepy_xtal_settings_corebias >> 2) << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT) + | ((sleepy_xtal_settings_corebias >> 2) << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT); + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) + | (sleepy_xtal_settings_corebias << _HFXO_XTALCTRL_COREBIASANA_SHIFT); + + // Put back FORCEEN and DISONDEMAND state + if (!disondemand) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } else { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } + if (forceen) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } else { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + } +#endif + } + + if (irq_flag & HFXO_IF_COREBIASOPTERR) { + // Clear Core Bias Optimization error flag + HFXO0->IF_CLR = irq_flag & HFXO_IF_COREBIASOPTERR; + +#if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) + // In case the Core Bias Optimization fails during error handling, + // we disable it + if (in_error_state == true) { + // Disable HFXO. + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + + while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) { + } + + // Skip Core Bias Optimization in case of error + HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; + + // Put back FORCEEN and DISONDEMAND state + if (!disondemand) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } else { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } + if (forceen) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } else { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + } + } +#endif + } +} +#endif // _SILICON_LABS_32B_SERIES_2 diff --git a/Libs/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h b/Libs/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h new file mode 100644 index 0000000..3989462 --- /dev/null +++ b/Libs/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h @@ -0,0 +1,50 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager Internal API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_HFXO_MANAGER_INTERNAL_H +#define SLI_HFXO_MANAGER_INTERNAL_H + +#include "sl_hfxo_manager.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Updates sleepy crystal settings in specific hardware registers. + ******************************************************************************/ +sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(const sl_hfxo_manager_sleepy_xtal_settings_t *settings); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_HFXO_MANAGER_INTERNAL_H */ diff --git a/Libs/platform/service/interrupt_manager/inc/arm/cmsis_nvic_virtual.h b/Libs/platform/service/interrupt_manager/inc/arm/cmsis_nvic_virtual.h new file mode 100644 index 0000000..d04dee2 --- /dev/null +++ b/Libs/platform/service/interrupt_manager/inc/arm/cmsis_nvic_virtual.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file + * @brief CMSIS NVIC Virtual Header + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef CMSIS_NVIC_VIRTUAL_H +#define CMSIS_NVIC_VIRTUAL_H + +#include "sl_interrupt_manager.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// NVIC backward compatibility layer +#define NVIC_EnableIRQ(irqn) sl_interrupt_manager_enable_irq(irqn) +#define NVIC_DisableIRQ(irqn) sl_interrupt_manager_disable_irq(irqn) +#define NVIC_SetPriority sl_interrupt_manager_set_irq_priority +#define NVIC_GetPriority sl_interrupt_manager_get_irq_priority +#define NVIC_SystemReset sl_interrupt_manager_reset_system +#define NVIC_GetPendingIRQ(irqn) sl_interrupt_manager_is_irq_pending(irqn) +#define NVIC_SetPendingIRQ(irqn) sl_interrupt_manager_set_irq_pending(irqn) +#define NVIC_ClearPendingIRQ(irqn) sl_interrupt_manager_clear_irq_pending(irqn) +#define NVIC_GetActive(irqn) sl_interrupt_manager_get_active_irq(irqn) + +// Original NVIC calls +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_CMSIS_NVIC_VIRTUAL_H */ diff --git a/Libs/platform/service/interrupt_manager/inc/sl_interrupt_manager.h b/Libs/platform/service/interrupt_manager/inc/sl_interrupt_manager.h new file mode 100644 index 0000000..d297923 --- /dev/null +++ b/Libs/platform/service/interrupt_manager/inc/sl_interrupt_manager.h @@ -0,0 +1,404 @@ +/***************************************************************************//** + * @file + * @brief Interrupt Management API to enable and configure interrupts. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_INTERRUPT_MANAGER_H +#define SL_INTERRUPT_MANAGER_H + +#include +#include +#include "sl_core.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup interrupt_manager Interrupt Manager + * @brief Interrupt management service can be used for general interrupt management. + * The source files for Interrupt Manager platform software module are present under + * platform/services/interrupt_manager. + * @details + * ## Overview + * The Interrupt Manager is a service that offers interupt management functions and configurations + * for setting the interrupt vector in RAM, managing the core reset initiation function and + * doing general interrupt management operations. + * + * ## Configuration Options + * + * Some properties of the Interrupt Manager are compile-time configurable. These + * properties are set in the sl_interrupt_manager_s2_config.h file. + * These are the available configuration parameters with default values defined. + * @code + * + * // Put the interrupt vector table in RAM. + * // Set to 1 to put the vector table in RAM. + * // Default: 0 + * #define SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM 0 + * @endcode + * + * @note The SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM configuration is only available + * on series 2. Enabling the S2_INTERRUPTS_IN_RAM configuration will tell the Interrupt Manager + * to copy the interrupt vector table from ROM to RAM and select it as the interrupt table. + * On newer series this feature is always enabled. + * + * ## The API + * + * This section contains brief descriptions of the functions in the API. For more + * information on input and output parameters and return values, + * click on the hyperlinked function names. + * + * @ref sl_interrupt_manager_disable_interrupts and @ref sl_interrupt_manager_enable_interrupts() + * are used to prevent interrupts from executing during a certain timelapse. + * + * @ref sl_interrupt_manager_is_irq_disabled, @ref sl_interrupt_manager_is_irq_blocked + * are used to know the status of an interrupt, either if it's disabled or blocked by one of the + * following reasons: priority masking, disabling or an active interrupt of higher priority + * is executing. + * + * @ref sl_interrupt_manager_is_irq_pending, @ref sl_interrupt_manager_set_irq_pending and + * @ref sl_interrupt_manager_clear_irq_pending + * are used for control and query of external interrupt source pending status. + * + * @ref sl_interrupt_manager_get_irq_priority and @ref sl_interrupt_manager_set_irq_priority + * are used to get or set the priority for a specific interrupt. + * + * ## Priority Stratification + * With the Interrupt Manager service and more generally in the Simplicity SDK, there are multiple distinct + * levels of priority stratification. + * + * Each of these has their own characteristics and purposes. + * For example, the higher priority group is considered to not be able to call kernel, power manager + * or protocol stacks functions. They will only be impacted by critical sections (general interrupt + * disable) but will be above atomic base interrupt priority level for execution. The higher level + * is considered to be between 0 and 2 and the base interrupt priority level is 3. + * + * In the normal priority group you will find most application interrupts and such interrupts will be + * the ones that will make calls to more features such as kernel, power manager and protocol stacks API. + * It is this way because they are less deterministic than the "higher priority interrupts". + * + * + * + *
    Priority stratification inside SDK
    PriorityPurpose + *
    0 - 2 (Highest) + *
      + *
    • No Kernel calls + *
    • No Power Manager calls + *
    • Not maskable by atomic sections + *
    + *
    3 - 7 (Normal) + *
      + *
    • kernel calls + *
    • power manager + *
    • protocol stacks API + *
    + *
    7 (Lowest) + *
      + *
    • PendSV level of priority + *
    + *
    + * @{ + ******************************************************************************/ + +/// @brief sl_interrupt_manager interrupt handler function. +typedef void(*sl_interrupt_manager_irq_handler_t)(void); + +/***************************************************************************//** + * @brief + * Initialize interrupt controller hardware and initialise vector table + * in RAM. + * + * @note + * The interrupt manager init function will perform the initialization only + * once even if it's called multiple times. + ******************************************************************************/ +void sl_interrupt_manager_init(void); + +/***************************************************************************//** + * @brief + * Reset the cpu core. + ******************************************************************************/ +void sl_interrupt_manager_reset_system(void); + +/***************************************************************************//** + * @brief + * Disable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_disable_interrupts(void); + +/***************************************************************************//** + * @brief + * Enable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_enable_interrupts(void); + +/***************************************************************************//** + * @brief + * Disable interrupt for an interrupt source. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_disable_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Enable interrupt for an interrupt source. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_enable_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Check if an interrupt is disabled. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * True if the interrupt is disabled. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_disabled(int32_t irqn); + +/***************************************************************************//** + * @brief + * Check if a specific interrupt is blocked. + * + * @note + * The function return true if the IRQ is disabled. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * True if the interrupt is disabled or blocked. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_blocked(int32_t irqn); + +/***************************************************************************//** + * @brief + * Get Pending Interrupt + * + * @note + * Read the pending status of a specified interrupt and returns it status. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * false Interrupt status is not pending. + * true Interrupt status is pending. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_pending(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set interrupt status to pending. + * + * @note + * Sets an interrupt pending status to true. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_pending(int32_t irqn); + +/***************************************************************************//** +* @brief +* Clear Pending Interrupt +* +* @details +* Clear an interrupt pending status +* +* @param[in] irqn +* The interrupt number of the interrupt source. +* +* @note +* irqn must not be negative. +*******************************************************************************/ +void sl_interrupt_manager_clear_irq_pending(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set the interrupt handler of an interrupt source. + * + * @note + * This function depends on a RAM based interrupt vector table, i.e. + * SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM must be true. Or the device + * must be Series 3. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @param[in] handler + * The new interrupt handler for the interrupt source. + * + * @return + * The prior interrupt handler for the interrupt source. + ******************************************************************************/ +sl_status_t sl_interrupt_manager_set_irq_handler(int32_t irqn, + sl_interrupt_manager_irq_handler_t handler); + +/***************************************************************************//** + * @brief + * Get the interrupt preemption priority of an interrupt source. + * + * @note + * The number of priority levels is platform dependent. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * The interrupt priority for the interrupt source. + * Value 0 denotes the highest priority. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_irq_priority(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set the interrupt preemption priority of an interrupt source. + * + * @note + * The number of priority levels is platform dependent. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @param[in] priority + * The new interrupt priority for the interrupt source. + * Value 0 denotes the highest priority. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_priority(int32_t irqn, uint32_t priority); + +/***************************************************************************//** + * @brief + * Increase the interrupt preemption priority of an interrupt source. + * relative to the default priority. + * + * @details + * This function is useful to be architecture agnostic with priority values. + * + * Usage: + * new_prio = sl_interrupt_manager_increase_irq_priority_from_default(IRQn, 1); + * + * This will increase the priority of IRQn by 1. + * + * @param[in] irqn + * The irq to change the priority. + * + * @param[in] diff + * The relative difference. + ******************************************************************************/ +void sl_interrupt_manager_increase_irq_priority_from_default(int32_t irqn, uint32_t diff); + +/***************************************************************************//** + * @brief + * Decrease the interrupt preemption priority of an interrupt source + * relative to the default priority. + * + * @details + * This function is useful to be architecture agnostic with priority values. + * + * Usage: + * new_prio = sl_interrupt_manager_decrease_irq_priority_from_default(IRQn, 1); + * + * This will decrease the priority of IRQn by 1. + * + * @param[in] irqn + * The irq to change the priority. + * + * @param[in] diff + * The relative difference. + ******************************************************************************/ +void sl_interrupt_manager_decrease_irq_priority_from_default(int32_t irqn, uint32_t diff); + +/***************************************************************************//** + * @brief + * Get the default interrupt preemption priority value. + * + * @return + * The default priority. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_default_priority(void); + +/***************************************************************************//** + * @brief + * Get the highest interrupt preemption priority value. + * + * @return + * The highest priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_highest_priority(void); + +/***************************************************************************//** + * @brief + * Get the lowest interrupt preemption priority value. + * + * @return + * The lowest priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_lowest_priority(void); + +/***************************************************************************//** + * @brief + * Get the interrupt active status. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * The interrupt active status. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_active_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Get the current ISR table. + * + * @details + * Depending on the configuration of the Interrupt Manager, this table of + * ISRs may be in RAM or in FLASH, and each ISR may or may not be wrapped by + * enter/exit hooks. + * + * @return + * The current ISR table. + ******************************************************************************/ +sl_interrupt_manager_irq_handler_t* sl_interrupt_manager_get_isr_table(void); + +/** @} (end addtogroup interrupt_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_INTERRUPT_MANAGER_H */ diff --git a/Libs/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c b/Libs/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c new file mode 100644 index 0000000..cfeb5c4 --- /dev/null +++ b/Libs/platform/service/interrupt_manager/src/sl_interrupt_manager_cortexm.c @@ -0,0 +1,601 @@ +/***************************************************************************//** + * @file + * @brief Interrupt manager API to enable disable interrupts. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_interrupt_manager.h" +#include "sl_core.h" +#include "sl_assert.h" +#include "em_device.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include +#endif + +#if defined(SL_CATALOG_CODE_CLASSIFICATION_VALIDATOR_PRESENT) +#include "sli_code_classification_validator.h" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "sl_interrupt_manager_s2_config.h" +#endif + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ +#define CORTEX_INTERRUPTS (16) +#define TOTAL_INTERRUPTS (CORTEX_INTERRUPTS + EXT_IRQ_COUNT) + +#define LOWEST_NVIC_PRIORITY ((1U << __NVIC_PRIO_BITS) - 1U) +#define SL_INTERRUPT_MANAGER_DEFAULT_PRIORITY 5U + +// Use same alignement as IAR +#define VECTOR_TABLE_ALIGNMENT (512) + +// Interrupt vector placement is in RAM +#if (defined(SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM) \ + && (SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM == 1)) \ + || defined(SL_CATALOG_INTERRUPT_MANAGER_VECTOR_TABLE_IN_RAM_PRESENT) +#define VECTOR_TABLE_IN_RAM (1) +#endif + +#if defined(SL_CATALOG_INTERRUPT_MANAGER_HOOKS_PRESENT) +#define SL_INTERRUPT_MANAGER_ENABLE_HOOKS (1) +#endif + +// Interrupt vector table need to be in a different section of RAM for Cortex-M55. +#if defined(__CM55_REV) +#define RAM_BASE SRAM_BASE // ITCM_RAM_BASE +#define RAM_SIZE SRAM_SIZE // ITCM_RAM_SIZE +#if defined(__GNUC__) +#define VECTOR_TABLE_SECTION __attribute__((section(".vector_table_ram"))) +#else +#define VECTOR_TABLE_SECTION _Pragma("location =\".vector_table_ram\"") +#endif +#else +#define RAM_BASE SRAM_BASE +#define RAM_SIZE SRAM_SIZE +#define VECTOR_TABLE_SECTION +#endif + +#if defined(VECTOR_TABLE_IN_RAM) + +#if defined(__GNUC__) +// Create a vector table in RAM aligned to 512. +static sl_interrupt_manager_irq_handler_t vector_table_ram[TOTAL_INTERRUPTS] __attribute__((aligned(VECTOR_TABLE_ALIGNMENT) )) VECTOR_TABLE_SECTION; +#elif defined(__ICCARM__) +#pragma data_alignment = VECTOR_TABLE_ALIGNMENT +static sl_interrupt_manager_irq_handler_t vector_table_ram[TOTAL_INTERRUPTS] VECTOR_TABLE_SECTION; +#endif /* defined(__GNUC__) */ + +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) +// When interrupt manager hooks are enabled, the actual vector table (either in +// ram or in flash) will call an ISR wrapper. The actual ISRs will be registered +// and called from the wrapped_vector_table. +#if defined(__GNUC__) +static sl_interrupt_manager_irq_handler_t wrapped_vector_table[TOTAL_INTERRUPTS] __attribute__((aligned(VECTOR_TABLE_ALIGNMENT) )) VECTOR_TABLE_SECTION; +#elif defined(__ICCARM__) +#pragma data_alignment = VECTOR_TABLE_ALIGNMENT +static sl_interrupt_manager_irq_handler_t wrapped_vector_table[TOTAL_INTERRUPTS] VECTOR_TABLE_SECTION; +#endif /* defined(__GNUC__) */ +#endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ + +#endif /* VECTOR_TABLE_IN_RAM */ + +/******************************************************************************* + ***************************** PROTOTYPES *********************************** + ******************************************************************************/ +static void enable_interrupt(int32_t irqn); +static void disable_interrupt(int32_t irqn); +static void set_priority(int32_t irqn, uint32_t priority); +static uint32_t get_priority(int32_t irqn); + +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) +#if defined(SL_CATALOG_CODE_CLASSIFICATION_VALIDATOR_PRESENT) +CCV_SECTION +#endif +static void sli_interrupt_manager_isr_wrapper(void); +#endif /* SL_INTERRUPT_MANAGER_HOOKS */ + +/******************************************************************************* + ***************************** VARIABLES *********************************** + ******************************************************************************/ + +// Initialization flag. +static bool is_interrupt_manager_initialized = false; + +/******************************************************************************* + ***************************** FUNCTIONS *********************************** + ******************************************************************************/ + +#if defined(VECTOR_TABLE_IN_RAM) +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) + +__WEAK void sl_interrupt_manager_irq_enter_hook(void) +{ + return; +} + +__WEAK void sl_interrupt_manager_irq_exit_hook(void) +{ + return; +} + +static void sli_interrupt_manager_isr_wrapper(void) +{ + uint32_t irqn = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); + sl_interrupt_manager_irq_enter_hook(); + wrapped_vector_table[irqn](); + sl_interrupt_manager_irq_exit_hook(); +} + +#endif /* SL_INTERRUPT_MANAGER_HOOKS */ + +/***************************************************************************//** + * @brief + * Set a new RAM based interrupt vector table. + ******************************************************************************/ +sl_interrupt_manager_irq_handler_t *sli_interrupt_manager_set_irq_table(sl_interrupt_manager_irq_handler_t *table, + uint32_t handler_count) +{ + sl_interrupt_manager_irq_handler_t * current; + + EFM_ASSERT(((uint32_t)table >= RAM_BASE) && (uint32_t)table < (RAM_BASE + RAM_SIZE)); + + // ASSERT if misaligned with respect to the VTOR register implementation. + EFM_ASSERT(((uint32_t)table & ~SCB_VTOR_TBLOFF_Msk) == 0U); + + // ASSERT if misaligned with respect to the vector table size. + // The vector table address must be aligned at its size rounded up to nearest 2^n. + EFM_ASSERT(((uint32_t)table + & ((1UL << (32UL - __CLZ((handler_count * 4UL) - 1UL))) - 1UL)) + == 0UL); + + // Disable all interrupts while updating the vector table + sl_interrupt_manager_disable_interrupts(); + + current = (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; + + SCB->VTOR = (uint32_t)table; + + // Make sure all explicit memory access are complete before proceding. + __DSB(); + + sl_interrupt_manager_enable_interrupts(); + + return current; +} + +#endif /* VECTOR_TABLE_IN_RAM */ + +/***************************************************************************//** + * @brief + * Initialize interrupt controller hardware and initialise vector table in RAM. + * + * @note + * The interrupt manager init function will perform the initialization only + * once even if it's called multiple times. + ******************************************************************************/ +void sl_interrupt_manager_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + if (!is_interrupt_manager_initialized) { + is_interrupt_manager_initialized = true; + CORE_EXIT_ATOMIC(); + } else { + CORE_EXIT_ATOMIC(); + return; + } + + #if defined(VECTOR_TABLE_IN_RAM) + + sl_interrupt_manager_irq_handler_t* current; + + CORE_ENTER_CRITICAL(); + + current = (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; + + // copy ROM vector table to RAM table + for (uint32_t i = 0; i < TOTAL_INTERRUPTS; i++) { + #if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) + wrapped_vector_table[i] = current[i]; + if ( i >= CORTEX_INTERRUPTS ) { + vector_table_ram[i] = sli_interrupt_manager_isr_wrapper; + } else { + vector_table_ram[i] = current[i]; + } + #else + vector_table_ram[i] = current[i]; + #endif + } + + // Set RAM table as irq table. + sli_interrupt_manager_set_irq_table(vector_table_ram, TOTAL_INTERRUPTS); + + CORE_EXIT_CRITICAL(); + + #endif /* VECTOR_TABLE_IN_RAM */ + + for (IRQn_Type i = SVCall_IRQn; i < EXT_IRQ_COUNT; i++) { + sl_interrupt_manager_set_irq_priority(i, SL_INTERRUPT_MANAGER_DEFAULT_PRIORITY); + } +} + +/***************************************************************************//** + * @brief + * Reset the cpu core. + ******************************************************************************/ +void sl_interrupt_manager_reset_system(void) +{ + CORE_RESET_SYSTEM(); +} + +/***************************************************************************//** + * @brief + * Disable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_disable_interrupts(void) +{ + __disable_irq(); +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_enable_interrupts(void) +{ + __enable_irq(); +} + +/***************************************************************************//** + * @brief + * Disable interrupt for an interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_disable_irq(int32_t irqn) +{ + EFM_ASSERT((irqn >= 0) && (irqn <= EXT_IRQ_COUNT)); + + disable_interrupt(irqn); +} + +/***************************************************************************//** + * @brief + * Enable interrupt for an interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_enable_irq(int32_t irqn) +{ + EFM_ASSERT((irqn >= 0) && (irqn <= EXT_IRQ_COUNT)); + + enable_interrupt(irqn); +} + +/***************************************************************************//** + * @brief + * Check if an interrupt is disabled. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_disabled(int32_t irqn) +{ + EFM_ASSERT((irqn >= 0) && (irqn < EXT_IRQ_COUNT)); + + return (NVIC->ISER[irqn >> 5U] & (1UL << (irqn & 0x1FUL))) == 0UL; +} + +/***************************************************************************//** + * @brief + * Check if an interrupt is disabled or blocked. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_blocked(int32_t irqn) +{ + uint32_t irq_priority, active_irq; + +#if (__CORTEX_M >= 3) + uint32_t basepri; + + EFM_ASSERT((irqn >= MemoryManagement_IRQn) + && (irqn < (IRQn_Type)EXT_IRQ_COUNT)); +#else + EFM_ASSERT((irqn >= SVCall_IRQn) && ((IRQn_Type)irqn < EXT_IRQ_COUNT)); +#endif + + if ((__get_PRIMASK() & 1U) != 0U) { + return true; + } + + if (sl_interrupt_manager_is_irq_disabled(irqn)) { + return true; + } + + irq_priority = get_priority(irqn); + +#if (__CORTEX_M >= 3) + basepri = __get_BASEPRI(); + + if ((basepri != 0U) + && (irq_priority >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { + return true; + } +#endif + + active_irq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; + + if (active_irq != 0U) { + if (irq_priority >= get_priority(active_irq - 16U)) { + return true; + } + } + + return false; +} + +/***************************************************************************//** + * @brief + * Get Pending Interrupt. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_pending(int32_t irqn) +{ + if (irqn >= 0) { + return (NVIC->ISPR[(((uint32_t)irqn) >> 5UL)] & (1UL << (((uint32_t)irqn) & 0x1FUL))) != 0UL; + } else { + return false; + } +} + +/***************************************************************************//** + * @brief + * Set irq status to pending. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_pending(int32_t irqn) +{ + if (irqn >= 0) { + NVIC->ISPR[(((uint32_t)irqn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)irqn) & 0x1FUL)); + } +} + +/***************************************************************************//** + * @brief + * Clear Pending Interrupt. + ******************************************************************************/ +void sl_interrupt_manager_clear_irq_pending(int32_t irqn) +{ + if (irqn >= 0) { + NVIC->ICPR[(((uint32_t)irqn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)irqn) & 0x1FUL)); + } +} + +/***************************************************************************//** + * @brief + * Set the interrupt handler of an interrupt source. + ******************************************************************************/ +sl_status_t sl_interrupt_manager_set_irq_handler(int32_t irqn, + sl_interrupt_manager_irq_handler_t handler) +{ +#if defined(VECTOR_TABLE_IN_RAM) + + uint32_t interrupt_status; + sl_interrupt_manager_irq_handler_t *table; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + if ((irqn < 0) || (irqn >= EXT_IRQ_COUNT)) { + return SL_STATUS_INVALID_PARAMETER; + } + + interrupt_status = (uint32_t)(((NVIC->ISER[(((uint32_t)irqn) >> 5UL)] & (1UL << (((uint32_t)irqn) & 0x1FUL))) != 0UL) ? 1UL : 0UL); + + // Disable irqn interrupt while updating the handler's address + sl_interrupt_manager_disable_irq(irqn); + + #if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) + table = wrapped_vector_table; + #else + table = (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; + #endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ + + // Make sure the VTOR points to a table in RAM. + if (((uint32_t)table < RAM_BASE) || (uint32_t)table > (RAM_BASE + RAM_SIZE)) { + return SL_STATUS_NOT_INITIALIZED; + } + + table[irqn + 16] = handler; + + // Make sure all explicit memory access are complete before proceding. + __DSB(); + __ISB(); + + CORE_EXIT_CRITICAL(); + + if (interrupt_status == 1) { + sl_interrupt_manager_enable_irq(irqn); + } + + return SL_STATUS_OK; +#else + (void) irqn; + (void) handler; + return SL_STATUS_INVALID_CONFIGURATION; +#endif /* VECTOR_TABLE_IN_RAM */ +} + +/***************************************************************************//** + * @brief + * Get the interrupt preemption priority of an interrupt source. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_irq_priority(int32_t irqn) +{ + uint32_t irq_priority = 0; + + EFM_ASSERT((irqn >= -CORTEX_INTERRUPTS) && (irqn <= EXT_IRQ_COUNT)); + + irq_priority = get_priority(irqn); + + return irq_priority; +} + +/***************************************************************************//** + * @brief + * Set the interrupt preemption priority of an interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_priority(int32_t irqn, uint32_t priority) +{ + EFM_ASSERT((irqn >= -CORTEX_INTERRUPTS) && (irqn <= EXT_IRQ_COUNT)); + EFM_ASSERT(priority <= LOWEST_NVIC_PRIORITY); + + set_priority(irqn, priority); +} + +/***************************************************************************//** + * @brief + * Increase the interrupt preemption priority of an interrupt source + * relative to the default priority. + ******************************************************************************/ +void sl_interrupt_manager_increase_irq_priority_from_default(int32_t irqn, uint32_t diff) +{ + uint32_t prio = sl_interrupt_manager_get_default_priority(); + sl_interrupt_manager_set_irq_priority(irqn, prio - diff); +} + +/***************************************************************************//** + * @brief + * Decrease the interrupt preemption priority of an interrupt source. + * relative to the default priority. + ******************************************************************************/ +void sl_interrupt_manager_decrease_irq_priority_from_default(int32_t irqn, uint32_t diff) +{ + uint32_t prio = sl_interrupt_manager_get_default_priority(); + sl_interrupt_manager_set_irq_priority(irqn, prio + diff); +} + +/***************************************************************************//** + * @brief + * Get the default interrupt preemption priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_default_priority(void) +{ + return SL_INTERRUPT_MANAGER_DEFAULT_PRIORITY; +} + +/***************************************************************************//** + * @brief + * Get the highest interrupt preemption priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_highest_priority(void) +{ + return 0; +} + +/***************************************************************************//** + * @brief + * Get the lowest interrupt preemption priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_lowest_priority(void) +{ + return LOWEST_NVIC_PRIORITY; +} + +/***************************************************************************//** + * @brief + * Get the interrupt active status. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_active_irq(int32_t irqn) +{ + if ((int32_t)(irqn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)irqn) >> 5UL)] & (1UL << (((uint32_t)irqn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } else { + return(0U); + } +} + +/***************************************************************************//** + * @brief + * Enable an interrupts on the current core + ******************************************************************************/ +void enable_interrupt(int32_t irqn) +{ + if ((int32_t)(irqn) >= 0) { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)irqn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)irqn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + +/***************************************************************************//** + * @brief + * Disable an interrupts on the current core + ******************************************************************************/ +void disable_interrupt(int32_t irqn) +{ + if ((int32_t)(irqn) >= 0) { + NVIC->ICER[(((uint32_t)irqn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)irqn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + +/***************************************************************************//** + * @brief + * Set the priority of an interrupt. + ******************************************************************************/ +void set_priority(int32_t irqn, uint32_t priority) +{ + if (irqn >= 0) { + NVIC->IPR[((uint32_t)irqn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { + SCB->SHPR[(((uint32_t)irqn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + +/***************************************************************************//** + * @brief + * Get the priority of an interrupt. + ******************************************************************************/ +uint32_t get_priority(int32_t irqn) +{ + if (irqn >= 0) { + return(((uint32_t)NVIC->IPR[((uint32_t)irqn)] >> (8U - __NVIC_PRIO_BITS))); + } else { + return(((uint32_t)SCB->SHPR[(((uint32_t)irqn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + +/***************************************************************************//** + * @brief + * Get the current table of ISRs. + ******************************************************************************/ +sl_interrupt_manager_irq_handler_t* sl_interrupt_manager_get_isr_table(void) +{ +#if defined(SL_INTERRUPT_MANAGER_ENABLE_HOOKS) + return wrapped_vector_table; +#else + return (sl_interrupt_manager_irq_handler_t*)SCB->VTOR; +#endif /* SL_INTERRUPT_MANAGER_ENABLE_HOOKS */ +} diff --git a/Libs/platform/service/interrupt_manager/src/sli_interrupt_manager.h b/Libs/platform/service/interrupt_manager/src/sli_interrupt_manager.h new file mode 100644 index 0000000..4da329d --- /dev/null +++ b/Libs/platform/service/interrupt_manager/src/sli_interrupt_manager.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file + * @brief Interrupt Manager API internal utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_INTERRUPT_MANAGER_H +#define SLI_INTERRUPT_MANAGER_H + +#include "sl_interrupt_manager.h" +#include "em_device.h" + +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "sl_interrupt_manager_s2_config.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @brief + * Set a new RAM based interrupt vector table. + * + * @details + * This function will copy the existing vector table to a RAM area supplied + * by the application and set the interrupt controller to use that. + * + * @note + * The table RAM area must be aligned to a TBD byte boundary. + * + * @param[in] table + * Base address of new table. + * + * @param[in] handler_count + * The size of the table, unit is number of interrupt handlers. + * + * @return + * The prior interrupt vector table address. + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_3) \ + || (defined(SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM) \ + && (SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM == 1)) + +sl_interrupt_manager_irq_handler_t *sli_interrupt_manager_set_irq_table(sl_interrupt_manager_irq_handler_t *table, + uint32_t handler_count); + +#endif + +/***************************************************************************//** + * @brief + * Pre-interrupt hook. + * + * @details + * This function is called before each interrupt service routine + * when the interrupt manager hooks feature is enabled. + * + * @note + * The function is weakly defined, and may be user-defined. By default, the + * pre-interrupt hook is empty. + ******************************************************************************/ +void sl_interrupt_manager_irq_enter_hook(void); + +/***************************************************************************//** + * @brief + * Register post-interrupt hook. + * + * @details + * This function is called after each interrupt service routine + * when the interrupt manager hooks feature is enabled. + * + * @note + * The function is weakly defined, and may be user-defined. By default, the + * post-interrupt hook is empty. + ******************************************************************************/ +void sl_interrupt_manager_irq_exit_hook(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SL_INTERRUPT_MANAGER_H */ diff --git a/Libs/platform/service/iostream/inc/sl_iostream.h b/Libs/platform/service/iostream/inc/sl_iostream.h new file mode 100644 index 0000000..c33ab25 --- /dev/null +++ b/Libs/platform/service/iostream/inc/sl_iostream.h @@ -0,0 +1,286 @@ +/***************************************************************************//** + * @file + * @brief IO Stream. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_H +#define SL_IOSTREAM_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "sl_enum.h" +#include "sl_status.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iostream I/O Stream + * @brief I/O Stream can be used to read/write different formats of data to various streams. + * The source files for I/O Stream platform software module are present under platform/services/iostream. + * @details + * ## Overview + * + * I/O Stream is a platform module software that provides Input/Output functionalities + * by creating streams. Streams are abstractions allowing a uniform way to read/write + * data regardless of the physical communication interface. + * + * I/O Stream offers many interfaces, see submodules for a list of all types available + * and their specificities.You can load multiple streams in the project and you can + * select the interface that must be used at runtime.Some interface type can also + * be instantiated, meaning that you can have multiple instances of an interface + * type which will be normally bound to a hardware peripheral. + * + * ## Initialization + * + * The I/O Stream core doesn't require any initialization. Instead each stream type has + * their own initialization and their own configuration. See I/O Stream specific type + * to know more about how to initialize a stream. + * + * Note that most stream will set itself as the default stream during their initialization. + * Thus the initial default stream will be the last stream initialized. + * + * ## Default system-wide stream + * + * Multiple streams can be initialized in your application and you can configure a default + * stream that must be used when no stream is specified. Also note that the default stream + * will be used when calling printf and you can change the default stream at runtime. + * The following defines should be used for the default stream: + * + * SL_IOSTREAM_STDIN + * SL_IOSTREAM_STDOUT + * SL_IOSTREAM_STDERR + * + * ## RTOS - Task's default stream + * + * In the case of an RTOS environment, each task can set its own stream. By default, the task + * stream will be set to the system_wide default stream. From your task, you can change the + * default stream assigned to your task without affecting the other tasks' stream. + * + * ## Printf + * + * I/O Stream provides third-party printf integrations. It can work with toolchain implementation + * or with the tiny printf implementation for embedded system. The printf API doesn't have an + * argument for specifying the stream to be used, so I/O Stream provides a printf API that takes + * a stream as an argument and calls the configured third-party implementation of printf. + * + * @{ + ******************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define SL_IOSTREAM_STDIN 0 ///< Default input stream +#define SL_IOSTREAM_STDOUT 0 ///< Default output stream +#define SL_IOSTREAM_STDERR 0 ///< Default error stream +/// @endcond + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Struct representing iostream operations. +typedef struct { + void *context; ///< context + sl_status_t (*write)(void *context, const void *buffer, size_t buffer_length); ///< write + sl_status_t (*read)(void *context, void *buffer, size_t buffer_length, size_t *bytes_read); ///< read +} sl_iostream_t; + +/// @brief Enumeration representing the possible types of iostream instances. +SL_ENUM(sl_iostream_type_t){ + SL_IOSTREAM_TYPE_SWO = 0, ///< SWO Instance + SL_IOSTREAM_TYPE_RTT = 1, ///< RTT Instance + SL_IOSTREAM_TYPE_UART = 2, ///< USART Instance + SL_IOSTREAM_TYPE_VUART = 3, ///< Vuart + SL_IOSTREAM_TYPE_DEBUG_OUTPUT = 4, ///< Backchannel output Instance Type + SL_IOSTREAM_TYPE_LOOPBACK = 5, ///< Loopback Instance + SL_IOSTREAM_TYPE_UNDEFINED = 6, ///< Undefined Instance Type +}; + +/// @brief Struct representing an I/O Stream instance. +typedef struct { + sl_iostream_t *handle; ///< iostream instance handle. + char *name; ///< iostream instance name. + sl_iostream_type_t type; ///< iostream instance type. + uint8_t periph_id; ///< iostream peripheral id. + sl_status_t (*init)(void); ///< iostream instance init function. +} sl_iostream_instance_info_t; + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +// Special stream to be used when you want to avoid printing anything +extern sl_iostream_t sl_iostream_null; +/// @endcond + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Set the stream as default I/O Stream. + * + * @param[in] stream I/O Stream to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_set_default(sl_iostream_t *stream); + +/***************************************************************************//** + * Get the default I/O Stream configured. + * + * @return Status result + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_default(void); + +/***************************************************************************//** + * Configure the systemwide default stream. + * + * @param[in] stream I/O Stream to be used. + * + * @return Status result + ******************************************************************************/ +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) +sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream); +#else +#define sl_iostream_set_system_default sl_iostream_set_default +#endif + +/***************************************************************************//** + * Output data on a stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] buffer Buffer that contains the data to output. + * + * @param[in] buffer_length Data length contained in the buffer. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_write(sl_iostream_t *stream, + const void *buffer, + size_t buffer_length); + +/***************************************************************************//** + * Get data from a stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[out] buffer Buffer that contains the data to output. + * + * @param[in] buffer_length Data length contained in the buffer. + * + * @param[out] bytes_read Data length copied to the buffer. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_read(sl_iostream_t *stream, + void *buffer, + size_t buffer_length, + size_t *bytes_read); + +/***************************************************************************//** + * Print a character on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] c Character to print + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_putchar(sl_iostream_t *stream, + char c); + +/***************************************************************************//** + * Print a character on stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDIN; Default input stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[out] c Pointer to variable that will receive the character. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_getchar(sl_iostream_t *stream, + char *c); + +/***************************************************************************//** + * Print a formated string on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] format String that contains the text to be written. + * + * @param[in] argp A value identifying a variable arguments list. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, + const char *format, + va_list argp); + +#if defined(__GNUC__) +__attribute__((format(printf, 2, 3))) +#endif + +/***************************************************************************//** + * Print a formated string on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] format String that contains the text to be written. + * + * @param[in] ... Additional arguments. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_printf(sl_iostream_t *stream, + const char *format, + ...); + +/** @} (end addtogroup iostream) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_H diff --git a/Libs/platform/service/iostream/inc/sl_iostream_rtt.h b/Libs/platform/service/iostream/inc/sl_iostream_rtt.h new file mode 100644 index 0000000..26c8ca1 --- /dev/null +++ b/Libs/platform/service/iostream/inc/sl_iostream_rtt.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IO Stream RTT Component. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_RTT_H +#define SL_IOSTREAM_RTT_H + +#include "sl_iostream.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iostream + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup iostream_rtt I/O Stream RTT + * @brief I/O Stream RTT + * @details + * ## Overview + * + * Real Time Transfer (RTT) is a bi-directional communication interface developed + * by Segger and used with J-Link module. You need to have the Segger RTT library + * in your project to use this stream. It is offered as a third-party module in + * the Silicon Labs SDK. + * + * RTT module uses a control block structure located in RAM memory with a specific + * ID so that it can be discovered when a connection is established via J-Link. + * The control block references a ring buffer for each configured channel. You can + * configure the number and size of the ring buffers at compile-time in + * SEGGER_RTT_Conf.h configuration file. Please refer to Segger's documentation + * for further information on RTT. + * + * Note that you should only use this stream in a development environment. You + * should avoid using it in production. + * + * ## Initialization + * + * The stream sets itself as the default stream at the end of the initialization + * function.You must reconfigure the default interface if you have multiple streams + * in your project else the last stream initialized will be set as the system default + * stream. + * + * ## Power manager integration + * + * Because RTT communication uses the J-link debug interface when going into EM2 or EM3, + * the system will actually go into a special Energy Mode to maintain the debug + * capabilities and the power consumption will still remain high. Therefore it is unwise + * to keep a debug interface with RTT channel open if you want to test your power + * consumption. + * + * ## Communication channel connection + * + * For connecting to the RTT channel you can use the tools provided by Segger or you + * can open a telnet session and connect to the port 19021 using your host IP + * address when the debugger is connected using USB and using J-Link debugger IP address + * when your debugger is connected over ethernet. + * + * @{ + ******************************************************************************/ + +extern sl_iostream_t *sl_iostream_rtt_handle; ///< sl_iostream_rtt_handle +extern sl_iostream_instance_info_t sl_iostream_instance_rtt_info; ///< sl_iostream_instance_rtt_info + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * RTT Stream init. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_rtt_init(void); + +/** @} (end addtogroup iostream_rtt) */ +/** @} (end addtogroup iostream) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_RTT_H diff --git a/Libs/platform/service/iostream/src/sl_iostream.c b/Libs/platform/service/iostream/src/sl_iostream.c new file mode 100644 index 0000000..aa5a638 --- /dev/null +++ b/Libs/platform/service/iostream/src/sl_iostream.c @@ -0,0 +1,303 @@ +/***************************************************************************//** + * @file + * @brief IO Stream. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_iostream.h" +#include "sl_status.h" +#include "sl_assert.h" +#include "sl_core.h" + +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) +#include "cmsis_os2.h" +#include "sli_cmsis_os2_ext_task_register.h" +#endif + +#if defined(SL_CATALOG_PRINTF_PRESENT) +#include "printf.h" +#else +#include +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) +#define TASK_REGISTER_ID_INVALID 0xFF +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) +static sli_task_register_id_t sli_task_register_id = TASK_REGISTER_ID_INVALID; +static sl_iostream_t *sli_iostream_system_default = NULL; +#endif +static sl_iostream_t *sli_iostream_default = NULL; + +sl_iostream_t sl_iostream_null = { + .write = NULL, + .read = NULL, + .context = NULL +}; + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_PRINTF_PRESENT) +static void stream_putchar(char character, + void *arg); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Registers default IO stream to be used + ******************************************************************************/ +sl_status_t sl_iostream_set_default(sl_iostream_t *stream) +{ +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + sli_task_register_id_t reg_id; + sl_status_t status; +#endif + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + if (osThreadGetId() != NULL) { + reg_id = sli_task_register_id; + if (reg_id == TASK_REGISTER_ID_INVALID) { + status = sli_osTaskRegisterNew(®_id); + EFM_ASSERT(status == SL_STATUS_OK); + sli_task_register_id = reg_id; + } + } +#endif + sli_iostream_default = stream; + CORE_EXIT_CRITICAL(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + if (osThreadGetId() != NULL) { + status = sli_osTaskRegisterSetValue(NULL, reg_id, (uint32_t)stream); + EFM_ASSERT(status == SL_STATUS_OK); + } +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Get default IO stream configured + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_default(void) +{ +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + sl_status_t status; + sli_task_register_id_t reg_id; +#endif + sl_iostream_t *stream = NULL; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + reg_id = sli_task_register_id; +#endif + stream = sli_iostream_default; + CORE_EXIT_CRITICAL(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) + if (osThreadGetId() != NULL) { + if (reg_id != TASK_REGISTER_ID_INVALID) { + uint32_t reg; + + status = sli_osTaskRegisterGetValue(NULL, sli_task_register_id, ®); + EFM_ASSERT(status == SL_STATUS_OK); + + stream = (sl_iostream_t *)reg; + } + } + if (stream == NULL) { + CORE_ENTER_CRITICAL(); + stream = sli_iostream_system_default; + CORE_EXIT_CRITICAL(); + } +#endif + + return stream; +} + +/***************************************************************************//** + * Set systemwide default IO stream + ******************************************************************************/ +#if defined(SL_CATALOG_KERNEL_PRESENT) && !defined(SL_IOSTREAM_FORCE_BAREMETAL) +sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream) +{ + sl_status_t status = SL_STATUS_OK; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_iostream_system_default = stream; + CORE_EXIT_CRITICAL(); + return status; +} +#endif + +/***************************************************************************//** + * Stream write implementation + ******************************************************************************/ +sl_status_t sl_iostream_write(sl_iostream_t *stream, + const void *buffer, + size_t buffer_length) +{ + if (stream == SL_IOSTREAM_STDOUT) { + stream = sl_iostream_get_default(); + } + + if ((stream != NULL) && (stream->write != NULL)) { + return stream->write(stream->context, buffer, buffer_length); + } else { + return SL_STATUS_INVALID_CONFIGURATION; + } +} + +/***************************************************************************//** + * Stream read implementation + ******************************************************************************/ +sl_status_t sl_iostream_read(sl_iostream_t *stream, + void *buffer, + size_t buffer_length, + size_t *bytes_read) +{ + size_t size; + size_t *read_size = &size; + + if (stream == SL_IOSTREAM_STDIN) { + stream = sl_iostream_get_default(); + } + + if (bytes_read != NULL) { + read_size = bytes_read; + } + + if ((stream != NULL) && (stream->read != NULL)) { + return stream->read(stream->context, buffer, buffer_length, read_size); + } else { + return SL_STATUS_INVALID_CONFIGURATION; + } +} + +/***************************************************************************//** + * Stream putchar implementation + ******************************************************************************/ +sl_status_t sl_iostream_putchar(sl_iostream_t *stream, + char c) +{ + return sl_iostream_write(stream, &c, 1); +} + +/***************************************************************************//** + * Stream getchar implementation + ******************************************************************************/ +sl_status_t sl_iostream_getchar(sl_iostream_t *stream, + char *c) +{ + return sl_iostream_read(stream, c, 1, NULL); +} + +/***************************************************************************//** + * Stream vprintf implementation + ******************************************************************************/ +sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, + const char *format, + va_list argp) +{ +#if !defined(SL_CATALOG_PRINTF_PRESENT) + sl_iostream_t *default_stream; +#endif + sl_iostream_t *output_stream = stream; + sl_status_t status = SL_STATUS_OK; + int ret; + +#if defined(SL_CATALOG_PRINTF_PRESENT) + if (output_stream == SL_IOSTREAM_STDOUT) { + output_stream = sl_iostream_get_default(); + } + ret = vfctprintf(stream_putchar, output_stream, format, argp); +#else + if (output_stream == SL_IOSTREAM_STDOUT) { + default_stream = sl_iostream_get_default(); + output_stream = default_stream; + } else { + default_stream = sl_iostream_get_default(); + if (default_stream != output_stream) { + sl_iostream_set_default(output_stream); + } + } + + ret = vprintf(format, argp); + if (default_stream != output_stream) { + sl_iostream_set_default(default_stream); + } +#endif + if (ret <= 0) { + status = SL_STATUS_OBJECT_WRITE; + } + + return status; +} + +/***************************************************************************//** + * Stream printf implementation + ******************************************************************************/ +sl_status_t sl_iostream_printf(sl_iostream_t *stream, + const char *format, + ...) +{ + sl_status_t status; + va_list argp; + va_start(argp, format); + status = sl_iostream_vprintf(stream, format, argp); + va_end(argp); + return status; +} + +/***************************************************************************//** + * putchar implementation for sl_iostream_printf; called by fnctprintf() + ******************************************************************************/ +#if defined(SL_CATALOG_PRINTF_PRESENT) +static void stream_putchar(char character, + void *arg) +{ + sl_iostream_putchar((sl_iostream_t *)arg, character); +} +#endif diff --git a/Libs/platform/service/iostream/src/sl_iostream_rtt.c b/Libs/platform/service/iostream/src/sl_iostream_rtt.c new file mode 100644 index 0000000..12961da --- /dev/null +++ b/Libs/platform/service/iostream/src/sl_iostream_rtt.c @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file + * @brief IO Stream RTT Component. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_iostream_rtt.h" +//#include "SEGGER_RTT.h" +#include "sl_status.h" + +#if !defined(IOSTREAM_RTT_UP_MODE) +#define IOSTREAM_RTT_UP_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM +#endif + +#if !defined(IOSTREAM_RTT_DOWN_MODE) +#define IOSTREAM_RTT_DOWN_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM +#endif + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +static sl_status_t rtt_write(void *context, + const void *buffer, + size_t buffer_length); + +static sl_status_t rtt_read(void *context, + void *buffer, + size_t buffer_length, + size_t *bytes_read); + +/******************************************************************************* + ****************************** VARIABLES ********************************** + ******************************************************************************/ + +static sl_iostream_t sl_iostream_rtt = { + .read = rtt_read, + .write = rtt_write, + .context = NULL +}; + +sl_iostream_t *sl_iostream_rtt_handle = &sl_iostream_rtt; + +sl_iostream_instance_info_t sl_iostream_instance_rtt_info = { + .handle = &sl_iostream_rtt, + .name = "rtt", + .type = SL_IOSTREAM_TYPE_RTT, + .periph_id = 0, + .init = sl_iostream_rtt_init, +}; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * RTT Stream init. + ******************************************************************************/ +sl_status_t sl_iostream_rtt_init(void) +{ + //SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_UP_MODE); + //SEGGER_RTT_ConfigDownBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_DOWN_MODE); + sl_iostream_set_system_default(&sl_iostream_rtt); + + return SL_STATUS_OK; +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Internal RTT stream write implementation + ******************************************************************************/ +static sl_status_t rtt_write(void *context, + const void *buffer, + size_t buffer_length) +{ + uint32_t ret = 0; + sl_status_t status; + (void)context; + (void)ret; + + //ret = SEGGER_RTT_Write(0, buffer, buffer_length); + +#if ((IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_TRIM) \ + || (IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_SKIP)) + status = SL_STATUS_OK; // Ignore error +#else + if (ret > 0) { + status = SL_STATUS_OK; + } else { + status = SL_STATUS_IO; + } +#endif + + return status; +} + +/***************************************************************************//** + * Internal RTT stream read implementation + ******************************************************************************/ +static sl_status_t rtt_read(void *context, + void *buffer, + size_t buffer_length, + size_t *bytes_read) +{ + sl_status_t status; + (void)context; + + // *bytes_read = SEGGER_RTT_Read(0, buffer, buffer_length); + + if (*bytes_read > 0) { + status = SL_STATUS_OK; + } else { + status = SL_STATUS_EMPTY; + } + + return status; +} diff --git a/Libs/platform/service/memory_manager/inc/sl_memory_manager.h b/Libs/platform/service/memory_manager/inc/sl_memory_manager.h new file mode 100644 index 0000000..21767ab --- /dev/null +++ b/Libs/platform/service/memory_manager/inc/sl_memory_manager.h @@ -0,0 +1,971 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver API definition. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMORY_MANAGER_H_ +#define SL_MEMORY_MANAGER_H_ + +#include +#include +#include +#include + +#include "sl_status.h" +#include "sl_core.h" +#include "sl_memory_manager_region.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup memory_manager Memory Manager + * + * @details + * ## Overview + * + * The Memory Manager is a platform-level software module that provides different + * ways to perform runtime allocations, either one shot or dynamic. + * The Memory Manager complements the toolchain linker by managing the RAM memory + * not allocated/partitioned by the linker. It offers different constructs that + * will help the different Silicon Labs SDK software modules and your application + * to build, as much as possible, an efficient and optimized RAM layout. The main + * Memory Manager constructs will be: + * - A dynamic allocation API + * - A memory pool API + * - A dynamic reservation API + * + * The Memory Manager can be used in an RTOS context as it is thread-safe by + * protecting adequately its internal shared resources. + * + * ## Initialization + * + * The initialization part includes the following configuration files: + * - \b sl_memory_manager_region_config.h + * - \b sl_memory_manager_config.h + * + * These header files offer a few configurations for the Memory Manager. + * They use the CMSIS Configuration Wizard Annotations that can be rendered + * by Simplicity Studio to set graphically the configuration settings value. + * + * The API function sl_memory_init() is used to initialize the Memory Manager + * module. This function must be called early during your initialization sequence. + * If the SL System component (@ref system) is used by your application, the + * sl_memory_init() call will be added automatically to your initialization + * sequence. + * + * \a sl_memory_manager_region_config.h allows to configure the stack size for + * the application. The default value of 4096 bytes for SL_STACK_SIZE will + * be used by the linker to allocate a stack zone in the RAM. In a baremetal + * application, the stack size is bound to the value set by SL_STACK_SIZE. + * So you should carefully size the stack in that case. + * In an RTOS application, the stack size SL_STACK_SIZE will serve mainly for the + * code running in the main() context until the kernel is launched. Once the kernel is + * started, the different tasks' stacks, created upon tasks' creation, will allow + * to save the different contexts (that is task, function, ISR contexts). The main + * stack will be less active while the application's tasks are running. + * + * @note It is not possible to specify a minimum heap size via a configuration value + * in \a sl_memory_manager_region_config.h. The GCC and IAR linker files define + * a heap section in RAM that will be the last zone of the RAM partitioned by + * the toolchain linker. The size of this heap zone will be the remaining + * space of the RAM. If you need to perform some checks on the heap size, you + * should do it at runtime using the Memory Manager \ref subsubsection-statistics + * "statistics API". You cannot do it during the toolchain preprocessor time. + * + * ## Functionalities + * + * The Memory Manager offers different functionalities such as: + * - Dynamically allocating and freeing blocks. + * - Creating and deleting memory pools. Allocating and freeing fixed-size + * blocks from a given pool. + * - Reserving and releasing blocks. + * - Getting statistics about the heap usage and the stack. + * - Retargeting the standard C library memory functions malloc()/free()/ + * calloc()/realloc() to the Memory Manager ones. + * - Overloading the C++ standard new/delete operators to the Memory Manager + * malloc()/free() + * + * \subsubsection subsubsection-dynamic-allocation Dynamic Allocation + * The dynamic allocation API allows to dynamically allocate and free memory blocks + * of various sizes. The API supports the classic signatures of memory functions + * malloc()/free()/calloc()/realloc() while also offering variants of the same + * functions. + * + * + *
    OperationStandard-Like FunctionVariant Function + *
    Allocating a blocksl_malloc() + *
      + *
    • sl_memory_alloc() + *
    • sl_memory_alloc_advanced() + *
    + *
    Freeing a blocksl_free()sl_memory_free() + *
    Allocating a block whose content is zero'edsl_calloc()sl_memory_calloc() + *
    Re-allocating a blocksl_realloc()sl_memory_realloc() + *
    + * + * The variants functions \a sl_memory_xxxx() differs from the standard-like functions + * with the following: + * - They return an error code of type \a sl_status_t. You may want + * to process any returned error code different from \a SL_STATUS_OK. + * - They allow to specify a block alignment requirement in bytes. The alignment + * can be any power-of-two values between 1 and 512 bytes inclusively. The default + * block alignment the Memory Manager will use is 8 bytes to maximize CPU accesses + * to allocated memory blocks. + * - They allow to specify a block type as long-term or short-term (further explained + * below). The Memory Manager allows to allocate a block from different ends of the heap + * to limit the fragmentation. + * + * Allocating a block can be done by specifying your requested size with the simple + * sl_malloc(). If you have a special alignment requirement, the function + * sl_memory_alloc_advanced() is the one to use. + * The Memory Manager will use a first fit algorithm to find the block fitting + * the requested size. If the found block is too large, the allocator tries to split it + * to create a new free block from the unwanted portion of the found block. The block + * internal split operation helps to limit the internal fragmentation. + * + * The dynamic allocation API allows to specify the block type as long-term + * (BLOCK_TYPE_LONG_TERM) or short-term (BLOCK_TYPE_SHORT_TERM) with the + * functions sl_memory_alloc() or sl_memory_alloc_advanced(). + * The long-term (LT) allocations are allocated from the heap start, + * while short-term (ST) ones are allocated from the heap end. LT/ST allocations + * relate to the expected lifetime of the block allocation. LT blocks are used for + * the full duration of the application or for something that is expected + * to last a long time. For instance, a control data structure enabling the proper + * functioning of a stack's layer, a driver, a part of the application layer. + * ST blocks are used for something that is expected to be freed quite quickly. + * For example, a received buffer that needs to be processed and once processed + * will be freed. + * Grouping your allocations as LT blocks and/or ST blocks can help to limit the + * heap fragmentation. + * Certain functions does not allow to indicate the block type. In that case, + * a default type is selected by the allocator. + * + * + *
    FunctionBlock type + *
    sl_malloc()Long-term by default + *
    sl_memory_alloc()Long-term or short-term + *
    sl_memory_alloc_advanced()Long-term or short-term + *
    sl_calloc()Long-term by default + *
    sl_memory_calloc()Long-term or short-term + *
    sl_realloc()Long-term by default + *
    sl_memory_realloc()Long-term by default + *
    + * + * Freeing a block is done by calling sl_free() or sl_memory_free(). sl_memory_free() + * returns an error code of type sl_status_t that you may want to test. Passing a NULL + * pointer to sl_free() or sl_memory_free() results in a neutral situation where the + * free() function will do nothing. If the same block is freed twice, the function + * sl_memory_free() will return an error. During the free operation, the function will + * try to merge adjacent blocks to the block that is being freed in order to limit + * the internal fragmentation. The adjacent blocks must, of course, not be in use + * to be merged. + * + * If you want to get a block from the heap whose content has been initialized to zero + * to avoid any garbage values, the function sl_calloc() or sl_memory_calloc() can be + * called. + * + * If you need to reallocate a block, the function sl_realloc() or sl_memory_realloc() + * should be called. Both versions allow to: + * - Extend the block with the requested size greater than the original size. + * - Reduce the block with the requested size smaller than the original size. + * - Extend a different block with the requested size greater than the original size. + * + * The block can be moved elsewhere in the heap if it is impossible to extend it in its + * current memory space. A reduced block will always stay in the original block space as the + * allocator does not need to provide a different block. + * The content of the reallocated memory block is preserved up to the lesser of the + * new and old sizes, even if the block is moved to a new location. If the new size + * is larger, the value of the newly allocated portion is indeterminate. + * Some combinations of input parameters when calling sl_realloc() or sl_memory_realloc() + * will lead to the same behavior as sl_malloc(), sl_memory_alloc() or sl_free(), + * sl_memory_free() (cf. the sl_realloc() or sl_memory_realloc() function description + * for more details about those combinations). + * + * The following code snippet shows a basic block allocation and + * deallocation using the standard-like functions: + * @code{.c} + * uint8_t *ptr8; + * + * ptr8 = (uint8_t *)sl_malloc(200); + * memset(ptr8, 0xAA, 100); + * sl_free(ptr8); + * @endcode + * + * This other code snippet shows the same basic block allocation and + * deallocation using the variant functions: + * @code{.c} + * uint8_t *ptr8; + * sl_status_t status; + * + * status = sl_memory_alloc(100, BLOCK_TYPE_LONG_TERM, (void **)&ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * memset(ptr8, 0xBB, 100); + * + * status = sl_memory_free(ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * @endcode + * + * ### Memory Pool + * + * The memory pool API allows to: + * - Create a pool composed of N number of fixed-size blocks: sl_memory_create_pool(). + * - Delete a pool: sl_memory_delete_pool(). + * - Get a block from the pool: sl_memory_pool_alloc(). + * - Free a pool's block: sl_memory_pool_free(). + * + * Memory pools are convenient if you want to ensure a sort of guaranteed quotas + * for some memory allocations situations. It is also more robust to unexpected + * allocations errors as opposed to the dynamic allocation API in which a block + * allocation can fail randomly if there is no free block to satisfy the requested + * size. + * + * The memory pool API uses a pool handle. This handle is initialized when the pool + * is created with sl_memory_create_pool(). Then this handle is passed as an input + * parameter of the other functions. The handle can be allocated statically or + * dynamically. A static pool handle means the handle of type + * @ref sl_memory_pool_t "sl_memory_pool_t{}" is a global variable for example. + * A dynamic pool handle means the handle is obtained from the heap itself by + * calling the function sl_memory_pool_handle_alloc().The dynamic pool handle will + * be freed with a call to sl_memory_pool_handle_free(). + * + * The following code snippet shows a typical memory pool API sequence using + * a static pool handle: + * @code{.c} + * uint8_t *ptr8; + * sl_status_t status; + * sl_memory_pool_t pool1_handle = { 0 }; + * + * // Create a pool of 15 blocks whose size is 100 bytes for each block. + * status = sl_memory_create_pool(100, 15, &pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * status = sl_memory_pool_alloc(&pool1_handle, (void **)&ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * memset(ptr8, 0xCC, 100); + * + * status = sl_memory_pool_free(&pool1_handle, ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * status = sl_memory_delete_pool(&pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * @endcode + * + * This other code snippet presents the previous typical memory pool API sequence + * using a dynamic pool handle: + * @code{.c} + * sl_status_t status; + * sl_memory_pool_t *pool1_handle = NULL; + * + * status = sl_memory_pool_handle_alloc(&pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * // Create a pool of 15 blocks of 100 bytes in size. + * status = sl_memory_create_pool(100, 15, &pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * // Get blocks from the pool, use them and free them once done. + * ... + * + * status = sl_memory_delete_pool(&pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * status = sl_memory_pool_handle_free(pool1_handle); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * @endcode + * + * ### Dynamic Reservation + * + * The dynamic reservation is a special construct allowing to reserve a block + * of a given size with sl_memory_reserve_block() and to release it with + * sl_memory_release_block(). The reserved block can then be used to any + * application purposes. The reserved block will be taken from the + * short-term section at the end of the heap. + * Please note that the dynamic reservation API is not meant + * to be used in the same way as the \ref subsubsection-dynamic-allocation + * "dynamic allocation API". + * + * The dynamic reservation API uses a reservation handle. This handle is initialized + * when the block is reserved with sl_memory_reserve_block(). Then this handle + * is passed as an input parameter to the other functions. The handle can be + * allocated statically or dynamically. A static reservation handle means the handle + * of type @ref sl_memory_reservation_t "sl_memory_reservation_t{}" is a global + * variable for example. A dynamic reservation handle means the handle is + * obtained from the heap itself by calling the function + * sl_memory_reservation_handle_alloc(). The dynamic reservaiton handle will be + * freed with a call to sl_memory_reservation_handle_free(). + * + * The following code snippet shows a typical dynamic reservation API sequence + * using a static reservation handle: + * @code{.c} + * uint8_t *ptr8; + * sl_status_t status; + * sl_memory_reservation_t reservation_handle1 = { 0 }; + * + * status = sl_memory_reserve_block(1024, + * SL_MEMORY_BLOCK_ALIGN_8_BYTES, + * reservation_handle1, + * (void **)&ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * memset(ptr8, 0xDD, 1024); + * + * status = sl_memory_release_block(&reservation_handle1); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * @endcode + * + * This other code snippet demonstrates the previous typical dynamic reservation API + * sequence using a dynamic reservation handle: + * @code{.c} + * uint8_t *ptr8; + * sl_status_t status; + * sl_memory_reservation_t *reservation_handle1; + * + * status = sl_memory_reservation_handle_alloc(&reservation_handle1); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * status = sl_memory_reserve_block(1024, + * SL_MEMORY_BLOCK_ALIGN_8_BYTES, + * reservation_handle1, + * (void **)&ptr8); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * memset(ptr8, 0xEE, 1024); + * + * status = sl_memory_release_block(&reservation_handle1); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * + * status = sl_memory_reservation_handle_free(reservation_handle1); + * if (status != SL_STATUS_OK) { + * // Process the error condition. + * } + * @endcode + * + * \subsubsection subsubsection-statistics Statistics + * + * As your code is allocating and freeing blocks, you may want to know at a certain + * instant what the current state of the heap is. Some heap statistics queries at + * runtime can help to understand the current usage of the heap. By using the + * following statistics functions, you may be able to perform some asynchronous + * runtime heap checks: + * - Total heap size: sl_memory_get_total_heap_size(). + * - Current free heap size: sl_memory_get_free_heap_size(). + * - Current used heap size: sl_memory_get_used_heap_size(). + * - Highest accumulated heap size usage: sl_memory_get_heap_high_watermark(). + * - You can reset the high heap usage watermark with + * sl_memory_reset_heap_high_watermark(). + * + * Besides a few functions each dedicated to a specific statistic, the function + * sl_memory_get_heap_info() allows to get a general heap information structure + * of type @ref sl_memory_heap_info_t "sl_memory_heap_info_t{}" with several heap + * statistics. Some of them overlap the statistics returned by the dedicated + * functions while the others complements statistics returned by the dedicated + * functions. Refer to the description of @ref sl_memory_heap_info_t + * "sl_memory_heap_info_t{}" for more information of each field. + * + * If you want to know the start address and the total size of the program's + * stack and/or heap, simply call respectively the function sl_memory_get_stack_region() + * and/or sl_memory_get_heap_region(). + * + * ### C/C++ Toolchains Standard Memory Functions Retarget/Overload + * + * A program can perform dynamic memory allocations and deallocations using the + * standard memory functions whose implementation is provided by the C or C++ + * toolchain libraries. + * - C toolchain for the classic malloc()/free()/calloc()/realloc() + * - C++ toolchain for the new/delete operators + * + * The Memory Manager supports the C standard memory functions retarget and the C++ + * new/delete overload. + * + * When the \b memory_manager component is installed, the C standard memory + * functions are automatically retargeted to the Memory Manager ones: + * - GCC: coupled to the linker option "--wrap", the functions retargeted are + * - standard _malloc_r() -> sl_malloc() + * - standard _free_r() -> sl_free() + * - standard _calloc_r() -> sl_calloc() + * - standard _realloc_r() -> sl_realloc() + * - IAR: it has three separate heap memory handlers (the basic, the advanced, + * and the no-free heap handlers). IAR generally auto-selects one of the handlers. + * - Basic heap + * - standard __basic_malloc() -> sl_malloc() + * - standard __basic_free() -> sl_free() + * - standard __basic_calloc() -> sl_calloc() + * - standard __basic_realloc() -> sl_realloc() + * - Advanced heap + * - standard __iar_dl_malloc() -> sl_malloc() + * - standard __iar_dl_free() -> sl_free() + * - standard __iar_dl_calloc() -> sl_calloc() + * - standard __iar_dl_realloc() -> sl_realloc() + * - No Free heap + * - standard __no_free_malloc() -> sl_malloc() + * - standard __no_free_calloc() -> sl_calloc() + * + * If you need the C++ new/delete global overload calling sl_memory_alloc() and + * sl_memory_free(), please install the additional component + * \b memory_manager_cpp. + * This global overload of new/delete operators will also apply to any C++ + * standard containers (for example vector, string, list). + * + * @note The Silicon Labs SDK generates a GCC or IAR linker script with Simplicity + * Studio. A typical toolchain linker script will define a section called "heap" + * or "HEAP". Usually, the C memory standard functions will assume a linker-defined + * "heap" section exists. If the memory_manager component is present, the + * toolchain linker script will define a new heap section named "memory_manager_heap" + * or "MEMORY_MANAGER_HEAP". Since the Memory Manager retargets the standard + * function malloc()/free()/calloc()/realloc() to the Memory Manager ones, there + * should not be any issues in your program. If an unlikely situation occurs where + * the toolchain standard memory functions retarget does not work, your application + * might end up calling a standard malloc() implementation from the + * toolchain instead of the Memory Manager one. In that case, a runtime + * error can occur and it is expected. You should then review the project settings + * to detect why the Memory Manager retarget did not work properly. + * + * ## Hints + * ### Memory Allocations from ISR + * + * In general, ISR must be kept short. Allocating and freeing blocks from an ISR is + * possible but you should be careful. Nothing really prevents you from calling the + * dynamic allocation API functions such as sl_malloc() and sl_free(). But keep in + * mind a few things with the dynamic allocation API: + * - The dynamic allocation API functions protect their internal resources + * such as global lists managing the heap metadata by using critical sections. + * So when in your ISR, you will disable interrupts for a certain period of time, + * preventing other interrupts to be processed in time if your application has hard + * real-time constraints. This increases the overall interrupt latency of your + * system if this ISR executes very often to perform a dynamic memory operation + * - They can introduce non-deterministic behavior which is undesirable if your + * application requires crucial precise timing + * - A function such as sl_malloc() can fail if there is no block to satisfy + * your requested size allocation. Implementing the proper error handling in the + * ISR may increase the time spent in the ISR. + * + * In the end, it really depends of your ISR processing context doing memory + * allocations/deallocations. If you really need to perform dynamic allocation from + * ISR, it may be better at least to use a memory pool. Getting and releasing a block + * from a pool is an operation more deterministic. And if you have properly + * sized your pool with a number of available blocks, you are less likely to + * encounter an allocation error. + * + * @{ + *****************************************************************************/ + +// ---------------------------------------------------------------------------- +// DEFINES + +/// Special value to indicate the default block alignment to the Memory Manager +/// allocator. 8 bytes is the minimum alignment to account for largest CPU data +/// type that can be used in some block allocation scenarios. +#define SL_MEMORY_BLOCK_ALIGN_DEFAULT 0xFFFFFFFFU + +/// Pre-defined values for block alignment managed by the Memory Manager allocator. +#define SL_MEMORY_BLOCK_ALIGN_8_BYTES 8U ///< 8 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_16_BYTES 16U ///< 16 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_32_BYTES 32U ///< 32 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_64_BYTES 64U ///< 64 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_128_BYTES 128U ///< 128 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_256_BYTES 256U ///< 256 bytes alignment. +#define SL_MEMORY_BLOCK_ALIGN_512_BYTES 512U ///< 512 bytes alignment. + +// ---------------------------------------------------------------------------- +// DATA TYPES + +/// @brief Block type. +typedef enum { + BLOCK_TYPE_LONG_TERM = 0, ///< Long-term block type. + BLOCK_TYPE_SHORT_TERM = 1 ///< Short-term block type. +} sl_memory_block_type_t; + +/// @brief General purpose heap information. +typedef struct { + uint32_t base_addr; ///< Heap base address. + size_t used_size; ///< Used size (in bytes), independently of alignment. + size_t free_size; ///< Free size (in bytes), independently of alignment. + size_t total_size; ///< Total heap size (in bytes). + size_t free_block_count; ///< Number of free blocks. + size_t free_block_largest_size; ///< Largest free block size (in bytes). + size_t free_block_smallest_size; ///< Smallest free block size (in bytes). + size_t used_block_count; ///< Number of used blocks. + size_t used_block_largest_size; ///< Largest used block size (in bytes). + size_t used_block_smallest_size; ///< Smallest used block size (in bytes). +} sl_memory_heap_info_t; + +/// @brief Memory block reservation handle. +typedef struct { + void *block_address; ///< Reserved block base address. + size_t block_size; ///< Reserved block size (in bytes). +} sl_memory_reservation_t; + +/// @brief Memory pool handle. +typedef struct { +#if defined(SL_MEMORY_POOL_POWER_AWARE) + sl_memory_reservation_t *reservation; ///< Pointer to reservation handle. +#else + void *block_address; ///< Reserved block base address. +#endif + uint32_t *block_free; ///< Pointer to pool's free blocks list. + size_t block_count; ///< Max quantity of blocks in the pool. + size_t block_size; ///< Size of each block. +} sl_memory_pool_t; + +// ---------------------------------------------------------------------------- +// PROTOTYPES + +/***************************************************************************//** + * Initializes the memory manager. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function should only be called once. + ******************************************************************************/ +sl_status_t sl_memory_init(void); + +/***************************************************************************//** + * Reserves a memory block that will never need retention in EM2. + * + * @param[in] size Size of the block, in bytes. + * @param[in] align Required alignment for the block, in bytes. + * @param[out] block Pointer to variable that will receive the start address + * of the allocated block. NULL in case of error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note Required alignment of memory block (in bytes) MUST be a power of 2 + * and can range from 1 to 512 bytes. + * The define SL_MEMORY_BLOCK_ALIGN_DEFAULT can be specified to select + * the default alignment. + ******************************************************************************/ +sl_status_t sl_memory_reserve_no_retention(size_t size, + size_t align, + void **block); + +/***************************************************************************//** + * Allocates a memory block of at least requested size from the heap. Simple + * version. + * + * @param[in] size Size of the block, in bytes. + * + * @return Pointer to allocated block if successful. Null pointer if + * allocation failed. + * + * @note Requesting a block of 0 byte will return a null pointer. + * + * @note All allocated blocks using this function will be considered long-term + * allocations. + ******************************************************************************/ +void *sl_malloc(size_t size); + +/***************************************************************************//** + * Dynamically allocates a block of memory. + * + * @param[in] size Size of the block, in bytes. + * @param[in] type Type of block (long-term or short-term). + * BLOCK_TYPE_LONG_TERM + * BLOCK_TYPE_SHORT_TERM + * @param[out] block Pointer to variable that will receive the start address + * of the allocated block. NULL in case of error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_alloc(size_t size, + sl_memory_block_type_t type, + void **block); + +/***************************************************************************//** + * Dynamically allocates a block of memory. Advanced version that allows to + * specify alignment. + * + * @param[in] size Size of the block, in bytes. + * @param[in] align Required alignment for the block, in bytes. + * @param[in] type Type of block (long-term or short term). + * BLOCK_TYPE_LONG_TERM + * BLOCK_TYPE_SHORT_TERM + * @param[out] block Pointer to variable that will receive the start address + * of the allocated block. NULL in case of error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note Required alignment of memory block (in bytes) MUST be a power of 2 + * and can range from 1 to 512 bytes. + * The define SL_MEMORY_BLOCK_ALIGN_DEFAULT can be specified to select + * the default alignment. + ******************************************************************************/ +sl_status_t sl_memory_alloc_advanced(size_t size, + size_t align, + sl_memory_block_type_t type, + void **block); + +/***************************************************************************//** + * Frees a previously allocated block back into the heap. Simple version. + * + * @param[in] ptr Pointer to memory block to be freed. + * + * @note Passing a null pointer does nothing. + ******************************************************************************/ +void sl_free(void *ptr); + +/***************************************************************************//** + * Frees a dynamically allocated block of memory. + * + * @param[in] block Pointer to the block that must be freed. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_free(void *block); + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. Simple version. + * + * @param[in] item_count Number of elements to be allocated. + * @param[in] size Size of each elements, in bytes. + * + * @return Pointer to allocated block if successful. Null pointer if + * allocation failed. + * + * @note All allocated blocks using this function will be considered long-term + * allocations. + ******************************************************************************/ +void *sl_calloc(size_t item_count, + size_t size); + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. + * + * @param[in] item_count Number of elements to be allocated. + * @param[in] size Size of each elements, in bytes. + * @param[in] type Type of block (long-term or short-term). + * BLOCK_TYPE_LONG_TERM + * BLOCK_TYPE_SHORT_TERM + * @param[out] block Pointer to variable that will receive the start + * address of the allocated block. NULL in case of + * error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_calloc(size_t item_count, + size_t size, + sl_memory_block_type_t type, + void **block); + +/***************************************************************************//** + * Resizes a previously allocated memory block. Simple version. + * + * @param[in] ptr Pointer to the allocation to resize. If NULL, behavior + * is same as sl_malloc(), sl_memory_alloc(). + * @param[in] size New size of the block, in bytes. If 0, behavior is same as + * sl_free(), sl_memory_free(). + * + * @return Pointer to newly allocated block, if successful. Null pointer if + * re-allocation failed. + * + * @note All re-allocated blocks using this function will be considered + * long-term allocations. + * + * @note 'ptr' NULL and 'size' of 0 bytes is an incorrect parameters + * combination. No reallocation will be done by the function as it is + * an error condition. + * + * @note If the new 'size' is the same as the old, the function changes nothing + * and returns the same provided address 'ptr'. + ******************************************************************************/ +void *sl_realloc(void *ptr, + size_t size); + +/***************************************************************************//** + * Resizes a previously allocated memory block. + * + * @param[in] ptr Pointer to the allocation to resize. If NULL, behavior + * is same as sl_malloc(), sl_memory_alloc(). + * @param[in] size New size of the block, in bytes. If 0, behavior is same as + * sl_free(), sl_memory_free(). + * @param[out] block Pointer to variable that will receive the start address of + * the new allocated memory. NULL in case of error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note All re-allocated blocks using this function will be considered + * long-term allocations. + * + * @note 'ptr' NULL and 'size' of 0 bytes is an incorrect parameters + * combination. No reallocation will be done by the function as it is + * an error condition. + * + * @note If the new 'size' is the same as the old, the function changes nothing + * and returns the same provided address 'ptr'. + ******************************************************************************/ +sl_status_t sl_memory_realloc(void *ptr, + size_t size, + void **block); + +/***************************************************************************//** + * Dynamically reserves a block of memory. + * + * @param[in] size Size of the block, in bytes. + * @param[in] align Required alignment for the block, in bytes. + * @param[in] handle Handle to the reserved block. + * @param[out] block Pointer to variable that will receive the start address + * of the allocated block. NULL in case of error condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note Required alignment of memory block (in bytes) MUST be a power of 2 + * and can range from 1 to 512 bytes. + * The define SL_MEMORY_BLOCK_ALIGN_DEFAULT can be specified to select + * the default alignment. + ******************************************************************************/ +sl_status_t sl_memory_reserve_block(size_t size, + size_t align, + sl_memory_reservation_t *handle, + void **block); + +/***************************************************************************//** + * Frees a dynamically reserved block of memory. + * + * @param[in] handle Handle to the reserved block. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_release_block(sl_memory_reservation_t *handle); + +/***************************************************************************//** + * Dynamically allocates a block reservation handle. + * + * @param[out] handle Handle to the reserved block. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_reservation_handle_alloc(sl_memory_reservation_t **handle); + +/***************************************************************************//** + * Frees a dynamically allocated block reservation handle. + * + * @param[in] handle Handle to the reserved block. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_reservation_handle_free(sl_memory_reservation_t *handle); + +/***************************************************************************//** + * Gets the size of the memory reservation handle structure. + * + * @return Memory reservation handle structure's size in bytes. + ******************************************************************************/ +uint32_t sl_memory_reservation_handle_get_size(void); + +/***************************************************************************//** + * Creates a memory pool. + * + * @param[in] block_size Size of each block, in bytes. + * @param[in] block_count Number of blocks in the pool. + * @param[in] pool_handle Handle to the memory pool. + * + * @note This function assumes the 'pool_handle' is provided by the caller: + * - either statically (e.g. as a global variable) + * - or dynamically by calling sl_memory_pool_handle_alloc(). + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_create_pool(size_t block_size, + uint32_t block_count, + sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Deletes a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note All pool allocations need to be freed by calling sl_memory_pool_free() + * on each block before calling sl_memory_delete_pool(). + * + * @note The pool_handle provided is neither freed or invalidated. It can be + * reused in a new call to sl_memory_create_pool() to create another pool. + ******************************************************************************/ +sl_status_t sl_memory_delete_pool(sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Allocates a block from a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * @param[out] block Pointer to a variable that will receive the address + * of the allocated block. NULL in case of error + * condition. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, + void **block); + +/***************************************************************************//** + * Frees a block from a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * @param[in] block Pointer to the block to free. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, + void *block); + +/***************************************************************************//** + * Dynamically allocates a memory pool handle. + * + * @param[out] pool_handle Handle to the memory pool. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_alloc(sl_memory_pool_t **pool_handle); + +/***************************************************************************//** + * Frees a dynamically allocated memory pool handle. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Gets the size of the memory pool handle structure. + * + * @return Memory pool handle structure's size. + ******************************************************************************/ +uint32_t sl_memory_pool_handle_get_size(void); + +/***************************************************************************//** + * Gets the total count of blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Total number of blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_total_block_count(const sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Gets the count of free blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Number of free blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_free_block_count(const sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Gets the count of used blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Number of used blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_used_block_count(const sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Populates an sl_memory_heap_info_t{} structure with the current status of + * the heap. + * + * @param[in] heap_info Pointer to structure that will receive further heap + * information data. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_memory_get_heap_info(sl_memory_heap_info_t *heap_info); + +/***************************************************************************//** + * Gets the total size of the heap. + * + * @return Heap's size in bytes. + ******************************************************************************/ +size_t sl_memory_get_total_heap_size(void); + +/***************************************************************************//** + * Gets the current free heap size. + * + * @return Free heap size in bytes. + ******************************************************************************/ +size_t sl_memory_get_free_heap_size(void); + +/***************************************************************************//** + * Gets the current used heap size. + * + * @return Used heap size in bytes. + ******************************************************************************/ +size_t sl_memory_get_used_heap_size(void); + +/***************************************************************************//** + * Gets heap high watermark. + * + * @return Highest heap usage in bytes recorded. + ******************************************************************************/ +size_t sl_memory_get_heap_high_watermark(void); + +/***************************************************************************//** + * Reset heap high watermark to the current heap used. + ******************************************************************************/ +void sl_memory_reset_heap_high_watermark(void); + +/** @} (end addtogroup memory_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_MEMORY_MANAGER_H_ */ diff --git a/Libs/platform/service/memory_manager/inc/sl_memory_manager_region.h b/Libs/platform/service/memory_manager/inc/sl_memory_manager_region.h new file mode 100644 index 0000000..132105d --- /dev/null +++ b/Libs/platform/service/memory_manager/inc/sl_memory_manager_region.h @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file + * @brief Getters for Heap and stack. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MEMORY_MANAGER_REGION_H_ +#define SL_MEMORY_MANAGER_REGION_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup memory_manager Memory Manager + * @{ + ******************************************************************************/ + +// ---------------------------------------------------------------------------- +// DATA TYPES + +/// @brief Memory region structure. +typedef struct sl_memory_region_t { + void * addr; ///< Pointer to the beginning of the memory region. Can be NULL. + size_t size; ///< Size of this memory region. +} sl_memory_region_t; + +// ---------------------------------------------------------------------------- +// PROTOTYPES + +/***************************************************************************//** + * Gets size and location of the stack. + * + * @return description of the region reserved for the C stack. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_stack_region(void); + +/***************************************************************************//** + * Gets size and location of the heap. + * + * @return description of the region reserved for the C heap. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_heap_region(void); + +/** @} end addtogroup memory_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_MEMORY_MANAGER_REGION_H_ */ diff --git a/Libs/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h b/Libs/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h new file mode 100644 index 0000000..6e1d06c --- /dev/null +++ b/Libs/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h @@ -0,0 +1,631 @@ +/***************************************************************************//** + * @file + * @brief Macros and functions for memory profiling + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MEMORY_PROFILER_H +#define SLI_MEMORY_PROFILER_H + +#include +#include +#include +#include "sl_status.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) + +// The component catalog is present, so we're in an application build and can +// check if the Memory Profiler is present +#include "sl_component_catalog.h" +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +// The Memory Profiler is present. Use its configuration and enable profiling. +#include "sli_memory_profiler_config.h" +#define SLI_MEMORY_PROFILER_ENABLE_PROFILING 1 +#else +// The Memory Profiler is not present. Disable profiling. +#define SLI_MEMORY_PROFILER_ENABLE_PROFILING 0 +#endif // defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + +#else // defined(SL_COMPONENT_CATALOG_PRESENT) + +// The component catalog is not present, so we're in a library build. The build +// environment of the library must specify the configuration defines that affect +// the macros in this header if it wants a non-default configuration. We default +// to enabling basic profiling but disabling ownership tracking. +#if !defined(SLI_MEMORY_PROFILER_ENABLE_PROFILING) +#define SLI_MEMORY_PROFILER_ENABLE_PROFILING 1 +#endif + +#if !defined(SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING) +#define SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING 0 +#endif + +#endif // defined(SL_COMPONENT_CATALOG_PRESENT) + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup memory_profiler Memory Profiler + * @{ + * + * @brief Memory profiler for tracking and reporting system RAM usage + * + * This memory profiler component provides a tool for tracking and reporting of + * system RAM usage. It is implemented as a combination of a simple component + * running in the Device Under Test (DUT) and a Python script running on a + * computer. The on-DUT component is a relatively thin layer that uses J-Link + * RTT (Real Time Transfer) to output events about memory allocation on the + * device. The Python script on the computer receives these events and maintains + * the memory usage bookkeeping. The script is available in + * `platform/service/memory_manager/profiler/scripts/memory_profiler_platform.py`. + * + * The memory profiler represents memory in a hierarchical structure with the + * physical RAM as the root of the tree. The physical RAM is split into + * allocations such as stack and heap, and the heap is further split into + * allocations for different uses of memory. + * + * Each node in the tree is represented by one instance of a memory tracker. + * Each tracker has a short description and records the current and peak number + * of bytes allocated. Leaves in the tree represent concrete uses of RAM, for + * example allocations of a particular object types in a wireless stack. + * Intermediate nodes typically correspond to memory allocation abstractions, + * such as memory pools or helper functions that are used by the concrete users + * of memory. + * + * The trackers can represent two different types of allocation behavior: + * + * 1. Pool trackers represent memory abstractions that make one contiguous + * allocation from their parent memory to allocate a pool. Portions of that + * pool are then given to callers that allocate memory from the pool + * abstraction. The Memory Manager (MM) heap is one example of such a + * pool. The MM heap reserves some portion of the physical RAM at + * initialization time and gives portions of that pool to its callers. + * Another example of a pool tracker are the individual pools that can be + * created and deleted at runtime using the MM Pool API. Each pool is + * associated with a pool tracker to track the allocation and freeing of the + * pool items during the lifetime of the pool. + * + * 2. Trackers that are not pools are used to collect the allocation statistics + * of a certain type of allocation or use case so that the memory use of that + * particular type can be easily distinguished from all the other users of + * memory. For example, the Memory Manager creates a separate tracker + * for long-term heap allocations, short-term heap allocations, and heap + * reservations, so that these can be counted individually. Components such + * as wireless stacks may create their own trackers for tracking things like + * the total sum of allocations made by a particular component, or more + * granularly the allocations made for a particular type of a resource. + * + * The Memory Manager is integrated to the Memory Profiler and all + * allocations from the heap are automatically tracked by the top-level trackers + * for the heap. This provides the usage tracking for the heap as a whole, i.e. + * how many bytes of heap are used in total. If a component or an application + * wants to track how many bytes it has allocated from the heap, it can create a + * new memory profiler tracker. Pool memory trackers are created with a call to + * `sli_memory_profiler_create_pool_tracker()` and other trackers are created + * with `sli_memory_profiler_create_tracker()`. + * + * Both types of trackers are identified by a handle of type + * `sli_memory_tracker_handle_t`, which is just a void pointer that is provided + * by the code that creates the tracker. Code that creates a tracker can use any + * void pointer that is guaranteed to be unique among all trackers for the + * duration of the tracker lifetime, i.e. until the tracker is deleted with a + * call to `sli_memory_profiler_delete_tracker()`. A good approach is to use a + * pointer that is tightly associated with the tracked object or use case. For + * example, a tracker for a memory pool can use the pool handle as the tracker + * handle. A function that wants to track the allocations it makes can use its + * own function pointer as the tracker handle. + * + * Top-level trackers for the heap are created at platform initialization time + * and are never deleted. Other trackers have the same lifetime as the entity or + * component that is being tracked. For example, when a memory pool is created, + * a tracker is created for the pool. When the pool is deleted, the tracker is + * also deleted. Similarly if a component creates a tracker for its memory use + * when the component is initialized or started, the component would typically + * delete the tracker for its memory when the component is de-initialized or + * stopped. Trackers are deleted with a call to + * `sli_memory_profiler_delete_tracker()`. + * + * The memory profiler implementation aims to minimize the impact of the memory + * profiler calls on both RAM and CPU usage when the profiling is not enabled by + * including the component in the SW configuration. To keep the calling code + * clean of conditional compilation but still allow completely removing the + * tracking calls when the profiler is not used, the calling code is encouraged + * to do the tracking via the macros such as @ref + * SLI_MEMORY_PROFILER_TRACK_ALLOC() and @ref SLI_MEMORY_PROFILER_TRACK_FREE(). + * These macros will automatically expand to empty when the profiling is + * disabled at build time. + * + * If a component is compiled into a library (as opposed to being compiled at + * application build time), the library may contain calls to the Memory Profiler + * API even if tracking will be disabled in the application. In this case the SW + * is linked with a stub Memory Profiler API implementation that provides dummy + * functions. The stub implementation does not use any RAM or RTT, so the + * overhead is minimized. + * + * Trackers use @ref SLI_MEMORY_PROFILER_TRACK_ALLOC() to track the allocation of + * memory blocks and include the bytes of RAM to the counts in the trackers. To + * make sure that any arbitrary pointer can be correctly mapped to the + * allocation it belongs to, every tracker must accurately track the pointer and + * size of the memory block that they are operating with. As an example, when an + * allocation from the MM heap is made, the MM heap implementation tracks the + * full allocation RAM block including any extra metadata or size padding that + * is used around the block returned to the caller. The caller will track the + * allocation using the size it requested from the heap (which is smaller than + * the full block needed to satisfy the allocation), and the pointer it received + * from the heap (which is within the full block allocated from the RAM). + * + * Trackers use @ref SLI_MEMORY_PROFILER_TRACK_FREE() to mark the freeing of a + * memory block. Here too the callers must accurately identify the freed block + * by providing the same pointer they provided in the corresponding call to + * track the allocation. The tracking of the free does not need to be fully + * symmetric, though. As an example, assume that an app has created the tracker + * `app_mallocs` and is using @ref SLI_MEMORY_PROFILER_TRACK_ALLOC() to track on + * that tracker every block it received from @ref sl_malloc(). When the + * application calls @ef sl_free() to free a memory block, the application does + * not need to call @ref SLI_MEMORY_PROFILER_TRACK_FREE() to mark the freeing. + * The MM heap will track the freeing in `sl_free()` and the freeing of the + * memory is automatically counted in the `app_mallocs` tracker as well. + * + ******************************************************************************/ + +/** + * @brief Memory tracker handle type + */ +typedef const void* sli_memory_tracker_handle_t; + +/** + * @brief Value used to indicate an invalid memory tracker handle + */ +#define SLI_INVALID_MEMORY_TRACKER_HANDLE ((sli_memory_tracker_handle_t) NULL) + +/** + * @brief Initialize the memory profiler + * + * Memory Profiler initialization is handled internally by the Platform + * initialization. Applications do not need to and should not call this function + * directly. + */ +void sli_memory_profiler_init(); + +/** + * @brief Get the current program counter + * + * This helper can be used to obtain the current program counter when invoking + * @ref SLI_MEMORY_PROFILER_TRACK_OWNERSHIP() with the intention of assigning + * the ownership to the location that is invoking the tracking macro. + * + * @return Current program counter + */ +#if defined(__GNUC__) +__attribute__( (always_inline) ) static inline void * sli_memory_profiler_get_pc(void) +{ + void *pc; + __asm volatile ("MOV %0, PC" : "=r" (pc)); + return pc; +} +#elif defined(__IAR_SYSTEMS_ICC__) +_Pragma("inline=forced") static inline void * sli_memory_profiler_get_pc(void) +{ + void *pc; + __asm volatile ("MOV %0, PC" : "=r" (pc)); + return pc; +} +#else +static inline void * sli_memory_profiler_get_pc(void) +{ + // Memory Profiler supports ownership tracking only with the GCC or IAR compiler + return NULL; +} +#endif + +/** + * @brief Get the return address of the current function + * + * This helper can be used to obtain the return address of the current function + * when invoking @ref SLI_MEMORY_PROFILER_TRACK_OWNERSHIP() with the intention + * of assigning the ownership to the location that made the call to the function + * that is invoking the tracking macro. + * + * Note that the IAR compiler does not provide a mechanism to reliably obtain + * the return address, so we must emulate that by taking the content of the link + * register. This is never completely reliable, but is guaranteed to fail if + * `sli_memory_profiler_get_return_address()` is used in a function after calls + * to other functions have already been made. Therefore this function should + * always be called right at the beginning of the function that wants to know + * the return address. + * + * @return The return address of the current function + */ +#if defined(__GNUC__) +__attribute__( (always_inline) ) static inline void * sli_memory_profiler_get_return_address(void) +{ + return __builtin_extract_return_addr(__builtin_return_address(0)); +} +#elif defined(__IAR_SYSTEMS_ICC__) +_Pragma("inline=forced") static inline void * sli_memory_profiler_get_return_address(void) +{ + uint32_t lr; + lr = __get_LR(); + return (void *)lr; +} +#else +static inline void * sli_memory_profiler_get_return_address(void) +{ + // Memory Profiler supports ownership tracking only with the GCC or IAR compiler + return NULL; +} +#endif + +/** + * @brief Create a pool memory tracker + * + * This function creates a memory tracker for a memory use case that allocates + * one fixed-size pool from some allocator and then allocates portions of the + * pool to its own clients. + * + * The memory block specified by @p pointer and @p size must match a memory + * allocation that the pool implementation has successfully obtained from some + * memory allocator that has tracked the allocation. If the pool implementation + * later frees the pool memory block (for example when the component that uses + * the pool is de-initialized), the pool implementation must delete the pool + * tracker with a call to @ref sli_memory_profiler_delete_tracker before it + * frees the memory block that the pool was using. + * + * @param[in] tracker_handle The handle to identify the tracker. The handle must + * remain unique among all trackers until the tracker is deleted with @ref + * sli_memory_profiler_delete_tracker. + * @param[in] description Short description of the usage of the tracker memory, + * or NULL to omit the description. The description can be set or updated + * later with a call to @ref sli_memory_profiler_describe_tracker. + * @param[in] ptr Pointer to the pool block allocated from the parent memory + * @param[in] size The size of the pool block allocated from the parent memory + * + * @return SL_STATUS_OK if a tracker was created, SL_STATUS_NOT_AVAILABLE if the + * Memory Profiler is not included in the application. + */ +sl_status_t sli_memory_profiler_create_pool_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description, + void* ptr, + size_t size); + +/** + * @brief Create a memory tracker + * + * This function creates a memory tracker for a use case that allocates blocks + * from tracked parent allocator. + * + * @param[in] tracker_handle The handle to identify the tracker. The handle must + * remain unique among all trackers until the tracker is deleted with @ref + * sli_memory_profiler_delete_tracker. + * @param[in] description Short description of the usage of the tracker memory, + * or NULL to omit the description. The description can be set or updated + * later with a call to @ref sli_memory_profiler_describe_tracker. + * + * @return SL_STATUS_OK if a tracker was created, SL_STATUS_NOT_AVAILABLE if the + * Memory Profiler is not included in the application. + */ +sl_status_t sli_memory_profiler_create_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description); + +/** + * @brief Add or update a description to a previously created memory tracker + * + * This function is typically used to assign a description to a tracker that has + * been created by a lower layer that does not know the use case of the memory. + * For example, when the Memory Manager creates a memory pool object, it + * creates a Memory Profiler tracker with the same handle as the pool handle but + * cannot assign a descriptive name, as it cannot know what the pool is used + * for. The caller that created the pool can then use this function with the + * pool handle to assign a description for the pool memory. + * + * @param[in] tracker_handle The handle of the memory tracker + * @param[in] description Short description of the usage of the tracker memory, + * or NULL to clear the description. + */ +void sli_memory_profiler_describe_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description); + +/** + * @brief Delete a memory tracker + * + * This function deletes a previously created memory tracker. + * + * @param[in] tracker_handle The handle of the memory tracker + */ +void sli_memory_profiler_delete_tracker(sli_memory_tracker_handle_t tracker_handle); + +/** + * @brief Track the allocation of a memory block + * + * NOTE: This function is intended to be called via the @ref + * SLI_MEMORY_PROFILER_TRACK_ALLOC() macro. + * + * @param[in] tracker_handle The handle of the memory tracker + * @param[in] ptr Pointer to the allocated memory or NULL if allocation failed + * @param[in] size The number of bytes allocated, or attempted to allocate + */ +void sli_memory_profiler_track_alloc(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + size_t size); + +/** + * @brief Track the reallocation of a previously allocated memory block + * + * NOTE: This function is intended to be called via the @ref + * SLI_MEMORY_PROFILER_TRACK_REALLOC() macro. + * + * NOTE: Reallocation is a special operation that is intended to be tracked only + * by the underlying heap allocator in the Memory Manager. Any + * higher-level allocations that are tracked within the reallocated block are + * automatically moved and resized without any tracking calls from the + * higher-level trackers. + * + * If the realloc operation involves allocating a new block and freeing the + * previous block, the Memory Manager heap must track the realloc when + * the allocation of the new memory has been tracked but the old memory block + * has not been freed yet. This is needed to guarantee that both @p ptr and @p + * realloced_ptr are valid and owned by the calling thread when the realloc is + * tracked. + * + * @param[in] tracker_handle The handle of the lowest-layer heap memory tracker + * @param[in] ptr Pointer to the original memory block + * @param[in] realloced_ptr Pointer to the resized or allocated memory + * @param[in] size The size that the block was reallocated to + */ +void sli_memory_profiler_track_realloc(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + void * realloced_ptr, + size_t size); + +/** + * @brief Track the allocation of a memory block and record ownership + * + * NOTE: This function is intended to be called via the @ref + * SLI_MEMORY_PROFILER_TRACK_ALLOC_WITH_OWNERSHIP() macro. + * + * @param[in] tracker_handle The handle of the memory tracker + * @param[in] ptr Pointer to the allocated memory or NULL if allocation failed + * @param[in] size The number of bytes allocated, or attempted to allocate + * @param[in] pc The program counter at the location of the allocation + */ +void sli_memory_profiler_track_alloc_with_ownership(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + size_t size, + void * pc); + +/** + * @brief Track the freeing of a memory block + * + * NOTE: This function is intended to be called via the + * @ref SLI_MEMORY_PROFILER_TRACK_FREE() macro. + * + * @param[in] tracker_handle The handle of the memory tracker + * @param[in] ptr Pointer to the allocated memory + */ +void sli_memory_profiler_track_free(sli_memory_tracker_handle_t tracker_handle, + void * ptr); + +/** + * @brief Track the transfer of memory allocation ownership + * + * NOTE: This function is intended to be called via @ref + * SLI_MEMORY_PROFILER_TRACK_OWNERSHIP() or @ref + * SLI_MEMORY_PROFILER_TRACK_OWNERSHIP_ON_TRACKER() macros. + * + * @param[in] tracker_handle Handle of the tracker level at which the ownership + * is taken. This is used to disambiguate in cases where nested allocations + * start at the same memory location, and the caller is specifically taking + * ownership of one of the outer blocks that may contain smaller allocations + * that have their own (more detailed) owners. If set to + * `SLI_INVALID_MEMORY_TRACKER_HANDLE`, the ownership of the innermost + * allocation is taken. + * @param[in] ptr Pointer to the allocated memory for which ownership is taken. + * The caller may pass a NULL pointer to indicate that the location pointer to + * be @p pc has failed to obtain a valid pointer, for example because a memory + * allocation that was meant to provide the pointer has failed. + * @param[in] pc The program counter at the location that took ownership + */ +void sli_memory_profiler_track_ownership(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + void * pc); + +/** + * @brief Trigger the creation of a snapshot of the current state + * + * This function can be used by the device to trigger the analysis software on + * the PC or Mac to take a snapshot of the current state of the allocation + * bookkeeping. This would typically be used by test cases that communicate with + * the device under test and want to synchronously record the state of the + * allocations at a known point in the test sequence. + * + * @param[in] name Short name for the snapshot that is being created. The name + * is immediately sent in the RTT event to the analysis software and does not + * need to be retained in the device. + */ +void sli_memory_profiler_take_snapshot(const char *name); + +/** + * @brief Output a generic log event in the RTT event stream + * + * This function is meant to be used for temporary debugging purposes only. When + * debugging a memory leak requires visibility to software actions other than + * memory allocation or free, calls to this generic logging mechanism can be + * added so that the sequence of software events can be seen with respect to the + * allocation and free events that are visible in the normal Memory Profiler + * events. + * + * @param[in] log_id Numeric identifier of this log event. This is passed in the + * RTT event to the analysis tool and the ID appears in the log produced by + * the analyzer but the value is not otherwise used by the Memory Profiler. It + * is the responsibility of the caller to use values that are sufficiently + * unique that the developer can identify the logs. + * + * @param[in] arg1 Arbitrary 32-bit argument that's relevant for the developer + * + * @param[in] arg2 Arbitrary 32-bit argument that's relevant for the developer + * + * @param[in] arg3 Arbitrary 32-bit argument that's relevant for the developer + * + * @param[in] pc The program counter at the location of the log call + */ +void sli_memory_profiler_log(uint32_t log_id, + uint32_t arg1, + uint32_t arg2, + uint32_t arg3, + void * pc); + +// The macros expand to their full content only when profiling is included +#if SLI_MEMORY_PROFILER_ENABLE_PROFILING + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_alloc + */ +#define SLI_MEMORY_PROFILER_TRACK_ALLOC(tracker_handle, ptr, size) \ + do { \ + sli_memory_profiler_track_alloc((tracker_handle), (ptr), (size)); \ + } while (0) + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_alloc_with_ownership + * + * If ownership tracking is disabled at build time, the macro reduces to normal + * tracking without ownership. + */ +#if SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING +#define SLI_MEMORY_PROFILER_TRACK_ALLOC_WITH_OWNERSHIP(tracker_handle, ptr, size, pc) \ + do { \ + void * volatile _pc = (pc); \ + sli_memory_profiler_track_alloc_with_ownership((tracker_handle), (ptr), (size), _pc); \ + } while (0) +#else // SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING +#define SLI_MEMORY_PROFILER_TRACK_ALLOC_WITH_OWNERSHIP(tracker_handle, ptr, size, pc) \ + do { \ + (void) (pc); \ + sli_memory_profiler_track_alloc((tracker_handle), (ptr), (size)); \ + } while (0) +#endif // SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_realloc + */ +#define SLI_MEMORY_PROFILER_TRACK_REALLOC(tracker_handle, ptr, realloced_ptr, size) \ + do { \ + sli_memory_profiler_track_realloc((tracker_handle), (ptr), (realloced_ptr), (size)); \ + } while (0) + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_free + */ +#define SLI_MEMORY_PROFILER_TRACK_FREE(tracker_handle, ptr) \ + do { \ + sli_memory_profiler_track_free((tracker_handle), (ptr)); \ + } while (0) + +#else // SLI_MEMORY_PROFILER_ENABLE_PROFILING + +// Empty implementation of tracking macros when memory profiling calls are +// excluded at build time +#define SLI_MEMORY_PROFILER_TRACK_ALLOC(tracker_handle, ptr, size) \ + do { \ + (void) (tracker_handle); \ + (void) (ptr); \ + (void) (size); \ + } while (0) + +#define SLI_MEMORY_PROFILER_TRACK_ALLOC_WITH_OWNERSHIP(tracker_handle, ptr, size, pc) \ + do { \ + (void) (tracker_handle); \ + (void) (ptr); \ + (void) (size); \ + (void) (pc); \ + } while (0) + +#define SLI_MEMORY_PROFILER_TRACK_REALLOC(tracker_handle, ptr, realloced_ptr, size) \ + do { \ + (void) (tracker_handle); \ + (void) (ptr); \ + (void) (realloced_ptr); \ + (void) (size); \ + } while (0) + +#define SLI_MEMORY_PROFILER_TRACK_FREE(tracker_handle, ptr) \ + do { \ + (void) (tracker_handle); \ + (void) (ptr); \ + } while (0) + +#endif // SLI_MEMORY_PROFILER_ENABLE_PROFILING + +// Ownership tracking calls are included based on dedicated configuration +#if SLI_MEMORY_PROFILER_ENABLE_PROFILING && SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_ownership + */ +#define SLI_MEMORY_PROFILER_TRACK_OWNERSHIP(ptr, pc) \ + do { \ + void * volatile _pc = (pc); \ + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, (ptr), _pc); \ + } while (0) + +/** + * @brief Macro to wrap calls to @ref sli_memory_profiler_track_ownership + */ +#define SLI_MEMORY_PROFILER_TRACK_OWNERSHIP_ON_TRACKER(tracker_handle, ptr, pc) \ + do { \ + void * volatile _pc = (pc); \ + sli_memory_profiler_track_ownership((tracker_handle), (ptr), _pc); \ + } while (0) + +#else // SLI_MEMORY_PROFILER_ENABLE_PROFILING && SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING + +#define SLI_MEMORY_PROFILER_TRACK_OWNERSHIP(ptr, pc) \ + do { \ + (void) (ptr); \ + (void) (pc); \ + } while (0) + +#define SLI_MEMORY_PROFILER_TRACK_OWNERSHIP_ON_TRACKER(tracker_handle, ptr, pc) \ + do { \ + (void) (tracker_handle); \ + (void) (ptr); \ + (void) (pc); \ + } while (0) + +#endif // SLI_MEMORY_PROFILER_ENABLE_PROFILING && SLI_MEMORY_PROFILER_ENABLE_OWNERSHIP_TRACKING + +/** @} end memory_profiler */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MEMORY_PROFILER_H diff --git a/Libs/platform/service/memory_manager/profiler/src/sli_memory_profiler_stubs.c b/Libs/platform/service/memory_manager/profiler/src/sli_memory_profiler_stubs.c new file mode 100644 index 0000000..32e69f4 --- /dev/null +++ b/Libs/platform/service/memory_manager/profiler/src/sli_memory_profiler_stubs.c @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file + * @brief Stub implementation of memory profiler + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_memory_profiler.h" +#include "sl_status.h" + +/* Create a memory tracker */ +sl_status_t sli_memory_profiler_create_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description) + +{ + (void) tracker_handle; + (void) description; + return SL_STATUS_NOT_AVAILABLE; +} + +/* Create a pool memory tracker */ +sl_status_t sli_memory_profiler_create_pool_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description, + void* ptr, + size_t size) +{ + (void) tracker_handle; + (void) description; + (void) ptr; + (void) size; + return SL_STATUS_NOT_AVAILABLE; +} + +/* Add or update a description to a previously created memory tracker */ +void sli_memory_profiler_describe_tracker(sli_memory_tracker_handle_t tracker_handle, + const char *description) +{ + (void) tracker_handle; + (void) description; +} + +/* Delete a memory tracker */ +void sli_memory_profiler_delete_tracker(sli_memory_tracker_handle_t tracker_handle) +{ + (void) tracker_handle; +} + +/* Track the allocation of a memory block */ +void sli_memory_profiler_track_alloc(sli_memory_tracker_handle_t tracker_handle, void * ptr, size_t size) +{ + (void) tracker_handle; + (void) ptr; + (void) size; +} + +/* Track the allocation of a memory block and record ownership */ +void sli_memory_profiler_track_alloc_with_ownership(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + size_t size, + void * pc) +{ + (void) tracker_handle; + (void) ptr; + (void) size; + (void) pc; +} + +/* Track the freeing of a memory block */ +void sli_memory_profiler_track_free(sli_memory_tracker_handle_t tracker_handle, void * ptr) +{ + (void) tracker_handle; + (void) ptr; +} + +/* Track the transfer of memory allocation ownership */ +void sli_memory_profiler_track_ownership(sli_memory_tracker_handle_t tracker_handle, + void * ptr, + void * pc) +{ + (void) tracker_handle; + (void) ptr; + (void) pc; +} + +/* Trigger the creation of a snapshot of the current state */ +void sli_memory_profiler_take_snapshot(const char *name) +{ + (void) name; +} + +/* Send a generic log */ +void sli_memory_profiler_log(uint32_t log_id, + uint32_t arg1, + uint32_t arg2, + uint32_t arg3, + void * pc) +{ + (void) log_id; + (void) arg1; + (void) arg2; + (void) arg3; + (void) pc; +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager.c b/Libs/platform/service/memory_manager/src/sl_memory_manager.c new file mode 100644 index 0000000..9a09ff3 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager.c @@ -0,0 +1,1200 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver Implementation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "sl_memory_manager_config.h" +#include "sl_memory_manager.h" +#include "sli_memory_manager.h" +#include "sl_assert.h" +#include "sl_bit.h" +#include "sl_common.h" +#include "sl_core.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "em_device.h" // For SRAM_BASE and SRAM_SIZE +#include "sli_memory_profiler.h" + +// Names for the top-level Memory Profiler trackers provided by the Common +// Memory Manager. The name string pointers are also used as the tracker +// handles. Heap and reservation names are shared with other files. +static const char sli_mm_ram_name[] = "Physical RAM"; +static const char sli_mm_stack_name[] = "C stack"; +const char sli_mm_heap_name[] = "MM Heap"; +const char sli_mm_heap_reservation_name[] = "MM reservation"; +static const char sli_mm_heap_malloc_lt_name[] = "MM malloc LT"; +static const char sli_mm_heap_malloc_st_name[] = "MM malloc ST"; +#endif + +#if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) +#include "SEGGER_SYSVIEW.h" +extern char __HeapBase[]; +extern char __HeapLimit[]; + +#define HEAP_SIZE (__HeapLimit - __HeapBase) + +// Heap ID for SystemView heap definitions. +// These values are chosen to be bigger than SEGGER_SYSVIEW_ID_BASE. +#define HEAP_LT_ID 0xFFFFFFFF +#define HEAP_ST_ID 0xFFFFFFFE + +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +extern sli_block_metadata_t *sli_free_lt_list_head; +extern sli_block_metadata_t *sli_free_st_list_head; +extern uint32_t sli_free_blocks_number; +static size_t heap_used_size; +static size_t heap_high_watermark; +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) +bool reserve_no_retention_first = true; +#endif + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +static sli_block_metadata_t *memory_manage_data_alignment(sli_block_metadata_t *current_block_metadata, + size_t block_align); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes the memory manager. + * + * @note (1) Calling this function multiple times will result in an unexpected + * behavior as the heap layout will be corrupted. + ******************************************************************************/ +sl_status_t sl_memory_init(void) +{ + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + sli_free_blocks_number = 0u; + heap_used_size = 0u; + heap_high_watermark = 0u; + + // At first, all general purpose heap available to long-term/short-term blocks. + sli_free_lt_list_head = (sli_block_metadata_t *)heap_region.addr; + sli_free_st_list_head = sli_free_lt_list_head; + + // First free block is entire heap size, minus one metadata block area. + // Long-term and short-term list initialized with the same free block. + sli_memory_metadata_init(sli_free_lt_list_head); + sli_free_lt_list_head->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(heap_region.size - SLI_BLOCK_METADATA_SIZE_BYTE); + sli_free_blocks_number++; + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + // Create the pool tracker for the physical RAM + sli_memory_profiler_create_pool_tracker(sli_mm_ram_name, + sli_mm_ram_name, + (void*) (uintptr_t) SRAM_BASE, + SRAM_SIZE); + + // Record the allocation of the stack from the physical RAM + sl_memory_region_t stack_region = sl_memory_get_stack_region(); + sli_memory_profiler_track_alloc(sli_mm_ram_name, + stack_region.addr, + stack_region.size); + + // Record the creation of the pool tracker for the stack + sli_memory_profiler_create_pool_tracker(sli_mm_stack_name, + sli_mm_stack_name, + stack_region.addr, + stack_region.size); + + // Record the allocation of the heap from the physical RAM + sli_memory_profiler_track_alloc(sli_mm_ram_name, + heap_region.addr, + heap_region.size); + + // Record the creation of the pool tracker for the heap + sli_memory_profiler_create_pool_tracker(sli_mm_heap_name, + sli_mm_heap_name, + heap_region.addr, + heap_region.size); + + // Create the malloc family of trackers + sli_memory_profiler_create_tracker(sli_mm_heap_malloc_lt_name, + sli_mm_heap_malloc_lt_name); + sli_memory_profiler_create_tracker(sli_mm_heap_malloc_st_name, + sli_mm_heap_malloc_st_name); + + // Create the reservation tracker + sli_memory_profiler_create_tracker(sli_mm_heap_reservation_name, + sli_mm_heap_reservation_name); +#endif + +#if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) + SEGGER_SYSVIEW_HeapDefine((void*)HEAP_LT_ID, (void*)__HeapBase, HEAP_SIZE, SLI_BLOCK_METADATA_SIZE_BYTE); + SEGGER_SYSVIEW_HeapDefine((void*)HEAP_ST_ID, (void*)__HeapBase, HEAP_SIZE, SLI_BLOCK_METADATA_SIZE_BYTE); + SEGGER_SYSVIEW_NameResource((uint32_t) HEAP_LT_ID, "HEAP LONG TERM"); + SEGGER_SYSVIEW_NameResource((uint32_t) HEAP_ST_ID, "HEAP SHORT TERM"); +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Reserves a memory block that will never need retention in EM2. + * + * @note (1) A first check is done to verify the heap has enough space for the + * requested size. This first check is not enough in case there is an + * alignment adjustment done thereafter. A second check is done to + * ensure the remaining size is enough to accommodate the requested + * size in case of alignment adjustment. + ******************************************************************************/ +sl_status_t sl_memory_reserve_no_retention(size_t size, + size_t align, + void **block) +{ + // Check proper alignment characteristics. + EFM_ASSERT((align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) + || (SL_MATH_IS_PWR2(align) + && (align <= SL_MEMORY_BLOCK_ALIGN_512_BYTES))); + + // Assert block reservation with retention is done prior to any other allocations types. +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + EFM_ASSERT(reserve_no_retention_first == true); +#endif + + size_t block_align = align; + void *data_payload_start = NULL; + size_t block_size_remaining; + size_t size_real; + sl_status_t status; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block reserved yet. + + if ((size == 0) || (size >= heap_region.size)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Adjust size to match the minimum alignment to maximize CPU access performance. + size_real = SLI_ALIGN_ROUND_UP(size, SLI_BLOCK_ALLOC_MIN_ALIGN); + + // Adjust alignment. + if ((block_align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) || (block_align <= 4U)) { + block_align = SLI_BLOCK_ALLOC_MIN_ALIGN; + } + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + block_size_remaining = SLI_BLOCK_LEN_DWORD_TO_BYTE(sli_free_st_list_head->length); + // Verify there is enough space in heap. + if (block_size_remaining >= size_real) { + // Get aligned block: get address from end of available heap minus the requested size. Round down this address. + *block = (void *)(((uint64_t *)sli_free_st_list_head + (sli_free_st_list_head->length + SLI_BLOCK_METADATA_SIZE_DWORD)) - SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real)); + *block = (void *)SLI_ALIGN_ROUND_DOWN(((uintptr_t)*block), block_align); + + // Update heap start metadata. Available heap size reduced from reserved block size aligned. + data_payload_start = (void *)((uint8_t *)sli_free_st_list_head + SLI_BLOCK_METADATA_SIZE_BYTE); + sli_free_st_list_head->length = (uint16_t)((uint64_t *)*block - (uint64_t *)data_payload_start); + + // Ensure there is still enough space after alignment. See Note #1. + if (block_size_remaining < SLI_BLOCK_LEN_DWORD_TO_BYTE(sli_free_st_list_head->length)) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_ALLOCATION_FAILED; + } + + status = SL_STATUS_OK; + } else { + status = SL_STATUS_ALLOCATION_FAILED; + } + + heap_used_size += size_real; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; + } + + CORE_EXIT_ATOMIC(); + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES + sli_memory_save_reservation_no_retention(*block, size, align); +#endif + + return status; +} + +/***************************************************************************//** + * Allocates a memory block of at least requested size from the heap. Simple + * version. + ******************************************************************************/ +void *sl_malloc(size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *block_avail = NULL; + + (void)sl_memory_alloc_advanced(size, SL_MEMORY_BLOCK_ALIGN_DEFAULT, BLOCK_TYPE_LONG_TERM, &block_avail); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); +#endif + + return block_avail; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory. + ******************************************************************************/ +sl_status_t sl_memory_alloc(size_t size, + sl_memory_block_type_t type, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_status_t status; + + status = sl_memory_alloc_advanced(size, SL_MEMORY_BLOCK_ALIGN_DEFAULT, type, block); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + + return status; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory. Advanced version that allows to + * specify alignment. + * + * @note (1) When splitting a long-term (LT) block, the block part not returned + * to the requester becomes a free block. The new block considered as + * a free block can be either a LT or short-term (ST) block at the + * next allocation. Consequently, the LT and ST head pointers must + * be updated to this new free block start address if it is needed. + ******************************************************************************/ +sl_status_t sl_memory_alloc_advanced(size_t size, + size_t align, + sl_memory_block_type_t type, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + + // Check proper alignment characteristics. + EFM_ASSERT((align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) + || (SL_MATH_IS_PWR2(align) + && (align <= SL_MEMORY_BLOCK_ALIGN_512_BYTES))); + + sli_block_metadata_t *current_block_metadata = NULL; + sli_block_metadata_t *allocated_blk = NULL; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + const sli_block_metadata_t *old_block_metadata = NULL; + size_t current_block_len; + size_t size_real; + size_t size_adjusted; + size_t block_size_remaining; + size_t block_align = (align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) ? SLI_BLOCK_ALLOC_MIN_ALIGN : align; + size_t other_offset; + bool is_aligned = false; +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + reserve_no_retention_first = false; +#endif + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block allocated yet. + + if ((size == 0) || (size >= heap_region.size)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Adjust size to match the minimum alignment to maximize CPU access performance. + size_real = SLI_ALIGN_ROUND_UP(size, SLI_BLOCK_ALLOC_MIN_ALIGN); + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + size_adjusted = sli_memory_find_free_block(size_real, align, type, false, ¤t_block_metadata); + + if ((current_block_metadata == NULL) || (size_adjusted == 0)) { + CORE_EXIT_ATOMIC(); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_name, NULL, size, return_address); +#endif + return SL_STATUS_ALLOCATION_FAILED; + } + + // The adjusted size changes only when the free block isn't aligned. + is_aligned = (size_adjusted == size_real) ? true : false; + + current_block_len = SLI_BLOCK_LEN_DWORD_TO_BYTE(current_block_metadata->length); + block_size_remaining = current_block_len - size_adjusted; + + // Prepare found block. + allocated_blk = current_block_metadata; + + // Update counter of free blocks. + sli_free_blocks_number--; + + // Split allocated block if possible. + if (block_size_remaining >= SLI_BLOCK_ALLOCATION_MIN_SIZE) { + sli_block_metadata_t *new_free_blk; + + if (type == BLOCK_TYPE_LONG_TERM) { + size_t new_free_blk_offset = size_real + SLI_BLOCK_METADATA_SIZE_BYTE; + + // Verify if alignment adjustment is required. + old_block_metadata = current_block_metadata; + if (!is_aligned) { + current_block_metadata = memory_manage_data_alignment(current_block_metadata, block_align); + allocated_blk = current_block_metadata; + } + + // Create a new free block with the adjusted size. + new_free_blk = (sli_block_metadata_t *)((uint8_t *)current_block_metadata + new_free_blk_offset); + sli_memory_metadata_init(new_free_blk); + new_free_blk->length = current_block_metadata->length - (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real + SLI_BLOCK_METADATA_SIZE_BYTE); + + new_free_blk->offset_neighbour_prev = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(new_free_blk_offset); + + if (current_block_metadata->offset_neighbour_next != 0) { + sli_block_metadata_t *old_next_block = (sli_block_metadata_t *)((uint64_t *)current_block_metadata + (current_block_metadata->offset_neighbour_next)); + + // Split block had a next block before the split. Update metadata of new free block + // and the metadata of the next block after the new free block. + new_free_blk->offset_neighbour_next = current_block_metadata->offset_neighbour_next - (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(new_free_blk_offset); + old_next_block->offset_neighbour_prev = new_free_blk->offset_neighbour_next; + } else { + new_free_blk->offset_neighbour_next = 0; // end of heap. + } + + // Initialize final metadata of found block. + allocated_blk->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); + allocated_blk->offset_neighbour_prev = current_block_metadata->offset_neighbour_prev; + allocated_blk->offset_neighbour_next = new_free_blk->offset_neighbour_prev; + + // Update head pointers. See Note #1. + sli_update_free_list_heads(new_free_blk, old_block_metadata, false); + } else { + // Create a new block = allocated block returned to requester. This new block is the nearest to the heap end. + allocated_blk = (sli_block_metadata_t *)((uint8_t *)current_block_metadata + block_size_remaining); + + sli_memory_metadata_init(allocated_blk); + allocated_blk->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_adjusted); + allocated_blk->offset_neighbour_prev = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(block_size_remaining); + + if (current_block_metadata->offset_neighbour_next != 0) { + sli_block_metadata_t *next_blk = (sli_block_metadata_t *)((uint64_t *)current_block_metadata + (current_block_metadata->offset_neighbour_next)); + // Add other offset (in case reservation is used). + other_offset = SLI_BLOCK_LEN_DWORD_TO_BYTE(current_block_metadata->offset_neighbour_next) - current_block_len; + allocated_blk->offset_neighbour_next = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_adjusted + other_offset); + next_blk->offset_neighbour_prev = allocated_blk->offset_neighbour_next; + } else { + allocated_blk->offset_neighbour_next = 0; // end of heap. + } + + // Update original found block which becomes a free block. + new_free_blk = current_block_metadata; + new_free_blk->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(block_size_remaining - SLI_BLOCK_METADATA_SIZE_BYTE); + new_free_blk->offset_neighbour_next = allocated_blk->offset_neighbour_prev; + // new_free_blk->offset_neighbour_prev doesn't change. It points to the right previous block. + + // Data payload alignment for short-term is managed during the first-fit algorithm loop + // at the beginning of this function. + + // When the found block is split for ST, the newly created block becomes the allocated block + // returned to the requester. In that case, the remaining part is already pointed by + // the ST header pointer and is the first free block to consider for the next allocation. + // Thus no need to update the ST header pointer. ST head pointer is always the same when the + // block is split. LT head pointer is left untouched for ST block allocation with split. + } + + allocated_blk->block_in_use = true; + // Account for the split block that is free. + sli_free_blocks_number++; + } else { + // Verify if alignment adjustment is required. + old_block_metadata = allocated_blk; + if (type == BLOCK_TYPE_SHORT_TERM) { + const void *data_payload = (void *)((uint8_t *)allocated_blk + SLI_BLOCK_METADATA_SIZE_BYTE); + is_aligned = SLI_ADDR_IS_ALIGNED(data_payload, block_align); + } + if (!is_aligned) { + allocated_blk = memory_manage_data_alignment(allocated_blk, block_align); + } + + // Initialize final metadata of found block that was not split. + // Other metadata members (length and offsets to previous/next) are already correctly set. + allocated_blk->block_in_use = true; // This setting must be done prior to calling sli_memory_find_head_free_block(). + + // Update head pointers accordingly. + sli_update_free_list_heads(allocated_blk, old_block_metadata, true); + } + + heap_used_size += size_adjusted; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; + } + + CORE_EXIT_ATOMIC(); + + *block = (void *)((uint8_t *)allocated_blk + SLI_BLOCK_METADATA_SIZE_BYTE); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc(sli_mm_heap_name, allocated_blk, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); + if (type == BLOCK_TYPE_LONG_TERM) { + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_malloc_lt_name, *block, size, return_address); + } else if (type == BLOCK_TYPE_SHORT_TERM) { + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_malloc_st_name, *block, size, return_address); + } +#endif + +#if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) + allocated_blk->block_type = type; + uint32_t tag = (uint32_t)__builtin_extract_return_addr(__builtin_return_address(0)); + tag |= type << 31U; + if (type == BLOCK_TYPE_LONG_TERM) { + SEGGER_SYSVIEW_HeapAllocEx((void*)HEAP_LT_ID, *block, size, tag); + } else if (type == BLOCK_TYPE_SHORT_TERM) { + SEGGER_SYSVIEW_HeapAllocEx((void*)HEAP_ST_ID, *block, size, tag); + } +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Frees a previously allocated block back into the heap. Simple version. + ******************************************************************************/ +void sl_free(void *ptr) +{ + (void)sl_memory_free(ptr); +} + +/***************************************************************************//** + * Frees a dynamically allocated block of memory. + * + * @note (1) According to IEEE Std 1003.1-2017 (Open Group Base Specifications + * Issue 7, 2018 edition), if ptr is a null pointer, no action shall + * occur. + * + * @note (2) There is no distinction between long-term (LT) and short-term (ST) + * blocks when freeing. The free operation is the same for both block + * types. Merging adjacent blocks is the same also. The only exception + * is the LT and ST head pointers. They must be updated accordingly + * with the freed block. The freed block can be a LT or ST block at + * the next allocation. + ******************************************************************************/ +sl_status_t sl_memory_free(void *block) +{ + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + + if (block == NULL) { + return SL_STATUS_NULL_POINTER; // See Note #1. + } + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_free(sli_mm_heap_name, ((uint8_t *)block - SLI_BLOCK_METADATA_SIZE_BYTE)); +#endif + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sli_block_metadata_t *current_metadata = (sli_block_metadata_t *)((uint8_t *)block - SLI_BLOCK_METADATA_SIZE_BYTE); + // Ensure the block being freed was in use with a valid length. + if (current_metadata->block_in_use == 0 || current_metadata->length == 0) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_FAIL; + } + + uint16_t total_size_free_block = current_metadata->length + SLI_BLOCK_METADATA_SIZE_DWORD; + sli_block_metadata_t *free_block = current_metadata; + sli_block_metadata_t *next_block = NULL; + + heap_used_size -= SLI_BLOCK_LEN_DWORD_TO_BYTE(current_metadata->length); + + // Update counter with block being freed. + sli_free_blocks_number++; + + // Check if previous block exists and is free. + if (current_metadata->offset_neighbour_prev > 0) { + sli_block_metadata_t *metadata_prev_blk = (sli_block_metadata_t *)((uint64_t *)current_metadata - current_metadata->offset_neighbour_prev); + + // Check that there is no reservation between current block and previous block. + uint32_t reservations_size_prev = metadata_prev_blk->offset_neighbour_next - metadata_prev_blk->length; + + if ((!metadata_prev_blk->block_in_use && !current_metadata->heap_start_align) + && (reservations_size_prev <= SLI_BLOCK_METADATA_SIZE_DWORD)) { + // Merge current block to free with previous adjacent block. + free_block = metadata_prev_blk; + total_size_free_block += metadata_prev_blk->length + SLI_BLOCK_METADATA_SIZE_DWORD; + + // 2 free blocks have been merged, account for 1 free block only. + sli_free_blocks_number--; + } else if (current_metadata->heap_start_align) { + // Special block whose data payload was aligned near heap start. Merge process is special as between + // the heap start and the block metadata, there is a lost zone to be merged. But at heap start, there is + // no valid metadata. A new valid metadata will exist after this special merge. + free_block = metadata_prev_blk; + total_size_free_block += current_metadata->offset_neighbour_prev; + current_metadata->heap_start_align = false; + free_block->offset_neighbour_prev = 0; // heap start. + } // Else previous block is in used, nothing to merge. + } + + // Check if next block exists and is free. + if ((current_metadata->offset_neighbour_next > 0) + && (((size_t)current_metadata + SLI_BLOCK_LEN_DWORD_TO_BYTE(current_metadata->offset_neighbour_next)) < ((size_t)heap_region.addr + heap_region.size))) { + next_block = (sli_block_metadata_t *)((uint64_t *)current_metadata + (current_metadata->offset_neighbour_next)); + + // Check that there is no reservation between current block and next block. + uint32_t reservations_size_next = current_metadata->offset_neighbour_next - current_metadata->length; + + if ((!next_block->block_in_use) && (reservations_size_next <= SLI_BLOCK_METADATA_SIZE_DWORD)) { + // Merge block with next adjacent block. + total_size_free_block += next_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + // Invalidate the next block metadata. + next_block->length = 0; + // Get the "next" block adjacent to the invalidated next block. + next_block = (next_block->offset_neighbour_next == 0) ? NULL : ((sli_block_metadata_t *)((uint64_t *)next_block + (next_block->offset_neighbour_next))); + + // 2 free blocks have been merged, account for 1 free block only. + sli_free_blocks_number--; + } + } + + // Invalidate the block being freed. + current_metadata->block_in_use = 0; + current_metadata->length = 0; + + // Update accordingly the metadata block considered as free. + free_block->length = total_size_free_block - SLI_BLOCK_METADATA_SIZE_DWORD; + free_block->block_in_use = 0; + if (next_block != NULL) { + // Update implicit double linked-list. + free_block->offset_neighbour_next = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD((size_t)next_block - (size_t)free_block); + next_block->offset_neighbour_prev = free_block->offset_neighbour_next; + } else { + free_block->offset_neighbour_next = 0; // Next block is the heap end. + } // free_block->offset_neighbour_prev does not change. + + // Update free list heads. See Note #2. + if (sli_free_lt_list_head == NULL // LT list is empty. Freed block becomes the new 1st element. + || sli_free_lt_list_head > free_block // LT list not empty. Verify if freed block becomes the head. + || sli_free_lt_list_head->length == 0) { + sli_free_lt_list_head = free_block; + } + + if (sli_free_st_list_head == NULL // ST list is empty. Freed block becomes the new 1st element. + || sli_free_st_list_head < free_block // ST list not empty. Verify if freed block becomes the head. + || sli_free_st_list_head->length == 0) { + sli_free_st_list_head = free_block; + } + + CORE_EXIT_ATOMIC(); + +#if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) + if (current_metadata->block_type == BLOCK_TYPE_LONG_TERM) { + SEGGER_SYSVIEW_HeapFree((void*)HEAP_LT_ID, block); + } else if (current_metadata->block_type == BLOCK_TYPE_SHORT_TERM) { + SEGGER_SYSVIEW_HeapFree((void*)HEAP_ST_ID, block); + } +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. Simple version. + ******************************************************************************/ +void *sl_calloc(size_t item_count, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *block_avail = NULL; + + (void)sl_memory_calloc(item_count, size, BLOCK_TYPE_LONG_TERM, &block_avail); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); +#endif + + return block_avail; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. + ******************************************************************************/ +sl_status_t sl_memory_calloc(size_t item_count, + size_t size, + sl_memory_block_type_t type, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + size_t block_size; + sl_status_t status = SL_STATUS_OK; + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block allocated yet. + + if ((size == 0) || (item_count == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Calculate block size to allocate. + block_size = item_count * size; + + // Allocate block. + status = sl_memory_alloc(block_size, type, block); + + if ((status == SL_STATUS_OK) && (*block != NULL)) { + // Clear block to zeros. + memset(*block, 0, block_size); + } + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + + return status; +} + +/***************************************************************************//** + * Resizes a previously allocated memory block. Simple version. + ******************************************************************************/ +void *sl_realloc(void *ptr, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *block_avail = NULL; + + (void)sl_memory_realloc(ptr, size, &block_avail); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + // Realloc to 0 bytes is equivalent to free, so only track ownership when size + // is other than 0 + if (size != 0) { + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); + } +#endif + + return block_avail; +} + +/***************************************************************************//** + * Resizes a previously allocated memory block. + * + * @note (1) If 'ptr' is a null pointer, sl_memory_realloc() is equivalent to + * sl_memory_malloc() for the specified 'size'. + * If 'size' is 0 and 'ptr' points to an existing block of memory, + * sl_memory_realloc() is equivalent to sl_memory_free() and the + * memory block is deallocated. + * + * @note (2) The content of the reallocated memory block is preserved up to + * the lesser of the new and old sizes, even if the block is moved + * to a new location. If the new size is larger, the value of the + * newly allocated portion is indeterminate. + ******************************************************************************/ +sl_status_t sl_memory_realloc(void *ptr, + size_t size, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + sl_status_t status = SL_STATUS_OK; + sli_block_metadata_t *current_block = NULL; + sli_block_metadata_t *next_block = NULL; + size_t current_block_len; + size_t size_real; + uint16_t reservation_offset; + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block allocated yet. + + if (size >= heap_region.size) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((ptr == NULL) && (size == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Manage special parameters values (see Note #1). + if (ptr == NULL) { + status = sl_memory_alloc(size, BLOCK_TYPE_LONG_TERM, block); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + return status; + } else if (size == 0) { + status = sl_memory_free(ptr); + return status; + } + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Get metadata of current block. + current_block = (sli_block_metadata_t *)((uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE); + current_block_len = SLI_BLOCK_LEN_DWORD_TO_BYTE(current_block->length); + + // Adjust size to match the minimum alignment to maximize CPU access performance. + size_real = SLI_ALIGN_ROUND_UP(size, SLI_BLOCK_ALLOC_MIN_ALIGN); + + // BLOCK EXTENSION. + if (size_real > current_block_len) { + bool find_new_block = false; + + if (current_block->offset_neighbour_next != 0) { + next_block = (sli_block_metadata_t *)((uint64_t *)current_block + (current_block->offset_neighbour_next)); + int32_t next_block_len_remaining = SLI_BLOCK_LEN_DWORD_TO_BYTE(next_block->length) - (size_real - current_block_len); + + // Verify if next block is free & has room to extend the current block. + if ((next_block->block_in_use == 0) && (next_block_len_remaining >= 0)) { + if (next_block_len_remaining >= SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE) { + // Enough space left in next block to leave a smaller free block. + + // Compute adjusted adjacent free block location. + sli_block_metadata_t *adjusted_next_block = (sli_block_metadata_t *)((uint8_t *)current_block + SLI_BLOCK_METADATA_SIZE_BYTE + size_real); + + // Update all relevant metadata fields of current block, next block, next next block (if applicable). + current_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); + current_block->offset_neighbour_next = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + sli_memory_metadata_init(adjusted_next_block); + adjusted_next_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(next_block_len_remaining); + adjusted_next_block->offset_neighbour_prev = current_block->offset_neighbour_next; + if (next_block->offset_neighbour_next != 0) { + sli_block_metadata_t *next_next_block = (sli_block_metadata_t *)((uint64_t *)next_block + next_block->offset_neighbour_next); + + // Add reservations offset. + reservation_offset = next_block->offset_neighbour_next - next_block->length; + + adjusted_next_block->offset_neighbour_next = adjusted_next_block->length + reservation_offset; + next_next_block->offset_neighbour_prev = adjusted_next_block->offset_neighbour_next; + } else { + adjusted_next_block->offset_neighbour_next = 0; // End of heap + } + + // Update head pointers accordingly. + sli_update_free_list_heads(adjusted_next_block, next_block, false); + // Ensure old next block metadata is invalid. + sli_memory_metadata_init(next_block); + } else { + // Not enough space in next block, simply append all next block to current one. + sli_free_blocks_number--; + current_block->length = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD + next_block->length; + if (next_block->offset_neighbour_next != 0) { + sli_block_metadata_t *next_next_block = (sli_block_metadata_t *)((uint64_t *)next_block + next_block->offset_neighbour_next); + + current_block->offset_neighbour_next = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + next_next_block->offset_neighbour_prev = current_block->offset_neighbour_next; + } else { + current_block->offset_neighbour_next = 0; // End of heap + } + + // Update head pointers accordingly. + sli_update_free_list_heads(current_block, next_block, true); + + // Ensure old next block metadata is invalid. + sli_memory_metadata_init(next_block); + } + + // At this point, current block data payload do not need to be copied. See Note #2. + + // Current block has been extended. Its payload must be returned to the caller. + *block = ptr; +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_realloc(sli_mm_heap_name, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + size_real + SLI_BLOCK_METADATA_SIZE_BYTE); +#endif + } else { + // Next block cannot fulfill the extension. Get a new one from the heap. + find_new_block = true; + } + } else { + // Current block is the last heap's block. No possible adjacent extension. + // Get a new one from the heap. + find_new_block = true; + } + + if (find_new_block == true) { + // Allocate a new block. + status = sl_memory_alloc(size_real, BLOCK_TYPE_LONG_TERM, block); + if (status != SL_STATUS_OK) { + CORE_EXIT_ATOMIC(); + return status; + } + + // Copy data from current block to new block. See Note #2. + memcpy(*block, ptr, current_block_len); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_realloc(sli_mm_heap_name, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + (uint8_t *)*block - SLI_BLOCK_METADATA_SIZE_BYTE, + size_real + SLI_BLOCK_METADATA_SIZE_BYTE); +#endif + + // Free current block. Reallocated block is different from the current one. + status = sl_memory_free(ptr); + if (status != SL_STATUS_OK) { + CORE_EXIT_ATOMIC(); + return status; + } + } + + if (find_new_block == false) { + heap_used_size += size_real - current_block_len; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; + } + } + + // BLOCK REDUCTION. + } else if (size_real < current_block_len) { + size_t current_block_remaining_len = current_block_len - size_real; + bool create_new_block = false; + + if (current_block->offset_neighbour_next != 0) { + next_block = (sli_block_metadata_t *)((uint64_t *)current_block + (current_block->offset_neighbour_next)); + + // Verify if next block is free to merge the newly unallocated portion of the current block. + if (next_block->block_in_use == 0) { + // Compute adjusted adjacent free block location. + sli_block_metadata_t *adjusted_next_block = (sli_block_metadata_t *)((uint8_t *)current_block + SLI_BLOCK_METADATA_SIZE_BYTE + size_real); + + // Update all relevant metadata fields of current block, next block, next next block (if applicable). + current_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); + current_block->offset_neighbour_next = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + sli_memory_metadata_init(adjusted_next_block); + adjusted_next_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(current_block_remaining_len) + next_block->length; + adjusted_next_block->offset_neighbour_prev = current_block->offset_neighbour_next; + if (next_block->offset_neighbour_next != 0) { + sli_block_metadata_t *next_next_block = (sli_block_metadata_t *)((uint64_t *)next_block + next_block->offset_neighbour_next); + + adjusted_next_block->offset_neighbour_next = adjusted_next_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + next_next_block->offset_neighbour_prev = adjusted_next_block->offset_neighbour_next; + } else { + adjusted_next_block->offset_neighbour_next = 0; // End of heap + } + + // Update head pointers accordingly. + sli_update_free_list_heads(adjusted_next_block, next_block, false); + + // Ensure old next block metadata is invalid. + sli_memory_metadata_init(next_block); + } else { + // Next block is in use and cannot be merged with the newly unallocated portion. + create_new_block = true; + } + } else { + // Current block is the last heap's block. No possible adjacent block to merge with the newly unallocated portion. + create_new_block = true; + } + + // Try to create a new free block in the unallocated portion of the current block. + if (create_new_block == true) { + if (current_block_remaining_len >= SLI_BLOCK_ALLOCATION_MIN_SIZE) { + // Compute adjusted adjacent free block location. + sli_block_metadata_t *adjusted_next_block = (sli_block_metadata_t *)((uint8_t *)current_block + SLI_BLOCK_METADATA_SIZE_BYTE + size_real); + + // Update all relevant metadata fields of current block, next block, next next block (if applicable). + current_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); + current_block->offset_neighbour_next = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + sli_memory_metadata_init(adjusted_next_block); + adjusted_next_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(current_block_remaining_len - SLI_BLOCK_METADATA_SIZE_BYTE); + adjusted_next_block->offset_neighbour_prev = current_block->offset_neighbour_next; + if (next_block != NULL) { + adjusted_next_block->offset_neighbour_next = adjusted_next_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + next_block->offset_neighbour_prev = adjusted_next_block->offset_neighbour_next; + } else { + adjusted_next_block->offset_neighbour_next = 0; // End of heap + } + + sli_free_blocks_number++; + // Update head pointers accordingly. + sli_update_free_list_heads(adjusted_next_block, NULL, false); + } else { + // Not enough space in current block remaining area to create a new free block. + // consider the current block unallocated portion as lost for now until the current block is freed. + // In that case, no need to update the current block metadata. All remains the same. + } + } + + // Current block has been reduced. Its payload must be returned to the caller. + *block = ptr; +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_realloc(sli_mm_heap_name, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + size_real + SLI_BLOCK_METADATA_SIZE_BYTE); +#endif + + heap_used_size -= current_block_len - size_real; + } else { + // If the size requested does not provoke a block extension or reduction, consider no error. + // And return the same given address. We still track it to show that resize was requested. + *block = ptr; +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_realloc(sli_mm_heap_name, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, + size_real + SLI_BLOCK_METADATA_SIZE_BYTE); +#endif + } + + CORE_EXIT_ATOMIC(); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + + return status; +} + +/***************************************************************************//** + * Populates an sl_memory_heap_info_t{} structure with the current status of + * the heap. + ******************************************************************************/ +sl_status_t sl_memory_get_heap_info(sl_memory_heap_info_t *heap_info) +{ + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + sli_block_metadata_t *block_metadata = (sli_block_metadata_t *)heap_region.addr; + bool compute = true; + size_t remaining_size = 0u; + size_t used_size = 0u; + size_t free_block_count = 0u; + size_t used_block_count = 0u; + size_t largest_free_size = 0u; + size_t smallest_free_size = SIZE_MAX; + size_t largest_used_size = 0u; + size_t smallest_used_size = SIZE_MAX; + + if (heap_info == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + do { + // Calculate the different used and remaining heap sizes. + if (block_metadata->block_in_use == 0) { + remaining_size += SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length); + largest_free_size = SL_MAX(SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length), largest_free_size); + smallest_free_size = SL_MIN(SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length), smallest_free_size); + free_block_count++; + } else { + used_size += SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length); + largest_used_size = SL_MAX(SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length), largest_used_size); + smallest_used_size = SL_MIN(SLI_BLOCK_LEN_DWORD_TO_BYTE(block_metadata->length), smallest_used_size); + used_block_count++; + } + + // Get the next block. + if (block_metadata->offset_neighbour_next == 0) { + compute = false; + } else { + block_metadata = (sli_block_metadata_t *)((uint64_t *)block_metadata + (block_metadata->offset_neighbour_next)); + } + } while (compute); + + CORE_EXIT_ATOMIC(); + + heap_info->base_addr = (size_t)heap_region.addr; + heap_info->total_size = heap_region.size; + heap_info->used_size = used_size; + heap_info->free_size = remaining_size; + heap_info->free_block_count = free_block_count; + heap_info->free_block_largest_size = largest_free_size; + heap_info->free_block_smallest_size = smallest_free_size; + heap_info->used_block_count = used_block_count; + heap_info->used_block_largest_size = largest_used_size; + heap_info->used_block_smallest_size = smallest_used_size; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the total size of the heap. + ******************************************************************************/ +size_t sl_memory_get_total_heap_size(void) +{ + sl_memory_heap_info_t heap_info; + + sl_memory_get_heap_info(&heap_info); + + return heap_info.total_size; +} + +/***************************************************************************//** + * Gets the current free heap size. + ******************************************************************************/ +size_t sl_memory_get_free_heap_size(void) +{ + sl_memory_heap_info_t heap_info; + + sl_memory_get_heap_info(&heap_info); + + return heap_info.free_size; +} + +/***************************************************************************//** + * Gets the current used heap size. + ******************************************************************************/ +size_t sl_memory_get_used_heap_size(void) +{ + sl_memory_heap_info_t heap_info; + + sl_memory_get_heap_info(&heap_info); + + return heap_info.used_size; +} + +/***************************************************************************//** + * Gets heap high watermark. + ******************************************************************************/ +size_t sl_memory_get_heap_high_watermark(void) +{ + size_t heap_high_watermark_value = 0; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + heap_high_watermark_value = heap_high_watermark; + CORE_EXIT_ATOMIC(); + + return heap_high_watermark_value; +} + +/***************************************************************************//** + * Reset heap high watermark to the current heap used. + ******************************************************************************/ +void sl_memory_reset_heap_high_watermark(void) +{ + sl_memory_heap_info_t heap_info; + + sl_memory_get_heap_info(&heap_info); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + heap_high_watermark = heap_info.used_size; + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Manages the required data alignment by moving the non-aligned block payload + * to the closest aligned location. + * + * @param[in] current_block_metadata Pointer to block whose payload start + * address must be moved to be aligned. + * + * @param[in] block_align Alignment required, in bytes. + * + * @return Pointer to the new block with the correct alignment. + * + ******************************************************************************/ +static sli_block_metadata_t *memory_manage_data_alignment(sli_block_metadata_t *current_block_metadata, + size_t block_align) +{ + void *data_payload = (void *)((uint8_t *)current_block_metadata + SLI_BLOCK_METADATA_SIZE_BYTE); + sli_block_metadata_t *old_block_metadata = current_block_metadata; + uint16_t align_offset; + + // Align payload to the correct alignment. + data_payload = (void *)SLI_ALIGN_ROUND_UP(((uintptr_t)data_payload), block_align); + + // Get the new metadata location and update all relevant fields. + current_block_metadata = (sli_block_metadata_t *)((uint8_t *)data_payload - SLI_BLOCK_METADATA_SIZE_BYTE); + sli_memory_metadata_init(current_block_metadata); + align_offset = (uint16_t)((uint64_t *)current_block_metadata - (uint64_t *)old_block_metadata); + current_block_metadata->length = old_block_metadata->length - align_offset; + + current_block_metadata->offset_neighbour_prev = old_block_metadata->offset_neighbour_prev + align_offset; + if (old_block_metadata->offset_neighbour_prev != 0) { + sli_block_metadata_t *prev_block = (sli_block_metadata_t *)((uint64_t *)old_block_metadata - old_block_metadata->offset_neighbour_prev); + + prev_block->offset_neighbour_next = current_block_metadata->offset_neighbour_prev; + // Merge lost space because of the alignment into the previous block. It helps to keep + // all computations in malloc()/free() valid. For ST split block, the lost space is back into + // a free block space. + prev_block->length += align_offset; + } else { + // Special case where the block data payload being aligned is at the heap start. A special flag in the block metadata + // is used to identify this special block in sl_memory_free() and accordingly perform the merge with previous adjacent block. + current_block_metadata->heap_start_align = true; + } + + if (old_block_metadata->offset_neighbour_next != 0) { + sli_block_metadata_t *next_block = (sli_block_metadata_t *)((uint64_t *)old_block_metadata + old_block_metadata->offset_neighbour_next); + + current_block_metadata->offset_neighbour_next = old_block_metadata->offset_neighbour_next - align_offset; + next_block->offset_neighbour_prev = current_block_metadata->offset_neighbour_next; + } else { + current_block_metadata->offset_neighbour_next = 0; + } + + return current_block_metadata; +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_cpp.cpp b/Libs/platform/service/memory_manager/src/sl_memory_manager_cpp.cpp new file mode 100644 index 0000000..8e70699 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_cpp.cpp @@ -0,0 +1,212 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's C++ Implementation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#include "sl_memory_manager.h" +#include "sl_assert.h" + +//-------------------------------------------------------------------------- +// MEMORY MANAGER PRE-INITIALIZATION + +#if defined (__GNUC__) +/***************************************************************************//** + * Initializes the memory manager. + * + * @note With a C++ application, the memory manager requires to be initialized + * prior to any malloc() done in any static global objects' constructors. + * + * This function is called after copying in RAM the .data section + * (initialized global variables) and zeroing the .bss section (non-initialized + * global variables) and before the main() entry point. The function is placed + * in a special section called .preinit_array. preinit_array hold pointers + * to functions that should be executed before any other initialization + * functions, including C++ static constructors. It allows very early + * initialization tasks that need to be completed before any dynamic linking + * or library initialization occurs. + * + * When sl_memory_init() is called early during the GCC/G++ startup code, + * sl_memory_init() is not called by the component sl_system. + ******************************************************************************/ +static void sl_memory_preinit(void) { + sl_memory_init(); +} + +__attribute__((used, section(".preinit_array"))) +static void (*preinit_array)(void) = sl_memory_preinit; +#endif + +#if defined(__IAR_SYSTEMS_ICC__) +/***************************************************************************//** + * Initializes the memory manager. + * + * @note This special C++ class and its associated global object allows the + * memory manager sl_memory_init() to be initialized prior to any malloc() done + * in any static global objects' constructors. + * It serves the same purpose as the C function sl_memory_preinit() used for + * GCC/G++ early initialization above. It will use the special section + * .preinit_array. + * + * The IAR "#pragma early_dynamic_initialization" marks certain global objects + * for earlier initialization by registering their constructor to the + * .preinit_array section. When sl_memory_init() is called early during the + * IAR startup code (i.e. after copying in RAM the .data section + * (initialized global variables) and zeroing the .bss section (non-initialized + * global variables) and before the main() entry point), sl_memory_init() + * is not called by the component sl_system. + ******************************************************************************/ +#pragma early_dynamic_initialization +class sl_memory_preinit +{ +public: + sl_memory_preinit() + { + sl_memory_init(); + } + + ~sl_memory_preinit() + { + } +}; + +sl_memory_preinit sl_memory_preinit_obj; +#endif + +//-------------------------------------------------------------------------- +// GLOBAL C++ NEW/DELETE OVERLOAD + +/***************************************************************************//** + * Overloaded new operator. + * Allocates a memory block of at least requested size from the heap. + * + * @param[in] size Size of the block, in bytes. + * + * @return Pointer to allocated block if successful. Null pointer if + * allocation failed. + ******************************************************************************/ +void *operator new(size_t size) +{ + void *block = NULL; + sl_status_t status; + + status = sl_memory_alloc(size, BLOCK_TYPE_LONG_TERM, (void **)&block); + if (status != SL_STATUS_OK) { + // Convert C NULL pointer to C++ dedicated type. + block = nullptr; + } + + return block; +} + +/***************************************************************************//** + * Overloaded delete operator used for single object allocations. + * Frees a previously allocated block back into the heap. + * + * @param[in] ptr Pointer to memory block to be freed. + ******************************************************************************/ +void operator delete(void *ptr) +{ + sl_status_t status; + + status = sl_memory_free(ptr); + if (status != SL_STATUS_OK) { + EFM_ASSERT(false); + } +} + +/***************************************************************************//** + * Overloaded delete operator used for array of objects allocations. + * Frees a previously allocated block back into the heap. + * + * @param[in] ptr Pointer to memory block to be freed. + ******************************************************************************/ +void operator delete[](void *ptr) +{ + sl_status_t status; + + status = sl_memory_free(ptr); + if (status != SL_STATUS_OK) { + EFM_ASSERT(false); + } +} + +/***************************************************************************//** + * Overloaded delete operator for single object allocations. + * Frees a previously allocated block back into the heap. + * + * @param[in] ptr Pointer to memory block to be freed. + * @param[in] size Size of block to be freed, in bytes. + * + * @note The -Wsized-deallocation option in G++ is a warning option related + * to C++17 and later versions. This other overloaded version of delete + * is recommended by -Wsized-deallocation option for C++17. Indeed, + * certain standard containers (e.g. vector, list) with C++17 use a delete + * that needs to provide a 'size' parameter. The Memory Manager + * does not provide a free() function taking a 'size' parameter. Hence, + * the 'size' parameter is simply ignored. When compiling with C++11, + * the same containers such as vector, list will use an overloaded delete + * without a 'size' parameter. + * The -Wsized-deallocation option is used to catch situations where + * you might be using the delete operator incorrectly with pointers + * that were not allocated with new or that were allocated with a type + * that doesn't have a suitable operator delete. + ******************************************************************************/ +void operator delete(void *ptr, + size_t size) +{ + sl_status_t status; + + (void)size; + + status = sl_memory_free(ptr); + if (status != SL_STATUS_OK) { + EFM_ASSERT(false); + } +} + +/***************************************************************************//** + * Overloaded delete operator used for array of objects allocations. + * Frees a previously allocated block back into the heap. + * + * @param[in] ptr Pointer to memory block to be freed. + * @param[in] size Size of block to be freed, in bytes. + ******************************************************************************/ +void operator delete[](void *ptr, + size_t size) +{ + sl_status_t status; + + (void)size; + + status = sl_memory_free(ptr); + if (status != SL_STATUS_OK) { + EFM_ASSERT(false); + } +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c b/Libs/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c new file mode 100644 index 0000000..b1d7fca --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c @@ -0,0 +1,377 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's Block Reservation Feature Implementation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "sl_memory_manager_config.h" +#include "sl_memory_manager.h" +#include "sli_memory_manager.h" +#include "sl_assert.h" +#include "sl_bit.h" +#include "sl_common.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Dynamically reserves a block of memory. + * + * @note (1) This function assumes the 'handle' is provided by the caller: + * - either statically (e.g. as a global variable) + * - or dynamically by calling sl_memory_reservation_handle_alloc(). + ******************************************************************************/ +sl_status_t sl_memory_reserve_block(size_t size, + size_t align, + sl_memory_reservation_t *handle, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + + // Check proper alignment characteristics. + EFM_ASSERT((align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) + || (SL_MATH_IS_PWR2(align) + && (align <= SL_MEMORY_BLOCK_ALIGN_512_BYTES))); + + (void) align; + sli_block_metadata_t *free_block_metadata = NULL; + void *reserved_blk = NULL; + size_t current_block_len; + size_t size_real; + size_t size_adjusted; + size_t block_size_remaining; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + reserve_no_retention_first = false; +#endif + + // Verify that the handle pointer isn't NULL. See Note #1. + if ((handle == NULL) || (block == NULL)) { + return SL_STATUS_NULL_POINTER; + } + + // Check that the block does not exist yet. + if ((handle->block_size != 0) || (handle->block_address != NULL)) { + return SL_STATUS_FAIL; + } + + *block = NULL; // No block reserved yet. + + if ((size == 0) || (size >= heap_region.size)) { + return SL_STATUS_INVALID_PARAMETER; + } + + size_real = SLI_ALIGN_ROUND_UP(size, SLI_BLOCK_ALLOC_MIN_ALIGN); + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // For block reservations, the size_adjusted contains the metadata. + size_adjusted = sli_memory_find_free_block(size_real, align, BLOCK_TYPE_SHORT_TERM, true, &free_block_metadata); + + if ((free_block_metadata == NULL) || (size_adjusted == 0)) { + CORE_EXIT_ATOMIC(); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_name, NULL, size, return_address); +#endif + return SL_STATUS_ALLOCATION_FAILED; + } + + current_block_len = SLI_BLOCK_LEN_DWORD_TO_BYTE(free_block_metadata->length); + // SLI_BLOCK_METADATA_SIZE_BYTE is added to the free block length to get the real remaining size as size_adjusted contains the metadata size. + block_size_remaining = (current_block_len + SLI_BLOCK_METADATA_SIZE_BYTE) - size_adjusted; + + // Create a new block = reserved block returned to requester. This new block is the nearest to the heap end. + reserved_blk = (sli_block_metadata_t *)((uint8_t *)free_block_metadata + block_size_remaining); + + sli_free_blocks_number--; + + // Split free and reserved blocks if possible. + if (block_size_remaining >= SLI_BLOCK_RESERVATION_MIN_SIZE_BYTE) { + // Changes size of free block. + free_block_metadata->length -= SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); + + // Account for the split block that is free. + sli_free_blocks_number++; + } else { + sli_block_metadata_t *neighbour_block = NULL; + + // Update next neighbour. + if (free_block_metadata->offset_neighbour_next != 0) { + neighbour_block = (sli_block_metadata_t *)((uint64_t *)free_block_metadata + free_block_metadata->offset_neighbour_next); + + if (free_block_metadata->offset_neighbour_prev != 0) { + neighbour_block->offset_neighbour_prev += free_block_metadata->offset_neighbour_prev; + } else { + // Heap start. + neighbour_block->offset_neighbour_next = 0; + } + } + + // Update previous neighbour. + if (free_block_metadata->offset_neighbour_prev != 0) { + neighbour_block = (sli_block_metadata_t *)((uint64_t *)free_block_metadata - free_block_metadata->offset_neighbour_prev); + + if (free_block_metadata->offset_neighbour_next != 0) { + neighbour_block->offset_neighbour_next += free_block_metadata->offset_neighbour_next; + } else { + // Heap end. + neighbour_block->offset_neighbour_next = 0; + } + } + + // Update head pointers accordingly. + sli_update_free_list_heads(neighbour_block, free_block_metadata, true); + } + + CORE_EXIT_ATOMIC(); + + handle->block_size = size; + handle->block_address = reserved_blk; + *block = reserved_blk; + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES + // Save the reservation for heap integrity check purposes. + sli_memory_save_reservation_handle(handle, align); +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc(sli_mm_heap_name, handle->block_address, size_real); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_reservation_name, + handle->block_address, + handle->block_size, + return_address); +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Frees a dynamically reserved block of memory. + * + * @note (1) Block reservation are not part of the double linked-list as they + * don't have metadata next to them compared to a LT/ST block that + * has a metadata with offset. When releasing a reserved block, + * the previous and next blocks that are part of the double linked-list + * need to be found to insert this new free block. The neighbours are + * found by browsing through the linked-list from the heap start until + * a block metadata's address is higher than the block being + * released's address. The previous and next blocks are then saved to + * properly update the double linked-list. + ******************************************************************************/ +sl_status_t sl_memory_release_block(sl_memory_reservation_t *handle) +{ + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + + uint16_t new_free_block_length; + sli_block_metadata_t *new_free_block = NULL; + sli_block_metadata_t *prev_block = NULL; + sli_block_metadata_t *next_block = NULL; + uint16_t reserved_block_offset; + + sli_block_metadata_t *current_metadata = (sli_block_metadata_t *)heap_region.addr; + + // Verify that the handle isn't NULL. + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_free(sli_mm_heap_name, handle->block_address); +#endif + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Find neighbours by searching from the heap start. See Note #1. + while ((uintptr_t)current_metadata < (uintptr_t)handle->block_address) { + prev_block = current_metadata; + + if (current_metadata->offset_neighbour_next == 0) { + break; + } + + current_metadata = (sli_block_metadata_t *)((uint64_t *)current_metadata + current_metadata->offset_neighbour_next); + } + next_block = ((uintptr_t)current_metadata >= (uintptr_t)handle->block_address) ? current_metadata : NULL; + + new_free_block = (sli_block_metadata_t *)handle->block_address; + new_free_block_length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(handle->block_size) - SLI_BLOCK_METADATA_SIZE_DWORD; + + // Create a new free block while trying to merge it with the previous and next free blocks if possible. + if (prev_block != NULL) { + // Calculate offset between the reserved block and the previous block's payload address. + reserved_block_offset = (uint16_t)((uint64_t *)handle->block_address - (uint64_t *)prev_block - SLI_BLOCK_METADATA_SIZE_DWORD); + // Then calculate the difference between the above offset and the length of the previous block. + reserved_block_offset -= prev_block->length; + + // Make sure there's no reserved block between the freed block and the previous block. + // Layout around the reserved block to free (aka R1) will be: + // |...|Metadata Free block|Data Free block|R1|| + if ((prev_block->block_in_use == 0) && (reserved_block_offset < SLI_BLOCK_RESERVATION_MIN_SIZE_DWORD)) { + // New freed block's previous block is free, so merge both free blocks. + new_free_block = prev_block; + prev_block = (sli_block_metadata_t *)((uint64_t *)prev_block - prev_block->offset_neighbour_prev); + new_free_block_length += new_free_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; + } else { + // Create a new free block, because previous block is a dynamic allocation, a reserved block or the start of the heap. + // Layout around the reserved block to free (aka R1) will be: + // |...|Metadata Free block|Data Free block|R2|R1|| or |...|Metadata ST1|Data ST1|R1|| or |...|Metadata LT|Data LT|R1|| + sli_free_blocks_number++; + } + } + + if (next_block != NULL) { + // Calculate offset between the reserved block and the next block. + reserved_block_offset = (uint16_t)((uint64_t *)next_block - (uint64_t *)handle->block_address); + // Then calculate the difference between the above offset and the size of the block being released. + reserved_block_offset -= SLI_BLOCK_LEN_BYTE_TO_DWORD(handle->block_size); + + // Make sure there's no reserved block between the freed block and the next block. + if ((next_block->block_in_use == 0) && (reserved_block_offset < SLI_BLOCK_RESERVATION_MIN_SIZE_DWORD)) { + // New freed block's following block is free, so merge both free blocks. + new_free_block_length += next_block->length + reserved_block_offset + SLI_BLOCK_METADATA_SIZE_DWORD; + // Invalidate the next block metadata. + next_block->length = 0; + // 2 free blocks have been merged, account for 1 free block only. + sli_free_blocks_number--; + + if (next_block->offset_neighbour_next != 0) { + // Get next block following current next block. + next_block = (sli_block_metadata_t *)((uint64_t *)next_block + next_block->offset_neighbour_next); + } else { + next_block = NULL; + } + } + } + + // Update the new free metadata block accordingly. + sli_memory_metadata_init(new_free_block); + new_free_block->length = new_free_block_length; + + if (next_block != NULL) { + new_free_block->offset_neighbour_next = (uint16_t)((uint64_t *)next_block - (uint64_t *)new_free_block); + next_block->offset_neighbour_prev = new_free_block->offset_neighbour_next; + } else { + // Heap end. + new_free_block->offset_neighbour_next = 0; + } + + if (prev_block != NULL) { + new_free_block->offset_neighbour_prev = (uint16_t)((uint64_t *)new_free_block - (uint64_t *)prev_block); + prev_block->offset_neighbour_next = new_free_block->offset_neighbour_prev; + } else { + // Heap start. + new_free_block->offset_neighbour_prev = 0; + } + + if (sli_free_lt_list_head == NULL // LT list is empty. Freed block becomes the new 1st element. + || sli_free_lt_list_head > new_free_block // LT list not empty. Verify if freed block becomes the head. + || sli_free_lt_list_head->length == 0) { + sli_free_lt_list_head = new_free_block; + } + + if (sli_free_st_list_head == NULL // ST list is empty. Freed block becomes the new 1st element. + || sli_free_st_list_head < new_free_block // ST list not empty. Verify if freed block becomes the head. + || sli_free_st_list_head->length == 0) { + sli_free_st_list_head = new_free_block; + } + + // Invalidate handle. + handle->block_address = NULL; + handle->block_size = 0; + + CORE_EXIT_ATOMIC(); + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES + sli_memory_remove_reservation_handle(handle); +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Dynamically allocates a block reservation handle. + ******************************************************************************/ +sl_status_t sl_memory_reservation_handle_alloc(sl_memory_reservation_t **handle) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_status_t status; + + status = sl_memory_alloc(sizeof(sl_memory_reservation_t), BLOCK_TYPE_LONG_TERM, (void**)handle); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *handle, return_address); +#endif + if (status != SL_STATUS_OK) { + return status; + } + + // Initialize handle data. + (*handle)->block_address = NULL; + (*handle)->block_size = 0; + + return status; +} + +/***************************************************************************//** + * Frees a dynamically allocated block reservation handle. + ******************************************************************************/ +sl_status_t sl_memory_reservation_handle_free(sl_memory_reservation_t *handle) +{ + // Check that block has been released before freeing handle. + if ((handle->block_size != 0) || (handle->block_address != NULL)) { + return SL_STATUS_FAIL; + } + + return sl_memory_free((void *)handle); +} + +/***************************************************************************//** + * Gets the size of the memory reservation handle structure. + ******************************************************************************/ +uint32_t sl_memory_reservation_handle_get_size(void) +{ + return sizeof(sl_memory_reservation_t); +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_pool.c b/Libs/platform/service/memory_manager/src/sl_memory_manager_pool.c new file mode 100644 index 0000000..028275f --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_pool.c @@ -0,0 +1,242 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's Memory Pool Lightweight Feature Implementation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include + +#include "sl_memory_manager.h" +#include "sli_memory_manager.h" +#include "sl_assert.h" +#include "sl_core.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + +#define SLI_MEM_POOL_OUT_OF_MEMORY 0xFFFFFFFF +#define SLI_MEM_POOL_REQUIRED_PADDING(obj_size) (((sizeof(size_t) - ((obj_size) % sizeof(size_t))) % sizeof(size_t))) + +/***************************************************************************//** + * Creates a memory pool. + ******************************************************************************/ +sl_status_t sl_memory_create_pool(size_t block_size, + uint32_t block_count, + sl_memory_pool_t *pool_handle) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_status_t status = SL_STATUS_OK; + uint8_t *block = NULL; + size_t block_addr; + size_t pool_size; + EFM_ASSERT(block_count != 0); + EFM_ASSERT(block_size != 0); + + if (pool_handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // SLI_MEM_POOL_REQUIRED_PADDING Rounds up to the nearest platform-dependant size. On a 32-bit processor, + // it will be rounded-up to 4 bytes. E.g. 101 bytes will be rounded up to 104 bytes. + pool_handle->block_size = block_size + (uint16_t)SLI_MEM_POOL_REQUIRED_PADDING(block_size); + pool_handle->block_count = block_count; + + // Reserve a block in which the entire pool will reside. Uses a long term allocation to keep + // behavior similar to dynamic reservation. + pool_size = pool_handle->block_size * pool_handle->block_count; + status = sl_memory_alloc(pool_size, BLOCK_TYPE_LONG_TERM, (void **)&block); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block, return_address); +#endif + + if (status != SL_STATUS_OK) { + return status; + } + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + // Create the tracker for the pool with no description. The code that created + // the pool can add the tracker description if relevant. + sli_memory_profiler_create_pool_tracker(pool_handle, NULL, block, pool_size); +#endif + + pool_handle->block_address = (void *)block; + + // Returned block pointer not used because its reference is already stored in block_address. + (void)█ + + pool_handle->block_free = (uint32_t *)pool_handle->block_address; + + block_addr = (size_t)pool_handle->block_address; + + // Populate the list of free blocks except the last block. + for (uint16_t i = 0; i < (block_count - 1); i++) { + *(size_t *)block_addr = block_addr + pool_handle->block_size; + block_addr += pool_handle->block_size; + } + + // Last element will indicate out of memory. + *(size_t *)block_addr = SLI_MEM_POOL_OUT_OF_MEMORY; + + return status; +} + +/***************************************************************************//** + * Deletes a memory pool. + * + * @note The pool_handle provided is neither freed or invalidated. It can be + * reused in a new call to sl_memory_create_pool() to create another pool. + ******************************************************************************/ +sl_status_t sl_memory_delete_pool(sl_memory_pool_t *pool_handle) +{ + sl_status_t status; + + // Verify that the handle pointer isn't NULL. + if (pool_handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + // Delete the memory tracker + sli_memory_profiler_delete_tracker(pool_handle); +#endif + + // Free block. + status = sl_memory_free(pool_handle->block_address); + + return status; +} + +/***************************************************************************//** + * Allocates a block from a memory pool. + ******************************************************************************/ +sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, + void **block) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + CORE_DECLARE_IRQ_STATE; + + if ((pool_handle == NULL) || (block == NULL)) { + return SL_STATUS_NULL_POINTER; + } + + // No block allocated yet. + *block = NULL; + + CORE_ENTER_ATOMIC(); + + if ((size_t)pool_handle->block_free == SLI_MEM_POOL_OUT_OF_MEMORY) { + CORE_EXIT_ATOMIC(); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc_with_ownership(pool_handle, NULL, pool_handle->block_size, return_address); +#endif + return SL_STATUS_EMPTY; + } + + // Get the next free block. + void *block_addr = pool_handle->block_free; + + // Update the next free block using the address saved in that block. + pool_handle->block_free = (void *)*(size_t *)block_addr; + + CORE_EXIT_ATOMIC(); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_alloc_with_ownership(pool_handle, block_addr, pool_handle->block_size, return_address); +#endif + + *block = block_addr; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Frees a block from a memory pool. + ******************************************************************************/ +sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, + void *block) +{ + CORE_DECLARE_IRQ_STATE; + + if ((pool_handle == NULL) || (block == NULL)) { + return SL_STATUS_NULL_POINTER; + } + + // Validate that the provided address is in the pool payload range. + EFM_ASSERT((block >= pool_handle->block_address) \ + && ((size_t)block <= ((size_t)pool_handle->block_address + (pool_handle->block_size * pool_handle->block_count)))); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_free(pool_handle, block); +#endif + + CORE_ENTER_ATOMIC(); + + // Save the current free block address in this block. + *(size_t *)block = (size_t)pool_handle->block_free; + pool_handle->block_free = block; + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the count of free blocks in a memory pool. + ******************************************************************************/ +uint32_t sl_memory_pool_get_free_block_count(const sl_memory_pool_t *pool_handle) +{ + uint32_t free_block_count = 0; + uint32_t *free_block; + + if (pool_handle == NULL) { + return 0; + } + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + free_block = pool_handle->block_free; + + // Go through the free block list and count the number of free blocks remaining. + while ((size_t)free_block != SLI_MEM_POOL_OUT_OF_MEMORY) { + free_block = *(uint32_t **)free_block; + free_block_count++; + } + + CORE_EXIT_ATOMIC(); + + return free_block_count; +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_pool_common.c b/Libs/platform/service/memory_manager/src/sl_memory_manager_pool_common.c new file mode 100644 index 0000000..3050a34 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_pool_common.c @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's Memory Pool Common Implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_memory_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Dynamically allocates a memory pool handle. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_alloc(sl_memory_pool_t **pool_handle) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_status_t status; + + // Allocate pool_handle as a long-term block. + status = sl_memory_alloc(sizeof(sl_memory_pool_t), BLOCK_TYPE_LONG_TERM, (void **)pool_handle); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *pool_handle, return_address); +#endif + + return status; +} + +/***************************************************************************//** + * Frees a dynamically allocated memory pool handle. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle) +{ + sl_status_t status; + + // Free memory pool_handle. + status = sl_memory_free((void *)pool_handle); + + return status; +} + +/***************************************************************************//** + * Gets the size of the memory pool handle structure. + ******************************************************************************/ +uint32_t sl_memory_pool_handle_get_size(void) +{ + return sizeof(sl_memory_pool_t); +} + +/***************************************************************************//** + * Gets the total count of blocks in a memory pool. + ******************************************************************************/ +uint32_t sl_memory_pool_get_total_block_count(const sl_memory_pool_t *pool_handle) +{ + if (pool_handle == NULL) { + return 0; + } + + return pool_handle->block_count; +} + +/***************************************************************************//** + * Gets the count of used blocks in a memory pool. + ******************************************************************************/ +uint32_t sl_memory_pool_get_used_block_count(const sl_memory_pool_t *pool_handle) +{ + uint32_t used_block_count = 0; + + if (pool_handle == NULL) { + return 0; + } + + used_block_count = pool_handle->block_count - sl_memory_pool_get_free_block_count(pool_handle); + + return used_block_count; +} diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_region.c b/Libs/platform/service/memory_manager/src/sl_memory_manager_region.c new file mode 100644 index 0000000..52ccde6 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_region.c @@ -0,0 +1,144 @@ +/***************************************************************************//** + * @file + * @brief Getters for Heap and stack + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include "em_device.h" +#include "sl_memory_manager_region.h" +#include "sl_memory_manager_region_config.h" +#include "sl_component_catalog.h" + +#define IAR_HEAP_BLOCK_NAME "MEMORY_MANAGER_HEAP" + +// Prevent's compilation errors when building in simulation. +#ifndef __USED + #define __USED +#endif + +#if defined(__GNUC__) +// Declare stack object used with GCC. +static char sl_stack[SL_STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +/* + * Declare the base and limit of the full heap region used with GCC to make + * use of otherwise unused memory. + */ +extern char __HeapBase[]; +extern char __HeapLimit[]; + +#elif defined(__ICCARM__) +// Declare stack object used with IAR. +__root char sl_stack[SL_STACK_SIZE] @ ".stack"; + + #pragma section=IAR_HEAP_BLOCK_NAME + +#endif + +/***************************************************************************//** + * Gets size and location of the stack. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_stack_region(void) +{ + sl_memory_region_t region; + + region.addr = &sl_stack; + region.size = SL_STACK_SIZE; + return region; +} + +/***************************************************************************//** + * Gets size and location of the heap. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_heap_region(void) +{ + sl_memory_region_t region; + + // Report the actual heap region. +#if defined(__GNUC__) + region.addr = __HeapBase; + region.size = (uintptr_t) __HeapLimit - (uintptr_t) __HeapBase; + +#elif defined(__ICCARM__) + region.addr = __section_begin(IAR_HEAP_BLOCK_NAME); + region.size = __section_size(IAR_HEAP_BLOCK_NAME); +#endif + + return region; +} + +#if defined(__GNUC__) +/***************************************************************************//** + * Extends the process data space. + * + * @param[in] incr Number of bytes to increment/decrement + * + * @return Start of the new space allocated if successful. -1 if error. + * + * @note (1) This is a helper function called by the standard C library + * function malloc(). _sbrk() is used to dynamically change the + * amount of space allocated for the calling process data segment. + * The change is made by allocating the appropriate amount of space + * from the end of heap. + * _sbrk() adds 'incr' bytes to the end of heap and changes + * the allocated space accordingly. 'incr' can be negative, in which + * case the amount of allocated space is decreased. + * + * @note (2) When the Memory Manager (MM) is used, there is no need for + * _sbrk() as there is no possible extension with the MM controlling + * the entire heap size. + * If _sbrk() is called by the standard C library, then the project + * may have used the standard C malloc() function implementation. + * In that case, the MM retarget, wrapping the GCC malloc() to the + * MM sl_malloc(), may have not worked. You may want to double-check + * your project settings. + ******************************************************************************/ +__USED void * _sbrk(int incr) +{ +#if defined(SL_CATALOG_MEMORY_MANAGER_PRESENT) + (void)incr; + + // This means there is an issue with the setup of C standard library. See Note #2. + while (1) { + // infinite loop + } +#else + static char *heap_end = __HeapBase; + char *prev_heap_end; + + if ((heap_end + incr) > __HeapLimit) { + // Not enough heap + return (void *) -1; + } + + prev_heap_end = heap_end; + heap_end += incr; + + return prev_heap_end; +#endif +} +#endif diff --git a/Libs/platform/service/memory_manager/src/sl_memory_manager_retarget.c b/Libs/platform/service/memory_manager/src/sl_memory_manager_retarget.c new file mode 100644 index 0000000..29581f0 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sl_memory_manager_retarget.c @@ -0,0 +1,378 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's Retarget Implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_memory_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + +#if defined(__GNUC__) +// Wrapping a system function with GCC works by using the linker option '--wrap=symbol'. +// Any undefined reference to "symbol" will be resolved to "__wrap_symbol". +// Any undefined reference to "__real_symbol" will be resolved to "symbol". +// In our case, "__real_symbol" is not really required as the retargeted standard +// C memory functions will call the corresponding Memory Manager (MM) +// native function and not the standard functions again. So it should be seen: +// standard _malloc_r() -> MM sl_malloc() +// standard _free_r() -> MM sl_free() +// standard _calloc_r() -> MM sl_calloc() +// standard _realloc_r() -> MM sl_realloc() +#define STD_LIB_WRAPPER_MALLOC __wrap__malloc_r +#define STD_LIB_WRAPPER_FREE __wrap__free_r +#define STD_LIB_WRAPPER_CALLOC __wrap__calloc_r +#define STD_LIB_WRAPPER_REALLOC __wrap__realloc_r + +// The GNU gold linker has an issue with LTO and wrapping, where the symbol is +// stripped even if it is used in the source code, which leads to link-time errors. +// https://sourceware.org/bugzilla/show_bug.cgi?id=24415 +// By marking the wrapper as externally_visible, the symbol will not be stripped +// from the final binary, regardless if it is referenced or not in the source code. +#define ATTR_EXT_VIS __attribute__((externally_visible)) + +// Reentrant parameter. +#define RARG const struct _reent *reent, +#define VOID_RARG (void) reent + +#elif defined(__IAR_SYSTEMS_ICC__) +// Wrapping a system function works with IAR by patching symbol definitions using $Super$$ and $Sub$$ +// The $Super$$ special pattern identifies the original unpatched function used for calling +// the original function directly. +// The $Sub$$ special pattern identifies the new function that is called instead of the +// original function. +// In our case, $Super$$ is not really required as the retargeted standard +// C memory functions will call the corresponding Memory Manager (MM) +// native function and not the standard functions again. +// +// NOTE: IAR supports three separate heap memory handlers: the basic, the advanced, and the no-free +// heap handlers. +// - If there are calls to heap memory allocation routines in your application, but no calls +// to heap deallocation routines, the linker automatically chooses the no-free heap. +// - If there are calls to heap memory allocation routines in your application, the linker +// automatically chooses the advanced heap. +// - If there are calls to heap memory allocation routines in a library for example, the linker +// automatically chooses the basic heap. +// +// Depending on the heap handler type, IAR will select a different malloc/free/calloc/realloc +// implementation provided by the IAR system library. That's why, there are different sets of +// macros below below to wrap the right IAR standard memory functions with $Sub$$. +// - Basic heap: IAR memory functions are prefixed with "basic_" +// - Advanced heap: IAR memory functions are prefixed with "dl" +// - No Free heap: IAR memory functions are prefixed with "no_free" +// +// For No Free heap, IAR does not provide a free and realloc implementation. +#if (__VER__ == 8050009) +#define STD_LIB_WRAPPER_MALLOC $Sub$$__iar_dlmalloc +#define STD_LIB_WRAPPER_FREE $Sub$$__iar_dlfree +#define STD_LIB_WRAPPER_CALLOC $Sub$$__iar_dlcalloc +#define STD_LIB_WRAPPER_REALLOC $Sub$$__iar_dlrealloc +#elif (__VER__ == 9040001) +#define STD_LIB_WRAPPER_MALLOC $Sub$$__basic_malloc +#define STD_LIB_WRAPPER_FREE $Sub$$__basic_free +#define STD_LIB_WRAPPER_CALLOC $Sub$$__basic_calloc +#define STD_LIB_WRAPPER_REALLOC $Sub$$__basic_realloc + +#define STD_LIB_WRAPPER_MALLOC_ADVANCED $Sub$$__iar_dlmalloc +#define STD_LIB_WRAPPER_FREE_ADVANCED $Sub$$__iar_dlfree +#define STD_LIB_WRAPPER_CALLOC_ADVANCED $Sub$$__iar_dlcalloc +#define STD_LIB_WRAPPER_REALLOC_ADVANCED $Sub$$__iar_dlrealloc + +#define STD_LIB_WRAPPER_MALLOC_NO_FREE $Sub$$__no_free_malloc +#define STD_LIB_WRAPPER_CALLOC_NO_FREE $Sub$$__no_free_calloc +#else +#error Unsupported IAR compiler version for standard C memory functions retarget +#endif + +// Since IAR does not use LTO, resolve the attribute as nothing. +#define ATTR_EXT_VIS + +// Since IAR does not use reentrant functions, resolve reentrant parameter to nothing. +#define RARG +#define VOID_RARG + +#else +#error Unsupported compiler for standard C memory functions retarget +#endif + +#if defined(TEST_MEMORY_MANAGER_RETARGET_PRESENT) +volatile uint32_t retarget_malloc_counter = 0; +volatile uint32_t retarget_free_counter = 0; +volatile uint32_t retarget_calloc_counter = 0; +volatile uint32_t retarget_realloc_counter = 0; +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * malloc() wrapper. Allocates a memory block of at least requested size from + * the heap. + * + * @param[in] size Size of the block, in bytes. + * + * @return Pointer to allocated block if successful. Null pointer if + * allocation failed. + * + * @note Requesting a block of 0 byte will return a null pointer. + * + * @note All allocated blocks using this function will be considered long-term + * allocations. + ******************************************************************************/ +ATTR_EXT_VIS void *STD_LIB_WRAPPER_MALLOC(RARG + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + VOID_RARG; + void *ptr; + + ptr = sl_malloc(size); +#if defined(TEST_MEMORY_MANAGER_RETARGET_PRESENT) + retarget_malloc_counter++; +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} + +#if defined(__IAR_SYSTEMS_ICC__) && (__VER__ == 9040001) +void *STD_LIB_WRAPPER_MALLOC_ADVANCED(size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *ptr; + + ptr = sl_malloc(size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} + +void *STD_LIB_WRAPPER_MALLOC_NO_FREE(size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *ptr; + + ptr = sl_malloc(size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} +#endif + +/***************************************************************************//** + * free() wrapper. Frees a previously allocated block back into the heap. + * + * @param[in] ptr Pointer to memory block to be freed. + * + * @note Passing a null pointer does nothing. + ******************************************************************************/ +ATTR_EXT_VIS void STD_LIB_WRAPPER_FREE(RARG + void *ptr) +{ + VOID_RARG; + sl_free(ptr); +#if defined(TEST_MEMORY_MANAGER_RETARGET_PRESENT) + retarget_free_counter++; +#endif +} + +#if defined(__IAR_SYSTEMS_ICC__) && (__VER__ == 9040001) +void STD_LIB_WRAPPER_FREE_ADVANCED(void *ptr) +{ + sl_free(ptr); +} +#endif + +/***************************************************************************//** + * calloc() wrapper. Dynamically allocates a block of memory cleared to 0. + * + * @param[in] item_count Number of elements to be allocated. + * @param[in] size Size of each elements, in bytes. + * + * @return Pointer to allocated block if successful. Null pointer if + * allocation failed. + * + * @note All allocated blocks using this function will be considered long-term + * allocations. + ******************************************************************************/ +ATTR_EXT_VIS void *STD_LIB_WRAPPER_CALLOC(RARG + size_t item_count, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + VOID_RARG; + void *ptr; + + ptr = sl_calloc(item_count, size); +#if defined(TEST_MEMORY_MANAGER_RETARGET_PRESENT) + retarget_calloc_counter++; +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} + +#if defined(__IAR_SYSTEMS_ICC__) && (__VER__ == 9040001) +void *STD_LIB_WRAPPER_CALLOC_ADVANCED(size_t item_count, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *ptr; + + ptr = sl_calloc(item_count, size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} + +void *STD_LIB_WRAPPER_CALLOC_NO_FREE(size_t item_count, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *ptr; + + ptr = sl_calloc(item_count, size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + + return ptr; +} +#endif + +/***************************************************************************//** + * realloc() wrapper. Resizes a previously allocated memory block. + * + * @param[in] ptr Pointer to the allocation to resize. If NULL, behavior + * is same as sl_malloc(), sl_memory_alloc(). + * @param[in] size New size of the block, in bytes. If 0, behavior is same as + * sl_free(), sl_memory_free(). + * + * @return Pointer to newly allocated block, if successful. Null pointer if + * re-allocation failed. + * + * @note All re-allocated blocks using this function will be considered + * long-term allocations. + * + * @note 'ptr' NULL and 'size' of 0 bytes is an incorrect parameters + * combination. No reallocation will be done by the function as it is + * an error condition. + * + * @note If the new 'size' is the same as the old, the function changes nothing + * and returns the same provided address 'ptr'. + ******************************************************************************/ +ATTR_EXT_VIS void *STD_LIB_WRAPPER_REALLOC(RARG + void *ptr, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + VOID_RARG; + void *r_ptr; + + r_ptr = sl_realloc(ptr, size); +#if defined(TEST_MEMORY_MANAGER_RETARGET_PRESENT) + retarget_realloc_counter++; +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + r_ptr, + return_address); +#endif + + return r_ptr; +} + +#if defined(__IAR_SYSTEMS_ICC__) && (__VER__ == 9040001) +void *STD_LIB_WRAPPER_REALLOC_ADVANCED(void *ptr, + size_t size) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + void *r_ptr; + + r_ptr = sl_realloc(ptr, size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + r_ptr, + return_address); +#endif + + return r_ptr; +} +#endif diff --git a/Libs/platform/service/memory_manager/src/sli_memory_manager.h b/Libs/platform/service/memory_manager/src/sli_memory_manager.h new file mode 100644 index 0000000..e96c981 --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sli_memory_manager.h @@ -0,0 +1,340 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver API definition. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MEMORY_MANAGER_H_ +#define SLI_MEMORY_MANAGER_H_ + +#include "sl_memory_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Memory Manager integration to SystemView is enabled on GCC builds of +// applications that include the SystemView component +#if defined(SL_CATALOG_SYSTEMVIEW_TRACE_PRESENT) && defined(__GNUC__) +#define SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW +#endif + +// Minimum block alignment in bytes. 8 bytes is the minimum alignment to account for largest CPU data type +// that can be used in some block allocation scenarios. 64-bit data type may be used to manipulate the +// allocated block. The ARM processor ABI defines data types and byte alignment, and 8-byte alignment +// can be seen for the largest data object type. +#define SLI_BLOCK_ALLOC_MIN_ALIGN SL_MEMORY_BLOCK_ALIGN_8_BYTES + +// Minimum block allocation size to avoid creating a block too small while splitting up an allocated block. +// Minimum size is formed from (metadata + payload) size. Size expressed in bytes. +#define SLI_BLOCK_ALLOCATION_MIN_SIZE (SLI_BLOCK_METADATA_SIZE_BYTE + SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE) + +// Minimum block reservation size to avoid creating a block too small while splitting up a reserved block. +// Contrary to block allocations, reservations don't have metadata. +#define SLI_BLOCK_RESERVATION_MIN_SIZE_BYTE SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE +#define SLI_BLOCK_RESERVATION_MIN_SIZE_DWORD SLI_BLOCK_LEN_BYTE_TO_DWORD(SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE) + +// 64-bit word size (in octets). +#define SLI_WORD_SIZE_64 8u +// 32-bit word size (in octets). +#define SLI_WORD_SIZE_32 4u +#define SLI_DEF_INT_32_NBR_BITS 32u + +// 1-byte size (in bits). +#define SLI_DEF_INT_08_NBR_BITS 8u + +// Size of block metadata area in different units. +#define SLI_BLOCK_METADATA_SIZE_BYTE sizeof(sli_block_metadata_t) +#define SLI_BLOCK_METADATA_SIZE_DWORD SLI_BLOCK_LEN_BYTE_TO_DWORD(SLI_BLOCK_METADATA_SIZE_BYTE) + +// Size of reservation handle area in different units. +#define SLI_RESERVATION_HANDLE_SIZE_BYTE sizeof(sl_memory_reservation_t) +#define SLI_RESERVATION_HANDLE_SIZE_DWORD SLI_BLOCK_LEN_BYTE_TO_DWORD(SLI_RESERVATION_HANDLE_SIZE_BYTE) + +// Size of pool handle area in different units. +#define SLI_POOL_HANDLE_SIZE_BYTE sizeof(sl_memory_pool_t) +#define SLI_POOL_HANDLE_SIZE_DWORD SLI_BLOCK_LEN_BYTE_TO_DWORD(SLI_POOL_HANDLE_SIZE_BYTE) + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +#define SLI_MAX_RESERVATION_COUNT 32 +#endif + +/******************************************************************************* + ********************************** MACROS ********************************* + ******************************************************************************/ + +// Macros to align a value to the nearest value multiple of the specified alignment +// (rounded up or down). These macros are used for memory addresses requiring an alignment. +#define SLI_ALIGN_ROUND_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#define SLI_ALIGN_ROUND_DOWN(num, align) ((num) & ~((align) - 1)) + +// Macros to convert block length in different units (bytes, double words). +// Byte to word will round up to account for extra bytes. +#define SLI_BLOCK_LEN_DWORD_TO_BYTE(len) ((len) * SLI_WORD_SIZE_64) +#define SLI_BLOCK_LEN_BYTE_TO_DWORD(len) ((len + SLI_WORD_SIZE_64 - 1) / SLI_WORD_SIZE_64) + +// Macro to test address given a specified data alignment. +#define SLI_ADDR_IS_ALIGNED(ptr, align_byte) (((uintptr_t)(const void *)(ptr)) % (align_byte) == 0) + +// Macro to convert from bits to byte. +#define SLI_POOL_BITS_TO_BYTE(bits) (((bits) + 7u) / SLI_DEF_INT_08_NBR_BITS) + +/******************************************************************************* + ********************************* TYPEDEF ********************************* + ******************************************************************************/ + +// Block metadata containing information about allocated block. +// This metadata allows to implement explicit free blocks list. +// NOTE: The metadata size should ideally be a multiple of 8 bytes (see description of +// SLI_BLOCK_ALLOC_MIN_ALIGN for other details) or at least multiple of CPU data size +// (e.g. 4 bytes for 32-bit CPU). +// 'length' is expressed in double words unit. It can described a block up to 512 KB (65535 * 8 bytes). +typedef struct { + uint16_t block_in_use : 1; // Flag indicating if block allocated or not. + uint16_t heap_start_align : 1; // Flag indicating if first block at heap start undergone a data payload adjustment. +#if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) + uint16_t block_type : 1; // Block type (LT or ST). + uint16_t reserved : 13; // Unallocated for future usage. +#else + uint16_t reserved : 14; // Unallocated for future usage. +#endif + uint16_t length; // Block size (metadata not included just data payload), in double words (64 bit). + uint16_t offset_neighbour_prev; // Offset to previous neighbor, in double words. It includes metadata/payload sizes. + uint16_t offset_neighbour_next; // Offset to next neighbor, in double words. +} sli_block_metadata_t; + +/******************************************************************************* + **************************** GLOBAL VARIABLES ***************************** + ******************************************************************************/ + +extern sli_block_metadata_t *sli_free_st_list_head; +extern sli_block_metadata_t *sli_free_lt_list_head; +extern uint32_t sli_free_blocks_number; +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) +extern bool reserve_no_retention_first; +#endif + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +extern sl_memory_reservation_t* sli_reservation_handle_ptr_table[]; +extern uint32_t sli_reservation_alignment_table[]; + +extern sl_memory_reservation_t sli_reservation_no_retention_table[]; +extern uint32_t sli_reservation_no_retention_alignment_table[]; +#endif + +// The heap name is also used as the Memory Profiler tracker handle for the heap +// pool managed by the Memory Manager +extern const char sli_mm_heap_name[]; +extern const char sli_mm_heap_reservation_name[]; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initializes a memory block metadata to some reset values. + * + * @param[in] block_metadata Pointer to block metadata. + ******************************************************************************/ +void sli_memory_metadata_init(sli_block_metadata_t *block_metadata); + +/***************************************************************************//** + * Gets pointer to the first free block of adequate size. + * + * @param[in] size Size of the block, in bytes. + * @param[in] align Required alignment for the block, in bytes. + * @param[in] type Type of block (long-term or short term). + * BLOCK_TYPE_LONG_TERM + * BLOCK_TYPE_SHORT_TERM + * @param[in] block_reservation Indicates if the free block is for a dynamic + * reservation. + * @param[out] block Pointer to variable that will receive the + * start address of the free block. + * + * @return Size of the block adjusted with the alignment. + ******************************************************************************/ +size_t sli_memory_find_free_block(size_t size, + size_t align, + sl_memory_block_type_t type, + bool block_reservation, + sli_block_metadata_t **block); + +/***************************************************************************//** + * Finds the next free block that will become the long-term or short-term head + * pointer. + * + * @param[in] type Type of block (long-term or short term). + * BLOCK_TYPE_LONG_TERM + * BLOCK_TYPE_SHORT_TERM + * + * @param[in] block_start_from Pointer to block where to start searching. + * NULL pointer means start from one of heap + * ends according to the block type. + * + * @return Pointer to the new free block. + ******************************************************************************/ +sli_block_metadata_t *sli_memory_find_head_free_block(sl_memory_block_type_t type, + sli_block_metadata_t *block_start_from); + +/***************************************************************************//** + * Gets long-term head pointer to the first free block. + * + * @return Pointer to first free long-term block. + ******************************************************************************/ +void *sli_memory_get_longterm_head_ptr(void); + +/***************************************************************************//** + * Gets short-term head pointer to the first free block. + * + * @return Pointer to first free short-term block. + ******************************************************************************/ +void *sli_memory_get_shortterm_head_ptr(void); + +/***************************************************************************//** + * Update free lists heads (short and long terms) + * + * @param[in] free_head Block from where to start searching or next free block. + * + * @param[in] condition_block Block condition to check if update is necessary + * or not. + * + * @param[in] search Boolean condition to check if searching the heap for a free + * block is necessary. + ******************************************************************************/ +void sli_update_free_list_heads(sli_block_metadata_t *free_head, + const sli_block_metadata_t *condition_block, + bool search); + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +/***************************************************************************//** + * Gets the pointer to sl_memory_reservation_t{} by block address. + * + * @param[in] addr Pointer to the block reservation. + * + * @return Pointer to reservation handle. + ******************************************************************************/ +sl_memory_reservation_t *sli_memory_get_reservation_handle_by_addr(void *addr); + +/***************************************************************************//** + * Gets the size of a reservation by block address. + * + * @param[in] addr Pointer to the block reservation. + * + * @return Size of the reservation in bytes. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_size_by_addr(void *addr); + +/***************************************************************************//** + * Get the alignment of a reservation by block address. + * + * @param[in] addr Pointer to the block reservation. + * + * @return Alignment of the reservation in bytes. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_align_by_addr(void *addr); + +/***************************************************************************//** + * Bookkeeps a reservation for profiling purposes. + * + * @param[in] reservation_handle_ptr Pointer to the reservation handle. + * @param[in] align Alignment of the reservation. + * + * @return SL_STATUS_FULL if record is full. + ******************************************************************************/ +sl_status_t sli_memory_save_reservation_handle(sl_memory_reservation_t *reservation_handle_ptr, + uint32_t align); + +/***************************************************************************//** + * Removes a reservation from records. + * + * @param[in] reservation_handle_ptr Pointer to the reservation handle. + * + * @return SL_STATUS_NOT_FOUND if reservation is does not exist in records. + ******************************************************************************/ +sl_status_t sli_memory_remove_reservation_handle(sl_memory_reservation_t *reservation_handle_ptr); + +/***************************************************************************//** + * Bookkeeps a reservation (no retention) for profiling purposes. + * + * @param[in] block_address Pointer to the block reservation. + * @param[in] block_size Size of the reservation. + * @param[in] align Alignment of the reservation. + * + * @return SL_STATUS_NOT_FOUND if reservation is does not exist in records. + ******************************************************************************/ +sl_status_t sli_memory_save_reservation_no_retention(void * block_address, uint32_t block_size, uint32_t align); + +/***************************************************************************//** + * Gets the size of a reservation (no retention) by block address. + * + * @param[in] addr Pointer to the block reservation. + * + * @return Size of the reservation (no retention) in bytes. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_no_retention_size(void * addr); + +/***************************************************************************//** + * Gets the alignment of a reservation (no retention) by block address. + * + * @param[in] addr Pointer to the block reservation. + * + * @return Alignment of the reservation in bytes. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_no_retention_align(void * addr); + +/***************************************************************************//** + * Does a heap integrity check forwards from sli_free_lt_list_head and return + * the pointer to the corrupted sli_block_metadata_t{} (if applicable). + * This could go past reservations so there are checks. + * + * @return Pointer to the corrupted sli_block_metadata_t{}. + ******************************************************************************/ +sli_block_metadata_t * sli_memory_check_heap_integrity_forwards(void); + +/***************************************************************************//** + * Does a heap integrity check backwards from sli_free_st_list_head and return + * the pointer to the corrupted sli_block_metadata_t{} (if applicable). + * This should not go past any reservations, hence there are no checks. + * + * @return Pointer to the corrupted sli_block_metadata_t{}. + ******************************************************************************/ +sli_block_metadata_t *sli_memory_check_heap_integrity_backwards(void); +#endif /* SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES */ + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_MEMORY_MANAGER_H_ */ diff --git a/Libs/platform/service/memory_manager/src/sli_memory_manager_common.c b/Libs/platform/service/memory_manager/src/sli_memory_manager_common.c new file mode 100644 index 0000000..5faa47c --- /dev/null +++ b/Libs/platform/service/memory_manager/src/sli_memory_manager_common.c @@ -0,0 +1,712 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver Implementation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "sl_memory_manager_config.h" +#include "sl_memory_manager.h" +#include "sli_memory_manager.h" +#include "sl_assert.h" +#include "sl_bit.h" +#include "sl_common.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Minimum block alignment in bytes. 8 bytes is the minimum alignment to account for largest CPU data type +// that can be used in some block allocation scenarios. 64-bit data type may be used to manipulate the +// allocated block. The ARM processor ABI defines data types and byte alignment, and 8-byte alignment +// can be seen for the largest data object type. +#define SLI_BLOCK_ALLOC_MIN_ALIGN SL_MEMORY_BLOCK_ALIGN_8_BYTES + +// Minimum block allocation size to avoid creating a block too small while splitting up an allocated block. +// Minimum size is formed from (metadata + payload) size. Size expressed in bytes. +#define SLI_BLOCK_ALLOCATION_MIN_SIZE (SLI_BLOCK_METADATA_SIZE_BYTE + SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE) + +// 64-bit word size (in octets). +#define SLI_WORD_SIZE_64 8u + +// Size of metadata area in different units. +#define SLI_BLOCK_METADATA_SIZE_BYTE sizeof(sli_block_metadata_t) +#define SLI_BLOCK_METADATA_SIZE_DWORD SLI_BLOCK_LEN_BYTE_TO_DWORD(SLI_BLOCK_METADATA_SIZE_BYTE) + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +sli_block_metadata_t *sli_free_lt_list_head; +sli_block_metadata_t *sli_free_st_list_head; +uint32_t sli_free_blocks_number; + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +// Dynamic reservation bookkeeping. +sl_memory_reservation_t *sli_reservation_handle_ptr_table[SLI_MAX_RESERVATION_COUNT] = { NULL }; +uint32_t sli_reservation_alignment_table[SLI_MAX_RESERVATION_COUNT] = { 0 }; + +// Reservation no retention bookkeeping. +// Array of structs instead of pointers to avoid dynamic allocation for handle. +sl_memory_reservation_t sli_reservation_no_retention_table[SLI_MAX_RESERVATION_COUNT] = { 0 }; +uint32_t sli_reservation_no_retention_alignment_table[SLI_MAX_RESERVATION_COUNT] = { 0 }; +#endif + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +/***************************************************************************//** + * Gets the index in sli_reservation_handle_ptr_table[] by block address. + * + * @param[in] addr Pointer to block reservation. + * + * @return Corresponding index in sli_reservation_handle_ptr_table. + ******************************************************************************/ +static uint32_t get_reservation_ix_by_addr(void *addr) +{ + for (uint32_t ix = 0; ix < SLI_MAX_RESERVATION_COUNT; ix++) { + if (sli_reservation_handle_ptr_table[ix] == NULL) { + continue; + } + if (sli_reservation_handle_ptr_table[ix]->block_address == addr) { + return ix; + } + } + return -1; +} + +/***************************************************************************//** + * Gets the index in sli_reservation_handle_ptr_table[] + * by reservation handle pointer. + * + * @param[in] reservation_handle_ptr Pointer to reservation handle. + * + * @return Corresponding index in sli_reservation_handle_ptr_table. + ******************************************************************************/ +static uint32_t get_reservation_ix_by_handle(sl_memory_reservation_t *reservation_handle_ptr) +{ + for (uint32_t ix = 0; ix < SLI_MAX_RESERVATION_COUNT; ix++) { + if (sli_reservation_handle_ptr_table[ix] == NULL) { + continue; + } + if (sli_reservation_handle_ptr_table[ix] == reservation_handle_ptr) { + return ix; + } + } + return -1; +} + +/***************************************************************************//** + * Get an index of sli_reservation_handle_ptr_table that is free. + * + * @return Index of an empty entry in sli_reservation_handle_ptr_table. + ******************************************************************************/ +static uint32_t get_available_reservation_handle_ix(void) +{ + for (uint32_t ix = 0; ix < SLI_MAX_RESERVATION_COUNT; ix++) { + if (sli_reservation_handle_ptr_table[ix] == NULL) { + return ix; + } + } + return -1; +} + +/***************************************************************************//** + * Gets the index in sli_reservation_no_retention_table[] by block address. + * + * @param[in] addr Pointer to block reservation. + * + * @return Corresponding index in sli_reservation_no_retention_table[]. + ******************************************************************************/ +static uint32_t get_reservation_no_retention_ix(void *addr) +{ + for (uint32_t ix = 0; ix < SLI_MAX_RESERVATION_COUNT; ix++) { + if (sli_reservation_no_retention_table[ix].block_address == NULL) { + continue; + } + if (sli_reservation_no_retention_table[ix].block_address == addr) { + return ix; + } + } + return -1; +} + +/***************************************************************************//** + * Gets an index of sli_reservation_no_retention_table[] that is free. + * + * @return Index of an empty entry in sli_reservation_no_retention_table[]. + ******************************************************************************/ +static uint32_t get_available_reservation_no_retention_ix(void) +{ + for (uint32_t ix = 0; ix < SLI_MAX_RESERVATION_COUNT; ix++) { + if (sli_reservation_no_retention_table[ix].block_address == NULL) { + return ix; + } + } + return -1; +} +#endif + +/***************************************************************************//** + * Initializes a memory block metadata to some reset values. + ******************************************************************************/ +void sli_memory_metadata_init(sli_block_metadata_t *block_metadata) +{ + block_metadata->block_in_use = 0; + block_metadata->heap_start_align = 0; + block_metadata->reserved = 0; + block_metadata->length = 0; + block_metadata->offset_neighbour_prev = 0; + block_metadata->offset_neighbour_next = 0; +} + +/***************************************************************************//** + * Gets pointer pointing to the first free block of adequate size. + * + * @note (1) For a block reservation, there's no metadata next to the + * reserved block. For this reason, when looking for a free block + * large enough to fit a new reserved block, the size of the metadata + * is counted in the available size of the free blocks. + * + * @note (2) For a short-term block, if the required data alignment is greater + * than 8 bytes, the found block size must account for the correct + * alignment of the block data payload. A series of computations is + * done starting from the end of the found block to determine the + * best data offset needed to align the data payload. The worst + * alignment (size_real + block_align) cannot be taken by default + * as it may imply loosing too many bytes in internal fragmentation + * due to the alignment requirement. + ******************************************************************************/ +size_t sli_memory_find_free_block(size_t size, + size_t align, + sl_memory_block_type_t type, + bool block_reservation, + sli_block_metadata_t **block) +{ + sli_block_metadata_t *current_block_metadata = NULL; + void *data_payload = NULL; + size_t size_adjusted = 0; + size_t current_block_len; + size_t block_align = (align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) ? SLI_BLOCK_ALLOC_MIN_ALIGN : align; + size_t data_payload_offset; + bool is_aligned = false; + + *block = NULL; + + current_block_metadata = (type == BLOCK_TYPE_LONG_TERM) ? sli_free_lt_list_head : sli_free_st_list_head; + if (current_block_metadata == NULL) { + return 0; + } + + current_block_len = SLI_BLOCK_LEN_DWORD_TO_BYTE(current_block_metadata->length); + + // For a block reservation, add the metadata's size to the free blocks' available memory space. See Note #2. + current_block_len += block_reservation ? SLI_BLOCK_METADATA_SIZE_BYTE : 0; + + // Try to find a block to allocate (first-fit). + while (current_block_metadata != NULL) { + if ((!current_block_metadata->block_in_use) && (current_block_len >= size)) { + if (type == BLOCK_TYPE_LONG_TERM) { + // Check alignment requested and ensure size of found block can accommodate worst case alignment. + // For LT, alignment requirement can be verified here whether the block is split or not. + data_payload = (void *)((uint8_t *)current_block_metadata + SLI_BLOCK_METADATA_SIZE_BYTE); + is_aligned = SLI_ADDR_IS_ALIGNED(data_payload, block_align); + data_payload_offset = (uintptr_t)data_payload % block_align; + + if (is_aligned || (current_block_len >= (size + data_payload_offset))) { + // Compute remaining block size given an alignment handling or not. + size_adjusted = is_aligned ? size : (size + data_payload_offset); + break; + } + } else { + if (block_align == SLI_BLOCK_ALLOC_MIN_ALIGN) { + // If alignment is 8 bytes (default min alignment), take the requested adjusted size. + size_adjusted = size; + } else { + // If non 8-byte alignment, search the more optimized size accounting for the required alignment. See Note #3. + uint8_t *block_end = (uint8_t *)((uint64_t *)current_block_metadata + SLI_BLOCK_METADATA_SIZE_DWORD + current_block_metadata->length); + + data_payload = (void *)(block_end - size); + data_payload = (void *)SLI_ALIGN_ROUND_DOWN(((uintptr_t)data_payload), block_align); + size_adjusted = (size_t)(block_end - (uint8_t *)data_payload); + } + + if (current_block_len >= size_adjusted) { + break; + } + } + } + + // Get next block. + if (type == BLOCK_TYPE_LONG_TERM) { + if (current_block_metadata->offset_neighbour_next == 0) { + return 0; // End of heap. No block found. + } + // Long-term browsing direction goes from start to end of heap. + current_block_metadata = (sli_block_metadata_t *)((uint64_t *)current_block_metadata + (current_block_metadata->offset_neighbour_next)); + } else { + if (current_block_metadata->offset_neighbour_prev == 0) { + return 0; // Start of heap. No block found. + } + // Short-term browsing direction goes from end to start of heap. + current_block_metadata = (sli_block_metadata_t *)((uint64_t *)current_block_metadata - (current_block_metadata->offset_neighbour_prev)); + } + + current_block_len = SLI_BLOCK_LEN_DWORD_TO_BYTE(current_block_metadata->length); + current_block_len += block_reservation ? SLI_BLOCK_METADATA_SIZE_BYTE : 0; + } + + *block = current_block_metadata; + return size_adjusted; +} + +/***************************************************************************//** + * Finds the next free block that will become the long-term or short-term head + * pointer. + ******************************************************************************/ +sli_block_metadata_t *sli_memory_find_head_free_block(sl_memory_block_type_t type, + sli_block_metadata_t *block_start_from) +{ + sli_block_metadata_t *current_block_metadata = NULL; + sli_block_metadata_t *free_block_metadata = NULL; + bool search = true; + + if (sli_free_blocks_number == 0) { + // No more free blocks. + return NULL; + } + + if (block_start_from != NULL) { + // Start searching from the given block. + current_block_metadata = block_start_from; + } else { + // Start searching from heap start (long-term [LT]) or near heap end (short-term [ST]). + // For ST, searching cannot start at the absolute heap end. So the ST head pointer is used as it points + // to the last free block closest to the heap end. + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + + current_block_metadata = (type == BLOCK_TYPE_LONG_TERM) ? (sli_block_metadata_t *)heap_region.addr : sli_free_st_list_head; + } + + // Long-term block: find the first free block closest to the heap start. + // Short-term block: find the first free block closest to the heap end. + do { + if (current_block_metadata->block_in_use == 0) { + free_block_metadata = current_block_metadata; + search = false; + } else if ((type == BLOCK_TYPE_LONG_TERM) && (current_block_metadata->offset_neighbour_next != 0)) { + current_block_metadata = (sli_block_metadata_t *)((uint64_t *)current_block_metadata + (current_block_metadata->offset_neighbour_next)); + } else if ((type == BLOCK_TYPE_SHORT_TERM) && (current_block_metadata->offset_neighbour_prev != 0)) { + current_block_metadata = (sli_block_metadata_t *)((uint64_t *)current_block_metadata - (current_block_metadata->offset_neighbour_prev)); + } else { + free_block_metadata = NULL; + break; + } + } while (search); + + return free_block_metadata; +} + +/***************************************************************************//** + * Gets long-term head pointer pointing to the first free block. + ******************************************************************************/ +void *sli_memory_get_longterm_head_ptr(void) +{ + return (void *)sli_free_lt_list_head; +} + +/***************************************************************************//** + * Gets short-term head pointer pointing to the first free block. + ******************************************************************************/ +void *sli_memory_get_shortterm_head_ptr(void) +{ + return (void *)sli_free_st_list_head; +} + +/***************************************************************************//** + * Update free lists heads (short and long terms). + ******************************************************************************/ +void sli_update_free_list_heads(sli_block_metadata_t *free_head, + const sli_block_metadata_t *condition_block, + bool search) +{ + if (search) { + if ((sli_free_lt_list_head == condition_block) || (condition_block == NULL)) { + sli_free_lt_list_head = sli_memory_find_head_free_block(BLOCK_TYPE_LONG_TERM, free_head); + } + if ((sli_free_st_list_head == condition_block) || (condition_block == NULL)) { + sli_free_st_list_head = sli_memory_find_head_free_block(BLOCK_TYPE_SHORT_TERM, free_head); + } + } else { + if (sli_free_lt_list_head == condition_block) { + sli_free_lt_list_head = free_head; + } else if (free_head < sli_free_lt_list_head) { + sli_free_lt_list_head = free_head; + } + if (sli_free_st_list_head == condition_block) { + sli_free_st_list_head = free_head; + } else if (free_head > sli_free_st_list_head) { + sli_free_st_list_head = free_head; + } + } +} + +#ifdef SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES +/***************************************************************************//** + * Gets the pointer to sl_memory_reservation_t{} by block address. + ******************************************************************************/ +sl_memory_reservation_t *sli_memory_get_reservation_handle_by_addr(void *addr) +{ + uint32_t reservation_ix; + reservation_ix = get_reservation_ix_by_addr(addr); + + if (reservation_ix != (uint32_t)-1) { + return sli_reservation_handle_ptr_table[reservation_ix]; + } + + return NULL; +} + +/***************************************************************************//** + * Gets the size of a reservation by block address. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_size_by_addr(void *addr) +{ + sl_memory_reservation_t * reservation_handle_ptr; + reservation_handle_ptr = sli_memory_get_reservation_handle_by_addr(addr); + + if (reservation_handle_ptr != NULL) { + return reservation_handle_ptr->block_size; + } + // Not a reservation, return 0 size. + return 0; +} + +/***************************************************************************//** + * Gets the alignment of a reservation by block address. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_align_by_addr(void *addr) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_reservation_ix_by_addr(addr); + + if (reservation_ix != (uint32_t)-1) { + return sli_reservation_alignment_table[reservation_ix]; + } + + return 0; +} + +/***************************************************************************//** + * Bookkeeps a reservation for profiling purposes. + ******************************************************************************/ +sl_status_t sli_memory_save_reservation_handle(sl_memory_reservation_t *reservation_handle_ptr, + uint32_t align) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_available_reservation_handle_ix(); + + if (reservation_ix != (uint32_t)-1) { + sli_reservation_handle_ptr_table[reservation_ix] = reservation_handle_ptr; + sli_reservation_alignment_table[reservation_ix] = align; + return SL_STATUS_OK; + } else { + return SL_STATUS_FULL; + } +} + +/***************************************************************************//** + * Removes a reservation from records. + ******************************************************************************/ +sl_status_t sli_memory_remove_reservation_handle(sl_memory_reservation_t *reservation_handle_ptr) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_reservation_ix_by_handle(reservation_handle_ptr); + + if (reservation_ix != (uint32_t)-1) { + sli_reservation_handle_ptr_table[reservation_ix] = NULL; + sli_reservation_alignment_table[reservation_ix] = 0; + return SL_STATUS_OK; + } else { + return SL_STATUS_NOT_FOUND; + } +} + +/***************************************************************************//** + * Bookkeeps a reservation (no retention) for profiling purposes. + ******************************************************************************/ +sl_status_t sli_memory_save_reservation_no_retention(void * block_address, uint32_t block_size, uint32_t align) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_available_reservation_no_retention_ix(); + + if (reservation_ix != (uint32_t)-1) { + sli_reservation_no_retention_table[reservation_ix].block_address = block_address; + sli_reservation_no_retention_table[reservation_ix].block_size = block_size; + sli_reservation_no_retention_alignment_table[reservation_ix] = align; + + return SL_STATUS_OK; + } else { + return SL_STATUS_FULL; + } +} + +/***************************************************************************//** + * Gets the size of a reservation (no retention) by block address. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_no_retention_size(void * addr) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_reservation_no_retention_ix(addr); + + if (reservation_ix != (uint32_t)-1) { + return sli_reservation_no_retention_table[reservation_ix].block_size; + } + // Not a reservation (no retention), return 0 size. + return 0; +} + +/***************************************************************************//** + * Gets the alignment of a reservation (no retention) by block address. + ******************************************************************************/ +uint32_t sli_memory_get_reservation_no_retention_align(void * addr) +{ + uint32_t reservation_ix = -1; + reservation_ix = get_reservation_no_retention_ix(addr); + + if (reservation_ix != (uint32_t)-1) { + return sli_reservation_no_retention_alignment_table[reservation_ix]; + } + + return 0; +} + +/***************************************************************************//** + * Does a heap integrity check forwards from sli_free_lt_list_head and return + * the pointer to the corrupted sli_block_metadata_t{} (if applicable). + * This could go past reservations so there are checks. + ******************************************************************************/ +sli_block_metadata_t *sli_memory_check_heap_integrity_forwards(void) +{ + uint64_t * heap_end_by_metadata = 0; + uint32_t is_corrupted = 0; + uint32_t reservation_size; + uint32_t reservation_size_real; + uint32_t alignment; + sli_block_metadata_t* current = sli_free_lt_list_head; + sl_memory_region_t heap_region; + heap_region = sl_memory_get_heap_region(); + + while (current != NULL) { + // Reached last block in heap. + if (current->offset_neighbour_next == 0) { + heap_end_by_metadata = ((uint64_t *)current + (current->length + SLI_BLOCK_METADATA_SIZE_DWORD)); + + // Check if reservation (one or more). + alignment = sli_memory_get_reservation_align_by_addr((void *)heap_end_by_metadata); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)heap_end_by_metadata); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + + while (reservation_size != 0) { + heap_end_by_metadata = (uint64_t *)((uint8_t*)heap_end_by_metadata + reservation_size_real); + alignment = sli_memory_get_reservation_align_by_addr((void *)heap_end_by_metadata); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)heap_end_by_metadata); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + } + + // Check if reservation no retention (one or more). + // Only needed for forwards. + alignment = sli_memory_get_reservation_no_retention_align((void *)heap_end_by_metadata); + reservation_size = sli_memory_get_reservation_no_retention_size((void *)heap_end_by_metadata); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + + while (reservation_size != 0) { + heap_end_by_metadata = (uint64_t *)((uint8_t*)heap_end_by_metadata + reservation_size_real); + alignment = sli_memory_get_reservation_no_retention_align((void *)heap_end_by_metadata); + reservation_size = sli_memory_get_reservation_no_retention_size((void *)heap_end_by_metadata); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + } + + if (heap_end_by_metadata != (void *)((uintptr_t)heap_region.addr + heap_region.size)) { + is_corrupted = 1; + } + break; + } + + // Calculate the address of the next block using offset and length. + sli_block_metadata_t *next_blk_by_offset = (sli_block_metadata_t *)((uint64_t *)current + (current->offset_neighbour_next)); + sli_block_metadata_t *next_blk_by_len = (sli_block_metadata_t *)((uint64_t *)current + (current->length + SLI_BLOCK_METADATA_SIZE_DWORD)); + + // Check if reservation (one or more). + alignment = sli_memory_get_reservation_align_by_addr((void *)next_blk_by_len); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)next_blk_by_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + + while (reservation_size != 0) { + next_blk_by_len = (sli_block_metadata_t *)((uint8_t*)next_blk_by_len + reservation_size_real); + alignment = sli_memory_get_reservation_align_by_addr((void *)next_blk_by_len); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)next_blk_by_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + } + + // Check if reservation no retention (one or more). + // Only needed for forwards. + alignment = sli_memory_get_reservation_no_retention_align((void *)next_blk_by_len); + reservation_size = sli_memory_get_reservation_no_retention_size((void *)next_blk_by_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + + while (reservation_size != 0) { + next_blk_by_len = (sli_block_metadata_t *)((uint8_t*)next_blk_by_len + reservation_size_real); + alignment = sli_memory_get_reservation_no_retention_align((void *)next_blk_by_len); + reservation_size = sli_memory_get_reservation_no_retention_size((void *)next_blk_by_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + } + + if (next_blk_by_offset != next_blk_by_len) { + is_corrupted = 1; + break; + } else { + current = next_blk_by_offset; + } + } + + if (is_corrupted) { + return (sli_block_metadata_t *)current; + } + + return NULL; +} + +/***************************************************************************//** + * Does a heap integrity check backwards from sli_free_st_list_head and return + * the pointer to the corrupted sli_block_metadata_t{} (if applicable). + * This should not go past any reservations, hence there are no checks. + ******************************************************************************/ +sli_block_metadata_t *sli_memory_check_heap_integrity_backwards(void) +{ + uint64_t * heap_base_by_metadata = 0; + uint32_t is_corrupted = 0; + uint32_t reservation_size; + uint32_t reservation_size_real; + uint32_t alignment; + sli_block_metadata_t* current = sli_free_st_list_head; + sl_memory_region_t heap_region; + heap_region = sl_memory_get_heap_region(); + + while (current != NULL) { + // Reached first block in heap. + if (current->offset_neighbour_prev == 0) { + heap_base_by_metadata = ((uint64_t *)current); + if (heap_base_by_metadata != (void *)heap_region.addr) { + is_corrupted = 1; + } + break; + } + + // Calculate the address of the current block using offset and length of the previous block. + sli_block_metadata_t *prev_blk_by_offset = (sli_block_metadata_t *)((uint64_t *)current - (current->offset_neighbour_prev)); + sli_block_metadata_t *current_by_prev_offset = (sli_block_metadata_t *)((uint64_t *)prev_blk_by_offset + (prev_blk_by_offset->offset_neighbour_next)); + sli_block_metadata_t *current_by_prev_len = (sli_block_metadata_t *)((uint64_t *)prev_blk_by_offset + (prev_blk_by_offset->length + SLI_BLOCK_METADATA_SIZE_DWORD)); + + // Check if reservation (one or more). + // This is required when sli_free_st_list_head has reservations before it. + alignment = sli_memory_get_reservation_align_by_addr((void *)current_by_prev_len); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)current_by_prev_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + + while (reservation_size != 0) { + current_by_prev_len = (sli_block_metadata_t *)((uint8_t*)current_by_prev_len + reservation_size_real); + alignment = sli_memory_get_reservation_align_by_addr((void *)current_by_prev_len); + reservation_size = sli_memory_get_reservation_size_by_addr((void *)current_by_prev_len); + if (alignment == SL_MEMORY_BLOCK_ALIGN_DEFAULT) { + reservation_size_real = reservation_size; + } else { + reservation_size_real = SLI_ALIGN_ROUND_UP(reservation_size, alignment); + } + } + + if (current_by_prev_len != current_by_prev_offset) { + is_corrupted = 1; + break; + } else { + current = prev_blk_by_offset; + } + } + + if (is_corrupted) { + return (sli_block_metadata_t *)current; + } + + return NULL; +} +#endif /* SLI_MEMORY_MANAGER_ENABLE_TEST_UTILITIES */ diff --git a/Libs/platform/service/mpu/inc/sl_mpu.h b/Libs/platform/service/mpu/inc/sl_mpu.h new file mode 100644 index 0000000..9c20390 --- /dev/null +++ b/Libs/platform/service/mpu/inc/sl_mpu.h @@ -0,0 +1,85 @@ +/***************************************************************************//** + * @file + * @brief MPU API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup mpu RAM execution disable + * @brief RAM execution disable utilities can be used to disable execution from + * RAM and other selected memory regions. + * @details + * RAM execution disable utilities are useful to protect against code + * injection attacks. + * These utilities make use of MPU to disable execution from RAM and other + * selected memory regions. + * + * @{ + ******************************************************************************/ + +#ifndef SL_MPU_H +#define SL_MPU_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Configures internal SRAM as non-executable and enable MPU. + * + * @note This function configures the MPU in order to make the entire RAM as + * non-executable (with the exception of the functions marked as ramfunc). + ******************************************************************************/ +void sl_mpu_disable_execute_from_ram(void); + +/***************************************************************************//** + * Configures an address range as non-executable and enable MPU. + * + * @note Configures a MPU region in order to make an address range as + * non-executable. The memory region must have a size of at least 32 bytes. + * + * @param address_begin Beginning of memory segment. + * + * @param address_end End of memory segment. + * + * @param size Size of memory segment. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* SL_MPU_H */ + +/** @} (end addtogroup mpu) */ diff --git a/Libs/platform/service/mpu/src/sl_mpu.c b/Libs/platform/service/mpu/src/sl_mpu.c new file mode 100644 index 0000000..a27b007 --- /dev/null +++ b/Libs/platform/service/mpu/src/sl_mpu.c @@ -0,0 +1,493 @@ +/***************************************************************************//** + * @file + * @brief MPU API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_mpu.h" + +#include +#include +#include + +#include "em_device.h" +#include "sl_core.h" + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +#define MPU_MEMORY_ATTRIBUTE_IX_0 0U +#define MPU_MEMORY_ATTRIBUTE_IX_1 1U + +#define MPU_RBAR_BASE_ADDR_NONE 0U +#define MPU_RBAR_AP_READ_WRITE 0U +#define MPU_RBAR_AP_READ_ONLY 1U +#define MPU_RBAR_AP_PRIVILEGED 0U +#define MPU_RBAR_AP_NON_PRIVILEGED 1U +#define MPU_RBAR_XN_EXECUTION 0U +#define MPU_RBAR_XN_NON_EXECUTION 1U + +// Memory region attributes: non-shareable, read-write, non-privileged, non-executable. +#define MPU_RBAR_VALUE ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, \ + ARM_MPU_SH_NON, \ + MPU_RBAR_AP_READ_WRITE, \ + MPU_RBAR_AP_NON_PRIVILEGED, \ + MPU_RBAR_XN_NON_EXECUTION) + +// The MPU Region Limit Address Register defines the ending address of an MPU region. +// Bit [4:0] of the address value is assigned with 0x1F to provide the limit +// address to be checked against. +#define MPU_RLAR_LIMIT_ADDRESS_ALIGNMENT 32U + +// ARM memory map SRAM location and size. +#if defined(_SILICON_LABS_32B_SERIES_2) \ + || (defined(_SILICON_LABS_32B_SERIES_3) && defined(SL_RAM_LINKER)) +#define MPU_ARM_SRAM_MEM_BASE SRAM_BASE + +// This RAM size is not the real device size. It corresponds to the SRAM max size in the standard +// ARM Cortex-M33 memory map. The max size is 0.5GB. +#define MPU_ARM_SRAM_MEM_SIZE SRAM_SIZE + +#elif defined(_SILICON_LABS_32B_SERIES_3) +// These local constants ensure the MPU regions for the secure/non-secure RAM aliases +// and the secure/non-secure RAM non-aliases are properly managed for all +// secure/non-secure project configurations. +#define MPU_RAMFUNC_SRAM_ALIAS_START SRAM_ALIAS_BASE +#define MPU_RAMFUNC_SRAM_ALIAS_END (SRAM_ALIAS_BASE + (SRAM_SIZE - 1U)) + +#define MPU_DATA_SRAM_START SRAM_BASE +#define MPU_DATA_SRAM_END (SRAM_BASE + (SRAM_SIZE - 1U)) + +#if defined(SL_TRUSTZONE_SECURE) +#define MPU_NOT_USED_SRAM_ALIAS_START DMEM_INSTR_NS_MEM_BASE +#define MPU_NOT_USED_SRAM_ALIAS_END DMEM_INSTR_NS_MEM_END + +#define MPU_NOT_USED_SRAM_START DMEM_NS_MEM_BASE +#define MPU_NOT_USED_SRAM_END DMEM_NS_MEM_END +#else +#define MPU_NOT_USED_SRAM_ALIAS_START DMEM_INSTR_S_MEM_BASE +#define MPU_NOT_USED_SRAM_ALIAS_END DMEM_INSTR_S_MEM_END + +#define MPU_NOT_USED_SRAM_START DMEM_S_MEM_BASE +#define MPU_NOT_USED_SRAM_END DMEM_S_MEM_END +#endif +#endif + +#if defined(__ICCARM__) +// iccarm +#pragma section = "text_ram" +#define RAMFUNC_SECTION_BEGIN ((uint32_t)(uint32_t *)__section_begin("text_ram")) +#define RAMFUNC_SECTION_END ((uint32_t)(uint32_t *)__section_end("text_ram")) +#define RAMFUNC_SECTION_SIZE __section_size("text_ram") + +#elif defined(__GNUC__) +// armgcc +extern uint32_t __vma_ramfuncs_start__; +extern uint32_t __vma_ramfuncs_end__; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &__vma_ramfuncs_start__ +#define RAMFUNC_SECTION_END (uint32_t) &__vma_ramfuncs_end__ +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#elif defined(__CC_ARM) +// armcc +// The section name in the armcc scatter file must be "ram_code". +extern uint32_t ram_code$$Base; +extern uint32_t ram_code$$Limit; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &ram_code$$Base +#define RAMFUNC_SECTION_END (uint32_t) &ram_code$$Limit +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +static uint32_t region_nbr = 0; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * Configures internal SRAM as non-executable and enable MPU. + * + * @note (1) On series 2 devices, the MPU regions configuration for the RAM layout + * is for GCC and IAR: + * + * MPU Region Region Attributes Adresses Range + * ------------------------------------------------------------------------ + * 0x2000_0000 0x2007_FFFF (DATA, RAMFUNC) 0 non shareable, executable RAMFunc start to RAMFunc end + * 1 non shareable, non executable RAMFunc end to range end + * or + * 0x2000_0000 0x2007_FFFF (DATA) 0 shareable, non executable Entire range + * + * @note (2) On series 3 SIXG301 devices, there are the following RAM-related + * address ranges. + * - 0x0080_0000 0x0087_FFFF (Alias to DMEM_NS) - Non-secure + * - 0x1080_0000 0x1087_FFFF (Alias to DMEM (execute only)) -Secure + * - 0x2000_0000 0x2007_FFFF (DMEM_NS) - Non-secure + * - 0x3000_0000 0x3007_FFFF (DMEM) - Secure + * + * The MPU regions are configured differently depending on the RAM layout + * described in GCC and IAR linker scripts. A common characteristic + * to all the MPU regions for GCC and IAR is: + * - All MPU regions for RAM are non-cacheable. + * + * The table below presents the MPU regions for series 3 SIXG301 devices. + * The table assumes there are RAMFunc in RAM. If there are no RAMFunc + * functions, then the associated region will be a single region covering + * the full addresses range. + * + * GCC + * --- + * MPU Region* Region Attributes Adresses Range + * ------------------------------------------------------------------------ + * 0x0080_0000 0x0087_FFFF (RAMFUNC)* 0 shareable, executable RAMFunc start to RAMFunc end + * 1 non shareable, non executable RAMFunc end to range end + * or + * 0x0080_0000 0x0087_FFFF (NOT USED)* x non shareable, non executable Entire range (if no RAMFunc) + * + * 0x1080_0000 0x1087_FFFF (NOT USED)* 2 non shareable, non executable Entire range + * 0x2000_0000 0x2007_FFFF (DATA)* 3 shareable, non executable Entire range + * 0x3000_0000 0x3007_FFFF (NOT USED)* 4 non shareable, non executable Entire range + * + * IAR + * --- + * MPU Region* Region Attributes Adresses Range + * ------------------------------------------------------------------------ + * 0x0080_0000 0x0087_FFFF (NOT USED)* 0 non shareable, non executable Entire range + * 0x1080_0000 0x1087_FFFF (NOT USED)* 1 non shareable, non executable Entire range + * 0x2000_0000 0x2007_FFFF (DATA, RAMFUNC)* 2 shareable, non executable Range start to RAMFunc start + * 3 shareable, executable RAMFunc start to RAMFunc end + * 4 shareable, non executable RAMFunc end to range end + * or + * 0x2000_0000 0x2007_FFFF (NOT USED)* x non shareable, non executable Entire range (if no RAMFunc) + * + * 0x3000_0000 0x3007_FFFF (NOT USED)* 5 non shareable, non executable Entire range + + * *If the ARM Cortex-M33 works in non-secure, all non-secure alias/ + * non-alias will be used by default for RAMfunc and data in RAM. + * Same logic if the Cortex-M33 is in secure, all secure alias/non-alias + * will be used by default. The MPU regions creation will adapt to + * the default secure or non-secure addresses. And thus the order + * in which the MPU regions are created can vary. + *****************************************************************************/ +void sl_mpu_disable_execute_from_ram(void) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + uint32_t rbar; + + ARM_MPU_Disable(); + + // See Note #1. +#if defined(_SILICON_LABS_32B_SERIES_2) \ + || (defined(_SILICON_LABS_32B_SERIES_3) && defined(SL_RAM_LINKER)) + // Memory attributes: + // Outer memory with ARM_MPU_ATTR_MEMORY_(): non-transient data, Write-Through, cache allocation on read miss, no cache allocation on write miss. + // ARM_MPU_ATTR(): outer attributes filled, no inner memory + ARM_MPU_SetMemAttr(MPU_MEMORY_ATTRIBUTE_IX_0, + ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), 0)); + + // Region end address LSB are always considered 0x1F. + mpu_region_begin = MPU_ARM_SRAM_MEM_BASE; + mpu_region_end = (RAMFUNC_SECTION_SIZE > 0) ? (RAMFUNC_SECTION_BEGIN & MPU_RBAR_BASE_Msk) - MPU_RLAR_LIMIT_ADDRESS_ALIGNMENT + : (MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE); + + // Define initial MPU region: either 1 unique region = entire RAM. Or 1 region = from RAM START to RAMFUNC START. + if (mpu_region_begin <= mpu_region_end) { + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + } + + // Only if functions placed in RAM, define another region from RAMFUNC END to RAM END. + if (RAMFUNC_SECTION_SIZE > 0u) { + // Region end address LSB are always considered 0x1F. + mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; + mpu_region_end = MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE - MPU_RLAR_LIMIT_ADDRESS_ALIGNMENT; + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); + region_nbr++; + } + + // See Note #2. +#elif (defined(_SILICON_LABS_32B_SERIES_3) && !defined(SL_RAM_LINKER)) + // 1. Set the memory attributes for the entire RAM (alias and non-alias ranges). + // Outer & inner memories: non-cacheable. + ARM_MPU_SetMemAttr(MPU_MEMORY_ATTRIBUTE_IX_0, + ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + // 2. Create different MPU regions accounting for all RAM addresses ranges (secure/non-secure alias/non-alias) + // Secure or non secure alias (not used): 1 region (non shareable, non cacheable, non executable) + mpu_region_begin = MPU_NOT_USED_SRAM_ALIAS_START; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_NON, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_NOT_USED_SRAM_ALIAS_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + + // Non secure or secure alias (used for code if functions placed in RAM): +#if defined(__GNUC__) + if (RAMFUNC_SECTION_SIZE > 0u) { + // Functions placed in RAM: 1 region (shareable, non cacheable, executable) + mpu_region_begin = RAMFUNC_SECTION_BEGIN; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_OUTER, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (RAMFUNC_SECTION_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + + // Rest of the non secure or secure alias: non shareable, non cacheable, non executable + mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; // +31u allows to round up to the next 32 bytes alignment. + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_NON, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_RAMFUNC_SRAM_ALIAS_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + } else { +#endif + // No functions placed in RAM: 1 region (non shareable, non cacheable, non executable) + mpu_region_begin = MPU_RAMFUNC_SRAM_ALIAS_START; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_NON, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_RAMFUNC_SRAM_ALIAS_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; +#if defined(__GNUC__) +} +#endif + + // Secure or non secure non alias (used for data): 1 region (shareable, non cacheable, non executable) +#if defined(__ICCARM__) + if (RAMFUNC_SECTION_SIZE > 0u) { + // Beginning of non secure alias: shareable, non cacheable, non executable + mpu_region_begin = MPU_DATA_SRAM_START; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_OUTER, + MPU_RBAR_AP_READ_WRITE, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = ((RAMFUNC_SECTION_BEGIN - 1u) & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + + // Functions placed in RAM: 1 region (shareable, non cacheable, executable) + mpu_region_begin = RAMFUNC_SECTION_BEGIN; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_OUTER, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (RAMFUNC_SECTION_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + + // Rest of non secure alias: shareable, non cacheable, non executable + mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; // +31u allows to round up to the next 32 bytes alignment. + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_OUTER, + MPU_RBAR_AP_READ_WRITE, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_DATA_SRAM_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; + } else { +#endif + mpu_region_begin = MPU_DATA_SRAM_START; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_OUTER, + MPU_RBAR_AP_READ_WRITE, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_DATA_SRAM_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; +#if defined(__ICCARM__) +} +#endif + + // Non secure or secure non alias (not used): 1 region (non shareable, non cacheable, non executable) + mpu_region_begin = MPU_NOT_USED_SRAM_START; + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_NON, + MPU_RBAR_AP_READ_ONLY, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + mpu_region_end = (MPU_NOT_USED_SRAM_END & MPU_RLAR_LIMIT_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_0)); + region_nbr++; +#else + (void)rbar; + (void)mpu_region_begin; + (void)mpu_region_end; +#endif + + // Enable MPU with default background region. + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); +} + +/**************************************************************************//** + * Enables simplified MPU driver. Configures memory address as non-executable. + *****************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + sl_status_t status = SL_STATUS_OK; + + // Ensure there is still an available MPU region to configure. + if (region_nbr > MPU_RNR_REGION_Msk) { + status = SL_STATUS_NO_MORE_RESOURCE; + } + + ARM_MPU_Disable(); + + uint32_t rbar; + uint8_t is_overlapping = 0u; + uint32_t prev_base_address = 0u; + uint32_t prev_limit_address = 0u; + + // Size of memory region must be 32 bytes or more. + if (size >= 32u) { + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_begin = ((address_begin % 32u) == 0u) ? address_begin + : (address_begin + (32u - (address_begin % 32u))); + + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_end = ((address_end % 32u) == 0u) ? address_end + : (address_end - (address_end % 32u)); + + // The scanning to check the overlapping region + for (uint8_t index_region = 0; index_region < region_nbr; index_region++) { + // Set to the previous region number + MPU->RNR = index_region; + + // Read the base address that was configured by the region number register before + prev_base_address = (MPU->RBAR & MPU_RBAR_BASE_Msk); + // Read the limit address that was configured by the region number register before + prev_limit_address = (MPU->RLAR & MPU_RLAR_LIMIT_Msk); + + // Check the overlapping region + if ((mpu_region_begin == prev_base_address) && (mpu_region_end == prev_limit_address)) { + // The new region is the same as the previous region + is_overlapping = 1; + status = SL_STATUS_OK; + } else if (!((mpu_region_begin > prev_limit_address) || (mpu_region_end < prev_base_address))) { + // The new region is invalid + is_overlapping = 1; + status = SL_STATUS_INVALID_RANGE; + } + + if (is_overlapping == 1) { + break; + } + + MPU->RNR &= ~MPU_RNR_REGION_Msk; + } + + // Set specified memory region if no overlap has been detected. + if (!is_overlapping) { + // Device memory type non Gathering, non Re-ordering, Early Write Acknowledgment + ARM_MPU_SetMemAttr(MPU_MEMORY_ATTRIBUTE_IX_1, ARM_MPU_ATTR_DEVICE_nGnRE); + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + // Memory region attributes: non-shareable, read-write, non-privileged, non-executable + rbar = ARM_MPU_RBAR(MPU_RBAR_BASE_ADDR_NONE, + ARM_MPU_SH_NON, + MPU_RBAR_AP_READ_WRITE, + MPU_RBAR_AP_NON_PRIVILEGED, + MPU_RBAR_XN_NON_EXECUTION) + | (mpu_region_begin & MPU_RBAR_BASE_Msk); + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, MPU_MEMORY_ATTRIBUTE_IX_1)); + CORE_EXIT_ATOMIC(); + region_nbr++; + } + } + + // Enable MPU with default background region + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); + + return status; +} + +#if __CORTEX_M != (0u) +/**************************************************************************//** + * MemManage default exception handler. Reset target. + *****************************************************************************/ +__WEAK void mpu_fault_handler(void) +{ + // Force fail assert to trigger reset + __NVIC_SystemReset(); +} + +/**************************************************************************//** + * MemManage exception handler. + *****************************************************************************/ +void MemManage_Handler(void) +{ + mpu_fault_handler(); +} +#endif diff --git a/Libs/platform/service/power_manager/inc/sl_power_manager.h b/Libs/platform/service/power_manager/inc/sl_power_manager.h new file mode 100644 index 0000000..9e9336c --- /dev/null +++ b/Libs/platform/service/power_manager/inc/sl_power_manager.h @@ -0,0 +1,591 @@ +/***************************************************************************//** + * @file + * @brief Power Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_POWER_MANAGER_H +#define SL_POWER_MANAGER_H + +#ifndef SL_POWER_MANAGER_DEBUG +#include "sl_power_manager_config.h" +#endif +#include "sl_slist.h" +#include "sl_status.h" +#include "sl_sleeptimer.h" +#include "sl_enum.h" +#include "sl_core.h" +#include "sl_code_classification.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup power_manager Power Manager + * + * @details Power manager is a platform level software module that manages + * the system's energy modes. Its main purpose is to transition the system to a + * low energy mode when the processor has nothing to execute. The energy mode the + * system will transition to is determined each time the system goes to sleep + * using requirements. These requirements are set by the different software modules + * (drivers, stacks, application code, etc...). Power manager also ensures a + * strict control of some power hungry resources such as the high frequency + * external oscillator (normally called HFXO). Power manager also + * offers a notification mechanism through which any piece of software module can be + * notified of energy mode transitions through callbacks. + * + * @note Sleep Driver is deprecated. Use Power Manager for all sleep-related + * operations. See AN1358: + * Migrating from Sleep Driver to Power Manager for information on how + * to migrate from Sleep Driver to Power Manager. + * @note Emlib EMU functions EMU_EnterEM1()/EMU_EnterEM2()/EMU_EnterEM3() must not + * be used when the Power Manager is present. The Power Manager module must be + * the one deciding at which EM level the device sleeps to ensure the application + * properly works. Using both at the same time could lead to undefined behavior + * in the application. + * + * @details + * ## Initialization + * + * Power manager must be initialized prior to any call to power manager API. + * If sl_system is used, only sl_system_init() must be called, otherwise + * sl_power_manager_init() must be called manually. Note that power manager + * must be initialized after the clock(s), when initialized manually, as the + * power manager check which oscillators are used during the initialization phase. + * + * ## Add and remove requirements + * + * The drivers should add and remove energy mode requirements, at runtime, on the + * lowest energy mode for them depending on their state. When calling + * sl_power_manager_sleep(), the lowest possible Energy mode will be automatically + * selected. + * + * It is possible to add and remove requirements from ISR. If a specific energy mode + * is required in the ISR, but not required to generate the interrupt, a requirement + * on the energy mode can be added from the ISR. It is guaranteed that the associated + * clock will be active once sl_power_manager_add_requirement() returns. The EM + * requirement can be also be removed from an ISR. + * + * Requirements should not be removed if it was not previously added. + * + * ## Subscribe to events + * + * It possible to get notified when the system transition from a power level to + * another power level. This can allow to do some operations depending on which level + * the system goes, such as saving/restoring context. + * + * ## Sleep + * + * When the software has no more operation and only need to wait for an event, the + * software must call sl_power_manager_sleep(). This is automatically done when the + * kernel is present, but it needs to be called from the super loop in a baremetal + * project. + * + * ## Query callback functions + * + * ### Is OK to sleep + * + * Between the time `sl_power_manager_sleep` is called and the MCU is really put + * in a lower Energy mode, it is possible that an ISR occur and require the system + * to resume at that time instead of sleeping. So a callback is called in a critical + * section to validate that the MCU can go to sleep. + * + * In case of an application that runs on an RTOS, the RTOS will take care of determining + * if it is ok to sleep. In case of a baremetal application, the function `sl_power_manager_is_ok_to_sleep()` + * will be generated automatically by Simplicity Studio's wizard. + * The function will look at multiple software modules from the SDK to take a decision. + * The application can contribute to the decision by defining the function `app_is_ok_to_sleep()`. + * If any of the software modules (including the application via `app_is_ok_to_sleep()`) return false, + * the process of entering in sleep will be aborted. + * + * ### Sleep on ISR exit + * + * When the system enters sleep, the only way to wake it up is via an interrupt or + * exception. By default, power manager will assume that when an interrupt + * occurs and the corresponding ISR has been executed, the system must not go back + * to sleep. However, in the case where all the processing related to this interrupt + * is performed in the ISR, it is possible to go back to sleep by using this hook. + * + * In case of an application that runs on an RTOS, the RTOS will take care of determining + * if the system can go back to sleep on ISR exit. Power manager will ensure the system resumes + * its operations as soon as a task is resumed, posted or that its delay expires. + * In case of a baremetal application, the function `sl_power_manager_sleep_on_isr_exit()` will be generated + * automatically by Simplicity Studio's wizard. The function will look at multiple software modules from the SDK + * to take a decision. The application can contribute to the decision by defining the + * function `app_sleep_on_isr_exit()`. + * The generated function will take a decision based on the value returned by the different software modules + * (including the application via `app_sleep_on_isr_exit()`): + * + * `SL_POWER_MANAGER_IGNORE`: if the software module did not cause the system wakeup and/or doesn't want to contribute to the decision. + * `SL_POWER_MANAGER_SLEEP`: if the software module did cause the system wakeup, but the system should go back to sleep. + * `SL_POWER_MANAGER_WAKEUP`: if the software module did cause the system wakeup, and the system should not go back to sleep. + * + * If any software module returned `SL_POWER_MANAGER_SLEEP` and none returned `SL_POWER_MANAGER_WAKEUP`, + * the system will go back to sleep. Any other combination will cause the system not to go back to sleep. + * + * ### Debugging feature + * + * By setting the configuration define SL_POWER_MANAGER_DEBUG to 1, it is possible + * to record the requirements currently set and their owner. It is possible to print + * at any time a table that lists all the added requirements and their owner. This + * table can be printed by caling the function + * sl_power_manager_debug_print_em_requirements(). + * Make sure to add the following define + * ``` + * #define CURRENT_MODULE_NAME "" + * ``` + * to any application code source file that adds and removes requirements. + * + * ## Usage Example + * + * ``` + * #define EM_EVENT_MASK_ALL (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) + * + * sl_power_manager_em_transition_event_handle_t event_handle; + * sl_power_manager_em_transition_event_info_t event_info = { + * .event_mask = EM_EVENT_MASK_ALL, + * .on_event = my_events_callback, + * } + * + * void main(void) + * { + * // Initialize power manager; not needed if sl_system_init() is used. + * sl_power_manager_init(); + * + * // Limit sleep level to EM1 + * sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + * + * // Subscribe to all event types; get notified for every power transition. + * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); + * while (1) { + * // Actions + * [...] + * if (completed) { + * // Remove energy mode requirement, can go to EM2 or EM3 now, depending on the configuration + * sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + * } + * + * // Sleep to lowest possible energy mode; This call is not needed when using the kernel. + * sl_power_manager_sleep(); + * // Will resume after an interrupt or exception + * } + * } + * + * void my_events_callback(sl_power_manager_em_t from, + * sl_power_manager_em_t to) + * { + * printf("Event:%s-%s\r\n", string_lookup_table[from], string_lookup_table[to]); + * } + * ``` + * + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +// Current module name for debugging features +#ifndef CURRENT_MODULE_NAME +#define CURRENT_MODULE_NAME "Anonymous" ///< current module name +#endif + +// Power transition events +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 (1 << 0) ///< sl power manager event transition entering em0 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 (1 << 1) ///< sl power manager event transition leaving em0 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 (1 << 2) ///< sl power manager event transition entering em1 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 (1 << 3) ///< sl power manager event transition leaving em1 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 (1 << 4) ///< sl power manager event transition entering em2 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 (1 << 5) ///< sl power manager event transition leaving em2 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 (1 << 6) ///< sl power manager event transition entering em3 (DEPRECATED) +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3 (1 << 7) ///< sl power manager event transition leaving em3 (DEPRECATED) + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Energy modes +typedef enum { + SL_POWER_MANAGER_EM0 = 0, ///< Run Mode (Energy Mode 0) + SL_POWER_MANAGER_EM1, ///< Sleep Mode (Energy Mode 1) + SL_POWER_MANAGER_EM2, ///< Deep Sleep Mode (Energy Mode 2) + SL_POWER_MANAGER_EM3, ///< Stop Mode (Energy Mode 3) + SL_POWER_MANAGER_EM4, ///< Shutoff Mode (Energy Mode 4) +} sl_power_manager_em_t; + +/// @brief Mask of all the event(s) to listen to. +typedef uint32_t sl_power_manager_em_transition_event_t; + +/***************************************************************************//** + * Typedef for the user supplied callback function which is called when + * an energy mode transition occurs. + * + * @param from Energy mode we are leaving. + * @param to Energy mode we are entering. + ******************************************************************************/ +typedef void (*sl_power_manager_em_transition_on_event_t)(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +/// @brief Struct representing energy mode transition event information +typedef struct { + const sl_power_manager_em_transition_event_t event_mask; ///< Mask of the transitions on which the callback should be called. + const sl_power_manager_em_transition_on_event_t on_event; ///< Function that must be called when the event occurs. +} sl_power_manager_em_transition_event_info_t; + +/// @brief Struct representing energy mode transition event handle +typedef struct { + sl_slist_node_t node; ///< List node. + const sl_power_manager_em_transition_event_info_t *info; ///< Handle event info. +} sl_power_manager_em_transition_event_handle_t; + +/// On ISR Exit Hook answer +SL_ENUM(sl_power_manager_on_isr_exit_t) { + SL_POWER_MANAGER_IGNORE = (1UL << 0UL), ///< The module did not trigger an ISR and it doesn't want to contribute to the decision + SL_POWER_MANAGER_SLEEP = (1UL << 1UL), ///< The module was the one that caused the system wakeup and the system SHOULD go back to sleep + SL_POWER_MANAGER_WAKEUP = (1UL << 2UL), ///< The module was the one that caused the system wakeup and the system MUST NOT go back to sleep +}; + +// ----------------------------------------------------------------------------- +// Internal Prototypes only to be used by Power Manager module +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, + bool add); + +// To make sure that we are able to optimize out the string argument when the +// debug feature is disable, we use a pre-processor macro resulting in a no-op. +// We also make sure to always have a definition for the function regardless if +// the debug feature is enable or not for binary compatibility. +#if (SL_POWER_MANAGER_DEBUG == 1) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, + bool add, + const char *name); +#else +#define sli_power_manager_debug_log_em_requirement(em, add, name) /* no-op */ +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Initialize Power Manager module. + * @return Status code + ******************************************************************************/ +sl_status_t sl_power_manager_init(void); + +/***************************************************************************//** + * Sleep at the lowest allowed energy mode. + * + * @note Must not be called from ISR + * @par + * @note This function will expect and call a callback with the following + * signature: `bool sl_power_manager_is_ok_to_sleep(void)`. + * + * @note This function can be used to cancel a sleep action and handle the + * possible race condition where an ISR that would cause a wakeup is + * triggered right after the decision to call sl_power_manager_sleep() + * has been made. + * + * @note This function must NOT be called with interrupts disabled. This means + * both BASEPRI and PRIMASK MUST have a value of 0 when invoking this + * function. + * + * Usage example: + * + * ```c + * void main(void) + * { + * sl_power_manager_init(); + * while (1) { + * tick(); + * sl_power_manager_sleep(); + * } + * } + * ``` + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sl_power_manager_sleep(void); + +/***************************************************************************//** + * Adds requirement on given energy mode. + * + * @param em Energy mode to add the requirement to: + * - ::SL_POWER_MANAGER_EM1 + * - ::SL_POWER_MANAGER_EM2 (DEPRECATED) + * + * @note Adding EM requirements on SL_POWER_MANAGER_EM2 is now DEPRECATED. + * The calls can simply be removed since the system will go to deepsleep + * (EM2/EM3) in the absence of EM1 requirements. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE void sl_power_manager_add_em_requirement(sl_power_manager_em_t em) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_power_manager_update_em_requirement(em, true); + + sli_power_manager_debug_log_em_requirement(em, true, (const char *)CURRENT_MODULE_NAME); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Removes requirement on given energy mode. + * + * @param em Energy mode to remove the requirement to: + * - ::SL_POWER_MANAGER_EM1 + * - ::SL_POWER_MANAGER_EM2 (DEPRECATED) + * + * @note Removing EM requirements on SL_POWER_MANAGER_EM2 is now DEPRECATED. + * The calls can simply be removed since the system will go to deepsleep + * (EM2/EM3) in the absence of EM1 requirements. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE void sl_power_manager_remove_em_requirement(sl_power_manager_em_t em) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_power_manager_update_em_requirement(em, false); + + sli_power_manager_debug_log_em_requirement(em, false, (const char *)CURRENT_MODULE_NAME); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Registers a callback to be called on given Energy Mode transition(s). + * + * @param event_handle Event handle (no initialization needed). + * + * @param event_info Event info structure that contains the event mask and the + * callback that must be called. + * + * @note Adding and removing requirement(s) from a callback on a transition event + * is not supported. + * + * @note The parameters passed must be persistent, meaning that they need to survive + * until the callback fires. + * + * @note SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 and + * SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3 are now DEPRECATED and should + * not be used in the event_info argument. + * + * Usage example: + * + * ```c + * #define EM_EVENT_MASK_ALL ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2) + * + * sl_power_manager_em_transition_event_handle_t event_handle; + * sl_power_manager_em_transition_event_info_t event_info = { + * .event_mask = EM_EVENT_MASK_ALL, + * .on_event = my_callback, + * }; + * + * void my_callback(sl_power_manager_em_t from, + * sl_power_manager_em_t to) + * { + * [...] + * } + * + * void main(void) + * { + * sl_power_manager_init(); + * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); + * } + * ``` + ******************************************************************************/ +void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, + const sl_power_manager_em_transition_event_info_t *event_info); + +/***************************************************************************//** + * Unregisters an event callback handle on Energy mode transition. + * + * @param event_handle Event handle which must be unregistered (must have been + * registered previously). + * + * @note An EFM_ASSERT is thrown if the handle is not found. + ******************************************************************************/ +void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle); + +/***************************************************************************//** + * Get configurable overhead value for early restore time in Sleeptimer ticks + * when a schedule wake-up is set. + * + * @return Current overhead value for early restore time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void); + +/***************************************************************************//** + * Set configurable overhead value for early restore time in Sleeptimer ticks + * used for schedule wake-up. + * Must be called after initialization else the value will be overwritten. + * + * @param overhead_tick Overhead value to set for early restore time. + * + * @note The overhead value can also be negative to remove time from the restore + * process. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick); + +/***************************************************************************//** + * Get configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @return Current minimum off-time value for schedule wake-up. + * + * @note Turning on external high frequency clock, such as HFXO, requires more + * energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency clock enable' is scheduled + * in 'x' time, there is a threshold 'x' value where turning off the clock + * is not worthwhile since the energy consumed by taking into account the + * wake-up will be greater than if we just keep the clock on until the next + * scheduled clock enabled. This threshold value is what we refer as the + * minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void); + +/***************************************************************************//** + * Set configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @param minimum_offtime_tick minimum off-time value to set for schedule + * wake-up. + * + * @note Turning on external high frequency clock, such as HFXO, requires more + * energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency clock enable' is scheduled + * in 'x' time, there is a threshold 'x' value where turning off the clock + * is not worthwhile since the energy consumed by taking into account the + * wake-up will be greater than if we just keep the clock on until the next + * scheduled clock enabled. This threshold value is what we refer as the + * minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick); + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @param enable True False variable act as a switch for this api + * + * @note Will also update the wake up time from EM2 to EM0. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); + +/**************************************************************************//** + * Determines if the HFXO interrupt was part of the last wake-up and/or if + * the HFXO early wakeup expired during the last ISR + * and if it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + * + * @note This function will always return false in case a requirement + * is added on SL_POWER_MANAGER_EM1, since we will + * never sleep at a lower level than EM1. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_power_manager_is_latest_wakeup_internal(void); + +/***************************************************************************//** + * Enter energy mode 4 (EM4). + * + * @note You should not expect to return from this function. Once the device + * enters EM4, only a power on reset or external reset pin can wake the + * device. + * + * @note On xG22 devices, this function re-configures the IADC if EM4 entry + * is possible. + ******************************************************************************/ +void sl_power_manager_enter_em4(void); + +/***************************************************************************//** + * When EM4 pin retention is set to power_manager_pin_retention_latch, + * then pins are retained through EM4 entry and wakeup. The pin state is + * released by calling this function. The feature allows peripherals or + * GPIO to be re-initialized after EM4 exit (reset), and when + * initialization is done, this function can release pins and return + * control to the peripherals or GPIO. + * + * @note When the EM4 Pin Retention feature is not available on a device, + * calling this function will do nothing. + ******************************************************************************/ +void sl_power_manager_em4_unlatch_pin_retention(void); + +/***************************************************************************//** + * Energy mode 4 pre-sleep hook function. + * + * @note This function is called by @ref sl_power_manager_enter_em4 just + * prior to the sequence of writes to put the device in EM4. The + * function implementation does not perform anything, but it is + * SL_WEAK so that it can be re-implemented in application code if + * actions are needed. + ******************************************************************************/ +void sl_power_manager_em4_presleep_hook(void); + +/** @} (end addtogroup power_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_POWER_MANAGER_H diff --git a/Libs/platform/service/power_manager/inc/sl_power_manager_debug.h b/Libs/platform/service/power_manager/inc/sl_power_manager_debug.h new file mode 100644 index 0000000..6376ab7 --- /dev/null +++ b/Libs/platform/service/power_manager/inc/sl_power_manager_debug.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief Power Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_POWER_MANAGER_DEBUG_H +#define SL_POWER_MANAGER_DEBUG_H + +#include "sl_power_manager.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup power_manager + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Print a table that describes the current requirements on each energy + * mode and their owner. + ******************************************************************************/ +void sl_power_manager_debug_print_em_requirements(void); + +/** @} (end addtogroup power_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Libs/platform/service/power_manager/inc/sli_power_manager.h b/Libs/platform/service/power_manager/inc/sli_power_manager.h new file mode 100644 index 0000000..1e2b9d4 --- /dev/null +++ b/Libs/platform/service/power_manager/inc/sli_power_manager.h @@ -0,0 +1,172 @@ +/***************************************************************************//** + * @file + * @brief Power Manager Private API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_POWER_MANAGER_H +#define SLI_POWER_MANAGER_H + +#include "sl_power_manager.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ****************************** HOOK REFERENCES **************************** + ******************************************************************************/ + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_power_manager_sleep_on_isr_exit(void); + +// Callback to application after wakeup but before restoring interrupts. +// For internal Silicon Labs use only +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_on_wakeup(void); + +// Hook that can be used by the log outputer to suspend transmission of logs +// in case it would require energy mode changes while in the sleep loop. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_suspend_log_transmission(void); + +// Hook that can be used by the log outputer to resume transmission of logs. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_resume_log_transmission(void); + +// Callback to notify possible transition from EM1P to EM2. +// For internal Silicon Labs use only +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_em1p_to_em2_notification(void); + +/***************************************************************************//** + * Mandatory callback that allows to cancel sleeping action. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_power_manager_is_ok_to_sleep(void); + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add); + +/***************************************************************************//** + * Adds requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with adding an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_add_hf_clock_settings_preservation_requirement(void); + +/***************************************************************************//** + * Removes requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with removing an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void); + +/***************************************************************************//** + * Informs the power manager module that the high accuracy/high frequency clock + * is used. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be called by RAIL initialization in case radio clock settings + * are not set before the Power Manager initialization. + ******************************************************************************/ +__WEAK void sli_power_manager_set_high_accuracy_hf_clock_as_used(void); + +/***************************************************************************//** + * Gets the wake-up restore process time. + * If we are not in the context of a deepsleep and therefore don't need to + * do a restore, the return value is 0. + * + * + * @return Wake-up restore process time. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sli_power_manager_get_restore_delay(void); + +/***************************************************************************//** + * Initiates the wake-up restore process. + ******************************************************************************/ +void sli_power_manager_initiate_restore(void); + +/***************************************************************************//** + * Performs pre sleep operations. + * + * @note Must only be called by the RTOS integration code. + ******************************************************************************/ +void sli_power_manager_pre_sleep(void); + +/***************************************************************************//** + * Fetches current energy mode + * + * @return Returns current energy mode + ******************************************************************************/ +sl_power_manager_em_t sli_power_manager_get_current_em(void); + +/***************************************************************************//** + * Update Energy Mode 4 configurations. + ******************************************************************************/ +void sli_power_manager_init_em4(void); + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + ******************************************************************************/ +void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); + +/***************************************************************************//** + * Initializes energy mode transition list. + ******************************************************************************/ +void sli_power_manager_em_transition_event_list_init(void); + +/***************************************************************************//** + * Notify subscribers about energy mode transition. + * + * @param from Energy mode from which CPU comes from. + * + * @param to Energy mode to which CPU is going to. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_POWER_MANAGER_H */ diff --git a/Libs/platform/service/power_manager/src/common/sl_power_manager_common.c b/Libs/platform/service/power_manager/src/common/sl_power_manager_common.c new file mode 100644 index 0000000..ffff08e --- /dev/null +++ b/Libs/platform/service/power_manager/src/common/sl_power_manager_common.c @@ -0,0 +1,213 @@ +/***************************************************************************//** + * @file + * @brief Power Manager common API implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager.h" +#include "sli_clock_manager.h" +#include "sl_assert.h" +#include "sl_atomic.h" +#include "sl_clock_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "em_device.h" +#if !defined(_SILICON_LABS_32B_SERIES_3) +#include "em_emu.h" +#else +#include "sli_power_manager_execution_modes_private.h" +#endif + +#include +#include +#include + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Events subscribers lists +static sl_slist_node_t *power_manager_em_transition_event_list = NULL; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Last-chance check before sleep. + * + * @return True, if the system should actually sleep. + * False, if not. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_is_ok_to_sleep(void) +{ + return true; +} + +/***************************************************************************//** + * Check if the MCU can sleep after an interrupt. + * + * @return True, if the system can sleep after the interrupt. + * False, otherwise. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_sleep_on_isr_exit(void) +{ + return false; +} + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) +{ +#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(enable); + + CORE_EXIT_CRITICAL(); +#else + (void)enable; +#endif +} + +/***************************************************************************//** + * Registers a callback to be called on given Energy Mode transition(s). + * + * @note Adding/Removing requirement(s) from the callback is not supported. + ******************************************************************************/ +void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, + const sl_power_manager_em_transition_event_info_t *event_info) +{ + CORE_DECLARE_IRQ_STATE; + + event_handle->info = event_info; + CORE_ENTER_CRITICAL(); + sl_slist_push(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Unregisters an event callback handle on Energy mode transition. + ******************************************************************************/ +void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sl_slist_remove(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Initializes energy mode transition list. + ******************************************************************************/ +void sli_power_manager_em_transition_event_list_init(void) +{ + sl_slist_init(&power_manager_em_transition_event_list); +} + +/***************************************************************************//** + * Notify subscribers about energy mode transition. + ******************************************************************************/ +void sli_power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + sl_power_manager_em_transition_event_handle_t *handle; + sl_power_manager_em_transition_event_t transition = 0; + + switch (to) { + case SL_POWER_MANAGER_EM0: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2; + break; + +#if !defined(SL_CATALOG_POWER_MANAGER_ARM_SLEEP_ON_EXIT) + case SL_POWER_MANAGER_EM3: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3; + break; +#endif + + default: + EFM_ASSERT(0); + } + + switch (from) { + case SL_POWER_MANAGER_EM0: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2; + break; + +#if !defined(SL_CATALOG_POWER_MANAGER_ARM_SLEEP_ON_EXIT) + case SL_POWER_MANAGER_EM3: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3; + break; +#endif + + default: + EFM_ASSERT(0); + } + + SL_SLIST_FOR_EACH_ENTRY(power_manager_em_transition_event_list, handle, sl_power_manager_em_transition_event_handle_t, node) { + if ((handle->info->event_mask & transition) > 0) { + handle->info->on_event(from, to); + } + } +} diff --git a/Libs/platform/service/power_manager/src/common/sl_power_manager_em4.c b/Libs/platform/service/power_manager/src/common/sl_power_manager_em4.c new file mode 100644 index 0000000..e553c99 --- /dev/null +++ b/Libs/platform/service/power_manager/src/common/sl_power_manager_em4.c @@ -0,0 +1,330 @@ +/***************************************************************************//** + * @file + * @brief Power Manager EM4 API implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_emu.h" +#include "em_cmu.h" +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#include "em_iadc.h" +#endif +#endif + +#include +#include + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#if defined(WDOG_PRESENT) +// Macros to determine if WDOG instances are clocked or not + +#if defined(CMU_CLKEN0_WDOG0) +#define WDOG0_CLOCK_ENABLED_BIT (CMU->CLKEN0 & CMU_CLKEN0_WDOG0) +#else +// There's no CMU->CLKEN1 so assume the WDOG0 is clocked +#define WDOG0_CLOCK_ENABLED_BIT 1 +#endif + +#if defined(CMU_CLKEN1_WDOG1) +#define WDOG1_CLOCK_ENABLED_BIT (CMU->CLKEN1 & CMU_CLKEN1_WDOG1) +#else +// There's no CMU->CLKEN1 so assume the WDOG1 is clocked +#define WDOG1_CLOCK_ENABLED_BIT 1 +#endif + +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static bool is_em4_blocked(void); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) +static void ramp_dvdd_and_switch_to_dcdc_bypass_mode(void); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * update energy mode 4 configurations. + ******************************************************************************/ +void sli_power_manager_init_em4(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2) + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | (uint32_t)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; +#else + EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; + em4_init.pinRetentionMode = (EMU_EM4PinRetention_TypeDef)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; + EMU_EM4Init(&em4_init); +#endif +} + +/****************************************************************************** + * Event called before entering EM4 sleep. + *****************************************************************************/ +SL_WEAK void sl_power_manager_em4_presleep_hook(void) +{ + // This implementation is empty, but this function can be redefined as it's a weak implementation. +} + +/***************************************************************************//** + * Enter energy mode 4 (EM4). + * + * @note You should not expect to return from this function. Once the device + * enters EM4, only a power on reset or external reset pin can wake the + * device. + * + * @note On xG22 devices, this function re-configures the IADC if EM4 entry + * is possible. + ******************************************************************************/ +__NO_RETURN void sl_power_manager_enter_em4(void) +{ + /* Device with Boost DC-DC cannot enter EM4 because Boost DC-DC module does not + * have BYPASS switch so DC-DC converter can not be set to bypass mode. */ +#if (defined(_SILICON_LABS_DCDC_FEATURE) \ + && (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST)) + EFM_ASSERT(false); +#endif + + // Make sure that we are not interrupted while we are entering em4 + CORE_CRITICAL_IRQ_DISABLE(); + + EFM_ASSERT(is_em4_blocked() == false); + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) + sli_metric_em4_wake_init(); +#endif + + uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + + // Make sure that the register write lock is disabled. + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; + +#if defined(_DCDC_IF_EM4ERR_MASK) + // Workaround for bug that may cause a Hard Fault on EM4 entry + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + // The buck DC-DC is available in all energy modes except for EM4. + // The DC-DC converter must first be turned off and switched over to bypass mode. +#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) + ramp_dvdd_and_switch_to_dcdc_bypass_mode(); + #else + EMU_DCDCModeSet(emuDcdcMode_Bypass); + #endif +#endif +#endif + + sl_power_manager_em4_presleep_hook(); + + for (uint8_t i = 0; i < 4; i++) { + EMU->EM4CTRL = em4seq2; + EMU->EM4CTRL = em4seq3; + } + EMU->EM4CTRL = em4seq2; + __WFI(); + + for (;; ) { + // __NO_RETURN + } +} + +/***************************************************************************//** + * When EM4 pin retention is set to power_manager_pin_retention_latch, + * then pins are retained through EM4 entry and wakeup. The pin state is + * released by calling this function. The feature allows peripherals or + * GPIO to be re-initialized after EM4 exit (reset), and when + * initialization is done, this function can release pins and return + * control to the peripherals or GPIO. + ******************************************************************************/ +void sl_power_manager_em4_unlatch_pin_retention(void) +{ +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) + EMU->CMD = EMU_CMD_EM4UNLATCH; +#endif +} + +/***************************************************************************//** + * Returns true if em4 entry is blocked by a watchdog peripheral. + ******************************************************************************/ +static bool is_em4_blocked(void) +{ +#if defined(WDOG_PRESENT) +#if WDOG_COUNT > 0 + if ( WDOG0_CLOCK_ENABLED_BIT && (WDOG0->CFG & WDOG_CFG_EM4BLOCK) && (WDOG0->EN & WDOG_EN_EN) ) { + return true; + } +#endif +#if WDOG_COUNT > 1 + if ( WDOG1_CLOCK_ENABLED_BIT && (WDOG1->CFG & WDOG_CFG_EM4BLOCK) && (WDOG1->EN & WDOG_EN_EN) ) { + return true; + } +#endif +#endif + return false; +} + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) + +/* The following section provides an optimization to improve peak current + * consumption on xG22 devices. + */ + +// ADC clock frequency (source and after prescale) +#define CLK_SRC_ADC_FREQ 9600000 // CLK_SRC_ADC +#define CLK_ADC_FREQ 1000000 // CLK_ADC + +extern void sli_delay_loop(uint32_t cycles); + +uint32_t * dcdc_test_addr = (uint32_t *)(DCDC_NS_BASE + 0x80); +uint32_t ipkval = 7; +uint32_t ipktimeout = 1; + +/* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ +uint32_t cmd[2] = { (1 << 2) | (1 << 3), (1 << 2) }; + +/***************************************************************************//** + * The voltage of Dvdd is ramped up to VMCU by sending pulses to a DCDC test + * register. These pulses are delayed, and ipkval and ipktimeout are tuned + * such that the voltage at Dvdd increases gradually to the voltage level of + * VMCU. Using the IADC, once Dvdd has gotten sufficiently close to VMCU, + * the DCDC peripheral is then switched into bypass mode. The IADC is used to + * detect this by sampling the voltage of Dvdd periodically, and calculating the + * difference between samples, when the difference is within some margin of zero + * then we know that the ramp sequence has reached a plateau. + ******************************************************************************/ +static void ramp_dvdd_and_switch_to_dcdc_bypass_mode(void) +{ + // Initialize the IADC for the purposes of detecting when the Dvdd ramp + // reaches a plateau. + IADC_Init_t init = IADC_INIT_DEFAULT; + IADC_AllConfigs_t initAllConfigs = IADC_ALLCONFIGS_DEFAULT; + IADC_InitSingle_t initSingle = IADC_INITSINGLE_DEFAULT; + IADC_SingleInput_t initSingleInput = IADC_SINGLEINPUT_DEFAULT; + CMU_ClockEnable(cmuClock_IADC0, true); + + init.srcClkPrescale = IADC_calcSrcClkPrescale(IADC0, CLK_SRC_ADC_FREQ, 0); + initAllConfigs.configs[0].reference = iadcCfgReferenceInt1V2; + initAllConfigs.configs[0].vRef = 1210; + initAllConfigs.configs[0].analogGain = iadcCfgAnalogGain1x; + initAllConfigs.configs[0].digAvg = iadcDigitalAverage1; + initAllConfigs.configs[0].adcClkPrescale = + IADC_calcAdcClkPrescale(IADC0, + CLK_ADC_FREQ, + 0, + iadcCfgModeNormal, + init.srcClkPrescale); + init.warmup = iadcWarmupKeepWarm; + + IADC_reset(IADC0); + CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_EM01GRPACLK); + initSingle.triggerAction = iadcTriggerActionContinuous; + initSingle.alignment = iadcAlignRight12; + initSingleInput.compare = false; // Disable Window CMP + initSingleInput.posInput = iadcPosInputDvdd; + IADC_init(IADC0, &init, &initAllConfigs); + IADC_initSingle(IADC0, &initSingle, &initSingleInput); + + // Start capturing + IADC_command(IADC0, iadcCmdStartSingle); + + // Initialize DCDC peak current value and timeout to reach peak current value + DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); + DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); + + /* Generate pulses */ + uint32_t iter = 1U; + IADC_Result_t prev_result; + volatile IADC_Result_t current_result = IADC_readSingleResult(IADC0); + while (true) { + // If the algorithm doesn't converge after 500 pulses, switch to dcdc + // bypass anyways. + if (iter >= 500) { + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + EFM_ASSERT(false); + return; + } + + /* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ + *dcdc_test_addr = cmd[0]; + *dcdc_test_addr = cmd[1]; + + // In DCDC mode, MCU input voltage VREGVDD cannot be directly measured, so + // we can't know what the target DVDD voltage is. Instead, since DVDD + // ramp-up should follow a RC charge curve, measure DVDD and keep charging + // until the delta between measures is smaller than the set tolerance. + if (iter % 20U == 0U) { + prev_result = current_result; + current_result = IADC_readSingleResult(IADC0); + if ( abs((int32_t)(current_result.data - prev_result.data)) < SL_POWER_MANAGER_RAMP_DVDD_TOLERANCE ) { + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + return; + } + } + + if (DCDC->IF & DCDC_IF_TMAX) { + if (ipkval) { + ipkval--; // DCDC peak current value + } + + if (ipktimeout < 7) { + ipktimeout++; // Timeout to reach peak current value + } + + DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); + DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); + + DCDC->IF_CLR = DCDC_IF_TMAX; + } + + /* delay for 8 clock cycles */ + sli_delay_loop(8); + iter++; + } +} + +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) diff --git a/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager.c b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager.c new file mode 100644 index 0000000..9e4621f --- /dev/null +++ b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager.c @@ -0,0 +1,1097 @@ +/***************************************************************************//** + * @file + * @brief Power Manager API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager_private.h" +#include "sli_power_manager.h" +#include "sli_sleeptimer.h" +#include "sli_clock_manager.h" +#include "sl_assert.h" +#include "sl_atomic.h" +#include "sl_clock_manager.h" + +#if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) +#include "sl_power_manager_execution_modes.h" +#endif + +#include "em_device.h" +#if !defined(_SILICON_LABS_32B_SERIES_3) +#include "em_emu.h" +#endif + +#include +#include +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Default overhead value for the wake-up time used for the schedule wake-up +// functionality. +#define SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK 0 + +// Determine if the device supports EM1P +#if !defined(SLI_DEVICE_SUPPORTS_EM1P) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#define SLI_DEVICE_SUPPORTS_EM1P +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Initialization flag. +static bool is_initialized = false; + +// Current active energy mode. +static sl_power_manager_em_t current_em = SL_POWER_MANAGER_EM0; + +// Table of energy modes counters. Each counter indicates the presence (not zero) +// or absence (zero) of requirements on a given energy mode. The table doesn't +// contain requirement on EM0. +static uint8_t requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE] = { + 0, // EM1 requirement counter + 0, // EM2 requirement counter +}; + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +// Store the sleeptimer module clock frequency for conversion calculation +static uint32_t sleeptimer_frequency; + +// Counter variable to save the number of High Accuracy HF clock requirements requested. +uint8_t requirement_high_accuracy_hf_clock_counter = 0; + +#ifdef SLI_DEVICE_SUPPORTS_EM1P +// Variable to indicate if the High Accuracy HF clock requirements count is back to zero. +bool requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + +// Saved energy mode we are coming from when waiting for HFXO ready. +static sl_power_manager_em_t waiting_clock_restore_from_em = SL_POWER_MANAGER_EM0; + +// Flag indicating if we are sleeping, waiting for the HF clock restore +static volatile bool is_sleeping_waiting_for_clock_restore = false; + +// Flag indicating if the system states (clocks) are saved and should be restored +static volatile bool is_states_saved = false; + +// Timer that it is used for enabling the clock for the scheduled wakeup +static sl_sleeptimer_timer_handle_t clock_wakeup_timer_handle = { 0 }; + +// Store if requirement on EM1 has been added before sleeping; +// i.e. only possible if sleeping for less than minimum off time +static bool requirement_on_em1_added = false; + +// Threshold delay in sleeptimer ticks indicating the minimum time required +// to make the shut down of external high frequency oscillator worthwhile before +// the next synchronous high frequency oscillator requirement. Shorter than this +// delay, the power gain of shutting down is invalidated. +uint32_t high_frequency_min_offtime_tick = 0; + +// Store the configuration overhead value in sleeptimer tick to add/remove to the wake-up time. +int32_t wakeup_time_config_overhead_tick = 0; + +static bool is_hf_x_oscillator_not_preserved; + +// Store if we are currently waiting for HF clock restoration to finish +static bool is_actively_waiting_for_clock_restore = false; + +// Indicates if the clock restore was completed from the HFXO ISR +static volatile bool is_restored_from_hfxo_isr = false; +static volatile bool is_restored_from_hfxo_isr_internal = false; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static sl_power_manager_em_t get_lowest_em(void); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void evaluate_wakeup(sl_power_manager_em_t to); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void update_em1_requirement(bool add); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, + void *data); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void clock_restore_and_wait(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void clock_restore(void); +#endif + +// Use PriMask to enter critical section by disabling interrupts. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static CORE_irqState_t enter_critical_with_primask(); + +// Exit critical section by re-enabling interrupts in PriMask. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static void exit_critical_with_primask(CORE_irqState_t primask_state); + +// Exit critical section and re-enter by using two funtion above. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static CORE_irqState_t yield_critical_with_primask(CORE_irqState_t primask_state); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initialize Power Manager module. + ******************************************************************************/ +sl_status_t sl_power_manager_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + // Initialize GPIO bus clock module if it hasn't been initialized + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + + if (!is_initialized) { + sl_status_t status = SL_STATUS_OK; + + // Initialize Sleeptimer module in case not already done. + status = sl_sleeptimer_init(); + if (status != SL_STATUS_OK) { + CORE_EXIT_CRITICAL(); + return status; + } +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Additional Sleeptimer HW configuration if the "power_manager_deepsleep" component is used + sli_sleeptimer_hal_power_manager_integration_init(); +#endif + + #if (SL_POWER_MANAGER_DEBUG == 1) + sli_power_manager_debug_init(); + #endif + sli_power_manager_em_transition_event_list_init(); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // If lowest energy mode is not restricted to EM1, determine and set lowest energy mode + sli_sleeptimer_set_pm_em_requirement(); + // Set the default wake-up overhead value + wakeup_time_config_overhead_tick = SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK; + + // Get the sleeptimer frequency + sleeptimer_frequency = sl_sleeptimer_get_timer_frequency(); +#endif + +#if defined(_EMU_CTRL_EM2DBGEN_MASK) && defined(SL_POWER_MANAGER_INIT_EMU_EM2_DEBUG_ENABLE) + // EM2 set debug enable + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) + | (SL_POWER_MANAGER_INIT_EMU_EM2_DEBUG_ENABLE << _EMU_CTRL_EM2DBGEN_SHIFT); +#endif + + // Initialize EM4 + sli_power_manager_init_em4(); + +#if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) + // Initialize execution mode feature + sli_power_manager_executions_modes_init(); +#endif + } + + // Do all necessary hardware initialization. + sli_power_manager_init_hardware(); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Set the HF minimum offtime in sleeptimer ticks + high_frequency_min_offtime_tick = sli_power_manager_get_default_high_frequency_minimum_offtime(); +#endif + + is_initialized = true; + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sleep at the lowest allowed energy mode. + ******************************************************************************/ +void sl_power_manager_sleep(void) +{ + CORE_irqState_t primask_state; + sl_power_manager_em_t lowest_em; + + primask_state = enter_critical_with_primask(); + + sli_power_manager_suspend_log_transmission(); + + if (sl_power_manager_is_ok_to_sleep() != true) { + sli_power_manager_resume_log_transmission(); + exit_critical_with_primask(primask_state); + return; + } + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Go to another energy mode (same, higher to lower or lower to higher) + do { + // Remove any previous EM1 requirement added internally by the power manager itself + if (requirement_on_em1_added) { + update_em1_requirement(false); + requirement_on_em1_added = false; + } + + lowest_em = get_lowest_em(); + evaluate_wakeup(lowest_em); + lowest_em = get_lowest_em(); // Reevaluate as a requirement can be added from evaluate_wakeup() + + if ((lowest_em >= SL_POWER_MANAGER_EM2) + && (is_states_saved == false)) { + sli_power_manager_save_states(); + } + + // Notify listeners if transition to another energy mode + if (lowest_em != current_em) { +#ifdef SLI_DEVICE_SUPPORTS_EM1P + requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + if (is_sleeping_waiting_for_clock_restore == false) { + // But only notify if we are not in the process of waiting for the HF oscillators restore. + sli_power_manager_notify_em_transition(current_em, lowest_em); + } + current_em = lowest_em; // Keep new active energy mode + } + +#ifdef SLI_DEVICE_SUPPORTS_EM1P + // Notification for possible transition from EM1P to EM2 + // For internal Silicon Labs use only + if (requirement_high_accuracy_hf_clock_back_to_zero + && current_em == SL_POWER_MANAGER_EM2) { + requirement_high_accuracy_hf_clock_back_to_zero = false; + sli_power_manager_em1p_to_em2_notification(); + } +#endif + + // Pre-sleep operations if any are necessary + if ((lowest_em >= SL_POWER_MANAGER_EM2) + && (is_states_saved == false)) { + // Only do pre-sleep operations if there is no requirement on High Accuracy Clock. + // Else we must not touch the clock tree. + if (requirement_high_accuracy_hf_clock_counter == 0) { + sli_power_manager_handle_pre_deepsleep_operations(); + is_hf_x_oscillator_not_preserved = true; + } + is_states_saved = true; + } + + // Apply lowest reachable energy mode + sli_power_manager_apply_em(current_em); + + // In case we are waiting for the restore from an early wake-up, + // we put back the current EM to the one before the early wake-up to do the next notification correctly. + if (is_sleeping_waiting_for_clock_restore == true) { + current_em = waiting_clock_restore_from_em; + } + + // Notify consumer of wakeup while interrupts are still off + // For internal Silicon Labs use only + sli_power_manager_on_wakeup(); + + primask_state = yield_critical_with_primask(primask_state); + + // In case the HF restore was completed from the HFXO ISR, + // and notification not done elsewhere, do it here + if (is_restored_from_hfxo_isr_internal == true) { + is_restored_from_hfxo_isr_internal = false; + if (current_em == waiting_clock_restore_from_em) { + current_em = SL_POWER_MANAGER_EM1; + sli_power_manager_notify_em_transition(waiting_clock_restore_from_em, SL_POWER_MANAGER_EM1); + } + } + + // Stop the internal power manager sleeptimer. + sl_sleeptimer_stop_timer(&clock_wakeup_timer_handle); + } while (sl_power_manager_sleep_on_isr_exit() == true); + +#ifdef SLI_DEVICE_SUPPORTS_EM1P + requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + + if (is_states_saved == true) { + is_sleeping_waiting_for_clock_restore = false; + // Restore clocks + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + // If possible, go back to sleep in EM1 while waiting for HF accuracy restore + while (!sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { + sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); + primask_state = yield_critical_with_primask(primask_state); + } + sli_power_manager_restore_states(); + is_states_saved = false; + } + + evaluate_wakeup(SL_POWER_MANAGER_EM0); +#else + bool first_iteration = true; + current_em = SL_POWER_MANAGER_EM1; + + // Notify listeners of transition to EM1 + sli_power_manager_notify_em_transition(SL_POWER_MANAGER_EM0, SL_POWER_MANAGER_EM1); + + do { + // Get lowest EM + lowest_em = get_lowest_em(); + + if (first_iteration == true + && lowest_em > SL_POWER_MANAGER_EM1) { + // Hook function for specific operations when we enter sleep with no EM1 requirement. + // Even though deepsleep is not entered, additional operations to reduce power can be perfomed. + sli_power_manager_em1hclkdiv_presleep_operations(); + first_iteration = false; + } + + // Apply EM1 energy mode + // Lowest EM is passed so that further actions can be taking by the HAL based on the EM requirements + // but only EM1 sleep will be entered. + sli_power_manager_apply_em(lowest_em); + + primask_state = yield_critical_with_primask(primask_state); + } while (sl_power_manager_sleep_on_isr_exit() == true); + + if (first_iteration == false) { + // Since the lowest_em can change inside ISR, we don't use it for the condition check. + sli_power_manager_em1hclkdiv_postsleep_operations(); + } +#endif + +#if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) + sli_power_manager_implement_execution_mode_on_wakeup(); +#endif + + // Indicate back to EM0 + sli_power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM0); + current_em = SL_POWER_MANAGER_EM0; + + sli_power_manager_resume_log_transmission(); + + exit_critical_with_primask(primask_state); +} + +/***************************************************************************//** + * Updates requirement on the given energy mode. + * + * @param em Energy mode. Possible values are: + * SL_POWER_MANAGER_EM1 + * SL_POWER_MANAGER_EM2 + * + * @param add Flag indicating if requirement is added (true) or removed + * (false). + * + * @note Need to be call inside a critical section. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, + bool add) +{ + // EM0 is not allowed + EFM_ASSERT((em > SL_POWER_MANAGER_EM0) && (em < SL_POWER_MANAGER_EM3)); + + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[em - 1] == UINT8_MAX) && (add == true))); + if ((requirement_em_table[em - 1] == UINT8_MAX) && (add == true)) { + return; + } + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[em - 1] == 0) && (add == false))); + if ((requirement_em_table[em - 1] == 0) && (add == false)) { + return; + } + // Increment (add) or decrement (remove) energy mode counter. + requirement_em_table[em - 1] += add ? 1 : -1; + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + if (add == true + && current_em >= SL_POWER_MANAGER_EM2) { // if currently sleeping at a level that can require a clock restore; i.e. called from ISR + sl_power_manager_em_t lowest_em; + // If requirement added when sleeping, restore the clock before continuing the processing. + // Retrieve lowest reachable energy mode + lowest_em = get_lowest_em(); + + if (lowest_em <= SL_POWER_MANAGER_EM1) { + // If new lowest requirement is greater than the current + // Restore clock; Everything is restored (HF and LF Clocks), the sleep loop will + // shutdown the clocks when returning sleeping + clock_restore_and_wait(); + } else if (current_em == SL_POWER_MANAGER_EM3 + && lowest_em == SL_POWER_MANAGER_EM2) { + // Restore LF clocks if we are transitioning from EM3 to EM2 + sli_power_manager_low_frequency_restore(); + } + + if (current_em != lowest_em) { + sli_power_manager_notify_em_transition(current_em, lowest_em); + current_em = lowest_em; // Keep new active energy mode + } + } +#else + (void)em; + (void)add; +#endif +} + +/***************************************************************************//** + * Updates requirement on preservation of High Frequency Clocks settings. + * + * @param add Flag indicating if requirement is added (true) or removed + * (false). + ******************************************************************************/ +void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add) +{ +#if (defined(SLI_DEVICE_SUPPORTS_EM1P) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true))); + if ((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true)) { + CORE_EXIT_CRITICAL(); + return; + } + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == 0) && (add == false))); + if ((requirement_high_accuracy_hf_clock_counter == 0) && (add == false)) { + CORE_EXIT_CRITICAL(); + return; + } + // Cannot add requirement if the "normal" clock settings are not currently applied + EFM_ASSERT(!((current_em > SL_POWER_MANAGER_EM2) && (add == true))); + + // Increment (add) or decrement (remove) energy mode counter. + requirement_high_accuracy_hf_clock_counter += add ? 1 : -1; + + // Save if the requirement is back to zero. + requirement_high_accuracy_hf_clock_back_to_zero = (requirement_high_accuracy_hf_clock_counter == 0) ? true : false; + + CORE_EXIT_CRITICAL(); +#else + (void)add; +#endif +} + +/***************************************************************************//** + * Adds requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with adding an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_add_hf_clock_settings_preservation_requirement(void) +{ +#if defined(SLI_DEVICE_SUPPORTS_EM1P) + sli_power_manager_update_hf_clock_settings_preservation_requirement(true); +#else + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +#endif +} + +/***************************************************************************//** + * Removes requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with removing an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void) +{ +#if defined(SLI_DEVICE_SUPPORTS_EM1P) + sli_power_manager_update_hf_clock_settings_preservation_requirement(false); +#else + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); +#endif +} + +/***************************************************************************//** + * Gets the wake-up restore process time. + * If we are not in the context of a deepsleep and therefore don't need to + * do a restore, the return value is 0. + * + * @return Wake-up restore process time. + ******************************************************************************/ +uint32_t sli_power_manager_get_restore_delay(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t wakeup_delay = 0; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + // If we are not currently in deepsleep, not need for any clock restore + if (current_em <= SL_POWER_MANAGER_EM1) { + CORE_EXIT_CRITICAL(); + return wakeup_delay; + } + + // Get the clock restore delay + wakeup_delay = sl_power_manager_schedule_wakeup_get_restore_overhead_tick(); + wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); + + CORE_EXIT_CRITICAL(); + + return wakeup_delay; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Initiates the wake-up restore process. + ******************************************************************************/ +void sli_power_manager_initiate_restore(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + // Start restore process + clock_restore(); + + CORE_EXIT_CRITICAL(); +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. + ******************************************************************************/ +bool sli_power_manager_get_clock_restore_status(void) +{ + return is_sleeping_waiting_for_clock_restore; +} +#endif + +/***************************************************************************//** + * Get configurable overhead value for early restore time in Sleeptimer ticks + * when a schedule wake-up is set. + * + * @return Current overhead value for early wake-up time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + int32_t overhead_tick; + + sl_atomic_load(overhead_tick, wakeup_time_config_overhead_tick); + return overhead_tick; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Set configurable overhead value for early restore time in Sleeptimer ticks + * used for schedule wake-up. + * Must be called after initialization else the value will be overwritten. + * + * @param overhead_tick Overhead value to set for early restore time. + * + * @note The overhead value can also be negative to remove time from the restore + * process. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + sl_atomic_store(wakeup_time_config_overhead_tick, overhead_tick); +#else + (void)overhead_tick; +#endif +} + +/***************************************************************************//** + * Get configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @return Current minimum off-time value for schedule wake-up. + * + * @note Turning on external high frequency oscillator, such as HFXO, requires + * more energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency oscillator enable' is + * scheduled in 'x' time, there is a threshold 'x' value where turning + * off the oscillator is not worthwhile since the energy consumed by + * taking into account the wake-up will be greater than if we just keep + * the oscillator on until the next scheduled oscillator enabled. This + * threshold value is what we refer as the minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t offtime_tick; + + sl_atomic_load(offtime_tick, high_frequency_min_offtime_tick); + return offtime_tick; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Set configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @param minimum_offtime_tick minimum off-time value to set for schedule + * wake-up. + * + * @note Turning on external high frequency oscillator, such as HFXO, requires + * more energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency oscillator enable' is + * scheduled in 'x' time, there is a threshold 'x' value where turning + * off the oscillator is not worthwhile since the energy consumed by + * taking into account the wake-up will be greater than if we just keep + * the oscillator on until the next scheduled oscillator enabled. This + * threshold value is what we refer as the minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + sl_atomic_store(high_frequency_min_offtime_tick, minimum_offtime_tick); +#else + (void)minimum_offtime_tick; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Converts microseconds time in sleeptimer ticks. + ******************************************************************************/ +uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us) +{ + return (((time_us * sleeptimer_frequency) + (1000000 - 1)) / 1000000); +} +#endif + +/**************************************************************************//** + * Determines if the HFXO interrupt was part of the last wake-up and/or if + * the HFXO early wakeup expired during the last ISR + * and if it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + * + * @note This function will always return false in case + * a requirement is added on SL_POWER_MANAGER_EM1, + * since we will never sleep at a lower level than EM1. + *****************************************************************************/ +bool sl_power_manager_is_latest_wakeup_internal(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + CORE_DECLARE_IRQ_STATE; + bool sleep; + + CORE_ENTER_CRITICAL(); + sleep = is_restored_from_hfxo_isr; + is_restored_from_hfxo_isr = false; + CORE_EXIT_CRITICAL(); + + sleep |= sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(); + return sleep; +#else + return false; +#endif +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Get lowest energy mode to apply given the requirements on the different + * energy modes. + * + * @return Lowest energy mode: EM1, EM2 or EM3. + * + * @note If no requirement for any energy mode (EM1 and EM2), lowest energy mode + * is EM3. + ******************************************************************************/ +static sl_power_manager_em_t get_lowest_em(void) +{ + uint32_t em_ix; + sl_power_manager_em_t em; + + // Retrieve lowest Energy mode allowed given the requirements + em_ix = 1; + while ((em_ix < 3) && (requirement_em_table[em_ix - 1] == 0)) { + em_ix++; + } + + em = (sl_power_manager_em_t)em_ix; + + return em; +} + +/***************************************************************************//** + * Enter critical section by disabling interrupts using PriMask. + * + * @return primask Initial primask state. + * + * @note @ref sl_power_manager_sleep() function should use PriMask to disable + * interrupts. + ******************************************************************************/ +static CORE_irqState_t enter_critical_with_primask(void) +{ + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + + return irqState; +} + +/***************************************************************************//** + * Exit critical section by re-enabling interrupts using PriMask. + * + * @param primask_state Initial primask state. + ******************************************************************************/ +static void exit_critical_with_primask(CORE_irqState_t primask_state) +{ + if (primask_state == 0U) { + __enable_irq(); + __ISB(); + } +} + +/***************************************************************************//** + * Exit critical section and re-enter by using PriMask. + * + * @param[in] primask_state Initial primask state. + * + * @return Initial primask state. + ******************************************************************************/ +static CORE_irqState_t yield_critical_with_primask(CORE_irqState_t primask_state) +{ + exit_critical_with_primask(primask_state); + return enter_critical_with_primask(); +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Evaluates scheduled wakeup and restart timer based on the wakeup time. + * If the remaining time is shorter than the wakeup time then add a requirement + * on EM1 for avoiding the wakeup delay time. + * + * @note Must be called in a critical section. + ******************************************************************************/ +static void evaluate_wakeup(sl_power_manager_em_t to) +{ + sl_status_t status; + uint32_t tick_remaining; + + switch (to) { + case SL_POWER_MANAGER_EM0: + // Coming back from Sleep. + if (requirement_on_em1_added) { + update_em1_requirement(false); + requirement_on_em1_added = false; + } + break; + + case SL_POWER_MANAGER_EM1: + // External high frequency clock, such as HFXO, already enabled; No wakeup delay + break; + + case SL_POWER_MANAGER_EM2: + case SL_POWER_MANAGER_EM3: + // Get the time remaining until the next sleeptimer requiring early wake-up + status = sl_sleeptimer_get_remaining_time_of_first_timer(0, &tick_remaining); + if (status == SL_STATUS_OK) { + if (tick_remaining <= high_frequency_min_offtime_tick) { + // Add EM1 requirement if time remaining is to short to be energy efficient + // if going back to deepsleep. + update_em1_requirement(true); + requirement_on_em1_added = true; + } else { + int32_t wakeup_delay = 0; + int32_t cfg_overhead_tick = 0; + + // Calculate overall wake-up delay. + sl_atomic_load(cfg_overhead_tick, wakeup_time_config_overhead_tick); + wakeup_delay += cfg_overhead_tick; + wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); + EFM_ASSERT(wakeup_delay >= 0); + if (tick_remaining <= (uint32_t)wakeup_delay) { + // Add EM1 requirement if time remaining is smaller than wake-up delay. + update_em1_requirement(true); + requirement_on_em1_added = true; + } else { + uint16_t hf_accuracy_clk_flag = 0; + if (sli_power_manager_is_high_freq_accuracy_clk_used()) { + hf_accuracy_clk_flag = SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG; + } + // Start internal sleeptimer to do the early wake-up. + sl_sleeptimer_restart_timer(&clock_wakeup_timer_handle, + (tick_remaining - (uint32_t)wakeup_delay), + on_clock_wakeup_timeout, + NULL, + 0, + (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | hf_accuracy_clk_flag)); + } + } + } + break; + + default: + EFM_ASSERT(false); + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Updates internal EM1 requirement. + * We add an internal EM1 requirement when we would usually go into EM2/EM3 + * but there is not enough time before the next schedule event requiring a + * clock restore. So we just go to sleep in EM1. + * We remove this internal EM1 requirement next time we wake-up. + * + * @param add true, to add EM1 requirement, + * false, to remove EM1 requirement. + * + * @note For internal use only. + * + * @note Need to be call inside a critical section. + ******************************************************************************/ +static void update_em1_requirement(bool add) +{ + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true))); + if ((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true)) { + return; + } + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false))); + if ((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false)) { + return; + } +#if (SL_POWER_MANAGER_DEBUG == 1) + sli_power_manager_debug_log_em_requirement(SL_POWER_MANAGER_EM1, add, "PM_INTERNAL_EM1_REQUIREMENT"); +#endif + + // Increment (add) or decrement (remove) energy mode counter. + requirement_em_table[SL_POWER_MANAGER_EM1 - 1] += add ? 1 : -1; + + // In rare occasions a clock restore must be started here: + // - An asynchronous event wake-up the system from deepsleep very near the early wake-up event, + // When we re-enter the sleep loop, we delete the internal early wake-up timer, but during + // the evaluation before sleep, it is calculated that not enough time is remains to go to + // deepsleep. In that case, since we deleted the early wake-up timer we must start the + // restore process here. + // - A synchronous event is added during an ISR, when we evaluate if the timeout is bigger + // than the clock restore time, it's barely bigger, so no clock restore process is started + // at that time. But when we do the evaluate before sleep, the remaining time is now smaller + // than the clock restore delay. So me must start the restore process here. + if (add == true + && current_em >= SL_POWER_MANAGER_EM2 + && is_sleeping_waiting_for_clock_restore == false) { + clock_restore(); + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Do clock restore process and wait for it to be completed. + ******************************************************************************/ +static void clock_restore_and_wait(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + if (is_states_saved == true) { + if (is_actively_waiting_for_clock_restore == false) { + is_actively_waiting_for_clock_restore = true; + + // Since we will actively wait for clock restore, we cancel any current non-active wait. + is_sleeping_waiting_for_clock_restore = false; + } + + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + + CORE_EXIT_CRITICAL(); + // We remove the critical section in case HFXO fails to startup and the HFXO Interrupt needs to run to handle the error. + sli_power_manager_is_high_freq_accuracy_clk_ready(true); + CORE_ENTER_CRITICAL(); + if (is_actively_waiting_for_clock_restore) { + sli_power_manager_restore_states(); + is_actively_waiting_for_clock_restore = false; + } + + is_states_saved = false; + } + CORE_EXIT_CRITICAL(); +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Start clock restore process. + * + * @note Need to be call inside a critical section. + ******************************************************************************/ +static void clock_restore(void) +{ + // Check if we need to start the clock restore process + if (is_states_saved == true) { + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + if (sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { + // Do the clock restore if the HF oscillator is already ready + sli_power_manager_restore_states(); + is_states_saved = false; + + // We do the notification only when the restore is completed. + sli_power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM1); + current_em = SL_POWER_MANAGER_EM1; // Keep new active energy mode + } else { + // If the HF oscillator is not yet ready, we will go back to sleep while waiting + is_sleeping_waiting_for_clock_restore = true; + + // Save current EM to do the right notification later + waiting_clock_restore_from_em = current_em; + } + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Callback for clock enable timer. + * + * @param handle Pointer to sleeptimer handle + * + * @param data Pointer to callback data + * + * @note We restore the HF clocks and go to EM1 here to be ready in time for the + * Application sleeptimer callback. But no EM1 requirement is added + * here. Since the time until the Application sleeptimer times out is <= + * than the wake-up delay, it protects us from going back to sleep lower + * than EM1. After that, it's up to the Application sleeptimer callback to + * put a EM1 requirement if still needed. + ******************************************************************************/ +static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + (void)handle; + (void)data; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + if (is_actively_waiting_for_clock_restore) { + // In case we are already actively waiting for HFXO ready in another ISR, just exit + CORE_EXIT_CRITICAL(); + return; + } + + // If needed start the clock restore process + clock_restore(); + + CORE_EXIT_CRITICAL(); +} +#endif + +/***************************************************************************//** + * HFXO ready notification callback for internal use with power manager + * + * @note Will only be used on series 2 devices when HFXO Manager is present. + ******************************************************************************/ +void sli_hfxo_manager_notify_ready_for_power_manager(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Complete HF restore and change current Energy mode + // The notification will be done once back in the sleep loop + if (current_em != SL_POWER_MANAGER_EM0 + && (is_sleeping_waiting_for_clock_restore == true)) { + sli_power_manager_restore_states(); + is_sleeping_waiting_for_clock_restore = false; + is_states_saved = false; + is_restored_from_hfxo_isr = true; + is_restored_from_hfxo_isr_internal = true; + } +#endif +} + +/***************************************************************************//** + * HFXO PRS ready notification callback for internal use with power manager + * + * @note Will only be used on series 2 devices when HFXO Manager and SYSRTC + * is present. + ******************************************************************************/ +void sli_hfxo_notify_ready_for_power_manager_from_prs(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Set clock restore to true to indicate that HFXO has been restored from a + // PRS interrupt unless already in EM0 indicating HFXO didn't need to be restored. + if (current_em != SL_POWER_MANAGER_EM0) { + is_sleeping_waiting_for_clock_restore = true; + } +#endif +} + +/***************************************************************************//** + * Returns current energy mode. + ******************************************************************************/ +sl_power_manager_em_t sli_power_manager_get_current_em(void) +{ + return current_em; +} diff --git a/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c new file mode 100644 index 0000000..e0f87ff --- /dev/null +++ b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c @@ -0,0 +1,165 @@ +/***************************************************************************//** + * @file + * @brief Power Manager Debug API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sl_power_manager_debug.h" +#include "sli_power_manager_private.h" + +#if (SL_POWER_MANAGER_DEBUG == 1) +#include +#include +#include +#include + +static sl_slist_node_t *power_manager_debug_requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE]; +static sli_power_debug_requirement_entry_t power_debug_entry_table[SL_POWER_MANAGER_DEBUG_POOL_SIZE]; +static sl_slist_node_t *power_debug_free_entry_list = NULL; +static bool power_debug_ran_out_of_entry = false; + +static void power_manager_log_add_requirement(sl_slist_node_t **p_list, + bool add, + const char *name); + +/***************************************************************************//** + * Print a fancy table that describes the current requirements on each energy + * mode and their owner. + ******************************************************************************/ +void sl_power_manager_debug_print_em_requirements(void) +{ + uint8_t i; + sli_power_debug_requirement_entry_t *entry; + + if (power_debug_ran_out_of_entry) { + printf("WARNING: The system ran out of Debug Entry; This report is likely to be incomplete. Increase SL_POWER_MANAGER_DEBUG_POOL_SIZE\n\n"); + } + printf("------------------------------------------\n"); + printf("| EM requirements\n"); + printf("------------------------------------------\n"); + for (i = 0; i < SLI_POWER_MANAGER_EM_TABLE_SIZE; i++) { + if (power_manager_debug_requirement_em_table[i] != NULL) { + printf("| EM%d requirement module owners:\n", i + 1); + } + SL_SLIST_FOR_EACH_ENTRY(power_manager_debug_requirement_em_table[i], entry, sli_power_debug_requirement_entry_t, node) { + printf("| %s\n", entry->module_name); + } + if (power_manager_debug_requirement_em_table[i] != NULL) { + printf("------------------------------------------\n"); + } + } +} + +/***************************************************************************//** + * Initialize debugging feature. + ******************************************************************************/ +void sli_power_manager_debug_init(void) +{ + uint32_t i; + + for (i = 0; i < SL_POWER_MANAGER_DEBUG_POOL_SIZE; i++) { + sli_power_debug_requirement_entry_t *entry = &power_debug_entry_table[i]; + sl_slist_push(&power_debug_free_entry_list, &entry->node); + } +} + +/***************************************************************************//** + * Log requirement to a list + * + * @param p_list List where to push or remove the requirement. + * + * @param add Add (true) or remove (false) the requirement. + * + * @param name Module name that acquired or remove the requirement. + ******************************************************************************/ +static void power_manager_log_add_requirement(sl_slist_node_t **p_list, + bool add, + const char *name) +{ + sl_slist_node_t *node; + sli_power_debug_requirement_entry_t *entry; + + if (add == true) { + // Get entry from free list + node = sl_slist_pop(&power_debug_free_entry_list); + if (node == NULL) { + power_debug_ran_out_of_entry = true; + return; + } + + // Push entry to the EMx requirement debug list + entry = SL_SLIST_ENTRY(node, sli_power_debug_requirement_entry_t, node); + entry->module_name = name; + sl_slist_push(p_list, &entry->node); + } else { + sli_power_debug_requirement_entry_t *entry_remove = NULL; + + // Search in the EMx requirement debug list + SL_SLIST_FOR_EACH_ENTRY(*p_list, entry, sli_power_debug_requirement_entry_t, node) { + // Current module name and entry module name + if (strcmp(entry->module_name, name) == 0) { + entry_remove = entry; + break; + } + } + + if (entry_remove == NULL) { + return; + } + + sl_slist_remove(p_list, &entry_remove->node); + sl_slist_push(&power_debug_free_entry_list, &entry_remove->node); + } +} +#endif // SL_POWER_MANAGER_DEBUG + +#undef sli_power_manager_debug_log_em_requirement +/***************************************************************************//** + * Log energy mode (EM) requirement + * + * @param em Energy mode added or removed. + * + * @param add Add (true) or remove (false) the requirement. + * + * @param name Module name that adds or removes the requirement. + ******************************************************************************/ +void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, + bool add, + const char *name) +{ +#if (SL_POWER_MANAGER_DEBUG == 1) + if (em != SL_POWER_MANAGER_EM0) { + power_manager_log_add_requirement(&power_manager_debug_requirement_em_table[em - 1], add, name); + } +#else + (void)em; + (void)add; + (void)name; +#endif +} diff --git a/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c new file mode 100644 index 0000000..9909d78 --- /dev/null +++ b/Libs/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c @@ -0,0 +1,706 @@ +/***************************************************************************//** + * @file + * @brief Power Manager HAL API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) + +#include "em_emu.h" +#include "em_cmu.h" +#include "sl_assert.h" +#include "sl_power_manager.h" +#include "sli_power_manager.h" +#include "sli_power_manager_private.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer.h" +#include "sl_power_manager_config.h" + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#include "em_iadc.h" +#include +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +#include "sli_hfxo_manager.h" +#endif + +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Time required by the hardware to come out of EM2 in microseconds. +// This value includes HW startup, emlib and sleepdrv execution time. +// Voltage scaling, HFXO startup and HFXO steady times are excluded from +// this because they are handled separately. RTCCSYNC time is also +// excluded and it is handled by RTCCSYNC code itself. +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) +#else // (_SILICON_LABS_32B_SERIES_2_CONFIG == 2), +#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) +#endif + +// DPLL Locking delay related defines +#define DPLL_COARSECOUNT_VALUE (5u) + +// Time it takes to upscale voltage after EM2 in microseconds. +// This value represents the time for scaling from VSCALE0 to VSCALE2. +#define EM2_WAKEUP_VSCALE_OVERHEAD_US (64u) + +// Default time value in microseconds required to wake-up the hfxo oscillator. +#define HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US (400u) + +// high frequency oscillator wake-up time margin for possible variation +// A shift by 3 will be like a division by 8, so a percentage of 12.5%. +#define HFXO_START_UP_TIME_OVERHEAD_LOG2 3 + +// Default time value in microseconds for the HFXO minimum off time. +#define HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US (400u) + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +// Table size of HFXO wake-up time measurement +#define HFXO_WAKE_UP_TIME_TABLE_SIZE 10 +#endif + +// Defines for hidden HFXO0 DBGSTATUS register and STARTUPDONE flag +#define HFXO0_DBGSTATUS (*(volatile uint32_t *)(HFXO0_BASE + 0x05C)) +#define HFXO_DBGSTATUS_STARTUPDONE (0x1UL << 1) /**< Startup Done Status */ +#define _HFXO_DBGSTATUS_STARTUPDONE_SHIFT 1 /**< Shift value for HFXO_STARTUPDONE */ +#define _HFXO_DBGSTATUS_STARTUPDONE_MASK 0x2UL /**< Bit mask for HFXO_STARTUPDONE */ + +/******************************************************************************* + ******************************* MACROS ************************************* + ******************************************************************************/ + +/******************************************************************************* +* DPLL lock time can be approximately calculated by the equation: +* COARSECOUNT * (M + 1) * Tref +* Where +* - COARSECOUNT is calibration value in a hidden register. Its default value +* is 5 and should not change with calibration. +* - M is one the DPLL configuration parameter. +* - Tref is the reference clock period. +*******************************************************************************/ +#define DPLL_LOCKING_DELAY_US_FUNCTION(M, freq_ref) \ + (uint32_t)(((uint64_t)(DPLL_COARSECOUNT_VALUE * ((M) +1)) * 1000000 + ((freq_ref) - 1)) / (freq_ref)) + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +// Variables to save the relevant clock registers. +uint32_t cmu_em01_grpA_clock_register; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +uint32_t cmu_em01_grpB_clock_register; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) +uint32_t cmu_em01_grpC_clock_register; +#endif +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) +uint32_t cmu_dpll_ref_clock_register; +#endif + +uint32_t cmu_sys_clock_register; + +// Time in ticks required for the general wake-up process. +static uint32_t process_wakeup_overhead_tick = 0; + +#if defined(EMU_VSCALE_PRESENT) +static bool is_fast_wakeup_enabled = true; +#endif + +static bool is_hf_x_oscillator_used = false; +static bool is_dpll_used = false; +static bool is_entering_deepsleep = false; + +static bool is_hf_x_oscillator_already_started = false; + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +static uint32_t hf_x_oscillator_wakeup_time_tc_inital = 0; + +static uint32_t hfxo_wakeup_time_table[HFXO_WAKE_UP_TIME_TABLE_SIZE]; +static uint8_t hfxo_wakeup_time_table_index = 0; +static uint32_t hfxo_wakeup_time_sum_average = 0; + +// Time in ticks required for HFXO start-up after wake-up from sleep. +static uint32_t hfxo_wakeup_time_tick = 0; +#endif +#endif + +/***************************************************************************//** + * Do some hardware initialization if necessary. + ******************************************************************************/ +void sli_power_manager_init_hardware(void) +{ + // Initializes EMU (voltage scaling in EM2/3) +#if defined(EMU_VSCALE_EM01_PRESENT) + EMU_EM01Init_TypeDef em01_init = EMU_EM01INIT_DEFAULT; + + EMU_EM01Init(&em01_init); +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +#if defined(EMU_VSCALE_PRESENT) +#if defined(SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP) +#if (SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP == 0) + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); +#else + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(true); +#endif +#else + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); +#endif +#endif + + // Get the current HF oscillator for the SYSCLK + cmu_sys_clock_register = CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK; +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + cmu_dpll_ref_clock_register = CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK; +#endif + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; +#endif + + is_dpll_used = ((DPLL0->STATUS & _DPLL_STATUS_ENS_MASK) != 0); + + is_hf_x_oscillator_used = ((cmu_sys_clock_register == CMU_SYSCLKCTRL_CLKSEL_HFXO) + || ((CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) == CMU_EM01GRPACLKCTRL_CLKSEL_HFXO)); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->RADIOCLKCTRL & _CMU_RADIOCLKCTRL_EN_MASK) != 0); +#endif + +#if defined(CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO) + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO); +#endif + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO) + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO); +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Set HFXO wakeup time to conservative default value + hfxo_wakeup_time_tick = sli_power_manager_convert_delay_us_to_tick(HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US); + for (uint8_t i = 0; i < HFXO_WAKE_UP_TIME_TABLE_SIZE; i++) { + hfxo_wakeup_time_table[i] = hfxo_wakeup_time_tick; + hfxo_wakeup_time_sum_average += hfxo_wakeup_time_tick; + } +#endif + + if (is_dpll_used && !is_hf_x_oscillator_used) { + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) == _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO); + } + + // Calculate DPLL locking delay from its configuration + if (is_dpll_used) { + uint32_t freq = 0; + + switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { + case _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + freq = SystemHFXOClockGet(); + break; + + case _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + freq = SystemLFXOClockGet(); + break; + + case _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + freq = SystemCLKIN0Get(); + break; + + default: + EFM_ASSERT(false); + break; + } + if (freq > 0) { // Avoid division by 0 + // Add DPLL Locking delay + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(DPLL_LOCKING_DELAY_US_FUNCTION((DPLL0->CFG1 & _DPLL_CFG1_M_MASK) >> _DPLL_CFG1_M_SHIFT, freq)); + } + } + + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US); + +#endif +} + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3. + ******************************************************************************/ +void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) +{ +#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + + if (enable == is_fast_wakeup_enabled) { + return; + } + + EMU_EM23Init_TypeDef em23_init = EMU_EM23INIT_DEFAULT; + + // Enable/disable EMU voltage scaling in EM2/3 + if (enable) { + em23_init.vScaleEM23Voltage = emuVScaleEM23_FastWakeup; + } else { + em23_init.vScaleEM23Voltage = emuVScaleEM23_LowPower; + } + + EMU_EM23Init(&em23_init); + + // Calculate and add voltage scaling wake-up delays in ticks + if (enable) { + // Remove voltage scaling delay if it was added before + process_wakeup_overhead_tick -= sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); + } else { + // Add voltage scaling delay if it was not added before + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); + } + + is_fast_wakeup_enabled = enable; +#else + (void)enable; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Save the CMU HF clock select state, oscillator enable, and voltage scaling. + ******************************************************************************/ +void sli_power_manager_save_states(void) +{ + // Save HF clock sources + cmu_em01_grpA_clock_register = CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + cmu_em01_grpB_clock_register = CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + cmu_em01_grpC_clock_register = CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK; +#endif + + EMU_Save(); +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle pre-sleep operations if any are necessary, like manually disabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void EMU_EM23PresleepHook(void) +{ + // Change the HF Clocks to be on FSRCO before sleep + if (is_entering_deepsleep) { + is_entering_deepsleep = false; + + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | _CMU_SYSCLKCTRL_CLKSEL_FSRCO; + // Switch the HF Clocks oscillator's to FSRCO before deepsleep + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; +#endif + // Disable DPLL before deepsleep +#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + if (is_dpll_used) { + DPLL0->EN_CLR = DPLL_EN_EN; + while ((DPLL0->EN & _DPLL_EN_DISABLING_MASK) != 0) { + // Wait for DPLL to be disabled. + } + } +#endif +#endif + + SystemCoreClockUpdate(); + } + // Clear HFXO IEN RDY before entering sleep to prevent HFXO HW requests from waking up the system + HFXO0->IEN_CLR = HFXO_IEN_RDY; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle post-sleep operations. The idea is to start HFXO ASAP when we know we + * will need it. + * + * @note In case HFXO is already started when we wake-up (ENS flag is up), + * the hidden flag STARTUPDONE is check to see if the HFXO was just + * enabled or not. If HFXO is enabled automatically following the wake-up, + * the STARTUPDONE flag will not yet be up, and it's an indication that + * we can still process to the HFXO restore time measurement. + ******************************************************************************/ +void EMU_EM23PostsleepHook(void) +{ + // Re enable HFXO IEN RDY since it was disabled in EMU_EM23PresleepHook + HFXO0->IEN_SET = HFXO_IEN_RDY; + + // Poke sleeptimer to determine if power manager's timer expired before the + // ISR handler executes. + // Also, check if HFXO is used. + if (is_hf_x_oscillator_used + && sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_COMP) + && sli_sleeptimer_is_power_manager_timer_next_to_expire()) { + // Check if HFXO is already running and has finished its startup. + // If yes, don't do the HFXO restore time measurement. + if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 + && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) + || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { +#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Force-enable HFXO in case the HFXO on-demand request would be removed + // before we finish the restore process. + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + return; + } + + // Start measure HFXO restore time. + is_hf_x_oscillator_already_started = true; + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); + + // Switch SYSCLK to HFXO to measure restore time + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; + SystemCoreClockUpdate(); +#else + sli_hfxo_manager_begin_startup_measurement(); + + // Force enable HFXO to measure restore time + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle pre-deepsleep operations if any are necessary, like manually disabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +void sli_power_manager_handle_pre_deepsleep_operations(void) +{ + is_entering_deepsleep = true; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle post-sleep operations if any are necessary, like manually enabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +void sli_power_manager_restore_high_freq_accuracy_clk(void) +{ + if (!is_hf_x_oscillator_used) { + return; + } + + // For the cases where it's not started from an early wake up + // And if HFXO is not already running. + if (!is_hf_x_oscillator_already_started) { + // Check if HFXO is already running and has finished its startup. + // If yes, don't do the HFXO restore time measurement. + if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 + && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) + || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { +#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Force-enable HFXO in case the HFXO on-demand request would be removed + // before we finish the restore process. + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + return; + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); + + // Switch SYSCLK to HFXO to measure restore time + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; + SystemCoreClockUpdate(); +#else + // Start measure HFXO restore time + sli_hfxo_manager_begin_startup_measurement(); + + // Force enable HFXO to measure restore time + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + uint32_t current_time = sl_sleeptimer_get_tick_count() - hf_x_oscillator_wakeup_time_tc_inital; + // Calculate average for HFXO restore time + hfxo_wakeup_time_sum_average -= (int32_t)hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] - (int32_t)current_time; + hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] = current_time; + hfxo_wakeup_time_tick = ((hfxo_wakeup_time_sum_average + (HFXO_WAKE_UP_TIME_TABLE_SIZE - 1) ) / HFXO_WAKE_UP_TIME_TABLE_SIZE); + + // Update index of wakeup time table + hfxo_wakeup_time_table_index++; + hfxo_wakeup_time_table_index %= HFXO_WAKE_UP_TIME_TABLE_SIZE; +#endif + + is_hf_x_oscillator_already_started = false; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Checks if HF accuracy clocks is fully restored and, if needed, waits for it. + * + * @param wait True, to wait for HF accuracy clocks to be ready + * False, otherwise. + * + * @return True, if HFXO ready. + * False, otherwise. + ******************************************************************************/ +bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait) +{ + if (!is_hf_x_oscillator_used) { + return true; + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + (void)wait; + return true; +#else + return sli_hfxo_manager_is_hfxo_ready(wait); +#endif +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Restore CMU HF clock select state, oscillator enable, and voltage scaling. + ******************************************************************************/ +void sli_power_manager_restore_states(void) +{ + // Restore specific EMU saved contexts + EMU_Restore(); + + // Restore DPLL after deepsleep +#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + if (is_dpll_used) { + DPLL0->EN_SET = DPLL_EN_EN; + while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { + // Wait for DPLL to be ready. + } + } +#endif +#endif + + // Restore SYSCLK to what it was before the deepsleep + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmu_sys_clock_register; + + // Restore the HF Clocks to what they were before deepsleep + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | cmu_em01_grpA_clock_register; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | cmu_em01_grpB_clock_register; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | cmu_em01_grpC_clock_register; +#endif + + // Remove FORCEEN on HFXO + if (is_hf_x_oscillator_used) { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + } + + SystemCoreClockUpdate(); +} +#endif + +/***************************************************************************//** + * Applies energy mode. + * + * @param em Energy mode to apply: + * SL_POWER_MANAGER_EM0 + * SL_POWER_MANAGER_EM1 + * SL_POWER_MANAGER_EM2 + * + * @note EMU_EnterEM2() and EMU_EnterEM3() has the parameter 'restore' set to + * true in the Power Manager. When set to true, the parameter 'restore' + * allows the EMU driver to save and restore oscillators, clocks and + * voltage scaling. When the processor returns from EM2 or EM3, its + * execution resumes in a clean and stable state. + ******************************************************************************/ +void sli_power_manager_apply_em(sl_power_manager_em_t em) +{ +#if defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Perform required actions according to energy mode + switch (em) { + case SL_POWER_MANAGER_EM1: + case SL_POWER_MANAGER_EM2: + case SL_POWER_MANAGER_EM3: +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + // when measuring interrupt disabled time, we don't + // want to count the time spent in sleep + sl_cycle_counter_pause(); +#endif + EMU_EnterEM1(); +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + sl_cycle_counter_resume(); +#endif + break; + + default: + EFM_ASSERT(false); + break; + } +#else + // Perform required actions according to energy mode + switch (em) { + case SL_POWER_MANAGER_EM1: +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + // when measuring interrupt disabled time, we don't + // want to count the time spent in sleep + sl_cycle_counter_pause(); +#endif + EMU_EnterEM1(); +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + sl_cycle_counter_resume(); +#endif + break; + + case SL_POWER_MANAGER_EM2: + EMU_EnterEM2(false); + break; + + case SL_POWER_MANAGER_EM3: + EMU_EnterEM3(false); + break; + + default: + EFM_ASSERT(false); + break; + } +#endif // SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Returns the default minimum offtime for HFXO. + ******************************************************************************/ +uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void) +{ + return sli_power_manager_convert_delay_us_to_tick(HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US); +} +#endif + +/******************************************************************************* + * Gets the delay associated the wake-up process from EM23. + * + * @return Delay for the complete wake-up process with full restore. + ******************************************************************************/ +uint32_t sli_power_manager_get_wakeup_process_time_overhead(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t delay = 0; + + // Add HFXO start-up delay if applicable + if (is_hf_x_oscillator_used) { +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + delay = hfxo_wakeup_time_tick; +#else + delay = sli_hfxo_manager_get_startup_time(); +#endif + delay += delay >> HFXO_START_UP_TIME_OVERHEAD_LOG2; + } + + // Add all additional overhead wake-up delays (DPLL, VSCALE, general wake-up process) + delay += process_wakeup_overhead_tick; + + return delay; +#else + return 0; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Informs the power manager module that the high accuracy/high frequency clock + * is used. + ******************************************************************************/ +void sli_power_manager_set_high_accuracy_hf_clock_as_used(void) +{ + is_hf_x_oscillator_used = true; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Restores the Low Frequency clocks according to what LF oscillators are used. + * + * @note On series 2, the on-demand will enable automatically the oscillators + * used when coming from sleep. + ******************************************************************************/ +void sli_power_manager_low_frequency_restore(void) +{ + // Nothing to do as on-demand feature will enable the LF oscillators automatically. +} + +/***************************************************************************//** + * Informs the power manager if the high accuracy/high frequency clock + * is used, prior to scheduling an early clock restore. + * + * @return true if HFXO is used, else false. + ******************************************************************************/ +bool sli_power_manager_is_high_freq_accuracy_clk_used(void) +{ + return is_hf_x_oscillator_used; +} +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * HAL hook function for pre EM1HCLKDIV sleep. + ******************************************************************************/ +void sli_power_manager_em1hclkdiv_presleep_operations(void) +{ + // No operations to do before EM1HCLKDIV sleep on series 2 devices +} + +/******************************************************************************* + * HAL hook function for post EM1HCLKDIV sleep. + ******************************************************************************/ +void sli_power_manager_em1hclkdiv_postsleep_operations(void) +{ + // No operations to do before EM1HCLKDIV sleep on series 2 devices +} +#endif +#endif diff --git a/Libs/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h b/Libs/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h new file mode 100644 index 0000000..249313f --- /dev/null +++ b/Libs/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h @@ -0,0 +1,164 @@ +/***************************************************************************//** + * @file + * @brief Power Manager Internal API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_slist.h" +#include "sl_code_classification.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) +#include "emlib_core_debug_config.h" +#endif + +#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +#endif + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +#include "sl_cycle_counter.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#define SLI_POWER_MANAGER_EM_TABLE_SIZE 2 + +#define SLI_POWER_MANAGER_EM4_ENTRY_WAIT_LOOPS 200 +/******************************************************************************* + ***************************** DATA TYPES ********************************* + ******************************************************************************/ + +// Debug entry +typedef struct { + sl_slist_node_t node; + const char *module_name; +} sli_power_debug_requirement_entry_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void sli_power_manager_init_hardware(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_apply_em(sl_power_manager_em_t em); + +void sli_power_manager_debug_init(void); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_save_states(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_handle_pre_deepsleep_operations(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_restore_high_freq_accuracy_clk(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_restore_states(void); + +/******************************************************************************* + * Converts microseconds time in sleeptimer ticks. + ******************************************************************************/ +uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us); + +/******************************************************************************* + * Returns the default minimum offtime for xtal high frequency oscillator. + ******************************************************************************/ +uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void); + +/******************************************************************************* + * Restores the Low Frequency clocks according to which LF oscillators are used. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_low_frequency_restore(void); + +/***************************************************************************//** + * Informs the power manager if the high accuracy/high frequency clock + * is used, prior to scheduling an early clock restore. + * + * @return true if HFXO is used, else false. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sli_power_manager_is_high_freq_accuracy_clk_used(void); +#endif + +/******************************************************************************* + * Gets the delay associated the wake-up process from EM23. + * + * @return Delay for the complete wake-up process with full restore. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sli_power_manager_get_wakeup_process_time_overhead(void); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. + * + * @return true if Power Manager is sleeping waiting for clock restore, else false. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +bool sli_power_manager_get_clock_restore_status(void); +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * HAL hook function for pre EM1HCLKDIV sleep. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_em1hclkdiv_presleep_operations(void); + +/******************************************************************************* + * HAL hook function for post EM1HCLKDIV sleep. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_em1hclkdiv_postsleep_operations(void); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/Libs/platform/service/sleeptimer/inc/sl_sleeptimer.h b/Libs/platform/service/sleeptimer/inc/sl_sleeptimer.h new file mode 100644 index 0000000..5ec91e7 --- /dev/null +++ b/Libs/platform/service/sleeptimer/inc/sl_sleeptimer.h @@ -0,0 +1,1184 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sleeptimer Sleep Timer + * @{ + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_H +#define SL_SLEEPTIMER_H + +#include +#include +#include +#include "sl_status.h" +#include "sl_common.h" +#include "sl_code_classification.h" + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG (0x01) +#define SL_SLEEPTIMER_ANY_FLAG (0xFF) + +#define SLEEPTIMER_ENUM(name) typedef uint8_t name; enum name##_enum + +/// @endcond + +/// Timestamp, wall clock time in seconds. +typedef uint32_t sl_sleeptimer_timestamp_t; + +// Timestamp, 64 bits wall clock in seconds. +typedef uint64_t sl_sleeptimer_timestamp_64_t; ///< sl sleeptimer timestamp 64 t + +/// Time zone offset from UTC(second). +typedef int32_t sl_sleeptimer_time_zone_offset_t; + +// Forward declaration +typedef struct sl_sleeptimer_timer_handle sl_sleeptimer_timer_handle_t; + +/***************************************************************************//** + * Typedef for the user supplied callback function which is called when + * a timer expires. + * + * @param handle The timer handle. + * + * @param data An extra parameter for the user application. + ******************************************************************************/ +typedef void (*sl_sleeptimer_timer_callback_t)(sl_sleeptimer_timer_handle_t *handle, void *data); + +/// @brief Timer structure for sleeptimer +struct sl_sleeptimer_timer_handle { + void *callback_data; ///< User data to pass to callback function. + uint8_t priority; ///< Priority of timer. + uint16_t option_flags; ///< Option flags. + sl_sleeptimer_timer_handle_t *next; ///< Pointer to next element in list. + sl_sleeptimer_timer_callback_t callback; ///< Function to call when timer expires. + uint32_t timeout_periodic; ///< Periodic timeout. + uint32_t delta; ///< Delay relative to previous element in list. + uint32_t timeout_expected_tc; ///< Expected tick count of the next timeout (only used for periodic timer). + uint16_t conversion_error; ///< The error when converting ms to ticks (thousandths of ticks) + uint16_t accumulated_error; ///< Accumulated conversion error (thousandths of ticks) +}; + +/// @brief Month enum. +SLEEPTIMER_ENUM(sl_sleeptimer_month_t) { + MONTH_JANUARY = 0, + MONTH_FEBRUARY = 1, + MONTH_MARCH = 2, + MONTH_APRIL = 3, + MONTH_MAY = 4, + MONTH_JUNE = 5, + MONTH_JULY = 6, + MONTH_AUGUST = 7, + MONTH_SEPTEMBER = 8, + MONTH_OCTOBER = 9, + MONTH_NOVEMBER = 10, + MONTH_DECEMBER = 11, +}; + +/// @brief Week Day enum. +SLEEPTIMER_ENUM(sl_sleeptimer_weekDay_t) { + DAY_SUNDAY = 0, + DAY_MONDAY = 1, + DAY_TUESDAY = 2, + DAY_WEDNESDAY = 3, + DAY_THURSDAY = 4, + DAY_FRIDAY = 5, + DAY_SATURDAY = 6, +}; + +/// @brief Time and Date structure. +typedef struct time_date { + uint8_t sec; ///< Second (0-59) + uint8_t min; ///< Minute of month (0-59) + uint8_t hour; ///< Hour (0-23) + uint8_t month_day; ///< Day of month (1-31) + sl_sleeptimer_month_t month; ///< Month (0-11) + uint16_t year; ///< Year, based on a 1900 Epoch. + sl_sleeptimer_weekDay_t day_of_week; ///< Day of week (0-6) + uint16_t day_of_year; ///< Day of year (1-366) + sl_sleeptimer_time_zone_offset_t time_zone; ///< Offset, in seconds, from UTC +} sl_sleeptimer_date_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Initializes the Sleeptimer. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_init(void); + +/***************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Stops a timer. + * + * @param handle Pointer to handle to timer. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); + +/***************************************************************************//** + * Gets the status of a timer. + * + * @param handle Pointer to handle to timer. + * @param running Pointer to the status of the timer. + * + * @note A non periodic timer is considered not running during its callback. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_is_timer_running(const sl_sleeptimer_timer_handle_t *handle, + bool *running); + +/***************************************************************************//** + * Gets remaining time until timer expires. + * + * @param handle Pointer to handle to timer. + * @param time Time left in timer ticks. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_get_timer_time_remaining(const sl_sleeptimer_timer_handle_t *handle, + uint32_t *time); + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + * + * @param option_flags Set of flags to match: + * - SL_SLEEPTIMER_ANY_TIMER_FLAG + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * + * @param time_remaining Time left in timer ticks. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining); + +/***************************************************************************//** + * Gets current 32 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_sleeptimer_get_tick_count(void); + +/***************************************************************************//** + * Gets current 64 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint64_t sl_sleeptimer_get_tick_count64(void); + +/***************************************************************************//** + * Get timer frequency. + * + * @return Timer frequency in hertz. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_sleeptimer_get_timer_frequency(void); + +/***************************************************************************//** + * Converts a Unix timestamp into a date. + * + * @param time 32 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a 64 bit Unix timestamp into a date. + * + * @param time 64 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a date into a Unix timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 32 bit Unix timestamp. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note Dates are based on the Unix time representation. + * Range of dates supported : + * - January 1, 1970, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts a date into a 64 bit timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 64 bit Unix timestamp. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note Dates are based on the 64 bit Unix time representation. + * Range of dates supported : + * - January 1, 1900, 00:00:00 to December 31, 11899 23:59:59. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time); + +/***************************************************************************//** + * Convert date to string. + * + * @param str Output string. + * @param size Size of the input array. + * @param format The format specification character. + * @param date Pointer to date structure. + * + * @return 0 if error. Number of character in the output string. + * + * @note Refer strftime() from UNIX. + * http://man7.org/linux/man-pages/man3/strftime.3.html + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset); + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void); + +/***************************************************************************//** + * Retrieves current 32 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); + +/***************************************************************************//** + * Retrieves current 64 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time); + +/***************************************************************************//** + * Gets current date. + * + * @param date Pointer to a sl_sleeptimer_date_t structure. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets current time, in date format. + * + * @param date Pointer to current date. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 10:14:07 PM 01/18/2038. + * + * @param date Pointer to the structure to be populated. + * @param year Current year. May be provided based on a 0 Epoch or a 1900 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 11:59:59 PM 12/31/11899. + * + * @param date Pointer to the structure to be populated. + * @param year Current year based on 0 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Resulting date structure's year will be based on 1900 epoch + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Converts Unix timestamp into NTP timestamp. + * + * @param time Unix timestamp. + * @param ntp_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x0 to 0x7C55 817F + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time); + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + * + * @param ntp_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note NTP timestamp range supported : 0x83AA 7E80 to 0xFFFF FFFF + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + * + * @param time Unix timestamp. + * + * @param zigbee_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x386D 4380 to 0x7FFF FFFF + * ie. January 1, 2000, 00:00:0 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time); + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + * + * @param zigbee_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note ZIGBEE timestamp range supported : 0x0 to 0x4792 BC7F + * ie. January 1, 2000, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Calculates offset for time zone after UTC-0. + * + * @param hours Number of hours from UTC-0. + * @param minutes Number of minutes from UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_ahead_utc(uint8_t hours, + uint8_t minutes) +{ + return ((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Calculates offset for time zone before UTC-0. + * + * @param hours Number of hours to UTC-0. + * @param minutes Number of minutes to UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_behind_utc(uint8_t hours, + uint8_t minutes) +{ + return -(sl_sleeptimer_time_zone_offset_t)((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Active delay. + * + * @param time_ms Delay duration in milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms); + +/***************************************************************************//** + * Converts milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * + * @return Corresponding ticks number. + * + * @note The result is "rounded" to the superior tick number. + * This function is light and cannot fail so it should be privilegied to + * perform a millisecond to tick conversion. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms); + +/***************************************************************************//** + * Converts 32-bits milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * @param tick Pointer to the converted tick number. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note The result is "rounded" to the superior tick number. + * If possible the sl_sleeptimer_ms_to_tick() function should be used. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'time_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'time_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick); + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + * + * @return Maximum time or timeout value in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void); + +/***************************************************************************//** + * Converts ticks in milliseconds. + * + * @param tick Number of tick. + * + * @return Corresponding milliseconds number. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick); + +/***************************************************************************//** + * Converts 64-bit ticks in milliseconds. + * + * @param tick Number of tick. + * @param ms Pointer to the converted milliseconds number. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms); + +/***************************************************************************//** + * Allow sleep after ISR exit. + * + * @return true if sleep is allowed after ISR exit. False otherwise. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); + +/**************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_start_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_restart_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup sleeptimer) */ + +/* *INDENT-OFF* */ +/* THE REST OF THE FILE IS DOCUMENTATION ONLY! */ +/// @addtogroup sleeptimer Sleep Timer +/// @{ +/// +/// @details +/// Sleep Timer can be used for creating timers which are tightly integrated with power management. +/// The Power Manager requires precision timing to have all clocks ready on time, so that wakeup +/// happens a little bit earlier to prepare the system to be ready at the right time. +/// Sleep Timer uses one Hardware Timer and creates multiple software timer instances. It is important +/// to note that when sleeptimer is used with WTIMER/TIMER, the MCU cannot go to EM2 energy mode +/// because WTIMER/TIMER uses a high frequency clock source which is not retained in low energy mode. +/// +/// The sleeptimer.c and sleeptimer.h source files for the SLEEPTIMER device driver library are in the +/// service/sleeptimer folder. +/// +/// @n @section sleeptimer_intro Introduction +/// +/// The Sleeptimer driver provides software timers, delays, timekeeping and date functionalities using a low-frequency real-time clock peripheral. +/// +/// All Silicon Labs microcontrollers equipped with the RTC or RTCC peripheral are currently supported. Only one instance of this driver can be initialized by the application. +/// +/// @n @section sleeptimer_functionalities_overview Functionalities overview +/// +/// @n @subsection software_timers Software Timers +/// +/// This functionality allows the user to create periodic and one shot timers. A user callback can be associated with a timer and is called when the timer expires. +/// +/// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. +/// +/// As sleeptimer callback functions are executed in ISR, they should be kept simple and short. +/// For periodic timers, the sleeptimer's callbacks need to be shorter than the timer's period to allow the application to exit the interrupt context. +/// +/// @n @subsection timekeeping Timekeeping +/// +/// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver +/// +/// The `SL_SLEEPTIMER_WALLCLOCK_CONFIG` configuration enables a UNIX timestamp (seconds count since January 1, 1970, 00:00:00). +/// +/// This timestamp can be retrieved/modified using the following API: +/// +/// @li sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); +/// @li sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); +/// +/// Convenience conversion functions are provided to convert UNIX timestamp to/from NTP and Zigbee cluster format : +/// +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, uint32_t *ntp_time); +/// @li sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, sl_sleeptimer_timestamp_t *time); +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, uint32_t *zigbee_time); +/// @li sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, sl_sleeptimer_timestamp_t *time); +/// +/// @n @subsection date Date +/// +/// The previously described internal timestamp can also be retrieved/modified in a date format sl_sleeptimer_date_t. +/// +/// @n API : @n +/// +/// @li sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); +/// @li sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); +/// +/// @n @subsection frequency_setup Frequency Setup and Tick Count +/// +/// This driver works with a configurable time unit called tick. +/// +/// The frequency of the ticks is based on the clock source and the internal frequency divider. +/// +/// WTIMER/TIMER peripherals uses high frequency oscillator. To have a reasonable tick frequency, divider is set to maximum value (1024). +/// +/// One of the following clock sources must be enabled before initializing the sleeptimer: +/// +/// @li LFXO: external crystal oscillator. Typically running at 32.768 kHz. +/// @li LFRCO: internal oscillator running at 32.768 kHz +/// @li ULFRCO: Ultra low-frequency oscillator running at 1.000 kHz +/// @li HFXO: High Frequency Crystal Oscillator at 39 Mhz. HFXO is only needed when Sleeptimer runs on TIMER or WTIMER. +/// +/// The frequency divider is selected with the `SL_SLEEPTIMER_FREQ_DIVIDER` configuration. Its value must be a power of two within the range of 1 to 32. The number of ticks per second (sleeptimer frequency) is dictated by the following formula: +/// +/// Tick (seconds) = 1 / (clock_frequency / frequency_divider) +/// +/// The highest resolution for a tick is 30.5 us. It is achieved with a 32.768 kHz clock and a divider of 1. +/// +/// @n @section sleeptimer_getting_started Getting Started +/// +/// @n @subsection clock_selection Clock Selection +/// +/// The sleeptimer relies on the hardware timer to operate. The hardware timer peripheral must be properly clocked from the application. Selecting the appropriate timer is crucial for design considerations. Each timer can potentially be used as a sleeptimer and is also available to the user. However, note that if a timer is used by the sleeptimer, it can't be used by the application and vice versa. +/// +/// For WTIMER/TIMER peripherals, the user must select the appropriate oscillator if it is not the default wanted clock source. +/// +/// When WTIMER/TIMER is selected, sleeptimer uses channel 0 and it is not possible to use other channels of the same instance for other purposes. +/// +/// When SYSRTC is chosen, the Peripheral Reflex System (PRS) channel 1 and 2 will be used by sleeptimer and become unavailable. PRS_GetFreeChannel() can be used to retrieve an unallocated channel. +/// +/// @n @subsection Clock Selection in a Project without Micrium OS +/// +/// When RTC, RTCC, or BURTC is selected, the clock source for the peripheral must be configured and enabled in the application before initializing the sleeptimer module or any communication stacks. Most of the time, it consists in enabling the desired oscillators and setting up the clock source for the peripheral, like in the following example: +/// +/// @code{.c} +/// CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); +/// CMU_ClockEnable(cmuClock_RTCC, true); +/// @endcode +/// +/// @n @subsection clock_branch_select Clock Branch Select +/// +/// | Clock | Enum | Description | Frequency | +/// |--------|-------------------------|-----------------------------------|-----------| +/// | LFXO | cmuSelect_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | LFRCO | cmuSelect_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | ULFRCO | cmuSelect_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @subsection timer_clock_enable Timer Clock Enable +/// +/// | Module | Enum | Description | +/// |--------------------|-----------------------|----------------------------------------------------| +/// | RTCC | cmuClock_RTCC | Real-time counter and calendar clock (LF E branch) | +/// | RTC | cmuClock_RTC | Real time counter clock (LF A branch) | +/// | BURTC | cmuClock_BURTC | BURTC clock (EM4 Group A branch) | +/// +/// When the Radio internal RTC (PRORTC) is selected, it is not necessary to configure the clock source for the peripheral. However, it is important to enable the desired oscillator before initializing the sleeptimer module or any communication stacks. The best oscillator available (LFXO being the first choice) will be used by the sleeptimer at initalization. The following example shows how the desired oscilator should be enabled: +/// +/// @code{.c} +/// CMU_OscillatorEnable(cmuSelect_LFXO, true, true); +/// @endcode +/// +/// @n @subsection clock_micrium_os Clock Selection in a Project with Micrium OS +/// +/// When Micrium OS is used, a BSP (all instances) is provided that sets up some parts of the clock tree. The sleeptimer clock source will be enabled by this bsp. However, the desired oscillator remains configurable from the file bsp_cfg.h. +/// +/// The configuration `BSP_LF_CLK_SEL` determines which oscillator will be used by the sleeptimer's hardware timer peripheral. It can take the following values: +/// +/// | Config | Description | Frequency | +/// |--------------------------|-----------------------------------|-----------| +/// | BSP_LF_CLK_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | BSP_LF_CLK_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | BSP_LF_CLK_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @section sleeptimer_conf Configuration Options +/// +/// `SL_SLEEPTIMER_PERIPHERAL` can be set to one of the following values: +/// +/// | Config | Description | +/// | --------------------------------- |------------------------------------------------------------------------------------------------------| +/// | `SL_SLEEPTIMER_PERIPHERAL_DEFAULT`| Selects either RTC or RTCC, depending of what is available on the platform. | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTCC` | Selects RTCC | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTC` | Selects RTC | +/// | `SL_SLEEPTIMER_PERIPHERAL_PRORTC` | Selects Internal radio RTC. Available only on EFR32XG13, EFR32XG14, EFR32XG21 and EFR32XG22 families.| +/// | `SL_SLEEPTIMER_PERIPHERAL_BURTC` | Selects BURTC. Not available on Series 0 devices. | +/// +/// `SL_SLEEPTIMER_WALLCLOCK_CONFIG` must be set to 1 to enable timestamp and date functionnalities. +/// +/// `SL_SLEEPTIMER_FREQ_DIVIDER` must be a power of 2 within the range 1 to 32. When `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`, `SL_SLEEPTIMER_FREQ_DIVIDER` must be set to 1. +/// +/// `SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER` is only meaningful when `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`. Set to 1 if no communication stack is used in your project. Otherwise, must be set to 0. +/// +/// @n @section sleeptimer_api The API +/// +/// This section contains brief descriptions of the API functions. For +/// more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, `SL_STATUS_OK` is returned on success, +/// see sl_status.h for other error codes. +/// +/// The application code must include the @em sl_sleeptimer.h header file. +/// +/// All API functions can be called from within interrupt handlers. +/// +/// @ref sl_sleeptimer_init() @n +/// These functions initialize the sleeptimer driver. Typically, +/// sl_sleeptimer_init() is called once in the startup code. +/// +/// @ref sl_sleeptimer_start_timer() @n +/// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_timer() @n +/// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_start_periodic_timer() @n +/// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_periodic_timer() @n +/// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_stop_timer() @n +/// Stop a timer. +/// +/// @ref sl_sleeptimer_get_timer_time_remaining() @n +/// Get the time remaining before the timer expires. +/// +/// @ref sl_sleeptimer_delay_millisecond() @n +/// Delay for the given number of milliseconds. This is an "active wait" delay function. +/// +/// @ref sl_sleeptimer_is_timer_running() @n +/// Check if a timer is running. +/// +/// @ref sl_sleeptimer_get_time(), @ref sl_sleeptimer_set_time() @n +/// Get or set wallclock time. +/// +/// @ref sl_sleeptimer_ms_to_tick(), @ref sl_sleeptimer_ms32_to_tick(), +/// @ref sl_sleeptimer_tick_to_ms(), @ref sl_sleeptimer_tick64_to_ms() @n +/// Convert between milliseconds and RTC/RTCC +/// counter ticks. +/// +/// @n @anchor callback The timer expiry callback function: @n +/// The callback function, prototyped as @ref sl_sleeptimer_timer_callback_t(), is called from +/// within the RTC peripheral interrupt handler on timer expiration. +/// sl_sleeptimer_timer_callback_t(sl_sleeptimer_timer_handle_t *handle, void *data) +/// +/// @n @section sleeptimer_example Example +/// @code{.c} +///#include "sl_sleeptimer.h" +/// +///void my_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data) +///{ +/// //Code executed when the timer expire. +///} +/// +///int start_timer(void) +///{ +/// sl_status_t status; +/// sl_sleeptimer_timer_handle_t my_timer; +/// uint32_t timer_timeout = 300; +/// +/// // We assume the sleeptimer is initialized properly +/// +/// status = sl_sleeptimer_start_timer(&my_timer, +/// timer_timeout, +/// my_timer_callback, +/// (void *)NULL, +/// 0, +/// 0); +/// if(status != SL_STATUS_OK) { +/// return -1; +/// } +/// return 1; +///} +/// @endcode +/// +/// @} (end addtogroup sleeptimer) + +#endif // SL_SLEEPTIMER_H diff --git a/Libs/platform/service/sleeptimer/inc/sli_sleeptimer.h b/Libs/platform/service/sleeptimer/inc/sli_sleeptimer.h new file mode 100644 index 0000000..5d8d7a1 --- /dev/null +++ b/Libs/platform/service/sleeptimer/inc/sli_sleeptimer.h @@ -0,0 +1,143 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER SDK internal APIs. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SLEEPTIMER_H +#define SLI_SLEEPTIMER_H + +#include +#include +#include +#include "em_device.h" +#include "sl_sleeptimer_config.h" +#include "sl_code_classification.h" + +#define SLEEPTIMER_EVENT_OF (0x01) +#define SLEEPTIMER_EVENT_COMP (0x02) + +#define SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG 0x02 +#define SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG 0x04 + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_DEFAULT +#if defined(RTCC_PRESENT) && RTCC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTCC +#elif defined(RTC_PRESENT) && RTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTC +#elif defined(SYSRTC_PRESENT) && SYSRTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_SYSRTC +#elif defined(BURTC_PRESENT) && BURTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_BURTC +#elif defined(WTIMER_PRESENT) && WTIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_WTIMER +#elif defined(TIMER_PRESENT) && TIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_TIMER +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to Power Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_power_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to HFXO Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_hfxo_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get interrupt status. + * + * @param local_flag Internal interrupt flag. + * + * @return Boolean indicating if specified interrupt is set. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag); + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @return true if power manager will expire at next compare match, + * false otherwise. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void); + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_sleeptimer_set_pm_em_requirement(void); +#endif + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Boolean value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag); + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + * + * @return Capture value + * 0 if capture channel is not valid + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sli_sleeptimer_get_capture(void); + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_sleeptimer_reset_prs_signal(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_SLEEPTIMER_H */ diff --git a/Libs/platform/service/sleeptimer/src/sl_sleeptimer.c b/Libs/platform/service/sleeptimer/src/sl_sleeptimer.c new file mode 100644 index 0000000..d271b66 --- /dev/null +++ b/Libs/platform/service/sleeptimer/src/sl_sleeptimer.c @@ -0,0 +1,1967 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include + +#include "em_device.h" +#include "sl_core.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "sl_atomic.h" +#include "sl_sleeptimer_config.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#include "sli_power_manager.h" +#endif + +#define TIME_UNIX_EPOCH (1970u) +#define TIME_NTP_EPOCH (1900u) +#define TIME_ZIGBEE_EPOCH (2000u) +#define TIME_64_EPOCH TIME_NTP_EPOCH +#define TIME_NTP_UNIX_EPOCH_DIFF (TIME_UNIX_EPOCH - TIME_NTP_EPOCH) +#define TIME_ZIGBEE_UNIX_EPOCH_DIFF (TIME_ZIGBEE_EPOCH - TIME_UNIX_EPOCH) +#define TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH (TIME_NTP_UNIX_EPOCH_DIFF * 365u + 17u) ///< 70 years and 17 leap days +#define TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH (TIME_ZIGBEE_UNIX_EPOCH_DIFF * 365u + 7u) ///< 30 years and 7 leap days +#define TIME_SEC_PER_DAY (60u * 60u * 24u) +#define TIME_NTP_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_ZIGBEE_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_DAY_PER_YEAR (365u) +#define TIME_SEC_PER_YEAR (TIME_SEC_PER_DAY * TIME_DAY_PER_YEAR) +#define TIME_UNIX_TIMESTAMP_MAX (0x7FFFFFFF) +#define TIME_64_BIT_UNIX_TIMESTAMP_MAX (0x497968BD7F) /// Max 64 bit timestamp supported is 11:59:59 PM 12/31/11899 +#define TIME_UNIX_YEAR_MAX (2038u - TIME_NTP_EPOCH) ///< Max UNIX year based from a 1900 epoch +#define TIME_64_BIT_YEAR_MAX (11899u - TIME_NTP_EPOCH) ///< Max 64 bit format year based from a 1900 epoch +#define TIME_64_TO_32_EPOCH_OFFSET_SEC TIME_NTP_EPOCH_OFFSET_SEC +#define TIME_UNIX_TO_NTP_MAX (0xFFFFFFFF - TIME_NTP_EPOCH_OFFSET_SEC) + +// Minimum count difference used when evaluating if a timer expired or not after an interrupt +// by comparing the current count value and the expected expiration count value. +// The difference should be null or of few ticks since the counter never stop. +#define MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION 2 + +/// @brief Time Format. +SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { + TIME_FORMAT_UNIX = 0, ///< Number of seconds since January 1, 1970, 00:00. Type is signed, so represented on 31 bit. + TIME_FORMAT_NTP = 1, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_ZIGBEE_CLUSTER = 2, ///< Number of seconds since January 1, 2000, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_UNIX_64_BIT = 3, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 64 bit. +}; + +// tick_count, it can wrap around. +typedef uint32_t sl_sleeptimer_tick_count_t; + +// Overflow counter used to provide 64-bits tick count. +static volatile uint32_t overflow_counter; + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +// Current time count. +static volatile sl_sleeptimer_timestamp_64_t second_count; +// Tick rest when the frequency is not a divider of the timer width. +static volatile uint32_t overflow_tick_rest = 0; +// Current time zone offset. +static sl_sleeptimer_time_zone_offset_t tz_offset = 0; +// Precalculated tick rest in case of overflow. +static uint32_t calculated_tick_rest = 0; +// Precalculated timer overflow duration in seconds. +static uint32_t calculated_sec_count = 0; +#endif + +// Timer frequency in Hz. +static uint32_t timer_frequency; + +// Head of timer list. +static sl_sleeptimer_timer_handle_t *timer_head; + +// Count at last update of delta of first timer. +static volatile sl_sleeptimer_tick_count_t last_delta_update_count; + +// Initialization flag. +static bool is_sleeptimer_initialized = false; + +// Flag that indicates if power manager's timer will expire at next compare match. +static volatile bool next_timer_to_expire_is_power_manager = false; + +// Precalculated value to avoid millisecond to tick conversion overflow. +static uint32_t max_millisecond_conversion; + +// Sleep on ISR exit flag. +static volatile bool sleep_on_isr_exit = false; + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static sl_status_t set_comparator_for_next_timer(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void update_delta_list(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE uint32_t div_to_log2(uint32_t div); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE bool is_power_of_2(uint32_t nbr); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void process_expired_timer(sl_sleeptimer_timer_handle_t *timer); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void update_next_timer_to_expire_is_power_manager(void); + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data); + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +static bool is_leap_year(uint16_t year); +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year); + +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day); +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day); +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool isLeapYear); + +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_date(sl_sleeptimer_date_t *date); + +static bool is_valid_date_64(sl_sleeptimer_date_t *date); + +static const uint8_t days_in_month[2u][12] = { + /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ + { 31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u }, + { 31u, 29u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u } +}; +#endif + +/**************************************************************************//** + * Initializes sleep timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (!is_sleeptimer_initialized) { + timer_head = NULL; + last_delta_update_count = 0u; + overflow_counter = 0u; + sleeptimer_hal_init_timer(); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_OF); + timer_frequency = sleeptimer_hal_get_timer_frequency(); + if (timer_frequency == 0) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_INVALID_CONFIGURATION; + } + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + second_count = 0; + calculated_tick_rest = ((uint64_t)UINT32_MAX + 1) % (uint64_t)timer_frequency; + calculated_sec_count = (((uint64_t)UINT32_MAX + 1) / (uint64_t)timer_frequency); +#endif + max_millisecond_conversion = (uint32_t)(((uint64_t)UINT32_MAX * (uint64_t)1000u) / timer_frequency); + is_sleeptimer_initialized = true; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Starts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_NOT_READY; + } + + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer is not running. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Stops a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t error; + bool set_comparator = false; + + // Disable PRS compare and capture channel, if configured for early wakeup +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (handle->option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + sleeptimer_hal_disable_prs_compare_and_capture_channel(); + } +#endif + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_CRITICAL(); + update_delta_list(); + + // If first timer in list, update timer comparator. + if (timer_head == handle) { + set_comparator = true; + } + + error = delta_list_remove_timer(handle); + if (error != SL_STATUS_OK) { + CORE_EXIT_CRITICAL(); + + return error; + } + + if (set_comparator) { + error = set_comparator_for_next_timer(); + if (error == SL_STATUS_NULL_POINTER) { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + } + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the status of a timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_is_timer_running(const sl_sleeptimer_timer_handle_t *handle, + bool *running) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || running == NULL) { + return SL_STATUS_NULL_POINTER; + } else { + *running = false; + CORE_ENTER_ATOMIC(); + current = timer_head; + while (current != NULL && !*running) { + if (current == handle) { + *running = true; + } else { + current = current->next; + } + } + CORE_EXIT_ATOMIC(); + } + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets a 32 bits timer's time remaining. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_timer_time_remaining(const sl_sleeptimer_timer_handle_t *handle, + uint32_t *time) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || time == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + update_delta_list(); + *time = handle->delta; + + // Retrieve timer in list and add the deltas. + current = timer_head; + while (current != handle && current != NULL) { + *time += current->delta; + current = current->next; + } + + if (current != handle) { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_NOT_READY; + } + + // Substract time since last compare match. + if (*time > sleeptimer_hal_get_counter() - last_delta_update_count) { + *time -= sleeptimer_hal_get_counter() - last_delta_update_count; + } else { + *time = 0; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + uint32_t time = 0; + + CORE_ENTER_ATOMIC(); + // parse list and retrieve first timer with option flags requirement. + current = timer_head; + while (current != NULL) { + // save time remaining for timer. + time += current->delta; + // Check if the current timer has the flags requested + if (current->option_flags == option_flags + || option_flags == SL_SLEEPTIMER_ANY_FLAG) { + // Substract time since last compare match. + if (time > (sleeptimer_hal_get_counter() - last_delta_update_count)) { + time -= (sleeptimer_hal_get_counter() - last_delta_update_count); + } else { + time = 0; + } + *time_remaining = time; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; + } + current = current->next; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_EMPTY; +} + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SL_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @note This function is for internal use only. + * + * @note A check to validate that the Power Manager Sleeptimer is expired on + * top of being the next timer was added. This is because + * this function is called when coming back from EM2 sleep to validate + * that the system woke up because of this precise timer expiration. + * Some race conditions, seen with FreeRTOS, could create invalid RTC + * interrupt leading to believe that the power manager timer was expired + * when it was not. + *****************************************************************************/ +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) +{ + bool next_timer_is_power_manager; + + sl_atomic_load(next_timer_is_power_manager, next_timer_to_expire_is_power_manager); + + // Make sure that the Power Manager Sleeptimer is actually expired in addition + // to being the next timer. + if (next_timer_is_power_manager + && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { + next_timer_is_power_manager = false; + } + + return next_timer_is_power_manager; +} + +/***************************************************************************//** +* Gets current 32 bits tick count. +*******************************************************************************/ +uint32_t sl_sleeptimer_get_tick_count(void) +{ + uint32_t cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + cnt = sleeptimer_hal_get_counter(); + CORE_EXIT_ATOMIC(); + + return cnt; +} + +/***************************************************************************//** +* Gets current 64 bits tick count. +*******************************************************************************/ +uint64_t sl_sleeptimer_get_tick_count64(void) +{ + uint32_t tick_cnt; + uint32_t of_cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt = overflow_counter; + + if (sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_OF)) { + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt++; + } + CORE_EXIT_ATOMIC(); + + return (((uint64_t) of_cnt) << 32) | tick_cnt; +} + +/***************************************************************************//** + * Get timer frequency. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_timer_frequency(void) +{ + return timer_frequency; +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/***************************************************************************//** + * Retrieves current 32 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void) +{ + uint64_t temp_time = sl_sleeptimer_get_time_64(); + // Add offset for 64 to 32 bit time + if (temp_time >= TIME_64_TO_32_EPOCH_OFFSET_SEC) { + temp_time -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + } + // Return lower 32 bits of 64 bit time + uint32_t time = (temp_time & 0xFFFFFFFF); + + return time; +} + +/***************************************************************************//** + * Retrieves current 64 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void) +{ + uint32_t cnt = 0u; + uint32_t freq = 0u; + sl_sleeptimer_timestamp_64_t time; + CORE_DECLARE_IRQ_STATE; + + cnt = sleeptimer_hal_get_counter(); + freq = sl_sleeptimer_get_timer_frequency(); + + CORE_ENTER_ATOMIC(); + time = second_count + cnt / freq; + + if (cnt % freq + overflow_tick_rest >= freq) { + time++; + } + CORE_EXIT_ATOMIC(); + + return time; +} + +/***************************************************************************//** + * Sets current time from 32 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time) +{ + // convert 32 bit time to 64 bit time + uint64_t temp_time = time + (uint64_t)TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_set_time_64(temp_time); + return err_code; +} + +/***************************************************************************//** + * Sets current time from 64 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time) +{ + uint32_t freq = 0u; + uint32_t counter_sec = 0u; + uint32_t cnt = 0; + CORE_DECLARE_IRQ_STATE; + + // convert 64 bit time to 32 bit time + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } + + freq = sl_sleeptimer_get_timer_frequency(); + cnt = sleeptimer_hal_get_counter(); + + CORE_ENTER_ATOMIC(); + // store 64 bit time as 64 bits's + second_count = time; + + // Convert 64 bit time to 32 bit time in order to check for overflow + // i.e. if 32 bit time is >=counter_sec + uint64_t temp_time = second_count - TIME_64_TO_32_EPOCH_OFFSET_SEC; + uint32_t second_time_32 = (temp_time & 0xFFFFFFFF); + + overflow_tick_rest = 0; + counter_sec = cnt / freq; + + if (second_time_32 >= counter_sec) { + second_count -= counter_sec; + } else { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets current date. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_sleeptimer_time_zone_offset_t tz; + sl_status_t err_code = SL_STATUS_OK; + + // Fetch 64 bit timestamp + time = sl_sleeptimer_get_time_64(); + tz = sl_sleeptimer_get_tz(); + err_code = sl_sleeptimer_convert_time_to_date_64(time, tz, date); + + return err_code; +} + +/***************************************************************************//** + * Sets current time, in date format. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_status_t err_code = SL_STATUS_OK; + CORE_DECLARE_IRQ_STATE; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + err_code = sl_sleeptimer_convert_date_to_time_64(date, &time); + if (err_code != SL_STATUS_OK) { + return err_code; + } + + CORE_ENTER_ATOMIC(); + // sets the 64 bit second_time value + err_code = sl_sleeptimer_set_time_64(time); + if (err_code == SL_STATUS_OK) { + sl_sleeptimer_set_tz(date->time_zone); + } + CORE_EXIT_ATOMIC(); + + return err_code; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // If year is smaller than 1900, assume NTP Epoch is used. + date->year = ((year < TIME_NTP_EPOCH) ? year : (year - TIME_NTP_EPOCH)); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week(((date->year - TIME_NTP_UNIX_EPOCH_DIFF) * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_UNIX_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Ensure that year is greater than 1900 and based on 0 epoch + if (year < TIME_NTP_EPOCH) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Convert year based on 0 epoch to a valid date->year based on 1900 epoch + date->year = (year - TIME_NTP_EPOCH); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week_64((date->year * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_NTP_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a 32 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + // convert 32 bit timestamp to 64 bit + sl_sleeptimer_timestamp_64_t temp_time = (uint64_t)time + TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_convert_time_to_date_64(temp_time, time_zone, date); + return err_code; +} + +/******************************************************************************* + * Convert a 64 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + uint16_t full_year = 0; + uint16_t leap_day = 0; + uint8_t leap_year_flag = 0; + uint8_t current_month = 0; + + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, time_zone)) { + return SL_STATUS_INVALID_PARAMETER; + } + + time += time_zone; // add UTC offset to convert to Standard Time + date->sec = time % 60; + time /= 60; + date->min = time % 60; + time /= 60; + date->hour = time % 24; + time /= 24; // time is now the number of days since 1900 + + date->day_of_week = (sl_sleeptimer_weekDay_t)compute_day_of_week_64(time); + + full_year = time / TIME_DAY_PER_YEAR; // Approximates the number of full years + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_day = number_of_leap_days(base_year, current_year); // Approximates the number of leap days. + full_year = (time - leap_day) / TIME_DAY_PER_YEAR; // Computes the number of year integrating the leap days. + current_year = full_year + base_year; + leap_day = number_of_leap_days(base_year, current_year); // Computes the actual number of leap days of the previous years. + } + date->year = full_year; // Year in date struct must be based on a 1900 epoch. + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + time = (time - leap_day) - (TIME_DAY_PER_YEAR * full_year); // Subtracts days of previous year. + date->day_of_year = time + 1; + + while (time >= days_in_month[leap_year_flag][current_month]) { + time -= days_in_month[leap_year_flag][current_month]; // Subtracts the number of days of the passed month. + current_month++; + } + date->month = (sl_sleeptimer_month_t)current_month; + date->month_day = time + 1; + date->time_zone = time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure into a 32 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time) +{ + // Create a 64 bit time stamp + sl_sleeptimer_timestamp_64_t temp_time = 0; + sl_status_t err_code = sl_sleeptimer_convert_date_to_time_64(date, &temp_time); + + if (err_code != SL_STATUS_OK) { + return err_code; + } + // Convert 64 bit time to 32 bit time + + sl_sleeptimer_timestamp_64_t time_32 = temp_time; + time_32 -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + *time = (time_32 & 0xFFFFFFFF); + + return err_code; +} + +/******************************************************************************* + * Convert a date structure into a 64 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time) +{ + uint16_t month_days = 0; + uint8_t month; + uint16_t full_year = 0; + uint8_t leap_year_flag = 0; + uint16_t leap_days = 0; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + full_year = (date->year); // base year for 64 bits its 1900 not 1970 + month = date->month; // offset to get months value from 1 to 12. + + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + *time = (full_year * (uint64_t)TIME_SEC_PER_YEAR); + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_days = number_of_leap_days(base_year, current_year); + month_days = leap_days; + } + + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + for (int i = 0; i < month; i++) { + month_days += days_in_month[leap_year_flag][i]; // Add the number of days of the month of the year. + } + + month_days += (date->month_day - 1); // Add full days of the current month. + *time += month_days * TIME_SEC_PER_DAY; + *time += (3600 * date->hour) + (60 * date->min) + date->sec; + *time -= date->time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure to string. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date) +{ + uint32_t return_size = 0u; + if (is_valid_date(date)) { + struct tm date_struct; + + date_struct.tm_hour = date->hour; + date_struct.tm_mday = date->month_day; + date_struct.tm_min = date->min; + date_struct.tm_mon = date->month; + date_struct.tm_sec = date->sec; + date_struct.tm_wday = date->day_of_week; + date_struct.tm_yday = date->day_of_year; + date_struct.tm_year = date->year; + + return_size = strftime(str, + size, + (const char *)format, + &date_struct); + } + + return return_size; +} + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tz_offset = offset; + CORE_EXIT_ATOMIC(); +} + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void) +{ + sl_sleeptimer_time_zone_offset_t offset; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + offset = tz_offset; + CORE_EXIT_ATOMIC(); + + return offset; +} + +/***************************************************************************//** + * Converts Unix 32 timestamp into NTP timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time) +{ + if (time > TIME_UNIX_TO_NTP_MAX) { + // Maximum Unix timestamp that can be converted to NTP is 2085978495 + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t temp_ntp_time; + temp_ntp_time = time + TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_ntp_time, TIME_FORMAT_NTP, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *ntp_time = temp_ntp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = ntp_time - TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time) +{ + uint32_t temp_zigbee_time; + temp_zigbee_time = time - TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_zigbee_time, TIME_FORMAT_ZIGBEE_CLUSTER, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *zigbee_time = temp_zigbee_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = zigbee_time + TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +#endif // SL_SLEEPTIMER_WALLCLOCK_CONFIG + +/******************************************************************************* + * Active delay of 'time_ms' milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms) +{ + volatile bool wait = true; + sl_status_t error_code; + sl_sleeptimer_timer_handle_t delay_timer; + uint32_t delay = sl_sleeptimer_ms_to_tick(time_ms); + + error_code = sl_sleeptimer_start_timer(&delay_timer, + delay, + delay_callback, + (void *)&wait, + 0, + 0); + if (error_code == SL_STATUS_OK) { + while (wait) { // Active delay loop. + } + } +} + +/******************************************************************************* + * Converts milliseconds in ticks. + ******************************************************************************/ +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms) +{ + return (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000); +} + +/******************************************************************************* + * Converts 32-bits milliseconds in ticks. + ******************************************************************************/ +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick) +{ + if (time_ms <= max_millisecond_conversion) { + *tick = (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000u); + return SL_STATUS_OK; + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void) +{ + return max_millisecond_conversion; +} + +/******************************************************************************* + * Converts ticks in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick) +{ + uint32_t time_ms; + time_ms = 0; + + if (timer_frequency != 0u) { + if (is_power_of_2(timer_frequency)) { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + } else { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + } + } + + return time_ms; +} + +/******************************************************************************* + * Converts 64-bits ticks in milliseconds. + ******************************************************************************/ +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms) + +{ + if ((tick <= UINT64_MAX / 1000) + && (timer_frequency != 0u)) { + if (is_power_of_2(timer_frequency)) { + *ms = (tick * (uint64_t)1000u) >> div_to_log2(timer_frequency); + return SL_STATUS_OK; + } else { + *ms = (tick * (uint64_t)1000u) / timer_frequency; + return SL_STATUS_OK; + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/******************************************************************************* + * Process timer interrupt. + * + * @param local_flag Flag indicating the type of timer interrupt. + ******************************************************************************/ +void process_timer_irq(uint8_t local_flag) +{ + CORE_DECLARE_IRQ_STATE; + if (local_flag & SLEEPTIMER_EVENT_OF) { +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + uint32_t timer_freq = sl_sleeptimer_get_timer_frequency(); + + overflow_tick_rest += calculated_tick_rest; + if (overflow_tick_rest >= timer_freq) { + second_count++; + overflow_tick_rest -= timer_freq; + } + second_count = second_count + calculated_sec_count; +#endif + overflow_counter++; + + update_delta_list(); + + set_comparator_for_next_timer(); + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sl_sleeptimer_timer_handle_t *current = NULL; + + uint32_t nb_timer_expire = 0u; + uint16_t option_flags = 0; + + CORE_ENTER_ATOMIC(); + // Make sure the timers list is up to date with the time elapsed since the last update + update_delta_list(); + + // Process all timers that have expired. + while (timer_head && (timer_head->delta == 0)) { + sl_sleeptimer_timer_handle_t *temp = timer_head; + current = timer_head; + + // Process timers with higher priority first + while ((temp != NULL) && (temp->delta == 0)) { + if (current->priority > temp->priority) { + current = temp; + } + temp = temp->next; + } + CORE_EXIT_ATOMIC(); + + process_expired_timer(current); + + // Save current option flag and the number of timers that expired. + option_flags = current->option_flags; + nb_timer_expire++; + + CORE_ENTER_ATOMIC(); + + // Re-update the list to account for delays during timer's callback. + update_delta_list(); + } + + // If the only timer expired is the internal Power Manager one, + // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. + sleep_on_isr_exit = false; + if ((nb_timer_expire == 1u) && (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG)) { + sleep_on_isr_exit = true; + } + + sl_status_t error = set_comparator_for_next_timer(); + if (error == SL_STATUS_NULL_POINTER) { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_ATOMIC(); + } +} + +/******************************************************************************* + * Timer expiration callback for the delay function. + * + * @param handle Pointer to handle to timer. + * @param data Pointer to delay flag. + ******************************************************************************/ +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + volatile bool *wait_flag = (bool *)data; + + (void)handle; // Unused parameter. + + *wait_flag = false; +} + +/******************************************************************************* + * Inserts a timer in the delta list. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in ticks. + ******************************************************************************/ +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout) +{ + sl_sleeptimer_tick_count_t local_handle_delta = timeout; + +#ifdef SL_CATALOG_POWER_MANAGER_PRESENT + // If Power Manager is present, it's possible that a clock restore is needed right away + // if we are in the context of a deepsleep and the timeout value is smaller than the restore time. + // If it's the case, the restore will be started and the timeout value will be updated to match + // the restore delay. + if (handle->option_flags == 0) { + uint32_t wakeup_delay = sli_power_manager_get_restore_delay(); + + if (local_handle_delta < wakeup_delay) { + local_handle_delta = wakeup_delay; + sli_power_manager_initiate_restore(); + } + } +#endif + + handle->delta = local_handle_delta; + + if (timer_head != NULL) { + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + // Find timer position taking into accounts the deltas and priority. + while (current != NULL + && (local_handle_delta >= current->delta || current->delta == 0u + || (((local_handle_delta - current->delta) == 0) && (handle->priority > current->priority)))) { + local_handle_delta -= current->delta; + handle->delta = local_handle_delta; + prev = current; + current = current->next; + } + + // Insert timer in middle of delta list. + if (prev != NULL) { + prev->next = handle; + } else { + timer_head = handle; + } + handle->next = current; + + if (current != NULL) { + current->delta -= local_handle_delta; + } + } else { + timer_head = handle; + handle->next = NULL; + } +} + +/******************************************************************************* + * Removes a timer from delta list. + * + * @param handle Pointer to handle to timer. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) +{ + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Retrieve timer in delta list. + while (current != NULL && current != handle) { + prev = current; + current = current->next; + } + + if (current != handle) { + return SL_STATUS_INVALID_STATE; + } + + if (prev != NULL) { + prev->next = handle->next; + } else { + timer_head = handle->next; + } + + // Update delta of next timer + if (handle->next != NULL) { + handle->next->delta += handle->delta; + } + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Sets comparator for next timer. + ******************************************************************************/ +static sl_status_t set_comparator_for_next_timer(void) +{ + if (timer_head) { + if (timer_head->delta > 0) { + sl_sleeptimer_tick_count_t compare_value; + + compare_value = last_delta_update_count + timer_head->delta; + + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_compare(compare_value); + } else { + // In case timer has already expire, don't attempt to set comparator. Just + // trigger compare match interrupt. + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); + } + update_next_timer_to_expire_is_power_manager(); + return SL_STATUS_OK; + } + + return SL_STATUS_NULL_POINTER; +} + +/******************************************************************************* + * Updates timer list's deltas. + ******************************************************************************/ +static void update_delta_list(void) +{ + sl_sleeptimer_tick_count_t current_cnt = sleeptimer_hal_get_counter(); + sl_sleeptimer_timer_handle_t *timer_handle = timer_head; + sl_sleeptimer_tick_count_t time_diff = current_cnt - last_delta_update_count; + + // Go through the delta timer list and update every necessary deltas + // according to the time elapsed since the last update. + while (timer_handle != NULL && time_diff > 0) { + if (timer_handle->delta >= time_diff) { + timer_handle->delta -= time_diff; + time_diff = 0; + } else { + time_diff -= timer_handle->delta; + timer_handle->delta = 0; + } + timer_handle = timer_handle->next; + } + + last_delta_update_count = current_cnt; +} + +/******************************************************************************* + * Creates and start a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_initial Initial timeout, in timer ticks. + * @param timeout_periodic Periodic timeout, in timer ticks. This timeout + * applies once timeoutInitial expires. Can be set to 0 for a one + * shot timer. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + CORE_DECLARE_IRQ_STATE; + + handle->priority = priority; + handle->callback_data = callback_data; + handle->next = NULL; + handle->timeout_periodic = timeout_periodic; + handle->callback = callback; + handle->option_flags = option_flags; + if (timeout_periodic == 0) { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_initial; + } else { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_periodic; + } + + if (timeout_initial == 0) { + handle->delta = 0; + if (handle->callback != NULL) { + handle->callback(handle, handle->callback_data); + } + if (timeout_periodic != 0) { + timeout_initial = timeout_periodic; + } else { + return SL_STATUS_OK; + } + } + +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + HFXO0->CTRL |= HFXO_CTRL_EM23ONDEMAND; + sleeptimer_hal_set_compare_prs_hfxo_startup(timeout_initial); + return SL_STATUS_OK; + } +#endif + + CORE_ENTER_CRITICAL(); + update_delta_list(); + delta_list_insert_timer(handle, timeout_initial); + + // If first timer, update timer comparator. + if (timer_head == handle) { + set_comparator_for_next_timer(); + } + + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Processes an expired timer. + * + * @param timer Expired timer to process. + ******************************************************************************/ +static void process_expired_timer(sl_sleeptimer_timer_handle_t *timer) +{ + CORE_DECLARE_IRQ_STATE; + int32_t periodic_correction = 0u; + int64_t timeout_temp = 0; + bool skip_remove = false; + + // Check if periodic timer was delayed more than its actual timeout value + // and keep it at the head of the timers list if it's the case so that the + // callback function can be called the number of required time. + if (timer->timeout_periodic != 0u) { + timeout_temp = timer->timeout_periodic; + + periodic_correction = sleeptimer_hal_get_counter() - timer->timeout_expected_tc; + if (periodic_correction >= timeout_temp) { + skip_remove = true; + timer->timeout_expected_tc += timer->timeout_periodic; + } + } + + // Remove timer from list except if the timer is a periodic timer that was + // intentionally kept at the head of the timers list. + if (skip_remove != true) { + CORE_ENTER_ATOMIC(); + delta_list_remove_timer(timer); + CORE_EXIT_ATOMIC(); + } + + // Re-insert periodic timer that was previsouly removed from the list + // and compensate for any deviation from the periodic timer frequency. + if (timer->timeout_periodic != 0u && skip_remove != true) { + timeout_temp -= periodic_correction; + EFM_ASSERT(timeout_temp > 0); + // Compensate for drift caused by ms to ticks conversion + if (timer->conversion_error > 0) { + // Increment accumulated error by the ms to ticks conversion error + timer->accumulated_error += timer->conversion_error; + // If the accumulated error exceeds a tick, subtract that tick from the next + // periodic timer's timeout value. + if (timer->accumulated_error >= 1000) { + timer->accumulated_error -= 1000; + timeout_temp -= 1; + timer->timeout_expected_tc -= 1; + } + } + CORE_ENTER_ATOMIC(); + delta_list_insert_timer(timer, (sl_sleeptimer_tick_count_t)timeout_temp); + timer->timeout_expected_tc += timer->timeout_periodic; + CORE_EXIT_ATOMIC(); + } + + // Call timer callback function if any. + if (timer->callback != NULL) { + timer->callback(timer, timer->callback_data); + } +} + +/******************************************************************************* + * Updates internal flag that indicates if next timer to expire is the power + * manager's one. + ******************************************************************************/ +static void update_next_timer_to_expire_is_power_manager(void) +{ + sl_sleeptimer_timer_handle_t *current = timer_head; + uint32_t delta_diff_with_first = 0; + + next_timer_to_expire_is_power_manager = false; + + while ((delta_diff_with_first <= 1) && (current != NULL)) { + if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { + next_timer_to_expire_is_power_manager = true; + break; + } + + current = current->next; + if (current != NULL) { + delta_diff_with_first += current->delta; + } + } +} + +/**************************************************************************//** + * Determines if the power manager's early wakeup expired during the last ISR + * and it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + *****************************************************************************/ +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void) +{ + CORE_DECLARE_IRQ_STATE; + bool sleep; + + CORE_ENTER_ATOMIC(); + sleep = sleep_on_isr_exit; + CORE_EXIT_ATOMIC(); + + return sleep; +} + +/******************************************************************************* + * Convert dividend to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param div An unscaled dividend. + * + * @return Logarithm of 2. + ******************************************************************************/ +__STATIC_INLINE uint32_t div_to_log2(uint32_t div) +{ + return 31UL - __CLZ(div); // Count leading zeroes and "reverse" result. +} + +/******************************************************************************* + * Determines if a number is a power of two. + * + * @param nbr Input value. + * + * @return True if the number is a power of two. + ******************************************************************************/ +__STATIC_INLINE bool is_power_of_2(uint32_t nbr) +{ + if ((nbr != 0u) && ((nbr & (nbr - 1u)) == 0u)) { + return true; + } else { + return false; + } +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1970. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 4) % 7); // January 1st was a Thursday(4) in 1970 +} + +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1900. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 1) % 7); // January 1st was a Monday(1) in 1900 +} + +/******************************************************************************* + * Compute the day of the year. This function assumes that the inputs are properly + * sanitized. + * + * @param month Number of months since January. + * @param day Day of the month + * @param is_leap_year Specifies if the year computed against is a leap year. + * + * @return the number of days since the beginning of the year + ******************************************************************************/ +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool is_leap_year) +{ + uint8_t i; + uint16_t dayOfYear = 0; + + for (i = 0; i < month; ++i) { + dayOfYear += days_in_month[is_leap_year][i]; + } + dayOfYear += day; + + return dayOfYear; +} + +/******************************************************************************* + * Checks if the year is a leap year. + * + * @param year Year to check. + * + * @return true if the year is a leap year. False otherwise. + ******************************************************************************/ +static bool is_leap_year(uint16_t year) +{ + // 1900 is not a leap year but 0 % anything is 0. + if (year == 0) { + return false; + } + + bool leap_year; + + leap_year = (((year % 4u) == 0u) + && (((year % 100u) != 0u) || ((year % 400u) == 0u))) ? true : false; + + return (leap_year); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param base_year Year to start from to compute leap days. + * @param current_year Year end at for computing leap days. + * + * @return leap_days Days number of leap days between base_year and current_year. + ******************************************************************************/ +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year) +{ + // Regular leap years + uint16_t lo_reg = (base_year - 0) / 4; + uint16_t hi_reg = (current_year - 1) / 4; + uint16_t leap_days = hi_reg - lo_reg; + + // Account for non leap years + uint16_t lo_century = (base_year - 0) / 100; + uint16_t hi_century = (current_year - 1) / 100; + leap_days -= hi_century - lo_century; + + // Account for quad century leap years + uint16_t lo_quad = (base_year - 0) / 400; + uint16_t hi_quad = (current_year - 1) / 400; + leap_days += hi_quad - lo_quad; + + return (leap_days); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint32_t)abs(time_zone)) \ + || (time_zone >= 0 && (time <= UINT32_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX) { + if (time > TIME_UNIX_TIMESTAMP_MAX) { // Check if Unix time stamp is an unsigned 31 bits. + valid_time = false; + } + } else { + if ((format == TIME_FORMAT_NTP) && (time >= TIME_NTP_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else if ((format == TIME_FORMAT_ZIGBEE_CLUSTER) && (time <= TIME_UNIX_TIMESTAMP_MAX - TIME_ZIGBEE_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else { + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint64_t)abs(time_zone)) + || (time_zone >= 0 && (time <= UINT64_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX_64_BIT) { + if (time > TIME_64_BIT_UNIX_TIMESTAMP_MAX) { // Check if time stamp is an unsigned 64 bits. + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_UNIX_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + + // Unix is valid until the 19th of January 2038 at 03:14:07 + if (date->year == TIME_UNIX_YEAR_MAX) { + if ((uint8_t)date->month > (uint8_t)MONTH_JANUARY) { + return false; + } else if (date->month_day > 19) { + return false; + } else if (date->hour > 3) { + return false; + } else if (date->min > 14) { + return false; + } else if (date->sec > 7) { + return false; + } + } + + return true; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date_64(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_64_BIT_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + return true; +} +#endif + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void) +{ + return sleeptimer_hal_get_clock_accuracy(); +} + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag) +{ + sleep_on_isr_exit = flag; +} + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + ******************************************************************************/ +uint32_t sli_sleeptimer_get_capture(void) +{ + return sleeptimer_hal_get_capture(); +} + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +void sli_sleeptimer_reset_prs_signal(void) +{ + sleeptimer_hal_reset_prs_signal(); +} diff --git a/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c new file mode 100644 index 0000000..1769992 --- /dev/null +++ b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c @@ -0,0 +1,381 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER Hardware abstraction implementation for BURTC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) || defined(_SILICON_LABS_32B_SERIES_3) + +// Define module name for Power Manager debug feature +#define CURRENT_MODULE_NAME "SLEEPTIMER_BURTC" + +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" + +#include "sl_core.h" + +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_burtc.h" + +#define sleeptimer_hal_burtc_get_counter() BURTC_CounterGet() +#define sleeptimer_hal_burtc_get_compare() BURTC_CompareGet(0U) +#define sleeptimer_hal_burtc_set_compare(compare) BURTC_CompareSet(0, compare) +#define sleeptimer_hal_burtc_get_interrupts() BURTC_IntGet() +#define sleeptimer_hal_burtc_set_interrupts(flags) BURTC_IntSet(flags) +#define sleeptimer_hal_burtc_enable_interrupts(interrupts) BURTC_IntEnable(interrupts) +#define sleeptimer_hal_burtc_disable_interrupts(interrupts) BURTC_IntDisable(interrupts) +#define sleeptimer_hal_burtc_clear_interrupts(flags) BURTC_IntClear(flags) + +#elif defined(_SILICON_LABS_32B_SERIES_3) +#include "sl_hal_burtc.h" + +#define sleeptimer_hal_burtc_get_counter() sl_hal_burtc_get_counter() +#define sleeptimer_hal_burtc_get_compare() sl_hal_burtc_get_compare() +#define sleeptimer_hal_burtc_set_compare(compare) sl_hal_burtc_set_compare(compare) +#define sleeptimer_hal_burtc_get_interrupts() sl_hal_burtc_get_pending_interrupts() +#define sleeptimer_hal_burtc_set_interrupts(flags) sl_hal_burtc_set_interrupts(flags) +#define sleeptimer_hal_burtc_enable_interrupts(interrupts) sl_hal_burtc_enable_interrupts(interrupts) +#define sleeptimer_hal_burtc_disable_interrupts(interrupts) sl_hal_burtc_disable_interrupts(interrupts) +#define sleeptimer_hal_burtc_clear_interrupts(flags) sl_hal_burtc_clear_interrupts(flags) + +#endif + +#include "sl_clock_manager.h" +#include "sl_device_peripheral.h" +#include "sl_interrupt_manager.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_BURTC + +#if defined(_SILICON_LABS_32B_SERIES_0) +#error BURTC implementation of the sleeptimer not available on Series 0 chips +#endif + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define SLEEPTIMER_COMPARE_MIN_DIFF (5 + 1) +#else +#define SLEEPTIMER_COMPARE_MIN_DIFF (4 + 1) +#endif + +#define SLEEPTIMER_TMR_WIDTH (_BURTC_CNT_MASK) + +static uint32_t get_time_diff(uint32_t a, uint32_t b); + +/****************************************************************************** + * Convert HAL interrupt flag BURTC-interrupt-enable bitmask + *****************************************************************************/ +static uint32_t irqien_hal2burtc(uint8_t hal_flag) +{ + uint32_t burtc_if = 0u; + + if (hal_flag & SLEEPTIMER_EVENT_OF) { + burtc_if |= BURTC_IEN_OF; + } + + if (hal_flag & SLEEPTIMER_EVENT_COMP) { + burtc_if |= BURTC_IEN_COMP; + } + + return burtc_if; +} + +/****************************************************************************** + * Convert BURTC interrupt flags to HAL events + *****************************************************************************/ +static uint8_t irqflags_burtc2hal(uint32_t burtc_flag) +{ + uint8_t hal_if = 0u; + + if (burtc_flag & BURTC_IF_OF) { + hal_if |= SLEEPTIMER_EVENT_OF; + } + + if (burtc_flag & BURTC_IF_COMP) { + hal_if |= SLEEPTIMER_EVENT_COMP; + } + + return hal_if; +} + +/****************************************************************************** + * Initializes BURTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer() +{ + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_BURTC); + +#if defined(_SILICON_LABS_32B_SERIES_2) + BURTC_Init_TypeDef burtc_init = BURTC_INIT_DEFAULT; + + burtc_init.start = false; + burtc_init.clkDiv = SL_SLEEPTIMER_FREQ_DIVIDER; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + burtc_init.debugRun = true; +#endif + + BURTC_Init(&burtc_init); + BURTC_IntDisable(_BURTC_IEN_MASK); + BURTC_IntClear(_BURTC_IF_MASK); + BURTC_CounterReset(); + + BURTC_Start(); + BURTC_SyncWait(); +#elif defined(_SILICON_LABS_32B_SERIES_3) + sl_hal_burtc_init_config_t burtc_init = SL_HAL_BURTC_INIT_DEFAULT; + + burtc_init.clock_divider = SL_SLEEPTIMER_FREQ_DIVIDER; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + burtc_init.debug_run = true; +#endif + sl_hal_burtc_init(&burtc_init); + sl_hal_burtc_enable(); + sl_hal_burtc_disable_interrupts(_BURTC_IEN_MASK); + sl_hal_burtc_clear_interrupts(_BURTC_IF_MASK); + sl_hal_burtc_reset_counter(); + + sl_hal_burtc_start(); + sl_hal_burtc_wait_sync(); +#endif + + // Setup BURTC interrupt + sl_interrupt_manager_clear_irq_pending(BURTC_IRQn); + sl_interrupt_manager_enable_irq(BURTC_IRQn); +} + +/****************************************************************************** + * Gets BURTC counter. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return sleeptimer_hal_burtc_get_counter(); +} + +/****************************************************************************** + * Gets BURTC compare value + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return sleeptimer_hal_burtc_get_compare(); +} + +/****************************************************************************** + * Sets BURTC compare value + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the BURTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare_current; + uint32_t compare_new = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare_current = sleeptimer_hal_get_compare(); + + if ((((sleeptimer_hal_burtc_get_interrupts()) & _BURTC_IF_COMP_MASK) != 0) + || get_time_diff(compare_current, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare_current == counter) { + // Add margin if necessary + if (get_time_diff(compare_new, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_new = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + + // wrap around if necessary + compare_new %= SLEEPTIMER_TMR_WIDTH; + sleeptimer_hal_burtc_set_compare(compare_new - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + sleeptimer_hal_burtc_enable_interrupts(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Disables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + sleeptimer_hal_burtc_disable_interrupts(irqien_hal2burtc(local_flag)); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + sleeptimer_hal_burtc_set_interrupts(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + + uint32_t irq_flag = sleeptimer_hal_burtc_get_interrupts(); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = (irq_flag & BURTC_IF_COMP); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = (irq_flag & BURTC_IF_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * Gets BURTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + uint32_t frequency; + sl_clock_branch_t clock_branch; + + clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_BURTC); + sl_clock_manager_get_clock_branch_frequency(clock_branch, &frequency); + return (frequency >> (sleeptimer_hal_presc_to_log2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); +} + +/******************************************************************************* + * BURTC interrupt handler. + ******************************************************************************/ +void BURTC_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + + irq_flag = sleeptimer_hal_burtc_get_interrupts(); + + local_flag = irqflags_burtc2hal(irq_flag); + + sleeptimer_hal_burtc_clear_interrupts(irq_flag & (BURTC_IF_OF | BURTC_IF_COMP)); + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +static uint32_t get_time_diff(uint32_t a, uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + uint16_t precision; + sl_clock_manager_get_clock_branch_precision(SL_CLOCK_BRANCH_EM4GRPACLK, &precision); + return precision; +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +} +#endif +#endif + +#endif diff --git a/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c new file mode 100644 index 0000000..655fae8 --- /dev/null +++ b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c @@ -0,0 +1,443 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for SYSRTC. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Define module name for Power Manager debug feature +#define CURRENT_MODULE_NAME "SLEEPTIMER_SYSRTC" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "sl_hal_sysrtc.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "sl_code_classification.h" +#include "sl_core.h" +#include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" +#include "sl_device_peripheral.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) || defined(SL_CATALOG_HFXO_MANAGER_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_prs.h" +#else +#include "sl_hal_prs.h" +#endif +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) + +#define SLEEPTIMER_TMR_WIDTH (_SYSRTC_CNT_MASK) + +static bool cc_disabled = true; + +static bool cc1_disabled = true; + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes SYSRTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + sl_hal_sysrtc_config_t sysrtc_config = SYSRTC_CONFIG_DEFAULT; + sl_hal_sysrtc_group_config_t group_config = SYSRTC_GROUP_CONFIG_DEFAULT; + + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_SYSRTC0); + + // Make sure the bus clock enabling is done. + __DSB(); + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + sysrtc_config.enable_debug_run = true; +#endif + + sl_hal_sysrtc_init(&sysrtc_config); + + group_config.compare_channel0_enable = false; + + sl_hal_sysrtc_init_group(0u, &group_config); + + sl_hal_sysrtc_disable_group_interrupts(0u, _SYSRTC_GRP0_IEN_MASK); + sl_hal_sysrtc_clear_group_interrupts(0u, _SYSRTC_GRP0_IF_MASK); + sl_hal_sysrtc_enable(); + sl_hal_sysrtc_set_counter(0u); + + sl_interrupt_manager_clear_irq_pending(SYSRTC_APP_IRQn); + sl_interrupt_manager_enable_irq(SYSRTC_APP_IRQn); +} + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to Power Manager. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_hal_power_manager_integration_init(void) +{ + // Initialize PRS to start HFXO for early wakeup + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_PRS); + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS_ConnectSignal(1UL, prsTypeAsync, prsSignalSYSRTC0_GRP0OUT1); + PRS_ConnectConsumer(1UL, prsTypeAsync, prsConsumerHFXO0_OSCREQ); +#else + sl_hal_prs_async_connect_channel_producer(1UL, SL_HAL_PRS_ASYNC_SYSRTC0_GRP0OUT1); + sl_hal_prs_connect_channel_consumer(1UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_HFXO0_OSCREQ); +#endif + + // Set SYSRTC Compare Channel 1 + SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); +} +#endif + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to HFXO Manager. + ******************************************************************************/ +#if defined(SL_CATALOG_HFXO_MANAGER_PRESENT) +void sli_sleeptimer_hal_hfxo_manager_integration_init(void) +{ + // Set PRS signal from HFXO to SYSRTC capture channel + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_PRS); + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS_ConnectSignal(2UL, prsTypeAsync, prsSignalHFXO0L_STATUS1); + PRS_ConnectConsumer(2UL, prsTypeAsync, prsConsumerSYSRTC0_SRC0); +#else + sl_hal_prs_async_connect_channel_producer(2UL, SL_HAL_PRS_ASYNC_SYXO0L_STATUS1); + sl_hal_prs_connect_channel_consumer(2UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_SYSRTC0_IN0); +#endif + + // Set SYSRTC Capture Channel + SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); +} +#endif + +/****************************************************************************** + * Gets SYSRTC counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return sl_hal_sysrtc_get_counter(); +} + +/****************************************************************************** + * Gets SYSRTC channel zero's compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return sl_hal_sysrtc_get_group_compare_channel_value(0u, 0u); +} + +/****************************************************************************** + * Sets SYSRTC channel zero's compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the SYSRTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((sl_hal_sysrtc_get_group_interrupts(0u) & SYSRTC_GRP0_IEN_CMP0) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + sl_hal_sysrtc_set_group_compare_channel_value(0u, 0u, compare_value - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); + + if (cc_disabled) { + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP0EN; + cc_disabled = false; + } +} + +/******************************************************************************* + * Sets SYSRTC channel one's compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the SYSRTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + ******************************************************************************/ +void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare_value; + + CORE_ENTER_CRITICAL(); + + counter = sleeptimer_hal_get_counter(); + + compare_value = value + counter; + + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + + compare_value %= SLEEPTIMER_TMR_WIDTH; + + sl_hal_sysrtc_set_group_compare_channel_value(0u, 1u, compare_value - 1); + + CORE_EXIT_CRITICAL(); + + if (cc1_disabled) { + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP1EN; + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CAP0EN; + cc1_disabled = false; + } +} + +/****************************************************************************** + * Enables SYSRTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t sysrtc_ien = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + sysrtc_ien |= SYSRTC_GRP0_IEN_OVF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sysrtc_ien |= SYSRTC_GRP0_IEN_CMP0; + } + + sl_hal_sysrtc_enable_group_interrupts(0u, sysrtc_ien); +} + +/****************************************************************************** + * Disables SYSRTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t sysrtc_int_dis = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + sysrtc_int_dis |= SYSRTC_GRP0_IEN_OVF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sysrtc_int_dis |= SYSRTC_GRP0_IEN_CMP0; + + cc_disabled = true; + SYSRTC0->GRP0_CTRL &= ~_SYSRTC_GRP0_CTRL_CMP0EN_MASK; + } + + sl_hal_sysrtc_disable_group_interrupts(0u, sysrtc_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + SYSRTC0->GRP0_IF_SET = SYSRTC_GRP0_IF_CMP0; + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & SYSRTC_GRP0_IF_CMP0) == SYSRTC_GRP0_IF_CMP0); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & SYSRTC_GRP0_IF_OVF) == SYSRTC_GRP0_IF_OVF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * SYSRTC interrupt handler. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, + SL_CODE_CLASS_TIME_CRITICAL) +void SYSRTC_APP_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); + + if (irq_flag & SYSRTC_GRP0_IF_OVF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + + if (irq_flag & SYSRTC_GRP0_IF_CMP0) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + sl_hal_sysrtc_clear_group_interrupts(0u, irq_flag & (SYSRTC_GRP0_IF_OVF | SYSRTC_GRP0_IF_CMP0)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets SYSRTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + uint32_t frequency; + sl_clock_branch_t clock_branch; + + clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_SYSRTC0); + sl_clock_manager_get_clock_branch_frequency(clock_branch, &frequency); + return frequency; +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + uint16_t precision; + sl_clock_manager_get_clock_branch_precision(SL_CLOCK_BRANCH_SYSRTCCLK, &precision); + return precision; +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + if ((sl_hal_sysrtc_get_group_interrupts(0) & _SYSRTC_GRP0_IF_CAP0_MASK) != 0) { + sl_hal_sysrtc_clear_group_interrupts(0, _SYSRTC_GRP0_IF_CAP0_MASK); + return sl_hal_sysrtc_get_group_capture_channel_value(0); + } else { + return 0; + } +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + sl_hal_sysrtc_clear_group_interrupts(0, SYSRTC_GRP0_IF_CMP1); +} + +/******************************************************************************* + * Hardware Abstraction Layer to disable PRS compare and capture channel. + ******************************************************************************/ +void sleeptimer_hal_disable_prs_compare_and_capture_channel(void) +{ + if (!cc1_disabled) { + SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CMP1EN; + SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CAP0EN; + cc1_disabled = true; + } +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +} +#endif +#endif diff --git a/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c new file mode 100644 index 0000000..132c73c --- /dev/null +++ b/Libs/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c @@ -0,0 +1,393 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for TIMER. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Define module name for Power Manager debug feature +#define CURRENT_MODULE_NAME "SLEEPTIMER_TIMER" + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_timer.h" +#elif defined(_SILICON_LABS_32B_SERIES_3) +#include "sl_hal_timer.h" +#endif +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "sl_core.h" +#include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" +#include "sl_device_peripheral.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (1 + 1) + +// Macros used to constructs TIMER instance +#define _CONCAT_TWO_TOKENS(token_1, token_2) token_1 ## token_2 +#define _CONCAT_THREE_TOKENS(token_1, token_2, token_3) token_1 ## token_2 ## token_3 +#define CONCAT_TWO_TOKENS(token_1, token_2) _CONCAT_TWO_TOKENS(token_1, token_2) +#define CONCAT_THREE_TOKENS(token_1, token_2, token_3) _CONCAT_THREE_TOKENS(token_1, token_2, token_3) + +#if defined(TIMER_PRESENT) \ + && (SL_SLEEPTIMER_TIMER_INSTANCE < TIMER_COUNT) \ + && (TIMER_CNTWIDTH(SL_SLEEPTIMER_TIMER_INSTANCE) == 0x20) + #define SLEEPTIMER_TIMER_INSTANCE TIMER(SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_CHANNEL 0 + #define SLEEPTIMER_PERIPHERAL_TIMER CONCAT_TWO_TOKENS(SL_PERIPHERAL_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) + #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) + #define SLEEPTIMER_TIMER_IEN_COMPARE TIMER_IEN_CC0 + #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(SL_BUS_CLOCK_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_TOP_MAX _TIMER_TOP_MASK + #define SLEEPTIMER_TMR_WIDTH _TIMER_CNT_MASK +#else + #define TIMER_UNSUPORTED +#endif + +#if defined(TIMER_UNSUPORTED) +#error "The TIMER peripheral instance or channel is not supported. It must be a valid 32-bits size instance." +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) +#define sleeptimer_hal_timer_get_counter(timer_instance) TIMER_CounterGet(timer_instance) +#define sleeptimer_hal_timer_get_compare(timer_instance, channel) TIMER_CaptureGet(timer_instance, channel) +#define sleeptimer_hal_timer_set_compare(timer_instance, channel, compare) TIMER_CompareSet(timer_instance, channel, compare) +#define sleeptimer_hal_timer_get_interrupt(timer_instance) TIMER_IntGet(timer_instance) +#define sleeptimer_hal_timer_set_interrupt(timer_instance, flags) TIMER_IntSet(timer_instance, flags) +#define sleeptimer_hal_timer_enable_interrupt(timer_instance, flags) TIMER_IntEnable(timer_instance, flags) +#define sleeptimer_hal_timer_disable_interrupt(timer_instance, flags) TIMER_IntDisable(timer_instance, flags) +#define sleeptimer_hal_timer_clear_interrupt(timer_instance, flags) TIMER_IntClear(timer_instance, flags) +#else +#define sleeptimer_hal_timer_get_counter(timer_instance) sl_hal_timer_get_counter(timer_instance) +#define sleeptimer_hal_timer_get_compare(timer_instance, channel) sl_hal_timer_channel_get_compare(timer_instance, channel) +#define sleeptimer_hal_timer_set_compare(timer_instance, channel, compare) sl_hal_timer_channel_set_compare(timer_instance, channel, compare) +#define sleeptimer_hal_timer_get_interrupt(timer_instance) sl_hal_timer_get_pending_interrupts(timer_instance) +#define sleeptimer_hal_timer_set_interrupt(timer_instance, flags) sl_hal_timer_set_interrupts(timer_instance, flags) +#define sleeptimer_hal_timer_enable_interrupt(timer_instance, flags) sl_hal_timer_enable_interrupts(timer_instance, flags) +#define sleeptimer_hal_timer_disable_interrupt(timer_instance, flags) sl_hal_timer_disable_interrupts(timer_instance, flags) +#define sleeptimer_hal_timer_clear_interrupt(timer_instance, flags) sl_hal_timer_clear_interrupts(timer_instance, flags) +#endif + +static bool comp_int_disabled = true; + +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes TIMER sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + sl_clock_manager_enable_bus_clock(SLEEPTIMER_TIMER_CLK); + +#if defined(_SILICON_LABS_32B_SERIES_2) + TIMER_Init_TypeDef init_config = TIMER_INIT_DEFAULT; + TIMER_InitCC_TypeDef init_config_cc = TIMER_INITCC_DEFAULT; + init_config_cc.mode = timerCCModeCompare; + init_config.prescale = timerPrescale1024; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + init_config.debugRun = true; +#endif + + TIMER_InitCC(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); + TIMER_TopSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); + + TIMER_Init(SLEEPTIMER_TIMER_INSTANCE, &init_config); +#if defined(TIMER_STATUS_SYNCBUSY) + TIMER_SyncWait(SLEEPTIMER_TIMER_INSTANCE); +#endif + + TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + + TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); + +#elif defined(_SILICON_LABS_32B_SERIES_3) + sl_hal_timer_config_t init_config = SL_HAL_TIMER_CONFIG_DEFAULT; + sl_hal_timer_channel_config_t init_config_cc = SL_HAL_TIMER_CHANNEL_CONFIG_DEFAULT; + init_config_cc.channel_mode = SL_HAL_TIMER_CHANNEL_MODE_COMPARE; + init_config.prescaler = SL_HAL_TIMER_PRESCALER_DIV1024; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + init_config.debugRun = true; +#endif + + sl_hal_timer_channel_init(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); + sl_hal_timer_init(SLEEPTIMER_TIMER_INSTANCE, &init_config); + sl_hal_timer_disable_interrupts(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + sl_hal_timer_clear_interrupts(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + sl_hal_timer_enable(SLEEPTIMER_TIMER_INSTANCE); + sl_hal_timer_wait_sync(SLEEPTIMER_TIMER_INSTANCE); + sl_hal_timer_set_top(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); + sl_hal_timer_channel_set_compare(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); + sl_hal_timer_start(SLEEPTIMER_TIMER_INSTANCE); +#endif + + sl_interrupt_manager_clear_irq_pending(SLEEPTIMER_TIMER_IRQ); + sl_interrupt_manager_enable_irq(SLEEPTIMER_TIMER_IRQ); +} + +/****************************************************************************** + * Gets TIMER counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return sleeptimer_hal_timer_get_counter(SLEEPTIMER_TIMER_INSTANCE); +} + +/****************************************************************************** + * Gets TIMER compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return sleeptimer_hal_timer_get_compare(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL); +} + +/****************************************************************************** + * Sets TIMER compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the TIMER compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((sleeptimer_hal_timer_get_interrupt(SLEEPTIMER_TIMER_INSTANCE) & SLEEPTIMER_TIMER_IEN_COMPARE) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + sleeptimer_hal_timer_set_compare(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, compare_value - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + comp_int_disabled = false; + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t timer_ien = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_ien |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + if (comp_int_disabled == true) { + sleeptimer_hal_timer_clear_interrupt(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + comp_int_disabled = false; + } + timer_ien |= SLEEPTIMER_TIMER_IEN_COMPARE; + } + + sleeptimer_hal_timer_enable_interrupt(SLEEPTIMER_TIMER_INSTANCE, timer_ien); +} + +/****************************************************************************** + * Disables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t timer_int_dis = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_int_dis |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + timer_int_dis |= SLEEPTIMER_TIMER_IEN_COMPARE; + + comp_int_disabled = true; + } + + sleeptimer_hal_timer_disable_interrupt(SLEEPTIMER_TIMER_INSTANCE, timer_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sleeptimer_hal_timer_set_interrupt(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = sleeptimer_hal_timer_get_interrupt(SLEEPTIMER_TIMER_INSTANCE); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) == SLEEPTIMER_TIMER_IEN_COMPARE); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & TIMER_IEN_OF) == TIMER_IEN_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * TIMER interrupt handler. + ******************************************************************************/ +void SLEEPTIMER_TIMER_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = sleeptimer_hal_timer_get_interrupt(SLEEPTIMER_TIMER_INSTANCE); + + if (irq_flag & TIMER_IEN_OF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + + if (irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + sleeptimer_hal_timer_clear_interrupt(SLEEPTIMER_TIMER_INSTANCE, irq_flag & (TIMER_IEN_OF | SLEEPTIMER_TIMER_IEN_COMPARE)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets TIMER timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + // Returns source frequency divided by max prescaler value 1024. + uint32_t freq; + sl_clock_branch_t clock_branch; + + clock_branch = sl_device_peripheral_get_clock_branch(SLEEPTIMER_PERIPHERAL_TIMER); + sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq); + return (freq >> 10UL); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + uint16_t precision; + sl_clock_manager_get_clock_branch_precision(SL_CLOCK_BRANCH_EM01GRPACLK, &precision); + return precision; +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @return Capture value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note Lowest possible energy mode for TIMER peripheral is EM1. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +} +#endif +#endif diff --git a/Libs/platform/service/sleeptimer/src/sli_sleeptimer_hal.h b/Libs/platform/service/sleeptimer/src/sli_sleeptimer_hal.h new file mode 100644 index 0000000..42682ed --- /dev/null +++ b/Libs/platform/service/sleeptimer/src/sli_sleeptimer_hal.h @@ -0,0 +1,189 @@ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction layer definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_HAL_H +#define SL_SLEEPTIMER_HAL_H + +#include +#include +#include +#include "em_device.h" +#include "sli_sleeptimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer of the sleep timer init. + ******************************************************************************/ +void sleeptimer_hal_init_timer(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the current timer count. + * + * @return Value in ticks of the timer counter. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sleeptimer_hal_get_counter(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get a timer comparator value. + * + * @return Value in ticks of the timer comparator. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sleeptimer_hal_get_compare(void); + +/******************************************************************************* + * Hardware Abstraction Layer to set a timer comparator value. + * + * @param value Number of ticks to set. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_set_compare(uint32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to set a comparator value to trigger a + * peripheral request signal to initialize. + * + * @param value Number of ticks to set. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to get the timer frequency. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sleeptimer_hal_get_timer_frequency(void); + +/******************************************************************************* + * Hardware Abstraction Layer to enable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_enable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to disable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_disable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_set_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to get the sleeptimer's clock accuracy. + * + * @return Clock accuracy in PPM. + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @note Not supported by all peripherals Sleeptimer can use. + * + * @return Capture value. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t sleeptimer_hal_get_capture(void); + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_reset_prs_signal(void); + +/******************************************************************************* + * Hardware Abstraction Layer to disable PRS compare and capture channel. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void sleeptimer_hal_disable_prs_compare_and_capture_channel(void); + +/******************************************************************************* + * Process the timer interrupt. + * + * @param flags Internal interrupt flag. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +void process_timer_irq(uint8_t local_flag); + +/***************************************************************************//** + * @brief + * Convert prescaler divider to a logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] presc + * Prescaler value used to set the frequency divider. The divider is equal to + * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be + * equal to (divider - 1). + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t sleeptimer_hal_presc_to_log2(uint32_t presc) +{ + uint32_t log2; + + // Integer prescalers take argument less than 32768. + EFM_ASSERT(presc < 32768U); + + // Count leading zeroes and "reverse" result. Consider divider value to get + // exponent n from 2^n, so ('presc' +1). + log2 = 31UL - __CLZ(presc + (uint32_t) 1); + + // Check that prescaler is a 2^n number. + EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); + + return log2; +} + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SLEEPTIMER_HAL_H */ diff --git a/Libs/platform/service/system/inc/sl_system_init.h b/Libs/platform/service/system/inc/sl_system_init.h new file mode 100644 index 0000000..9bdd8ea --- /dev/null +++ b/Libs/platform/service/system/inc/sl_system_init.h @@ -0,0 +1,153 @@ +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_INIT_H +#define SL_SYSTEM_INIT_H + +/***************************************************************************//** + * @addtogroup system System Initialization and Action Processing + * @brief System Initialization and Action Processing + * @details + * ### System Init + * System Init provides a function for initializing the system and the products: + * + * - sl_system_init(). + * + * This function calls a set of functions that are automatically generated + * and located in `autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_init -> sl_platform_init() + * - driver_init -> sl_driver_init() + * - service_init -> sl_service_init() + * - stack_init -> sl_stack_init() + * - internal_app_init -> sl_internal_app_init() + * + * These events are fired in the order listed above when `sl_system_init()` + * is called. + * + * ### System Kernel + * + * System Kernel component provides a function for starting the kernel: + * + * - sl_system_kernel_start(). + * + * This function calls a functions that is automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - kernel_start -> sl_kernel_start() + * + * The event is fired when `sl_system_kernel_start()` is called. + * + * ### System Process Action + * + * System Process Action component provides a function for running + * the products from a super loop: + * + * - sl_system_process_action(). + * + * This function calls a set of functions that are automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_process_action -> sl_platform_process_action() + * - service_process_action -> sl_service_process_action() + * - stack_process_action -> sl_stack_process_action() + * - internal_app_process_action -> sl_internal_process_action() + * + * These events are fired in the order listed above when `sl_system_process_action()` + * is called. + * + * Usage example: + * + * @code{.c} + * #if defined(SL_COMPONENT_CATALOG_PRESENT) + * #include "sl_component_catalog.h" + * #endif + * #include "sl_system_init.h" + * #include "sl_power_manager.h" + * #include "app.h" + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * #include "sl_system_kernel.h" + * #else + * #include "sl_system_process_action.h" + * #endif + * + * int main(void) + * { + * // Initialize Silicon Labs device, system, service(s) and protocol stack(s). + * // Note that if the kernel is present, processing task(s) will be created by + * // this call. + * sl_system_init(); + * + * // Initialize the application. + * app_init(); + * + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * // Start the kernel. Task(s) created in app_init() will start running. + * sl_system_kernel_start(); + * #else + * do { + * // Do not remove this call: Silicon Labs components process action routine + * // must be called from the super loop. + * sl_system_process_action(); + * + * // Application process. + * app_process_action(); + * + * // Let the CPU go to sleep if the system allow it. + * sl_power_manager_sleep(); + * } while (1); + * #endif // SL_CATALOG_KERNEL_PRESENT + * } + * @endcode + * @{ + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize Silicon Labs products + */ +void sl_system_init(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_INIT_H diff --git a/Libs/platform/service/system/inc/sl_system_kernel.h b/Libs/platform/service/system/inc/sl_system_kernel.h new file mode 100644 index 0000000..38a0932 --- /dev/null +++ b/Libs/platform/service/system/inc/sl_system_kernel.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief System Kernel Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_KERNEL_H +#define SL_SYSTEM_KERNEL_H + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Start the kernel + */ +void sl_system_kernel_start(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_KERNEL_H diff --git a/Libs/platform/service/system/src/sl_system_init.c b/Libs/platform/service/system/src/sl_system_init.c new file mode 100644 index 0000000..9e4988f --- /dev/null +++ b/Libs/platform/service/system/src/sl_system_init.c @@ -0,0 +1,39 @@ +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_init(void) +{ + sl_platform_init(); + sl_driver_init(); + sl_service_init(); + sl_stack_init(); + sl_internal_app_init(); +} diff --git a/Libs/platform/service/system/src/sl_system_kernel.c b/Libs/platform/service/system/src/sl_system_kernel.c new file mode 100644 index 0000000..749802d --- /dev/null +++ b/Libs/platform/service/system/src/sl_system_kernel.c @@ -0,0 +1,35 @@ +/***************************************************************************//** + * @file + * @brief System Kernel Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_kernel_start(void) +{ + sl_kernel_start(); +} diff --git a/Libs/platform/service/udelay/inc/sl_udelay.h b/Libs/platform/service/udelay/inc/sl_udelay.h new file mode 100644 index 0000000..e26a356 --- /dev/null +++ b/Libs/platform/service/udelay/inc/sl_udelay.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef UDELAY_H +#define UDELAY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup udelay Microsecond Delay + * @brief Microsecond delay function + * @{ + ******************************************************************************/ + +/** + * @brief + * Delay a number of microseconds + * + * @details + * This function will use a busy loop to delay code execution by a certain + * number of microseconds before returning to the caller. This function will + * not return to the caller earlier than the time given as the input parameter. + * This function will not use any hardware timing peripherals, it is using + * the core clock frequency to calculate the delay. + * + * Note that there will always be some overhead associated with calling this + * function in addition to the internal delay loop. This overhead is relatively + * small when the delay is large (>= 100us). + * + * The accuracy of this delay loop will be affected by interrupts and context + * switching. If accuracy is needed, a hardware timer should be used + * to handle delays. + * + * @param[in] us + * This is the number of microseconds to delay execution. This function will + * return after this amount of time has elapsed. Minimum value is 0 us and + * maximum value is 100 000 us (100 ms). It is however recommended to use + * the sleeptimer api for delays of more than 1 ms as it is using a hardware + * counter and will result in better accuracy. + */ +void sl_udelay_wait(unsigned us); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup udelay) */ + +#endif diff --git a/Libs/platform/service/udelay/src/sl_udelay.c b/Libs/platform/service/udelay/src/sl_udelay.c new file mode 100644 index 0000000..aa2931e --- /dev/null +++ b/Libs/platform/service/udelay/src/sl_udelay.c @@ -0,0 +1,69 @@ +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_udelay.h" +#include "em_device.h" +#include "sl_assert.h" +#include + +/* The Cortex-M33 has a faster execution of the hw loop + * with the same arm instructions. */ +#if defined(__CORTEX_M) && (__CORTEX_M == 33U) + #define HW_LOOP_CYCLE 3 +#else + #define HW_LOOP_CYCLE 4 +#endif + +void sli_delay_loop(unsigned n); + +void sl_udelay_wait(unsigned us) +{ + uint32_t freq_khz; + uint32_t ns_period; + uint32_t cycles; + uint32_t loops; + + freq_khz = SystemCoreClockGet() / 1000U; + if (freq_khz == 0) { + EFM_ASSERT(false); + return; + } + + ns_period = 1000000U / freq_khz; + if (ns_period == 0) { + EFM_ASSERT(false); + return; + } + + cycles = us * 1000U / ns_period; + loops = cycles / HW_LOOP_CYCLE; + if (loops > 0U) { + sli_delay_loop(loops); + } +} diff --git a/Libs/platform/service/udelay/src/sl_udelay_armv6m_gcc.S b/Libs/platform/service/udelay/src/sl_udelay_armv6m_gcc.S new file mode 100644 index 0000000..bb16feb --- /dev/null +++ b/Libs/platform/service/udelay/src/sl_udelay_armv6m_gcc.S @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func + .global sli_delay_loop + +/* + * @brief + * Hardware delay loop + * + * @detail + * This is the hardware specific delay loop. It is designed specifically to + * execute in 4 or 3 cycles for each iteration depending on the architecture. + * Using this information the caller can use the core clock frequency to + * calculate the number of loops required in order to delay a specific time + * period. + * + * @param[in] n (r0) + * n is the number of loops to execute. Each loop will execute in 4 cycles. + * Note that we assume that r0 > 0, so this invariant should be checked by + * the caller. + */ +sli_delay_loop: + subs r0, r0, #1 + beq done + b.n sli_delay_loop +done: + bx lr + + .end diff --git a/Output/Debug/Obj/Firmware/Firmware_files.ind b/Output/Debug/Obj/Firmware/Firmware_files.ind new file mode 100644 index 0000000..52883ca --- /dev/null +++ b/Output/Debug/Obj/Firmware/Firmware_files.ind @@ -0,0 +1,103 @@ +"Output/Debug/Obj/Firmware/sl_event_handler.o" +"Output/Debug/Obj/Firmware/system_efr32mg24.o" +"Output/Debug/Obj/Firmware/os_systick.o" +"Output/Debug/Obj/Firmware/cmsis_os2.o" +"Output/Debug/Obj/Firmware/croutine.o" +"Output/Debug/Obj/Firmware/event_groups.o" +"Output/Debug/Obj/Firmware/list.o" +"Output/Debug/Obj/Firmware/port.o" +"Output/Debug/Obj/Firmware/portasm.o" +"Output/Debug/Obj/Firmware/heap_3.o" +"Output/Debug/Obj/Firmware/tick_power_manager.o" +"Output/Debug/Obj/Firmware/queue.o" +"Output/Debug/Obj/Firmware/stream_buffer.o" +"Output/Debug/Obj/Firmware/tasks.o" +"Output/Debug/Obj/Firmware/timers.o" +"Output/Debug/Obj/Firmware/sl_assert.o" +"Output/Debug/Obj/Firmware/sl_cmsis_os2_common.o" +"Output/Debug/Obj/Firmware/sl_core_cortexm.o" +"Output/Debug/Obj/Firmware/sl_slist.o" +"Output/Debug/Obj/Firmware/sl_syscalls.o" +"Output/Debug/Obj/Firmware/sli_cmsis_os2_ext_task_register.o" +"Output/Debug/Obj/Firmware/sl_button.o" +"Output/Debug/Obj/Firmware/sl_simple_button.o" +"Output/Debug/Obj/Firmware/sl_gpio.o" +"Output/Debug/Obj/Firmware/sl_led.o" +"Output/Debug/Obj/Firmware/sl_simple_led.o" +"Output/Debug/Obj/Firmware/em_acmp.o" +"Output/Debug/Obj/Firmware/em_burtc.o" +"Output/Debug/Obj/Firmware/em_cmu.o" +"Output/Debug/Obj/Firmware/em_core.o" +"Output/Debug/Obj/Firmware/em_dbg.o" +"Output/Debug/Obj/Firmware/em_emu.o" +"Output/Debug/Obj/Firmware/em_eusart.o" +"Output/Debug/Obj/Firmware/em_gpcrc.o" +"Output/Debug/Obj/Firmware/em_gpio.o" +"Output/Debug/Obj/Firmware/em_i2c.o" +"Output/Debug/Obj/Firmware/em_iadc.o" +"Output/Debug/Obj/Firmware/em_ldma.o" +"Output/Debug/Obj/Firmware/em_letimer.o" +"Output/Debug/Obj/Firmware/em_msc.o" +"Output/Debug/Obj/Firmware/em_opamp.o" +"Output/Debug/Obj/Firmware/em_pcnt.o" +"Output/Debug/Obj/Firmware/em_prs.o" +"Output/Debug/Obj/Firmware/em_rmu.o" +"Output/Debug/Obj/Firmware/em_system.o" +"Output/Debug/Obj/Firmware/em_timer.o" +"Output/Debug/Obj/Firmware/em_usart.o" +"Output/Debug/Obj/Firmware/em_vdac.o" +"Output/Debug/Obj/Firmware/em_wdog.o" +"Output/Debug/Obj/Firmware/sl_hal_gpio.o" +"Output/Debug/Obj/Firmware/sl_hal_sysrtc.o" +"Output/Debug/Obj/Firmware/sl_hal_system.o" +"Output/Debug/Obj/Firmware/sl_clock_manager.o" +"Output/Debug/Obj/Firmware/sl_clock_manager_hal_s2.o" +"Output/Debug/Obj/Firmware/sl_clock_manager_init.o" +"Output/Debug/Obj/Firmware/sl_clock_manager_init_hal_s2.o" +"Output/Debug/Obj/Firmware/sl_device_init_dcdc_s2.o" +"Output/Debug/Obj/Firmware/sl_device_clock_efr32xg24.o" +"Output/Debug/Obj/Firmware/sl_device_peripheral_hal_efr32xg24.o" +"Output/Debug/Obj/Firmware/sl_device_clock.o" +"Output/Debug/Obj/Firmware/sl_device_gpio.o" +"Output/Debug/Obj/Firmware/sl_device_peripheral.o" +"Output/Debug/Obj/Firmware/sl_hfxo_manager.o" +"Output/Debug/Obj/Firmware/sl_hfxo_manager_hal_s2.o" +"Output/Debug/Obj/Firmware/sl_interrupt_manager_cortexm.o" +"Output/Debug/Obj/Firmware/sl_iostream.o" +"Output/Debug/Obj/Firmware/sl_iostream_rtt.o" +"Output/Debug/Obj/Firmware/sli_memory_profiler_stubs.o" +"Output/Debug/Obj/Firmware/sl_memory_manager.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_cpp.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_dynamic_reservation.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_pool.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_pool_common.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_region.o" +"Output/Debug/Obj/Firmware/sl_memory_manager_retarget.o" +"Output/Debug/Obj/Firmware/sli_memory_manager_common.o" +"Output/Debug/Obj/Firmware/sl_mpu.o" +"Output/Debug/Obj/Firmware/sl_power_manager_common.o" +"Output/Debug/Obj/Firmware/sl_power_manager_em4.o" +"Output/Debug/Obj/Firmware/sl_power_manager.o" +"Output/Debug/Obj/Firmware/sl_power_manager_debug.o" +"Output/Debug/Obj/Firmware/sl_power_manager_hal_s2.o" +"Output/Debug/Obj/Firmware/sl_sleeptimer.o" +"Output/Debug/Obj/Firmware/sl_sleeptimer_hal_burtc.o" +"Output/Debug/Obj/Firmware/sl_sleeptimer_hal_sysrtc.o" +"Output/Debug/Obj/Firmware/sl_sleeptimer_hal_timer.o" +"Output/Debug/Obj/Firmware/sl_system_init.o" +"Output/Debug/Obj/Firmware/sl_system_kernel.o" +"Output/Debug/Obj/Firmware/sl_udelay.o" +"Output/Debug/Obj/Firmware/sl_udelay_armv6m_gcc.o" +"Output/Debug/Obj/Firmware/main.o" +"Output/Debug/Obj/Firmware/EFR32MG24_Startup.o" +"Output/Debug/Obj/Firmware/efr32mg24_Vectors.o" +"Output/Debug/Obj/Firmware/SEGGER_THUMB_Startup.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/libcxx_noexcept_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/libc_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/SEGGER_crtinit_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/prinops_rtt_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/heapops_basic_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/heapops_disable_interrupts_locking_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/strops_unaligned_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/mbops_timeops_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio 8.22a/lib/libcxxabi_noexcept_v8mml_fpv5_sp_d16_hard_t_le_eabi_balanced.a" diff --git a/Output/Debug/Obj/Firmware/em_emu-df97bff7.o.tmp b/Output/Debug/Obj/Firmware/em_emu-df97bff7.o.tmp new file mode 100644 index 0000000..e69de29 diff --git a/Output/Debug/Obj/Firmware/sl_syscalls-637c085d.o.tmp b/Output/Debug/Obj/Firmware/sl_syscalls-637c085d.o.tmp new file mode 100644 index 0000000..e69de29 diff --git a/Output/Debug/Obj/Firmware/timers-d0bfcf77.o.tmp b/Output/Debug/Obj/Firmware/timers-d0bfcf77.o.tmp new file mode 100644 index 0000000..e69de29 diff --git a/SEGGER_THUMB_Startup.s b/SEGGER_THUMB_Startup.s new file mode 100644 index 0000000..62c2496 --- /dev/null +++ b/SEGGER_THUMB_Startup.s @@ -0,0 +1,288 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2024 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_THUMB_Startup.s +Purpose : Generic runtime init startup code for ARM CPUs running + in THUMB mode. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + + .syntax unified + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .thumb_func + .code 16 +\Name: +.endm +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .weak \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + ldr R4, =__SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + ldr R0, [R4] // Get next initialization function from table + adds R4, R4, #4 // Increment table pointer to point to function arguments + blx R0 // Call initialization function + b L(RunInit) + // +MARK_FUNC __SEGGER_init_done +MARK_FUNC __startup_complete + // + // Time to call main(), the application entry point. + // +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init R0 and R1. + // + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + b . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load R0 and R1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + movs R0, #ARGSSPACE + ldr R1, =__SEGGER_init_arg_data + bl SEGGER_SEMIHOST_GetArgs + ldr R1, =__SEGGER_init_arg_data + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + bl exit // Call exit function + b . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mov R5, R0 // Save the exit parameter/return result + // + // Call destructors + // + ldr R0, =__dtors_start__ // Pointer to destructor list + ldr R1, =__dtors_end__ +L(Loop): + cmp R0, R1 + beq L(End) // Reached end of destructor list? => Done + ldr R2, [R0] // Load current destructor address into R2 + adds R0, R0, #4 // Increment pointer + push {R0-R1} // Save R0 and R1 + blx R2 // Call destructor + pop {R0-R1} // Restore R0 and R1 + b L(Loop) +L(End): + // + // Call atexit functions + // + bl __SEGGER_RTL_execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mov R0, R5 + // + // Entry points for _exit and _Exit, which terminate immediately. + // Note: Destructors and registered atexit functions are not called. File descriptors are not closed. + // +MARK_FUNC _exit +MARK_FUNC _Exit + bl SEGGER_SEMIHOST_Exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + b L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss + .balign 4 +__SEGGER_init_arg_data: + .space ARGSSPACE + .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data + .type __SEGGER_init_arg_data, %object +#endif + +/*************************** End of file ****************************/ diff --git a/autogen/RTE_Components.h b/autogen/RTE_Components.h new file mode 100644 index 0000000..6531f56 --- /dev/null +++ b/autogen/RTE_Components.h @@ -0,0 +1,34 @@ +// This file is autogenerated by Simplicity Configuration Tools. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + +#define RTE_RTOS_FreeRTOS_CORE + +#define RTE_RTOS_FreeRTOS_CONFIG_RTOS2 + +#define RTE_RTOS_FreeRTOS_COROUTINE + +#define RTE_RTOS_FreeRTOS_EVENTGROUPS + +#define RTE_RTOS_FreeRTOS_TIMERS + +#define RTE_RTOS_FreeRTOS_HEAP_3 + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Simplicity Configuration Tools. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/autogen/sl_component_catalog.h b/autogen/sl_component_catalog.h new file mode 100644 index 0000000..b16ee31 --- /dev/null +++ b/autogen/sl_component_catalog.h @@ -0,0 +1,94 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_MATTER_ACCESS_CONTROL_PRESENT +#define SL_CATALOG_MATTER_ADMINISTRATOR_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_BASIC_INFORMATION_PRESENT +#define SL_CATALOG_MATTER_BINDINGS_PRESENT +#define SL_CATALOG_MATTER_BLE_PRESENT +#define SL_CATALOG_MATTER_BRIDGED_DEVICE_BASIC_INFORMATION_PRESENT +#define SL_CATALOG_MATTER_DESCRIPTOR_PRESENT +#define SL_CATALOG_MATTER_DIAGNOSTIC_LOGS_PRESENT +#define SL_CATALOG_MATTER_ETHERNET_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_FIXED_LABEL_PRESENT +#define SL_CATALOG_GATT_CONFIGURATION_PRESENT +#define SL_CATALOG_MATTER_GENERAL_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_GENERAL_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_GROUP_KEY_MGMT_PRESENT +#define SL_CATALOG_MATTER_GROUPS_PRESENT +#define SL_CATALOG_MATTER_IDENTIFY_PRESENT +#define SL_CATALOG_MATTER_LEVEL_CONTROL_PRESENT +#define SL_CATALOG_MATTER_LOCALIZATION_CONFIGURATION_PRESENT +#define SL_CATALOG_MATTER_NETWORK_COMMISSIONING_PRESENT +#define SL_CATALOG_MATTER_ON_OFF_PRESENT +#define SL_CATALOG_MATTER_OPERATIONAL_CREDENTIALS_PRESENT +#define SL_CATALOG_MATTER_OTA_REQUESTOR_PRESENT +#define SL_CATALOG_MATTER_SCENES_PRESENT +#define SL_CATALOG_MATTER_SOFTWARE_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_SWITCH_PRESENT +#define SL_CATALOG_MATTER_THREAD_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_MATTER_TIME_FORMAT_LOCALIZATION_PRESENT +#define SL_CATALOG_MATTER_USER_LABEL_PRESENT +#define SL_CATALOG_MATTER_WIFI_NETWORK_DIAGNOSTICS_PRESENT +#define SL_CATALOG_BLUETOOTH_CONFIGURATION_PRESENT +#define SL_CATALOG_BLUETOOTH_CTE_SUPPORT_PRESENT +#define SL_CATALOG_BLUETOOTH_CS_SUPPORT_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_GATT_SERVER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_SYSTEM_PRESENT +#define SL_CATALOG_BLUETOOTH_HOST_ADAPTATION_PRESENT +#define SL_CATALOG_BLUETOOTH_RTOS_ADAPTATION_PRESENT +#define SL_CATALOG_BLUETOOTH_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT +#define SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT +#define SL_CATALOG_CLOCK_MANAGER_PRESENT +#define SL_CATALOG_CMSIS_OS_COMMON_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT +#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT +#define SL_CATALOG_EMLIB_CORE_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_EMLIB_RMU_PRESENT +#define SL_CATALOG_FREERTOS_KERNEL_PRESENT +#define SL_CATALOG_KERNEL_PRESENT +#define SL_CATALOG_GPIO_PRESENT +#define SL_CATALOG_GPIOINTERRUPT_PRESENT +#define SL_CATALOG_HFXO_MANAGER_PRESENT +#define SL_CATALOG_INTERRUPT_MANAGER_PRESENT +#define SL_CATALOG_IOSTREAM_PRESENT +#define SL_CATALOG_MEMORY_MANAGER_PRESENT +#define SL_CATALOG_MEMORY_PROFILER_API_PRESENT +#define SL_CATALOG_MPU_PRESENT +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT +#define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_OPENTHREAD_CLI_PRESENT +#define SL_CATALOG_OT_GP_INTERFACE_PRESENT +#define SL_CATALOG_OPENTHREAD_STACK_PRESENT +#define SL_CATALOG_POWER_MANAGER_PRESENT +#define SL_CATALOG_PSA_CRYPTO_PRESENT +#define SL_CATALOG_RADIO_PRIORITY_15_4_PRESENT +#define SL_CATALOG_RAIL_LIB_PRESENT +#define SL_CATALOG_RAIL_UTIL_PTI_PRESENT +#define SL_CATALOG_SE_MANAGER_PRESENT +#define SL_CATALOG_SECURITY_MANAGER_PRESENT +#define SL_CATALOG_BTN0_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN0_PRESENT +#define SL_CATALOG_BTN1_PRESENT +#define SL_CATALOG_SIMPLE_BUTTON_BTN1_PRESENT +#define SL_CATALOG_LED0_PRESENT +#define SL_CATALOG_SIMPLE_LED_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT +#define SL_CATALOG_LED1_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED1_PRESENT +#define SL_CATALOG_LED2_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED2_PRESENT +#define SL_CATALOG_SL_CORE_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT +#define SL_CATALOG_UARTDRV_EUSART_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/autogen/sl_event_handler.c b/autogen/sl_event_handler.c new file mode 100644 index 0000000..08079df --- /dev/null +++ b/autogen/sl_event_handler.c @@ -0,0 +1,104 @@ +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_interrupt_manager.h" +//#include "sl_board_init.h" +#include "sl_clock_manager_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_clock_manager.h" +#include "sl_hfxo_manager.h" +//#include "pa_conversions_efr32.h" +//#include "sl_rail_util_power_manager_init.h" +//#include "sl_rail_util_pti.h" +//#include "sl_rail_util_rssi.h" +//#include "btl_interface.h" +//#include "sl_board_control.h" +//#include "sl_bt_rtos_adaptation.h" +//#include "platform-efr32.h" +#include "sl_sleeptimer.h" +#include "sl_mpu.h" +#include "sl_gpio.h" +//#include "gpiointerrupt.h" +//#include "sl_iostream_rtt.h" +//#include "sl_mbedtls.h" +//#include "sl_ot_rtos_adaptation.h" +//#include "sl_simple_button_instances.h" +//#include "sl_simple_led_instances.h" +//#include "sl_uartdrv_instances.h" +//#include "psa/crypto.h" +//#include "sl_se_manager.h" +//#include "sli_protocol_crypto.h" +#include "cmsis_os2.h" +//#include "sl_iostream_init_instances.h" +//#include "sl_bluetooth.h" +//#include "nvm3_default.h" +//#include "sl_iostream_handles.h" +#include "sl_power_manager.h" + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_interrupt_manager_init(); + //sl_board_preinit(); + sl_clock_manager_init(); + sl_device_init_dcdc(); + sl_clock_manager_runtime_init(); + sl_hfxo_manager_init_hardware(); + //sl_board_init(); + //bootloader_init(); + osKernelInitialize(); + //nvm3_initDefault(); + sl_power_manager_init(); +} + +void sl_kernel_start(void) +{ + //sli_bt_rtos_adaptation_kernel_start(); + osKernelStart(); +} + +void sl_driver_init(void) +{ + //sl_gpio_init(); + //GPIOINT_Init(); + //sl_simple_button_init_instances(); + //sl_simple_led_init_instances(); + //sl_uartdrv_init_instances(); +} + +void sl_service_init(void) +{ + //sl_board_configure_vcom(); + //sl_sleeptimer_init(); + //sl_hfxo_manager_init(); + //sl_mpu_disable_execute_from_ram(); + //sl_mbedtls_init(); + //psa_crypto_init(); + //sl_se_init(); + //sli_protocol_crypto_init(); + //sli_aes_seed_mask(); + sl_iostream_init_instances(); +} + +void sl_stack_init(void) +{ + //sl_rail_util_pa_init(); + //sl_rail_util_power_manager_init(); + //sl_rail_util_pti_init(); + //sl_rail_util_rssi_init(); + //sl_bt_rtos_init(); + //sl_ot_sys_init(); +} + +void sl_internal_app_init(void) +{ + //sl_ot_rtos_stack_init(); + //sl_ot_rtos_app_init(); +} + +void sl_iostream_init_instances(void) +{ + //sl_iostream_rtt_init(); + //sl_iostream_set_console_instance(); +} + diff --git a/autogen/sl_event_handler.h b/autogen/sl_event_handler.h new file mode 100644 index 0000000..ef8751b --- /dev/null +++ b/autogen/sl_event_handler.h @@ -0,0 +1,12 @@ +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_kernel_start(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_iostream_init_instances(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/config/FreeRTOSConfig.h b/config/FreeRTOSConfig.h new file mode 100644 index 0000000..748f823 --- /dev/null +++ b/config/FreeRTOSConfig.h @@ -0,0 +1,336 @@ +/* + * + * Copyright (c) 2020 Project CHIP Authors + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*************************************************************************** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#ifdef SLI_SI91X_MCU_INTERFACE +#include "si91x_device.h" +extern uint32_t SystemCoreClock; +#if SL_ICD_ENABLED +#include "sl_si91x_m4_ps.h" +#endif // SL_ICD_ENABLED +#else // For EFR32 +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "em_device.h" +//#include "sl_assert.h" +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#ifdef SL_CATALOG_SYSTEMVIEW_TRACE_PRESENT +#include "SEGGER_SYSVIEW_FreeRTOS.h" +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* Energy saving modes. */ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#define configUSE_TICKLESS_IDLE 1 +#elif (SLI_SI91X_MCU_INTERFACE && SL_ICD_ENABLED) +#define configUSE_TICKLESS_IDLE 1 +#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 70 +#define configPRE_SLEEP_PROCESSING(x) +#define configPOST_SLEEP_PROCESSING(x) +#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) +#else +#define configUSE_TICKLESS_IDLE 0 +#endif // SL_CATALOG_POWER_MANAGER_PRESENT + +#define configTICK_RATE_HZ (1024) + +/* Definition used by Keil to replace default system clock source. */ +#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1 + +/* Hook function related definitions. */ +#define configUSE_TICK_HOOK (1) +#define configCHECK_FOR_STACK_OVERFLOW (2) +#define configUSE_MALLOC_FAILED_HOOK (1) +#define configUSE_IDLE_HOOK (1) + +/* Main functions*/ +/* Run time stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS (0) + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES (0) +#define configMAX_CO_ROUTINE_PRIORITIES (1) + +/* Software timer related definitions. */ +#define configUSE_TIMERS (1) +// Keep the timerTask at the highest prio as some of our stacks tasks leverage eventing with timers. +#define configTIMER_TASK_PRIORITY (55) /* Highest priority */ +#define configTIMER_QUEUE_LENGTH (10) +#define configTIMER_TASK_STACK_DEPTH (1024) + +#ifdef SLI_SI91X_MCU_INTERFACE +#ifdef __NVIC_PRIO_BITS +#undef __NVIC_PRIO_BITS +#endif +#define configPRIO_BITS 6 /* 6 priority levels. */ +#endif // SLI_SI91X_MCU_INTERFACE + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (255) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#ifdef SLI_SI91X_MCU_INTERFACE +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 20 +#else +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 48 +#endif // SLI_SI91X_MCU_INTERFACE + +#define configENABLE_FPU 1 +#define configENABLE_MPU 0 +/* FreeRTOS Secure Side Only and TrustZone Security Extension */ +#ifndef configRUN_FREERTOS_SECURE_ONLY +// prevent redefinition with Series 3 +#define configRUN_FREERTOS_SECURE_ONLY 1 +#endif +#define configENABLE_TRUSTZONE 0 +/* FreeRTOS MPU specific definitions. */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS (0) + +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configUSE_PREEMPTION (1) +#define configUSE_TIME_SLICING (1) +#define configUSE_PORT_OPTIMISED_TASK_SELECTION (0) +#define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG (1) /* See into vPortSuppressTicksAndSleep source code for explanation */ +#define configMAX_PRIORITIES (56) +#define configMINIMAL_STACK_SIZE (320) /* Number of words to use for Idle and Timer stacks */ + +#ifdef HEAP_MONITORING +#define configMAX_TASK_NAME_LEN (24) +#else +#define configMAX_TASK_NAME_LEN (10) +#endif // HEAP_MONITORING + +#define configUSE_16_BIT_TICKS (0) +#define configIDLE_SHOULD_YIELD (1) +#define configUSE_MUTEXES (1) +#define configUSE_RECURSIVE_MUTEXES (1) +#define configUSE_COUNTING_SEMAPHORES (1) +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 +#define configQUEUE_REGISTRY_SIZE (10) +#define configUSE_QUEUE_SETS (0) +#define configUSE_NEWLIB_REENTRANT (0) +#define configENABLE_BACKWARD_COMPATIBILITY (1) +#define configSUPPORT_STATIC_ALLOCATION (1) +#define configSUPPORT_DYNAMIC_ALLOCATION (1) + +#ifdef PW_RPC_ENABLED +#define EXTRA_HEAP_k 10 +#else +#define EXTRA_HEAP_k 0 +#endif + +#ifndef configTOTAL_HEAP_SIZE +#ifdef SL_WIFI +#ifdef DIC_ENABLE +#ifdef SLI_SI91X_MCU_INTERFACE +#define configTOTAL_HEAP_SIZE ((size_t) ((75 + EXTRA_HEAP_k) * 1024)) +#else +#define configTOTAL_HEAP_SIZE ((size_t) ((68 + EXTRA_HEAP_k) * 1024)) +#endif // SLI_SI91X_MCU_INTERFACE +#else +#define configTOTAL_HEAP_SIZE ((size_t) ((42 + EXTRA_HEAP_k) * 1024)) +#endif // DIC +#else // SL_WIFI +#if SL_CONFIG_OPENTHREAD_LIB == 1 +#define configTOTAL_HEAP_SIZE ((size_t) ((40 + EXTRA_HEAP_k) * 1024)) +#else +#define configTOTAL_HEAP_SIZE ((size_t) ((38 + EXTRA_HEAP_k) * 1024)) +#endif // SL_CONFIG_OPENTHREAD_LIB +#endif // configTOTAL_HEAP_SIZE +#endif // configTOTAL_HEAP_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet (1) +#define INCLUDE_uxTaskPriorityGet (1) +#define INCLUDE_vTaskDelete (1) +#define INCLUDE_vTaskSuspend (1) +#define INCLUDE_xResumeFromISR (1) +#define INCLUDE_vTaskDelayUntil (1) +#define INCLUDE_vTaskDelay (1) +#define INCLUDE_xTaskGetSchedulerState (1) +#define INCLUDE_xTaskGetCurrentTaskHandle (1) +#define INCLUDE_uxTaskGetStackHighWaterMark (1) +#define INCLUDE_xTaskGetIdleTaskHandle (1) +#define INCLUDE_xTimerGetTimerDaemonTaskHandle (1) +#define INCLUDE_pcTaskGetTaskName (1) +#define INCLUDE_eTaskGetState (1) +#define INCLUDE_xEventGroupSetBitFromISR (1) +#define INCLUDE_xEventGroupSetBitsFromISR (1) +#define INCLUDE_xSemaphoreGetMutexHolder (1) +#define INCLUDE_xTimerPendFunctionCall (1) +#define INCLUDE_xTaskGetHandle (1) + +/* Stop if an assertion fails. */ +#define configASSERT(x) \ + if ((x) == 0) \ + { \ + taskDISABLE_INTERRUPTS(); \ + printf("\nFREERTOS ASSERT ( %s )\n", #x); \ + for (;;) \ + ; \ + } +#define configASSERTNULL(x) \ + if ((x) == NULL) \ + { \ + taskDISABLE_INTERRUPTS(); \ + for (;;) \ + ; \ + } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +/* Ensure Cortex-M port compatibility. */ +#define SysTick_Handler xPortSysTickHandler + +/* Thread local storage pointers used by the SDK */ + +#ifndef configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS +#define configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS +#define configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS 2 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS \ + (configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS + configNUM_SDK_THREAD_LOCAL_STORAGE_POINTERS + 1) +#endif + +#if defined(__GNUC__) +/* For the linker. */ +#define fabs __builtin_fabs +#endif + +#ifndef configNUM_USER_THREAD_LOCAL_STORAGE_POINTERS +#error RC-FRTOS +#endif + +#ifdef __cplusplus +} +#endif diff --git a/config/emlib_core_debug_config.h b/config/emlib_core_debug_config.h new file mode 100644 index 0000000..07ee9b9 --- /dev/null +++ b/config/emlib_core_debug_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/config/sl_clock_manager_oscillator_config.h b/config/sl_clock_manager_oscillator_config.h new file mode 100644 index 0000000..6a5ef1d --- /dev/null +++ b/config/sl_clock_manager_oscillator_config.h @@ -0,0 +1,376 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Oscillators configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Oscillators Settings + +// HFXO Settings (if High Frequency crystal is used) + +// Enable +// Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO +#ifndef SL_CLOCK_MANAGER_HFXO_EN +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#endif + +// Mode +// +// XTAL +// EXTCLK +// EXTCLKPKDET +// HFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_HFXO_MODE +#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL +#endif + +// Frequency in Hz <38000000-40000000> +// 39000000 +#ifndef SL_CLOCK_MANAGER_HFXO_FREQ +#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 +#endif + +// CTUNE <0-255> +// 140 +#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE +#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 +#endif + +// Precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION +#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 +#endif + +// CTUNE HXFO manufacturing +// Enable to use CTUNE HFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1 +#endif + +// HFXO crystal sharing feature +// Enable to configure HFXO crystal sharing leader or follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 +#endif + +// Crystal sharing leader +// Enable to configure HFXO crystal sharing leader +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 +#endif + +// Crystal sharing leader minimum startup delay +// If enabled, BUFOUT does not start until timeout set in +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. +// This prevents waste of power if BUFOUT is ready too early. +// 1 +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 +#endif + +// Wait duration of oscillator startup sequence +// +// T42US +// T83US +// T108US +// T133US +// T158US +// T183US +// T208US +// T233US +// T258US +// T283US +// T333US +// T375US +// T417US +// T458US +// T500US +// T667US +// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US +#endif +// +// + +// Crystal sharing follower +// Enable to configure HFXO crystal sharing follower +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 +#endif +// + +// GPIO Port +// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this port will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 +#endif + +// GPIO Pin +// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN +// is enabled, this pin will be used to receive the BUFOUT request. If +// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin +// will be used to request BUFOUT from the crystal sharing leader. +#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN +#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 +#endif +// +// + +// LFXO Settings (if Low Frequency crystal is used) +// Enable to configure LFXO +#ifndef SL_CLOCK_MANAGER_LFXO_EN +#define SL_CLOCK_MANAGER_LFXO_EN 1 +#endif + +// Mode +// +// XTAL +// BUFEXTCLK +// DIGEXTCLK +// LFXO_CFG_MODE_XTAL +#ifndef SL_CLOCK_MANAGER_LFXO_MODE +#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL +#endif + +// CTUNE <0-127> +// 63 +#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE +#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 +#endif + +// LFXO precision in PPM <0-65535> +// 50 +#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION +#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 +#endif + +// Startup Timeout Delay +// +// CYCLES2 +// CYCLES256 +// CYCLES1K +// CYCLES2K +// CYCLES4K +// CYCLES8K +// CYCLES16K +// CYCLES32K +// LFXO_CFG_TIMEOUT_CYCLES4K +#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT +#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K +#endif + +// CTUNE LXFO manufacturing +// Enable to use CTUNE LFXO manufacturing value for calibration +// 1 +#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN +#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1 +#endif +// + +// HFRCO and DPLL Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 80 MHz +// cmuHFRCODPLLFreq_80M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCO_BAND +#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz +#endif + +// Use DPLL +// Enable to use the DPLL with HFRCO +#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN +#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 +#endif + +// Target Frequency in Hz <1000000-80000000> +// DPLL target frequency +// 78000000 +#ifndef SL_CLOCK_MANAGER_DPLL_FREQ +#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 +#endif + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// 3839 +#ifndef SL_CLOCK_MANAGER_DPLL_N +#define SL_CLOCK_MANAGER_DPLL_N 3839 +#endif + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// 1919 +#ifndef SL_CLOCK_MANAGER_DPLL_M +#define SL_CLOCK_MANAGER_DPLL_M 1919 +#endif + +// Reference Clock +// Reference clock source for DPLL +// DISABLED +// HFXO +// LFXO +// CLKIN0 +// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK +#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO +#endif + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// cmuDPLLEdgeSel_Fall +#ifndef SL_CLOCK_MANAGER_DPLL_EDGE +#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall +#endif + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// cmuDPLLLockMode_Freq +#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE +#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase +#endif + +// Automatic Lock Recovery +// 1 +#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER +#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 +#endif + +// Enable Dither +// 0 +#ifndef SL_CLOCK_MANAGER_DPLL_DITHER +#define SL_CLOCK_MANAGER_DPLL_DITHER 0 +#endif +// +// + +// HFRCOEM23 Settings +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 40 MHz +// cmuHFRCOEM23Freq_19M0Hz +#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND +#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz +#endif +// + +// LFRCO Settings +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// cmuPrecisionDefault +#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION +#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +#endif +// + +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/config/sl_clock_manager_tree_config.h b/config/sl_clock_manager_tree_config.h new file mode 100644 index 0000000..3f4794f --- /dev/null +++ b/config/sl_clock_manager_tree_config.h @@ -0,0 +1,308 @@ +/***************************************************************************//** + * @file + * @brief Clock Manager - Clock Tree configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H +#define SL_CLOCK_MANAGER_TREE_CONFIG_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE +// selection of each clock branch to the right HW register value. +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Clock Tree Settings + +// Default Clock Source Selection for HF clock branches +// AUTO +// HFRCODPLL +// HFXO +// FSRCO +// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO +#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#endif + +// Default Clock Source Selection for LF clock branches +// LFRCO +// LFXO +// ULFRCO +// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO +#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO +#endif + +// System Clock Branch Settings + +// Clock Source Selection for SYSCLK branch +// DEFAULT_HF +// FSRCO +// HFRCODPLL +// HFXO +// CLKIN0 +// Selection of the Clock source for SYSCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// HCLK branch divider +// DIV1 +// DIV2 +// DIV4 +// DIV8 +// DIV16 +// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. +// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER +#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 +#endif + +// PCLK branch divider +// DIV1 +// DIV2 +// PCLK branch is derived from HCLK. This clock drives the APB bus interface. +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 +#endif + +// + +// Trace Clock Branches Settings +// Clock Source Selection for TRACECLK branch +// DISABLE +// SYSCLK +// HFRCOEM23 +// HFRCODPLLRT +// Selection of the Clock source for TRACECLK +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK +#endif + +// TRACECLK branch Divider +// DIV1 +// DIV2 +// DIV3 +// DIV4 +// Selection of the divider value for TRACECLK branch +// CMU_TRACECLKCTRL_PRESC_DIV1 +#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER +#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 +#endif + +// + +// High Frequency Clock Branches Settings +// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible +// EM01GRPACLK clock the Timer peripherals +// Clock Source Selection for EM01GRPACLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM01GRPCCLK branch +// DEFAULT_HF +// HFRCODPLL +// HFXO +// FSRCO +// HFRCOEM23 +// HFRCODPLLRT +// HFXORT +// Selection of the Clock source for EM01GRPCCLK +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE +#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE +#endif + +// Clock Source Selection for IADCCLK branch +// EM01GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for IADCCLK +// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE +#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// + +// Low Frequency Clock Branches Settings + +// Clock Source Selection for EM23GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM23GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for EM4GRPACLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for EM4GRPACLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE +#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for SYSRTCCLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// Selection of the Clock source for SYSRTCCLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG0CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG0CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for WDOG1CLK branch +// DEFAULT_LF +// LFRCO +// LFXO +// ULFRCO +// HCLKDIV1024 +// Selection of the Clock source for WDOG1CLK +// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE +#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE +#endif + +// Clock Source Selection for PCNT0CLK branch +// DISABLED +// EM23GRPACLK +// PCNTS0 +// Selection of the Clock source for PCNT0CLK +// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE +#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK +#endif + +// + +// Mixed Frequency Clock Branch Settings +// Clock Source Selection for EUSART0CLK branch +// DISABLED +// EM01GRPCCLK +// HFRCOEM23 +// LFRCO +// LFXO +// Selection of the Clock source for EUSART0CLK +// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE +#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK +#endif + +// Clock Source Selection for SYSTICKCLK branch +// <0=> HCLK +// <1=> EM23GRPACLK +// Selection of the Clock source for SYSTICKCLK +// 0 +#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE +#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 +#endif + +// Clock Source Selection for VDAC0CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC0CLK +// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + +// +// + +#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/config/sl_core_config.h b/config/sl_core_config.h new file mode 100644 index 0000000..27b173d --- /dev/null +++ b/config/sl_core_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief sl_core Configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_CORE_CONFIG_H +#define SL_CORE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Abstraction Configuration + +// Enables measurement of interrupt masking time for debugging purposes. +// Default: 0 +#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0 +// + +// <<< end of configuration section >>> +#endif // SL_CORE_CONFIG_H diff --git a/config/sl_device_init_dcdc_config.h b/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000..4fb8839 --- /dev/null +++ b/config/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 12 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/config/sl_hfxo_manager_config.h b/config/sl_hfxo_manager_config.h new file mode 100644 index 0000000..d9ccd3c --- /dev/null +++ b/config/sl_hfxo_manager_config.h @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file + * @brief HFXO Manager configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_HFXO_MANAGER_CONFIG_H +#define SL_HFXO_MANAGER_CONFIG_H + +// HFXO Manager Configuration + +// Enable custom IRQ handler for crystal HF oscillator. +// Enable if HFXO0_IRQHandler is needed from your application. +// The HFXO IRQ priority must not be changed as the HFXO Manager module needs it to be high priority +// and to stay enabled through atomic sections. +// The function sl_hfxo_manager_irq_handler() will have to be called from you custom handler if this is enabled. +// Default: 0 +#define SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER 0 + +// Enable support for Sleepy Crystals. +// If Enabled and if HFXO fails to startup due to a sleepy crystal, HFXO Manager will retry the startup with more aggressive settings +// before falling back to the configured settings. +// Default: 0 +#define SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT 0 + +// + +#endif /* SL_HFXO_MANAGER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/config/sl_interrupt_manager_s2_config.h b/config/sl_interrupt_manager_s2_config.h new file mode 100644 index 0000000..714893a --- /dev/null +++ b/config/sl_interrupt_manager_s2_config.h @@ -0,0 +1,47 @@ +/***************************************************************************//** + * @file + * @brief Interrupt Manager configuration file for series 2 devices. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_INTERRUPT_MANAGER_S2_CONFIG_H +#define SL_INTERRUPT_MANAGER_S2_CONFIG_H + +// Interrupt Manager Configuration + +// Put the interrupt vector table in RAM. +// Set to 1 to put the vector table in RAM. +// Default: 0 +#define SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM 0 + +// + +#endif /* SSL_INTERRUPT_MANAGER_S2_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/config/sl_memory_manager_config.h b/config/sl_memory_manager_config.h new file mode 100644 index 0000000..7e4b056 --- /dev/null +++ b/config/sl_memory_manager_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap Allocator configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_CONFIG_H +#define SL_MEMORY_MANAGER_CONFIG_H + +// Memory Manager Configuration + +// Minimum block allocation size +// <32-128:8> +// Minimum block allocation size to avoid creating a block too small while splitting up an allocated block. +// Size expressed in bytes and can only be a multiple of 8 bytes for the proper data alignment management done by the dynamic allocator malloc() function. +// Default: 32 +#define SL_MEMORY_MANAGER_BLOCK_ALLOCATION_MIN_SIZE (32) + +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_CONFIG_H */ diff --git a/config/sl_memory_manager_region_config.h b/config/sl_memory_manager_region_config.h new file mode 100644 index 0000000..f34bb11 --- /dev/null +++ b/config/sl_memory_manager_region_config.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Memory Heap and stack size configuration file. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_MEMORY_MANAGER_REGION_CONFIG_H +#define SL_MEMORY_MANAGER_REGION_CONFIG_H + +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE +#define SL_STACK_SIZE 4608 +#endif +// + +// <<< end of configuration section >>> + +#endif /* SL_MEMORY_MANAGER_REGION_CONFIG_H */ diff --git a/config/sl_power_manager_config.h b/config/sl_power_manager_config.h new file mode 100644 index 0000000..42f59d7 --- /dev/null +++ b/config/sl_power_manager_config.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file + * @brief Power Manager configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_POWER_MANAGER_CONFIG_H +#define SL_POWER_MANAGER_CONFIG_H + +// Power Manager Configuration + +// Enable custom IRQ handler for external HF oscillator. +// Enable if CMU_IRQHandler/HFXO0_IRQHandler is needed from your application. +// The function sl_power_manager_irq_handler() will have to be called from you custom handler if this is enabled. +// Default: 0 +#define SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER 0 + +// Enable fast wakeup (disable voltage scaling in EM2/3 mode) +// Enable or disable voltage scaling in EM2/3 modes (when available). This decreases wakeup time by about 30 us. +// Deprecated. It is replaced by the function sl_power_manager_em23_voltage_scaling_enable_fast_wakeup() +// Default: 0 +#define SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP 0 + +// Enable debugging feature +// Enable or disable debugging features (trace the different modules that have requirements). +// Default: 0 +#define SL_POWER_MANAGER_DEBUG 0 + +// Maximum numbers of requirements that can be logged +// Default: 10 +#define SL_POWER_MANAGER_DEBUG_POOL_SIZE 10 +// + +// Pin retention mode +// +// No retention +// Retention through EM4 +// Retention through EM4 and wakeup +// power_manager_pin_retention_disable +#define SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE EMU_EM4CTRL_EM4IORETMODE_DISABLE + +// Enable EM2 debugging feature +// Enable or disable debugging features. +// Default: 1 +#define SL_POWER_MANAGER_INIT_EMU_EM2_DEBUG_ENABLE 1 +// + +// + +#endif /* SL_POWER_MANAGER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/config/sl_simple_button_config.h b/config/sl_simple_button_config.h new file mode 100644 index 0000000..531f4f2 --- /dev/null +++ b/config/sl_simple_button_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver Configuration + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_CONFIG_H +#define SL_SIMPLE_BUTTON_CONFIG_H + +#include "sl_gpio.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple Button Driver Configuration + +// Number of bits <1-15> +// Default: 5 +// Defines the number of calls to sl_simple_button_poll_step wherein the button +// state must remain the same before the button state is considered debounced +#define SL_SIMPLE_BUTTON_DEBOUNCE_BITS 5U + +// +// GPIO Input +// GPIO Input Pull +// GPIO Input Pull Filter +// Default: gpioModeInput +#define SL_SIMPLE_BUTTON_GPIO_MODE SL_GPIO_MODE_INPUT + +// +// SL_SIMPLE_BUTTON_GPIO_MODE == SL_GPIO_MODE_INPUT, Filter if DOUT is set +// SL_SIMPLE_BUTTON_GPIO_MODE == SL_GPIO_MODE_INPUT_PULL, DOUT determines pull direction +#define SL_SIMPLE_BUTTON_GPIO_DOUT 0U + +// +// 0 Active Low +// 1 Active High +// Default: 0 +#define SL_SIMPLE_BUTTON_POLARITY 0U + +// Allow the app to manage Buttons and LEDs on the same pin +// 0 Error if Buttons and LEDs are on the same pin +// 1 Do not error if Buttons and LEDs are on the same pin +// Default: 0 +#define SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT 0U + +// + +// <<< end of configuration section >>> +#endif // SL_SIMPLE_BUTTON_CONFIG_H diff --git a/config/sl_sleeptimer_config.h b/config/sl_sleeptimer_config.h new file mode 100644 index 0000000..8344ef5 --- /dev/null +++ b/config/sl_sleeptimer_config.h @@ -0,0 +1,82 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 +#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 +#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// WTIMER +// TIMER +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) +// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. +// Default: 0 +#define SL_SLEEPTIMER_TIMER_INSTANCE 0 + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider (not applicable for WTIMER/TIMER) +// WTIMER/TIMER peripherals are always prescaled to 1024. +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/main.c b/main.c new file mode 100644 index 0000000..2e3a8c4 --- /dev/null +++ b/main.c @@ -0,0 +1,65 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : main.c +Purpose : Generic application start + +*/ + +#include +#include "FreeRTOS.h" +#include "task.h" +#include "sl_system_init.h" + +static void exampleTask( void * parameters ) +{ + /* Unused parameters. */ + ( void ) parameters; + uint8_t i = 0; + for( ; ; ) + { + printf( "hello world %d\n",i++ ); + /* Example Task Code */ + vTaskDelay( 100 ); /* delay 100 ticks */ + } +} + +/********************************************************************* +* +* main() +* +* Function description +* Application entry point. +*/ + +int main(void) { + static StaticTask_t exampleTaskTCB; + static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ]; + + printf( "Example FreeRTOS Project\n" ); + + sl_system_init(); + + /* create tasks */ + xTaskCreateStatic( exampleTask, + "example", + configMINIMAL_STACK_SIZE, + NULL, + configMAX_PRIORITIES - 1U, + &( exampleTaskStack[ 0 ] ), + &( exampleTaskTCB ) ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + for( ; ; ) + { + /* Should not reach here. */ + } +} + +/*************************** End of file ****************************/